drivers/video/tegra/dc/hdmi.c

   1 /*
   2  * drivers/video/tegra/dc/hdmi.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Erik Gilling <konkers@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/fb.h>
  22 #include <linux/gpio.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/switch.h>
  28 #include <linux/workqueue.h>
  29
  30 #include <mach/clk.h>
  31 #include <mach/dc.h>
  32 #include <mach/fb.h>
  33 #include <mach/nvhost.h>
  34
  35 #include "dc_reg.h"
  36 #include "dc_priv.h"
  37 #include "hdmi_reg.h"
  38 #include "hdmi.h"
  39 #include "edid.h"
  40
  41 /* datasheet claims this will always be 216MHz */
  42 #define HDMI_AUDIOCLK_FREQ              216000000
  43
  44 #define HDMI_REKEY_DEFAULT              56
  45
  46 struct tegra_dc_hdmi_data {
  47         struct tegra_dc                 *dc;
  48         struct tegra_edid               *edid;
  49         struct delayed_work             work;
  50
  51         struct resource                 *base_res;
  52         void __iomem                    *base;
  53         struct clk                      *clk;
  54
  55         struct clk                      *disp1_clk;
  56         struct clk                      *disp2_clk;
  57
  58         struct switch_dev               hpd_switch;
  59
  60         spinlock_t                      suspend_lock;
  61         bool                            suspended;
  62         bool                            hpd_pending;
  63
  64         bool                            dvi;
  65 };
  66
  67 const struct fb_videomode tegra_dc_hdmi_supported_modes[] = {
  68         /* 1280x720p 60hz: EIA/CEA-861-B Format 4 */
  69         {
  70                 .xres =         1280,
  71                 .yres =         720,
  72                 .pixclock =     KHZ2PICOS(74250),
  73                 .hsync_len =    40,     /* h_sync_width */
  74                 .vsync_len =    5,      /* v_sync_width */
  75                 .left_margin =  220,    /* h_back_porch */
  76                 .upper_margin = 20,     /* v_back_porch */
  77                 .right_margin = 110,    /* h_front_porch */
  78                 .lower_margin = 5,      /* v_front_porch */
  79                 .vmode =        FB_VMODE_NONINTERLACED,
  80                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  81         },
  82
  83         /* 720x480p 59.94hz: EIA/CEA-861-B Formats 2 & 3 */
  84         {
  85                 .xres =         720,
  86                 .yres =         480,
  87                 .pixclock =     KHZ2PICOS(27000),
  88                 .hsync_len =    62,     /* h_sync_width */
  89                 .vsync_len =    6,      /* v_sync_width */
  90                 .left_margin =  60,     /* h_back_porch */
  91                 .upper_margin = 30,     /* v_back_porch */
  92                 .right_margin = 16,     /* h_front_porch */
  93                 .lower_margin = 9,      /* v_front_porch */
  94                 .vmode =        FB_VMODE_NONINTERLACED,
  95                 .sync = 0,
  96         },
  97
  98         /* 640x480p 60hz: EIA/CEA-861-B Format 1 */
  99         {
 100                 .xres =         640,
 101                 .yres =         480,
 102                 .pixclock =     KHZ2PICOS(25200),
 103                 .hsync_len =    96,     /* h_sync_width */
 104                 .vsync_len =    2,      /* v_sync_width */
 105                 .left_margin =  48,     /* h_back_porch */
 106                 .upper_margin = 33,     /* v_back_porch */
 107                 .right_margin = 16,     /* h_front_porch */
 108                 .lower_margin = 10,     /* v_front_porch */
 109                 .vmode =        FB_VMODE_NONINTERLACED,
 110                 .sync = 0,
 111         },
 112
 113         /* 720x576p 50hz EIA/CEA-861-B Formats 17 & 18 */
 114         {
 115                 .xres =         720,
 116                 .yres =         576,
 117                 .pixclock =     KHZ2PICOS(27000),
 118                 .hsync_len =    64,     /* h_sync_width */
 119                 .vsync_len =    5,      /* v_sync_width */
 120                 .left_margin =  68,     /* h_back_porch */
 121                 .upper_margin = 39,     /* v_back_porch */
 122                 .right_margin = 12,     /* h_front_porch */
 123                 .lower_margin = 5,      /* v_front_porch */
 124                 .vmode =        FB_VMODE_NONINTERLACED,
 125                 .sync = 0,
 126         },
 127
 128         /* 1920x1080p 59.94/60hz EIA/CEA-861-B Format 16 */
 129         {
 130                 .xres =         1920,
 131                 .yres =         1080,
 132                 .pixclock =     KHZ2PICOS(148500),
 133                 .hsync_len =    44,     /* h_sync_width */
 134                 .vsync_len =    5,      /* v_sync_width */
 135                 .left_margin =  148,    /* h_back_porch */
 136                 .upper_margin = 36,     /* v_back_porch */
 137                 .right_margin = 88,     /* h_front_porch */
 138                 .lower_margin = 4,      /* v_front_porch */
 139                 .vmode =        FB_VMODE_NONINTERLACED,
 140                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 141         },
 142 };
 143
 144 struct tegra_hdmi_audio_config {
 145         unsigned pix_clock;
 146         unsigned n;
 147         unsigned cts;
 148 };
 149
 150 const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
 151         {25200000,      4096,   25250},
 152         {27000000,      4096,   27000},
 153         {54000000,      4096,   54000},
 154         {74250000,      4096,   74250},
 155         {148500000,     4096,   148500},
 156         {0,             0,      0},
 157 };
 158
 159 const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
 160         {25200000,      14112,  63125},
 161         {27000000,      6272,   30000},
 162         {54000000,      6272,   60000},
 163         {74250000,      6272,   82500},
 164         {148500000,     6272,   165000},
 165         {0,             0,      0},
 166 };
 167
 168 const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
 169         {25200000,      6144,   25250},
 170         {27000000,      6144,   27000},
 171         {54000000,      6144,   54000},
 172         {74250000,      6144,   74250},
 173         {148500000,     6144,   148500},
 174         {0,             0,      0},
 175 };
 176
 177 static const struct tegra_hdmi_audio_config
 178 *tegra_hdmi_get_audio_config(unsigned audio_freq, unsigned pix_clock)
 179 {
 180         const struct tegra_hdmi_audio_config *table;
 181
 182         switch (audio_freq) {
 183         case 32000:
 184                 table = tegra_hdmi_audio_32k;
 185                 break;
 186
 187         case 44100:
 188                 table = tegra_hdmi_audio_44_1k;
 189                 break;
 190
 191         case 48000:
 192                 table = tegra_hdmi_audio_48k;
 193                 break;
 194
 195         default:
 196                 return NULL;
 197         }
 198
 199         while (table->pix_clock) {
 200                 if (table->pix_clock == pix_clock)
 201                         return table;
 202                 table++;
 203         }
 204
 205         return NULL;
 206 }
 207
 208
 209 static inline unsigned long tegra_hdmi_readl(struct tegra_dc_hdmi_data *hdmi,
 210                                              unsigned long reg)
 211 {
 212         return readl(hdmi->base + reg * 4);
 213 }
 214
 215 static inline void tegra_hdmi_writel(struct tegra_dc_hdmi_data *hdmi,
 216                                      unsigned long val, unsigned long reg)
 217 {
 218         writel(val, hdmi->base + reg * 4);
 219 }
 220
 221 static inline void tegra_hdmi_clrsetbits(struct tegra_dc_hdmi_data *hdmi,
 222                                          unsigned long reg, unsigned long clr,
 223                                          unsigned long set)
 224 {
 225         unsigned long val = tegra_hdmi_readl(hdmi, reg);
 226         val &= ~clr;
 227         val |= set;
 228         tegra_hdmi_writel(hdmi, val, reg);
 229 }
 230
 231 #define DUMP_REG(a) do {                                                \
 232                 printk("HDMI %-32s\t%03x\t%08lx\n",                     \
 233                        #a, a, tegra_hdmi_readl(hdmi, a));               \
 234         } while (0)
 235
 236 #ifdef DEBUG
 237 static void hdmi_dumpregs(struct tegra_dc_hdmi_data *hdmi)
 238 {
 239         DUMP_REG(HDMI_CTXSW);
 240         DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
 241         DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
 242         DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
 243         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
 244         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
 245         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
 246         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
 247         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
 248         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
 249         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
 250         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
 251         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
 252         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
 253         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
 254         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
 255         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
 256         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
 257         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
 258         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
 259         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
 260         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
 261         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
 262         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
 263         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
 264         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
 265         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
 266         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
 267         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
 268         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
 269         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 270         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
 271         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
 272         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
 273         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
 274         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 275         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
 276         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
 277         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
 278         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
 279         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
 280         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
 281         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 282         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
 283         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
 284         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
 285         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
 286         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
 287         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
 288         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
 289         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
 290         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
 291         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
 292         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
 293         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
 294         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
 295         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 296         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 297         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
 298         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
 299         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
 300         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
 301         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
 302         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
 303         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
 304         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
 305         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
 306         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
 307         DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
 308         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
 309         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
 310         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
 311         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
 312         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
 313         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
 314         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
 315         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
 316         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
 317         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
 318         DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
 319         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
 320         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
 321         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_CTRL);
 322         DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
 323         DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
 324         DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
 325         DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
 326         DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
 327         DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
 328         DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
 329         DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
 330         DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
 331         DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
 332         DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
 333         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
 334         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST0);
 335         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST1);
 336         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST2);
 337         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST3);
 338         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST4);
 339         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST5);
 340         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST6);
 341         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST7);
 342         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST8);
 343         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST9);
 344         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTA);
 345         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTB);
 346         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTC);
 347         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTD);
 348         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTE);
 349         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTF);
 350         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
 351         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
 352         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
 353         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
 354         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
 355         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
 356         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
 357         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
 358         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
 359         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
 360         DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
 361         DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
 362         DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
 363         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
 364         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
 365         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
 366         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
 367         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
 368         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
 369         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
 370         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
 371         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
 372         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
 373         DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
 374         DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
 375         DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
 376         DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
 377         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
 378         DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
 379         DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
 380         DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
 381         DUMP_REG(HDMI_NV_PDISP_SCRATCH);
 382         DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
 383         DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
 384         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
 385         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
 386         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
 387         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
 388         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
 389         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
 390         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
 391         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
 392         DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
 393 }
 394 #endif
 395
 396 #define PIXCLOCK_TOLERANCE      200
 397
 398 static bool tegra_dc_hdmi_mode_equal(const struct fb_videomode *mode1,
 399                                         const struct fb_videomode *mode2)
 400 {
 401         return mode1->xres      == mode2->xres &&
 402                 mode1->yres     == mode2->yres &&
 403                 mode1->vmode    == mode2->vmode;
 404 }
 405
 406 static bool tegra_dc_hdmi_mode_filter(struct fb_videomode *mode)
 407 {
 408         int i;
 409         int clocks;
 410
 411         for (i = 0; i < ARRAY_SIZE(tegra_dc_hdmi_supported_modes); i++) {
 412                 if (tegra_dc_hdmi_mode_equal(&tegra_dc_hdmi_supported_modes[i],
 413                                              mode)) {
 414                         memcpy(mode, &tegra_dc_hdmi_supported_modes[i], sizeof(*mode));
 415                         mode->flag = FB_MODE_IS_DETAILED;
 416                         clocks = (mode->left_margin + mode->xres + mode->right_margin + mode->hsync_len) *
 417                                 (mode->upper_margin + mode->yres + mode->lower_margin + mode->vsync_len);
 418                         mode->refresh = (PICOS2KHZ(mode->pixclock) * 1000) / clocks;
 419                         return true;
 420                 }
 421         }
 422
 423         return false;
 424 }
 425
 426
 427 static bool tegra_dc_hdmi_hpd(struct tegra_dc *dc)
 428 {
 429         int sense;
 430         int level;
 431
 432         level = gpio_get_value(dc->out->hotplug_gpio);
 433
 434         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
 435
 436         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
 437                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
 438 }
 439
 440 static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
 441 {
 442         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 443         struct fb_monspecs specs;
 444         int err;
 445
 446         if (!tegra_dc_hdmi_hpd(dc))
 447                 goto fail;
 448
 449         err = tegra_edid_get_monspecs(hdmi->edid, &specs);
 450         if (err < 0) {
 451                 dev_err(&dc->ndev->dev, "error reading edid\n");
 452                 goto fail;
 453         }
 454
 455         /* monitors like to lie about these but they are still useful for
 456          * detecting aspect ratios
 457          */
 458         dc->out->h_size = specs.max_x * 1000;
 459         dc->out->v_size = specs.max_y * 1000;
 460
 461
 462         hdmi->dvi = !(specs.misc & FB_MISC_HDMI);
 463
 464         tegra_fb_update_monspecs(dc->fb, &specs, tegra_dc_hdmi_mode_filter);
 465         switch_set_state(&hdmi->hpd_switch, 1);
 466         dev_info(&dc->ndev->dev, "display detected\n");
 467         return true;
 468
 469 fail:
 470         switch_set_state(&hdmi->hpd_switch, 0);
 471         return false;
 472 }
 473
 474
 475 static void tegra_dc_hdmi_detect_worker(struct work_struct *work)
 476 {
 477         struct tegra_dc_hdmi_data *hdmi =
 478                 container_of(to_delayed_work(work), struct tegra_dc_hdmi_data, work);
 479         struct tegra_dc *dc = hdmi->dc;
 480
 481         if (!tegra_dc_hdmi_detect(dc)) {
 482                 tegra_dc_disable(dc);
 483                 tegra_fb_update_monspecs(dc->fb, NULL, NULL);
 484         }
 485 }
 486
 487 static irqreturn_t tegra_dc_hdmi_irq(int irq, void *ptr)
 488 {
 489         struct tegra_dc *dc = ptr;
 490         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 491         unsigned long flags;
 492
 493         spin_lock_irqsave(&hdmi->suspend_lock, flags);
 494         if (hdmi->suspended) {
 495                 hdmi->hpd_pending = true;
 496         } else {
 497                 if (tegra_dc_hdmi_hpd(dc))
 498                         schedule_delayed_work(&hdmi->work, msecs_to_jiffies(100));
 499                 else
 500                         schedule_delayed_work(&hdmi->work, msecs_to_jiffies(0));
 501         }
 502         spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
 503
 504         return IRQ_HANDLED;
 505 }
 506
 507 static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
 508 {
 509         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 510         unsigned long flags;
 511
 512         spin_lock_irqsave(&hdmi->suspend_lock, flags);
 513         hdmi->suspended = true;
 514         spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
 515 }
 516
 517 static void tegra_dc_hdmi_resume(struct tegra_dc *dc)
 518 {
 519         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 520         unsigned long flags;
 521
 522         spin_lock_irqsave(&hdmi->suspend_lock, flags);
 523         hdmi->suspended = false;
 524         if (hdmi->hpd_pending) {
 525                 if (tegra_dc_hdmi_hpd(dc))
 526                         schedule_delayed_work(&hdmi->work, msecs_to_jiffies(100));
 527                 else
 528                         schedule_delayed_work(&hdmi->work, msecs_to_jiffies(0));
 529                 hdmi->hpd_pending = false;
 530         }
 531         spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
 532 }
 533
 534 static int tegra_dc_hdmi_init(struct tegra_dc *dc)
 535 {
 536         struct tegra_dc_hdmi_data *hdmi;
 537         struct resource *res;
 538         struct resource *base_res;
 539         void __iomem *base;
 540         struct clk *clk = NULL;
 541         struct clk *disp1_clk = NULL;
 542         struct clk *disp2_clk = NULL;
 543         int err;
 544
 545         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
 546         if (!hdmi)
 547                 return -ENOMEM;
 548
 549         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM, "hdmi_regs");
 550         if (!res) {
 551                 dev_err(&dc->ndev->dev, "hdmi: no mem resource\n");
 552                 err = -ENOENT;
 553                 goto err_free_hdmi;
 554         }
 555
 556         base_res = request_mem_region(res->start, resource_size(res), dc->ndev->name);
 557         if (!base_res) {
 558                 dev_err(&dc->ndev->dev, "hdmi: request_mem_region failed\n");
 559                 err = -EBUSY;
 560                 goto err_free_hdmi;
 561         }
 562
 563         base = ioremap(res->start, resource_size(res));
 564         if (!base) {
 565                 dev_err(&dc->ndev->dev, "hdmi: registers can't be mapped\n");
 566                 err = -EBUSY;
 567                 goto err_release_resource_reg;
 568         }
 569
 570         clk = clk_get(&dc->ndev->dev, "hdmi");
 571         if (IS_ERR_OR_NULL(clk)) {
 572                 dev_err(&dc->ndev->dev, "hdmi: can't get clock\n");
 573                 err = -ENOENT;
 574                 goto err_iounmap_reg;
 575         }
 576
 577         disp1_clk = clk_get_sys("tegradc.0", NULL);
 578         if (IS_ERR_OR_NULL(disp1_clk)) {
 579                 dev_err(&dc->ndev->dev, "hdmi: can't disp1 clock\n");
 580                 err = -ENOENT;
 581                 goto err_put_clock;
 582         }
 583
 584         disp2_clk = clk_get_sys("tegradc.1", NULL);
 585         if (IS_ERR_OR_NULL(disp2_clk)) {
 586                 dev_err(&dc->ndev->dev, "hdmi: can't disp2 clock\n");
 587                 err = -ENOENT;
 588                 goto err_put_clock;
 589         }
 590
 591         /* TODO: support non-hotplug */
 592         if (request_irq(gpio_to_irq(dc->out->hotplug_gpio), tegra_dc_hdmi_irq,
 593                         IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
 594                         dev_name(&dc->ndev->dev), dc)) {
 595                 dev_err(&dc->ndev->dev, "hdmi: request_irq %d failed\n",
 596                         gpio_to_irq(dc->out->hotplug_gpio));
 597                 err = -EBUSY;
 598                 goto err_put_clock;
 599         }
 600
 601         hdmi->edid = tegra_edid_create(dc->out->dcc_bus);
 602         if (IS_ERR_OR_NULL(hdmi->edid)) {
 603                 dev_err(&dc->ndev->dev, "hdmi: can't create edid\n");
 604                 err = PTR_ERR(hdmi->edid);
 605                 goto err_free_irq;
 606         }
 607
 608         INIT_DELAYED_WORK(&hdmi->work, tegra_dc_hdmi_detect_worker);
 609
 610         hdmi->dc = dc;
 611         hdmi->base = base;
 612         hdmi->base_res = base_res;
 613         hdmi->clk = clk;
 614         hdmi->disp1_clk = disp1_clk;
 615         hdmi->disp2_clk = disp2_clk;
 616         hdmi->suspended = false;
 617         hdmi->hpd_pending = false;
 618         spin_lock_init(&hdmi->suspend_lock);
 619
 620         hdmi->hpd_switch.name = "hdmi";
 621         switch_dev_register(&hdmi->hpd_switch);
 622
 623         dc->out->depth = 24;
 624
 625         tegra_dc_set_outdata(dc, hdmi);
 626
 627         return 0;
 628
 629 err_free_irq:
 630         free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
 631 err_put_clock:
 632         if (!IS_ERR_OR_NULL(disp2_clk))
 633                 clk_put(disp2_clk);
 634         if (!IS_ERR_OR_NULL(disp1_clk))
 635                 clk_put(disp1_clk);
 636         if (!IS_ERR_OR_NULL(clk))
 637                 clk_put(clk);
 638 err_iounmap_reg:
 639         iounmap(base);
 640 err_release_resource_reg:
 641         release_resource(base_res);
 642 err_free_hdmi:
 643         kfree(hdmi);
 644         return err;
 645 }
 646
 647 static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
 648 {
 649         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 650
 651         free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
 652         cancel_delayed_work_sync(&hdmi->work);
 653         switch_dev_unregister(&hdmi->hpd_switch);
 654         iounmap(hdmi->base);
 655         release_resource(hdmi->base_res);
 656         clk_put(hdmi->clk);
 657         clk_put(hdmi->disp1_clk);
 658         clk_put(hdmi->disp2_clk);
 659         tegra_edid_destroy(hdmi->edid);
 660
 661         kfree(hdmi);
 662
 663 }
 664
 665 static void tegra_dc_hdmi_setup_audio_fs_tables(struct tegra_dc *dc)
 666 {
 667         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 668         int i;
 669         unsigned freqs[] = {
 670                 32000,
 671                 44100,
 672                 48000,
 673                 88200,
 674                 96000,
 675                 176400,
 676                 192000,
 677         };
 678
 679         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
 680                 unsigned f = freqs[i];
 681                 unsigned eight_half;
 682                 unsigned delta;;
 683
 684                 if (f > 96000)
 685                         delta = 2;
 686                 else if (f > 48000)
 687                         delta = 6;
 688                 else
 689                         delta = 9;
 690
 691                 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
 692                 tegra_hdmi_writel(hdmi, AUDIO_FS_LOW(eight_half - delta) |
 693                                   AUDIO_FS_HIGH(eight_half + delta),
 694                                   HDMI_NV_PDISP_AUDIO_FS(i));
 695         }
 696 }
 697
 698 static int tegra_dc_hdmi_setup_audio(struct tegra_dc *dc)
 699 {
 700         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 701         const struct tegra_hdmi_audio_config *config;
 702         unsigned long audio_n;
 703         unsigned audio_freq = 44100; /* TODO: find some way of configuring this */
 704
 705         tegra_hdmi_writel(hdmi,
 706                           AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
 707                           AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
 708                           AUDIO_CNTRL0_SOURCE_SELECT_AUTO,
 709                           HDMI_NV_PDISP_AUDIO_CNTRL0);
 710
 711         config = tegra_hdmi_get_audio_config(audio_freq, dc->mode.pclk);
 712         if (!config) {
 713                 dev_err(&dc->ndev->dev,
 714                         "hdmi: can't set audio to %d at %d pix_clock",
 715                         audio_freq, dc->mode.pclk);
 716                 return -EINVAL;
 717         }
 718
 719         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
 720
 721         audio_n = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNALTE |
 722                 AUDIO_N_VALUE(config->n - 1);
 723         tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
 724
 725         tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
 726                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 727
 728         tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
 729                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 730
 731         tegra_hdmi_writel(hdmi, SPARE_HW_CTS | SPARE_FORCE_SW_CTS |
 732                           SPARE_CTS_RESET_VAL(1),
 733                           HDMI_NV_PDISP_HDMI_SPARE);
 734
 735         audio_n &= ~AUDIO_N_RESETF;
 736         tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
 737
 738         tegra_dc_hdmi_setup_audio_fs_tables(dc);
 739
 740         return 0;
 741 }
 742
 743 static void tegra_dc_hdmi_write_infopack(struct tegra_dc *dc, int header_reg,
 744                                          u8 type, u8 version, void *data, int len)
 745 {
 746         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 747         u32 subpack[2];  /* extra byte for zero padding of subpack */
 748         int i;
 749         u8 csum;
 750
 751         /* first byte of data is the checksum */
 752         csum = type + version + len - 1;
 753         for (i = 1; i < len; i++)
 754                 csum +=((u8 *)data)[i];
 755         ((u8 *)data)[0] = 0x100 - csum;
 756
 757         tegra_hdmi_writel(hdmi, INFOFRAME_HEADER_TYPE(type) |
 758                           INFOFRAME_HEADER_VERSION(version) |
 759                           INFOFRAME_HEADER_LEN(len - 1),
 760                           header_reg);
 761
 762         /* The audio inforame only has one set of subpack registers.  The hdmi
 763          * block pads the rest of the data as per the spec so we have to fixup
 764          * the length before filling in the subpacks.
 765          */
 766         if (header_reg == HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER)
 767                 len = 6;
 768
 769         /* each subpack 7 bytes devided into:
 770          *   subpack_low - bytes 0 - 3
 771          *   subpack_high - bytes 4 - 6 (with byte 7 padded to 0x00)
 772          */
 773         for (i = 0; i < len; i++) {
 774                 int subpack_idx = i % 7;
 775
 776                 if (subpack_idx == 0)
 777                         memset(subpack, 0x0, sizeof(subpack));
 778
 779                 ((u8 *)subpack)[subpack_idx] = ((u8 *)data)[i];
 780
 781                 if (subpack_idx == 6 || (i + 1 == len)) {
 782                         int reg = header_reg + 1 + (i / 7) * 2;
 783
 784                         tegra_hdmi_writel(hdmi, subpack[0], reg);
 785                         tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
 786                 }
 787         }
 788 }
 789
 790 static void tegra_dc_hdmi_setup_avi_infoframe(struct tegra_dc *dc, bool dvi)
 791 {
 792         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 793         struct hdmi_avi_infoframe avi;
 794
 795         if (dvi) {
 796                 tegra_hdmi_writel(hdmi, 0x0,
 797                                   HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 798                 return;
 799         }
 800
 801         memset(&avi, 0x0, sizeof(avi));
 802
 803         avi.r = HDMI_AVI_R_SAME;
 804
 805         if (dc->mode.v_active == 480) {
 806                 if (dc->mode.h_active == 640) {
 807                         avi.m = HDMI_AVI_M_4_3;
 808                         avi.vic = 1;
 809                 } else {
 810                         avi.m = HDMI_AVI_M_16_9;
 811                         avi.vic = 3;
 812                 }
 813         } else if (dc->mode.v_active == 576) {
 814                 /* CEC modes 17 and 18 differ only by the pysical size of the
 815                  * screen so we have to calculation the physical aspect
 816                  * ratio.  4 * 10 / 3  is 13
 817                  */
 818                 if ((dc->out->h_size * 10) / dc->out->v_size > 14) {
 819                         avi.m = HDMI_AVI_M_16_9;
 820                         avi.vic = 18;
 821                 } else {
 822                         avi.m = HDMI_AVI_M_16_9;
 823                         avi.vic = 17;
 824                 }
 825         } else if (dc->mode.v_active == 720) {
 826                 avi.m = HDMI_AVI_M_16_9;
 827                 if (dc->mode.h_front_porch == 110)
 828                         avi.vic = 4; /* 60 Hz */
 829                 else
 830                         avi.vic = 19; /* 50 Hz */
 831         } else if (dc->mode.v_active == 720) {
 832                 avi.m = HDMI_AVI_M_16_9;
 833                 if (dc->mode.h_front_porch == 88)
 834                         avi.vic = 16; /* 60 Hz */
 835                 else if (dc->mode.h_front_porch == 528)
 836                         avi.vic = 31; /* 50 Hz */
 837                 else
 838                         avi.vic = 32; /* 24 Hz */
 839         } else {
 840                 avi.m = HDMI_AVI_M_16_9;
 841                 avi.vic = 0;
 842         }
 843
 844
 845         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
 846                                      HDMI_INFOFRAME_TYPE_AVI,
 847                                      HDMI_AVI_VERSION,
 848                                      &avi, sizeof(avi));
 849
 850         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
 851                           HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 852 }
 853
 854 static void tegra_dc_hdmi_setup_audio_infoframe(struct tegra_dc *dc, bool dvi)
 855 {
 856         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 857         struct hdmi_audio_infoframe audio;
 858
 859         if (dvi) {
 860                 tegra_hdmi_writel(hdmi, 0x0,
 861                                   HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 862                 return;
 863         }
 864
 865         memset(&audio, 0x0, sizeof(audio));
 866
 867         audio.cc = HDMI_AUDIO_CC_2;
 868         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
 869                                      HDMI_INFOFRAME_TYPE_AUDIO,
 870                                      HDMI_AUDIO_VERSION,
 871                                      &audio, sizeof(audio));
 872
 873         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
 874                           HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 875 }
 876
 877 static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
 878 {
 879         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 880         int pulse_start;
 881         int dispclk_div_8_2;
 882         int pll0;
 883         int pll1;
 884         int ds;
 885         int retries;
 886         int rekey;
 887         int err;
 888         unsigned long val;
 889
 890         /* enbale power, clocks, resets, etc. */
 891
 892         /* The upstream DC needs to be clocked for accesses to HDMI to not
 893          * hard lock the system.  Because we don't know if HDMI is conencted
 894          * to disp1 or disp2 we need to enable both until we set the DC mux.
 895          */
 896         clk_enable(hdmi->disp1_clk);
 897         clk_enable(hdmi->disp2_clk);
 898         tegra_dc_setup_clk(dc, hdmi->clk);
 899         clk_set_rate(hdmi->clk, dc->mode.pclk);
 900
 901         clk_enable(hdmi->clk);
 902         tegra_periph_reset_assert(hdmi->clk);
 903         mdelay(1);
 904         tegra_periph_reset_deassert(hdmi->clk);
 905
 906         /* TODO: copy HDCP keys from KFUSE to HDMI */
 907
 908         /* Program display timing registers: handled by dc */
 909
 910         /* program HDMI registers and SOR sequencer */
 911
 912         tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
 913         tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
 914                         DC_DISP_DISP_COLOR_CONTROL);
 915
 916         /* video_preamble uses h_pulse2 */
 917         pulse_start = dc->mode.h_ref_to_sync + dc->mode.h_sync_width +
 918                 dc->mode.h_back_porch - 10;
 919         tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
 920         tegra_dc_writel(dc,
 921                         PULSE_MODE_NORMAL |
 922                         PULSE_POLARITY_HIGH |
 923                         PULSE_QUAL_VACTIVE |
 924                         PULSE_LAST_END_A,
 925                         DC_DISP_H_PULSE2_CONTROL);
 926         tegra_dc_writel(dc, PULSE_START(pulse_start) | PULSE_END(pulse_start + 8),
 927                   DC_DISP_H_PULSE2_POSITION_A);
 928
 929         tegra_hdmi_writel(hdmi,
 930                           VSYNC_WINDOW_END(0x210) |
 931                           VSYNC_WINDOW_START(0x200) |
 932                           VSYNC_WINDOW_ENABLE,
 933                           HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
 934
 935         tegra_hdmi_writel(hdmi,
 936                           (dc->ndev->id ? HDMI_SRC_DISPLAYB : HDMI_SRC_DISPLAYA) |
 937                           ARM_VIDEO_RANGE_LIMITED,
 938                           HDMI_NV_PDISP_INPUT_CONTROL);
 939
 940         clk_disable(hdmi->disp1_clk);
 941         clk_disable(hdmi->disp2_clk);
 942
 943         dispclk_div_8_2 = clk_get_rate(hdmi->clk) / 1000000 * 4;
 944         tegra_hdmi_writel(hdmi,
 945                           SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
 946                           SOR_REFCLK_DIV_FRAC(dispclk_div_8_2),
 947                           HDMI_NV_PDISP_SOR_REFCLK);
 948
 949
 950         if (!hdmi->dvi) {
 951                 err = tegra_dc_hdmi_setup_audio(dc);
 952
 953                 if (err < 0)
 954                         hdmi->dvi = true;
 955         }
 956
 957         rekey = HDMI_REKEY_DEFAULT;
 958         val = HDMI_CTRL_REKEY(rekey);
 959         val |= HDMI_CTRL_MAX_AC_PACKET((dc->mode.h_sync_width +
 960                                         dc->mode.h_back_porch +
 961                                         dc->mode.h_front_porch -
 962                                         rekey - 18) / 32);
 963         if (!hdmi->dvi)
 964                 val |= HDMI_CTRL_ENABLE;
 965         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_CTRL);
 966
 967         if (hdmi->dvi)
 968                 tegra_hdmi_writel(hdmi, 0x0,
 969                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 970         else
 971                 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
 972                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 973
 974
 975         tegra_dc_hdmi_setup_avi_infoframe(dc, hdmi->dvi);
 976         tegra_dc_hdmi_setup_audio_infoframe(dc, hdmi->dvi);
 977
 978         /* TMDS CONFIG */
 979         pll0 = 0x200033f;
 980         pll1 = 0;
 981
 982         pll0 &= ~SOR_PLL_PWR & ~SOR_PLL_VCOPD & ~SOR_PLL_PDBG & ~SOR_PLL_PDPORT & ~SOR_PLL_PULLDOWN &
 983                 ~SOR_PLL_VCOCAP(~0) & ~SOR_PLL_ICHPMP(~0);
 984         pll0 |= SOR_PLL_RESISTORSEL;
 985
 986         if (dc->mode.pclk <= 27000000)
 987                 pll0 |= SOR_PLL_VCOCAP(0);
 988         else if (dc->mode.pclk <= 74250000)
 989                 pll0 |= SOR_PLL_VCOCAP(1);
 990         else
 991                 pll0 |= SOR_PLL_VCOCAP(3);
 992
 993         if (dc->mode.h_active == 1080) {
 994                 pll0 |= SOR_PLL_ICHPMP(1) | SOR_PLL_TX_REG_LOAD(3) |
 995                         SOR_PLL_TX_REG_LOAD(3) | SOR_PLL_BG_V17_S(3);
 996                 pll1 |= SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN;
 997         } else {
 998                 pll0 |= SOR_PLL_ICHPMP(2);
 999         }
1000
1001         tegra_hdmi_writel(hdmi, pll0, HDMI_NV_PDISP_SOR_PLL0);
1002         tegra_hdmi_writel(hdmi, pll1, HDMI_NV_PDISP_SOR_PLL1);
1003
1004         if (pll1 & SOR_PLL_PE_EN) {
1005                 tegra_hdmi_writel(hdmi,
1006                                   PE_CURRENT0(0xf) |
1007                                   PE_CURRENT1(0xf) |
1008                                   PE_CURRENT2(0xf) |
1009                                   PE_CURRENT3(0xf),
1010                                   HDMI_NV_PDISP_PE_CURRENT);
1011         }
1012
1013         /* enable SOR */
1014         if (dc->mode.h_active == 1080)
1015                 ds = DRIVE_CURRENT_13_500_mA;
1016         else
1017                 ds = DRIVE_CURRENT_5_250_mA;
1018
1019         tegra_hdmi_writel(hdmi,
1020                           DRIVE_CURRENT_LANE0(ds) |
1021                           DRIVE_CURRENT_LANE1(ds) |
1022                           DRIVE_CURRENT_LANE2(ds) |
1023                           DRIVE_CURRENT_LANE3(ds) |
1024                           DRIVE_CURRENT_FUSE_OVERRIDE,
1025                           HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1026
1027         tegra_hdmi_writel(hdmi,
1028                           SOR_SEQ_CTL_PU_PC(0) |
1029                           SOR_SEQ_PU_PC_ALT(0) |
1030                           SOR_SEQ_PD_PC(8) |
1031                           SOR_SEQ_PD_PC_ALT(8),
1032                           HDMI_NV_PDISP_SOR_SEQ_CTL);
1033
1034         val = SOR_SEQ_INST_WAIT_TIME(1) |
1035                 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1036                 SOR_SEQ_INST_HALT |
1037                 SOR_SEQ_INST_PIN_A_LOW |
1038                 SOR_SEQ_INST_PIN_B_LOW |
1039                 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1040
1041         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST0);
1042         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST8);
1043
1044         val = 0x1c800;
1045         val &= ~SOR_CSTM_ROTCLK(~0);
1046         val |= SOR_CSTM_ROTCLK(2);
1047         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_CSTM);
1048
1049
1050         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1051         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
1052         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1053
1054
1055         /* start SOR */
1056         tegra_hdmi_writel(hdmi,
1057                           SOR_PWR_NORMAL_STATE_PU |
1058                           SOR_PWR_NORMAL_START_NORMAL |
1059                           SOR_PWR_SAFE_STATE_PD |
1060                           SOR_PWR_SETTING_NEW_TRIGGER,
1061                           HDMI_NV_PDISP_SOR_PWR);
1062         tegra_hdmi_writel(hdmi,
1063                           SOR_PWR_NORMAL_STATE_PU |
1064                           SOR_PWR_NORMAL_START_NORMAL |
1065                           SOR_PWR_SAFE_STATE_PD |
1066                           SOR_PWR_SETTING_NEW_DONE,
1067                           HDMI_NV_PDISP_SOR_PWR);
1068
1069         retries = 1000;
1070         do {
1071                 BUG_ON(--retries < 0);
1072                 val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1073         } while (val & SOR_PWR_SETTING_NEW_PENDING);
1074
1075         val = SOR_STATE_ASY_CRCMODE_COMPLETE |
1076                 SOR_STATE_ASY_OWNER_HEAD0 |
1077                 SOR_STATE_ASY_SUBOWNER_BOTH |
1078                 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1079                 SOR_STATE_ASY_DEPOL_POS;
1080
1081         if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1082                 val |= SOR_STATE_ASY_HSYNCPOL_NEG;
1083         else
1084                 val |= SOR_STATE_ASY_HSYNCPOL_POS;
1085
1086         if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1087                 val |= SOR_STATE_ASY_VSYNCPOL_NEG;
1088         else
1089                 val |= SOR_STATE_ASY_VSYNCPOL_POS;
1090
1091         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE2);
1092
1093         val = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1094         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE1);
1095
1096         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1097         tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1098         tegra_hdmi_writel(hdmi, val | SOR_STATE_ATTACHED,
1099                           HDMI_NV_PDISP_SOR_STATE1);
1100         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1101
1102         tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1103
1104         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1105                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1106                         DC_CMD_DISPLAY_POWER_CONTROL);
1107
1108         tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
1109         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
1110         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1111 }
1112
1113 static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
1114 {
1115         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1116
1117         tegra_periph_reset_assert(hdmi->clk);
1118         clk_disable(hdmi->clk);
1119 }
1120 struct tegra_dc_out_ops tegra_dc_hdmi_ops = {
1121         .init = tegra_dc_hdmi_init,
1122         .destroy = tegra_dc_hdmi_destroy,
1123         .enable = tegra_dc_hdmi_enable,
1124         .disable = tegra_dc_hdmi_disable,
1125         .detect = tegra_dc_hdmi_detect,
1126         .suspend = tegra_dc_hdmi_suspend,
1127         .resume = tegra_dc_hdmi_resume,
1128 };
1129