drivers/video/tegra/dc/hdmi.c

   1 /*
   2  * drivers/video/tegra/dc/hdmi.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Erik Gilling <konkers@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/fb.h>
  22 #include <linux/gpio.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/workqueue.h>
  28
  29 #include <mach/clk.h>
  30 #include <mach/dc.h>
  31 #include <mach/fb.h>
  32 #include <mach/nvhost.h>
  33
  34 #include <video/tegrafb.h>
  35
  36 #include "dc_reg.h"
  37 #include "dc_priv.h"
  38 #include "hdmi_reg.h"
  39 #include "hdmi.h"
  40 #include "edid.h"
  41 #include "nvhdcp.h"
  42
  43 /* datasheet claims this will always be 216MHz */
  44 #define HDMI_AUDIOCLK_FREQ              216000000
  45
  46 #define HDMI_REKEY_DEFAULT              56
  47
  48 struct tegra_dc_hdmi_data {
  49         struct tegra_dc                 *dc;
  50         struct tegra_edid               *edid;
  51         struct tegra_nvhdcp             *nvhdcp;
  52         struct delayed_work             work;
  53
  54         struct resource                 *base_res;
  55         void __iomem                    *base;
  56         struct clk                      *clk;
  57
  58         struct clk                      *disp1_clk;
  59         struct clk                      *disp2_clk;
  60
  61         spinlock_t                      suspend_lock;
  62         bool                            suspended;
  63         bool                            hpd_pending;
  64
  65         bool                            dvi;
  66 };
  67
  68 const struct fb_videomode tegra_dc_hdmi_supported_modes[] = {
  69         /* 1280x720p 60hz: EIA/CEA-861-B Format 4 */
  70         {
  71                 .xres =         1280,
  72                 .yres =         720,
  73                 .pixclock =     KHZ2PICOS(74250),
  74                 .hsync_len =    40,     /* h_sync_width */
  75                 .vsync_len =    5,      /* v_sync_width */
  76                 .left_margin =  220,    /* h_back_porch */
  77                 .upper_margin = 20,     /* v_back_porch */
  78                 .right_margin = 110,    /* h_front_porch */
  79                 .lower_margin = 5,      /* v_front_porch */
  80                 .vmode =        FB_VMODE_NONINTERLACED,
  81                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  82         },
  83
  84         /* 720x480p 59.94hz: EIA/CEA-861-B Formats 2 & 3 */
  85         {
  86                 .xres =         720,
  87                 .yres =         480,
  88                 .pixclock =     KHZ2PICOS(27000),
  89                 .hsync_len =    62,     /* h_sync_width */
  90                 .vsync_len =    6,      /* v_sync_width */
  91                 .left_margin =  60,     /* h_back_porch */
  92                 .upper_margin = 30,     /* v_back_porch */
  93                 .right_margin = 16,     /* h_front_porch */
  94                 .lower_margin = 9,      /* v_front_porch */
  95                 .vmode =        FB_VMODE_NONINTERLACED,
  96                 .sync = 0,
  97         },
  98
  99         /* 640x480p 60hz: EIA/CEA-861-B Format 1 */
 100         {
 101                 .xres =         640,
 102                 .yres =         480,
 103                 .pixclock =     KHZ2PICOS(25200),
 104                 .hsync_len =    96,     /* h_sync_width */
 105                 .vsync_len =    2,      /* v_sync_width */
 106                 .left_margin =  48,     /* h_back_porch */
 107                 .upper_margin = 33,     /* v_back_porch */
 108                 .right_margin = 16,     /* h_front_porch */
 109                 .lower_margin = 10,     /* v_front_porch */
 110                 .vmode =        FB_VMODE_NONINTERLACED,
 111                 .sync = 0,
 112         },
 113
 114         /* 720x576p 50hz EIA/CEA-861-B Formats 17 & 18 */
 115         {
 116                 .xres =         720,
 117                 .yres =         576,
 118                 .pixclock =     KHZ2PICOS(27000),
 119                 .hsync_len =    64,     /* h_sync_width */
 120                 .vsync_len =    5,      /* v_sync_width */
 121                 .left_margin =  68,     /* h_back_porch */
 122                 .upper_margin = 39,     /* v_back_porch */
 123                 .right_margin = 12,     /* h_front_porch */
 124                 .lower_margin = 5,      /* v_front_porch */
 125                 .vmode =        FB_VMODE_NONINTERLACED,
 126                 .sync = 0,
 127         },
 128
 129         /* 1920x1080p 59.94/60hz EIA/CEA-861-B Format 16 */
 130         {
 131                 .xres =         1920,
 132                 .yres =         1080,
 133                 .pixclock =     KHZ2PICOS(148500),
 134                 .hsync_len =    44,     /* h_sync_width */
 135                 .vsync_len =    5,      /* v_sync_width */
 136                 .left_margin =  148,    /* h_back_porch */
 137                 .upper_margin = 36,     /* v_back_porch */
 138                 .right_margin = 88,     /* h_front_porch */
 139                 .lower_margin = 4,      /* v_front_porch */
 140                 .vmode =        FB_VMODE_NONINTERLACED,
 141                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 142         },
 143 };
 144
 145 struct tegra_hdmi_audio_config {
 146         unsigned pix_clock;
 147         unsigned n;
 148         unsigned cts;
 149 };
 150
 151 const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
 152         {25200000,      4096,   25250},
 153         {27000000,      4096,   27000},
 154         {54000000,      4096,   54000},
 155         {74250000,      4096,   74250},
 156         {148500000,     4096,   148500},
 157         {0,             0,      0},
 158 };
 159
 160 const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
 161         {25200000,      14112,  63125},
 162         {27000000,      6272,   30000},
 163         {54000000,      6272,   60000},
 164         {74250000,      6272,   82500},
 165         {148500000,     6272,   165000},
 166         {0,             0,      0},
 167 };
 168
 169 const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
 170         {25200000,      6144,   25250},
 171         {27000000,      6144,   27000},
 172         {54000000,      6144,   54000},
 173         {74250000,      6144,   74250},
 174         {148500000,     6144,   148500},
 175         {0,             0,      0},
 176 };
 177
 178 static const struct tegra_hdmi_audio_config
 179 *tegra_hdmi_get_audio_config(unsigned audio_freq, unsigned pix_clock)
 180 {
 181         const struct tegra_hdmi_audio_config *table;
 182
 183         switch (audio_freq) {
 184         case 32000:
 185                 table = tegra_hdmi_audio_32k;
 186                 break;
 187
 188         case 44100:
 189                 table = tegra_hdmi_audio_44_1k;
 190                 break;
 191
 192         case 48000:
 193                 table = tegra_hdmi_audio_48k;
 194                 break;
 195
 196         default:
 197                 return NULL;
 198         }
 199
 200         while (table->pix_clock) {
 201                 if (table->pix_clock == pix_clock)
 202                         return table;
 203                 table++;
 204         }
 205
 206         return NULL;
 207 }
 208
 209
 210 unsigned long tegra_hdmi_readl(struct tegra_dc_hdmi_data *hdmi,
 211                                              unsigned long reg)
 212 {
 213         return readl(hdmi->base + reg * 4);
 214 }
 215
 216 void tegra_hdmi_writel(struct tegra_dc_hdmi_data *hdmi,
 217                                      unsigned long val, unsigned long reg)
 218 {
 219         writel(val, hdmi->base + reg * 4);
 220 }
 221
 222 static inline void tegra_hdmi_clrsetbits(struct tegra_dc_hdmi_data *hdmi,
 223                                          unsigned long reg, unsigned long clr,
 224                                          unsigned long set)
 225 {
 226         unsigned long val = tegra_hdmi_readl(hdmi, reg);
 227         val &= ~clr;
 228         val |= set;
 229         tegra_hdmi_writel(hdmi, val, reg);
 230 }
 231
 232 #define DUMP_REG(a) do {                                                \
 233                 printk("HDMI %-32s\t%03x\t%08lx\n",                     \
 234                        #a, a, tegra_hdmi_readl(hdmi, a));               \
 235         } while (0)
 236
 237 #ifdef DEBUG
 238 static void hdmi_dumpregs(struct tegra_dc_hdmi_data *hdmi)
 239 {
 240         DUMP_REG(HDMI_CTXSW);
 241         DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
 242         DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
 243         DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
 244         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
 245         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
 246         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
 247         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
 248         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
 249         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
 250         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
 251         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
 252         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
 253         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
 254         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
 255         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
 256         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
 257         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
 258         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
 259         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
 260         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
 261         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
 262         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
 263         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
 264         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
 265         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
 266         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
 267         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
 268         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
 269         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
 270         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 271         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
 272         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
 273         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
 274         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
 275         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 276         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
 277         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
 278         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
 279         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
 280         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
 281         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
 282         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 283         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
 284         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
 285         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
 286         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
 287         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
 288         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
 289         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
 290         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
 291         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
 292         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
 293         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
 294         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
 295         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
 296         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 297         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 298         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
 299         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
 300         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
 301         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
 302         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
 303         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
 304         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
 305         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
 306         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
 307         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
 308         DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
 309         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
 310         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
 311         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
 312         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
 313         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
 314         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
 315         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
 316         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
 317         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
 318         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
 319         DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
 320         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
 321         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
 322         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_CTRL);
 323         DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
 324         DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
 325         DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
 326         DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
 327         DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
 328         DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
 329         DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
 330         DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
 331         DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
 332         DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
 333         DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
 334         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
 335         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST0);
 336         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST1);
 337         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST2);
 338         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST3);
 339         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST4);
 340         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST5);
 341         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST6);
 342         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST7);
 343         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST8);
 344         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST9);
 345         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTA);
 346         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTB);
 347         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTC);
 348         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTD);
 349         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTE);
 350         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTF);
 351         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
 352         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
 353         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
 354         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
 355         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
 356         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
 357         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
 358         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
 359         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
 360         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
 361         DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
 362         DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
 363         DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
 364         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
 365         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
 366         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
 367         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
 368         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
 369         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
 370         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
 371         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
 372         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
 373         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
 374         DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
 375         DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
 376         DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
 377         DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
 378         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
 379         DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
 380         DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
 381         DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
 382         DUMP_REG(HDMI_NV_PDISP_SCRATCH);
 383         DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
 384         DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
 385         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
 386         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
 387         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
 388         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
 389         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
 390         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
 391         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
 392         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
 393         DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
 394 }
 395 #endif
 396
 397 #define PIXCLOCK_TOLERANCE      200
 398
 399 static bool tegra_dc_hdmi_mode_equal(const struct fb_videomode *mode1,
 400                                         const struct fb_videomode *mode2)
 401 {
 402         return mode1->xres      == mode2->xres &&
 403                 mode1->yres     == mode2->yres &&
 404                 mode1->vmode    == mode2->vmode;
 405 }
 406
 407 static bool tegra_dc_hdmi_mode_filter(struct fb_videomode *mode)
 408 {
 409         int i;
 410         int clocks;
 411
 412         for (i = 0; i < ARRAY_SIZE(tegra_dc_hdmi_supported_modes); i++) {
 413                 if (tegra_dc_hdmi_mode_equal(&tegra_dc_hdmi_supported_modes[i],
 414                                              mode)) {
 415                         memcpy(mode, &tegra_dc_hdmi_supported_modes[i], sizeof(*mode));
 416                         mode->flag = FB_MODE_IS_DETAILED;
 417                         clocks = (mode->left_margin + mode->xres + mode->right_margin + mode->hsync_len) *
 418                                 (mode->upper_margin + mode->yres + mode->lower_margin + mode->vsync_len);
 419                         mode->refresh = (PICOS2KHZ(mode->pixclock) * 1000) / clocks;
 420                         return true;
 421                 }
 422         }
 423
 424         return false;
 425 }
 426
 427
 428 static bool tegra_dc_hdmi_hpd(struct tegra_dc *dc)
 429 {
 430         int sense;
 431         int level;
 432
 433         level = gpio_get_value(dc->out->hotplug_gpio);
 434
 435         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
 436
 437         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
 438                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
 439 }
 440
 441 static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
 442 {
 443         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 444         struct fb_monspecs specs;
 445         int err;
 446
 447         if (!tegra_dc_hdmi_hpd(dc))
 448                 goto fail;
 449
 450         err = tegra_edid_get_monspecs(hdmi->edid, &specs);
 451         if (err < 0) {
 452                 dev_err(&dc->ndev->dev, "error reading edid\n");
 453                 goto fail;
 454         }
 455
 456         /* monitors like to lie about these but they are still useful for
 457          * detecting aspect ratios
 458          */
 459         dc->out->h_size = specs.max_x * 1000;
 460         dc->out->v_size = specs.max_y * 1000;
 461
 462
 463         hdmi->dvi = !(specs.misc & FB_MISC_HDMI);
 464
 465         tegra_fb_update_monspecs(dc->fb, &specs, tegra_dc_hdmi_mode_filter);
 466         dev_info(&dc->ndev->dev, "display detected\n");
 467         return true;
 468
 469 fail:
 470         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
 471         return false;
 472 }
 473
 474
 475 static void tegra_dc_hdmi_detect_worker(struct work_struct *work)
 476 {
 477         struct tegra_dc_hdmi_data *hdmi =
 478                 container_of(to_delayed_work(work), struct tegra_dc_hdmi_data, work);
 479         struct tegra_dc *dc = hdmi->dc;
 480
 481         if (!tegra_dc_hdmi_detect(dc)) {
 482                 tegra_dc_disable(dc);
 483                 tegra_fb_update_monspecs(dc->fb, NULL, NULL);
 484         }
 485 }
 486
 487 static irqreturn_t tegra_dc_hdmi_irq(int irq, void *ptr)
 488 {
 489         struct tegra_dc *dc = ptr;
 490         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 491         unsigned long flags;
 492
 493         spin_lock_irqsave(&hdmi->suspend_lock, flags);
 494         if (hdmi->suspended) {
 495                 hdmi->hpd_pending = true;
 496         } else {
 497                 if (tegra_dc_hdmi_hpd(dc))
 498                         schedule_delayed_work(&hdmi->work, msecs_to_jiffies(100));
 499                 else
 500                         schedule_delayed_work(&hdmi->work, msecs_to_jiffies(0));
 501         }
 502         spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
 503
 504         return IRQ_HANDLED;
 505 }
 506
 507 static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
 508 {
 509         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 510         unsigned long flags;
 511
 512         spin_lock_irqsave(&hdmi->suspend_lock, flags);
 513         tegra_nvhdcp_suspend(hdmi->nvhdcp);
 514         hdmi->suspended = true;
 515         spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
 516 }
 517
 518 static void tegra_dc_hdmi_resume(struct tegra_dc *dc)
 519 {
 520         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 521         unsigned long flags;
 522
 523         spin_lock_irqsave(&hdmi->suspend_lock, flags);
 524         hdmi->suspended = false;
 525         if (hdmi->hpd_pending) {
 526                 if (tegra_dc_hdmi_hpd(dc))
 527                         schedule_delayed_work(&hdmi->work, msecs_to_jiffies(100));
 528                 else
 529                         schedule_delayed_work(&hdmi->work, msecs_to_jiffies(0));
 530                 hdmi->hpd_pending = false;
 531         }
 532         spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
 533 }
 534
 535 static int tegra_dc_hdmi_init(struct tegra_dc *dc)
 536 {
 537         struct tegra_dc_hdmi_data *hdmi;
 538         struct resource *res;
 539         struct resource *base_res;
 540         void __iomem *base;
 541         struct clk *clk = NULL;
 542         struct clk *disp1_clk = NULL;
 543         struct clk *disp2_clk = NULL;
 544         int err;
 545
 546         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
 547         if (!hdmi)
 548                 return -ENOMEM;
 549
 550         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM, "hdmi_regs");
 551         if (!res) {
 552                 dev_err(&dc->ndev->dev, "hdmi: no mem resource\n");
 553                 err = -ENOENT;
 554                 goto err_free_hdmi;
 555         }
 556
 557         base_res = request_mem_region(res->start, resource_size(res), dc->ndev->name);
 558         if (!base_res) {
 559                 dev_err(&dc->ndev->dev, "hdmi: request_mem_region failed\n");
 560                 err = -EBUSY;
 561                 goto err_free_hdmi;
 562         }
 563
 564         base = ioremap(res->start, resource_size(res));
 565         if (!base) {
 566                 dev_err(&dc->ndev->dev, "hdmi: registers can't be mapped\n");
 567                 err = -EBUSY;
 568                 goto err_release_resource_reg;
 569         }
 570
 571         clk = clk_get(&dc->ndev->dev, "hdmi");
 572         if (IS_ERR_OR_NULL(clk)) {
 573                 dev_err(&dc->ndev->dev, "hdmi: can't get clock\n");
 574                 err = -ENOENT;
 575                 goto err_iounmap_reg;
 576         }
 577
 578         disp1_clk = clk_get_sys("tegradc.0", NULL);
 579         if (IS_ERR_OR_NULL(disp1_clk)) {
 580                 dev_err(&dc->ndev->dev, "hdmi: can't disp1 clock\n");
 581                 err = -ENOENT;
 582                 goto err_put_clock;
 583         }
 584
 585         disp2_clk = clk_get_sys("tegradc.1", NULL);
 586         if (IS_ERR_OR_NULL(disp2_clk)) {
 587                 dev_err(&dc->ndev->dev, "hdmi: can't disp2 clock\n");
 588                 err = -ENOENT;
 589                 goto err_put_clock;
 590         }
 591
 592         /* TODO: support non-hotplug */
 593         if (request_irq(gpio_to_irq(dc->out->hotplug_gpio), tegra_dc_hdmi_irq,
 594                         IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
 595                         dev_name(&dc->ndev->dev), dc)) {
 596                 dev_err(&dc->ndev->dev, "hdmi: request_irq %d failed\n",
 597                         gpio_to_irq(dc->out->hotplug_gpio));
 598                 err = -EBUSY;
 599                 goto err_put_clock;
 600         }
 601
 602         hdmi->edid = tegra_edid_create(dc->out->dcc_bus);
 603         if (IS_ERR_OR_NULL(hdmi->edid)) {
 604                 dev_err(&dc->ndev->dev, "hdmi: can't create edid\n");
 605                 err = PTR_ERR(hdmi->edid);
 606                 goto err_free_irq;
 607         }
 608
 609         hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, dc->ndev->id,
 610                         dc->out->dcc_bus);
 611         if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
 612                 dev_err(&dc->ndev->dev, "hdmi: can't create nvhdcp\n");
 613                 err = PTR_ERR(hdmi->nvhdcp);
 614                 goto err_edid_destroy;
 615         }
 616
 617         INIT_DELAYED_WORK(&hdmi->work, tegra_dc_hdmi_detect_worker);
 618
 619         hdmi->dc = dc;
 620         hdmi->base = base;
 621         hdmi->base_res = base_res;
 622         hdmi->clk = clk;
 623         hdmi->disp1_clk = disp1_clk;
 624         hdmi->disp2_clk = disp2_clk;
 625         hdmi->suspended = false;
 626         hdmi->hpd_pending = false;
 627         spin_lock_init(&hdmi->suspend_lock);
 628
 629         dc->out->depth = 24;
 630
 631         tegra_dc_set_outdata(dc, hdmi);
 632
 633         /* boards can select default content protection policy */
 634         if (dc->out->flags & TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND) {
 635                 tegra_nvhdcp_set_policy(hdmi->nvhdcp,
 636                         TEGRA_NVHDCP_POLICY_ON_DEMAND);
 637         } else {
 638                 tegra_nvhdcp_set_policy(hdmi->nvhdcp,
 639                         TEGRA_NVHDCP_POLICY_ALWAYS_ON);
 640         }
 641         return 0;
 642
 643 err_edid_destroy:
 644         tegra_edid_destroy(hdmi->edid);
 645 err_free_irq:
 646         free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
 647 err_put_clock:
 648         if (!IS_ERR_OR_NULL(disp2_clk))
 649                 clk_put(disp2_clk);
 650         if (!IS_ERR_OR_NULL(disp1_clk))
 651                 clk_put(disp1_clk);
 652         if (!IS_ERR_OR_NULL(clk))
 653                 clk_put(clk);
 654 err_iounmap_reg:
 655         iounmap(base);
 656 err_release_resource_reg:
 657         release_resource(base_res);
 658 err_free_hdmi:
 659         kfree(hdmi);
 660         return err;
 661 }
 662
 663 static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
 664 {
 665         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 666
 667         free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
 668         cancel_delayed_work_sync(&hdmi->work);
 669         iounmap(hdmi->base);
 670         release_resource(hdmi->base_res);
 671         clk_put(hdmi->clk);
 672         clk_put(hdmi->disp1_clk);
 673         clk_put(hdmi->disp2_clk);
 674         tegra_edid_destroy(hdmi->edid);
 675         tegra_nvhdcp_destroy(hdmi->nvhdcp);
 676
 677         kfree(hdmi);
 678
 679 }
 680
 681 static void tegra_dc_hdmi_setup_audio_fs_tables(struct tegra_dc *dc)
 682 {
 683         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 684         int i;
 685         unsigned freqs[] = {
 686                 32000,
 687                 44100,
 688                 48000,
 689                 88200,
 690                 96000,
 691                 176400,
 692                 192000,
 693         };
 694
 695         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
 696                 unsigned f = freqs[i];
 697                 unsigned eight_half;
 698                 unsigned delta;;
 699
 700                 if (f > 96000)
 701                         delta = 2;
 702                 else if (f > 48000)
 703                         delta = 6;
 704                 else
 705                         delta = 9;
 706
 707                 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
 708                 tegra_hdmi_writel(hdmi, AUDIO_FS_LOW(eight_half - delta) |
 709                                   AUDIO_FS_HIGH(eight_half + delta),
 710                                   HDMI_NV_PDISP_AUDIO_FS(i));
 711         }
 712 }
 713
 714 static int tegra_dc_hdmi_setup_audio(struct tegra_dc *dc)
 715 {
 716         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 717         const struct tegra_hdmi_audio_config *config;
 718         unsigned long audio_n;
 719         unsigned audio_freq = 44100; /* TODO: find some way of configuring this */
 720
 721         tegra_hdmi_writel(hdmi,
 722                           AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
 723                           AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
 724                           AUDIO_CNTRL0_SOURCE_SELECT_AUTO,
 725                           HDMI_NV_PDISP_AUDIO_CNTRL0);
 726
 727         config = tegra_hdmi_get_audio_config(audio_freq, dc->mode.pclk);
 728         if (!config) {
 729                 dev_err(&dc->ndev->dev,
 730                         "hdmi: can't set audio to %d at %d pix_clock",
 731                         audio_freq, dc->mode.pclk);
 732                 return -EINVAL;
 733         }
 734
 735         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
 736
 737         audio_n = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNALTE |
 738                 AUDIO_N_VALUE(config->n - 1);
 739         tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
 740
 741         tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
 742                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 743
 744         tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
 745                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 746
 747         tegra_hdmi_writel(hdmi, SPARE_HW_CTS | SPARE_FORCE_SW_CTS |
 748                           SPARE_CTS_RESET_VAL(1),
 749                           HDMI_NV_PDISP_HDMI_SPARE);
 750
 751         audio_n &= ~AUDIO_N_RESETF;
 752         tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
 753
 754         tegra_dc_hdmi_setup_audio_fs_tables(dc);
 755
 756         return 0;
 757 }
 758
 759 static void tegra_dc_hdmi_write_infopack(struct tegra_dc *dc, int header_reg,
 760                                          u8 type, u8 version, void *data, int len)
 761 {
 762         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 763         u32 subpack[2];  /* extra byte for zero padding of subpack */
 764         int i;
 765         u8 csum;
 766
 767         /* first byte of data is the checksum */
 768         csum = type + version + len - 1;
 769         for (i = 1; i < len; i++)
 770                 csum +=((u8 *)data)[i];
 771         ((u8 *)data)[0] = 0x100 - csum;
 772
 773         tegra_hdmi_writel(hdmi, INFOFRAME_HEADER_TYPE(type) |
 774                           INFOFRAME_HEADER_VERSION(version) |
 775                           INFOFRAME_HEADER_LEN(len - 1),
 776                           header_reg);
 777
 778         /* The audio inforame only has one set of subpack registers.  The hdmi
 779          * block pads the rest of the data as per the spec so we have to fixup
 780          * the length before filling in the subpacks.
 781          */
 782         if (header_reg == HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER)
 783                 len = 6;
 784
 785         /* each subpack 7 bytes devided into:
 786          *   subpack_low - bytes 0 - 3
 787          *   subpack_high - bytes 4 - 6 (with byte 7 padded to 0x00)
 788          */
 789         for (i = 0; i < len; i++) {
 790                 int subpack_idx = i % 7;
 791
 792                 if (subpack_idx == 0)
 793                         memset(subpack, 0x0, sizeof(subpack));
 794
 795                 ((u8 *)subpack)[subpack_idx] = ((u8 *)data)[i];
 796
 797                 if (subpack_idx == 6 || (i + 1 == len)) {
 798                         int reg = header_reg + 1 + (i / 7) * 2;
 799
 800                         tegra_hdmi_writel(hdmi, subpack[0], reg);
 801                         tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
 802                 }
 803         }
 804 }
 805
 806 static void tegra_dc_hdmi_setup_avi_infoframe(struct tegra_dc *dc, bool dvi)
 807 {
 808         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 809         struct hdmi_avi_infoframe avi;
 810
 811         if (dvi) {
 812                 tegra_hdmi_writel(hdmi, 0x0,
 813                                   HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 814                 return;
 815         }
 816
 817         memset(&avi, 0x0, sizeof(avi));
 818
 819         avi.r = HDMI_AVI_R_SAME;
 820
 821         if (dc->mode.v_active == 480) {
 822                 if (dc->mode.h_active == 640) {
 823                         avi.m = HDMI_AVI_M_4_3;
 824                         avi.vic = 1;
 825                 } else {
 826                         avi.m = HDMI_AVI_M_16_9;
 827                         avi.vic = 3;
 828                 }
 829         } else if (dc->mode.v_active == 576) {
 830                 /* CEC modes 17 and 18 differ only by the pysical size of the
 831                  * screen so we have to calculation the physical aspect
 832                  * ratio.  4 * 10 / 3  is 13
 833                  */
 834                 if ((dc->out->h_size * 10) / dc->out->v_size > 14) {
 835                         avi.m = HDMI_AVI_M_16_9;
 836                         avi.vic = 18;
 837                 } else {
 838                         avi.m = HDMI_AVI_M_16_9;
 839                         avi.vic = 17;
 840                 }
 841         } else if (dc->mode.v_active == 720) {
 842                 avi.m = HDMI_AVI_M_16_9;
 843                 if (dc->mode.h_front_porch == 110)
 844                         avi.vic = 4; /* 60 Hz */
 845                 else
 846                         avi.vic = 19; /* 50 Hz */
 847         } else if (dc->mode.v_active == 720) {
 848                 avi.m = HDMI_AVI_M_16_9;
 849                 if (dc->mode.h_front_porch == 88)
 850                         avi.vic = 16; /* 60 Hz */
 851                 else if (dc->mode.h_front_porch == 528)
 852                         avi.vic = 31; /* 50 Hz */
 853                 else
 854                         avi.vic = 32; /* 24 Hz */
 855         } else {
 856                 avi.m = HDMI_AVI_M_16_9;
 857                 avi.vic = 0;
 858         }
 859
 860
 861         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
 862                                      HDMI_INFOFRAME_TYPE_AVI,
 863                                      HDMI_AVI_VERSION,
 864                                      &avi, sizeof(avi));
 865
 866         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
 867                           HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 868 }
 869
 870 static void tegra_dc_hdmi_setup_audio_infoframe(struct tegra_dc *dc, bool dvi)
 871 {
 872         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 873         struct hdmi_audio_infoframe audio;
 874
 875         if (dvi) {
 876                 tegra_hdmi_writel(hdmi, 0x0,
 877                                   HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 878                 return;
 879         }
 880
 881         memset(&audio, 0x0, sizeof(audio));
 882
 883         audio.cc = HDMI_AUDIO_CC_2;
 884         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
 885                                      HDMI_INFOFRAME_TYPE_AUDIO,
 886                                      HDMI_AUDIO_VERSION,
 887                                      &audio, sizeof(audio));
 888
 889         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
 890                           HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 891 }
 892
 893 static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
 894 {
 895         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 896         int pulse_start;
 897         int dispclk_div_8_2;
 898         int pll0;
 899         int pll1;
 900         int ds;
 901         int retries;
 902         int rekey;
 903         int err;
 904         unsigned long val;
 905
 906         /* enbale power, clocks, resets, etc. */
 907
 908         /* The upstream DC needs to be clocked for accesses to HDMI to not
 909          * hard lock the system.  Because we don't know if HDMI is conencted
 910          * to disp1 or disp2 we need to enable both until we set the DC mux.
 911          */
 912         clk_enable(hdmi->disp1_clk);
 913         clk_enable(hdmi->disp2_clk);
 914         tegra_dc_setup_clk(dc, hdmi->clk);
 915         clk_set_rate(hdmi->clk, dc->mode.pclk);
 916
 917         clk_enable(hdmi->clk);
 918         tegra_periph_reset_assert(hdmi->clk);
 919         mdelay(1);
 920         tegra_periph_reset_deassert(hdmi->clk);
 921
 922         /* TODO: copy HDCP keys from KFUSE to HDMI */
 923
 924         /* Program display timing registers: handled by dc */
 925
 926         /* program HDMI registers and SOR sequencer */
 927
 928         tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
 929         tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
 930                         DC_DISP_DISP_COLOR_CONTROL);
 931
 932         /* video_preamble uses h_pulse2 */
 933         pulse_start = dc->mode.h_ref_to_sync + dc->mode.h_sync_width +
 934                 dc->mode.h_back_porch - 10;
 935         tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
 936         tegra_dc_writel(dc,
 937                         PULSE_MODE_NORMAL |
 938                         PULSE_POLARITY_HIGH |
 939                         PULSE_QUAL_VACTIVE |
 940                         PULSE_LAST_END_A,
 941                         DC_DISP_H_PULSE2_CONTROL);
 942         tegra_dc_writel(dc, PULSE_START(pulse_start) | PULSE_END(pulse_start + 8),
 943                   DC_DISP_H_PULSE2_POSITION_A);
 944
 945         tegra_hdmi_writel(hdmi,
 946                           VSYNC_WINDOW_END(0x210) |
 947                           VSYNC_WINDOW_START(0x200) |
 948                           VSYNC_WINDOW_ENABLE,
 949                           HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
 950
 951         tegra_hdmi_writel(hdmi,
 952                           (dc->ndev->id ? HDMI_SRC_DISPLAYB : HDMI_SRC_DISPLAYA) |
 953                           ARM_VIDEO_RANGE_LIMITED,
 954                           HDMI_NV_PDISP_INPUT_CONTROL);
 955
 956         clk_disable(hdmi->disp1_clk);
 957         clk_disable(hdmi->disp2_clk);
 958
 959         dispclk_div_8_2 = clk_get_rate(hdmi->clk) / 1000000 * 4;
 960         tegra_hdmi_writel(hdmi,
 961                           SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
 962                           SOR_REFCLK_DIV_FRAC(dispclk_div_8_2),
 963                           HDMI_NV_PDISP_SOR_REFCLK);
 964
 965
 966         if (!hdmi->dvi) {
 967                 err = tegra_dc_hdmi_setup_audio(dc);
 968
 969                 if (err < 0)
 970                         hdmi->dvi = true;
 971         }
 972
 973         rekey = HDMI_REKEY_DEFAULT;
 974         val = HDMI_CTRL_REKEY(rekey);
 975         val |= HDMI_CTRL_MAX_AC_PACKET((dc->mode.h_sync_width +
 976                                         dc->mode.h_back_porch +
 977                                         dc->mode.h_front_porch -
 978                                         rekey - 18) / 32);
 979         if (!hdmi->dvi)
 980                 val |= HDMI_CTRL_ENABLE;
 981         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_CTRL);
 982
 983         if (hdmi->dvi)
 984                 tegra_hdmi_writel(hdmi, 0x0,
 985                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 986         else
 987                 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
 988                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 989
 990
 991         tegra_dc_hdmi_setup_avi_infoframe(dc, hdmi->dvi);
 992         tegra_dc_hdmi_setup_audio_infoframe(dc, hdmi->dvi);
 993
 994         /* TMDS CONFIG */
 995         pll0 = 0x200033f;
 996         pll1 = 0;
 997
 998         pll0 &= ~SOR_PLL_PWR & ~SOR_PLL_VCOPD & ~SOR_PLL_PDBG & ~SOR_PLL_PDPORT & ~SOR_PLL_PULLDOWN &
 999                 ~SOR_PLL_VCOCAP(~0) & ~SOR_PLL_ICHPMP(~0);
1000         pll0 |= SOR_PLL_RESISTORSEL;
1001
1002         if (dc->mode.pclk <= 27000000)
1003                 pll0 |= SOR_PLL_VCOCAP(0);
1004         else if (dc->mode.pclk <= 74250000)
1005                 pll0 |= SOR_PLL_VCOCAP(1);
1006         else
1007                 pll0 |= SOR_PLL_VCOCAP(3);
1008
1009         if (dc->mode.h_active == 1080) {
1010                 pll0 |= SOR_PLL_ICHPMP(1) | SOR_PLL_TX_REG_LOAD(3) |
1011                         SOR_PLL_TX_REG_LOAD(3) | SOR_PLL_BG_V17_S(3);
1012                 pll1 |= SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN;
1013         } else {
1014                 pll0 |= SOR_PLL_ICHPMP(2);
1015         }
1016
1017         tegra_hdmi_writel(hdmi, pll0, HDMI_NV_PDISP_SOR_PLL0);
1018         tegra_hdmi_writel(hdmi, pll1, HDMI_NV_PDISP_SOR_PLL1);
1019
1020         if (pll1 & SOR_PLL_PE_EN) {
1021                 tegra_hdmi_writel(hdmi,
1022                                   PE_CURRENT0(0xf) |
1023                                   PE_CURRENT1(0xf) |
1024                                   PE_CURRENT2(0xf) |
1025                                   PE_CURRENT3(0xf),
1026                                   HDMI_NV_PDISP_PE_CURRENT);
1027         }
1028
1029         /* enable SOR */
1030         if (dc->mode.h_active == 1080)
1031                 ds = DRIVE_CURRENT_13_500_mA;
1032         else
1033                 ds = DRIVE_CURRENT_5_250_mA;
1034
1035         tegra_hdmi_writel(hdmi,
1036                           DRIVE_CURRENT_LANE0(ds) |
1037                           DRIVE_CURRENT_LANE1(ds) |
1038                           DRIVE_CURRENT_LANE2(ds) |
1039                           DRIVE_CURRENT_LANE3(ds) |
1040                           DRIVE_CURRENT_FUSE_OVERRIDE,
1041                           HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1042
1043         tegra_hdmi_writel(hdmi,
1044                           SOR_SEQ_CTL_PU_PC(0) |
1045                           SOR_SEQ_PU_PC_ALT(0) |
1046                           SOR_SEQ_PD_PC(8) |
1047                           SOR_SEQ_PD_PC_ALT(8),
1048                           HDMI_NV_PDISP_SOR_SEQ_CTL);
1049
1050         val = SOR_SEQ_INST_WAIT_TIME(1) |
1051                 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1052                 SOR_SEQ_INST_HALT |
1053                 SOR_SEQ_INST_PIN_A_LOW |
1054                 SOR_SEQ_INST_PIN_B_LOW |
1055                 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1056
1057         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST0);
1058         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST8);
1059
1060         val = 0x1c800;
1061         val &= ~SOR_CSTM_ROTCLK(~0);
1062         val |= SOR_CSTM_ROTCLK(2);
1063         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_CSTM);
1064
1065
1066         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1067         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
1068         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1069
1070
1071         /* start SOR */
1072         tegra_hdmi_writel(hdmi,
1073                           SOR_PWR_NORMAL_STATE_PU |
1074                           SOR_PWR_NORMAL_START_NORMAL |
1075                           SOR_PWR_SAFE_STATE_PD |
1076                           SOR_PWR_SETTING_NEW_TRIGGER,
1077                           HDMI_NV_PDISP_SOR_PWR);
1078         tegra_hdmi_writel(hdmi,
1079                           SOR_PWR_NORMAL_STATE_PU |
1080                           SOR_PWR_NORMAL_START_NORMAL |
1081                           SOR_PWR_SAFE_STATE_PD |
1082                           SOR_PWR_SETTING_NEW_DONE,
1083                           HDMI_NV_PDISP_SOR_PWR);
1084
1085         retries = 1000;
1086         do {
1087                 BUG_ON(--retries < 0);
1088                 val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1089         } while (val & SOR_PWR_SETTING_NEW_PENDING);
1090
1091         val = SOR_STATE_ASY_CRCMODE_COMPLETE |
1092                 SOR_STATE_ASY_OWNER_HEAD0 |
1093                 SOR_STATE_ASY_SUBOWNER_BOTH |
1094                 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1095                 SOR_STATE_ASY_DEPOL_POS;
1096
1097         if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1098                 val |= SOR_STATE_ASY_HSYNCPOL_NEG;
1099         else
1100                 val |= SOR_STATE_ASY_HSYNCPOL_POS;
1101
1102         if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1103                 val |= SOR_STATE_ASY_VSYNCPOL_NEG;
1104         else
1105                 val |= SOR_STATE_ASY_VSYNCPOL_POS;
1106
1107         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE2);
1108
1109         val = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1110         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE1);
1111
1112         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1113         tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1114         tegra_hdmi_writel(hdmi, val | SOR_STATE_ATTACHED,
1115                           HDMI_NV_PDISP_SOR_STATE1);
1116         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1117
1118         tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1119
1120         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1121                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1122                         DC_CMD_DISPLAY_POWER_CONTROL);
1123
1124         tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
1125         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
1126         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1127
1128         if (!hdmi->dvi)
1129                 tegra_nvhdcp_set_plug(hdmi->nvhdcp, 1);
1130 }
1131
1132 static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
1133 {
1134         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1135
1136         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
1137
1138         tegra_periph_reset_assert(hdmi->clk);
1139         clk_disable(hdmi->clk);
1140 }
1141
1142 struct tegra_dc_out_ops tegra_dc_hdmi_ops = {
1143         .init = tegra_dc_hdmi_init,
1144         .destroy = tegra_dc_hdmi_destroy,
1145         .enable = tegra_dc_hdmi_enable,
1146         .disable = tegra_dc_hdmi_disable,
1147         .detect = tegra_dc_hdmi_detect,
1148         .suspend = tegra_dc_hdmi_suspend,
1149         .resume = tegra_dc_hdmi_resume,
1150 };
1151