2 * Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
3 * author: chenhengming, chm@rock-chips.com
4 * Alpha Lin, alpha.lin@rock-chips.com
5 * Jung Zhao, jung.zhao@rock-chips.com
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/clk.h>
21 #include <linux/compat.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/reset.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/wakelock.h>
33 #include <linux/cdev.h>
35 #include <linux/of_platform.h>
36 #include <linux/of_irq.h>
37 #include <linux/regmap.h>
38 #include <linux/mfd/syscon.h>
39 #include <linux/uaccess.h>
40 #include <linux/debugfs.h>
41 #include <linux/pm_runtime.h>
42 #include <linux/iopoll.h>
44 #include <linux/rockchip/cru.h>
45 #include <linux/rockchip/pmu.h>
46 #include <linux/rockchip/grf.h>
48 #include <linux/dma-buf.h>
49 #include <linux/rockchip-iovmm.h>
51 #include "vcodec_hw_info.h"
52 #include "vcodec_hw_vpu.h"
53 #include "vcodec_hw_rkv.h"
54 #include "vcodec_hw_vpu2.h"
56 #include "vcodec_service.h"
58 #include "vcodec_iommu_ops.h"
62 * +------+-------------------+
64 * +------+-------------------+
65 * 0~23 bit is for different information type
66 * 24~31 bit is for information print format
69 #define DEBUG_POWER 0x00000001
70 #define DEBUG_CLOCK 0x00000002
71 #define DEBUG_IRQ_STATUS 0x00000004
72 #define DEBUG_IOMMU 0x00000008
73 #define DEBUG_IOCTL 0x00000010
74 #define DEBUG_FUNCTION 0x00000020
75 #define DEBUG_REGISTER 0x00000040
76 #define DEBUG_EXTRA_INFO 0x00000080
77 #define DEBUG_TIMING 0x00000100
78 #define DEBUG_TASK_INFO 0x00000200
80 #define DEBUG_SET_REG 0x00001000
81 #define DEBUG_GET_REG 0x00002000
82 #define DEBUG_PPS_FILL 0x00004000
83 #define DEBUG_IRQ_CHECK 0x00008000
84 #define DEBUG_CACHE_32B 0x00010000
86 #define PRINT_FUNCTION 0x80000000
87 #define PRINT_LINE 0x40000000
89 #define MHZ (1000 * 1000)
90 #define SIZE_REG(reg) ((reg) * 4)
92 #define VCODEC_CLOCK_ENABLE 1
93 #define EXTRA_INFO_MAGIC 0x4C4A46
96 module_param(debug, int, S_IRUGO | S_IWUSR);
97 MODULE_PARM_DESC(debug, "bit switch for vcodec_service debug information");
99 * hardware information organization
101 * In order to support multiple hardware with different version the hardware
102 * information is organized as follow:
104 * 1. First, index hardware by register size / position.
105 * These information is fix for each hardware and do not relate to runtime
106 * work flow. It only related to resource allocation.
107 * Descriptor: struct vpu_hw_info
109 * 2. Then, index hardware by runtime configuration
110 * These information is related to runtime setting behave including enable
111 * register, irq register and other key control flag
112 * Descriptor: struct vpu_task_info
114 * 3. Final, on iommu case the fd translation is required
115 * Descriptor: struct vpu_trans_info
129 struct extra_info_elem {
135 struct extra_info_for_iommu {
138 struct extra_info_elem elem[20];
141 static const struct vcodec_info vcodec_info_set[] = {
143 .hw_id = VPU_ID_8270,
144 .hw_info = &hw_vpu_8270,
145 .task_info = task_vpu,
146 .trans_info = trans_vpu,
149 .hw_id = VPU_ID_4831,
150 .hw_info = &hw_vpu_4831,
151 .task_info = task_vpu,
152 .trans_info = trans_vpu,
155 .hw_id = VPU_DEC_ID_9190,
156 .hw_info = &hw_vpu_9190,
157 .task_info = task_vpu,
158 .trans_info = trans_vpu,
162 .hw_info = &hw_rkhevc,
163 .task_info = task_rkv,
164 .trans_info = trans_rkv,
168 .hw_info = &hw_rkvdec,
169 .task_info = task_rkv,
170 .trans_info = trans_rkv,
175 .task_info = task_vpu2,
176 .trans_info = trans_vpu2,
180 /* Both VPU1 and VPU2 */
181 static const struct vcodec_device_info vpu_device_info = {
182 .device_type = VCODEC_DEVICE_TYPE_VPUX,
183 .name = "vpu-service",
186 static const struct vcodec_device_info vpu_combo_device_info = {
187 .device_type = VCODEC_DEVICE_TYPE_VPUC,
191 static const struct vcodec_device_info hevc_device_info = {
192 .device_type = VCODEC_DEVICE_TYPE_HEVC,
193 .name = "hevc-service",
196 static const struct vcodec_device_info rkvd_device_info = {
197 .device_type = VCODEC_DEVICE_TYPE_RKVD,
203 #define vpu_debug_func(type, fmt, args...) \
205 if (unlikely(debug & type)) { \
206 pr_info("%s:%d: " fmt, \
207 __func__, __LINE__, ##args); \
210 #define vpu_debug(type, fmt, args...) \
212 if (unlikely(debug & type)) { \
213 pr_info(fmt, ##args); \
217 #define vpu_debug_func(level, fmt, args...)
218 #define vpu_debug(level, fmt, args...)
221 #define vpu_debug_enter() vpu_debug_func(DEBUG_FUNCTION, "enter\n")
222 #define vpu_debug_leave() vpu_debug_func(DEBUG_FUNCTION, "leave\n")
224 #define vpu_err(fmt, args...) \
225 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
244 * struct for process session which connect to vpu
246 * @author ChenHengming (2011-5-3)
249 enum VPU_CLIENT_TYPE type;
250 /* a linked list of data so we can access them for debugging */
251 struct list_head list_session;
252 /* a linked list of register data waiting for process */
253 struct list_head waiting;
254 /* a linked list of register data in processing */
255 struct list_head running;
256 /* a linked list of register data processed */
257 struct list_head done;
258 wait_queue_head_t wait;
260 atomic_t task_running;
264 * struct for process register set
266 * @author ChenHengming (2011-5-4)
269 enum VPU_CLIENT_TYPE type;
271 struct vpu_session *session;
272 struct vpu_subdev_data *data;
273 struct vpu_task_info *task;
274 const struct vpu_trans_info *trans;
276 /* link to vpu service session */
277 struct list_head session_link;
278 /* link to register set list */
279 struct list_head status_link;
282 struct list_head mem_region_list;
288 atomic_t irq_count_codec;
289 atomic_t irq_count_pp;
294 enum vcodec_device_id {
295 VCODEC_DEVICE_ID_VPU,
296 VCODEC_DEVICE_ID_HEVC,
297 VCODEC_DEVICE_ID_COMBO,
298 VCODEC_DEVICE_ID_RKVDEC,
299 VCODEC_DEVICE_ID_BUTT
302 enum VCODEC_RUNNING_MODE {
303 VCODEC_RUNNING_MODE_NONE = -1,
304 VCODEC_RUNNING_MODE_VPU,
305 VCODEC_RUNNING_MODE_HEVC,
306 VCODEC_RUNNING_MODE_RKVDEC
309 struct vcodec_mem_region {
310 struct list_head srv_lnk;
311 struct list_head reg_lnk;
312 struct list_head session_lnk;
313 unsigned long iova; /* virtual address for iommu */
320 MMU_ACTIVATED = BIT(0)
323 struct vpu_subdev_data {
327 struct device *child_dev;
331 struct vpu_service_info *pservice;
334 enum VCODEC_RUNNING_MODE mode;
335 struct list_head lnk_service;
339 struct vpu_device enc_dev;
340 struct vpu_device dec_dev;
342 enum VPU_HW_ID hw_id;
343 struct vpu_hw_info *hw_info;
344 struct vpu_task_info *task_info;
345 const struct vpu_trans_info *trans_info;
350 #ifdef CONFIG_DEBUG_FS
351 struct dentry *debugfs_dir;
352 struct dentry *debugfs_file_regs;
355 struct device *mmu_dev;
356 struct vcodec_iommu_info *iommu_info;
357 struct work_struct set_work;
360 struct vpu_service_info {
361 struct wake_lock wake_lock;
362 struct delayed_work power_off_work;
363 struct wake_lock set_wake_lock;
364 struct workqueue_struct *set_workq;
365 ktime_t last; /* record previous power-on time */
366 /* vpu service structure global lock */
368 /* link to link_reg in struct vpu_reg */
369 struct list_head waiting;
370 /* link to link_reg in struct vpu_reg */
371 struct list_head running;
372 /* link to link_reg in struct vpu_reg */
373 struct list_head done;
374 /* link to list_session in struct vpu_session */
375 struct list_head session;
376 atomic_t total_running;
378 atomic_t power_on_cnt;
379 atomic_t power_off_cnt;
381 struct mutex shutdown_lock;
382 struct vpu_reg *reg_codec;
383 struct vpu_reg *reg_pproc;
384 struct vpu_reg *reg_resev;
385 struct vpu_dec_config dec_config;
386 struct vpu_enc_config enc_config;
390 atomic_t freq_status;
392 struct clk *aclk_vcodec;
393 struct clk *hclk_vcodec;
394 struct clk *clk_core;
395 struct clk *clk_cabac;
396 struct clk *pd_video;
398 #ifdef CONFIG_RESET_CONTROLLER
399 struct reset_control *rst_a;
400 struct reset_control *rst_h;
401 struct reset_control *rst_v;
406 atomic_t reset_request;
407 struct list_head mem_region_list;
409 enum vcodec_device_id dev_id;
411 enum VCODEC_RUNNING_MODE curr_mode;
414 struct delayed_work simulate_work;
426 struct list_head subdev_list;
437 struct compat_vpu_request {
443 #define VDPU_SOFT_RESET_REG 101
444 #define VDPU_CLEAN_CACHE_REG 516
445 #define VEPU_CLEAN_CACHE_REG 772
446 #define HEVC_CLEAN_CACHE_REG 260
448 #define VPU_REG_ENABLE(base, reg) writel_relaxed(1, base + reg)
450 #define VDPU_SOFT_RESET(base) VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
451 #define VDPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
452 #define VEPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
453 #define HEVC_CLEAN_CACHE(base) VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
455 #define VPU_POWER_OFF_DELAY (4 * HZ) /* 4s */
456 #define VPU_TIMEOUT_DELAY (2 * HZ) /* 2s */
458 static void *vcodec_get_drv_data(struct platform_device *pdev);
460 static void vpu_service_power_on(struct vpu_subdev_data *data,
461 struct vpu_service_info *pservice);
463 static void time_record(struct vpu_task_info *task, int is_end)
465 if (unlikely(debug & DEBUG_TIMING) && task)
466 do_gettimeofday((is_end) ? (&task->end) : (&task->start));
469 static void time_diff(struct vpu_task_info *task)
471 vpu_debug(DEBUG_TIMING, "%s task: %ld ms\n", task->name,
472 (task->end.tv_sec - task->start.tv_sec) * 1000 +
473 (task->end.tv_usec - task->start.tv_usec) / 1000);
476 static void vcodec_enter_mode(struct vpu_subdev_data *data)
480 struct vpu_service_info *pservice = data->pservice;
481 struct vpu_subdev_data *subdata, *n;
483 if (pservice->subcnt < 2) {
484 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
485 set_bit(MMU_ACTIVATED, &data->state);
487 if (atomic_read(&pservice->enabled)) {
488 if (vcodec_iommu_attach(data->iommu_info))
490 "vcodec service attach failed\n"
494 !atomic_read(&pservice->enabled)
501 if (pservice->curr_mode == data->mode)
504 vpu_debug(DEBUG_IOMMU, "vcodec enter mode %d\n", data->mode);
505 list_for_each_entry_safe(subdata, n,
506 &pservice->subdev_list, lnk_service) {
507 if (data != subdata && subdata->mmu_dev &&
508 test_bit(MMU_ACTIVATED, &subdata->state)) {
509 clear_bit(MMU_ACTIVATED, &subdata->state);
510 vcodec_iommu_detach(subdata->iommu_info);
513 bits = 1 << pservice->mode_bit;
514 #ifdef CONFIG_MFD_SYSCON
516 regmap_read(pservice->grf, pservice->mode_ctrl, &raw);
518 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
519 regmap_write(pservice->grf, pservice->mode_ctrl,
520 raw | bits | (bits << 16));
522 regmap_write(pservice->grf, pservice->mode_ctrl,
523 (raw & (~bits)) | (bits << 16));
524 } else if (pservice->grf_base) {
525 u32 *grf_base = pservice->grf_base;
527 raw = readl_relaxed(grf_base + pservice->mode_ctrl / 4);
528 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
529 writel_relaxed(raw | bits | (bits << 16),
530 grf_base + pservice->mode_ctrl / 4);
532 writel_relaxed((raw & (~bits)) | (bits << 16),
533 grf_base + pservice->mode_ctrl / 4);
535 vpu_err("no grf resource define, switch decoder failed\n");
539 if (pservice->grf_base) {
540 u32 *grf_base = pservice->grf_base;
542 raw = readl_relaxed(grf_base + pservice->mode_ctrl / 4);
543 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
544 writel_relaxed(raw | bits | (bits << 16),
545 grf_base + pservice->mode_ctrl / 4);
547 writel_relaxed((raw & (~bits)) | (bits << 16),
548 grf_base + pservice->mode_ctrl / 4);
550 vpu_err("no grf resource define, switch decoder failed\n");
554 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
555 set_bit(MMU_ACTIVATED, &data->state);
556 if (atomic_read(&pservice->enabled))
557 vcodec_iommu_attach(data->iommu_info);
559 /* FIXME BUG_ON should not be used in mass produce */
560 BUG_ON(!atomic_read(&pservice->enabled));
563 pservice->prev_mode = pservice->curr_mode;
564 pservice->curr_mode = data->mode;
567 static void vcodec_exit_mode(struct vpu_subdev_data *data)
570 * In case of VPU Combo, it require HW switch its running mode
571 * before the other HW component start work. set current HW running
572 * mode to none, can ensure HW switch to its reqired mode properly.
574 data->pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
577 static int vpu_get_clk(struct vpu_service_info *pservice)
579 #if VCODEC_CLOCK_ENABLE
580 struct device *dev = pservice->dev;
582 switch (pservice->dev_id) {
583 case VCODEC_DEVICE_ID_HEVC:
584 pservice->pd_video = devm_clk_get(dev, "pd_hevc");
585 if (IS_ERR(pservice->pd_video)) {
586 pservice->pd_video = NULL;
587 dev_info(dev, "failed on clk_get pd_hevc\n");
589 case VCODEC_DEVICE_ID_COMBO:
590 case VCODEC_DEVICE_ID_RKVDEC:
591 pservice->clk_cabac = devm_clk_get(dev, "clk_cabac");
592 if (IS_ERR(pservice->clk_cabac)) {
593 dev_err(dev, "failed on clk_get clk_cabac\n");
594 pservice->clk_cabac = NULL;
596 pservice->clk_core = devm_clk_get(dev, "clk_core");
597 if (IS_ERR(pservice->clk_core)) {
598 dev_err(dev, "failed on clk_get clk_core\n");
599 pservice->clk_core = NULL;
602 case VCODEC_DEVICE_ID_VPU:
603 pservice->aclk_vcodec = devm_clk_get(dev, "aclk_vcodec");
604 if (IS_ERR(pservice->aclk_vcodec)) {
605 dev_err(dev, "failed on clk_get aclk_vcodec\n");
606 pservice->aclk_vcodec = NULL;
610 pservice->hclk_vcodec = devm_clk_get(dev, "hclk_vcodec");
611 if (IS_ERR(pservice->hclk_vcodec)) {
612 dev_err(dev, "failed on clk_get hclk_vcodec\n");
613 pservice->hclk_vcodec = NULL;
616 if (pservice->pd_video == NULL) {
617 pservice->pd_video = devm_clk_get(dev, "pd_video");
618 if (IS_ERR(pservice->pd_video)) {
619 pservice->pd_video = NULL;
620 dev_info(dev, "do not have pd_video\n");
634 static void _vpu_reset(struct vpu_subdev_data *data)
636 struct vpu_service_info *pservice = data->pservice;
637 enum pmu_idle_req type = IDLE_REQ_VIDEO;
639 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC)
640 type = IDLE_REQ_HEVC;
642 dev_info(pservice->dev, "resetting...\n");
643 WARN_ON(pservice->reg_codec != NULL);
644 WARN_ON(pservice->reg_pproc != NULL);
645 WARN_ON(pservice->reg_resev != NULL);
646 pservice->reg_codec = NULL;
647 pservice->reg_pproc = NULL;
648 pservice->reg_resev = NULL;
650 #ifdef CONFIG_RESET_CONTROLLER
651 dev_info(pservice->dev, "for 3288/3368...");
652 if (of_machine_is_compatible("rockchip,rk3288"))
653 rockchip_pmu_idle_request(pservice->dev, true);
654 if (pservice->rst_a && pservice->rst_h) {
655 dev_info(pservice->dev, "vpu reset in\n");
658 reset_control_assert(pservice->rst_v);
659 reset_control_assert(pservice->rst_a);
660 reset_control_assert(pservice->rst_h);
663 reset_control_deassert(pservice->rst_h);
664 reset_control_deassert(pservice->rst_a);
666 reset_control_deassert(pservice->rst_v);
667 } else if (pservice->rst_v) {
668 dev_info(pservice->dev, "hevc reset in\n");
669 reset_control_assert(pservice->rst_v);
672 reset_control_deassert(pservice->rst_v);
674 if (of_machine_is_compatible("rockchip,rk3288"))
675 rockchip_pmu_idle_request(pservice->dev, false);
679 static void vpu_reset(struct vpu_subdev_data *data)
681 struct vpu_service_info *pservice = data->pservice;
684 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
685 clear_bit(MMU_ACTIVATED, &data->state);
686 if (atomic_read(&pservice->enabled)) {
687 /* Need to reset iommu */
688 vcodec_iommu_detach(data->iommu_info);
690 /* FIXME BUG_ON should not be used in mass produce */
691 BUG_ON(!atomic_read(&pservice->enabled));
695 atomic_set(&pservice->reset_request, 0);
696 dev_info(pservice->dev, "reset done\n");
699 static void reg_deinit(struct vpu_subdev_data *data, struct vpu_reg *reg);
700 static void vpu_service_session_clear(struct vpu_subdev_data *data,
701 struct vpu_session *session)
703 struct vpu_reg *reg, *n;
705 list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
706 reg_deinit(data, reg);
708 list_for_each_entry_safe(reg, n, &session->running, session_link) {
709 reg_deinit(data, reg);
711 list_for_each_entry_safe(reg, n, &session->done, session_link) {
712 reg_deinit(data, reg);
716 static void vpu_service_clear(struct vpu_subdev_data *data)
718 struct vpu_reg *reg, *n;
719 struct vpu_session *session, *s;
720 struct vpu_service_info *pservice = data->pservice;
722 list_for_each_entry_safe(reg, n, &pservice->waiting, status_link) {
723 reg_deinit(reg->data, reg);
726 /* wake up session wait event to prevent the timeout hw reset
727 * during reboot procedure.
729 list_for_each_entry_safe(session, s,
730 &pservice->session, list_session)
731 wake_up(&session->wait);
734 static void vpu_service_dump(struct vpu_service_info *pservice)
739 static void vpu_service_power_off(struct vpu_service_info *pservice)
742 struct vpu_subdev_data *data = NULL, *n;
743 int ret = atomic_add_unless(&pservice->enabled, -1, 0);
748 total_running = atomic_read(&pservice->total_running);
750 pr_alert("alert: power off when %d task running!!\n",
753 pr_alert("alert: delay 50 ms for running task\n");
754 vpu_service_dump(pservice);
757 dev_dbg(pservice->dev, "power off...\n");
761 list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
762 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
763 clear_bit(MMU_ACTIVATED, &data->state);
764 vcodec_iommu_detach(data->iommu_info);
767 pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
768 pm_runtime_put(pservice->dev);
769 #if VCODEC_CLOCK_ENABLE
770 if (pservice->pd_video)
771 clk_disable_unprepare(pservice->pd_video);
772 if (pservice->hclk_vcodec)
773 clk_disable_unprepare(pservice->hclk_vcodec);
774 if (pservice->aclk_vcodec)
775 clk_disable_unprepare(pservice->aclk_vcodec);
776 if (pservice->clk_core)
777 clk_disable_unprepare(pservice->clk_core);
778 if (pservice->clk_cabac)
779 clk_disable_unprepare(pservice->clk_cabac);
782 atomic_add(1, &pservice->power_off_cnt);
783 wake_unlock(&pservice->wake_lock);
784 dev_dbg(pservice->dev, "power off done\n");
787 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
789 queue_delayed_work(system_wq, &pservice->power_off_work,
790 VPU_POWER_OFF_DELAY);
793 static void vpu_power_off_work(struct work_struct *work_s)
795 struct delayed_work *dlwork = container_of(work_s,
796 struct delayed_work, work);
797 struct vpu_service_info *pservice = container_of(dlwork,
798 struct vpu_service_info, power_off_work);
800 if (mutex_trylock(&pservice->lock)) {
801 vpu_service_power_off(pservice);
802 mutex_unlock(&pservice->lock);
804 /* Come back later if the device is busy... */
805 vpu_queue_power_off_work(pservice);
809 static void vpu_service_power_on(struct vpu_subdev_data *data,
810 struct vpu_service_info *pservice)
813 ktime_t now = ktime_get();
815 if (ktime_to_ns(ktime_sub(now, pservice->last)) > NSEC_PER_SEC ||
816 atomic_read(&pservice->power_on_cnt)) {
818 cancel_delayed_work_sync(&pservice->power_off_work);
819 vpu_queue_power_off_work(pservice);
820 pservice->last = now;
822 ret = atomic_add_unless(&pservice->enabled, 1, 1);
826 dev_dbg(pservice->dev, "power on\n");
828 #define BIT_VCODEC_CLK_SEL (1<<10)
829 if (of_machine_is_compatible("rockchip,rk3126"))
830 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1)
831 | BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
832 RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
834 #if VCODEC_CLOCK_ENABLE
835 if (pservice->aclk_vcodec)
836 clk_prepare_enable(pservice->aclk_vcodec);
837 if (pservice->hclk_vcodec)
838 clk_prepare_enable(pservice->hclk_vcodec);
839 if (pservice->clk_core)
840 clk_prepare_enable(pservice->clk_core);
841 if (pservice->clk_cabac)
842 clk_prepare_enable(pservice->clk_cabac);
843 if (pservice->pd_video)
844 clk_prepare_enable(pservice->pd_video);
846 pm_runtime_get_sync(pservice->dev);
849 atomic_add(1, &pservice->power_on_cnt);
850 wake_lock(&pservice->wake_lock);
853 static inline bool reg_check_interlace(struct vpu_reg *reg)
855 u32 type = (reg->reg[3] & (1 << 23));
860 static inline enum VPU_DEC_FMT reg_check_fmt(struct vpu_reg *reg)
862 enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] >> 28) & 0xf);
867 static inline int reg_probe_width(struct vpu_reg *reg)
869 int width_in_mb = reg->reg[4] >> 23;
871 return width_in_mb * 16;
874 static inline int reg_probe_hevc_y_stride(struct vpu_reg *reg)
876 int y_virstride = reg->reg[8];
881 static int vcodec_fd_to_iova(struct vpu_subdev_data *data,
882 struct vpu_session *session,
888 struct vcodec_mem_region *mem_region;
890 hdl = vcodec_iommu_import(data->iommu_info, session, fd);
894 mem_region = kzalloc(sizeof(*mem_region), GFP_KERNEL);
895 if (mem_region == NULL) {
896 vpu_err("allocate memory for iommu memory region failed\n");
897 vcodec_iommu_free(data->iommu_info, session, hdl);
901 mem_region->hdl = hdl;
902 ret = vcodec_iommu_map_iommu(data->iommu_info, session, mem_region->hdl,
903 &mem_region->iova, &mem_region->len);
905 vpu_err("fd %d ion map iommu failed\n", fd);
907 vcodec_iommu_free(data->iommu_info, session, hdl);
911 INIT_LIST_HEAD(&mem_region->reg_lnk);
912 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
913 return mem_region->iova;
917 * NOTE: rkvdec/rkhevc put scaling list address in pps buffer hardware will read
918 * it by pps id in video stream data.
920 * So we need to translate the address in iommu case. The address data is also
921 * 10bit fd + 22bit offset mode.
922 * Because userspace decoder do not give the pps id in the register file sets
923 * kernel driver need to translate each scaling list address in pps buffer which
924 * means 256 pps for H.264, 64 pps for H.265.
926 * In order to optimize the performance kernel driver ask userspace decoder to
927 * set all scaling list address in pps buffer to the same one which will be used
928 * on current decoding task. Then kernel driver can only translate the first
929 * address then copy it all pps buffer.
931 static int fill_scaling_list_addr_in_pps(
932 struct vpu_subdev_data *data,
937 int scaling_list_addr_offset)
939 int base = scaling_list_addr_offset;
943 scaling_offset = (u32)pps[base + 0];
944 scaling_offset += (u32)pps[base + 1] << 8;
945 scaling_offset += (u32)pps[base + 2] << 16;
946 scaling_offset += (u32)pps[base + 3] << 24;
948 scaling_fd = scaling_offset & 0x3ff;
949 scaling_offset = scaling_offset >> 10;
951 if (scaling_fd > 0) {
953 u32 tmp = vcodec_fd_to_iova(data, reg->session, reg,
956 if (IS_ERR_VALUE(tmp))
958 tmp += scaling_offset;
960 for (i = 0; i < pps_info_count; i++, base += pps_info_size) {
961 pps[base + 0] = (tmp >> 0) & 0xff;
962 pps[base + 1] = (tmp >> 8) & 0xff;
963 pps[base + 2] = (tmp >> 16) & 0xff;
964 pps[base + 3] = (tmp >> 24) & 0xff;
971 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data,
972 struct vpu_session *session,
974 int size, struct vpu_reg *reg,
975 struct extra_info_for_iommu *ext_inf)
977 struct vpu_service_info *pservice = data->pservice;
978 struct vpu_task_info *task = reg->task;
979 enum FORMAT_TYPE type;
982 struct vcodec_mem_region *mem_region;
986 if (tbl == NULL || size <= 0) {
987 dev_err(pservice->dev, "input arguments invalidate\n");
992 type = task->get_fmt(reg->reg);
994 dev_err(pservice->dev, "invalid task with NULL get_fmt\n");
998 for (i = 0; i < size; i++) {
999 int usr_fd = reg->reg[tbl[i]] & 0x3FF;
1001 /* if userspace do not set the fd at this register, skip */
1006 * for avoiding cache sync issue, we need to map/unmap
1007 * input buffer every time. FIX ME, if it is unnecessary
1009 if (task->reg_rlc == tbl[i])
1010 vcodec_iommu_free_fd(data->iommu_info, session, usr_fd);
1012 * special offset scale case
1014 * This translation is for fd + offset translation.
1015 * One register has 32bits. We need to transfer both buffer file
1016 * handle and the start address offset so we packet file handle
1017 * and offset together using below format.
1019 * 0~9 bit for buffer file handle range 0 ~ 1023
1020 * 10~31 bit for offset range 0 ~ 4M
1022 * But on 4K case the offset can be larger the 4M
1023 * So on H.264 4K vpu/vpu2 decoder we scale the offset by 16
1024 * But MPEG4 will use the same register for colmv and it do not
1027 * RKVdec do not have this issue.
1029 if ((type == FMT_H264D || type == FMT_VP9D) &&
1030 task->reg_dir_mv > 0 && task->reg_dir_mv == tbl[i])
1031 offset = reg->reg[tbl[i]] >> 10 << 4;
1033 offset = reg->reg[tbl[i]] >> 10;
1035 vpu_debug(DEBUG_IOMMU, "pos %3d fd %3d offset %10d i %d\n",
1036 tbl[i], usr_fd, offset, i);
1038 hdl = vcodec_iommu_import(data->iommu_info, session, usr_fd);
1040 if (task->reg_pps > 0 && task->reg_pps == tbl[i]) {
1041 int pps_info_offset;
1044 int scaling_list_addr_offset;
1048 pps_info_offset = offset;
1049 pps_info_count = 256;
1051 scaling_list_addr_offset = 23;
1054 pps_info_offset = 0;
1055 pps_info_count = 64;
1057 scaling_list_addr_offset = 74;
1060 pps_info_offset = 0;
1063 scaling_list_addr_offset = 0;
1067 vpu_debug(DEBUG_PPS_FILL,
1068 "scaling list filling parameter:\n");
1069 vpu_debug(DEBUG_PPS_FILL,
1070 "pps_info_offset %d\n", pps_info_offset);
1071 vpu_debug(DEBUG_PPS_FILL,
1072 "pps_info_count %d\n", pps_info_count);
1073 vpu_debug(DEBUG_PPS_FILL,
1074 "pps_info_size %d\n", pps_info_size);
1075 vpu_debug(DEBUG_PPS_FILL,
1076 "scaling_list_addr_offset %d\n",
1077 scaling_list_addr_offset);
1079 if (pps_info_count) {
1082 pps = vcodec_iommu_map_kernel
1083 (data->iommu_info, session, hdl);
1085 vpu_debug(DEBUG_PPS_FILL,
1086 "scaling list setting pps %p\n", pps);
1087 pps += pps_info_offset;
1089 fill_scaling_list_addr_in_pps
1090 (data, reg, pps, pps_info_count,
1092 scaling_list_addr_offset);
1094 vcodec_iommu_unmap_kernel
1095 (data->iommu_info, session, hdl);
1099 mem_region = kzalloc(sizeof(*mem_region), GFP_KERNEL);
1102 vcodec_iommu_free(data->iommu_info, session, hdl);
1106 mem_region->hdl = hdl;
1107 mem_region->reg_idx = tbl[i];
1109 ret = vcodec_iommu_map_iommu(data->iommu_info, session,
1110 mem_region->hdl, &mem_region->iova,
1113 dev_err(pservice->dev,
1114 "reg %d fd %d ion map iommu failed\n",
1117 vcodec_iommu_free(data->iommu_info, session, hdl);
1122 * special for vpu dec num 12: record decoded length
1123 * hacking for decoded length
1124 * NOTE: not a perfect fix, the fd is not recorded
1126 if (task->reg_len > 0 && task->reg_len == tbl[i]) {
1127 reg->dec_base = mem_region->iova + offset;
1128 vpu_debug(DEBUG_REGISTER, "dec_set %08x\n",
1132 reg->reg[tbl[i]] = mem_region->iova + offset;
1133 INIT_LIST_HEAD(&mem_region->reg_lnk);
1134 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
1137 if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
1138 for (i = 0; i < ext_inf->cnt; i++) {
1139 vpu_debug(DEBUG_IOMMU, "reg[%d] + offset %d\n",
1140 ext_inf->elem[i].index,
1141 ext_inf->elem[i].offset);
1142 reg->reg[ext_inf->elem[i].index] +=
1143 ext_inf->elem[i].offset;
1150 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
1151 struct vpu_session *session,
1152 struct vpu_reg *reg,
1153 struct extra_info_for_iommu *ext_inf)
1155 struct vpu_service_info *pservice = data->pservice;
1156 enum FORMAT_TYPE type = reg->task->get_fmt(reg->reg);
1158 if (type < FMT_TYPE_BUTT) {
1159 const struct vpu_trans_info *info = ®->trans[type];
1160 const u8 *tbl = info->table;
1161 int size = info->count;
1163 return vcodec_bufid_to_iova(data, session, tbl, size, reg,
1167 dev_err(pservice->dev, "found invalid format type!\n");
1171 static void get_reg_freq(struct vpu_subdev_data *data, struct vpu_reg *reg)
1174 if (!of_machine_is_compatible("rockchip,rk2928g")) {
1175 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1176 if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1177 if (reg_probe_width(reg) > 3200) {
1178 /*raise frequency for 4k avc.*/
1179 reg->freq = VPU_FREQ_600M;
1182 if (reg_check_interlace(reg))
1183 reg->freq = VPU_FREQ_400M;
1186 if (data->hw_id == HEVC_ID) {
1187 if (reg_probe_hevc_y_stride(reg) > 60000)
1188 reg->freq = VPU_FREQ_400M;
1190 if (reg->type == VPU_PP)
1191 reg->freq = VPU_FREQ_400M;
1195 static struct vpu_reg *reg_init(struct vpu_subdev_data *data,
1196 struct vpu_session *session,
1197 void __user *src, u32 size)
1199 struct vpu_service_info *pservice = data->pservice;
1201 struct extra_info_for_iommu extra_info;
1202 struct vpu_reg *reg = kzalloc(sizeof(*reg) + data->reg_size,
1208 vpu_err("error: kzalloc failed\n");
1212 if (size > data->reg_size) {
1213 extra_size = size - data->reg_size;
1214 size = data->reg_size;
1216 reg->session = session;
1218 reg->type = session->type;
1220 reg->freq = VPU_FREQ_DEFAULT;
1221 reg->task = &data->task_info[session->type];
1222 reg->trans = data->trans_info;
1223 reg->reg = (u32 *)®[1];
1224 INIT_LIST_HEAD(®->session_link);
1225 INIT_LIST_HEAD(®->status_link);
1227 INIT_LIST_HEAD(®->mem_region_list);
1229 if (copy_from_user(®->reg[0], (void __user *)src, size)) {
1230 vpu_err("error: copy_from_user failed\n");
1235 if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1236 vpu_err("error: copy_from_user failed\n");
1241 if (vcodec_reg_address_translate(data, session, reg, &extra_info) < 0) {
1244 vpu_err("error: translate reg address failed, dumping regs\n");
1245 for (i = 0; i < size >> 2; i++)
1246 dev_err(pservice->dev, "reg[%02d]: %08x\n",
1247 i, *((u32 *)src + i));
1253 mutex_lock(&pservice->lock);
1254 list_add_tail(®->status_link, &pservice->waiting);
1255 list_add_tail(®->session_link, &session->waiting);
1256 mutex_unlock(&pservice->lock);
1258 if (pservice->auto_freq)
1259 get_reg_freq(data, reg);
1266 static void reg_deinit(struct vpu_subdev_data *data, struct vpu_reg *reg)
1268 struct vpu_service_info *pservice = data->pservice;
1269 struct vcodec_mem_region *mem_region = NULL, *n;
1271 list_del_init(®->session_link);
1272 list_del_init(®->status_link);
1273 if (reg == pservice->reg_codec)
1274 pservice->reg_codec = NULL;
1275 if (reg == pservice->reg_pproc)
1276 pservice->reg_pproc = NULL;
1278 /* release memory region attach to this registers table. */
1279 list_for_each_entry_safe(mem_region, n,
1280 ®->mem_region_list, reg_lnk) {
1281 vcodec_iommu_unmap_iommu(data->iommu_info, reg->session,
1283 vcodec_iommu_free(data->iommu_info, reg->session,
1285 list_del_init(&mem_region->reg_lnk);
1292 static void reg_from_wait_to_run(struct vpu_service_info *pservice,
1293 struct vpu_reg *reg)
1296 list_del_init(®->status_link);
1297 list_add_tail(®->status_link, &pservice->running);
1299 list_del_init(®->session_link);
1300 list_add_tail(®->session_link, ®->session->running);
1304 static void reg_copy_from_hw(struct vpu_reg *reg, u32 *src, u32 count)
1307 u32 *dst = reg->reg;
1310 for (i = 0; i < count; i++, src++)
1311 *dst++ = readl_relaxed(src);
1313 dst = (u32 *)®->reg[0];
1314 for (i = 0; i < count; i++)
1315 vpu_debug(DEBUG_GET_REG, "get reg[%02d] %08x\n", i, dst[i]);
1320 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1321 struct vpu_reg *reg)
1323 struct vpu_service_info *pservice = data->pservice;
1324 struct vpu_hw_info *hw_info = data->hw_info;
1325 struct vpu_task_info *task = reg->task;
1329 list_del_init(®->status_link);
1330 list_add_tail(®->status_link, &pservice->done);
1332 list_del_init(®->session_link);
1333 list_add_tail(®->session_link, ®->session->done);
1335 switch (reg->type) {
1337 pservice->reg_codec = NULL;
1338 reg_copy_from_hw(reg, data->enc_dev.regs, hw_info->enc_reg_num);
1339 reg->reg[task->reg_irq] = pservice->irq_status;
1342 pservice->reg_codec = NULL;
1343 reg_copy_from_hw(reg, data->dec_dev.regs, hw_info->dec_reg_num);
1345 /* revert hack for decoded length */
1346 if (task->reg_len > 0) {
1347 int reg_len = task->reg_len;
1348 u32 dec_get = reg->reg[reg_len];
1349 s32 dec_length = dec_get - reg->dec_base;
1351 vpu_debug(DEBUG_REGISTER,
1352 "dec_get %08x dec_length %d\n",
1353 dec_get, dec_length);
1354 reg->reg[reg_len] = dec_length << 10;
1357 reg->reg[task->reg_irq] = pservice->irq_status;
1360 pservice->reg_pproc = NULL;
1361 reg_copy_from_hw(reg, data->dec_dev.regs, hw_info->dec_reg_num);
1362 writel_relaxed(0, data->dec_dev.regs + task->reg_irq);
1366 u32 *regs = data->dec_dev.regs;
1368 pservice->reg_codec = NULL;
1369 pservice->reg_pproc = NULL;
1371 reg_copy_from_hw(reg, data->dec_dev.regs, hw_info->dec_reg_num);
1373 /* NOTE: remove pp pipeline mode flag first */
1374 pipe_mode = readl_relaxed(regs + task->reg_pipe);
1375 pipe_mode &= ~task->pipe_mask;
1376 writel_relaxed(pipe_mode, regs + task->reg_pipe);
1378 /* revert hack for decoded length */
1379 if (task->reg_len > 0) {
1380 int reg_len = task->reg_len;
1381 u32 dec_get = reg->reg[reg_len];
1382 s32 dec_length = dec_get - reg->dec_base;
1384 vpu_debug(DEBUG_REGISTER,
1385 "dec_get %08x dec_length %d\n",
1386 dec_get, dec_length);
1387 reg->reg[reg_len] = dec_length << 10;
1390 reg->reg[task->reg_irq] = pservice->irq_status;
1393 vpu_err("error: copy reg from hw with unknown type %d\n",
1397 vcodec_exit_mode(data);
1399 atomic_sub(1, ®->session->task_running);
1400 atomic_sub(1, &pservice->total_running);
1401 wake_up(®->session->wait);
1406 static void vpu_service_set_freq(struct vpu_service_info *pservice,
1407 struct vpu_reg *reg)
1409 enum VPU_FREQ curr = atomic_read(&pservice->freq_status);
1411 if (curr == reg->freq)
1414 atomic_set(&pservice->freq_status, reg->freq);
1415 switch (reg->freq) {
1416 case VPU_FREQ_200M: {
1417 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1419 case VPU_FREQ_266M: {
1420 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1422 case VPU_FREQ_300M: {
1423 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1425 case VPU_FREQ_400M: {
1426 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1428 case VPU_FREQ_500M: {
1429 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1431 case VPU_FREQ_600M: {
1432 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1435 unsigned long rate = 300*MHZ;
1437 if (of_machine_is_compatible("rockchip,rk2928g"))
1440 clk_set_rate(pservice->aclk_vcodec, rate);
1445 static void reg_copy_to_hw(struct vpu_subdev_data *data, struct vpu_reg *reg)
1447 struct vpu_service_info *pservice = data->pservice;
1448 struct vpu_task_info *task = reg->task;
1449 struct vpu_hw_info *hw_info = data->hw_info;
1451 u32 *src = (u32 *)®->reg[0];
1452 u32 enable_mask = task->enable_mask;
1453 u32 gating_mask = task->gating_mask;
1454 u32 reg_en = task->reg_en;
1458 atomic_add(1, &pservice->total_running);
1459 atomic_add(1, ®->session->task_running);
1461 if (pservice->auto_freq)
1462 vpu_service_set_freq(pservice, reg);
1464 vcodec_enter_mode(data);
1466 switch (reg->type) {
1468 u32 *dst = data->enc_dev.regs;
1470 u32 end = hw_info->enc_reg_num;
1471 /* u32 reg_gating = task->reg_gating; */
1473 pservice->reg_codec = reg;
1475 vpu_debug(DEBUG_TASK_INFO,
1476 "reg: base %3d end %d en %2d mask: en %x gate %x\n",
1477 base, end, reg_en, enable_mask, gating_mask);
1479 VEPU_CLEAN_CACHE(dst);
1481 if (debug & DEBUG_SET_REG)
1482 for (i = base; i < end; i++)
1483 vpu_debug(DEBUG_SET_REG, "set reg[%02d] %08x\n",
1487 * NOTE: encoder need to setup mode first
1489 writel_relaxed(src[reg_en] & enable_mask, dst + reg_en);
1491 /* NOTE: encoder gating is not on enable register */
1492 /* src[reg_gating] |= gating_mask; */
1494 for (i = base; i < end; i++) {
1496 writel_relaxed(src[i], dst + i);
1499 writel(src[reg_en], dst + reg_en);
1502 time_record(reg->task, 0);
1505 u32 *dst = data->dec_dev.regs;
1506 u32 len = hw_info->dec_reg_num;
1507 u32 base = hw_info->base_dec;
1508 u32 end = hw_info->end_dec;
1510 pservice->reg_codec = reg;
1512 vpu_debug(DEBUG_TASK_INFO,
1513 "reg: base %3d end %d en %2d mask: en %x gate %x\n",
1514 base, end, reg_en, enable_mask, gating_mask);
1516 VDPU_CLEAN_CACHE(dst);
1518 /* on rkvdec set cache size to 64byte */
1519 if (pservice->dev_id == VCODEC_DEVICE_ID_RKVDEC) {
1520 u32 *cache_base = dst + 0x100;
1521 u32 val = (debug & DEBUG_CACHE_32B) ? (0x3) : (0x13);
1522 writel_relaxed(val, cache_base + 0x07);
1523 writel_relaxed(val, cache_base + 0x17);
1526 if (debug & DEBUG_SET_REG)
1527 for (i = 0; i < len; i++)
1528 vpu_debug(DEBUG_SET_REG, "set reg[%02d] %08x\n",
1531 * NOTE: The end register is invalid. Do NOT write to it
1532 * Also the base register must be written
1534 for (i = base; i < end; i++) {
1536 writel_relaxed(src[i], dst + i);
1539 writel(src[reg_en] | gating_mask, dst + reg_en);
1542 time_record(reg->task, 0);
1545 u32 *dst = data->dec_dev.regs;
1546 u32 base = hw_info->base_pp;
1547 u32 end = hw_info->end_pp;
1549 pservice->reg_pproc = reg;
1551 vpu_debug(DEBUG_TASK_INFO,
1552 "reg: base %3d end %d en %2d mask: en %x gate %x\n",
1553 base, end, reg_en, enable_mask, gating_mask);
1555 if (debug & DEBUG_SET_REG)
1556 for (i = base; i < end; i++)
1557 vpu_debug(DEBUG_SET_REG, "set reg[%02d] %08x\n",
1560 for (i = base; i < end; i++) {
1562 writel_relaxed(src[i], dst + i);
1565 writel(src[reg_en] | gating_mask, dst + reg_en);
1568 time_record(reg->task, 0);
1571 u32 *dst = data->dec_dev.regs;
1572 u32 base = hw_info->base_dec_pp;
1573 u32 end = hw_info->end_dec_pp;
1575 pservice->reg_codec = reg;
1576 pservice->reg_pproc = reg;
1578 vpu_debug(DEBUG_TASK_INFO,
1579 "reg: base %3d end %d en %2d mask: en %x gate %x\n",
1580 base, end, reg_en, enable_mask, gating_mask);
1582 /* VDPU_SOFT_RESET(dst); */
1583 VDPU_CLEAN_CACHE(dst);
1585 if (debug & DEBUG_SET_REG)
1586 for (i = base; i < end; i++)
1587 vpu_debug(DEBUG_SET_REG, "set reg[%02d] %08x\n",
1590 for (i = base; i < end; i++) {
1592 writel_relaxed(src[i], dst + i);
1595 /* NOTE: dec output must be disabled */
1597 writel(src[reg_en] | gating_mask, dst + reg_en);
1600 time_record(reg->task, 0);
1603 vpu_err("error: unsupport session type %d", reg->type);
1604 atomic_sub(1, &pservice->total_running);
1605 atomic_sub(1, ®->session->task_running);
1612 static void try_set_reg(struct vpu_subdev_data *data)
1614 struct vpu_service_info *pservice = data->pservice;
1618 mutex_lock(&pservice->shutdown_lock);
1619 if (atomic_read(&pservice->service_on) == 0) {
1620 mutex_unlock(&pservice->shutdown_lock);
1623 if (!list_empty(&pservice->waiting)) {
1624 struct vpu_reg *reg_codec = pservice->reg_codec;
1625 struct vpu_reg *reg_pproc = pservice->reg_pproc;
1627 bool change_able = (reg_codec == NULL) && (reg_pproc == NULL);
1628 int reset_request = atomic_read(&pservice->reset_request);
1629 struct vpu_reg *reg = list_entry(pservice->waiting.next,
1630 struct vpu_reg, status_link);
1632 vpu_service_power_on(data, pservice);
1634 if (change_able || !reset_request) {
1635 switch (reg->type) {
1641 if (reg_codec == NULL)
1643 if (pservice->auto_freq && (reg_pproc != NULL))
1647 if (reg_codec == NULL) {
1648 if (reg_pproc == NULL)
1651 if ((reg_codec->type == VPU_DEC) &&
1652 (reg_pproc == NULL))
1657 * can not charge frequency
1658 * when vpu is working
1660 if (pservice->auto_freq)
1669 dev_err(pservice->dev,
1670 "undefined reg type %d\n",
1676 /* then check reset request */
1677 if (reset_request && !change_able)
1680 /* do reset before setting registers */
1685 reg_from_wait_to_run(pservice, reg);
1686 reg_copy_to_hw(reg->data, reg);
1690 mutex_unlock(&pservice->shutdown_lock);
1694 static void vpu_set_register_work(struct work_struct *work_s)
1696 struct vpu_subdev_data *data = container_of(work_s,
1697 struct vpu_subdev_data,
1699 struct vpu_service_info *pservice = data->pservice;
1701 mutex_lock(&pservice->lock);
1703 mutex_unlock(&pservice->lock);
1706 static int return_reg(struct vpu_subdev_data *data,
1707 struct vpu_reg *reg, u32 __user *dst)
1709 struct vpu_hw_info *hw_info = data->hw_info;
1710 size_t size = reg->size;
1714 switch (reg->type) {
1719 base = hw_info->base_dec_pp;
1722 base = hw_info->base_pp;
1725 base = hw_info->base_dec_pp;
1728 vpu_err("error: copy reg to user with unknown type %d\n",
1734 if (copy_to_user(dst, ®->reg[base], size)) {
1735 vpu_err("error: copy_to_user failed\n");
1739 reg_deinit(data, reg);
1744 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1747 struct vpu_subdev_data *data =
1748 container_of(filp->f_path.dentry->d_inode->i_cdev,
1749 struct vpu_subdev_data, cdev);
1750 struct vpu_service_info *pservice = data->pservice;
1751 struct vpu_session *session = (struct vpu_session *)filp->private_data;
1754 if (NULL == session)
1758 case VPU_IOC_SET_CLIENT_TYPE: {
1759 session->type = (enum VPU_CLIENT_TYPE)arg;
1760 vpu_debug(DEBUG_IOCTL, "pid %d set client type %d\n",
1761 session->pid, session->type);
1763 case VPU_IOC_GET_HW_FUSE_STATUS: {
1764 struct vpu_request req;
1766 vpu_debug(DEBUG_IOCTL, "pid %d get hw status %d\n",
1767 session->pid, session->type);
1768 if (copy_from_user(&req, (void __user *)arg, sizeof(req))) {
1769 vpu_err("error: get hw status copy_from_user failed\n");
1772 void *config = (session->type != VPU_ENC) ?
1773 ((void *)&pservice->dec_config) :
1774 ((void *)&pservice->enc_config);
1775 size_t size = (session->type != VPU_ENC) ?
1776 (sizeof(struct vpu_dec_config)) :
1777 (sizeof(struct vpu_enc_config));
1778 if (copy_to_user((void __user *)req.req,
1780 vpu_err("error: get hw status copy_to_user failed type %d\n",
1786 case VPU_IOC_SET_REG: {
1787 struct vpu_request req;
1788 struct vpu_reg *reg;
1790 vpu_debug(DEBUG_IOCTL, "pid %d set reg type %d\n",
1791 session->pid, session->type);
1792 if (copy_from_user(&req, (void __user *)arg,
1793 sizeof(struct vpu_request))) {
1794 vpu_err("error: set reg copy_from_user failed\n");
1798 reg = reg_init(data, session, (void __user *)req.req, req.size);
1802 queue_work(pservice->set_workq, &data->set_work);
1805 case VPU_IOC_GET_REG: {
1806 struct vpu_request req;
1807 struct vpu_reg *reg;
1810 vpu_debug(DEBUG_IOCTL, "pid %d get reg type %d\n",
1811 session->pid, session->type);
1812 if (copy_from_user(&req, (void __user *)arg,
1813 sizeof(struct vpu_request))) {
1814 vpu_err("error: get reg copy_from_user failed\n");
1818 ret = wait_event_timeout(session->wait,
1819 !list_empty(&session->done),
1822 if (!list_empty(&session->done)) {
1824 vpu_err("warning: pid %d wait task error ret %d\n",
1828 if (unlikely(ret < 0)) {
1829 vpu_err("error: pid %d wait task ret %d\n",
1831 } else if (ret == 0) {
1832 vpu_err("error: pid %d wait %d task done timeout\n",
1834 atomic_read(&session->task_running));
1840 int task_running = atomic_read(&session->task_running);
1842 mutex_lock(&pservice->lock);
1843 vpu_service_dump(pservice);
1845 atomic_set(&session->task_running, 0);
1846 atomic_sub(task_running,
1847 &pservice->total_running);
1848 dev_err(pservice->dev,
1849 "%d task is running but not return, reset hardware...",
1852 dev_err(pservice->dev, "done\n");
1854 vpu_service_session_clear(data, session);
1855 mutex_unlock(&pservice->lock);
1859 mutex_lock(&pservice->lock);
1860 reg = list_entry(session->done.next,
1861 struct vpu_reg, session_link);
1862 return_reg(data, reg, (u32 __user *)req.req);
1863 mutex_unlock(&pservice->lock);
1865 case VPU_IOC_PROBE_IOMMU_STATUS: {
1866 int iommu_enable = 1;
1868 vpu_debug(DEBUG_IOCTL, "VPU_IOC_PROBE_IOMMU_STATUS\n");
1870 if (copy_to_user((void __user *)arg,
1871 &iommu_enable, sizeof(int))) {
1872 vpu_err("error: iommu status copy_to_user failed\n");
1877 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1884 #ifdef CONFIG_COMPAT
1885 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1888 struct vpu_subdev_data *data =
1889 container_of(filp->f_path.dentry->d_inode->i_cdev,
1890 struct vpu_subdev_data, cdev);
1891 struct vpu_service_info *pservice = data->pservice;
1892 struct vpu_session *session = (struct vpu_session *)filp->private_data;
1895 vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1896 (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1897 if (NULL == session)
1901 case COMPAT_VPU_IOC_SET_CLIENT_TYPE: {
1902 session->type = (enum VPU_CLIENT_TYPE)arg;
1903 vpu_debug(DEBUG_IOCTL, "compat set client type %d\n",
1906 case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS: {
1907 struct compat_vpu_request req;
1909 vpu_debug(DEBUG_IOCTL, "compat get hw status %d\n",
1911 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1912 sizeof(struct compat_vpu_request))) {
1913 vpu_err("error: compat get hw status copy_from_user failed\n");
1916 void *config = (session->type != VPU_ENC) ?
1917 ((void *)&pservice->dec_config) :
1918 ((void *)&pservice->enc_config);
1919 size_t size = (session->type != VPU_ENC) ?
1920 (sizeof(struct vpu_dec_config)) :
1921 (sizeof(struct vpu_enc_config));
1923 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1925 vpu_err("error: compat get hw status copy_to_user failed type %d\n",
1931 case COMPAT_VPU_IOC_SET_REG: {
1932 struct compat_vpu_request req;
1933 struct vpu_reg *reg;
1935 vpu_debug(DEBUG_IOCTL, "compat set reg type %d\n",
1937 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1938 sizeof(struct compat_vpu_request))) {
1939 vpu_err("compat set_reg copy_from_user failed\n");
1942 reg = reg_init(data, session,
1943 compat_ptr((compat_uptr_t)req.req), req.size);
1947 queue_work(pservice->set_workq, &data->set_work);
1950 case COMPAT_VPU_IOC_GET_REG: {
1951 struct compat_vpu_request req;
1952 struct vpu_reg *reg;
1955 vpu_debug(DEBUG_IOCTL, "compat get reg type %d\n",
1957 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1958 sizeof(struct compat_vpu_request))) {
1959 vpu_err("compat get reg copy_from_user failed\n");
1963 ret = wait_event_timeout(session->wait,
1964 !list_empty(&session->done),
1967 if (!list_empty(&session->done)) {
1969 vpu_err("warning: pid %d wait task error ret %d\n",
1973 if (unlikely(ret < 0)) {
1974 vpu_err("error: pid %d wait task ret %d\n",
1976 } else if (ret == 0) {
1977 vpu_err("error: pid %d wait %d task done timeout\n",
1979 atomic_read(&session->task_running));
1985 int task_running = atomic_read(&session->task_running);
1987 mutex_lock(&pservice->lock);
1988 vpu_service_dump(pservice);
1990 atomic_set(&session->task_running, 0);
1991 atomic_sub(task_running,
1992 &pservice->total_running);
1993 dev_err(pservice->dev,
1994 "%d task is running but not return, reset hardware...",
1997 dev_err(pservice->dev, "done\n");
1999 vpu_service_session_clear(data, session);
2000 mutex_unlock(&pservice->lock);
2004 mutex_lock(&pservice->lock);
2005 reg = list_entry(session->done.next,
2006 struct vpu_reg, session_link);
2007 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
2008 mutex_unlock(&pservice->lock);
2010 case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS: {
2011 int iommu_enable = 1;
2013 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_PROBE_IOMMU_STATUS\n");
2015 if (copy_to_user(compat_ptr((compat_uptr_t)arg),
2016 &iommu_enable, sizeof(int))) {
2017 vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
2022 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
2030 static int vpu_service_check_hw(struct vpu_subdev_data *data)
2032 struct vpu_service_info *pservice = data->pservice;
2033 int ret = -EINVAL, i = 0;
2034 u32 hw_id = readl_relaxed(data->regs);
2036 hw_id = (hw_id >> 16) & 0xFFFF;
2037 dev_info(pservice->dev, "checking hw id %x\n", hw_id);
2038 data->hw_info = NULL;
2040 for (i = 0; i < ARRAY_SIZE(vcodec_info_set); i++) {
2041 const struct vcodec_info *info = &vcodec_info_set[i];
2043 if (hw_id == info->hw_id) {
2044 data->hw_id = info->hw_id;
2045 data->hw_info = info->hw_info;
2046 data->task_info = info->task_info;
2047 data->trans_info = info->trans_info;
2055 static int vpu_service_open(struct inode *inode, struct file *filp)
2057 struct vpu_subdev_data *data = container_of(
2058 inode->i_cdev, struct vpu_subdev_data, cdev);
2059 struct vpu_service_info *pservice = data->pservice;
2060 struct vpu_session *session = NULL;
2064 session = kzalloc(sizeof(*session), GFP_KERNEL);
2066 vpu_err("error: unable to allocate memory for vpu_session.");
2070 data->iommu_info->debug_level = debug;
2072 session->type = VPU_TYPE_BUTT;
2073 session->pid = current->pid;
2074 INIT_LIST_HEAD(&session->waiting);
2075 INIT_LIST_HEAD(&session->running);
2076 INIT_LIST_HEAD(&session->done);
2077 INIT_LIST_HEAD(&session->list_session);
2078 init_waitqueue_head(&session->wait);
2079 atomic_set(&session->task_running, 0);
2080 mutex_lock(&pservice->lock);
2081 list_add_tail(&session->list_session, &pservice->session);
2082 filp->private_data = (void *)session;
2083 mutex_unlock(&pservice->lock);
2085 dev_dbg(pservice->dev, "dev opened\n");
2087 return nonseekable_open(inode, filp);
2090 static int vpu_service_release(struct inode *inode, struct file *filp)
2092 struct vpu_subdev_data *data = container_of(
2093 inode->i_cdev, struct vpu_subdev_data, cdev);
2094 struct vpu_service_info *pservice = data->pservice;
2096 struct vpu_session *session = (struct vpu_session *)filp->private_data;
2099 if (NULL == session)
2102 task_running = atomic_read(&session->task_running);
2104 dev_err(pservice->dev,
2105 "error: session %d still has %d task running when closing\n",
2106 session->pid, task_running);
2109 wake_up(&session->wait);
2111 mutex_lock(&pservice->lock);
2112 /* remove this filp from the asynchronusly notified filp's */
2113 list_del_init(&session->list_session);
2114 vpu_service_session_clear(data, session);
2115 vcodec_iommu_clear(data->iommu_info, session);
2117 filp->private_data = NULL;
2118 mutex_unlock(&pservice->lock);
2120 dev_info(pservice->dev, "closed\n");
2125 static const struct file_operations vpu_service_fops = {
2126 .unlocked_ioctl = vpu_service_ioctl,
2127 .open = vpu_service_open,
2128 .release = vpu_service_release,
2129 #ifdef CONFIG_COMPAT
2130 .compat_ioctl = compat_vpu_service_ioctl,
2134 static irqreturn_t vdpu_irq(int irq, void *dev_id);
2135 static irqreturn_t vdpu_isr(int irq, void *dev_id);
2136 static irqreturn_t vepu_irq(int irq, void *dev_id);
2137 static irqreturn_t vepu_isr(int irq, void *dev_id);
2138 static void get_hw_info(struct vpu_subdev_data *data);
2140 static struct device *rockchip_get_sysmmu_dev(const char *compt)
2142 struct device_node *dn = NULL;
2143 struct platform_device *pd = NULL;
2144 struct device *ret = NULL;
2146 dn = of_find_compatible_node(NULL, NULL, compt);
2148 pr_err("can't find device node %s \r\n", compt);
2152 pd = of_find_device_by_node(dn);
2154 pr_err("can't find platform device in device node %s\n", compt);
2162 #ifdef CONFIG_IOMMU_API
2163 static inline void platform_set_sysmmu(struct device *iommu,
2166 dev->archdata.iommu = iommu;
2169 static inline void platform_set_sysmmu(struct device *iommu,
2175 int vcodec_sysmmu_fault_hdl(struct device *dev,
2176 enum rk_iommu_inttype itype,
2177 unsigned long pgtable_base,
2178 unsigned long fault_addr, unsigned int status)
2180 struct platform_device *pdev;
2181 struct vpu_service_info *pservice;
2182 struct vpu_subdev_data *data;
2187 pr_err("invalid NULL dev\n");
2191 pdev = container_of(dev, struct platform_device, dev);
2193 pr_err("invalid NULL platform_device\n");
2197 data = platform_get_drvdata(pdev);
2199 pr_err("invalid NULL vpu_subdev_data\n");
2203 pservice = data->pservice;
2204 if (pservice == NULL) {
2205 pr_err("invalid NULL vpu_service_info\n");
2209 if (pservice->reg_codec) {
2210 struct vpu_reg *reg = pservice->reg_codec;
2211 struct vcodec_mem_region *mem, *n;
2214 pr_err("vcodec, fault addr 0x%08lx\n", fault_addr);
2215 if (!list_empty(®->mem_region_list)) {
2216 list_for_each_entry_safe(mem, n, ®->mem_region_list,
2218 pr_err("vcodec, reg[%02u] mem region [%02d] 0x%lx %lx\n",
2219 mem->reg_idx, i, mem->iova, mem->len);
2223 pr_err("no memory region mapped\n");
2227 struct vpu_subdev_data *data = reg->data;
2228 u32 *base = (u32 *)data->dec_dev.regs;
2229 u32 len = data->hw_info->dec_reg_num;
2231 pr_err("current errror register set:\n");
2233 for (i = 0; i < len; i++)
2234 pr_err("reg[%02d] %08x\n",
2235 i, readl_relaxed(base + i));
2238 pr_alert("vcodec, page fault occur, reset hw\n");
2240 /* reg->reg[101] = 1; */
2247 static int vcodec_subdev_probe(struct platform_device *pdev,
2248 struct vpu_service_info *pservice)
2250 uint8_t *regs = NULL;
2252 uint32_t ioaddr = 0;
2253 struct resource *res = NULL;
2254 struct vpu_hw_info *hw_info = NULL;
2255 struct device *dev = &pdev->dev;
2256 struct device_node *np = pdev->dev.of_node;
2257 struct vpu_subdev_data *data = NULL;
2258 struct platform_device *sub_dev = NULL;
2259 struct device_node *sub_np = NULL;
2260 const char *name = np->name;
2261 char mmu_dev_dts_name[40];
2263 dev_info(dev, "probe device");
2265 data = devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
2269 data->pservice = pservice;
2272 INIT_WORK(&data->set_work, vpu_set_register_work);
2273 of_property_read_u32(np, "dev_mode", (u32 *)&data->mode);
2275 if (pservice->reg_base == 0) {
2276 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2277 data->regs = devm_ioremap_resource(dev, res);
2278 if (IS_ERR(data->regs)) {
2279 ret = PTR_ERR(data->regs);
2282 ioaddr = res->start;
2284 data->regs = pservice->reg_base;
2285 ioaddr = pservice->ioaddr;
2288 sub_np = of_parse_phandle(np, "iommus", 0);
2290 sub_dev = of_find_device_by_node(sub_np);
2291 data->mmu_dev = &sub_dev->dev;
2294 /* Back to legacy iommu probe */
2295 if (!data->mmu_dev) {
2296 switch (data->mode) {
2297 case VCODEC_RUNNING_MODE_VPU:
2298 sprintf(mmu_dev_dts_name,
2299 VPU_IOMMU_COMPATIBLE_NAME);
2301 case VCODEC_RUNNING_MODE_RKVDEC:
2302 sprintf(mmu_dev_dts_name,
2303 VDEC_IOMMU_COMPATIBLE_NAME);
2305 case VCODEC_RUNNING_MODE_HEVC:
2307 sprintf(mmu_dev_dts_name,
2308 HEVC_IOMMU_COMPATIBLE_NAME);
2313 rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2315 platform_set_sysmmu(data->mmu_dev, dev);
2317 rockchip_iovmm_set_fault_handler
2318 (dev, vcodec_sysmmu_fault_hdl);
2321 dev_info(dev, "vpu mmu dec %p\n", data->mmu_dev);
2323 clear_bit(MMU_ACTIVATED, &data->state);
2324 vpu_service_power_on(data, pservice);
2326 of_property_read_u32(np, "allocator", (u32 *)&pservice->alloc_type);
2327 data->iommu_info = vcodec_iommu_info_create(dev, data->mmu_dev,
2328 pservice->alloc_type);
2329 dev_info(dev, "allocator is %s\n", pservice->alloc_type == 1 ? "drm" :
2330 (pservice->alloc_type == 2 ? "ion" : "null"));
2331 vcodec_enter_mode(data);
2332 ret = vpu_service_check_hw(data);
2334 vpu_err("error: hw info check faild\n");
2337 vcodec_exit_mode(data);
2339 hw_info = data->hw_info;
2340 regs = (u8 *)data->regs;
2342 if (hw_info->dec_reg_num) {
2343 data->dec_dev.iosize = hw_info->dec_io_size;
2344 data->dec_dev.regs = (u32 *)(regs + hw_info->dec_offset);
2347 if (hw_info->enc_reg_num) {
2348 data->enc_dev.iosize = hw_info->enc_io_size;
2349 data->enc_dev.regs = (u32 *)(regs + hw_info->enc_offset);
2352 data->reg_size = max(hw_info->dec_io_size, hw_info->enc_io_size);
2354 data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
2355 if (data->irq_enc > 0) {
2356 ret = devm_request_threaded_irq(dev, data->irq_enc,
2358 IRQF_SHARED, dev_name(dev),
2361 dev_err(dev, "error: can't request vepu irq %d\n",
2366 data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
2367 if (data->irq_dec > 0) {
2368 ret = devm_request_threaded_irq(dev, data->irq_dec,
2370 IRQF_SHARED, dev_name(dev),
2373 dev_err(dev, "error: can't request vdpu irq %d\n",
2378 atomic_set(&data->dec_dev.irq_count_codec, 0);
2379 atomic_set(&data->dec_dev.irq_count_pp, 0);
2380 atomic_set(&data->enc_dev.irq_count_codec, 0);
2381 atomic_set(&data->enc_dev.irq_count_pp, 0);
2384 pservice->auto_freq = true;
2386 /* create device node */
2387 ret = alloc_chrdev_region(&data->dev_t, 0, 1, name);
2389 dev_err(dev, "alloc dev_t failed\n");
2393 cdev_init(&data->cdev, &vpu_service_fops);
2395 data->cdev.owner = THIS_MODULE;
2396 data->cdev.ops = &vpu_service_fops;
2398 ret = cdev_add(&data->cdev, data->dev_t, 1);
2401 dev_err(dev, "add dev_t failed\n");
2405 data->cls = class_create(THIS_MODULE, name);
2407 if (IS_ERR(data->cls)) {
2408 ret = PTR_ERR(data->cls);
2409 dev_err(dev, "class_create err:%d\n", ret);
2413 data->child_dev = device_create(data->cls, dev,
2414 data->dev_t, "%s", name);
2416 platform_set_drvdata(pdev, data);
2418 INIT_LIST_HEAD(&data->lnk_service);
2419 list_add_tail(&data->lnk_service, &pservice->subdev_list);
2423 if (data->child_dev) {
2424 device_destroy(data->cls, data->dev_t);
2425 cdev_del(&data->cdev);
2426 unregister_chrdev_region(data->dev_t, 1);
2430 class_destroy(data->cls);
2434 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2436 struct vpu_service_info *pservice = data->pservice;
2438 vcodec_iommu_info_destroy(data->iommu_info);
2439 data->iommu_info = NULL;
2441 mutex_lock(&pservice->lock);
2442 cancel_delayed_work_sync(&pservice->power_off_work);
2443 vpu_service_power_off(pservice);
2444 mutex_unlock(&pservice->lock);
2446 device_destroy(data->cls, data->dev_t);
2447 class_destroy(data->cls);
2448 cdev_del(&data->cdev);
2449 unregister_chrdev_region(data->dev_t, 1);
2451 #ifdef CONFIG_DEBUG_FS
2452 if (!IS_ERR_OR_NULL(data->debugfs_dir))
2453 debugfs_remove_recursive(data->debugfs_dir);
2457 static void vcodec_read_property(struct device_node *np,
2458 struct vpu_service_info *pservice)
2460 pservice->mode_bit = 0;
2461 pservice->mode_ctrl = 0;
2462 pservice->subcnt = 0;
2463 pservice->grf_base = NULL;
2465 of_property_read_u32(np, "subcnt", &pservice->subcnt);
2467 if (pservice->subcnt > 1) {
2468 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2469 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2471 #ifdef CONFIG_MFD_SYSCON
2472 pservice->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2473 if (IS_ERR_OR_NULL(pservice->grf)) {
2474 pservice->grf = NULL;
2476 pservice->grf_base = RK_GRF_VIRT;
2478 vpu_err("can't find vpu grf property\n");
2484 pservice->grf_base = RK_GRF_VIRT;
2486 vpu_err("can't find vpu grf property\n");
2491 #ifdef CONFIG_RESET_CONTROLLER
2492 pservice->rst_a = devm_reset_control_get(pservice->dev, "video_a");
2493 pservice->rst_h = devm_reset_control_get(pservice->dev, "video_h");
2494 pservice->rst_v = devm_reset_control_get(pservice->dev, "video");
2496 if (IS_ERR_OR_NULL(pservice->rst_a)) {
2497 dev_warn(pservice->dev, "No aclk reset resource define\n");
2498 pservice->rst_a = NULL;
2501 if (IS_ERR_OR_NULL(pservice->rst_h)) {
2502 dev_warn(pservice->dev, "No hclk reset resource define\n");
2503 pservice->rst_h = NULL;
2506 if (IS_ERR_OR_NULL(pservice->rst_v)) {
2507 dev_warn(pservice->dev, "No core reset resource define\n");
2508 pservice->rst_v = NULL;
2512 of_property_read_string(np, "name", (const char **)&pservice->name);
2515 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2517 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2518 pservice->curr_mode = -1;
2520 wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2521 INIT_LIST_HEAD(&pservice->waiting);
2522 INIT_LIST_HEAD(&pservice->running);
2523 mutex_init(&pservice->lock);
2524 mutex_init(&pservice->shutdown_lock);
2525 atomic_set(&pservice->service_on, 1);
2527 INIT_LIST_HEAD(&pservice->done);
2528 INIT_LIST_HEAD(&pservice->session);
2529 INIT_LIST_HEAD(&pservice->subdev_list);
2531 pservice->reg_pproc = NULL;
2532 atomic_set(&pservice->total_running, 0);
2533 atomic_set(&pservice->enabled, 0);
2534 atomic_set(&pservice->power_on_cnt, 0);
2535 atomic_set(&pservice->power_off_cnt, 0);
2536 atomic_set(&pservice->reset_request, 0);
2538 INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2539 pservice->last.tv64 = 0;
2541 pservice->alloc_type = 0;
2544 static int vcodec_probe(struct platform_device *pdev)
2548 struct resource *res = NULL;
2549 struct device *dev = &pdev->dev;
2550 struct device_node *np = pdev->dev.of_node;
2551 struct vpu_service_info *pservice = NULL;
2552 struct vcodec_device_info *driver_data;
2554 pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info),
2558 pservice->dev = dev;
2560 pservice->set_workq = create_singlethread_workqueue("vcodec");
2561 if (!pservice->set_workq) {
2562 dev_err(dev, "failed to create workqueue\n");
2566 driver_data = vcodec_get_drv_data(pdev);
2570 vcodec_read_property(np, pservice);
2571 vcodec_init_drvdata(pservice);
2573 /* Underscore for label, hyphens for name */
2574 switch (driver_data->device_type) {
2575 case VCODEC_DEVICE_TYPE_VPUX:
2576 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2578 case VCODEC_DEVICE_TYPE_VPUC:
2579 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2581 case VCODEC_DEVICE_TYPE_HEVC:
2582 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2584 case VCODEC_DEVICE_TYPE_RKVD:
2585 pservice->dev_id = VCODEC_DEVICE_ID_RKVDEC;
2588 dev_err(dev, "unsupported device type\n");
2592 if (0 > vpu_get_clk(pservice))
2595 if (of_property_read_bool(np, "reg")) {
2596 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2598 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2599 if (IS_ERR(pservice->reg_base)) {
2600 vpu_err("ioremap registers base failed\n");
2601 ret = PTR_ERR(pservice->reg_base);
2604 pservice->ioaddr = res->start;
2606 pservice->reg_base = 0;
2609 pm_runtime_enable(dev);
2611 if (of_property_read_bool(np, "subcnt")) {
2612 struct vpu_subdev_data *data = NULL;
2614 data = devm_kzalloc(dev, sizeof(struct vpu_subdev_data),
2619 for (i = 0; i < pservice->subcnt; i++) {
2620 struct device_node *sub_np;
2621 struct platform_device *sub_pdev;
2623 sub_np = of_parse_phandle(np, "rockchip,sub", i);
2624 sub_pdev = of_find_device_by_node(sub_np);
2626 vcodec_subdev_probe(sub_pdev, pservice);
2628 data->pservice = pservice;
2629 platform_set_drvdata(pdev, data);
2631 vcodec_subdev_probe(pdev, pservice);
2634 vpu_service_power_off(pservice);
2636 dev_info(dev, "init success\n");
2641 dev_info(dev, "init failed\n");
2642 vpu_service_power_off(pservice);
2643 destroy_workqueue(pservice->set_workq);
2644 wake_lock_destroy(&pservice->wake_lock);
2649 static int vcodec_remove(struct platform_device *pdev)
2651 struct vpu_subdev_data *data = platform_get_drvdata(pdev);
2653 vcodec_subdev_remove(data);
2655 pm_runtime_disable(data->pservice->dev);
2660 static void vcodec_shutdown(struct platform_device *pdev)
2662 struct vpu_subdev_data *data = platform_get_drvdata(pdev);
2663 struct vpu_service_info *pservice = data->pservice;
2664 struct device_node *np = pdev->dev.of_node;
2669 dev_info(&pdev->dev, "vcodec shutdown");
2671 mutex_lock(&pservice->shutdown_lock);
2672 atomic_set(&pservice->service_on, 0);
2673 mutex_unlock(&pservice->shutdown_lock);
2675 ret = readx_poll_timeout(atomic_read,
2676 &pservice->total_running,
2677 val, val == 0, 20000, 200000);
2678 if (ret == -ETIMEDOUT)
2679 dev_err(&pdev->dev, "wait total running time out\n");
2681 vcodec_exit_mode(data);
2682 vpu_service_clear(data);
2683 if (of_property_read_bool(np, "subcnt")) {
2684 for (i = 0; i < pservice->subcnt; i++) {
2685 struct device_node *sub_np;
2686 struct platform_device *sub_pdev;
2688 sub_np = of_parse_phandle(np, "rockchip,sub", i);
2689 sub_pdev = of_find_device_by_node(sub_np);
2690 vcodec_subdev_remove(platform_get_drvdata(sub_pdev));
2694 vcodec_subdev_remove(data);
2697 pm_runtime_disable(&pdev->dev);
2700 static const struct of_device_id vcodec_service_dt_ids[] = {
2702 .compatible = "rockchip,vpu_service",
2703 .data = &vpu_device_info,
2706 .compatible = "rockchip,hevc_service",
2707 .data = &hevc_device_info,
2710 .compatible = "rockchip,vpu_combo",
2711 .data = &vpu_combo_device_info,
2714 .compatible = "rockchip,rkvdec",
2715 .data = &rkvd_device_info,
2720 MODULE_DEVICE_TABLE(of, vcodec_service_dt_ids);
2722 static void *vcodec_get_drv_data(struct platform_device *pdev)
2724 struct vcodec_device_info *driver_data = NULL;
2725 const struct of_device_id *match;
2727 match = of_match_node(vcodec_service_dt_ids, pdev->dev.of_node);
2729 driver_data = (struct vcodec_device_info *)match->data;
2734 static struct platform_driver vcodec_driver = {
2735 .probe = vcodec_probe,
2736 .remove = vcodec_remove,
2737 .shutdown = vcodec_shutdown,
2739 .name = "rk-vcodec",
2740 .owner = THIS_MODULE,
2741 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2745 static void get_hw_info(struct vpu_subdev_data *data)
2747 struct vpu_service_info *pservice = data->pservice;
2748 struct vpu_dec_config *dec = &pservice->dec_config;
2749 struct vpu_enc_config *enc = &pservice->enc_config;
2751 if (of_machine_is_compatible("rockchip,rk2928") ||
2752 of_machine_is_compatible("rockchip,rk3036") ||
2753 of_machine_is_compatible("rockchip,rk3066") ||
2754 of_machine_is_compatible("rockchip,rk3126") ||
2755 of_machine_is_compatible("rockchip,rk3188"))
2756 dec->max_dec_pic_width = 1920;
2758 dec->max_dec_pic_width = 4096;
2760 if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2761 dec->h264_support = 3;
2762 dec->jpeg_support = 1;
2763 dec->mpeg4_support = 2;
2764 dec->vc1_support = 3;
2765 dec->mpeg2_support = 1;
2766 dec->pp_support = 1;
2767 dec->sorenson_support = 1;
2768 dec->ref_buf_support = 3;
2769 dec->vp6_support = 1;
2770 dec->vp7_support = 1;
2771 dec->vp8_support = 1;
2772 dec->avs_support = 1;
2773 dec->jpeg_ext_support = 0;
2774 dec->custom_mpeg4_support = 1;
2776 dec->mvc_support = 1;
2778 if (!of_machine_is_compatible("rockchip,rk3036")) {
2779 u32 config_reg = readl_relaxed(data->enc_dev.regs + 63);
2781 enc->max_encoded_width = config_reg & ((1 << 11) - 1);
2782 enc->h264_enabled = 1;
2783 enc->mpeg4_enabled = (config_reg >> 26) & 1;
2784 enc->jpeg_enabled = 1;
2785 enc->vs_enabled = (config_reg >> 24) & 1;
2786 enc->rgb_enabled = (config_reg >> 28) & 1;
2787 enc->reg_size = data->reg_size;
2792 pservice->auto_freq = true;
2793 vpu_debug(DEBUG_EXTRA_INFO,
2794 "vpu_service set to auto frequency mode\n");
2795 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2797 pservice->bug_dec_addr = of_machine_is_compatible
2798 ("rockchip,rk30xx");
2799 } else if (data->mode == VCODEC_RUNNING_MODE_RKVDEC) {
2800 pservice->auto_freq = true;
2801 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2803 /* disable frequency switch in hevc.*/
2804 pservice->auto_freq = false;
2808 static bool check_irq_err(struct vpu_task_info *task, u32 irq_status)
2810 vpu_debug(DEBUG_IRQ_CHECK, "task %s status %08x mask %08x\n",
2811 task->name, irq_status, task->error_mask);
2813 return (task->error_mask & irq_status) ? true : false;
2816 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2818 struct vpu_subdev_data *data = (struct vpu_subdev_data *)dev_id;
2819 struct vpu_service_info *pservice = data->pservice;
2820 struct vpu_task_info *task = NULL;
2821 struct vpu_device *dev = &data->dec_dev;
2822 u32 hw_id = data->hw_info->hw_id;
2826 task = &data->task_info[TASK_DEC];
2828 raw_status = readl_relaxed(dev->regs + task->reg_irq);
2829 dec_status = raw_status;
2831 vpu_debug(DEBUG_TASK_INFO,
2832 "vdpu_irq reg %d status %x mask: irq %x ready %x error %0x\n",
2833 task->reg_irq, dec_status,
2834 task->irq_mask, task->ready_mask, task->error_mask);
2836 if (dec_status & task->irq_mask) {
2837 time_record(task, 1);
2838 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq dec status %08x\n",
2840 if ((dec_status & 0x40001) == 0x40001) {
2843 readl_relaxed(dev->regs +
2845 } while ((dec_status & 0x40001) == 0x40001);
2848 if (check_irq_err(task, dec_status))
2849 atomic_add(1, &pservice->reset_request);
2851 writel_relaxed(0, dev->regs + task->reg_irq);
2853 /* set clock gating to save power */
2854 writel(task->gating_mask, dev->regs + task->reg_en);
2856 atomic_add(1, &dev->irq_count_codec);
2860 task = &data->task_info[TASK_PP];
2861 if (hw_id != HEVC_ID && hw_id != RKV_DEC_ID) {
2862 u32 pp_status = readl_relaxed(dev->regs + task->irq_mask);
2864 if (pp_status & task->irq_mask) {
2865 time_record(task, 1);
2866 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq pp status %08x\n",
2869 if (check_irq_err(task, dec_status))
2870 atomic_add(1, &pservice->reset_request);
2873 writel_relaxed(pp_status & (~task->reg_irq),
2874 dev->regs + task->irq_mask);
2875 atomic_add(1, &dev->irq_count_pp);
2880 pservice->irq_status = raw_status;
2882 if (atomic_read(&dev->irq_count_pp) ||
2883 atomic_read(&dev->irq_count_codec))
2884 return IRQ_WAKE_THREAD;
2889 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2891 struct vpu_subdev_data *data = (struct vpu_subdev_data *)dev_id;
2892 struct vpu_service_info *pservice = data->pservice;
2893 struct vpu_device *dev = &data->dec_dev;
2895 mutex_lock(&pservice->lock);
2896 if (atomic_read(&dev->irq_count_codec)) {
2897 atomic_sub(1, &dev->irq_count_codec);
2898 if (pservice->reg_codec == NULL) {
2899 vpu_err("error: dec isr with no task waiting\n");
2901 reg_from_run_to_done(data, pservice->reg_codec);
2902 /* avoid vpu timeout and can't recover problem */
2903 if (data->mode == VCODEC_RUNNING_MODE_VPU)
2904 VDPU_SOFT_RESET(data->regs);
2908 if (atomic_read(&dev->irq_count_pp)) {
2909 atomic_sub(1, &dev->irq_count_pp);
2910 if (pservice->reg_pproc == NULL)
2911 vpu_err("error: pp isr with no task waiting\n");
2913 reg_from_run_to_done(data, pservice->reg_pproc);
2916 queue_work(pservice->set_workq, &data->set_work);
2917 mutex_unlock(&pservice->lock);
2921 static irqreturn_t vepu_irq(int irq, void *dev_id)
2923 struct vpu_subdev_data *data = (struct vpu_subdev_data *)dev_id;
2924 struct vpu_service_info *pservice = data->pservice;
2925 struct vpu_task_info *task = &data->task_info[TASK_ENC];
2926 struct vpu_device *dev = &data->enc_dev;
2929 irq_status = readl_relaxed(dev->regs + task->reg_irq);
2931 vpu_debug(DEBUG_TASK_INFO,
2932 "vepu_irq reg %d status %x mask: irq %x ready %x error %0x\n",
2933 task->reg_irq, irq_status,
2934 task->irq_mask, task->ready_mask, task->error_mask);
2936 vpu_debug(DEBUG_IRQ_STATUS, "vepu_irq enc status %08x\n", irq_status);
2938 if (likely(irq_status & task->irq_mask)) {
2939 time_record(task, 1);
2941 if (check_irq_err(task, irq_status))
2942 atomic_add(1, &pservice->reset_request);
2945 writel_relaxed(irq_status & (~task->irq_mask),
2946 dev->regs + task->reg_irq);
2948 atomic_add(1, &dev->irq_count_codec);
2952 pservice->irq_status = irq_status;
2954 if (atomic_read(&dev->irq_count_codec))
2955 return IRQ_WAKE_THREAD;
2960 static irqreturn_t vepu_isr(int irq, void *dev_id)
2962 struct vpu_subdev_data *data = (struct vpu_subdev_data *)dev_id;
2963 struct vpu_service_info *pservice = data->pservice;
2964 struct vpu_device *dev = &data->enc_dev;
2966 mutex_lock(&pservice->lock);
2967 if (atomic_read(&dev->irq_count_codec)) {
2968 atomic_sub(1, &dev->irq_count_codec);
2969 if (NULL == pservice->reg_codec)
2970 vpu_err("error: enc isr with no task waiting\n");
2972 reg_from_run_to_done(data, pservice->reg_codec);
2974 queue_work(pservice->set_workq, &data->set_work);
2975 mutex_unlock(&pservice->lock);
2980 module_platform_driver(vcodec_driver);
2981 MODULE_LICENSE("GPL v2");