2 * Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
3 * author: chenhengming, chm@rock-chips.com
4 * Alpha Lin, alpha.lin@rock-chips.com
5 * Jung Zhao, jung.zhao@rock-chips.com
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/clk.h>
21 #include <linux/compat.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/reset.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/wakelock.h>
33 #include <linux/cdev.h>
35 #include <linux/of_platform.h>
36 #include <linux/of_irq.h>
37 #include <linux/regmap.h>
38 #include <linux/mfd/syscon.h>
39 #include <linux/uaccess.h>
40 #include <linux/debugfs.h>
41 #include <linux/pm_runtime.h>
43 #include <linux/rockchip/cru.h>
44 #include <linux/rockchip/pmu.h>
45 #include <linux/rockchip/grf.h>
47 #include <linux/dma-buf.h>
48 #include <linux/rockchip-iovmm.h>
50 #include "vcodec_hw_info.h"
51 #include "vcodec_hw_vpu.h"
52 #include "vcodec_hw_rkv.h"
53 #include "vcodec_hw_vpu2.h"
55 #include "vcodec_service.h"
57 #include "vcodec_iommu_ops.h"
61 * +------+-------------------+
63 * +------+-------------------+
64 * 0~23 bit is for different information type
65 * 24~31 bit is for information print format
68 #define DEBUG_POWER 0x00000001
69 #define DEBUG_CLOCK 0x00000002
70 #define DEBUG_IRQ_STATUS 0x00000004
71 #define DEBUG_IOMMU 0x00000008
72 #define DEBUG_IOCTL 0x00000010
73 #define DEBUG_FUNCTION 0x00000020
74 #define DEBUG_REGISTER 0x00000040
75 #define DEBUG_EXTRA_INFO 0x00000080
76 #define DEBUG_TIMING 0x00000100
77 #define DEBUG_TASK_INFO 0x00000200
79 #define DEBUG_SET_REG 0x00001000
80 #define DEBUG_GET_REG 0x00002000
81 #define DEBUG_PPS_FILL 0x00004000
82 #define DEBUG_IRQ_CHECK 0x00008000
83 #define DEBUG_CACHE_32B 0x00010000
85 #define PRINT_FUNCTION 0x80000000
86 #define PRINT_LINE 0x40000000
88 #define MHZ (1000 * 1000)
89 #define SIZE_REG(reg) ((reg) * 4)
91 #define VCODEC_CLOCK_ENABLE 1
92 #define EXTRA_INFO_MAGIC 0x4C4A46
95 module_param(debug, int, S_IRUGO | S_IWUSR);
96 MODULE_PARM_DESC(debug, "bit switch for vcodec_service debug information");
98 * hardware information organization
100 * In order to support multiple hardware with different version the hardware
101 * information is organized as follow:
103 * 1. First, index hardware by register size / position.
104 * These information is fix for each hardware and do not relate to runtime
105 * work flow. It only related to resource allocation.
106 * Descriptor: struct vpu_hw_info
108 * 2. Then, index hardware by runtime configuration
109 * These information is related to runtime setting behave including enable
110 * register, irq register and other key control flag
111 * Descriptor: struct vpu_task_info
113 * 3. Final, on iommu case the fd translation is required
114 * Descriptor: struct vpu_trans_info
128 struct extra_info_elem {
134 struct extra_info_for_iommu {
137 struct extra_info_elem elem[20];
140 static const struct vcodec_info vcodec_info_set[] = {
142 .hw_id = VPU_ID_8270,
143 .hw_info = &hw_vpu_8270,
144 .task_info = task_vpu,
145 .trans_info = trans_vpu,
148 .hw_id = VPU_ID_4831,
149 .hw_info = &hw_vpu_4831,
150 .task_info = task_vpu,
151 .trans_info = trans_vpu,
154 .hw_id = VPU_DEC_ID_9190,
155 .hw_info = &hw_vpu_9190,
156 .task_info = task_vpu,
157 .trans_info = trans_vpu,
161 .hw_info = &hw_rkhevc,
162 .task_info = task_rkv,
163 .trans_info = trans_rkv,
167 .hw_info = &hw_rkvdec,
168 .task_info = task_rkv,
169 .trans_info = trans_rkv,
174 .task_info = task_vpu2,
175 .trans_info = trans_vpu2,
179 /* Both VPU1 and VPU2 */
180 static const struct vcodec_device_info vpu_device_info = {
181 .device_type = VCODEC_DEVICE_TYPE_VPUX,
182 .name = "vpu-service",
185 static const struct vcodec_device_info vpu_combo_device_info = {
186 .device_type = VCODEC_DEVICE_TYPE_VPUC,
190 static const struct vcodec_device_info hevc_device_info = {
191 .device_type = VCODEC_DEVICE_TYPE_HEVC,
192 .name = "hevc-service",
195 static const struct vcodec_device_info rkvd_device_info = {
196 .device_type = VCODEC_DEVICE_TYPE_RKVD,
202 #define vpu_debug_func(type, fmt, args...) \
204 if (unlikely(debug & type)) { \
205 pr_info("%s:%d: " fmt, \
206 __func__, __LINE__, ##args); \
209 #define vpu_debug(type, fmt, args...) \
211 if (unlikely(debug & type)) { \
212 pr_info(fmt, ##args); \
216 #define vpu_debug_func(level, fmt, args...)
217 #define vpu_debug(level, fmt, args...)
220 #define vpu_debug_enter() vpu_debug_func(DEBUG_FUNCTION, "enter\n")
221 #define vpu_debug_leave() vpu_debug_func(DEBUG_FUNCTION, "leave\n")
223 #define vpu_err(fmt, args...) \
224 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
243 * struct for process session which connect to vpu
245 * @author ChenHengming (2011-5-3)
248 enum VPU_CLIENT_TYPE type;
249 /* a linked list of data so we can access them for debugging */
250 struct list_head list_session;
251 /* a linked list of register data waiting for process */
252 struct list_head waiting;
253 /* a linked list of register data in processing */
254 struct list_head running;
255 /* a linked list of register data processed */
256 struct list_head done;
257 wait_queue_head_t wait;
259 atomic_t task_running;
263 * struct for process register set
265 * @author ChenHengming (2011-5-4)
268 enum VPU_CLIENT_TYPE type;
270 struct vpu_session *session;
271 struct vpu_subdev_data *data;
272 struct vpu_task_info *task;
273 const struct vpu_trans_info *trans;
275 /* link to vpu service session */
276 struct list_head session_link;
277 /* link to register set list */
278 struct list_head status_link;
281 struct list_head mem_region_list;
287 atomic_t irq_count_codec;
288 atomic_t irq_count_pp;
293 enum vcodec_device_id {
294 VCODEC_DEVICE_ID_VPU,
295 VCODEC_DEVICE_ID_HEVC,
296 VCODEC_DEVICE_ID_COMBO,
297 VCODEC_DEVICE_ID_RKVDEC,
298 VCODEC_DEVICE_ID_BUTT
301 enum VCODEC_RUNNING_MODE {
302 VCODEC_RUNNING_MODE_NONE = -1,
303 VCODEC_RUNNING_MODE_VPU,
304 VCODEC_RUNNING_MODE_HEVC,
305 VCODEC_RUNNING_MODE_RKVDEC
308 struct vcodec_mem_region {
309 struct list_head srv_lnk;
310 struct list_head reg_lnk;
311 struct list_head session_lnk;
312 unsigned long iova; /* virtual address for iommu */
319 MMU_ACTIVATED = BIT(0)
322 struct vpu_subdev_data {
326 struct device *child_dev;
330 struct vpu_service_info *pservice;
333 enum VCODEC_RUNNING_MODE mode;
334 struct list_head lnk_service;
338 struct vpu_device enc_dev;
339 struct vpu_device dec_dev;
341 enum VPU_HW_ID hw_id;
342 struct vpu_hw_info *hw_info;
343 struct vpu_task_info *task_info;
344 const struct vpu_trans_info *trans_info;
349 #ifdef CONFIG_DEBUG_FS
350 struct dentry *debugfs_dir;
351 struct dentry *debugfs_file_regs;
354 struct device *mmu_dev;
355 struct vcodec_iommu_info *iommu_info;
358 struct vpu_service_info {
359 struct wake_lock wake_lock;
360 struct delayed_work power_off_work;
361 ktime_t last; /* record previous power-on time */
362 /* vpu service structure global lock */
364 /* link to link_reg in struct vpu_reg */
365 struct list_head waiting;
366 /* link to link_reg in struct vpu_reg */
367 struct list_head running;
368 /* link to link_reg in struct vpu_reg */
369 struct list_head done;
370 /* link to list_session in struct vpu_session */
371 struct list_head session;
372 atomic_t total_running;
374 atomic_t power_on_cnt;
375 atomic_t power_off_cnt;
377 struct mutex shutdown_lock;
378 struct vpu_reg *reg_codec;
379 struct vpu_reg *reg_pproc;
380 struct vpu_reg *reg_resev;
381 struct vpu_dec_config dec_config;
382 struct vpu_enc_config enc_config;
386 atomic_t freq_status;
388 struct clk *aclk_vcodec;
389 struct clk *hclk_vcodec;
390 struct clk *clk_core;
391 struct clk *clk_cabac;
392 struct clk *pd_video;
394 #ifdef CONFIG_RESET_CONTROLLER
395 struct reset_control *rst_a;
396 struct reset_control *rst_h;
397 struct reset_control *rst_v;
402 atomic_t reset_request;
403 struct list_head mem_region_list;
405 enum vcodec_device_id dev_id;
407 enum VCODEC_RUNNING_MODE curr_mode;
410 struct delayed_work simulate_work;
422 struct list_head subdev_list;
433 struct compat_vpu_request {
439 #define VDPU_SOFT_RESET_REG 101
440 #define VDPU_CLEAN_CACHE_REG 516
441 #define VEPU_CLEAN_CACHE_REG 772
442 #define HEVC_CLEAN_CACHE_REG 260
444 #define VPU_REG_ENABLE(base, reg) writel_relaxed(1, base + reg)
446 #define VDPU_SOFT_RESET(base) VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
447 #define VDPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
448 #define VEPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
449 #define HEVC_CLEAN_CACHE(base) VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
451 #define VPU_POWER_OFF_DELAY (4 * HZ) /* 4s */
452 #define VPU_TIMEOUT_DELAY (2 * HZ) /* 2s */
454 static void *vcodec_get_drv_data(struct platform_device *pdev);
456 static void vpu_service_power_on(struct vpu_subdev_data *data,
457 struct vpu_service_info *pservice);
459 static void time_record(struct vpu_task_info *task, int is_end)
461 if (unlikely(debug & DEBUG_TIMING) && task)
462 do_gettimeofday((is_end) ? (&task->end) : (&task->start));
465 static void time_diff(struct vpu_task_info *task)
467 vpu_debug(DEBUG_TIMING, "%s task: %ld ms\n", task->name,
468 (task->end.tv_sec - task->start.tv_sec) * 1000 +
469 (task->end.tv_usec - task->start.tv_usec) / 1000);
472 static void vcodec_enter_mode(struct vpu_subdev_data *data)
476 struct vpu_service_info *pservice = data->pservice;
477 struct vpu_subdev_data *subdata, *n;
479 if (pservice->subcnt < 2)
482 if (pservice->curr_mode == data->mode)
485 vpu_debug(DEBUG_IOMMU, "vcodec enter mode %d\n", data->mode);
486 list_for_each_entry_safe(subdata, n,
487 &pservice->subdev_list, lnk_service) {
488 if (data != subdata && subdata->mmu_dev &&
489 test_bit(MMU_ACTIVATED, &subdata->state)) {
490 clear_bit(MMU_ACTIVATED, &subdata->state);
493 bits = 1 << pservice->mode_bit;
494 #ifdef CONFIG_MFD_SYSCON
496 regmap_read(pservice->grf, pservice->mode_ctrl, &raw);
498 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
499 regmap_write(pservice->grf, pservice->mode_ctrl,
500 raw | bits | (bits << 16));
502 regmap_write(pservice->grf, pservice->mode_ctrl,
503 (raw & (~bits)) | (bits << 16));
504 } else if (pservice->grf_base) {
505 u32 *grf_base = pservice->grf_base;
507 raw = readl_relaxed(grf_base + pservice->mode_ctrl / 4);
508 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
509 writel_relaxed(raw | bits | (bits << 16),
510 grf_base + pservice->mode_ctrl / 4);
512 writel_relaxed((raw & (~bits)) | (bits << 16),
513 grf_base + pservice->mode_ctrl / 4);
515 vpu_err("no grf resource define, switch decoder failed\n");
519 if (pservice->grf_base) {
520 u32 *grf_base = pservice->grf_base;
522 raw = readl_relaxed(grf_base + pservice->mode_ctrl / 4);
523 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
524 writel_relaxed(raw | bits | (bits << 16),
525 grf_base + pservice->mode_ctrl / 4);
527 writel_relaxed((raw & (~bits)) | (bits << 16),
528 grf_base + pservice->mode_ctrl / 4);
530 vpu_err("no grf resource define, switch decoder failed\n");
534 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
535 set_bit(MMU_ACTIVATED, &data->state);
536 if (!atomic_read(&pservice->enabled))
537 /* FIXME BUG_ON should not be used in mass produce */
538 BUG_ON(!atomic_read(&pservice->enabled));
541 pservice->prev_mode = pservice->curr_mode;
542 pservice->curr_mode = data->mode;
545 static void vcodec_exit_mode(struct vpu_subdev_data *data)
548 * In case of VPU Combo, it require HW switch its running mode
549 * before the other HW component start work. set current HW running
550 * mode to none, can ensure HW switch to its reqired mode properly.
552 data->pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
555 static int vpu_get_clk(struct vpu_service_info *pservice)
557 #if VCODEC_CLOCK_ENABLE
558 struct device *dev = pservice->dev;
560 switch (pservice->dev_id) {
561 case VCODEC_DEVICE_ID_HEVC:
562 pservice->pd_video = devm_clk_get(dev, "pd_hevc");
563 if (IS_ERR(pservice->pd_video)) {
564 pservice->pd_video = NULL;
565 dev_info(dev, "failed on clk_get pd_hevc\n");
567 case VCODEC_DEVICE_ID_COMBO:
568 case VCODEC_DEVICE_ID_RKVDEC:
569 pservice->clk_cabac = devm_clk_get(dev, "clk_cabac");
570 if (IS_ERR(pservice->clk_cabac)) {
571 dev_err(dev, "failed on clk_get clk_cabac\n");
572 pservice->clk_cabac = NULL;
574 pservice->clk_core = devm_clk_get(dev, "clk_core");
575 if (IS_ERR(pservice->clk_core)) {
576 dev_err(dev, "failed on clk_get clk_core\n");
577 pservice->clk_core = NULL;
580 case VCODEC_DEVICE_ID_VPU:
581 pservice->aclk_vcodec = devm_clk_get(dev, "aclk_vcodec");
582 if (IS_ERR(pservice->aclk_vcodec)) {
583 dev_err(dev, "failed on clk_get aclk_vcodec\n");
584 pservice->aclk_vcodec = NULL;
588 pservice->hclk_vcodec = devm_clk_get(dev, "hclk_vcodec");
589 if (IS_ERR(pservice->hclk_vcodec)) {
590 dev_err(dev, "failed on clk_get hclk_vcodec\n");
591 pservice->hclk_vcodec = NULL;
594 if (pservice->pd_video == NULL) {
595 pservice->pd_video = devm_clk_get(dev, "pd_video");
596 if (IS_ERR(pservice->pd_video)) {
597 pservice->pd_video = NULL;
598 dev_info(dev, "do not have pd_video\n");
612 static void _vpu_reset(struct vpu_subdev_data *data)
614 struct vpu_service_info *pservice = data->pservice;
615 enum pmu_idle_req type = IDLE_REQ_VIDEO;
617 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC)
618 type = IDLE_REQ_HEVC;
620 dev_info(pservice->dev, "resetting...\n");
621 WARN_ON(pservice->reg_codec != NULL);
622 WARN_ON(pservice->reg_pproc != NULL);
623 WARN_ON(pservice->reg_resev != NULL);
624 pservice->reg_codec = NULL;
625 pservice->reg_pproc = NULL;
626 pservice->reg_resev = NULL;
628 #ifdef CONFIG_RESET_CONTROLLER
629 dev_info(pservice->dev, "for 3288/3368...");
630 if (of_machine_is_compatible("rockchip,rk3288"))
631 rockchip_pmu_idle_request(pservice->dev, true);
632 if (pservice->rst_a && pservice->rst_h) {
633 dev_info(pservice->dev, "vpu reset in\n");
636 reset_control_assert(pservice->rst_v);
637 reset_control_assert(pservice->rst_a);
638 reset_control_assert(pservice->rst_h);
641 reset_control_deassert(pservice->rst_h);
642 reset_control_deassert(pservice->rst_a);
644 reset_control_deassert(pservice->rst_v);
645 } else if (pservice->rst_v) {
646 dev_info(pservice->dev, "hevc reset in\n");
647 reset_control_assert(pservice->rst_v);
650 reset_control_deassert(pservice->rst_v);
652 if (of_machine_is_compatible("rockchip,rk3288"))
653 rockchip_pmu_idle_request(pservice->dev, false);
657 static void vpu_reset(struct vpu_subdev_data *data)
659 struct vpu_service_info *pservice = data->pservice;
662 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
663 if (atomic_read(&pservice->enabled)) {
664 /* Need to reset iommu */
665 vcodec_iommu_detach(data->iommu_info);
666 vcodec_iommu_attach(data->iommu_info);
668 /* FIXME BUG_ON should not be used in mass produce */
669 BUG_ON(!atomic_read(&pservice->enabled));
673 atomic_set(&pservice->reset_request, 0);
674 dev_info(pservice->dev, "reset done\n");
677 static void reg_deinit(struct vpu_subdev_data *data, struct vpu_reg *reg);
678 static void vpu_service_session_clear(struct vpu_subdev_data *data,
679 struct vpu_session *session)
681 struct vpu_reg *reg, *n;
683 list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
684 reg_deinit(data, reg);
686 list_for_each_entry_safe(reg, n, &session->running, session_link) {
687 reg_deinit(data, reg);
689 list_for_each_entry_safe(reg, n, &session->done, session_link) {
690 reg_deinit(data, reg);
694 static void vpu_service_clear(struct vpu_subdev_data *data)
696 struct vpu_reg *reg, *n;
697 struct vpu_session *session, *s;
698 struct vpu_service_info *pservice = data->pservice;
700 list_for_each_entry_safe(reg, n, &pservice->waiting, status_link) {
701 reg_deinit(data, reg);
704 /* wake up session wait event to prevent the timeout hw reset
705 * during reboot procedure.
707 list_for_each_entry_safe(session, s,
708 &pservice->session, list_session)
709 wake_up(&session->wait);
712 static void vpu_service_dump(struct vpu_service_info *pservice)
717 static void vpu_service_power_off(struct vpu_service_info *pservice)
720 struct vpu_subdev_data *data = NULL, *n;
721 int ret = atomic_add_unless(&pservice->enabled, -1, 0);
726 total_running = atomic_read(&pservice->total_running);
728 pr_alert("alert: power off when %d task running!!\n",
731 pr_alert("alert: delay 50 ms for running task\n");
732 vpu_service_dump(pservice);
735 dev_dbg(pservice->dev, "power off...\n");
739 list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
740 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
741 clear_bit(MMU_ACTIVATED, &data->state);
742 vcodec_iommu_detach(data->iommu_info);
745 pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
746 pm_runtime_put(pservice->dev);
747 #if VCODEC_CLOCK_ENABLE
748 if (pservice->pd_video)
749 clk_disable_unprepare(pservice->pd_video);
750 if (pservice->hclk_vcodec)
751 clk_disable_unprepare(pservice->hclk_vcodec);
752 if (pservice->aclk_vcodec)
753 clk_disable_unprepare(pservice->aclk_vcodec);
754 if (pservice->clk_core)
755 clk_disable_unprepare(pservice->clk_core);
756 if (pservice->clk_cabac)
757 clk_disable_unprepare(pservice->clk_cabac);
760 atomic_add(1, &pservice->power_off_cnt);
761 wake_unlock(&pservice->wake_lock);
762 dev_dbg(pservice->dev, "power off done\n");
765 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
767 queue_delayed_work(system_wq, &pservice->power_off_work,
768 VPU_POWER_OFF_DELAY);
771 static void vpu_power_off_work(struct work_struct *work_s)
773 struct delayed_work *dlwork = container_of(work_s,
774 struct delayed_work, work);
775 struct vpu_service_info *pservice = container_of(dlwork,
776 struct vpu_service_info, power_off_work);
778 if (mutex_trylock(&pservice->lock)) {
779 vpu_service_power_off(pservice);
780 mutex_unlock(&pservice->lock);
782 /* Come back later if the device is busy... */
783 vpu_queue_power_off_work(pservice);
787 static void vpu_service_power_on(struct vpu_subdev_data *data,
788 struct vpu_service_info *pservice)
791 ktime_t now = ktime_get();
793 if (ktime_to_ns(ktime_sub(now, pservice->last)) > NSEC_PER_SEC ||
794 atomic_read(&pservice->power_on_cnt)) {
796 cancel_delayed_work_sync(&pservice->power_off_work);
797 vpu_queue_power_off_work(pservice);
798 pservice->last = now;
800 ret = atomic_add_unless(&pservice->enabled, 1, 1);
802 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
803 set_bit(MMU_ACTIVATED, &data->state);
804 vcodec_iommu_attach(data->iommu_info);
809 dev_dbg(pservice->dev, "power on\n");
811 #define BIT_VCODEC_CLK_SEL (1<<10)
812 if (of_machine_is_compatible("rockchip,rk3126"))
813 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1)
814 | BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
815 RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
817 #if VCODEC_CLOCK_ENABLE
818 if (pservice->aclk_vcodec)
819 clk_prepare_enable(pservice->aclk_vcodec);
820 if (pservice->hclk_vcodec)
821 clk_prepare_enable(pservice->hclk_vcodec);
822 if (pservice->clk_core)
823 clk_prepare_enable(pservice->clk_core);
824 if (pservice->clk_cabac)
825 clk_prepare_enable(pservice->clk_cabac);
826 if (pservice->pd_video)
827 clk_prepare_enable(pservice->pd_video);
829 pm_runtime_get_sync(pservice->dev);
831 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
832 set_bit(MMU_ACTIVATED, &data->state);
833 if (atomic_read(&pservice->enabled))
834 vcodec_iommu_attach(data->iommu_info);
837 * FIXME BUG_ON should not be used in mass
840 BUG_ON(!atomic_read(&pservice->enabled));
844 atomic_add(1, &pservice->power_on_cnt);
845 wake_lock(&pservice->wake_lock);
848 static inline bool reg_check_interlace(struct vpu_reg *reg)
850 u32 type = (reg->reg[3] & (1 << 23));
855 static inline enum VPU_DEC_FMT reg_check_fmt(struct vpu_reg *reg)
857 enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] >> 28) & 0xf);
862 static inline int reg_probe_width(struct vpu_reg *reg)
864 int width_in_mb = reg->reg[4] >> 23;
866 return width_in_mb * 16;
869 static inline int reg_probe_hevc_y_stride(struct vpu_reg *reg)
871 int y_virstride = reg->reg[8];
876 static int vcodec_fd_to_iova(struct vpu_subdev_data *data,
877 struct vpu_session *session,
883 struct vcodec_mem_region *mem_region;
885 hdl = vcodec_iommu_import(data->iommu_info, session, fd);
889 mem_region = kzalloc(sizeof(*mem_region), GFP_KERNEL);
890 if (mem_region == NULL) {
891 vpu_err("allocate memory for iommu memory region failed\n");
892 vcodec_iommu_free(data->iommu_info, session, hdl);
896 mem_region->hdl = hdl;
897 ret = vcodec_iommu_map_iommu(data->iommu_info, session, mem_region->hdl,
898 &mem_region->iova, &mem_region->len);
900 vpu_err("fd %d ion map iommu failed\n", fd);
902 vcodec_iommu_free(data->iommu_info, session, hdl);
906 INIT_LIST_HEAD(&mem_region->reg_lnk);
907 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
908 return mem_region->iova;
912 * NOTE: rkvdec/rkhevc put scaling list address in pps buffer hardware will read
913 * it by pps id in video stream data.
915 * So we need to translate the address in iommu case. The address data is also
916 * 10bit fd + 22bit offset mode.
917 * Because userspace decoder do not give the pps id in the register file sets
918 * kernel driver need to translate each scaling list address in pps buffer which
919 * means 256 pps for H.264, 64 pps for H.265.
921 * In order to optimize the performance kernel driver ask userspace decoder to
922 * set all scaling list address in pps buffer to the same one which will be used
923 * on current decoding task. Then kernel driver can only translate the first
924 * address then copy it all pps buffer.
926 static int fill_scaling_list_addr_in_pps(
927 struct vpu_subdev_data *data,
932 int scaling_list_addr_offset)
934 int base = scaling_list_addr_offset;
938 scaling_offset = (u32)pps[base + 0];
939 scaling_offset += (u32)pps[base + 1] << 8;
940 scaling_offset += (u32)pps[base + 2] << 16;
941 scaling_offset += (u32)pps[base + 3] << 24;
943 scaling_fd = scaling_offset & 0x3ff;
944 scaling_offset = scaling_offset >> 10;
946 if (scaling_fd > 0) {
948 u32 tmp = vcodec_fd_to_iova(data, reg->session, reg,
951 if (IS_ERR_VALUE(tmp))
953 tmp += scaling_offset;
955 for (i = 0; i < pps_info_count; i++, base += pps_info_size) {
956 pps[base + 0] = (tmp >> 0) & 0xff;
957 pps[base + 1] = (tmp >> 8) & 0xff;
958 pps[base + 2] = (tmp >> 16) & 0xff;
959 pps[base + 3] = (tmp >> 24) & 0xff;
966 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data,
967 struct vpu_session *session,
969 int size, struct vpu_reg *reg,
970 struct extra_info_for_iommu *ext_inf)
972 struct vpu_service_info *pservice = data->pservice;
973 struct vpu_task_info *task = reg->task;
974 enum FORMAT_TYPE type;
977 struct vcodec_mem_region *mem_region;
981 if (tbl == NULL || size <= 0) {
982 dev_err(pservice->dev, "input arguments invalidate\n");
987 type = task->get_fmt(reg->reg);
989 dev_err(pservice->dev, "invalid task with NULL get_fmt\n");
993 for (i = 0; i < size; i++) {
994 int usr_fd = reg->reg[tbl[i]] & 0x3FF;
996 /* if userspace do not set the fd at this register, skip */
1001 * for avoiding cache sync issue, we need to map/unmap
1002 * input buffer every time. FIX ME, if it is unnecessary
1004 if (task->reg_rlc == tbl[i])
1005 vcodec_iommu_free_fd(data->iommu_info, session, usr_fd);
1007 * special offset scale case
1009 * This translation is for fd + offset translation.
1010 * One register has 32bits. We need to transfer both buffer file
1011 * handle and the start address offset so we packet file handle
1012 * and offset together using below format.
1014 * 0~9 bit for buffer file handle range 0 ~ 1023
1015 * 10~31 bit for offset range 0 ~ 4M
1017 * But on 4K case the offset can be larger the 4M
1018 * So on H.264 4K vpu/vpu2 decoder we scale the offset by 16
1019 * But MPEG4 will use the same register for colmv and it do not
1022 * RKVdec do not have this issue.
1024 if ((type == FMT_H264D || type == FMT_VP9D) &&
1025 task->reg_dir_mv > 0 && task->reg_dir_mv == tbl[i])
1026 offset = reg->reg[tbl[i]] >> 10 << 4;
1028 offset = reg->reg[tbl[i]] >> 10;
1030 vpu_debug(DEBUG_IOMMU, "pos %3d fd %3d offset %10d i %d\n",
1031 tbl[i], usr_fd, offset, i);
1033 hdl = vcodec_iommu_import(data->iommu_info, session, usr_fd);
1035 if (task->reg_pps > 0 && task->reg_pps == tbl[i]) {
1036 int pps_info_offset;
1039 int scaling_list_addr_offset;
1043 pps_info_offset = offset;
1044 pps_info_count = 256;
1046 scaling_list_addr_offset = 23;
1049 pps_info_offset = 0;
1050 pps_info_count = 64;
1052 scaling_list_addr_offset = 74;
1055 pps_info_offset = 0;
1058 scaling_list_addr_offset = 0;
1062 vpu_debug(DEBUG_PPS_FILL,
1063 "scaling list filling parameter:\n");
1064 vpu_debug(DEBUG_PPS_FILL,
1065 "pps_info_offset %d\n", pps_info_offset);
1066 vpu_debug(DEBUG_PPS_FILL,
1067 "pps_info_count %d\n", pps_info_count);
1068 vpu_debug(DEBUG_PPS_FILL,
1069 "pps_info_size %d\n", pps_info_size);
1070 vpu_debug(DEBUG_PPS_FILL,
1071 "scaling_list_addr_offset %d\n",
1072 scaling_list_addr_offset);
1074 if (pps_info_count) {
1077 mutex_lock(&pservice->lock);
1079 pps = vcodec_iommu_map_kernel
1080 (data->iommu_info, session, hdl);
1082 vpu_debug(DEBUG_PPS_FILL,
1083 "scaling list setting pps %p\n", pps);
1084 pps += pps_info_offset;
1086 fill_scaling_list_addr_in_pps
1087 (data, reg, pps, pps_info_count,
1089 scaling_list_addr_offset);
1091 vcodec_iommu_unmap_kernel
1092 (data->iommu_info, session, hdl);
1093 mutex_unlock(&pservice->lock);
1097 mem_region = kzalloc(sizeof(*mem_region), GFP_KERNEL);
1100 vcodec_iommu_free(data->iommu_info, session, hdl);
1104 mem_region->hdl = hdl;
1105 mem_region->reg_idx = tbl[i];
1107 ret = vcodec_iommu_map_iommu(data->iommu_info, session,
1108 mem_region->hdl, &mem_region->iova,
1111 dev_err(pservice->dev,
1112 "reg %d fd %d ion map iommu failed\n",
1115 vcodec_iommu_free(data->iommu_info, session, hdl);
1120 * special for vpu dec num 12: record decoded length
1121 * hacking for decoded length
1122 * NOTE: not a perfect fix, the fd is not recorded
1124 if (task->reg_len > 0 && task->reg_len == tbl[i]) {
1125 reg->dec_base = mem_region->iova + offset;
1126 vpu_debug(DEBUG_REGISTER, "dec_set %08x\n",
1130 reg->reg[tbl[i]] = mem_region->iova + offset;
1131 INIT_LIST_HEAD(&mem_region->reg_lnk);
1132 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
1135 if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
1136 for (i = 0; i < ext_inf->cnt; i++) {
1137 vpu_debug(DEBUG_IOMMU, "reg[%d] + offset %d\n",
1138 ext_inf->elem[i].index,
1139 ext_inf->elem[i].offset);
1140 reg->reg[ext_inf->elem[i].index] +=
1141 ext_inf->elem[i].offset;
1148 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
1149 struct vpu_session *session,
1150 struct vpu_reg *reg,
1151 struct extra_info_for_iommu *ext_inf)
1153 struct vpu_service_info *pservice = data->pservice;
1154 enum FORMAT_TYPE type = reg->task->get_fmt(reg->reg);
1156 if (type < FMT_TYPE_BUTT) {
1157 const struct vpu_trans_info *info = ®->trans[type];
1158 const u8 *tbl = info->table;
1159 int size = info->count;
1161 return vcodec_bufid_to_iova(data, session, tbl, size, reg,
1165 dev_err(pservice->dev, "found invalid format type!\n");
1169 static void get_reg_freq(struct vpu_subdev_data *data, struct vpu_reg *reg)
1172 if (!of_machine_is_compatible("rockchip,rk2928g")) {
1173 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1174 if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1175 if (reg_probe_width(reg) > 3200) {
1176 /*raise frequency for 4k avc.*/
1177 reg->freq = VPU_FREQ_600M;
1180 if (reg_check_interlace(reg))
1181 reg->freq = VPU_FREQ_400M;
1184 if (data->hw_id == HEVC_ID) {
1185 if (reg_probe_hevc_y_stride(reg) > 60000)
1186 reg->freq = VPU_FREQ_400M;
1188 if (reg->type == VPU_PP)
1189 reg->freq = VPU_FREQ_400M;
1193 static struct vpu_reg *reg_init(struct vpu_subdev_data *data,
1194 struct vpu_session *session,
1195 void __user *src, u32 size)
1197 struct vpu_service_info *pservice = data->pservice;
1199 struct extra_info_for_iommu extra_info;
1200 struct vpu_reg *reg = kzalloc(sizeof(*reg) + data->reg_size,
1206 vpu_err("error: kzalloc failed\n");
1210 if (size > data->reg_size) {
1211 extra_size = size - data->reg_size;
1212 size = data->reg_size;
1214 reg->session = session;
1216 reg->type = session->type;
1218 reg->freq = VPU_FREQ_DEFAULT;
1219 reg->task = &data->task_info[session->type];
1220 reg->trans = data->trans_info;
1221 reg->reg = (u32 *)®[1];
1222 INIT_LIST_HEAD(®->session_link);
1223 INIT_LIST_HEAD(®->status_link);
1225 INIT_LIST_HEAD(®->mem_region_list);
1227 if (copy_from_user(®->reg[0], (void __user *)src, size)) {
1228 vpu_err("error: copy_from_user failed\n");
1233 if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1234 vpu_err("error: copy_from_user failed\n");
1239 if (vcodec_reg_address_translate(data, session, reg, &extra_info) < 0) {
1242 vpu_err("error: translate reg address failed, dumping regs\n");
1243 for (i = 0; i < size >> 2; i++)
1244 dev_err(pservice->dev, "reg[%02d]: %08x\n",
1245 i, *((u32 *)src + i));
1251 mutex_lock(&pservice->lock);
1252 list_add_tail(®->status_link, &pservice->waiting);
1253 list_add_tail(®->session_link, &session->waiting);
1254 mutex_unlock(&pservice->lock);
1256 if (pservice->auto_freq)
1257 get_reg_freq(data, reg);
1264 static void reg_deinit(struct vpu_subdev_data *data, struct vpu_reg *reg)
1266 struct vpu_service_info *pservice = data->pservice;
1267 struct vcodec_mem_region *mem_region = NULL, *n;
1269 list_del_init(®->session_link);
1270 list_del_init(®->status_link);
1271 if (reg == pservice->reg_codec)
1272 pservice->reg_codec = NULL;
1273 if (reg == pservice->reg_pproc)
1274 pservice->reg_pproc = NULL;
1276 /* release memory region attach to this registers table. */
1277 list_for_each_entry_safe(mem_region, n,
1278 ®->mem_region_list, reg_lnk) {
1279 vcodec_iommu_unmap_iommu(data->iommu_info, reg->session,
1281 vcodec_iommu_free(data->iommu_info, reg->session,
1283 list_del_init(&mem_region->reg_lnk);
1290 static void reg_from_wait_to_run(struct vpu_service_info *pservice,
1291 struct vpu_reg *reg)
1294 list_del_init(®->status_link);
1295 list_add_tail(®->status_link, &pservice->running);
1297 list_del_init(®->session_link);
1298 list_add_tail(®->session_link, ®->session->running);
1302 static void reg_copy_from_hw(struct vpu_reg *reg, u32 *src, u32 count)
1305 u32 *dst = reg->reg;
1308 for (i = 0; i < count; i++, src++)
1309 *dst++ = readl_relaxed(src);
1311 dst = (u32 *)®->reg[0];
1312 for (i = 0; i < count; i++)
1313 vpu_debug(DEBUG_GET_REG, "get reg[%02d] %08x\n", i, dst[i]);
1318 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1319 struct vpu_reg *reg)
1321 struct vpu_service_info *pservice = data->pservice;
1322 struct vpu_hw_info *hw_info = data->hw_info;
1323 struct vpu_task_info *task = reg->task;
1327 list_del_init(®->status_link);
1328 list_add_tail(®->status_link, &pservice->done);
1330 list_del_init(®->session_link);
1331 list_add_tail(®->session_link, ®->session->done);
1333 switch (reg->type) {
1335 pservice->reg_codec = NULL;
1336 reg_copy_from_hw(reg, data->enc_dev.regs, hw_info->enc_reg_num);
1337 reg->reg[task->reg_irq] = pservice->irq_status;
1340 pservice->reg_codec = NULL;
1341 reg_copy_from_hw(reg, data->dec_dev.regs, hw_info->dec_reg_num);
1343 /* revert hack for decoded length */
1344 if (task->reg_len > 0) {
1345 int reg_len = task->reg_len;
1346 u32 dec_get = reg->reg[reg_len];
1347 s32 dec_length = dec_get - reg->dec_base;
1349 vpu_debug(DEBUG_REGISTER,
1350 "dec_get %08x dec_length %d\n",
1351 dec_get, dec_length);
1352 reg->reg[reg_len] = dec_length << 10;
1355 reg->reg[task->reg_irq] = pservice->irq_status;
1358 pservice->reg_pproc = NULL;
1359 reg_copy_from_hw(reg, data->dec_dev.regs, hw_info->dec_reg_num);
1360 writel_relaxed(0, data->dec_dev.regs + task->reg_irq);
1364 u32 *regs = data->dec_dev.regs;
1366 pservice->reg_codec = NULL;
1367 pservice->reg_pproc = NULL;
1369 reg_copy_from_hw(reg, data->dec_dev.regs, hw_info->dec_reg_num);
1371 /* NOTE: remove pp pipeline mode flag first */
1372 pipe_mode = readl_relaxed(regs + task->reg_pipe);
1373 pipe_mode &= ~task->pipe_mask;
1374 writel_relaxed(pipe_mode, regs + task->reg_pipe);
1376 /* revert hack for decoded length */
1377 if (task->reg_len > 0) {
1378 int reg_len = task->reg_len;
1379 u32 dec_get = reg->reg[reg_len];
1380 s32 dec_length = dec_get - reg->dec_base;
1382 vpu_debug(DEBUG_REGISTER,
1383 "dec_get %08x dec_length %d\n",
1384 dec_get, dec_length);
1385 reg->reg[reg_len] = dec_length << 10;
1388 reg->reg[task->reg_irq] = pservice->irq_status;
1391 vpu_err("error: copy reg from hw with unknown type %d\n",
1395 vcodec_exit_mode(data);
1397 atomic_sub(1, ®->session->task_running);
1398 atomic_sub(1, &pservice->total_running);
1399 wake_up(®->session->wait);
1404 static void vpu_service_set_freq(struct vpu_service_info *pservice,
1405 struct vpu_reg *reg)
1407 enum VPU_FREQ curr = atomic_read(&pservice->freq_status);
1409 if (curr == reg->freq)
1412 atomic_set(&pservice->freq_status, reg->freq);
1413 switch (reg->freq) {
1414 case VPU_FREQ_200M: {
1415 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1417 case VPU_FREQ_266M: {
1418 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1420 case VPU_FREQ_300M: {
1421 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1423 case VPU_FREQ_400M: {
1424 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1426 case VPU_FREQ_500M: {
1427 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1429 case VPU_FREQ_600M: {
1430 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1433 unsigned long rate = 300*MHZ;
1435 if (of_machine_is_compatible("rockchip,rk2928g"))
1438 clk_set_rate(pservice->aclk_vcodec, rate);
1443 static void reg_copy_to_hw(struct vpu_subdev_data *data, struct vpu_reg *reg)
1445 struct vpu_service_info *pservice = data->pservice;
1446 struct vpu_task_info *task = reg->task;
1447 struct vpu_hw_info *hw_info = data->hw_info;
1449 u32 *src = (u32 *)®->reg[0];
1450 u32 enable_mask = task->enable_mask;
1451 u32 gating_mask = task->gating_mask;
1452 u32 reg_en = task->reg_en;
1456 atomic_add(1, &pservice->total_running);
1457 atomic_add(1, ®->session->task_running);
1459 if (pservice->auto_freq)
1460 vpu_service_set_freq(pservice, reg);
1462 vcodec_enter_mode(data);
1464 switch (reg->type) {
1466 u32 *dst = data->enc_dev.regs;
1468 u32 end = hw_info->enc_reg_num;
1469 /* u32 reg_gating = task->reg_gating; */
1471 pservice->reg_codec = reg;
1473 vpu_debug(DEBUG_TASK_INFO, "reg: base %3d end %d en %2d mask: en %x gate %x\n",
1474 base, end, reg_en, enable_mask, gating_mask);
1476 VEPU_CLEAN_CACHE(dst);
1478 if (debug & DEBUG_SET_REG)
1479 for (i = base; i < end; i++)
1480 vpu_debug(DEBUG_SET_REG, "set reg[%02d] %08x\n",
1484 * NOTE: encoder need to setup mode first
1486 writel_relaxed(src[reg_en] & enable_mask, dst + reg_en);
1488 /* NOTE: encoder gating is not on enable register */
1489 /* src[reg_gating] |= gating_mask; */
1491 for (i = base; i < end; i++) {
1493 writel_relaxed(src[i], dst + i);
1496 writel(src[reg_en], dst + reg_en);
1499 time_record(reg->task, 0);
1502 u32 *dst = data->dec_dev.regs;
1503 u32 len = hw_info->dec_reg_num;
1504 u32 base = hw_info->base_dec;
1505 u32 end = hw_info->end_dec;
1507 pservice->reg_codec = reg;
1509 vpu_debug(DEBUG_TASK_INFO, "reg: base %3d end %d en %2d mask: en %x gate %x\n",
1510 base, end, reg_en, enable_mask, gating_mask);
1512 VDPU_CLEAN_CACHE(dst);
1514 /* on rkvdec set cache size to 64byte */
1515 if (pservice->dev_id == VCODEC_DEVICE_ID_RKVDEC) {
1516 u32 *cache_base = dst + 0x100;
1517 u32 val = (debug & DEBUG_CACHE_32B) ? (0x3) : (0x13);
1518 writel_relaxed(val, cache_base + 0x07);
1519 writel_relaxed(val, cache_base + 0x17);
1522 if (debug & DEBUG_SET_REG)
1523 for (i = 0; i < len; i++)
1524 vpu_debug(DEBUG_SET_REG, "set reg[%02d] %08x\n",
1527 * NOTE: The end register is invalid. Do NOT write to it
1528 * Also the base register must be written
1530 for (i = base; i < end; i++) {
1532 writel_relaxed(src[i], dst + i);
1535 writel(src[reg_en] | gating_mask, dst + reg_en);
1538 time_record(reg->task, 0);
1541 u32 *dst = data->dec_dev.regs;
1542 u32 base = hw_info->base_pp;
1543 u32 end = hw_info->end_pp;
1545 pservice->reg_pproc = reg;
1547 vpu_debug(DEBUG_TASK_INFO, "reg: base %3d end %d en %2d mask: en %x gate %x\n",
1548 base, end, reg_en, enable_mask, gating_mask);
1550 if (debug & DEBUG_SET_REG)
1551 for (i = base; i < end; i++)
1552 vpu_debug(DEBUG_SET_REG, "set reg[%02d] %08x\n",
1555 for (i = base; i < end; i++) {
1557 writel_relaxed(src[i], dst + i);
1560 writel(src[reg_en] | gating_mask, dst + reg_en);
1563 time_record(reg->task, 0);
1566 u32 *dst = data->dec_dev.regs;
1567 u32 base = hw_info->base_dec_pp;
1568 u32 end = hw_info->end_dec_pp;
1570 pservice->reg_codec = reg;
1571 pservice->reg_pproc = reg;
1573 vpu_debug(DEBUG_TASK_INFO, "reg: base %3d end %d en %2d mask: en %x gate %x\n",
1574 base, end, reg_en, enable_mask, gating_mask);
1576 /* VDPU_SOFT_RESET(dst); */
1577 VDPU_CLEAN_CACHE(dst);
1579 if (debug & DEBUG_SET_REG)
1580 for (i = base; i < end; i++)
1581 vpu_debug(DEBUG_SET_REG, "set reg[%02d] %08x\n",
1584 for (i = base; i < end; i++) {
1586 writel_relaxed(src[i], dst + i);
1589 /* NOTE: dec output must be disabled */
1591 writel(src[reg_en] | gating_mask, dst + reg_en);
1594 time_record(reg->task, 0);
1597 vpu_err("error: unsupport session type %d", reg->type);
1598 atomic_sub(1, &pservice->total_running);
1599 atomic_sub(1, ®->session->task_running);
1606 static void try_set_reg(struct vpu_subdev_data *data)
1608 struct vpu_service_info *pservice = data->pservice;
1612 mutex_lock(&pservice->shutdown_lock);
1613 if (atomic_read(&pservice->service_on) == 0) {
1614 mutex_unlock(&pservice->shutdown_lock);
1617 if (!list_empty(&pservice->waiting)) {
1618 struct vpu_reg *reg_codec = pservice->reg_codec;
1619 struct vpu_reg *reg_pproc = pservice->reg_pproc;
1621 bool change_able = (reg_codec == NULL) && (reg_pproc == NULL);
1622 int reset_request = atomic_read(&pservice->reset_request);
1623 struct vpu_reg *reg = list_entry(pservice->waiting.next,
1624 struct vpu_reg, status_link);
1626 if (change_able || !reset_request) {
1627 switch (reg->type) {
1633 if (reg_codec == NULL)
1635 if (pservice->auto_freq && (reg_pproc != NULL))
1639 if (reg_codec == NULL) {
1640 if (reg_pproc == NULL)
1643 if ((reg_codec->type == VPU_DEC) &&
1644 (reg_pproc == NULL))
1649 * can not charge frequency
1650 * when vpu is working
1652 if (pservice->auto_freq)
1661 dev_err(pservice->dev,
1662 "undefined reg type %d\n",
1668 /* then check reset request */
1669 if (reset_request && !change_able)
1672 /* do reset before setting registers */
1677 reg_from_wait_to_run(pservice, reg);
1678 reg_copy_to_hw(reg->data, reg);
1682 mutex_unlock(&pservice->shutdown_lock);
1686 static int return_reg(struct vpu_subdev_data *data,
1687 struct vpu_reg *reg, u32 __user *dst)
1689 struct vpu_hw_info *hw_info = data->hw_info;
1690 size_t size = reg->size;
1694 switch (reg->type) {
1699 base = hw_info->base_dec_pp;
1702 base = hw_info->base_pp;
1705 base = hw_info->base_dec_pp;
1708 vpu_err("error: copy reg to user with unknown type %d\n",
1714 if (copy_to_user(dst, ®->reg[base], size)) {
1715 vpu_err("error: copy_to_user failed\n");
1719 reg_deinit(data, reg);
1724 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1727 struct vpu_subdev_data *data =
1728 container_of(filp->f_path.dentry->d_inode->i_cdev,
1729 struct vpu_subdev_data, cdev);
1730 struct vpu_service_info *pservice = data->pservice;
1731 struct vpu_session *session = (struct vpu_session *)filp->private_data;
1734 if (NULL == session)
1738 case VPU_IOC_SET_CLIENT_TYPE: {
1739 session->type = (enum VPU_CLIENT_TYPE)arg;
1740 vpu_debug(DEBUG_IOCTL, "pid %d set client type %d\n",
1741 session->pid, session->type);
1743 case VPU_IOC_GET_HW_FUSE_STATUS: {
1744 struct vpu_request req;
1746 vpu_debug(DEBUG_IOCTL, "pid %d get hw status %d\n",
1747 session->pid, session->type);
1748 if (copy_from_user(&req, (void __user *)arg, sizeof(req))) {
1749 vpu_err("error: get hw status copy_from_user failed\n");
1752 void *config = (session->type != VPU_ENC) ?
1753 ((void *)&pservice->dec_config) :
1754 ((void *)&pservice->enc_config);
1755 size_t size = (session->type != VPU_ENC) ?
1756 (sizeof(struct vpu_dec_config)) :
1757 (sizeof(struct vpu_enc_config));
1758 if (copy_to_user((void __user *)req.req,
1760 vpu_err("error: get hw status copy_to_user failed type %d\n",
1766 case VPU_IOC_SET_REG: {
1767 struct vpu_request req;
1768 struct vpu_reg *reg;
1770 vpu_service_power_on(data, pservice);
1772 vpu_debug(DEBUG_IOCTL, "pid %d set reg type %d\n",
1773 session->pid, session->type);
1774 if (copy_from_user(&req, (void __user *)arg,
1775 sizeof(struct vpu_request))) {
1776 vpu_err("error: set reg copy_from_user failed\n");
1780 reg = reg_init(data, session, (void __user *)req.req, req.size);
1784 mutex_lock(&pservice->lock);
1786 mutex_unlock(&pservice->lock);
1789 case VPU_IOC_GET_REG: {
1790 struct vpu_request req;
1791 struct vpu_reg *reg;
1794 vpu_service_power_on(data, pservice);
1796 vpu_debug(DEBUG_IOCTL, "pid %d get reg type %d\n",
1797 session->pid, session->type);
1798 if (copy_from_user(&req, (void __user *)arg,
1799 sizeof(struct vpu_request))) {
1800 vpu_err("error: get reg copy_from_user failed\n");
1804 ret = wait_event_timeout(session->wait,
1805 !list_empty(&session->done),
1808 if (!list_empty(&session->done)) {
1810 vpu_err("warning: pid %d wait task error ret %d\n",
1814 if (unlikely(ret < 0)) {
1815 vpu_err("error: pid %d wait task ret %d\n",
1817 } else if (ret == 0) {
1818 vpu_err("error: pid %d wait %d task done timeout\n",
1820 atomic_read(&session->task_running));
1826 int task_running = atomic_read(&session->task_running);
1828 mutex_lock(&pservice->lock);
1829 vpu_service_dump(pservice);
1831 atomic_set(&session->task_running, 0);
1832 atomic_sub(task_running,
1833 &pservice->total_running);
1834 dev_err(pservice->dev,
1835 "%d task is running but not return, reset hardware...",
1838 dev_err(pservice->dev, "done\n");
1840 vpu_service_session_clear(data, session);
1841 mutex_unlock(&pservice->lock);
1845 mutex_lock(&pservice->lock);
1846 reg = list_entry(session->done.next,
1847 struct vpu_reg, session_link);
1848 return_reg(data, reg, (u32 __user *)req.req);
1849 mutex_unlock(&pservice->lock);
1851 case VPU_IOC_PROBE_IOMMU_STATUS: {
1852 int iommu_enable = 1;
1854 vpu_debug(DEBUG_IOCTL, "VPU_IOC_PROBE_IOMMU_STATUS\n");
1856 if (copy_to_user((void __user *)arg,
1857 &iommu_enable, sizeof(int))) {
1858 vpu_err("error: iommu status copy_to_user failed\n");
1863 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1870 #ifdef CONFIG_COMPAT
1871 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1874 struct vpu_subdev_data *data =
1875 container_of(filp->f_path.dentry->d_inode->i_cdev,
1876 struct vpu_subdev_data, cdev);
1877 struct vpu_service_info *pservice = data->pservice;
1878 struct vpu_session *session = (struct vpu_session *)filp->private_data;
1881 vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1882 (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1883 if (NULL == session)
1887 case COMPAT_VPU_IOC_SET_CLIENT_TYPE: {
1888 session->type = (enum VPU_CLIENT_TYPE)arg;
1889 vpu_debug(DEBUG_IOCTL, "compat set client type %d\n",
1892 case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS: {
1893 struct compat_vpu_request req;
1895 vpu_debug(DEBUG_IOCTL, "compat get hw status %d\n",
1897 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1898 sizeof(struct compat_vpu_request))) {
1899 vpu_err("error: compat get hw status copy_from_user failed\n");
1902 void *config = (session->type != VPU_ENC) ?
1903 ((void *)&pservice->dec_config) :
1904 ((void *)&pservice->enc_config);
1905 size_t size = (session->type != VPU_ENC) ?
1906 (sizeof(struct vpu_dec_config)) :
1907 (sizeof(struct vpu_enc_config));
1909 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1911 vpu_err("error: compat get hw status copy_to_user failed type %d\n",
1917 case COMPAT_VPU_IOC_SET_REG: {
1918 struct compat_vpu_request req;
1919 struct vpu_reg *reg;
1921 vpu_service_power_on(data, pservice);
1923 vpu_debug(DEBUG_IOCTL, "compat set reg type %d\n",
1925 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1926 sizeof(struct compat_vpu_request))) {
1927 vpu_err("compat set_reg copy_from_user failed\n");
1930 reg = reg_init(data, session,
1931 compat_ptr((compat_uptr_t)req.req), req.size);
1935 mutex_lock(&pservice->lock);
1937 mutex_unlock(&pservice->lock);
1940 case COMPAT_VPU_IOC_GET_REG: {
1941 struct compat_vpu_request req;
1942 struct vpu_reg *reg;
1945 vpu_service_power_on(data, pservice);
1947 vpu_debug(DEBUG_IOCTL, "compat get reg type %d\n",
1949 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1950 sizeof(struct compat_vpu_request))) {
1951 vpu_err("compat get reg copy_from_user failed\n");
1955 ret = wait_event_timeout(session->wait,
1956 !list_empty(&session->done),
1959 if (!list_empty(&session->done)) {
1961 vpu_err("warning: pid %d wait task error ret %d\n",
1965 if (unlikely(ret < 0)) {
1966 vpu_err("error: pid %d wait task ret %d\n",
1968 } else if (ret == 0) {
1969 vpu_err("error: pid %d wait %d task done timeout\n",
1971 atomic_read(&session->task_running));
1977 int task_running = atomic_read(&session->task_running);
1979 mutex_lock(&pservice->lock);
1980 vpu_service_dump(pservice);
1982 atomic_set(&session->task_running, 0);
1983 atomic_sub(task_running,
1984 &pservice->total_running);
1985 dev_err(pservice->dev,
1986 "%d task is running but not return, reset hardware...",
1989 dev_err(pservice->dev, "done\n");
1991 vpu_service_session_clear(data, session);
1992 mutex_unlock(&pservice->lock);
1996 mutex_lock(&pservice->lock);
1997 reg = list_entry(session->done.next,
1998 struct vpu_reg, session_link);
1999 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
2000 mutex_unlock(&pservice->lock);
2002 case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS: {
2003 int iommu_enable = 1;
2005 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_PROBE_IOMMU_STATUS\n");
2007 if (copy_to_user(compat_ptr((compat_uptr_t)arg),
2008 &iommu_enable, sizeof(int))) {
2009 vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
2014 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
2022 static int vpu_service_check_hw(struct vpu_subdev_data *data)
2024 struct vpu_service_info *pservice = data->pservice;
2025 int ret = -EINVAL, i = 0;
2026 u32 hw_id = readl_relaxed(data->regs);
2028 hw_id = (hw_id >> 16) & 0xFFFF;
2029 dev_info(pservice->dev, "checking hw id %x\n", hw_id);
2030 data->hw_info = NULL;
2032 for (i = 0; i < ARRAY_SIZE(vcodec_info_set); i++) {
2033 const struct vcodec_info *info = &vcodec_info_set[i];
2035 if (hw_id == info->hw_id) {
2036 data->hw_id = info->hw_id;
2037 data->hw_info = info->hw_info;
2038 data->task_info = info->task_info;
2039 data->trans_info = info->trans_info;
2047 static int vpu_service_open(struct inode *inode, struct file *filp)
2049 struct vpu_subdev_data *data = container_of(
2050 inode->i_cdev, struct vpu_subdev_data, cdev);
2051 struct vpu_service_info *pservice = data->pservice;
2052 struct vpu_session *session = NULL;
2056 session = kzalloc(sizeof(*session), GFP_KERNEL);
2058 vpu_err("error: unable to allocate memory for vpu_session.");
2062 data->iommu_info->debug_level = debug;
2064 session->type = VPU_TYPE_BUTT;
2065 session->pid = current->pid;
2066 INIT_LIST_HEAD(&session->waiting);
2067 INIT_LIST_HEAD(&session->running);
2068 INIT_LIST_HEAD(&session->done);
2069 INIT_LIST_HEAD(&session->list_session);
2070 init_waitqueue_head(&session->wait);
2071 atomic_set(&session->task_running, 0);
2072 mutex_lock(&pservice->lock);
2073 list_add_tail(&session->list_session, &pservice->session);
2074 filp->private_data = (void *)session;
2075 mutex_unlock(&pservice->lock);
2077 dev_dbg(pservice->dev, "dev opened\n");
2079 return nonseekable_open(inode, filp);
2082 static int vpu_service_release(struct inode *inode, struct file *filp)
2084 struct vpu_subdev_data *data = container_of(
2085 inode->i_cdev, struct vpu_subdev_data, cdev);
2086 struct vpu_service_info *pservice = data->pservice;
2088 struct vpu_session *session = (struct vpu_session *)filp->private_data;
2091 if (NULL == session)
2094 task_running = atomic_read(&session->task_running);
2096 dev_err(pservice->dev,
2097 "error: session %d still has %d task running when closing\n",
2098 session->pid, task_running);
2101 wake_up(&session->wait);
2103 vpu_service_power_on(data, pservice);
2104 mutex_lock(&pservice->lock);
2105 /* remove this filp from the asynchronusly notified filp's */
2106 list_del_init(&session->list_session);
2107 vpu_service_session_clear(data, session);
2108 vcodec_iommu_clear(data->iommu_info, session);
2110 filp->private_data = NULL;
2111 mutex_unlock(&pservice->lock);
2113 dev_info(pservice->dev, "closed\n");
2118 static const struct file_operations vpu_service_fops = {
2119 .unlocked_ioctl = vpu_service_ioctl,
2120 .open = vpu_service_open,
2121 .release = vpu_service_release,
2122 #ifdef CONFIG_COMPAT
2123 .compat_ioctl = compat_vpu_service_ioctl,
2127 static irqreturn_t vdpu_irq(int irq, void *dev_id);
2128 static irqreturn_t vdpu_isr(int irq, void *dev_id);
2129 static irqreturn_t vepu_irq(int irq, void *dev_id);
2130 static irqreturn_t vepu_isr(int irq, void *dev_id);
2131 static void get_hw_info(struct vpu_subdev_data *data);
2133 static struct device *rockchip_get_sysmmu_dev(const char *compt)
2135 struct device_node *dn = NULL;
2136 struct platform_device *pd = NULL;
2137 struct device *ret = NULL;
2139 dn = of_find_compatible_node(NULL, NULL, compt);
2141 pr_err("can't find device node %s \r\n", compt);
2145 pd = of_find_device_by_node(dn);
2147 pr_err("can't find platform device in device node %s\n", compt);
2155 #ifdef CONFIG_IOMMU_API
2156 static inline void platform_set_sysmmu(struct device *iommu,
2159 dev->archdata.iommu = iommu;
2162 static inline void platform_set_sysmmu(struct device *iommu,
2168 int vcodec_sysmmu_fault_hdl(struct device *dev,
2169 enum rk_iommu_inttype itype,
2170 unsigned long pgtable_base,
2171 unsigned long fault_addr, unsigned int status)
2173 struct platform_device *pdev;
2174 struct vpu_service_info *pservice;
2175 struct vpu_subdev_data *data;
2180 pr_err("invalid NULL dev\n");
2184 pdev = container_of(dev, struct platform_device, dev);
2186 pr_err("invalid NULL platform_device\n");
2190 data = platform_get_drvdata(pdev);
2192 pr_err("invalid NULL vpu_subdev_data\n");
2196 pservice = data->pservice;
2197 if (pservice == NULL) {
2198 pr_err("invalid NULL vpu_service_info\n");
2202 if (pservice->reg_codec) {
2203 struct vpu_reg *reg = pservice->reg_codec;
2204 struct vcodec_mem_region *mem, *n;
2207 pr_err("vcodec, fault addr 0x%08lx\n", fault_addr);
2208 if (!list_empty(®->mem_region_list)) {
2209 list_for_each_entry_safe(mem, n, ®->mem_region_list,
2211 pr_err("vcodec, reg[%02u] mem region [%02d] 0x%lx %lx\n",
2212 mem->reg_idx, i, mem->iova, mem->len);
2216 pr_err("no memory region mapped\n");
2220 struct vpu_subdev_data *data = reg->data;
2221 u32 *base = (u32 *)data->dec_dev.regs;
2222 u32 len = data->hw_info->dec_reg_num;
2224 pr_err("current errror register set:\n");
2226 for (i = 0; i < len; i++)
2227 pr_err("reg[%02d] %08x\n",
2228 i, readl_relaxed(base + i));
2231 pr_alert("vcodec, page fault occur, reset hw\n");
2233 /* reg->reg[101] = 1; */
2240 static int vcodec_subdev_probe(struct platform_device *pdev,
2241 struct vpu_service_info *pservice)
2243 uint8_t *regs = NULL;
2245 uint32_t ioaddr = 0;
2246 struct resource *res = NULL;
2247 struct vpu_hw_info *hw_info = NULL;
2248 struct device *dev = &pdev->dev;
2249 struct device_node *np = pdev->dev.of_node;
2250 struct vpu_subdev_data *data = NULL;
2251 struct platform_device *sub_dev = NULL;
2252 struct device_node *sub_np = NULL;
2253 const char *name = np->name;
2254 char mmu_dev_dts_name[40];
2256 dev_info(dev, "probe device");
2258 data = devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
2262 data->pservice = pservice;
2264 of_property_read_u32(np, "dev_mode", (u32 *)&data->mode);
2266 if (pservice->reg_base == 0) {
2267 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2268 data->regs = devm_ioremap_resource(dev, res);
2269 if (IS_ERR(data->regs)) {
2270 ret = PTR_ERR(data->regs);
2273 ioaddr = res->start;
2275 data->regs = pservice->reg_base;
2276 ioaddr = pservice->ioaddr;
2279 sub_np = of_parse_phandle(np, "iommus", 0);
2281 sub_dev = of_find_device_by_node(sub_np);
2282 data->mmu_dev = &sub_dev->dev;
2285 /* Back to legacy iommu probe */
2286 if (!data->mmu_dev) {
2287 switch (data->mode) {
2288 case VCODEC_RUNNING_MODE_VPU:
2289 sprintf(mmu_dev_dts_name,
2290 VPU_IOMMU_COMPATIBLE_NAME);
2292 case VCODEC_RUNNING_MODE_RKVDEC:
2293 sprintf(mmu_dev_dts_name,
2294 VDEC_IOMMU_COMPATIBLE_NAME);
2296 case VCODEC_RUNNING_MODE_HEVC:
2298 sprintf(mmu_dev_dts_name,
2299 HEVC_IOMMU_COMPATIBLE_NAME);
2304 rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2306 platform_set_sysmmu(data->mmu_dev, dev);
2308 rockchip_iovmm_set_fault_handler
2309 (dev, vcodec_sysmmu_fault_hdl);
2312 dev_info(dev, "vpu mmu dec %p\n", data->mmu_dev);
2314 clear_bit(MMU_ACTIVATED, &data->state);
2315 vpu_service_power_on(data, pservice);
2317 ret = vpu_service_check_hw(data);
2319 vpu_err("error: hw info check faild\n");
2323 hw_info = data->hw_info;
2324 regs = (u8 *)data->regs;
2326 if (hw_info->dec_reg_num) {
2327 data->dec_dev.iosize = hw_info->dec_io_size;
2328 data->dec_dev.regs = (u32 *)(regs + hw_info->dec_offset);
2331 if (hw_info->enc_reg_num) {
2332 data->enc_dev.iosize = hw_info->enc_io_size;
2333 data->enc_dev.regs = (u32 *)(regs + hw_info->enc_offset);
2336 data->reg_size = max(hw_info->dec_io_size, hw_info->enc_io_size);
2338 data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
2339 if (data->irq_enc > 0) {
2340 ret = devm_request_threaded_irq(dev, data->irq_enc,
2342 IRQF_SHARED, dev_name(dev),
2345 dev_err(dev, "error: can't request vepu irq %d\n",
2350 data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
2351 if (data->irq_dec > 0) {
2352 ret = devm_request_threaded_irq(dev, data->irq_dec,
2354 IRQF_SHARED, dev_name(dev),
2357 dev_err(dev, "error: can't request vdpu irq %d\n",
2362 atomic_set(&data->dec_dev.irq_count_codec, 0);
2363 atomic_set(&data->dec_dev.irq_count_pp, 0);
2364 atomic_set(&data->enc_dev.irq_count_codec, 0);
2365 atomic_set(&data->enc_dev.irq_count_pp, 0);
2367 vcodec_enter_mode(data);
2368 of_property_read_u32(np, "allocator", (u32 *)&pservice->alloc_type);
2369 data->iommu_info = vcodec_iommu_info_create(dev, data->mmu_dev,
2370 pservice->alloc_type);
2371 dev_info(dev, "allocator is %s\n", pservice->alloc_type == 1 ? "drm" :
2372 (pservice->alloc_type == 2 ? "ion" : "null"));
2374 pservice->auto_freq = true;
2376 vcodec_exit_mode(data);
2377 /* create device node */
2378 ret = alloc_chrdev_region(&data->dev_t, 0, 1, name);
2380 dev_err(dev, "alloc dev_t failed\n");
2384 cdev_init(&data->cdev, &vpu_service_fops);
2386 data->cdev.owner = THIS_MODULE;
2387 data->cdev.ops = &vpu_service_fops;
2389 ret = cdev_add(&data->cdev, data->dev_t, 1);
2392 dev_err(dev, "add dev_t failed\n");
2396 data->cls = class_create(THIS_MODULE, name);
2398 if (IS_ERR(data->cls)) {
2399 ret = PTR_ERR(data->cls);
2400 dev_err(dev, "class_create err:%d\n", ret);
2404 data->child_dev = device_create(data->cls, dev,
2405 data->dev_t, "%s", name);
2407 platform_set_drvdata(pdev, data);
2409 INIT_LIST_HEAD(&data->lnk_service);
2410 list_add_tail(&data->lnk_service, &pservice->subdev_list);
2414 if (data->child_dev) {
2415 device_destroy(data->cls, data->dev_t);
2416 cdev_del(&data->cdev);
2417 unregister_chrdev_region(data->dev_t, 1);
2421 class_destroy(data->cls);
2425 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2427 struct vpu_service_info *pservice = data->pservice;
2429 vcodec_iommu_info_destroy(data->iommu_info);
2430 data->iommu_info = NULL;
2432 mutex_lock(&pservice->lock);
2433 cancel_delayed_work_sync(&pservice->power_off_work);
2434 vpu_service_power_off(pservice);
2435 mutex_unlock(&pservice->lock);
2437 device_destroy(data->cls, data->dev_t);
2438 class_destroy(data->cls);
2439 cdev_del(&data->cdev);
2440 unregister_chrdev_region(data->dev_t, 1);
2442 #ifdef CONFIG_DEBUG_FS
2443 if (!IS_ERR_OR_NULL(data->debugfs_dir))
2444 debugfs_remove_recursive(data->debugfs_dir);
2448 static void vcodec_read_property(struct device_node *np,
2449 struct vpu_service_info *pservice)
2451 pservice->mode_bit = 0;
2452 pservice->mode_ctrl = 0;
2453 pservice->subcnt = 0;
2454 pservice->grf_base = NULL;
2456 of_property_read_u32(np, "subcnt", &pservice->subcnt);
2458 if (pservice->subcnt > 1) {
2459 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2460 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2462 #ifdef CONFIG_MFD_SYSCON
2463 pservice->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2464 if (IS_ERR_OR_NULL(pservice->grf)) {
2465 pservice->grf = NULL;
2467 pservice->grf_base = RK_GRF_VIRT;
2469 vpu_err("can't find vpu grf property\n");
2475 pservice->grf_base = RK_GRF_VIRT;
2477 vpu_err("can't find vpu grf property\n");
2482 #ifdef CONFIG_RESET_CONTROLLER
2483 pservice->rst_a = devm_reset_control_get(pservice->dev, "video_a");
2484 pservice->rst_h = devm_reset_control_get(pservice->dev, "video_h");
2485 pservice->rst_v = devm_reset_control_get(pservice->dev, "video");
2487 if (IS_ERR_OR_NULL(pservice->rst_a)) {
2488 dev_warn(pservice->dev, "No aclk reset resource define\n");
2489 pservice->rst_a = NULL;
2492 if (IS_ERR_OR_NULL(pservice->rst_h)) {
2493 dev_warn(pservice->dev, "No hclk reset resource define\n");
2494 pservice->rst_h = NULL;
2497 if (IS_ERR_OR_NULL(pservice->rst_v)) {
2498 dev_warn(pservice->dev, "No core reset resource define\n");
2499 pservice->rst_v = NULL;
2503 of_property_read_string(np, "name", (const char **)&pservice->name);
2506 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2508 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2509 pservice->curr_mode = -1;
2511 wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2512 INIT_LIST_HEAD(&pservice->waiting);
2513 INIT_LIST_HEAD(&pservice->running);
2514 mutex_init(&pservice->lock);
2515 mutex_init(&pservice->shutdown_lock);
2516 atomic_set(&pservice->service_on, 1);
2518 INIT_LIST_HEAD(&pservice->done);
2519 INIT_LIST_HEAD(&pservice->session);
2520 INIT_LIST_HEAD(&pservice->subdev_list);
2522 pservice->reg_pproc = NULL;
2523 atomic_set(&pservice->total_running, 0);
2524 atomic_set(&pservice->enabled, 0);
2525 atomic_set(&pservice->power_on_cnt, 0);
2526 atomic_set(&pservice->power_off_cnt, 0);
2527 atomic_set(&pservice->reset_request, 0);
2529 INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2530 pservice->last.tv64 = 0;
2532 pservice->alloc_type = 0;
2535 static int vcodec_probe(struct platform_device *pdev)
2539 struct resource *res = NULL;
2540 struct device *dev = &pdev->dev;
2541 struct device_node *np = pdev->dev.of_node;
2542 struct vpu_service_info *pservice = NULL;
2543 struct vcodec_device_info *driver_data;
2545 pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info),
2549 pservice->dev = dev;
2551 driver_data = vcodec_get_drv_data(pdev);
2555 vcodec_read_property(np, pservice);
2556 vcodec_init_drvdata(pservice);
2558 /* Underscore for label, hyphens for name */
2559 switch (driver_data->device_type) {
2560 case VCODEC_DEVICE_TYPE_VPUX:
2561 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2563 case VCODEC_DEVICE_TYPE_VPUC:
2564 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2566 case VCODEC_DEVICE_TYPE_HEVC:
2567 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2569 case VCODEC_DEVICE_TYPE_RKVD:
2570 pservice->dev_id = VCODEC_DEVICE_ID_RKVDEC;
2573 dev_err(dev, "unsupported device type\n");
2577 if (0 > vpu_get_clk(pservice))
2580 if (of_property_read_bool(np, "reg")) {
2581 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2583 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2584 if (IS_ERR(pservice->reg_base)) {
2585 vpu_err("ioremap registers base failed\n");
2586 ret = PTR_ERR(pservice->reg_base);
2589 pservice->ioaddr = res->start;
2591 pservice->reg_base = 0;
2594 pm_runtime_enable(dev);
2596 if (of_property_read_bool(np, "subcnt")) {
2597 for (i = 0; i < pservice->subcnt; i++) {
2598 struct device_node *sub_np;
2599 struct platform_device *sub_pdev;
2601 sub_np = of_parse_phandle(np, "rockchip,sub", i);
2602 sub_pdev = of_find_device_by_node(sub_np);
2604 vcodec_subdev_probe(sub_pdev, pservice);
2607 vcodec_subdev_probe(pdev, pservice);
2610 vpu_service_power_off(pservice);
2612 dev_info(dev, "init success\n");
2617 dev_info(dev, "init failed\n");
2618 vpu_service_power_off(pservice);
2619 wake_lock_destroy(&pservice->wake_lock);
2624 static int vcodec_remove(struct platform_device *pdev)
2626 struct vpu_subdev_data *data = platform_get_drvdata(pdev);
2628 vcodec_subdev_remove(data);
2630 pm_runtime_disable(data->pservice->dev);
2635 static void vcodec_shutdown(struct platform_device *pdev)
2637 struct vpu_subdev_data *data = platform_get_drvdata(pdev);
2638 struct vpu_service_info *pservice = data->pservice;
2640 dev_info(&pdev->dev, "vcodec shutdown");
2642 mutex_lock(&pservice->shutdown_lock);
2643 atomic_set(&pservice->service_on, 0);
2644 mutex_unlock(&pservice->shutdown_lock);
2646 vcodec_exit_mode(data);
2648 vpu_service_power_on(data, pservice);
2649 vpu_service_clear(data);
2650 vcodec_subdev_remove(data);
2652 pm_runtime_disable(&pdev->dev);
2655 static const struct of_device_id vcodec_service_dt_ids[] = {
2657 .compatible = "rockchip,vpu_service",
2658 .data = &vpu_device_info,
2661 .compatible = "rockchip,hevc_service",
2662 .data = &hevc_device_info,
2665 .compatible = "rockchip,vpu_combo",
2666 .data = &vpu_combo_device_info,
2669 .compatible = "rockchip,rkvdec",
2670 .data = &rkvd_device_info,
2675 MODULE_DEVICE_TABLE(of, vcodec_service_dt_ids);
2677 static void *vcodec_get_drv_data(struct platform_device *pdev)
2679 struct vcodec_device_info *driver_data = NULL;
2680 const struct of_device_id *match;
2682 match = of_match_node(vcodec_service_dt_ids, pdev->dev.of_node);
2684 driver_data = (struct vcodec_device_info *)match->data;
2689 static struct platform_driver vcodec_driver = {
2690 .probe = vcodec_probe,
2691 .remove = vcodec_remove,
2692 .shutdown = vcodec_shutdown,
2694 .name = "rk-vcodec",
2695 .owner = THIS_MODULE,
2696 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2700 static void get_hw_info(struct vpu_subdev_data *data)
2702 struct vpu_service_info *pservice = data->pservice;
2703 struct vpu_dec_config *dec = &pservice->dec_config;
2704 struct vpu_enc_config *enc = &pservice->enc_config;
2706 if (of_machine_is_compatible("rockchip,rk2928") ||
2707 of_machine_is_compatible("rockchip,rk3036") ||
2708 of_machine_is_compatible("rockchip,rk3066") ||
2709 of_machine_is_compatible("rockchip,rk3126") ||
2710 of_machine_is_compatible("rockchip,rk3188"))
2711 dec->max_dec_pic_width = 1920;
2713 dec->max_dec_pic_width = 4096;
2715 if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2716 dec->h264_support = 3;
2717 dec->jpeg_support = 1;
2718 dec->mpeg4_support = 2;
2719 dec->vc1_support = 3;
2720 dec->mpeg2_support = 1;
2721 dec->pp_support = 1;
2722 dec->sorenson_support = 1;
2723 dec->ref_buf_support = 3;
2724 dec->vp6_support = 1;
2725 dec->vp7_support = 1;
2726 dec->vp8_support = 1;
2727 dec->avs_support = 1;
2728 dec->jpeg_ext_support = 0;
2729 dec->custom_mpeg4_support = 1;
2731 dec->mvc_support = 1;
2733 if (!of_machine_is_compatible("rockchip,rk3036")) {
2734 u32 config_reg = readl_relaxed(data->enc_dev.regs + 63);
2736 enc->max_encoded_width = config_reg & ((1 << 11) - 1);
2737 enc->h264_enabled = 1;
2738 enc->mpeg4_enabled = (config_reg >> 26) & 1;
2739 enc->jpeg_enabled = 1;
2740 enc->vs_enabled = (config_reg >> 24) & 1;
2741 enc->rgb_enabled = (config_reg >> 28) & 1;
2742 enc->reg_size = data->reg_size;
2747 pservice->auto_freq = true;
2748 vpu_debug(DEBUG_EXTRA_INFO, "vpu_service set to auto frequency mode\n");
2749 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2751 pservice->bug_dec_addr = of_machine_is_compatible
2752 ("rockchip,rk30xx");
2753 } else if (data->mode == VCODEC_RUNNING_MODE_RKVDEC) {
2754 pservice->auto_freq = true;
2755 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2757 /* disable frequency switch in hevc.*/
2758 pservice->auto_freq = false;
2762 static bool check_irq_err(struct vpu_task_info *task, u32 irq_status)
2764 vpu_debug(DEBUG_IRQ_CHECK, "task %s status %08x mask %08x\n",
2765 task->name, irq_status, task->error_mask);
2767 return (task->error_mask & irq_status) ? true : false;
2770 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2772 struct vpu_subdev_data *data = (struct vpu_subdev_data *)dev_id;
2773 struct vpu_service_info *pservice = data->pservice;
2774 struct vpu_task_info *task = NULL;
2775 struct vpu_device *dev = &data->dec_dev;
2776 u32 hw_id = data->hw_info->hw_id;
2780 task = &data->task_info[TASK_DEC];
2782 raw_status = readl_relaxed(dev->regs + task->reg_irq);
2783 dec_status = raw_status;
2785 vpu_debug(DEBUG_TASK_INFO, "vdpu_irq reg %d status %x mask: irq %x ready %x error %0x\n",
2786 task->reg_irq, dec_status,
2787 task->irq_mask, task->ready_mask, task->error_mask);
2789 if (dec_status & task->irq_mask) {
2790 time_record(task, 1);
2791 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq dec status %08x\n",
2793 if ((dec_status & 0x40001) == 0x40001) {
2796 readl_relaxed(dev->regs +
2798 } while ((dec_status & 0x40001) == 0x40001);
2801 if (check_irq_err(task, dec_status))
2802 atomic_add(1, &pservice->reset_request);
2804 writel_relaxed(0, dev->regs + task->reg_irq);
2806 /* set clock gating to save power */
2807 writel(task->gating_mask, dev->regs + task->reg_en);
2809 atomic_add(1, &dev->irq_count_codec);
2813 task = &data->task_info[TASK_PP];
2814 if (hw_id != HEVC_ID && hw_id != RKV_DEC_ID) {
2815 u32 pp_status = readl_relaxed(dev->regs + task->irq_mask);
2817 if (pp_status & task->irq_mask) {
2818 time_record(task, 1);
2819 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq pp status %08x\n",
2822 if (check_irq_err(task, dec_status))
2823 atomic_add(1, &pservice->reset_request);
2826 writel_relaxed(pp_status & (~task->reg_irq),
2827 dev->regs + task->irq_mask);
2828 atomic_add(1, &dev->irq_count_pp);
2833 pservice->irq_status = raw_status;
2835 if (atomic_read(&dev->irq_count_pp) ||
2836 atomic_read(&dev->irq_count_codec))
2837 return IRQ_WAKE_THREAD;
2842 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2844 struct vpu_subdev_data *data = (struct vpu_subdev_data *)dev_id;
2845 struct vpu_service_info *pservice = data->pservice;
2846 struct vpu_device *dev = &data->dec_dev;
2848 mutex_lock(&pservice->lock);
2849 if (atomic_read(&dev->irq_count_codec)) {
2850 atomic_sub(1, &dev->irq_count_codec);
2851 if (pservice->reg_codec == NULL) {
2852 vpu_err("error: dec isr with no task waiting\n");
2854 reg_from_run_to_done(data, pservice->reg_codec);
2855 /* avoid vpu timeout and can't recover problem */
2856 if (data->mode == VCODEC_RUNNING_MODE_VPU)
2857 VDPU_SOFT_RESET(data->regs);
2861 if (atomic_read(&dev->irq_count_pp)) {
2862 atomic_sub(1, &dev->irq_count_pp);
2863 if (pservice->reg_pproc == NULL)
2864 vpu_err("error: pp isr with no task waiting\n");
2866 reg_from_run_to_done(data, pservice->reg_pproc);
2869 mutex_unlock(&pservice->lock);
2873 static irqreturn_t vepu_irq(int irq, void *dev_id)
2875 struct vpu_subdev_data *data = (struct vpu_subdev_data *)dev_id;
2876 struct vpu_service_info *pservice = data->pservice;
2877 struct vpu_task_info *task = &data->task_info[TASK_ENC];
2878 struct vpu_device *dev = &data->enc_dev;
2881 irq_status = readl_relaxed(dev->regs + task->reg_irq);
2883 vpu_debug(DEBUG_TASK_INFO, "vepu_irq reg %d status %x mask: irq %x ready %x error %0x\n",
2884 task->reg_irq, irq_status,
2885 task->irq_mask, task->ready_mask, task->error_mask);
2887 vpu_debug(DEBUG_IRQ_STATUS, "vepu_irq enc status %08x\n", irq_status);
2889 if (likely(irq_status & task->irq_mask)) {
2890 time_record(task, 1);
2892 if (check_irq_err(task, irq_status))
2893 atomic_add(1, &pservice->reset_request);
2896 writel_relaxed(irq_status & (~task->irq_mask),
2897 dev->regs + task->reg_irq);
2899 atomic_add(1, &dev->irq_count_codec);
2903 pservice->irq_status = irq_status;
2905 if (atomic_read(&dev->irq_count_codec))
2906 return IRQ_WAKE_THREAD;
2911 static irqreturn_t vepu_isr(int irq, void *dev_id)
2913 struct vpu_subdev_data *data = (struct vpu_subdev_data *)dev_id;
2914 struct vpu_service_info *pservice = data->pservice;
2915 struct vpu_device *dev = &data->enc_dev;
2917 mutex_lock(&pservice->lock);
2918 if (atomic_read(&dev->irq_count_codec)) {
2919 atomic_sub(1, &dev->irq_count_codec);
2920 if (NULL == pservice->reg_codec)
2921 vpu_err("error: enc isr with no task waiting\n");
2923 reg_from_run_to_done(data, pservice->reg_codec);
2926 mutex_unlock(&pservice->lock);
2930 module_platform_driver(vcodec_driver);
2931 MODULE_LICENSE("GPL v2");