2 * Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
3 * author: chenhengming, chm@rock-chips.com
4 * Alpha Lin, alpha.lin@rock-chips.com
5 * Jung Zhao, jung.zhao@rock-chips.com
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/clk.h>
21 #include <linux/compat.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/reset.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/wakelock.h>
33 #include <linux/cdev.h>
35 #include <linux/of_platform.h>
36 #include <linux/of_irq.h>
37 #include <linux/regmap.h>
38 #include <linux/mfd/syscon.h>
39 #include <linux/uaccess.h>
40 #include <linux/debugfs.h>
41 #include <linux/pm_runtime.h>
42 #include <linux/iopoll.h>
44 #include <linux/rockchip/cru.h>
45 #include <linux/rockchip/pmu.h>
46 #include <linux/rockchip/grf.h>
48 #include <linux/dma-buf.h>
49 #include <linux/rockchip-iovmm.h>
51 #include "vcodec_hw_info.h"
52 #include "vcodec_hw_vpu.h"
53 #include "vcodec_hw_rkv.h"
54 #include "vcodec_hw_vpu2.h"
56 #include "vcodec_service.h"
58 #include "vcodec_iommu_ops.h"
62 * +------+-------------------+
64 * +------+-------------------+
65 * 0~23 bit is for different information type
66 * 24~31 bit is for information print format
69 #define DEBUG_POWER 0x00000001
70 #define DEBUG_CLOCK 0x00000002
71 #define DEBUG_IRQ_STATUS 0x00000004
72 #define DEBUG_IOMMU 0x00000008
73 #define DEBUG_IOCTL 0x00000010
74 #define DEBUG_FUNCTION 0x00000020
75 #define DEBUG_REGISTER 0x00000040
76 #define DEBUG_EXTRA_INFO 0x00000080
77 #define DEBUG_TIMING 0x00000100
78 #define DEBUG_TASK_INFO 0x00000200
80 #define DEBUG_SET_REG 0x00001000
81 #define DEBUG_GET_REG 0x00002000
82 #define DEBUG_PPS_FILL 0x00004000
83 #define DEBUG_IRQ_CHECK 0x00008000
84 #define DEBUG_CACHE_32B 0x00010000
86 #define PRINT_FUNCTION 0x80000000
87 #define PRINT_LINE 0x40000000
89 #define MHZ (1000 * 1000)
90 #define SIZE_REG(reg) ((reg) * 4)
92 #define VCODEC_CLOCK_ENABLE 1
93 #define EXTRA_INFO_MAGIC 0x4C4A46
96 module_param(debug, int, S_IRUGO | S_IWUSR);
97 MODULE_PARM_DESC(debug, "bit switch for vcodec_service debug information");
99 * hardware information organization
101 * In order to support multiple hardware with different version the hardware
102 * information is organized as follow:
104 * 1. First, index hardware by register size / position.
105 * These information is fix for each hardware and do not relate to runtime
106 * work flow. It only related to resource allocation.
107 * Descriptor: struct vpu_hw_info
109 * 2. Then, index hardware by runtime configuration
110 * These information is related to runtime setting behave including enable
111 * register, irq register and other key control flag
112 * Descriptor: struct vpu_task_info
114 * 3. Final, on iommu case the fd translation is required
115 * Descriptor: struct vpu_trans_info
129 struct extra_info_elem {
135 struct extra_info_for_iommu {
138 struct extra_info_elem elem[20];
141 static const struct vcodec_info vcodec_info_set[] = {
143 .hw_id = VPU_ID_8270,
144 .hw_info = &hw_vpu_8270,
145 .task_info = task_vpu,
146 .trans_info = trans_vpu,
149 .hw_id = VPU_ID_4831,
150 .hw_info = &hw_vpu_4831,
151 .task_info = task_vpu,
152 .trans_info = trans_vpu,
155 .hw_id = VPU_DEC_ID_9190,
156 .hw_info = &hw_vpu_9190,
157 .task_info = task_vpu,
158 .trans_info = trans_vpu,
162 .hw_info = &hw_rkhevc,
163 .task_info = task_rkv,
164 .trans_info = trans_rkv,
168 .hw_info = &hw_rkvdec,
169 .task_info = task_rkv,
170 .trans_info = trans_rkv,
175 .task_info = task_vpu2,
176 .trans_info = trans_vpu2,
180 /* Both VPU1 and VPU2 */
181 static const struct vcodec_device_info vpu_device_info = {
182 .device_type = VCODEC_DEVICE_TYPE_VPUX,
183 .name = "vpu-service",
186 static const struct vcodec_device_info vpu_combo_device_info = {
187 .device_type = VCODEC_DEVICE_TYPE_VPUC,
191 static const struct vcodec_device_info hevc_device_info = {
192 .device_type = VCODEC_DEVICE_TYPE_HEVC,
193 .name = "hevc-service",
196 static const struct vcodec_device_info rkvd_device_info = {
197 .device_type = VCODEC_DEVICE_TYPE_RKVD,
203 #define vpu_debug_func(type, fmt, args...) \
205 if (unlikely(debug & type)) { \
206 pr_info("%s:%d: " fmt, \
207 __func__, __LINE__, ##args); \
210 #define vpu_debug(type, fmt, args...) \
212 if (unlikely(debug & type)) { \
213 pr_info(fmt, ##args); \
217 #define vpu_debug_func(level, fmt, args...)
218 #define vpu_debug(level, fmt, args...)
221 #define vpu_debug_enter() vpu_debug_func(DEBUG_FUNCTION, "enter\n")
222 #define vpu_debug_leave() vpu_debug_func(DEBUG_FUNCTION, "leave\n")
224 #define vpu_err(fmt, args...) \
225 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
244 * struct for process session which connect to vpu
246 * @author ChenHengming (2011-5-3)
249 enum VPU_CLIENT_TYPE type;
250 /* a linked list of data so we can access them for debugging */
251 struct list_head list_session;
252 /* a linked list of register data waiting for process */
253 struct list_head waiting;
254 /* a linked list of register data in processing */
255 struct list_head running;
256 /* a linked list of register data processed */
257 struct list_head done;
258 wait_queue_head_t wait;
260 atomic_t task_running;
264 * struct for process register set
266 * @author ChenHengming (2011-5-4)
269 enum VPU_CLIENT_TYPE type;
271 struct vpu_session *session;
272 struct vpu_subdev_data *data;
273 struct vpu_task_info *task;
274 const struct vpu_trans_info *trans;
276 /* link to vpu service session */
277 struct list_head session_link;
278 /* link to register set list */
279 struct list_head status_link;
282 struct list_head mem_region_list;
288 atomic_t irq_count_codec;
289 atomic_t irq_count_pp;
294 enum vcodec_device_id {
295 VCODEC_DEVICE_ID_VPU,
296 VCODEC_DEVICE_ID_HEVC,
297 VCODEC_DEVICE_ID_COMBO,
298 VCODEC_DEVICE_ID_RKVDEC,
299 VCODEC_DEVICE_ID_BUTT
302 enum VCODEC_RUNNING_MODE {
303 VCODEC_RUNNING_MODE_NONE = -1,
304 VCODEC_RUNNING_MODE_VPU,
305 VCODEC_RUNNING_MODE_HEVC,
306 VCODEC_RUNNING_MODE_RKVDEC
309 struct vcodec_mem_region {
310 struct list_head srv_lnk;
311 struct list_head reg_lnk;
312 struct list_head session_lnk;
313 unsigned long iova; /* virtual address for iommu */
320 MMU_ACTIVATED = BIT(0)
323 struct vpu_subdev_data {
327 struct device *child_dev;
331 struct vpu_service_info *pservice;
334 enum VCODEC_RUNNING_MODE mode;
335 struct list_head lnk_service;
339 struct vpu_device enc_dev;
340 struct vpu_device dec_dev;
342 enum VPU_HW_ID hw_id;
343 struct vpu_hw_info *hw_info;
344 struct vpu_task_info *task_info;
345 const struct vpu_trans_info *trans_info;
350 #ifdef CONFIG_DEBUG_FS
351 struct dentry *debugfs_dir;
352 struct dentry *debugfs_file_regs;
355 struct device *mmu_dev;
356 struct vcodec_iommu_info *iommu_info;
359 struct vpu_service_info {
360 struct wake_lock wake_lock;
361 struct delayed_work power_off_work;
362 ktime_t last; /* record previous power-on time */
363 /* vpu service structure global lock */
365 /* link to link_reg in struct vpu_reg */
366 struct list_head waiting;
367 /* link to link_reg in struct vpu_reg */
368 struct list_head running;
369 /* link to link_reg in struct vpu_reg */
370 struct list_head done;
371 /* link to list_session in struct vpu_session */
372 struct list_head session;
373 atomic_t total_running;
375 atomic_t power_on_cnt;
376 atomic_t power_off_cnt;
378 struct mutex shutdown_lock;
379 struct vpu_reg *reg_codec;
380 struct vpu_reg *reg_pproc;
381 struct vpu_reg *reg_resev;
382 struct vpu_dec_config dec_config;
383 struct vpu_enc_config enc_config;
387 atomic_t freq_status;
389 struct clk *aclk_vcodec;
390 struct clk *hclk_vcodec;
391 struct clk *clk_core;
392 struct clk *clk_cabac;
393 struct clk *pd_video;
395 #ifdef CONFIG_RESET_CONTROLLER
396 struct reset_control *rst_a;
397 struct reset_control *rst_h;
398 struct reset_control *rst_v;
403 atomic_t reset_request;
404 struct list_head mem_region_list;
406 enum vcodec_device_id dev_id;
408 enum VCODEC_RUNNING_MODE curr_mode;
411 struct delayed_work simulate_work;
423 struct list_head subdev_list;
434 struct compat_vpu_request {
440 #define VDPU_SOFT_RESET_REG 101
441 #define VDPU_CLEAN_CACHE_REG 516
442 #define VEPU_CLEAN_CACHE_REG 772
443 #define HEVC_CLEAN_CACHE_REG 260
445 #define VPU_REG_ENABLE(base, reg) writel_relaxed(1, base + reg)
447 #define VDPU_SOFT_RESET(base) VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
448 #define VDPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
449 #define VEPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
450 #define HEVC_CLEAN_CACHE(base) VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
452 #define VPU_POWER_OFF_DELAY (4 * HZ) /* 4s */
453 #define VPU_TIMEOUT_DELAY (2 * HZ) /* 2s */
455 static void *vcodec_get_drv_data(struct platform_device *pdev);
457 static void vpu_service_power_on(struct vpu_subdev_data *data,
458 struct vpu_service_info *pservice);
460 static void time_record(struct vpu_task_info *task, int is_end)
462 if (unlikely(debug & DEBUG_TIMING) && task)
463 do_gettimeofday((is_end) ? (&task->end) : (&task->start));
466 static void time_diff(struct vpu_task_info *task)
468 vpu_debug(DEBUG_TIMING, "%s task: %ld ms\n", task->name,
469 (task->end.tv_sec - task->start.tv_sec) * 1000 +
470 (task->end.tv_usec - task->start.tv_usec) / 1000);
473 static void vcodec_enter_mode(struct vpu_subdev_data *data)
477 struct vpu_service_info *pservice = data->pservice;
478 struct vpu_subdev_data *subdata, *n;
480 if (pservice->subcnt < 2)
483 if (pservice->curr_mode == data->mode)
486 vpu_debug(DEBUG_IOMMU, "vcodec enter mode %d\n", data->mode);
487 list_for_each_entry_safe(subdata, n,
488 &pservice->subdev_list, lnk_service) {
489 if (data != subdata && subdata->mmu_dev &&
490 test_bit(MMU_ACTIVATED, &subdata->state)) {
491 clear_bit(MMU_ACTIVATED, &subdata->state);
494 bits = 1 << pservice->mode_bit;
495 #ifdef CONFIG_MFD_SYSCON
497 regmap_read(pservice->grf, pservice->mode_ctrl, &raw);
499 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
500 regmap_write(pservice->grf, pservice->mode_ctrl,
501 raw | bits | (bits << 16));
503 regmap_write(pservice->grf, pservice->mode_ctrl,
504 (raw & (~bits)) | (bits << 16));
505 } else if (pservice->grf_base) {
506 u32 *grf_base = pservice->grf_base;
508 raw = readl_relaxed(grf_base + pservice->mode_ctrl / 4);
509 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
510 writel_relaxed(raw | bits | (bits << 16),
511 grf_base + pservice->mode_ctrl / 4);
513 writel_relaxed((raw & (~bits)) | (bits << 16),
514 grf_base + pservice->mode_ctrl / 4);
516 vpu_err("no grf resource define, switch decoder failed\n");
520 if (pservice->grf_base) {
521 u32 *grf_base = pservice->grf_base;
523 raw = readl_relaxed(grf_base + pservice->mode_ctrl / 4);
524 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
525 writel_relaxed(raw | bits | (bits << 16),
526 grf_base + pservice->mode_ctrl / 4);
528 writel_relaxed((raw & (~bits)) | (bits << 16),
529 grf_base + pservice->mode_ctrl / 4);
531 vpu_err("no grf resource define, switch decoder failed\n");
535 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
536 set_bit(MMU_ACTIVATED, &data->state);
537 if (!atomic_read(&pservice->enabled))
538 /* FIXME BUG_ON should not be used in mass produce */
539 BUG_ON(!atomic_read(&pservice->enabled));
542 pservice->prev_mode = pservice->curr_mode;
543 pservice->curr_mode = data->mode;
546 static void vcodec_exit_mode(struct vpu_subdev_data *data)
549 * In case of VPU Combo, it require HW switch its running mode
550 * before the other HW component start work. set current HW running
551 * mode to none, can ensure HW switch to its reqired mode properly.
553 data->pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
556 static int vpu_get_clk(struct vpu_service_info *pservice)
558 #if VCODEC_CLOCK_ENABLE
559 struct device *dev = pservice->dev;
561 switch (pservice->dev_id) {
562 case VCODEC_DEVICE_ID_HEVC:
563 pservice->pd_video = devm_clk_get(dev, "pd_hevc");
564 if (IS_ERR(pservice->pd_video)) {
565 pservice->pd_video = NULL;
566 dev_info(dev, "failed on clk_get pd_hevc\n");
568 case VCODEC_DEVICE_ID_COMBO:
569 case VCODEC_DEVICE_ID_RKVDEC:
570 pservice->clk_cabac = devm_clk_get(dev, "clk_cabac");
571 if (IS_ERR(pservice->clk_cabac)) {
572 dev_err(dev, "failed on clk_get clk_cabac\n");
573 pservice->clk_cabac = NULL;
575 pservice->clk_core = devm_clk_get(dev, "clk_core");
576 if (IS_ERR(pservice->clk_core)) {
577 dev_err(dev, "failed on clk_get clk_core\n");
578 pservice->clk_core = NULL;
581 case VCODEC_DEVICE_ID_VPU:
582 pservice->aclk_vcodec = devm_clk_get(dev, "aclk_vcodec");
583 if (IS_ERR(pservice->aclk_vcodec)) {
584 dev_err(dev, "failed on clk_get aclk_vcodec\n");
585 pservice->aclk_vcodec = NULL;
589 pservice->hclk_vcodec = devm_clk_get(dev, "hclk_vcodec");
590 if (IS_ERR(pservice->hclk_vcodec)) {
591 dev_err(dev, "failed on clk_get hclk_vcodec\n");
592 pservice->hclk_vcodec = NULL;
595 if (pservice->pd_video == NULL) {
596 pservice->pd_video = devm_clk_get(dev, "pd_video");
597 if (IS_ERR(pservice->pd_video)) {
598 pservice->pd_video = NULL;
599 dev_info(dev, "do not have pd_video\n");
613 static void _vpu_reset(struct vpu_subdev_data *data)
615 struct vpu_service_info *pservice = data->pservice;
616 enum pmu_idle_req type = IDLE_REQ_VIDEO;
618 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC)
619 type = IDLE_REQ_HEVC;
621 dev_info(pservice->dev, "resetting...\n");
622 WARN_ON(pservice->reg_codec != NULL);
623 WARN_ON(pservice->reg_pproc != NULL);
624 WARN_ON(pservice->reg_resev != NULL);
625 pservice->reg_codec = NULL;
626 pservice->reg_pproc = NULL;
627 pservice->reg_resev = NULL;
629 #ifdef CONFIG_RESET_CONTROLLER
630 dev_info(pservice->dev, "for 3288/3368...");
631 if (of_machine_is_compatible("rockchip,rk3288"))
632 rockchip_pmu_idle_request(pservice->dev, true);
633 if (pservice->rst_a && pservice->rst_h) {
634 dev_info(pservice->dev, "vpu reset in\n");
637 reset_control_assert(pservice->rst_v);
638 reset_control_assert(pservice->rst_a);
639 reset_control_assert(pservice->rst_h);
642 reset_control_deassert(pservice->rst_h);
643 reset_control_deassert(pservice->rst_a);
645 reset_control_deassert(pservice->rst_v);
646 } else if (pservice->rst_v) {
647 dev_info(pservice->dev, "hevc reset in\n");
648 reset_control_assert(pservice->rst_v);
651 reset_control_deassert(pservice->rst_v);
653 if (of_machine_is_compatible("rockchip,rk3288"))
654 rockchip_pmu_idle_request(pservice->dev, false);
658 static void vpu_reset(struct vpu_subdev_data *data)
660 struct vpu_service_info *pservice = data->pservice;
663 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
664 if (atomic_read(&pservice->enabled)) {
665 /* Need to reset iommu */
666 vcodec_iommu_detach(data->iommu_info);
667 vcodec_iommu_attach(data->iommu_info);
669 /* FIXME BUG_ON should not be used in mass produce */
670 BUG_ON(!atomic_read(&pservice->enabled));
674 atomic_set(&pservice->reset_request, 0);
675 dev_info(pservice->dev, "reset done\n");
678 static void reg_deinit(struct vpu_subdev_data *data, struct vpu_reg *reg);
679 static void vpu_service_session_clear(struct vpu_subdev_data *data,
680 struct vpu_session *session)
682 struct vpu_reg *reg, *n;
684 list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
685 reg_deinit(data, reg);
687 list_for_each_entry_safe(reg, n, &session->running, session_link) {
688 reg_deinit(data, reg);
690 list_for_each_entry_safe(reg, n, &session->done, session_link) {
691 reg_deinit(data, reg);
695 static void vpu_service_clear(struct vpu_subdev_data *data)
697 struct vpu_reg *reg, *n;
698 struct vpu_session *session, *s;
699 struct vpu_service_info *pservice = data->pservice;
701 list_for_each_entry_safe(reg, n, &pservice->waiting, status_link) {
702 reg_deinit(reg->data, reg);
705 /* wake up session wait event to prevent the timeout hw reset
706 * during reboot procedure.
708 list_for_each_entry_safe(session, s,
709 &pservice->session, list_session)
710 wake_up(&session->wait);
713 static void vpu_service_dump(struct vpu_service_info *pservice)
718 static void vpu_service_power_off(struct vpu_service_info *pservice)
721 struct vpu_subdev_data *data = NULL, *n;
722 int ret = atomic_add_unless(&pservice->enabled, -1, 0);
727 total_running = atomic_read(&pservice->total_running);
729 pr_alert("alert: power off when %d task running!!\n",
732 pr_alert("alert: delay 50 ms for running task\n");
733 vpu_service_dump(pservice);
736 dev_dbg(pservice->dev, "power off...\n");
740 list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
741 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
742 clear_bit(MMU_ACTIVATED, &data->state);
743 vcodec_iommu_detach(data->iommu_info);
746 pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
747 pm_runtime_put(pservice->dev);
748 #if VCODEC_CLOCK_ENABLE
749 if (pservice->pd_video)
750 clk_disable_unprepare(pservice->pd_video);
751 if (pservice->hclk_vcodec)
752 clk_disable_unprepare(pservice->hclk_vcodec);
753 if (pservice->aclk_vcodec)
754 clk_disable_unprepare(pservice->aclk_vcodec);
755 if (pservice->clk_core)
756 clk_disable_unprepare(pservice->clk_core);
757 if (pservice->clk_cabac)
758 clk_disable_unprepare(pservice->clk_cabac);
761 atomic_add(1, &pservice->power_off_cnt);
762 wake_unlock(&pservice->wake_lock);
763 dev_dbg(pservice->dev, "power off done\n");
766 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
768 queue_delayed_work(system_wq, &pservice->power_off_work,
769 VPU_POWER_OFF_DELAY);
772 static void vpu_power_off_work(struct work_struct *work_s)
774 struct delayed_work *dlwork = container_of(work_s,
775 struct delayed_work, work);
776 struct vpu_service_info *pservice = container_of(dlwork,
777 struct vpu_service_info, power_off_work);
779 if (mutex_trylock(&pservice->lock)) {
780 vpu_service_power_off(pservice);
781 mutex_unlock(&pservice->lock);
783 /* Come back later if the device is busy... */
784 vpu_queue_power_off_work(pservice);
788 static void vpu_service_power_on(struct vpu_subdev_data *data,
789 struct vpu_service_info *pservice)
792 ktime_t now = ktime_get();
794 if (ktime_to_ns(ktime_sub(now, pservice->last)) > NSEC_PER_SEC ||
795 atomic_read(&pservice->power_on_cnt)) {
797 cancel_delayed_work_sync(&pservice->power_off_work);
798 vpu_queue_power_off_work(pservice);
799 pservice->last = now;
801 ret = atomic_add_unless(&pservice->enabled, 1, 1);
803 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
804 set_bit(MMU_ACTIVATED, &data->state);
805 vcodec_iommu_attach(data->iommu_info);
810 dev_dbg(pservice->dev, "power on\n");
812 #define BIT_VCODEC_CLK_SEL (1<<10)
813 if (of_machine_is_compatible("rockchip,rk3126"))
814 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1)
815 | BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
816 RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
818 #if VCODEC_CLOCK_ENABLE
819 if (pservice->aclk_vcodec)
820 clk_prepare_enable(pservice->aclk_vcodec);
821 if (pservice->hclk_vcodec)
822 clk_prepare_enable(pservice->hclk_vcodec);
823 if (pservice->clk_core)
824 clk_prepare_enable(pservice->clk_core);
825 if (pservice->clk_cabac)
826 clk_prepare_enable(pservice->clk_cabac);
827 if (pservice->pd_video)
828 clk_prepare_enable(pservice->pd_video);
830 pm_runtime_get_sync(pservice->dev);
832 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
833 set_bit(MMU_ACTIVATED, &data->state);
834 if (atomic_read(&pservice->enabled))
835 vcodec_iommu_attach(data->iommu_info);
838 * FIXME BUG_ON should not be used in mass
841 BUG_ON(!atomic_read(&pservice->enabled));
845 atomic_add(1, &pservice->power_on_cnt);
846 wake_lock(&pservice->wake_lock);
849 static inline bool reg_check_interlace(struct vpu_reg *reg)
851 u32 type = (reg->reg[3] & (1 << 23));
856 static inline enum VPU_DEC_FMT reg_check_fmt(struct vpu_reg *reg)
858 enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] >> 28) & 0xf);
863 static inline int reg_probe_width(struct vpu_reg *reg)
865 int width_in_mb = reg->reg[4] >> 23;
867 return width_in_mb * 16;
870 static inline int reg_probe_hevc_y_stride(struct vpu_reg *reg)
872 int y_virstride = reg->reg[8];
877 static int vcodec_fd_to_iova(struct vpu_subdev_data *data,
878 struct vpu_session *session,
884 struct vcodec_mem_region *mem_region;
886 hdl = vcodec_iommu_import(data->iommu_info, session, fd);
890 mem_region = kzalloc(sizeof(*mem_region), GFP_KERNEL);
891 if (mem_region == NULL) {
892 vpu_err("allocate memory for iommu memory region failed\n");
893 vcodec_iommu_free(data->iommu_info, session, hdl);
897 mem_region->hdl = hdl;
898 ret = vcodec_iommu_map_iommu(data->iommu_info, session, mem_region->hdl,
899 &mem_region->iova, &mem_region->len);
901 vpu_err("fd %d ion map iommu failed\n", fd);
903 vcodec_iommu_free(data->iommu_info, session, hdl);
907 INIT_LIST_HEAD(&mem_region->reg_lnk);
908 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
909 return mem_region->iova;
913 * NOTE: rkvdec/rkhevc put scaling list address in pps buffer hardware will read
914 * it by pps id in video stream data.
916 * So we need to translate the address in iommu case. The address data is also
917 * 10bit fd + 22bit offset mode.
918 * Because userspace decoder do not give the pps id in the register file sets
919 * kernel driver need to translate each scaling list address in pps buffer which
920 * means 256 pps for H.264, 64 pps for H.265.
922 * In order to optimize the performance kernel driver ask userspace decoder to
923 * set all scaling list address in pps buffer to the same one which will be used
924 * on current decoding task. Then kernel driver can only translate the first
925 * address then copy it all pps buffer.
927 static int fill_scaling_list_addr_in_pps(
928 struct vpu_subdev_data *data,
933 int scaling_list_addr_offset)
935 int base = scaling_list_addr_offset;
939 scaling_offset = (u32)pps[base + 0];
940 scaling_offset += (u32)pps[base + 1] << 8;
941 scaling_offset += (u32)pps[base + 2] << 16;
942 scaling_offset += (u32)pps[base + 3] << 24;
944 scaling_fd = scaling_offset & 0x3ff;
945 scaling_offset = scaling_offset >> 10;
947 if (scaling_fd > 0) {
949 u32 tmp = vcodec_fd_to_iova(data, reg->session, reg,
952 if (IS_ERR_VALUE(tmp))
954 tmp += scaling_offset;
956 for (i = 0; i < pps_info_count; i++, base += pps_info_size) {
957 pps[base + 0] = (tmp >> 0) & 0xff;
958 pps[base + 1] = (tmp >> 8) & 0xff;
959 pps[base + 2] = (tmp >> 16) & 0xff;
960 pps[base + 3] = (tmp >> 24) & 0xff;
967 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data,
968 struct vpu_session *session,
970 int size, struct vpu_reg *reg,
971 struct extra_info_for_iommu *ext_inf)
973 struct vpu_service_info *pservice = data->pservice;
974 struct vpu_task_info *task = reg->task;
975 enum FORMAT_TYPE type;
978 struct vcodec_mem_region *mem_region;
982 if (tbl == NULL || size <= 0) {
983 dev_err(pservice->dev, "input arguments invalidate\n");
988 type = task->get_fmt(reg->reg);
990 dev_err(pservice->dev, "invalid task with NULL get_fmt\n");
994 for (i = 0; i < size; i++) {
995 int usr_fd = reg->reg[tbl[i]] & 0x3FF;
997 /* if userspace do not set the fd at this register, skip */
1002 * for avoiding cache sync issue, we need to map/unmap
1003 * input buffer every time. FIX ME, if it is unnecessary
1005 if (task->reg_rlc == tbl[i])
1006 vcodec_iommu_free_fd(data->iommu_info, session, usr_fd);
1008 * special offset scale case
1010 * This translation is for fd + offset translation.
1011 * One register has 32bits. We need to transfer both buffer file
1012 * handle and the start address offset so we packet file handle
1013 * and offset together using below format.
1015 * 0~9 bit for buffer file handle range 0 ~ 1023
1016 * 10~31 bit for offset range 0 ~ 4M
1018 * But on 4K case the offset can be larger the 4M
1019 * So on H.264 4K vpu/vpu2 decoder we scale the offset by 16
1020 * But MPEG4 will use the same register for colmv and it do not
1023 * RKVdec do not have this issue.
1025 if ((type == FMT_H264D || type == FMT_VP9D) &&
1026 task->reg_dir_mv > 0 && task->reg_dir_mv == tbl[i])
1027 offset = reg->reg[tbl[i]] >> 10 << 4;
1029 offset = reg->reg[tbl[i]] >> 10;
1031 vpu_debug(DEBUG_IOMMU, "pos %3d fd %3d offset %10d i %d\n",
1032 tbl[i], usr_fd, offset, i);
1034 hdl = vcodec_iommu_import(data->iommu_info, session, usr_fd);
1036 if (task->reg_pps > 0 && task->reg_pps == tbl[i]) {
1037 int pps_info_offset;
1040 int scaling_list_addr_offset;
1044 pps_info_offset = offset;
1045 pps_info_count = 256;
1047 scaling_list_addr_offset = 23;
1050 pps_info_offset = 0;
1051 pps_info_count = 64;
1053 scaling_list_addr_offset = 74;
1056 pps_info_offset = 0;
1059 scaling_list_addr_offset = 0;
1063 vpu_debug(DEBUG_PPS_FILL,
1064 "scaling list filling parameter:\n");
1065 vpu_debug(DEBUG_PPS_FILL,
1066 "pps_info_offset %d\n", pps_info_offset);
1067 vpu_debug(DEBUG_PPS_FILL,
1068 "pps_info_count %d\n", pps_info_count);
1069 vpu_debug(DEBUG_PPS_FILL,
1070 "pps_info_size %d\n", pps_info_size);
1071 vpu_debug(DEBUG_PPS_FILL,
1072 "scaling_list_addr_offset %d\n",
1073 scaling_list_addr_offset);
1075 if (pps_info_count) {
1078 mutex_lock(&pservice->lock);
1080 pps = vcodec_iommu_map_kernel
1081 (data->iommu_info, session, hdl);
1083 vpu_debug(DEBUG_PPS_FILL,
1084 "scaling list setting pps %p\n", pps);
1085 pps += pps_info_offset;
1087 fill_scaling_list_addr_in_pps
1088 (data, reg, pps, pps_info_count,
1090 scaling_list_addr_offset);
1092 vcodec_iommu_unmap_kernel
1093 (data->iommu_info, session, hdl);
1094 mutex_unlock(&pservice->lock);
1098 mem_region = kzalloc(sizeof(*mem_region), GFP_KERNEL);
1101 vcodec_iommu_free(data->iommu_info, session, hdl);
1105 mem_region->hdl = hdl;
1106 mem_region->reg_idx = tbl[i];
1108 ret = vcodec_iommu_map_iommu(data->iommu_info, session,
1109 mem_region->hdl, &mem_region->iova,
1112 dev_err(pservice->dev,
1113 "reg %d fd %d ion map iommu failed\n",
1116 vcodec_iommu_free(data->iommu_info, session, hdl);
1121 * special for vpu dec num 12: record decoded length
1122 * hacking for decoded length
1123 * NOTE: not a perfect fix, the fd is not recorded
1125 if (task->reg_len > 0 && task->reg_len == tbl[i]) {
1126 reg->dec_base = mem_region->iova + offset;
1127 vpu_debug(DEBUG_REGISTER, "dec_set %08x\n",
1131 reg->reg[tbl[i]] = mem_region->iova + offset;
1132 INIT_LIST_HEAD(&mem_region->reg_lnk);
1133 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
1136 if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
1137 for (i = 0; i < ext_inf->cnt; i++) {
1138 vpu_debug(DEBUG_IOMMU, "reg[%d] + offset %d\n",
1139 ext_inf->elem[i].index,
1140 ext_inf->elem[i].offset);
1141 reg->reg[ext_inf->elem[i].index] +=
1142 ext_inf->elem[i].offset;
1149 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
1150 struct vpu_session *session,
1151 struct vpu_reg *reg,
1152 struct extra_info_for_iommu *ext_inf)
1154 struct vpu_service_info *pservice = data->pservice;
1155 enum FORMAT_TYPE type = reg->task->get_fmt(reg->reg);
1157 if (type < FMT_TYPE_BUTT) {
1158 const struct vpu_trans_info *info = ®->trans[type];
1159 const u8 *tbl = info->table;
1160 int size = info->count;
1162 return vcodec_bufid_to_iova(data, session, tbl, size, reg,
1166 dev_err(pservice->dev, "found invalid format type!\n");
1170 static void get_reg_freq(struct vpu_subdev_data *data, struct vpu_reg *reg)
1173 if (!of_machine_is_compatible("rockchip,rk2928g")) {
1174 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1175 if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1176 if (reg_probe_width(reg) > 3200) {
1177 /*raise frequency for 4k avc.*/
1178 reg->freq = VPU_FREQ_600M;
1181 if (reg_check_interlace(reg))
1182 reg->freq = VPU_FREQ_400M;
1185 if (data->hw_id == HEVC_ID) {
1186 if (reg_probe_hevc_y_stride(reg) > 60000)
1187 reg->freq = VPU_FREQ_400M;
1189 if (reg->type == VPU_PP)
1190 reg->freq = VPU_FREQ_400M;
1194 static struct vpu_reg *reg_init(struct vpu_subdev_data *data,
1195 struct vpu_session *session,
1196 void __user *src, u32 size)
1198 struct vpu_service_info *pservice = data->pservice;
1200 struct extra_info_for_iommu extra_info;
1201 struct vpu_reg *reg = kzalloc(sizeof(*reg) + data->reg_size,
1207 vpu_err("error: kzalloc failed\n");
1211 if (size > data->reg_size) {
1212 extra_size = size - data->reg_size;
1213 size = data->reg_size;
1215 reg->session = session;
1217 reg->type = session->type;
1219 reg->freq = VPU_FREQ_DEFAULT;
1220 reg->task = &data->task_info[session->type];
1221 reg->trans = data->trans_info;
1222 reg->reg = (u32 *)®[1];
1223 INIT_LIST_HEAD(®->session_link);
1224 INIT_LIST_HEAD(®->status_link);
1226 INIT_LIST_HEAD(®->mem_region_list);
1228 if (copy_from_user(®->reg[0], (void __user *)src, size)) {
1229 vpu_err("error: copy_from_user failed\n");
1234 if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1235 vpu_err("error: copy_from_user failed\n");
1240 if (vcodec_reg_address_translate(data, session, reg, &extra_info) < 0) {
1243 vpu_err("error: translate reg address failed, dumping regs\n");
1244 for (i = 0; i < size >> 2; i++)
1245 dev_err(pservice->dev, "reg[%02d]: %08x\n",
1246 i, *((u32 *)src + i));
1252 mutex_lock(&pservice->lock);
1253 list_add_tail(®->status_link, &pservice->waiting);
1254 list_add_tail(®->session_link, &session->waiting);
1255 mutex_unlock(&pservice->lock);
1257 if (pservice->auto_freq)
1258 get_reg_freq(data, reg);
1265 static void reg_deinit(struct vpu_subdev_data *data, struct vpu_reg *reg)
1267 struct vpu_service_info *pservice = data->pservice;
1268 struct vcodec_mem_region *mem_region = NULL, *n;
1270 list_del_init(®->session_link);
1271 list_del_init(®->status_link);
1272 if (reg == pservice->reg_codec)
1273 pservice->reg_codec = NULL;
1274 if (reg == pservice->reg_pproc)
1275 pservice->reg_pproc = NULL;
1277 /* release memory region attach to this registers table. */
1278 list_for_each_entry_safe(mem_region, n,
1279 ®->mem_region_list, reg_lnk) {
1280 vcodec_iommu_unmap_iommu(data->iommu_info, reg->session,
1282 vcodec_iommu_free(data->iommu_info, reg->session,
1284 list_del_init(&mem_region->reg_lnk);
1291 static void reg_from_wait_to_run(struct vpu_service_info *pservice,
1292 struct vpu_reg *reg)
1295 list_del_init(®->status_link);
1296 list_add_tail(®->status_link, &pservice->running);
1298 list_del_init(®->session_link);
1299 list_add_tail(®->session_link, ®->session->running);
1303 static void reg_copy_from_hw(struct vpu_reg *reg, u32 *src, u32 count)
1306 u32 *dst = reg->reg;
1309 for (i = 0; i < count; i++, src++)
1310 *dst++ = readl_relaxed(src);
1312 dst = (u32 *)®->reg[0];
1313 for (i = 0; i < count; i++)
1314 vpu_debug(DEBUG_GET_REG, "get reg[%02d] %08x\n", i, dst[i]);
1319 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1320 struct vpu_reg *reg)
1322 struct vpu_service_info *pservice = data->pservice;
1323 struct vpu_hw_info *hw_info = data->hw_info;
1324 struct vpu_task_info *task = reg->task;
1328 list_del_init(®->status_link);
1329 list_add_tail(®->status_link, &pservice->done);
1331 list_del_init(®->session_link);
1332 list_add_tail(®->session_link, ®->session->done);
1334 switch (reg->type) {
1336 pservice->reg_codec = NULL;
1337 reg_copy_from_hw(reg, data->enc_dev.regs, hw_info->enc_reg_num);
1338 reg->reg[task->reg_irq] = pservice->irq_status;
1341 pservice->reg_codec = NULL;
1342 reg_copy_from_hw(reg, data->dec_dev.regs, hw_info->dec_reg_num);
1344 /* revert hack for decoded length */
1345 if (task->reg_len > 0) {
1346 int reg_len = task->reg_len;
1347 u32 dec_get = reg->reg[reg_len];
1348 s32 dec_length = dec_get - reg->dec_base;
1350 vpu_debug(DEBUG_REGISTER,
1351 "dec_get %08x dec_length %d\n",
1352 dec_get, dec_length);
1353 reg->reg[reg_len] = dec_length << 10;
1356 reg->reg[task->reg_irq] = pservice->irq_status;
1359 pservice->reg_pproc = NULL;
1360 reg_copy_from_hw(reg, data->dec_dev.regs, hw_info->dec_reg_num);
1361 writel_relaxed(0, data->dec_dev.regs + task->reg_irq);
1365 u32 *regs = data->dec_dev.regs;
1367 pservice->reg_codec = NULL;
1368 pservice->reg_pproc = NULL;
1370 reg_copy_from_hw(reg, data->dec_dev.regs, hw_info->dec_reg_num);
1372 /* NOTE: remove pp pipeline mode flag first */
1373 pipe_mode = readl_relaxed(regs + task->reg_pipe);
1374 pipe_mode &= ~task->pipe_mask;
1375 writel_relaxed(pipe_mode, regs + task->reg_pipe);
1377 /* revert hack for decoded length */
1378 if (task->reg_len > 0) {
1379 int reg_len = task->reg_len;
1380 u32 dec_get = reg->reg[reg_len];
1381 s32 dec_length = dec_get - reg->dec_base;
1383 vpu_debug(DEBUG_REGISTER,
1384 "dec_get %08x dec_length %d\n",
1385 dec_get, dec_length);
1386 reg->reg[reg_len] = dec_length << 10;
1389 reg->reg[task->reg_irq] = pservice->irq_status;
1392 vpu_err("error: copy reg from hw with unknown type %d\n",
1396 vcodec_exit_mode(data);
1398 atomic_sub(1, ®->session->task_running);
1399 atomic_sub(1, &pservice->total_running);
1400 wake_up(®->session->wait);
1405 static void vpu_service_set_freq(struct vpu_service_info *pservice,
1406 struct vpu_reg *reg)
1408 enum VPU_FREQ curr = atomic_read(&pservice->freq_status);
1410 if (curr == reg->freq)
1413 atomic_set(&pservice->freq_status, reg->freq);
1414 switch (reg->freq) {
1415 case VPU_FREQ_200M: {
1416 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1418 case VPU_FREQ_266M: {
1419 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1421 case VPU_FREQ_300M: {
1422 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1424 case VPU_FREQ_400M: {
1425 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1427 case VPU_FREQ_500M: {
1428 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1430 case VPU_FREQ_600M: {
1431 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1434 unsigned long rate = 300*MHZ;
1436 if (of_machine_is_compatible("rockchip,rk2928g"))
1439 clk_set_rate(pservice->aclk_vcodec, rate);
1444 static void reg_copy_to_hw(struct vpu_subdev_data *data, struct vpu_reg *reg)
1446 struct vpu_service_info *pservice = data->pservice;
1447 struct vpu_task_info *task = reg->task;
1448 struct vpu_hw_info *hw_info = data->hw_info;
1450 u32 *src = (u32 *)®->reg[0];
1451 u32 enable_mask = task->enable_mask;
1452 u32 gating_mask = task->gating_mask;
1453 u32 reg_en = task->reg_en;
1457 atomic_add(1, &pservice->total_running);
1458 atomic_add(1, ®->session->task_running);
1460 if (pservice->auto_freq)
1461 vpu_service_set_freq(pservice, reg);
1463 vcodec_enter_mode(data);
1465 switch (reg->type) {
1467 u32 *dst = data->enc_dev.regs;
1469 u32 end = hw_info->enc_reg_num;
1470 /* u32 reg_gating = task->reg_gating; */
1472 pservice->reg_codec = reg;
1474 vpu_debug(DEBUG_TASK_INFO,
1475 "reg: base %3d end %d en %2d mask: en %x gate %x\n",
1476 base, end, reg_en, enable_mask, gating_mask);
1478 VEPU_CLEAN_CACHE(dst);
1480 if (debug & DEBUG_SET_REG)
1481 for (i = base; i < end; i++)
1482 vpu_debug(DEBUG_SET_REG, "set reg[%02d] %08x\n",
1486 * NOTE: encoder need to setup mode first
1488 writel_relaxed(src[reg_en] & enable_mask, dst + reg_en);
1490 /* NOTE: encoder gating is not on enable register */
1491 /* src[reg_gating] |= gating_mask; */
1493 for (i = base; i < end; i++) {
1495 writel_relaxed(src[i], dst + i);
1498 writel(src[reg_en], dst + reg_en);
1501 time_record(reg->task, 0);
1504 u32 *dst = data->dec_dev.regs;
1505 u32 len = hw_info->dec_reg_num;
1506 u32 base = hw_info->base_dec;
1507 u32 end = hw_info->end_dec;
1509 pservice->reg_codec = reg;
1511 vpu_debug(DEBUG_TASK_INFO,
1512 "reg: base %3d end %d en %2d mask: en %x gate %x\n",
1513 base, end, reg_en, enable_mask, gating_mask);
1515 VDPU_CLEAN_CACHE(dst);
1517 /* on rkvdec set cache size to 64byte */
1518 if (pservice->dev_id == VCODEC_DEVICE_ID_RKVDEC) {
1519 u32 *cache_base = dst + 0x100;
1520 u32 val = (debug & DEBUG_CACHE_32B) ? (0x3) : (0x13);
1521 writel_relaxed(val, cache_base + 0x07);
1522 writel_relaxed(val, cache_base + 0x17);
1525 if (debug & DEBUG_SET_REG)
1526 for (i = 0; i < len; i++)
1527 vpu_debug(DEBUG_SET_REG, "set reg[%02d] %08x\n",
1530 * NOTE: The end register is invalid. Do NOT write to it
1531 * Also the base register must be written
1533 for (i = base; i < end; i++) {
1535 writel_relaxed(src[i], dst + i);
1538 writel(src[reg_en] | gating_mask, dst + reg_en);
1541 time_record(reg->task, 0);
1544 u32 *dst = data->dec_dev.regs;
1545 u32 base = hw_info->base_pp;
1546 u32 end = hw_info->end_pp;
1548 pservice->reg_pproc = reg;
1550 vpu_debug(DEBUG_TASK_INFO,
1551 "reg: base %3d end %d en %2d mask: en %x gate %x\n",
1552 base, end, reg_en, enable_mask, gating_mask);
1554 if (debug & DEBUG_SET_REG)
1555 for (i = base; i < end; i++)
1556 vpu_debug(DEBUG_SET_REG, "set reg[%02d] %08x\n",
1559 for (i = base; i < end; i++) {
1561 writel_relaxed(src[i], dst + i);
1564 writel(src[reg_en] | gating_mask, dst + reg_en);
1567 time_record(reg->task, 0);
1570 u32 *dst = data->dec_dev.regs;
1571 u32 base = hw_info->base_dec_pp;
1572 u32 end = hw_info->end_dec_pp;
1574 pservice->reg_codec = reg;
1575 pservice->reg_pproc = reg;
1577 vpu_debug(DEBUG_TASK_INFO,
1578 "reg: base %3d end %d en %2d mask: en %x gate %x\n",
1579 base, end, reg_en, enable_mask, gating_mask);
1581 /* VDPU_SOFT_RESET(dst); */
1582 VDPU_CLEAN_CACHE(dst);
1584 if (debug & DEBUG_SET_REG)
1585 for (i = base; i < end; i++)
1586 vpu_debug(DEBUG_SET_REG, "set reg[%02d] %08x\n",
1589 for (i = base; i < end; i++) {
1591 writel_relaxed(src[i], dst + i);
1594 /* NOTE: dec output must be disabled */
1596 writel(src[reg_en] | gating_mask, dst + reg_en);
1599 time_record(reg->task, 0);
1602 vpu_err("error: unsupport session type %d", reg->type);
1603 atomic_sub(1, &pservice->total_running);
1604 atomic_sub(1, ®->session->task_running);
1611 static void try_set_reg(struct vpu_subdev_data *data)
1613 struct vpu_service_info *pservice = data->pservice;
1617 mutex_lock(&pservice->shutdown_lock);
1618 if (atomic_read(&pservice->service_on) == 0) {
1619 mutex_unlock(&pservice->shutdown_lock);
1622 if (!list_empty(&pservice->waiting)) {
1623 struct vpu_reg *reg_codec = pservice->reg_codec;
1624 struct vpu_reg *reg_pproc = pservice->reg_pproc;
1626 bool change_able = (reg_codec == NULL) && (reg_pproc == NULL);
1627 int reset_request = atomic_read(&pservice->reset_request);
1628 struct vpu_reg *reg = list_entry(pservice->waiting.next,
1629 struct vpu_reg, status_link);
1631 if (change_able || !reset_request) {
1632 switch (reg->type) {
1638 if (reg_codec == NULL)
1640 if (pservice->auto_freq && (reg_pproc != NULL))
1644 if (reg_codec == NULL) {
1645 if (reg_pproc == NULL)
1648 if ((reg_codec->type == VPU_DEC) &&
1649 (reg_pproc == NULL))
1654 * can not charge frequency
1655 * when vpu is working
1657 if (pservice->auto_freq)
1666 dev_err(pservice->dev,
1667 "undefined reg type %d\n",
1673 /* then check reset request */
1674 if (reset_request && !change_able)
1677 /* do reset before setting registers */
1682 reg_from_wait_to_run(pservice, reg);
1683 reg_copy_to_hw(reg->data, reg);
1687 mutex_unlock(&pservice->shutdown_lock);
1691 static int return_reg(struct vpu_subdev_data *data,
1692 struct vpu_reg *reg, u32 __user *dst)
1694 struct vpu_hw_info *hw_info = data->hw_info;
1695 size_t size = reg->size;
1699 switch (reg->type) {
1704 base = hw_info->base_dec_pp;
1707 base = hw_info->base_pp;
1710 base = hw_info->base_dec_pp;
1713 vpu_err("error: copy reg to user with unknown type %d\n",
1719 if (copy_to_user(dst, ®->reg[base], size)) {
1720 vpu_err("error: copy_to_user failed\n");
1724 reg_deinit(data, reg);
1729 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1732 struct vpu_subdev_data *data =
1733 container_of(filp->f_path.dentry->d_inode->i_cdev,
1734 struct vpu_subdev_data, cdev);
1735 struct vpu_service_info *pservice = data->pservice;
1736 struct vpu_session *session = (struct vpu_session *)filp->private_data;
1739 if (NULL == session)
1743 case VPU_IOC_SET_CLIENT_TYPE: {
1744 session->type = (enum VPU_CLIENT_TYPE)arg;
1745 vpu_debug(DEBUG_IOCTL, "pid %d set client type %d\n",
1746 session->pid, session->type);
1748 case VPU_IOC_GET_HW_FUSE_STATUS: {
1749 struct vpu_request req;
1751 vpu_debug(DEBUG_IOCTL, "pid %d get hw status %d\n",
1752 session->pid, session->type);
1753 if (copy_from_user(&req, (void __user *)arg, sizeof(req))) {
1754 vpu_err("error: get hw status copy_from_user failed\n");
1757 void *config = (session->type != VPU_ENC) ?
1758 ((void *)&pservice->dec_config) :
1759 ((void *)&pservice->enc_config);
1760 size_t size = (session->type != VPU_ENC) ?
1761 (sizeof(struct vpu_dec_config)) :
1762 (sizeof(struct vpu_enc_config));
1763 if (copy_to_user((void __user *)req.req,
1765 vpu_err("error: get hw status copy_to_user failed type %d\n",
1771 case VPU_IOC_SET_REG: {
1772 struct vpu_request req;
1773 struct vpu_reg *reg;
1775 vpu_service_power_on(data, pservice);
1777 vpu_debug(DEBUG_IOCTL, "pid %d set reg type %d\n",
1778 session->pid, session->type);
1779 if (copy_from_user(&req, (void __user *)arg,
1780 sizeof(struct vpu_request))) {
1781 vpu_err("error: set reg copy_from_user failed\n");
1785 reg = reg_init(data, session, (void __user *)req.req, req.size);
1789 mutex_lock(&pservice->lock);
1791 mutex_unlock(&pservice->lock);
1794 case VPU_IOC_GET_REG: {
1795 struct vpu_request req;
1796 struct vpu_reg *reg;
1799 vpu_service_power_on(data, pservice);
1801 vpu_debug(DEBUG_IOCTL, "pid %d get reg type %d\n",
1802 session->pid, session->type);
1803 if (copy_from_user(&req, (void __user *)arg,
1804 sizeof(struct vpu_request))) {
1805 vpu_err("error: get reg copy_from_user failed\n");
1809 ret = wait_event_timeout(session->wait,
1810 !list_empty(&session->done),
1813 if (!list_empty(&session->done)) {
1815 vpu_err("warning: pid %d wait task error ret %d\n",
1819 if (unlikely(ret < 0)) {
1820 vpu_err("error: pid %d wait task ret %d\n",
1822 } else if (ret == 0) {
1823 vpu_err("error: pid %d wait %d task done timeout\n",
1825 atomic_read(&session->task_running));
1831 int task_running = atomic_read(&session->task_running);
1833 mutex_lock(&pservice->lock);
1834 vpu_service_dump(pservice);
1836 atomic_set(&session->task_running, 0);
1837 atomic_sub(task_running,
1838 &pservice->total_running);
1839 dev_err(pservice->dev,
1840 "%d task is running but not return, reset hardware...",
1843 dev_err(pservice->dev, "done\n");
1845 vpu_service_session_clear(data, session);
1846 mutex_unlock(&pservice->lock);
1850 mutex_lock(&pservice->lock);
1851 reg = list_entry(session->done.next,
1852 struct vpu_reg, session_link);
1853 return_reg(data, reg, (u32 __user *)req.req);
1854 mutex_unlock(&pservice->lock);
1856 case VPU_IOC_PROBE_IOMMU_STATUS: {
1857 int iommu_enable = 1;
1859 vpu_debug(DEBUG_IOCTL, "VPU_IOC_PROBE_IOMMU_STATUS\n");
1861 if (copy_to_user((void __user *)arg,
1862 &iommu_enable, sizeof(int))) {
1863 vpu_err("error: iommu status copy_to_user failed\n");
1868 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1875 #ifdef CONFIG_COMPAT
1876 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1879 struct vpu_subdev_data *data =
1880 container_of(filp->f_path.dentry->d_inode->i_cdev,
1881 struct vpu_subdev_data, cdev);
1882 struct vpu_service_info *pservice = data->pservice;
1883 struct vpu_session *session = (struct vpu_session *)filp->private_data;
1886 vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1887 (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1888 if (NULL == session)
1892 case COMPAT_VPU_IOC_SET_CLIENT_TYPE: {
1893 session->type = (enum VPU_CLIENT_TYPE)arg;
1894 vpu_debug(DEBUG_IOCTL, "compat set client type %d\n",
1897 case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS: {
1898 struct compat_vpu_request req;
1900 vpu_debug(DEBUG_IOCTL, "compat get hw status %d\n",
1902 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1903 sizeof(struct compat_vpu_request))) {
1904 vpu_err("error: compat get hw status copy_from_user failed\n");
1907 void *config = (session->type != VPU_ENC) ?
1908 ((void *)&pservice->dec_config) :
1909 ((void *)&pservice->enc_config);
1910 size_t size = (session->type != VPU_ENC) ?
1911 (sizeof(struct vpu_dec_config)) :
1912 (sizeof(struct vpu_enc_config));
1914 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1916 vpu_err("error: compat get hw status copy_to_user failed type %d\n",
1922 case COMPAT_VPU_IOC_SET_REG: {
1923 struct compat_vpu_request req;
1924 struct vpu_reg *reg;
1926 vpu_service_power_on(data, pservice);
1928 vpu_debug(DEBUG_IOCTL, "compat set reg type %d\n",
1930 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1931 sizeof(struct compat_vpu_request))) {
1932 vpu_err("compat set_reg copy_from_user failed\n");
1935 reg = reg_init(data, session,
1936 compat_ptr((compat_uptr_t)req.req), req.size);
1940 mutex_lock(&pservice->lock);
1942 mutex_unlock(&pservice->lock);
1945 case COMPAT_VPU_IOC_GET_REG: {
1946 struct compat_vpu_request req;
1947 struct vpu_reg *reg;
1950 vpu_service_power_on(data, pservice);
1952 vpu_debug(DEBUG_IOCTL, "compat get reg type %d\n",
1954 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1955 sizeof(struct compat_vpu_request))) {
1956 vpu_err("compat get reg copy_from_user failed\n");
1960 ret = wait_event_timeout(session->wait,
1961 !list_empty(&session->done),
1964 if (!list_empty(&session->done)) {
1966 vpu_err("warning: pid %d wait task error ret %d\n",
1970 if (unlikely(ret < 0)) {
1971 vpu_err("error: pid %d wait task ret %d\n",
1973 } else if (ret == 0) {
1974 vpu_err("error: pid %d wait %d task done timeout\n",
1976 atomic_read(&session->task_running));
1982 int task_running = atomic_read(&session->task_running);
1984 mutex_lock(&pservice->lock);
1985 vpu_service_dump(pservice);
1987 atomic_set(&session->task_running, 0);
1988 atomic_sub(task_running,
1989 &pservice->total_running);
1990 dev_err(pservice->dev,
1991 "%d task is running but not return, reset hardware...",
1994 dev_err(pservice->dev, "done\n");
1996 vpu_service_session_clear(data, session);
1997 mutex_unlock(&pservice->lock);
2001 mutex_lock(&pservice->lock);
2002 reg = list_entry(session->done.next,
2003 struct vpu_reg, session_link);
2004 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
2005 mutex_unlock(&pservice->lock);
2007 case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS: {
2008 int iommu_enable = 1;
2010 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_PROBE_IOMMU_STATUS\n");
2012 if (copy_to_user(compat_ptr((compat_uptr_t)arg),
2013 &iommu_enable, sizeof(int))) {
2014 vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
2019 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
2027 static int vpu_service_check_hw(struct vpu_subdev_data *data)
2029 struct vpu_service_info *pservice = data->pservice;
2030 int ret = -EINVAL, i = 0;
2031 u32 hw_id = readl_relaxed(data->regs);
2033 hw_id = (hw_id >> 16) & 0xFFFF;
2034 dev_info(pservice->dev, "checking hw id %x\n", hw_id);
2035 data->hw_info = NULL;
2037 for (i = 0; i < ARRAY_SIZE(vcodec_info_set); i++) {
2038 const struct vcodec_info *info = &vcodec_info_set[i];
2040 if (hw_id == info->hw_id) {
2041 data->hw_id = info->hw_id;
2042 data->hw_info = info->hw_info;
2043 data->task_info = info->task_info;
2044 data->trans_info = info->trans_info;
2052 static int vpu_service_open(struct inode *inode, struct file *filp)
2054 struct vpu_subdev_data *data = container_of(
2055 inode->i_cdev, struct vpu_subdev_data, cdev);
2056 struct vpu_service_info *pservice = data->pservice;
2057 struct vpu_session *session = NULL;
2061 session = kzalloc(sizeof(*session), GFP_KERNEL);
2063 vpu_err("error: unable to allocate memory for vpu_session.");
2067 data->iommu_info->debug_level = debug;
2069 session->type = VPU_TYPE_BUTT;
2070 session->pid = current->pid;
2071 INIT_LIST_HEAD(&session->waiting);
2072 INIT_LIST_HEAD(&session->running);
2073 INIT_LIST_HEAD(&session->done);
2074 INIT_LIST_HEAD(&session->list_session);
2075 init_waitqueue_head(&session->wait);
2076 atomic_set(&session->task_running, 0);
2077 mutex_lock(&pservice->lock);
2078 list_add_tail(&session->list_session, &pservice->session);
2079 filp->private_data = (void *)session;
2080 mutex_unlock(&pservice->lock);
2082 dev_dbg(pservice->dev, "dev opened\n");
2084 return nonseekable_open(inode, filp);
2087 static int vpu_service_release(struct inode *inode, struct file *filp)
2089 struct vpu_subdev_data *data = container_of(
2090 inode->i_cdev, struct vpu_subdev_data, cdev);
2091 struct vpu_service_info *pservice = data->pservice;
2093 struct vpu_session *session = (struct vpu_session *)filp->private_data;
2096 if (NULL == session)
2099 task_running = atomic_read(&session->task_running);
2101 dev_err(pservice->dev,
2102 "error: session %d still has %d task running when closing\n",
2103 session->pid, task_running);
2106 wake_up(&session->wait);
2108 vpu_service_power_on(data, pservice);
2109 mutex_lock(&pservice->lock);
2110 /* remove this filp from the asynchronusly notified filp's */
2111 list_del_init(&session->list_session);
2112 vpu_service_session_clear(data, session);
2113 vcodec_iommu_clear(data->iommu_info, session);
2115 filp->private_data = NULL;
2116 mutex_unlock(&pservice->lock);
2118 dev_info(pservice->dev, "closed\n");
2123 static const struct file_operations vpu_service_fops = {
2124 .unlocked_ioctl = vpu_service_ioctl,
2125 .open = vpu_service_open,
2126 .release = vpu_service_release,
2127 #ifdef CONFIG_COMPAT
2128 .compat_ioctl = compat_vpu_service_ioctl,
2132 static irqreturn_t vdpu_irq(int irq, void *dev_id);
2133 static irqreturn_t vdpu_isr(int irq, void *dev_id);
2134 static irqreturn_t vepu_irq(int irq, void *dev_id);
2135 static irqreturn_t vepu_isr(int irq, void *dev_id);
2136 static void get_hw_info(struct vpu_subdev_data *data);
2138 static struct device *rockchip_get_sysmmu_dev(const char *compt)
2140 struct device_node *dn = NULL;
2141 struct platform_device *pd = NULL;
2142 struct device *ret = NULL;
2144 dn = of_find_compatible_node(NULL, NULL, compt);
2146 pr_err("can't find device node %s \r\n", compt);
2150 pd = of_find_device_by_node(dn);
2152 pr_err("can't find platform device in device node %s\n", compt);
2160 #ifdef CONFIG_IOMMU_API
2161 static inline void platform_set_sysmmu(struct device *iommu,
2164 dev->archdata.iommu = iommu;
2167 static inline void platform_set_sysmmu(struct device *iommu,
2173 int vcodec_sysmmu_fault_hdl(struct device *dev,
2174 enum rk_iommu_inttype itype,
2175 unsigned long pgtable_base,
2176 unsigned long fault_addr, unsigned int status)
2178 struct platform_device *pdev;
2179 struct vpu_service_info *pservice;
2180 struct vpu_subdev_data *data;
2185 pr_err("invalid NULL dev\n");
2189 pdev = container_of(dev, struct platform_device, dev);
2191 pr_err("invalid NULL platform_device\n");
2195 data = platform_get_drvdata(pdev);
2197 pr_err("invalid NULL vpu_subdev_data\n");
2201 pservice = data->pservice;
2202 if (pservice == NULL) {
2203 pr_err("invalid NULL vpu_service_info\n");
2207 if (pservice->reg_codec) {
2208 struct vpu_reg *reg = pservice->reg_codec;
2209 struct vcodec_mem_region *mem, *n;
2212 pr_err("vcodec, fault addr 0x%08lx\n", fault_addr);
2213 if (!list_empty(®->mem_region_list)) {
2214 list_for_each_entry_safe(mem, n, ®->mem_region_list,
2216 pr_err("vcodec, reg[%02u] mem region [%02d] 0x%lx %lx\n",
2217 mem->reg_idx, i, mem->iova, mem->len);
2221 pr_err("no memory region mapped\n");
2225 struct vpu_subdev_data *data = reg->data;
2226 u32 *base = (u32 *)data->dec_dev.regs;
2227 u32 len = data->hw_info->dec_reg_num;
2229 pr_err("current errror register set:\n");
2231 for (i = 0; i < len; i++)
2232 pr_err("reg[%02d] %08x\n",
2233 i, readl_relaxed(base + i));
2236 pr_alert("vcodec, page fault occur, reset hw\n");
2238 /* reg->reg[101] = 1; */
2245 static int vcodec_subdev_probe(struct platform_device *pdev,
2246 struct vpu_service_info *pservice)
2248 uint8_t *regs = NULL;
2250 uint32_t ioaddr = 0;
2251 struct resource *res = NULL;
2252 struct vpu_hw_info *hw_info = NULL;
2253 struct device *dev = &pdev->dev;
2254 struct device_node *np = pdev->dev.of_node;
2255 struct vpu_subdev_data *data = NULL;
2256 struct platform_device *sub_dev = NULL;
2257 struct device_node *sub_np = NULL;
2258 const char *name = np->name;
2259 char mmu_dev_dts_name[40];
2261 dev_info(dev, "probe device");
2263 data = devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
2267 data->pservice = pservice;
2269 of_property_read_u32(np, "dev_mode", (u32 *)&data->mode);
2271 if (pservice->reg_base == 0) {
2272 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2273 data->regs = devm_ioremap_resource(dev, res);
2274 if (IS_ERR(data->regs)) {
2275 ret = PTR_ERR(data->regs);
2278 ioaddr = res->start;
2280 data->regs = pservice->reg_base;
2281 ioaddr = pservice->ioaddr;
2284 sub_np = of_parse_phandle(np, "iommus", 0);
2286 sub_dev = of_find_device_by_node(sub_np);
2287 data->mmu_dev = &sub_dev->dev;
2290 /* Back to legacy iommu probe */
2291 if (!data->mmu_dev) {
2292 switch (data->mode) {
2293 case VCODEC_RUNNING_MODE_VPU:
2294 sprintf(mmu_dev_dts_name,
2295 VPU_IOMMU_COMPATIBLE_NAME);
2297 case VCODEC_RUNNING_MODE_RKVDEC:
2298 sprintf(mmu_dev_dts_name,
2299 VDEC_IOMMU_COMPATIBLE_NAME);
2301 case VCODEC_RUNNING_MODE_HEVC:
2303 sprintf(mmu_dev_dts_name,
2304 HEVC_IOMMU_COMPATIBLE_NAME);
2309 rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2311 platform_set_sysmmu(data->mmu_dev, dev);
2313 rockchip_iovmm_set_fault_handler
2314 (dev, vcodec_sysmmu_fault_hdl);
2317 dev_info(dev, "vpu mmu dec %p\n", data->mmu_dev);
2319 clear_bit(MMU_ACTIVATED, &data->state);
2320 vpu_service_power_on(data, pservice);
2322 vcodec_enter_mode(data);
2323 ret = vpu_service_check_hw(data);
2325 vpu_err("error: hw info check faild\n");
2329 hw_info = data->hw_info;
2330 regs = (u8 *)data->regs;
2332 if (hw_info->dec_reg_num) {
2333 data->dec_dev.iosize = hw_info->dec_io_size;
2334 data->dec_dev.regs = (u32 *)(regs + hw_info->dec_offset);
2337 if (hw_info->enc_reg_num) {
2338 data->enc_dev.iosize = hw_info->enc_io_size;
2339 data->enc_dev.regs = (u32 *)(regs + hw_info->enc_offset);
2342 data->reg_size = max(hw_info->dec_io_size, hw_info->enc_io_size);
2344 data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
2345 if (data->irq_enc > 0) {
2346 ret = devm_request_threaded_irq(dev, data->irq_enc,
2348 IRQF_SHARED, dev_name(dev),
2351 dev_err(dev, "error: can't request vepu irq %d\n",
2356 data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
2357 if (data->irq_dec > 0) {
2358 ret = devm_request_threaded_irq(dev, data->irq_dec,
2360 IRQF_SHARED, dev_name(dev),
2363 dev_err(dev, "error: can't request vdpu irq %d\n",
2368 atomic_set(&data->dec_dev.irq_count_codec, 0);
2369 atomic_set(&data->dec_dev.irq_count_pp, 0);
2370 atomic_set(&data->enc_dev.irq_count_codec, 0);
2371 atomic_set(&data->enc_dev.irq_count_pp, 0);
2373 of_property_read_u32(np, "allocator", (u32 *)&pservice->alloc_type);
2374 data->iommu_info = vcodec_iommu_info_create(dev, data->mmu_dev,
2375 pservice->alloc_type);
2376 dev_info(dev, "allocator is %s\n", pservice->alloc_type == 1 ? "drm" :
2377 (pservice->alloc_type == 2 ? "ion" : "null"));
2379 pservice->auto_freq = true;
2381 vcodec_exit_mode(data);
2382 /* create device node */
2383 ret = alloc_chrdev_region(&data->dev_t, 0, 1, name);
2385 dev_err(dev, "alloc dev_t failed\n");
2389 cdev_init(&data->cdev, &vpu_service_fops);
2391 data->cdev.owner = THIS_MODULE;
2392 data->cdev.ops = &vpu_service_fops;
2394 ret = cdev_add(&data->cdev, data->dev_t, 1);
2397 dev_err(dev, "add dev_t failed\n");
2401 data->cls = class_create(THIS_MODULE, name);
2403 if (IS_ERR(data->cls)) {
2404 ret = PTR_ERR(data->cls);
2405 dev_err(dev, "class_create err:%d\n", ret);
2409 data->child_dev = device_create(data->cls, dev,
2410 data->dev_t, "%s", name);
2412 platform_set_drvdata(pdev, data);
2414 INIT_LIST_HEAD(&data->lnk_service);
2415 list_add_tail(&data->lnk_service, &pservice->subdev_list);
2419 if (data->child_dev) {
2420 device_destroy(data->cls, data->dev_t);
2421 cdev_del(&data->cdev);
2422 unregister_chrdev_region(data->dev_t, 1);
2426 class_destroy(data->cls);
2430 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2432 struct vpu_service_info *pservice = data->pservice;
2434 vcodec_iommu_info_destroy(data->iommu_info);
2435 data->iommu_info = NULL;
2437 mutex_lock(&pservice->lock);
2438 cancel_delayed_work_sync(&pservice->power_off_work);
2439 vpu_service_power_off(pservice);
2440 mutex_unlock(&pservice->lock);
2442 device_destroy(data->cls, data->dev_t);
2443 class_destroy(data->cls);
2444 cdev_del(&data->cdev);
2445 unregister_chrdev_region(data->dev_t, 1);
2447 #ifdef CONFIG_DEBUG_FS
2448 if (!IS_ERR_OR_NULL(data->debugfs_dir))
2449 debugfs_remove_recursive(data->debugfs_dir);
2453 static void vcodec_read_property(struct device_node *np,
2454 struct vpu_service_info *pservice)
2456 pservice->mode_bit = 0;
2457 pservice->mode_ctrl = 0;
2458 pservice->subcnt = 0;
2459 pservice->grf_base = NULL;
2461 of_property_read_u32(np, "subcnt", &pservice->subcnt);
2463 if (pservice->subcnt > 1) {
2464 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2465 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2467 #ifdef CONFIG_MFD_SYSCON
2468 pservice->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2469 if (IS_ERR_OR_NULL(pservice->grf)) {
2470 pservice->grf = NULL;
2472 pservice->grf_base = RK_GRF_VIRT;
2474 vpu_err("can't find vpu grf property\n");
2480 pservice->grf_base = RK_GRF_VIRT;
2482 vpu_err("can't find vpu grf property\n");
2487 #ifdef CONFIG_RESET_CONTROLLER
2488 pservice->rst_a = devm_reset_control_get(pservice->dev, "video_a");
2489 pservice->rst_h = devm_reset_control_get(pservice->dev, "video_h");
2490 pservice->rst_v = devm_reset_control_get(pservice->dev, "video");
2492 if (IS_ERR_OR_NULL(pservice->rst_a)) {
2493 dev_warn(pservice->dev, "No aclk reset resource define\n");
2494 pservice->rst_a = NULL;
2497 if (IS_ERR_OR_NULL(pservice->rst_h)) {
2498 dev_warn(pservice->dev, "No hclk reset resource define\n");
2499 pservice->rst_h = NULL;
2502 if (IS_ERR_OR_NULL(pservice->rst_v)) {
2503 dev_warn(pservice->dev, "No core reset resource define\n");
2504 pservice->rst_v = NULL;
2508 of_property_read_string(np, "name", (const char **)&pservice->name);
2511 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2513 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2514 pservice->curr_mode = -1;
2516 wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2517 INIT_LIST_HEAD(&pservice->waiting);
2518 INIT_LIST_HEAD(&pservice->running);
2519 mutex_init(&pservice->lock);
2520 mutex_init(&pservice->shutdown_lock);
2521 atomic_set(&pservice->service_on, 1);
2523 INIT_LIST_HEAD(&pservice->done);
2524 INIT_LIST_HEAD(&pservice->session);
2525 INIT_LIST_HEAD(&pservice->subdev_list);
2527 pservice->reg_pproc = NULL;
2528 atomic_set(&pservice->total_running, 0);
2529 atomic_set(&pservice->enabled, 0);
2530 atomic_set(&pservice->power_on_cnt, 0);
2531 atomic_set(&pservice->power_off_cnt, 0);
2532 atomic_set(&pservice->reset_request, 0);
2534 INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2535 pservice->last.tv64 = 0;
2537 pservice->alloc_type = 0;
2540 static int vcodec_probe(struct platform_device *pdev)
2544 struct resource *res = NULL;
2545 struct device *dev = &pdev->dev;
2546 struct device_node *np = pdev->dev.of_node;
2547 struct vpu_service_info *pservice = NULL;
2548 struct vcodec_device_info *driver_data;
2550 pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info),
2554 pservice->dev = dev;
2556 driver_data = vcodec_get_drv_data(pdev);
2560 vcodec_read_property(np, pservice);
2561 vcodec_init_drvdata(pservice);
2563 /* Underscore for label, hyphens for name */
2564 switch (driver_data->device_type) {
2565 case VCODEC_DEVICE_TYPE_VPUX:
2566 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2568 case VCODEC_DEVICE_TYPE_VPUC:
2569 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2571 case VCODEC_DEVICE_TYPE_HEVC:
2572 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2574 case VCODEC_DEVICE_TYPE_RKVD:
2575 pservice->dev_id = VCODEC_DEVICE_ID_RKVDEC;
2578 dev_err(dev, "unsupported device type\n");
2582 if (0 > vpu_get_clk(pservice))
2585 if (of_property_read_bool(np, "reg")) {
2586 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2588 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2589 if (IS_ERR(pservice->reg_base)) {
2590 vpu_err("ioremap registers base failed\n");
2591 ret = PTR_ERR(pservice->reg_base);
2594 pservice->ioaddr = res->start;
2596 pservice->reg_base = 0;
2599 pm_runtime_enable(dev);
2601 if (of_property_read_bool(np, "subcnt")) {
2602 struct vpu_subdev_data *data = NULL;
2604 data = devm_kzalloc(dev, sizeof(struct vpu_subdev_data),
2609 for (i = 0; i < pservice->subcnt; i++) {
2610 struct device_node *sub_np;
2611 struct platform_device *sub_pdev;
2613 sub_np = of_parse_phandle(np, "rockchip,sub", i);
2614 sub_pdev = of_find_device_by_node(sub_np);
2616 vcodec_subdev_probe(sub_pdev, pservice);
2618 data->pservice = pservice;
2619 platform_set_drvdata(pdev, data);
2621 vcodec_subdev_probe(pdev, pservice);
2624 vpu_service_power_off(pservice);
2626 dev_info(dev, "init success\n");
2631 dev_info(dev, "init failed\n");
2632 vpu_service_power_off(pservice);
2633 wake_lock_destroy(&pservice->wake_lock);
2638 static int vcodec_remove(struct platform_device *pdev)
2640 struct vpu_subdev_data *data = platform_get_drvdata(pdev);
2642 vcodec_subdev_remove(data);
2644 pm_runtime_disable(data->pservice->dev);
2649 static void vcodec_shutdown(struct platform_device *pdev)
2651 struct vpu_subdev_data *data = platform_get_drvdata(pdev);
2652 struct vpu_service_info *pservice = data->pservice;
2653 struct device_node *np = pdev->dev.of_node;
2658 dev_info(&pdev->dev, "vcodec shutdown");
2660 mutex_lock(&pservice->shutdown_lock);
2661 atomic_set(&pservice->service_on, 0);
2662 mutex_unlock(&pservice->shutdown_lock);
2664 ret = readx_poll_timeout(atomic_read,
2665 &pservice->total_running,
2666 val, val == 0, 20000, 200000);
2667 if (ret == -ETIMEDOUT)
2668 dev_err(&pdev->dev, "wait total running time out\n");
2670 vcodec_exit_mode(data);
2672 vpu_service_clear(data);
2673 if (of_property_read_bool(np, "subcnt")) {
2674 for (i = 0; i < pservice->subcnt; i++) {
2675 struct device_node *sub_np;
2676 struct platform_device *sub_pdev;
2678 sub_np = of_parse_phandle(np, "rockchip,sub", i);
2679 sub_pdev = of_find_device_by_node(sub_np);
2681 vcodec_subdev_remove(platform_get_drvdata(sub_pdev));
2685 vcodec_subdev_remove(data);
2688 pm_runtime_disable(&pdev->dev);
2691 static const struct of_device_id vcodec_service_dt_ids[] = {
2693 .compatible = "rockchip,vpu_service",
2694 .data = &vpu_device_info,
2697 .compatible = "rockchip,hevc_service",
2698 .data = &hevc_device_info,
2701 .compatible = "rockchip,vpu_combo",
2702 .data = &vpu_combo_device_info,
2705 .compatible = "rockchip,rkvdec",
2706 .data = &rkvd_device_info,
2711 MODULE_DEVICE_TABLE(of, vcodec_service_dt_ids);
2713 static void *vcodec_get_drv_data(struct platform_device *pdev)
2715 struct vcodec_device_info *driver_data = NULL;
2716 const struct of_device_id *match;
2718 match = of_match_node(vcodec_service_dt_ids, pdev->dev.of_node);
2720 driver_data = (struct vcodec_device_info *)match->data;
2725 static struct platform_driver vcodec_driver = {
2726 .probe = vcodec_probe,
2727 .remove = vcodec_remove,
2728 .shutdown = vcodec_shutdown,
2730 .name = "rk-vcodec",
2731 .owner = THIS_MODULE,
2732 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2736 static void get_hw_info(struct vpu_subdev_data *data)
2738 struct vpu_service_info *pservice = data->pservice;
2739 struct vpu_dec_config *dec = &pservice->dec_config;
2740 struct vpu_enc_config *enc = &pservice->enc_config;
2742 if (of_machine_is_compatible("rockchip,rk2928") ||
2743 of_machine_is_compatible("rockchip,rk3036") ||
2744 of_machine_is_compatible("rockchip,rk3066") ||
2745 of_machine_is_compatible("rockchip,rk3126") ||
2746 of_machine_is_compatible("rockchip,rk3188"))
2747 dec->max_dec_pic_width = 1920;
2749 dec->max_dec_pic_width = 4096;
2751 if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2752 dec->h264_support = 3;
2753 dec->jpeg_support = 1;
2754 dec->mpeg4_support = 2;
2755 dec->vc1_support = 3;
2756 dec->mpeg2_support = 1;
2757 dec->pp_support = 1;
2758 dec->sorenson_support = 1;
2759 dec->ref_buf_support = 3;
2760 dec->vp6_support = 1;
2761 dec->vp7_support = 1;
2762 dec->vp8_support = 1;
2763 dec->avs_support = 1;
2764 dec->jpeg_ext_support = 0;
2765 dec->custom_mpeg4_support = 1;
2767 dec->mvc_support = 1;
2769 if (!of_machine_is_compatible("rockchip,rk3036")) {
2770 u32 config_reg = readl_relaxed(data->enc_dev.regs + 63);
2772 enc->max_encoded_width = config_reg & ((1 << 11) - 1);
2773 enc->h264_enabled = 1;
2774 enc->mpeg4_enabled = (config_reg >> 26) & 1;
2775 enc->jpeg_enabled = 1;
2776 enc->vs_enabled = (config_reg >> 24) & 1;
2777 enc->rgb_enabled = (config_reg >> 28) & 1;
2778 enc->reg_size = data->reg_size;
2783 pservice->auto_freq = true;
2784 vpu_debug(DEBUG_EXTRA_INFO,
2785 "vpu_service set to auto frequency mode\n");
2786 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2788 pservice->bug_dec_addr = of_machine_is_compatible
2789 ("rockchip,rk30xx");
2790 } else if (data->mode == VCODEC_RUNNING_MODE_RKVDEC) {
2791 pservice->auto_freq = true;
2792 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2794 /* disable frequency switch in hevc.*/
2795 pservice->auto_freq = false;
2799 static bool check_irq_err(struct vpu_task_info *task, u32 irq_status)
2801 vpu_debug(DEBUG_IRQ_CHECK, "task %s status %08x mask %08x\n",
2802 task->name, irq_status, task->error_mask);
2804 return (task->error_mask & irq_status) ? true : false;
2807 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2809 struct vpu_subdev_data *data = (struct vpu_subdev_data *)dev_id;
2810 struct vpu_service_info *pservice = data->pservice;
2811 struct vpu_task_info *task = NULL;
2812 struct vpu_device *dev = &data->dec_dev;
2813 u32 hw_id = data->hw_info->hw_id;
2817 task = &data->task_info[TASK_DEC];
2819 raw_status = readl_relaxed(dev->regs + task->reg_irq);
2820 dec_status = raw_status;
2822 vpu_debug(DEBUG_TASK_INFO,
2823 "vdpu_irq reg %d status %x mask: irq %x ready %x error %0x\n",
2824 task->reg_irq, dec_status,
2825 task->irq_mask, task->ready_mask, task->error_mask);
2827 if (dec_status & task->irq_mask) {
2828 time_record(task, 1);
2829 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq dec status %08x\n",
2831 if ((dec_status & 0x40001) == 0x40001) {
2834 readl_relaxed(dev->regs +
2836 } while ((dec_status & 0x40001) == 0x40001);
2839 if (check_irq_err(task, dec_status))
2840 atomic_add(1, &pservice->reset_request);
2842 writel_relaxed(0, dev->regs + task->reg_irq);
2844 /* set clock gating to save power */
2845 writel(task->gating_mask, dev->regs + task->reg_en);
2847 atomic_add(1, &dev->irq_count_codec);
2851 task = &data->task_info[TASK_PP];
2852 if (hw_id != HEVC_ID && hw_id != RKV_DEC_ID) {
2853 u32 pp_status = readl_relaxed(dev->regs + task->irq_mask);
2855 if (pp_status & task->irq_mask) {
2856 time_record(task, 1);
2857 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq pp status %08x\n",
2860 if (check_irq_err(task, dec_status))
2861 atomic_add(1, &pservice->reset_request);
2864 writel_relaxed(pp_status & (~task->reg_irq),
2865 dev->regs + task->irq_mask);
2866 atomic_add(1, &dev->irq_count_pp);
2871 pservice->irq_status = raw_status;
2873 if (atomic_read(&dev->irq_count_pp) ||
2874 atomic_read(&dev->irq_count_codec))
2875 return IRQ_WAKE_THREAD;
2880 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2882 struct vpu_subdev_data *data = (struct vpu_subdev_data *)dev_id;
2883 struct vpu_service_info *pservice = data->pservice;
2884 struct vpu_device *dev = &data->dec_dev;
2886 mutex_lock(&pservice->lock);
2887 if (atomic_read(&dev->irq_count_codec)) {
2888 atomic_sub(1, &dev->irq_count_codec);
2889 if (pservice->reg_codec == NULL) {
2890 vpu_err("error: dec isr with no task waiting\n");
2892 reg_from_run_to_done(data, pservice->reg_codec);
2893 /* avoid vpu timeout and can't recover problem */
2894 if (data->mode == VCODEC_RUNNING_MODE_VPU)
2895 VDPU_SOFT_RESET(data->regs);
2899 if (atomic_read(&dev->irq_count_pp)) {
2900 atomic_sub(1, &dev->irq_count_pp);
2901 if (pservice->reg_pproc == NULL)
2902 vpu_err("error: pp isr with no task waiting\n");
2904 reg_from_run_to_done(data, pservice->reg_pproc);
2907 mutex_unlock(&pservice->lock);
2911 static irqreturn_t vepu_irq(int irq, void *dev_id)
2913 struct vpu_subdev_data *data = (struct vpu_subdev_data *)dev_id;
2914 struct vpu_service_info *pservice = data->pservice;
2915 struct vpu_task_info *task = &data->task_info[TASK_ENC];
2916 struct vpu_device *dev = &data->enc_dev;
2919 irq_status = readl_relaxed(dev->regs + task->reg_irq);
2921 vpu_debug(DEBUG_TASK_INFO,
2922 "vepu_irq reg %d status %x mask: irq %x ready %x error %0x\n",
2923 task->reg_irq, irq_status,
2924 task->irq_mask, task->ready_mask, task->error_mask);
2926 vpu_debug(DEBUG_IRQ_STATUS, "vepu_irq enc status %08x\n", irq_status);
2928 if (likely(irq_status & task->irq_mask)) {
2929 time_record(task, 1);
2931 if (check_irq_err(task, irq_status))
2932 atomic_add(1, &pservice->reset_request);
2935 writel_relaxed(irq_status & (~task->irq_mask),
2936 dev->regs + task->reg_irq);
2938 atomic_add(1, &dev->irq_count_codec);
2942 pservice->irq_status = irq_status;
2944 if (atomic_read(&dev->irq_count_codec))
2945 return IRQ_WAKE_THREAD;
2950 static irqreturn_t vepu_isr(int irq, void *dev_id)
2952 struct vpu_subdev_data *data = (struct vpu_subdev_data *)dev_id;
2953 struct vpu_service_info *pservice = data->pservice;
2954 struct vpu_device *dev = &data->enc_dev;
2956 mutex_lock(&pservice->lock);
2957 if (atomic_read(&dev->irq_count_codec)) {
2958 atomic_sub(1, &dev->irq_count_codec);
2959 if (NULL == pservice->reg_codec)
2960 vpu_err("error: enc isr with no task waiting\n");
2962 reg_from_run_to_done(data, pservice->reg_codec);
2965 mutex_unlock(&pservice->lock);
2969 module_platform_driver(vcodec_driver);
2970 MODULE_LICENSE("GPL v2");