2 * Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
3 * author: chenhengming chm@rock-chips.com
4 * Alpha Lin, alpha.lin@rock-chips.com
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #ifndef __ARCH_ARM_MACH_ROCKCHIP_VCODEC_HW_VPU2_H
18 #define __ARCH_ARM_MACH_ROCKCHIP_VCODEC_HW_VPU2_H
20 #include "vcodec_hw_info.h"
22 /* hardware information */
23 #define REG_NUM_VPU2_DEC (159)
24 #define REG_NUM_VPU2_DEC_START (50)
25 #define REG_NUM_VPU2_DEC_END (159)
26 #define REG_NUM_VPU2_PP (41)
27 #define REG_NUM_VPU2_DEC_PP (159)
28 #define REG_NUM_VPU2_ENC (184)
29 #define REG_NUM_VPU2_DEC_OFFSET (0x400)
31 /* enable and gating register */
32 #define VPU2_REG_EN_ENC 103
33 #define VPU2_REG_ENC_GATE 109
34 #define VPU2_REG_ENC_GATE_BIT BIT(4)
36 #define VPU2_REG_EN_DEC 57
37 #define VPU2_REG_DEC_GATE 57
38 #define VPU2_REG_DEC_GATE_BIT BIT(4)
39 #define VPU2_REG_EN_PP 41
40 #define VPU2_REG_PP_GATE 1
41 #define VPU2_REG_PP_GATE_BIT BIT(8)
42 #define VPU2_REG_EN_DEC_PP 57
43 #define VPU2_REG_DEC_PP_GATE 57
44 #define VPU2_REG_DEC_PP_GATE_BIT BIT(4)
46 /* interrupt and error status register */
47 #define VPU2_DEC_INTERRUPT_REGISTER 55
48 #define VPU2_DEC_INTERRUPT_BIT BIT(0)
49 #define VPU2_DEC_READY_BIT BIT(4)
50 #define VPU2_DEC_BUS_ERROR_BIT BIT(5)
51 #define VPU2_DEC_BUFFER_EMPTY_BIT BIT(6)
52 #define VPU2_DEC_ASO_ERROR_BIT BIT(8)
53 #define VPU2_DEC_SLICE_DONE_BIT BIT(9)
54 #define VPU2_DEC_STREAM_ERROR_BIT BIT(12)
55 #define VPU2_DEC_TIMEOUT_BIT BIT(13)
56 #define VPU2_DEC_ERR_MASK (VPU2_DEC_BUS_ERROR_BIT \
57 |VPU2_DEC_BUFFER_EMPTY_BIT \
58 |VPU2_DEC_STREAM_ERROR_BIT \
59 |VPU2_DEC_TIMEOUT_BIT)
61 #define VPU2_PP_INTERRUPT_REGISTER 40
62 #define VPU2_PP_INTERRUPT_BIT BIT(0)
63 #define VPU2_PP_READY_BIT BIT(2)
64 #define VPU2_PP_BUS_ERROR_BIT BIT(3)
65 #define VPU2_PP_ERR_MASK VPU2_PP_BUS_ERROR_BIT
66 #define VPU2_PP_PIPELINE_REGISTER 41
67 #define VPU2_PP_PIPELINE_MODE_BIT BIT(4)
69 #define VPU2_ENC_INTERRUPT_REGISTER 109
70 #define VPU2_ENC_INTERRUPT_BIT BIT(0)
71 #define VPU2_ENC_READY_BIT BIT(1)
72 #define VPU2_ENC_BUS_ERROR_BIT BIT(4)
73 #define VPU2_ENC_BUFFER_FULL_BIT BIT(5)
74 #define VPU2_ENC_TIMEOUT_BIT BIT(6)
75 #define VPU2_ENC_ERR_MASK (VPU2_ENC_BUS_ERROR_BIT \
76 |VPU2_ENC_BUFFER_FULL_BIT \
77 |VPU2_ENC_TIMEOUT_BIT)
79 static const enum FORMAT_TYPE vpu2_dec_fmt_tbl[] = {
98 static enum FORMAT_TYPE vpu2_dec_get_fmt(u32 *regs)
100 u32 fmt_id = regs[53] & 0xf;
101 enum FORMAT_TYPE type = vpu2_dec_fmt_tbl[fmt_id];
105 static enum FORMAT_TYPE vpu2_pp_get_fmt(u32 *regs)
110 static const enum FORMAT_TYPE vpu2_enc_fmt_tbl[] = {
117 static enum FORMAT_TYPE vpu2_enc_get_fmt(u32 *regs)
119 u32 fmt_id = (regs[VPU2_REG_EN_ENC] >> 4) & 0x3;
120 enum FORMAT_TYPE type = vpu2_enc_fmt_tbl[fmt_id];
124 static struct vpu_task_info task_vpu2[TASK_TYPE_BUTT] = {
128 .reg_en = VPU2_REG_EN_ENC,
129 .reg_gating = VPU2_REG_ENC_GATE,
130 .reg_irq = VPU2_ENC_INTERRUPT_REGISTER,
136 .gating_mask = VPU2_REG_ENC_GATE_BIT,
138 .irq_mask = VPU2_ENC_INTERRUPT_BIT,
139 .ready_mask = VPU2_ENC_READY_BIT,
140 .error_mask = VPU2_ENC_ERR_MASK,
141 .get_fmt = vpu2_enc_get_fmt,
146 .reg_en = VPU2_REG_EN_DEC,
147 .reg_irq = VPU2_DEC_INTERRUPT_REGISTER,
151 .reg_pipe = VPU2_PP_PIPELINE_REGISTER,
153 .gating_mask = VPU2_REG_DEC_GATE_BIT,
154 .pipe_mask = VPU2_PP_PIPELINE_MODE_BIT,
155 .irq_mask = VPU2_DEC_INTERRUPT_BIT,
156 .ready_mask = VPU2_DEC_READY_BIT,
157 .error_mask = VPU2_DEC_ERR_MASK,
158 .get_fmt = vpu2_dec_get_fmt,
162 .reg_en = VPU2_REG_EN_PP,
163 .reg_irq = VPU2_PP_INTERRUPT_REGISTER,
167 .reg_pipe = VPU2_PP_PIPELINE_REGISTER,
169 .gating_mask = VPU2_REG_PP_GATE_BIT,
170 .pipe_mask = VPU2_PP_PIPELINE_MODE_BIT,
171 .irq_mask = VPU2_PP_INTERRUPT_BIT,
172 .ready_mask = VPU2_PP_READY_BIT,
173 .error_mask = VPU2_PP_ERR_MASK,
174 .get_fmt = vpu2_pp_get_fmt,
177 .name = "vpu2_dec_pp",
178 .reg_en = VPU2_REG_EN_DEC_PP,
179 .reg_irq = VPU2_DEC_INTERRUPT_REGISTER,
183 .reg_pipe = VPU2_PP_PIPELINE_REGISTER,
185 .gating_mask = VPU2_REG_DEC_GATE_BIT,
186 .pipe_mask = VPU2_PP_PIPELINE_MODE_BIT,
187 .irq_mask = VPU2_DEC_INTERRUPT_BIT,
188 .ready_mask = VPU2_DEC_READY_BIT,
189 .error_mask = VPU2_DEC_ERR_MASK,
190 .get_fmt = vpu2_dec_get_fmt,
194 static struct vpu_hw_info hw_vpu2 = {
198 .enc_reg_num = REG_NUM_VPU2_ENC,
199 .enc_io_size = REG_NUM_VPU2_ENC * 4,
201 .dec_offset = REG_NUM_VPU2_DEC_OFFSET,
202 .dec_reg_num = REG_NUM_VPU2_DEC_PP,
203 .dec_io_size = REG_NUM_VPU2_DEC_PP * 4,
205 .base_dec = REG_NUM_VPU2_DEC_START,
208 .end_dec = REG_NUM_VPU2_DEC_END,
209 .end_pp = REG_NUM_VPU2_PP,
210 .end_dec_pp = REG_NUM_VPU2_DEC_END,
214 * file handle translate information
216 DEF_FMT_TRANS_TBL(vpu2_jpegd,
217 131, 64, 63, 61, 21, 22
220 DEF_FMT_TRANS_TBL(vpu2_h264d,
221 64, 63, 84, 85, 86, 87, 88, 89,
222 90, 91, 92, 93, 94, 95, 96, 97,
226 DEF_FMT_TRANS_TBL(vpu2_vp6d,
227 64, 63, 131, 136, 145, 61
230 DEF_FMT_TRANS_TBL(vpu2_vp8d,
231 149, 64, 63, 131, 136, 137, 140, 141,
232 142, 143, 144, 145, 146, 147, 61
235 DEF_FMT_TRANS_TBL(vpu2_vc1d,
236 64, 63, 131, 148, 134, 135, 145, 62
239 DEF_FMT_TRANS_TBL(vpu2_default_dec,
240 64, 63, 131, 148, 134, 135, 61, 62
243 DEF_FMT_TRANS_TBL(vpu2_default_pp,
244 12, 13, 18, 19, 20, 21, 22
247 DEF_FMT_TRANS_TBL(vpu2_default_enc,
248 77, 78, 56, 57, 63, 64, 48, 49,
252 const struct vpu_trans_info trans_vpu2[FMT_TYPE_BUTT] = {
253 SETUP_FMT_TBL(FMT_JPEGD , vpu2_jpegd),
254 SETUP_FMT_TBL(FMT_H263D , vpu2_default_dec),
255 SETUP_FMT_TBL(FMT_H264D , vpu2_h264d),
256 EMPTY_FMT_TBL(FMT_H265D),
258 SETUP_FMT_TBL(FMT_MPEG1D, vpu2_default_dec),
259 SETUP_FMT_TBL(FMT_MPEG2D, vpu2_default_dec),
260 SETUP_FMT_TBL(FMT_MPEG4D, vpu2_default_dec),
262 SETUP_FMT_TBL(FMT_VP6D , vpu2_vp6d),
263 SETUP_FMT_TBL(FMT_VP7D , vpu2_default_dec),
264 SETUP_FMT_TBL(FMT_VP8D , vpu2_vp8d),
265 EMPTY_FMT_TBL(FMT_VP9D),
267 SETUP_FMT_TBL(FMT_PP , vpu2_default_pp),
269 SETUP_FMT_TBL(FMT_VC1D , vpu2_vc1d),
270 SETUP_FMT_TBL(FMT_AVSD , vpu2_default_dec),
272 SETUP_FMT_TBL(FMT_JPEGE , vpu2_default_enc),
273 SETUP_FMT_TBL(FMT_H264E , vpu2_default_enc),
274 SETUP_FMT_TBL(FMT_VP8E , vpu2_default_enc),