2 * Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
3 * author: chenhengming chm@rock-chips.com
4 * Alpha Lin, alpha.lin@rock-chips.com
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #ifndef __ARCH_ARM_MACH_ROCKCHIP_VCODEC_HW_VPU_H
18 #define __ARCH_ARM_MACH_ROCKCHIP_VCODEC_HW_VPU_H
20 #include "vcodec_hw_info.h"
22 /* hardware information */
23 #define REG_NUM_9190_DEC (60)
24 #define REG_NUM_9190_PP (41)
25 #define REG_NUM_9190_DEC_PP (REG_NUM_9190_DEC + REG_NUM_9190_PP)
27 #define REG_NUM_DEC_PP (REG_NUM_9190_DEC + REG_NUM_9190_PP)
29 #define REG_NUM_ENC_8270 (96)
30 #define REG_SIZE_ENC_8270 (0x200)
31 #define REG_NUM_ENC_4831 (164)
32 #define REG_SIZE_ENC_4831 (0x400)
35 /* enable and gating register */
36 #define VPU_REG_EN_ENC 14
37 #define VPU_REG_ENC_GATE 2
38 #define VPU_REG_ENC_GATE_BIT BIT(4)
40 #define VPU_REG_EN_DEC 1
41 #define VPU_REG_DEC_GATE 2
42 #define VPU_REG_DEC_GATE_BIT BIT(10)
43 #define VPU_REG_EN_PP 0
44 #define VPU_REG_PP_GATE 1
45 #define VPU_REG_PP_GATE_BIT BIT(8)
46 #define VPU_REG_EN_DEC_PP 1
47 #define VPU_REG_DEC_PP_GATE 61
48 #define VPU_REG_DEC_PP_GATE_BIT BIT(8)
50 /* interrupt and error status register */
51 #define VPU_DEC_INTERRUPT_REGISTER 1
52 #define VPU_DEC_INTERRUPT_BIT BIT(8)
53 #define VPU_DEC_READY_BIT BIT(12)
54 #define VPU_DEC_BUS_ERROR_BIT BIT(13)
55 #define VPU_DEC_BUFFER_EMPTY_BIT BIT(14)
56 #define VPU_DEC_ASO_ERROR_BIT BIT(15)
57 #define VPU_DEC_STREAM_ERROR_BIT BIT(16)
58 #define VPU_DEC_SLICE_DONE_BIT BIT(17)
59 #define VPU_DEC_TIMEOUT_BIT BIT(18)
60 #define VPU_DEC_ERR_MASK (VPU_DEC_BUS_ERROR_BIT \
61 |VPU_DEC_BUFFER_EMPTY_BIT \
62 |VPU_DEC_STREAM_ERROR_BIT \
65 #define VPU_PP_INTERRUPT_REGISTER 60
66 #define VPU_PP_PIPELINE_MODE_BIT BIT(1)
67 #define VPU_PP_INTERRUPT_BIT BIT(8)
68 #define VPU_PP_READY_BIT BIT(12)
69 #define VPU_PP_BUS_ERROR_BIT BIT(13)
70 #define VPU_PP_ERR_MASK VPU_PP_BUS_ERROR_BIT
72 #define VPU_ENC_INTERRUPT_REGISTER 1
73 #define VPU_ENC_INTERRUPT_BIT BIT(0)
74 #define VPU_ENC_READY_BIT BIT(2)
75 #define VPU_ENC_BUS_ERROR_BIT BIT(3)
76 #define VPU_ENC_BUFFER_FULL_BIT BIT(5)
77 #define VPU_ENC_TIMEOUT_BIT BIT(6)
78 #define VPU_ENC_ERR_MASK (VPU_ENC_BUS_ERROR_BIT \
79 |VPU_ENC_BUFFER_FULL_BIT \
82 static const enum FORMAT_TYPE vpu_dec_fmt_tbl[] = {
101 static enum FORMAT_TYPE vpu_dec_get_fmt(u32 *regs)
103 u32 fmt_id = (regs[3] >> 28) & 0xf;
104 enum FORMAT_TYPE type = vpu_dec_fmt_tbl[fmt_id];
108 static enum FORMAT_TYPE vpu_pp_get_fmt(u32 *regs)
113 static const enum FORMAT_TYPE vpu_enc_fmt_tbl[] = {
120 static enum FORMAT_TYPE vpu_enc_get_fmt(u32 *regs)
122 u32 fmt_id = (regs[VPU_REG_EN_ENC] >> 1) & 0x3;
123 enum FORMAT_TYPE type = vpu_enc_fmt_tbl[fmt_id];
127 static struct vpu_task_info task_vpu[TASK_TYPE_BUTT] = {
131 .reg_en = VPU_REG_EN_ENC,
132 .reg_irq = VPU_ENC_INTERRUPT_REGISTER,
140 .irq_mask = VPU_ENC_INTERRUPT_BIT,
141 .ready_mask = VPU_ENC_READY_BIT,
142 .error_mask = VPU_ENC_ERR_MASK,
143 .get_fmt = vpu_enc_get_fmt,
148 .reg_en = VPU_REG_EN_DEC,
149 .reg_irq = VPU_DEC_INTERRUPT_REGISTER,
153 .reg_pipe = VPU_PP_INTERRUPT_REGISTER,
156 .pipe_mask = VPU_PP_PIPELINE_MODE_BIT,
157 .irq_mask = VPU_DEC_INTERRUPT_BIT,
158 .ready_mask = VPU_DEC_READY_BIT,
159 .error_mask = VPU_DEC_ERR_MASK,
160 .get_fmt = vpu_dec_get_fmt,
164 .reg_en = VPU_REG_EN_PP,
165 .reg_irq = VPU_PP_INTERRUPT_REGISTER,
169 .reg_pipe = VPU_PP_INTERRUPT_REGISTER,
172 .pipe_mask = VPU_PP_PIPELINE_MODE_BIT,
173 .irq_mask = VPU_PP_INTERRUPT_BIT,
174 .ready_mask = VPU_PP_READY_BIT,
175 .error_mask = VPU_PP_ERR_MASK,
176 .get_fmt = vpu_pp_get_fmt,
179 .name = "vpu_dec_pp",
181 .reg_en = VPU_REG_EN_DEC,
182 .reg_irq = VPU_DEC_INTERRUPT_REGISTER,
186 .reg_pipe = VPU_PP_INTERRUPT_REGISTER,
189 .pipe_mask = VPU_PP_PIPELINE_MODE_BIT,
190 .irq_mask = VPU_DEC_INTERRUPT_BIT,
191 .ready_mask = VPU_DEC_READY_BIT,
192 .error_mask = VPU_DEC_ERR_MASK,
193 .get_fmt = vpu_dec_get_fmt,
197 static struct vpu_hw_info hw_vpu_8270 = {
198 .hw_id = VPU_ID_8270,
201 .enc_reg_num = REG_NUM_ENC_8270,
202 .enc_io_size = REG_NUM_ENC_8270 * 4,
204 .dec_offset = REG_SIZE_ENC_8270,
205 .dec_reg_num = REG_NUM_9190_DEC_PP,
206 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
209 .base_pp = VPU_PP_INTERRUPT_REGISTER,
211 .end_dec = REG_NUM_9190_DEC,
212 .end_pp = REG_NUM_9190_DEC_PP,
213 .end_dec_pp = REG_NUM_9190_DEC_PP,
216 static struct vpu_hw_info hw_vpu_4831 = {
217 .hw_id = VPU_ID_4831,
220 .enc_reg_num = REG_NUM_ENC_4831,
221 .enc_io_size = REG_NUM_ENC_4831 * 4,
223 .dec_offset = REG_SIZE_ENC_4831,
224 .dec_reg_num = REG_NUM_9190_DEC_PP,
225 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
228 .base_pp = VPU_PP_INTERRUPT_REGISTER,
230 .end_dec = REG_NUM_9190_DEC,
231 .end_pp = REG_NUM_9190_DEC_PP,
232 .end_dec_pp = REG_NUM_9190_DEC_PP,
235 static struct vpu_hw_info hw_vpu_9190 = {
236 .hw_id = VPU_DEC_ID_9190,
243 .dec_reg_num = REG_NUM_9190_DEC_PP,
244 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
247 .base_pp = VPU_PP_INTERRUPT_REGISTER,
249 .end_dec = REG_NUM_9190_DEC,
250 .end_pp = REG_NUM_9190_DEC_PP,
251 .end_dec_pp = REG_NUM_9190_DEC_PP,
255 * file handle translate information
257 DEF_FMT_TRANS_TBL(vpu_jpegd,
258 12, 13, 14, 40, 66, 67
261 DEF_FMT_TRANS_TBL(vpu_h264d,
262 12, 13, 14, 15, 16, 17, 18, 19,
263 20, 21, 22, 23, 24, 25, 26, 27,
267 DEF_FMT_TRANS_TBL(vpu_vp6d,
268 12, 13, 14, 18, 27, 40
271 DEF_FMT_TRANS_TBL(vpu_vp8d,
272 10, 12, 13, 14, 18, 19, 22, 23,
273 24, 25, 26, 27, 28, 29, 40
276 DEF_FMT_TRANS_TBL(vpu_vc1d,
277 12, 13, 14, 15, 16, 17, 27, 41
280 DEF_FMT_TRANS_TBL(vpu_defaultd,
281 12, 13, 14, 15, 16, 17, 40, 41
284 DEF_FMT_TRANS_TBL(vpu_default_pp,
285 63, 64, 65, 66, 67, 73, 74
288 DEF_FMT_TRANS_TBL(vpu_vp8e,
289 5, 6, 7, 8, 9, 10, 11, 12, 13, 16, 17, 26, 51, 52, 58, 59
292 DEF_FMT_TRANS_TBL(vpu_defaulte,
293 5, 6, 7, 8, 9, 10, 11, 12, 13, 51
296 const struct vpu_trans_info trans_vpu[FMT_TYPE_BUTT] = {
297 SETUP_FMT_TBL(FMT_JPEGD , vpu_jpegd),
298 SETUP_FMT_TBL(FMT_H263D , vpu_defaultd),
299 SETUP_FMT_TBL(FMT_H264D , vpu_h264d),
300 EMPTY_FMT_TBL(FMT_H265D),
302 SETUP_FMT_TBL(FMT_MPEG1D, vpu_defaultd),
303 SETUP_FMT_TBL(FMT_MPEG2D, vpu_defaultd),
304 SETUP_FMT_TBL(FMT_MPEG4D, vpu_defaultd),
306 SETUP_FMT_TBL(FMT_VP6D , vpu_vp6d),
307 SETUP_FMT_TBL(FMT_VP7D , vpu_defaultd),
308 SETUP_FMT_TBL(FMT_VP8D , vpu_vp8d),
309 EMPTY_FMT_TBL(FMT_VP9D),
311 SETUP_FMT_TBL(FMT_VC1D , vpu_vc1d),
312 SETUP_FMT_TBL(FMT_AVSD , vpu_defaultd),
314 SETUP_FMT_TBL(FMT_PP , vpu_default_pp),
316 SETUP_FMT_TBL(FMT_JPEGE , vpu_defaulte),
317 SETUP_FMT_TBL(FMT_H264E , vpu_defaulte),
318 SETUP_FMT_TBL(FMT_VP8E , vpu_vp8e),