drivers/video/rockchip/vcodec/vcodec_hw_rkv.h

   1 /**
   2  * Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
   3  * author: chenhengming chm@rock-chips.com
   4  *         Alpha Lin, alpha.lin@rock-chips.com
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #ifndef __ARCH_ARM_MACH_ROCKCHIP_VCODEC_HW_RKV_H
  18 #define __ARCH_ARM_MACH_ROCKCHIP_VCODEC_HW_RKV_H
  19
  20 #include "vcodec_hw_info.h"
  21
  22 /* hardware information */
  23 #define REG_NUM_HEVC_DEC                (68)
  24 #define REG_NUM_RKV_DEC                 (78)
  25
  26 /* enable and gating register */
  27 #define RKV_REG_EN_DEC                  1
  28 #define RKV_REG_DEC_GATING_BIT          BIT(1)
  29
  30 /* interrupt and error status register */
  31 #define HEVC_INTERRUPT_REGISTER         1
  32 #define HEVC_INTERRUPT_BIT              BIT(8)
  33 #define HEVC_DEC_INT_RAW_BIT            BIT(9)
  34 #define HEVC_READY_BIT                  BIT(12)
  35 #define HEVC_DEC_BUS_ERROR_BIT          BIT(13)
  36 #define HEVC_DEC_STR_ERROR_BIT          BIT(14)
  37 #define HEVC_DEC_TIMEOUT_BIT            BIT(15)
  38 #define HEVC_DEC_BUFFER_EMPTY_BIT       BIT(16)
  39 #define HEVC_DEC_COLMV_ERROR_BIT        BIT(17)
  40 #define HEVC_DEC_ERR_MASK               (HEVC_DEC_BUS_ERROR_BIT \
  41                                         |HEVC_DEC_STR_ERROR_BIT \
  42                                         |HEVC_DEC_TIMEOUT_BIT \
  43                                         |HEVC_DEC_BUFFER_EMPTY_BIT \
  44                                         |HEVC_DEC_COLMV_ERROR_BIT)
  45
  46 #define RKV_DEC_INTERRUPT_REGISTER      1
  47 #define RKV_DEC_INTERRUPT_BIT           BIT(8)
  48 #define RKV_DEC_INT_RAW_BIT             BIT(9)
  49 #define RKV_DEC_READY_BIT               BIT(12)
  50 #define RKV_DEC_BUS_ERROR_BIT           BIT(13)
  51 #define RKV_DEC_STR_ERROR_BIT           BIT(14)
  52 #define RKV_DEC_TIMEOUT_BIT             BIT(15)
  53 #define RKV_DEC_BUFFER_EMPTY_BIT        BIT(16)
  54 #define RKV_DEC_COLMV_ERROR_BIT         BIT(17)
  55 #define RKV_DEC_ERR_MASK                (RKV_DEC_BUS_ERROR_BIT \
  56                                         |RKV_DEC_STR_ERROR_BIT \
  57                                         |RKV_DEC_TIMEOUT_BIT \
  58                                         |RKV_DEC_BUFFER_EMPTY_BIT \
  59                                         |RKV_DEC_COLMV_ERROR_BIT)
  60
  61 static const enum FORMAT_TYPE rkv_dec_fmt_tbl[] = {
  62         [0]  = FMT_H265D,
  63         [1]  = FMT_H264D,
  64         [2]  = FMT_VP9D,
  65         [3]  = FMT_TYPE_BUTT,
  66 };
  67
  68 static enum FORMAT_TYPE rkv_dec_get_fmt(u32 *regs)
  69 {
  70         u32 fmt_id = (regs[2] >> 20) & 0x3;
  71         enum FORMAT_TYPE type = rkv_dec_fmt_tbl[fmt_id];
  72         return type;
  73 }
  74
  75 static struct vpu_task_info task_rkv[TASK_TYPE_BUTT] = {
  76         {
  77                 .name = "invalid",
  78                 .reg_en = 0,
  79                 .reg_irq = 0,
  80                 .reg_len = 0,
  81                 .reg_dir_mv = 0,
  82                 .reg_pps = 0,
  83                 .reg_pipe = 0,
  84                 .enable_mask = 0,
  85                 .gating_mask = 0,
  86                 .pipe_mask = 0,
  87                 .irq_mask = 0,
  88                 .ready_mask = 0,
  89                 .error_mask = 0,
  90                 .get_fmt = NULL,
  91         },
  92         {
  93                 .name = "rkvdec",
  94                 .reg_en = RKV_REG_EN_DEC,
  95                 .reg_irq = RKV_DEC_INTERRUPT_REGISTER,
  96                 .reg_len = 4,
  97                 .reg_dir_mv = 52,
  98                 .reg_pps = 42,
  99                 .reg_pipe = 0,
 100                 .enable_mask = 0,
 101                 .gating_mask = RKV_REG_DEC_GATING_BIT,
 102                 .irq_mask = HEVC_INTERRUPT_BIT,
 103                 .pipe_mask = 0,
 104                 .ready_mask = HEVC_READY_BIT,
 105                 .error_mask = HEVC_DEC_ERR_MASK,
 106                 .get_fmt = rkv_dec_get_fmt,
 107         },
 108         {
 109                 .name = "invalid",
 110                 .reg_en = 0,
 111                 .reg_irq = 0,
 112                 .reg_len = 0,
 113                 .reg_dir_mv = 0,
 114                 .reg_pps = 0,
 115                 .reg_pipe = 0,
 116                 .enable_mask = 0,
 117                 .gating_mask = 0,
 118                 .pipe_mask = 0,
 119                 .irq_mask = 0,
 120                 .ready_mask = 0,
 121                 .error_mask = 0,
 122                 .get_fmt = NULL,
 123         },
 124         {
 125                 .name = "invalid",
 126                 .reg_en = 0,
 127                 .reg_irq = 0,
 128                 .reg_len = 0,
 129                 .reg_dir_mv = 0,
 130                 .reg_pps = 0,
 131                 .reg_pipe = 0,
 132                 .enable_mask = 0,
 133                 .gating_mask = 0,
 134                 .pipe_mask = 0,
 135                 .irq_mask = 0,
 136                 .ready_mask = 0,
 137                 .error_mask = 0,
 138                 .get_fmt = NULL,
 139         },};
 140
 141 static struct vpu_hw_info hw_rkhevc = {
 142         .hw_id          = HEVC_ID,
 143
 144         .enc_offset     = 0,
 145         .enc_reg_num    = 0,
 146         .enc_io_size    = 0,
 147
 148         .dec_offset     = 0,
 149         .dec_reg_num    = REG_NUM_HEVC_DEC,
 150         .dec_io_size    = REG_NUM_HEVC_DEC * 4,
 151
 152         /* NOTE: can not write to register 0 */
 153         .base_dec       = 1,
 154         .base_pp        = 0,
 155         .base_dec_pp    = 0,
 156         .end_dec        = REG_NUM_HEVC_DEC,
 157         .end_pp         = 0,
 158         .end_dec_pp     = 0,
 159 };
 160
 161 static struct vpu_hw_info hw_rkvdec = {
 162         .hw_id          = RKV_DEC_ID,
 163
 164         .enc_offset     = 0,
 165         .enc_reg_num    = 0,
 166         .enc_io_size    = 0,
 167
 168         .dec_offset     = 0x0,
 169         .dec_reg_num    = REG_NUM_RKV_DEC,
 170         .dec_io_size    = REG_NUM_RKV_DEC * 4,
 171
 172         /* NOTE: can not write to register 0 */
 173         .base_dec       = 1,
 174         .base_pp        = 0,
 175         .base_dec_pp    = 0,
 176         .end_dec        = REG_NUM_RKV_DEC,
 177         .end_pp         = 0,
 178         .end_dec_pp     = 0,
 179 };
 180
 181 /*
 182  * file handle translate information
 183  */
 184 DEF_FMT_TRANS_TBL(rkv_h264d,
 185                   4,  6,  7,  10, 11, 12, 13, 14,
 186                   15, 16, 17, 18, 19, 20, 21, 22,
 187                   23, 24, 41, 42, 43, 48, 75
 188 );
 189
 190 DEF_FMT_TRANS_TBL(rkv_h265d,
 191                   4,  6,  7,  10, 11, 12, 13, 14,
 192                   15, 16, 17, 18, 19, 20, 21, 22,
 193                   23, 24, 42, 43
 194 );
 195
 196 DEF_FMT_TRANS_TBL(rkv_vp9d,
 197                   4,  6,  7,  11, 12, 13, 14, 15,
 198                   16, 52
 199 );
 200
 201 const struct vpu_trans_info trans_rkv[FMT_TYPE_BUTT] = {
 202         EMPTY_FMT_TBL(FMT_JPEGD),
 203         EMPTY_FMT_TBL(FMT_H263D),
 204         SETUP_FMT_TBL(FMT_H264D , rkv_h264d),
 205         SETUP_FMT_TBL(FMT_H265D , rkv_h265d),
 206
 207         EMPTY_FMT_TBL(FMT_MPEG1D),
 208         EMPTY_FMT_TBL(FMT_MPEG2D),
 209         EMPTY_FMT_TBL(FMT_MPEG4D),
 210
 211         EMPTY_FMT_TBL(FMT_VP6D),
 212         EMPTY_FMT_TBL(FMT_VP7D),
 213         EMPTY_FMT_TBL(FMT_VP8D),
 214         SETUP_FMT_TBL(FMT_VP9D  , rkv_vp9d),
 215
 216         EMPTY_FMT_TBL(FMT_PP),
 217
 218         EMPTY_FMT_TBL(FMT_VC1D),
 219         EMPTY_FMT_TBL(FMT_AVSD),
 220
 221         EMPTY_FMT_TBL(FMT_JPEGE),
 222         EMPTY_FMT_TBL(FMT_H264E),
 223         EMPTY_FMT_TBL(FMT_VP8E),
 224 };
 225
 226 #endif