2 drivers/video/rockchip/transmitter/rk616_mipi_dsi.h
4 #include <linux/rockchip/grf.h>
5 #ifndef RK616_MIPI_DSI_H
6 #define RK616_MIPI_DSI_H
8 #define MIPI_DSI_PHY_OFFSET 0x0C00
9 #define MIPI_DSI_PHY_SIZE 0x34c
10 #define MIPI_DSI_HOST_OFFSET 0x1000
12 #ifdef DWC_DSI_VERSION_0x3131302A
13 #define MIPI_DSI_HOST_SIZE 0x74
15 #define MIPI_DSI_HOST_SIZE 0xcc
18 //function bits definition register addr | bits | offest
19 #define REG_ADDR(a) ((a) << 16)
20 #define REG_BITS(a) ((a) << 8)
21 #define BITS_OFFSET(a) (a)
22 #define DSI_HOST_BITS(addr, bits, bit_offset) (REG_ADDR((addr)+MIPI_DSI_HOST_OFFSET) \
23 | REG_BITS(bits) | BITS_OFFSET(bit_offset))
24 #define DSI_DPHY_BITS(addr, bits, bit_offset) (REG_ADDR((addr)+MIPI_DSI_PHY_OFFSET) \
25 | REG_BITS(bits) | BITS_OFFSET(bit_offset))
27 #ifdef DWC_DSI_VERSION_0x3131302A
29 #define VERSION DSI_HOST_BITS(0x00, 32, 0)
30 #define GEN_HDR DSI_HOST_BITS(0x34, 32, 0)
31 #define GEN_PLD_DATA DSI_HOST_BITS(0x38, 32, 0)
32 #define ERROR_ST0 DSI_HOST_BITS(0x44, 21, 0)
33 #define ERROR_ST1 DSI_HOST_BITS(0x48, 18, 0)
34 #define ERROR_MSK0 DSI_HOST_BITS(0x4C, 21, 0)
35 #define ERROR_MSK1 DSI_HOST_BITS(0x50, 18, 0)
37 #define shutdownz DSI_HOST_BITS(0x04, 1, 0)
38 #define en18_loosely DSI_HOST_BITS(0x0c, 1, 10)
39 #define colorm_active_low DSI_HOST_BITS(0x0c, 1, 9)
40 #define shutd_active_low DSI_HOST_BITS(0x0c, 1, 8)
41 #define hsync_active_low DSI_HOST_BITS(0x0c, 1, 7)
42 #define vsync_active_low DSI_HOST_BITS(0x0c, 1, 6)
43 #define dataen_active_low DSI_HOST_BITS(0x0c, 1, 5)
44 #define dpi_color_coding DSI_HOST_BITS(0x0c, 3, 2)
45 #define dpi_vcid DSI_HOST_BITS(0x0c, 1, 0)
46 #define vid_hline_time DSI_HOST_BITS(0x28, 14, 18)
47 #define vid_hbp_time DSI_HOST_BITS(0x28, 9, 9)
48 #define vid_hsa_time DSI_HOST_BITS(0x28, 9, 0)
49 #define vid_active_lines DSI_HOST_BITS(0x2c, 11, 16)
50 #define vid_vfp_lines DSI_HOST_BITS(0x2c, 6, 10)
51 #define vid_vbp_lines DSI_HOST_BITS(0x2c, 6, 4)
52 #define vid_vsa_lines DSI_HOST_BITS(0x2c, 4, 0)
53 #define TO_CLK_DIVISION DSI_HOST_BITS(0x08, 8, 8)
54 #define TX_ESC_CLK_DIVISION DSI_HOST_BITS(0x08, 8, 0)
55 #define gen_vid_rx DSI_HOST_BITS(0x18, 2, 5)
56 #define crc_rx_en DSI_HOST_BITS(0x18, 1, 4)
57 #define ecc_rx_en DSI_HOST_BITS(0x18, 1, 3)
58 #define bta_en DSI_HOST_BITS(0x18, 1, 2)
59 #define eotp_rx_en DSI_HOST_BITS(0x18, 1, 1)
60 #define eotp_tx_en DSI_HOST_BITS(0x18, 1, 0)
61 #define lp_cmd_en DSI_HOST_BITS(0x1c, 1, 12)
62 #define frame_bta_ack_en DSI_HOST_BITS(0x1c, 1, 11)
63 #define en_null_pkt DSI_HOST_BITS(0x1c, 1, 10)
64 #define en_multi_pkt DSI_HOST_BITS(0x1c, 1, 9)
65 #define lp_hfp_en DSI_HOST_BITS(0x1c, 1, 8)
66 #define lp_hbp_en DSI_HOST_BITS(0x1c, 1, 7)
67 #define lp_vact_en DSI_HOST_BITS(0x1c, 1, 6)
68 #define lp_vfp_en DSI_HOST_BITS(0x1c, 1, 5)
69 #define lp_vbp_en DSI_HOST_BITS(0x1c, 1, 4)
70 #define lp_vsa_en DSI_HOST_BITS(0x1c, 1, 3)
71 #define vid_mode_type DSI_HOST_BITS(0x1c, 2, 1)
72 #define en_video_mode DSI_HOST_BITS(0x1c, 1, 0)
73 #define null_pkt_size DSI_HOST_BITS(0x20, 10, 21)
74 #define num_chunks DSI_HOST_BITS(0x20, 10, 11)
75 #define vid_pkt_size DSI_HOST_BITS(0x20, 11, 0)
76 #define tear_fx_en DSI_HOST_BITS(0x24, 1, 14)
77 #define ack_rqst_en DSI_HOST_BITS(0x24, 1, 13)
78 #define dcs_lw_tx DSI_HOST_BITS(0x24, 1, 12)
79 #define gen_lw_tx DSI_HOST_BITS(0x24, 1, 11)
80 #define max_rd_pkt_size DSI_HOST_BITS(0x24, 1, 10)
81 #define dcs_sr_0p_tx DSI_HOST_BITS(0x24, 1, 9)
82 #define dcs_sw_1p_tx DSI_HOST_BITS(0x24, 1, 8)
83 #define dcs_sw_0p_tx DSI_HOST_BITS(0x24, 1, 7)
84 #define gen_sr_2p_tx DSI_HOST_BITS(0x24, 1, 6)
85 #define gen_sr_1p_tx DSI_HOST_BITS(0x24, 1, 5)
86 #define gen_sr_0p_tx DSI_HOST_BITS(0x24, 1, 4)
87 #define gen_sw_2p_tx DSI_HOST_BITS(0x24, 1, 3)
88 #define gen_sw_1p_tx DSI_HOST_BITS(0x24, 1, 2)
89 #define gen_sw_0p_tx DSI_HOST_BITS(0x24, 1, 1)
90 #define en_cmd_mode DSI_HOST_BITS(0x24, 1, 0)
91 #define phy_hs2lp_time DSI_HOST_BITS(0x30, 8, 24)
92 #define phy_lp2hs_time DSI_HOST_BITS(0x30, 8, 16)
93 #define max_rd_time DSI_HOST_BITS(0x30, 15, 0)
94 #define lprx_to_cnt DSI_HOST_BITS(0x40, 16, 16)
95 #define hstx_to_cnt DSI_HOST_BITS(0x40, 16, 0)
96 #define phy_enableclk DSI_HOST_BITS(0x54, 1, 2)
97 //#define phy_rstz DSI_HOST_BITS(0x54, 1, 1)
98 //#define phy_shutdownz DSI_HOST_BITS(0x54, 1, 0)
100 #define phy_stop_wait_time DSI_HOST_BITS(0x58, 8, 2)
101 #define n_lanes DSI_HOST_BITS(0x58, 2, 0)
102 #define phy_tx_triggers DSI_HOST_BITS(0x5c, 4, 5)
103 #define phy_txexitulpslan DSI_HOST_BITS(0x5c, 1, 4)
104 #define phy_txrequlpslan DSI_HOST_BITS(0x5c, 1, 3)
105 #define phy_txexitulpsclk DSI_HOST_BITS(0x5c, 1, 2)
106 #define phy_txrequlpsclk DSI_HOST_BITS(0x5c, 1, 1)
107 #define phy_txrequestclkhs DSI_HOST_BITS(0x5c, 1, 0)
108 #define phy_testclk DSI_HOST_BITS(0x64, 1, 1)
109 #define phy_testclr DSI_HOST_BITS(0x64, 1, 0)
110 #define phy_testen DSI_HOST_BITS(0x68, 1, 16)
111 #define phy_testdout DSI_HOST_BITS(0x68, 8, 8)
112 #define phy_testdin DSI_HOST_BITS(0x68, 8, 0)
113 #define outvact_lpcmd_time DSI_HOST_BITS(0x70, 8, 8)
114 #define invact_lpcmd_time DSI_HOST_BITS(0x70, 8, 0)
115 #define gen_rd_cmd_busy DSI_HOST_BITS(0x3c, 1, 6)
116 #define gen_pld_r_full DSI_HOST_BITS(0x3c, 1, 5)
117 #define gen_pld_r_empty DSI_HOST_BITS(0x3c, 1, 4)
118 #define gen_pld_w_full DSI_HOST_BITS(0x3c, 1, 3) //800byte write GEN_PLD_DATA
119 #define gen_pld_w_empty DSI_HOST_BITS(0x3c, 1, 2)
120 #define gen_cmd_full DSI_HOST_BITS(0x3c, 1, 1) //20 write GEN_HDR
121 #define gen_cmd_empty DSI_HOST_BITS(0x3c, 1, 0)
122 #define phystopstateclklane DSI_HOST_BITS(0x60, 1, 2)
123 #define phylock DSI_HOST_BITS(0x60, 1, 0)
125 #else //***************************************************************//
126 //DWC_DSI_VERSION_0x3133302A
127 #define VERSION DSI_HOST_BITS(0x000, 32, 0)
128 #define shutdownz DSI_HOST_BITS(0x004, 1, 0)
129 #define TO_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 8)
130 #define TX_ESC_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 0)
131 #define dpi_vcid DSI_HOST_BITS(0x00c, 2, 0)
132 #define en18_loosely DSI_HOST_BITS(0x010, 1, 8)
133 #define dpi_color_coding DSI_HOST_BITS(0x010, 4, 0) //need modify in code
134 #define colorm_active_low DSI_HOST_BITS(0x014, 1, 4)
135 #define shutd_active_low DSI_HOST_BITS(0x014, 1, 3)
136 #define hsync_active_low DSI_HOST_BITS(0x014, 1, 2)
137 #define vsync_active_low DSI_HOST_BITS(0x014, 1, 1)
138 #define dataen_active_low DSI_HOST_BITS(0x014, 1, 0)
139 #define outvact_lpcmd_time DSI_HOST_BITS(0x018, 8, 16) //attence
140 #define invact_lpcmd_time DSI_HOST_BITS(0x018, 8, 0)
141 //#define dbi_vcid DSI_HOST_BITS(0x01c, 2, 0)
142 #define crc_rx_en DSI_HOST_BITS(0x02c, 1, 4)
143 #define ecc_rx_en DSI_HOST_BITS(0x02c, 1, 3)
144 #define bta_en DSI_HOST_BITS(0x02c, 1, 2)
145 #define eotp_rx_en DSI_HOST_BITS(0x02c, 1, 1)
146 #define eotp_tx_en DSI_HOST_BITS(0x02c, 1, 0)
147 #define gen_vid_rx DSI_HOST_BITS(0x030, 2, 0) //libing (0x030, 2, 5)-> (0x030, 2, 0)
148 #define cmd_video_mode DSI_HOST_BITS(0x034, 1, 0)
149 #define vpg_orientation DSI_HOST_BITS(0x038, 1, 24) //libing
150 #define vpg_mode DSI_HOST_BITS(0x038, 1, 20) //libing
151 #define vpg_en DSI_HOST_BITS(0x038, 1, 16) //libing
152 #define lp_cmd_en DSI_HOST_BITS(0x038, 1, 15)
153 #define frame_bta_ack_en DSI_HOST_BITS(0x038, 1, 14)
154 #define lp_hfp_en DSI_HOST_BITS(0x038, 1, 13)
155 #define lp_hbp_en DSI_HOST_BITS(0x038, 1, 12)
156 #define lp_vact_en DSI_HOST_BITS(0x038, 1, 11)
157 #define lp_vfp_en DSI_HOST_BITS(0x038, 1, 10)
158 #define lp_vbp_en DSI_HOST_BITS(0x038, 1, 9)
159 #define lp_vsa_en DSI_HOST_BITS(0x038, 1, 8)
160 #define vid_mode_type DSI_HOST_BITS(0x038, 2, 0)
161 #define vid_pkt_size DSI_HOST_BITS(0x03c, 14, 0)
162 #define num_chunks DSI_HOST_BITS(0x040, 13, 0)
163 #define null_pkt_size DSI_HOST_BITS(0x044, 13, 0)
164 #define vid_hsa_time DSI_HOST_BITS(0x048, 12, 0)
165 #define vid_hbp_time DSI_HOST_BITS(0x04c, 12, 0)
166 #define vid_hline_time DSI_HOST_BITS(0x050, 15, 0)
167 #define vid_vsa_lines DSI_HOST_BITS(0x054, 10, 0)
168 #define vid_vbp_lines DSI_HOST_BITS(0x058, 10, 0)
169 #define vid_vfp_lines DSI_HOST_BITS(0x05c, 10, 0)
170 #define vid_active_lines DSI_HOST_BITS(0x060, 14, 0)
171 #define max_rd_pkt_size DSI_HOST_BITS(0x068, 1, 24)
172 #define dcs_lw_tx DSI_HOST_BITS(0x068, 1, 19)
173 #define dcs_sr_0p_tx DSI_HOST_BITS(0x068, 1, 18)
174 #define dcs_sw_1p_tx DSI_HOST_BITS(0x068, 1, 17)
175 #define dcs_sw_0p_tx DSI_HOST_BITS(0x068, 1, 16)
176 #define gen_lw_tx DSI_HOST_BITS(0x068, 1, 14)
177 #define gen_sr_2p_tx DSI_HOST_BITS(0x068, 1, 13)
178 #define gen_sr_1p_tx DSI_HOST_BITS(0x068, 1, 12)
179 #define gen_sr_0p_tx DSI_HOST_BITS(0x068, 1, 11)
180 #define gen_sw_2p_tx DSI_HOST_BITS(0x068, 1, 10)
181 #define gen_sw_1p_tx DSI_HOST_BITS(0x068, 1, 9)
182 #define gen_sw_0p_tx DSI_HOST_BITS(0x068, 1, 8)
183 #define ack_rqst_en DSI_HOST_BITS(0x068, 1, 1)
184 #define tear_fx_en DSI_HOST_BITS(0x068, 1, 0)
185 #define GEN_HDR DSI_HOST_BITS(0x06c, 32, 0)
186 #define GEN_PLD_DATA DSI_HOST_BITS(0x070, 32, 0) //need modify
187 #define gen_rd_cmd_busy DSI_HOST_BITS(0x074, 1, 6)
188 #define gen_pld_r_full DSI_HOST_BITS(0x074, 1, 5)
189 #define gen_pld_r_empty DSI_HOST_BITS(0x074, 1, 4)
190 #define gen_pld_w_full DSI_HOST_BITS(0x074, 1, 3) //800byte write GEN_PLD_DATA
191 #define gen_pld_w_empty DSI_HOST_BITS(0x074, 1, 2)
192 #define gen_cmd_full DSI_HOST_BITS(0x074, 1, 1) //20 write GEN_HDR
193 #define gen_cmd_empty DSI_HOST_BITS(0x074, 1, 0)
194 #define hstx_to_cnt DSI_HOST_BITS(0x078, 16, 16) //need modify
195 #define lprx_to_cnt DSI_HOST_BITS(0x078, 16, 0)
196 #define hs_rd_to_cnt DSI_HOST_BITS(0x07c, 16, 0) //new(read)
197 #define lp_rd_to_cnt DSI_HOST_BITS(0x080, 16, 0) //new(read)
198 #define presp_to_mode DSI_HOST_BITS(0x084, 1, 24) //new
199 #define hs_wr_to_cnt DSI_HOST_BITS(0x084, 16, 0) //new
200 #define lp_wr_to_cnt DSI_HOST_BITS(0x088, 16, 0) //new
201 #define bta_to_cnt DSI_HOST_BITS(0x08c, 16, 0) //new
202 //#define send_3d_cfg DSI_HOST_BITS(0x090, 1, 16) //new
203 //#define right_first DSI_HOST_BITS(0x090, 1, 5) //new
204 //#define second_vsync DSI_HOST_BITS(0x090, 1, 4) //new
205 //#define format_3d DSI_HOST_BITS(0x090, 2, 2) //new
206 //#define mode_3d DSI_HOST_BITS(0x090, 2, 0) //new
207 #define auto_clklane_ctrl DSI_HOST_BITS(0x094, 1, 1) //new
208 #define phy_txrequestclkhs DSI_HOST_BITS(0x094, 1, 0)
209 #define phy_hs2lp_time_clk_lane DSI_HOST_BITS(0x098, 10, 16) //libing
210 #define phy_hs2hs_time_clk_lane DSI_HOST_BITS(0x098, 10, 0) //libing
211 #define phy_hs2lp_time DSI_HOST_BITS(0x09c, 8, 24)
212 #define phy_lp2hs_time DSI_HOST_BITS(0x09c, 8, 16)
213 #define max_rd_time DSI_HOST_BITS(0x09c, 15, 0)
214 #define phy_forcepll DSI_HOST_BITS(0x0a0, 1, 3) //new Dependency: DSI_HOST_FPGA = 0. Otherwise, this bit is reserved.
215 #define phy_enableclk DSI_HOST_BITS(0x0a0, 1, 2)
216 #define phy_rstz DSI_HOST_BITS(0x0a0, 1, 1) //libing
217 #define phy_shutdownz DSI_HOST_BITS(0x0a0, 1, 0) //libing
218 #define phy_stop_wait_time DSI_HOST_BITS(0x0a4, 8, 8)
219 #define n_lanes DSI_HOST_BITS(0x0a4, 2, 0)
220 #define phy_txexitulpslan DSI_HOST_BITS(0x0a8, 1, 3)
221 #define phy_txrequlpslan DSI_HOST_BITS(0x0a8, 1, 2)
222 #define phy_txexitulpsclk DSI_HOST_BITS(0x0a8, 1, 1)
223 #define phy_txrequlpsclk DSI_HOST_BITS(0x0a8, 1, 0)
224 #define phy_tx_triggers DSI_HOST_BITS(0x0ac, 4, 0)
226 #define phystopstateclklane DSI_HOST_BITS(0x0b0, 1, 2)
227 #define phylock DSI_HOST_BITS(0x0b0, 1, 0)
228 #define phy_testclk DSI_HOST_BITS(0x0b4, 1, 1)
229 #define phy_testclr DSI_HOST_BITS(0x0b4, 1, 0)
230 #define phy_testen DSI_HOST_BITS(0x0b8, 1, 16)
231 #define phy_testdout DSI_HOST_BITS(0x0b8, 8, 8)
232 #define phy_testdin DSI_HOST_BITS(0x0b8, 8, 0)
234 #define PHY_TEST_CTRL1 DSI_HOST_BITS(0x0b8, 17, 0)
235 #define PHY_TEST_CTRL0 DSI_HOST_BITS(0x0b4, 2, 0)
237 #define INT_ST0 DSI_HOST_BITS(0x0bc, 21, 0)
238 #define INT_ST1 DSI_HOST_BITS(0x0c0, 18, 0)
239 #define INT_MKS0 DSI_HOST_BITS(0x0c4, 21, 0)
240 #define INT_MKS1 DSI_HOST_BITS(0x0c8, 18, 0) //libing
241 #define INT_FORCE0 DSI_HOST_BITS(0x0d8, 21, 0) //libing
242 #define INT_FORCE1 DSI_HOST_BITS(0x0dc, 18, 0) //libing
244 #define code_hs_rx_clock 0x34
245 #define code_hs_rx_lane0 0x44
246 #define code_hs_rx_lane1 0x54
247 #define code_hs_rx_lane2 0x84
248 #define code_hs_rx_lane3 0x94
250 #define code_pll_input_div_rat 0x17
251 #define code_pll_loop_div_rat 0x18
252 #define code_pll_input_loop_div_rat 0x19
254 #define code_hstxdatalanerequsetstatetime 0x70
255 #define code_hstxdatalanepreparestatetime 0x71
256 #define code_hstxdatalanehszerostatetime 0x72
262 //#define en_null_pkt DSI_HOST_BITS(0x1c, 1, 13) //delete
263 //#define en_multi_pkt DSI_HOST_BITS(0x1c, 1, 13) //delete
264 #endif /* end of DWC_DSI_VERSION_0x3131302A */
268 //MIPI DSI DPHY REGISTERS
269 #define DPHY_REGISTER0 DSI_DPHY_BITS(0x00, 32, 0)
270 #define DPHY_REGISTER1 DSI_DPHY_BITS(0x04, 32, 0)
271 #define DPHY_REGISTER3 DSI_DPHY_BITS(0x0c, 32, 0)
272 #define DPHY_REGISTER4 DSI_DPHY_BITS(0x10, 32, 0)
273 #define DPHY_REGISTER20 DSI_DPHY_BITS(0X80, 32, 0)
275 #define lane_en_ck DSI_DPHY_BITS(0x00, 1, 6)
276 #define lane_en_3 DSI_DPHY_BITS(0x00, 1, 5)
277 #define lane_en_2 DSI_DPHY_BITS(0x00, 1, 4)
278 #define lane_en_1 DSI_DPHY_BITS(0x00, 1, 3)
279 #define lane_en_0 DSI_DPHY_BITS(0x00, 1, 2)
281 #define reg_da_ppfc DSI_DPHY_BITS(0x04, 1, 4)
282 #define reg_da_syncrst DSI_DPHY_BITS(0x04, 1, 2)
283 #define reg_da_ldopd DSI_DPHY_BITS(0x04, 1, 1)
284 #define reg_da_pllpd DSI_DPHY_BITS(0x04, 1, 0)
286 #define reg_fbdiv_8 DSI_DPHY_BITS(0x0c, 1, 5)
287 #define reg_prediv DSI_DPHY_BITS(0x0c, 5, 0)
288 #define reg_fbdiv DSI_DPHY_BITS(0x10, 8, 0)
290 #define reg_dig_rstn DSI_DPHY_BITS(0X80, 1, 0)
292 #define DPHY_CLOCK_OFFSET REG_ADDR(0X0100)
293 #define DPHY_LANE0_OFFSET REG_ADDR(0X0180)
294 #define DPHY_LANE1_OFFSET REG_ADDR(0X0200)
295 #define DPHY_LANE2_OFFSET REG_ADDR(0X0280)
296 #define DPHY_LANE3_OFFSET REG_ADDR(0X0300)
298 #define reg_ths_settle DSI_DPHY_BITS(0x0000, 4, 0)
299 #define reg_hs_tlpx DSI_DPHY_BITS(0x0014, 6, 0)
300 #define reg_hs_ths_prepare DSI_DPHY_BITS(0x0018, 7, 0)
301 #define reg_hs_the_zero DSI_DPHY_BITS(0x001c, 6, 0)
302 #define reg_hs_ths_trail DSI_DPHY_BITS(0x0020, 7, 0)
303 #define reg_hs_ths_exit DSI_DPHY_BITS(0x0024, 5, 0)
304 #define reg_hs_tclk_post DSI_DPHY_BITS(0x0028, 4, 0)
305 #define reserved DSI_DPHY_BITS(0x002c, 1, 0)
306 #define reg_hs_twakup_h DSI_DPHY_BITS(0x0030, 2, 0)
307 #define reg_hs_twakup_l DSI_DPHY_BITS(0x0034, 8, 0)
308 #define reg_hs_tclk_pre DSI_DPHY_BITS(0x0038, 4, 0)
309 #define reg_hs_tta_go DSI_DPHY_BITS(0x0040, 6, 0)
310 #define reg_hs_tta_sure DSI_DPHY_BITS(0x0044, 6, 0)
311 #define reg_hs_tta_wait DSI_DPHY_BITS(0x0048, 6, 0)
314 #ifdef DWC_DSI_VERSION_0x3131302A
316 #define DSI_MISC_BITS(addr, bits, bit_offset) (REG_ADDR(addr) \
317 | REG_BITS(bits) | BITS_OFFSET(bit_offset))
319 #define CRU_CRU_CLKSEL1_CON (0x005c)
320 #define CRU_CFG_MISC_CON (0x009c)
322 #define cfg_mipiclk_gaten DSI_MISC_BITS(CRU_CRU_CLKSEL1_CON, 1, 10)
324 #define mipi_int DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 19)
325 #define mipi_edpihalt DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 16)
326 #define pin_forcetxstopmode_3 DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 11)
327 #define pin_forcetxstopmode_2 DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 10)
328 #define pin_forcetxstopmode_1 DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 9)
329 #define pin_forcetxstopmode_0 DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 8)
330 #define pin_forcerxmode_0 DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 7)
331 #define pin_turndisable_0 DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 6)
332 #define dpicolom DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 2)
333 #define dpishutdn DSI_MISC_BITS(CRU_CFG_MISC_CON, 1, 1)
338 //#define mipi_edpihalt
339 #define pin_forcetxstopmode_3
340 #define pin_forcetxstopmode_2
341 #define pin_forcetxstopmode_1
342 #define pin_forcetxstopmode_0
343 #define pin_forcerxmode_0
344 #define pin_turndisable_0
351 //global operation timing parameter
359 //default time unit is ns
360 //Unit Interval, equal to the duration of any HS state on the Clock Lane
362 u32 CLK_MISS; //min:no max:60
363 u32 CLK_POST; //min:60 ns + 52*UI max:no
364 u32 CLK_PRE; //min:8*UI max:no
365 u32 CLK_PREPARE; //min:38 max:95
366 u32 CLK_SETTLE; //min:95 max:300
367 u32 CLK_TERM_EN; //min:Time for Dn to reach VTERM-EN max:38
368 u32 CLK_TRAIL; //min:60 max:no
369 u32 CLK_ZERO; //min:300 - CLK_PREPARE max:no
370 u32 D_TERM_EN; //min:Time for Dn to reach VTERM-EN max:35 ns + 4*UI
371 u32 EOT; //min:no max:105 ns + n*12*UI
372 u32 HS_EXIT; //min:100 max:no
373 u32 HS_PREPARE; //min:40 ns + 4*UI max:85 ns + 6*UI
374 u32 HS_ZERO; //min:145 ns + 10*UI - HS_PREPARE max:no
375 u32 HS_SETTLE; //min:85 ns + 6*UI max:145 ns + 10*UI
376 u32 HS_SKIP; //min:40 max:55 ns + 4*UI
377 u32 HS_TRAIL; //min: max( n*8*UI, 60 ns + n*4*UI ) max:no
378 u32 NIT; //min:100us max:no
379 u32 LPX; //min:50 max:no
380 u32 TA_GET; //min:5*TLPX
381 u32 TA_GO; //min:4*TLPX
382 u32 TA_SURE; //min:TLPX max:2*TLPX
383 u32 WAKEUP; //min:1ms max:no
389 u32 ref_clk; //input_clk
390 u32 ddr_clk; //data bit clk
391 u32 txbyte_clk; //1/8 of ddr_clk
397 u32 Ttxbyte_clk; //ps
402 #ifdef CONFIG_MIPI_DSI_LINUX
404 unsigned long iobase;
405 void __iomem *membase;
421 #ifdef CONFIG_MIPI_DSI_LINUX
422 unsigned long iobase;
423 void __iomem *membase;
432 struct dsi_host host;
433 struct mipi_dsi_ops ops;
434 struct mipi_dsi_screen screen;
435 #ifdef CONFIG_MIPI_DSI_LINUX
436 struct clk *dsi_pclk;
438 #ifdef CONFIG_HAS_EARLYSUSPEND
439 struct early_suspend early_suspend;
442 struct dentry *debugfs_dir;
443 struct platform_device *pdev;
446 int rk_mipi_get_dsi_clk(void);
447 int rk_mipi_get_dsi_num(void);
448 int rk_mipi_get_dsi_lane(void);
450 extern int rk616_mipi_dsi_ft_init(void);
451 int rk_mipi_dsi_init_lite(struct dsi *dsi);
452 #endif /* end of RK616_MIPI_DSI_H */