drivers/video/rockchip/transmitter/rk616_mipi_dsi.c

   1 /*
   2  * Copyright (C) 2013 ROCKCHIP, Inc.
   3  * drivers/video/display/transmitter/rk616_mipi_dsi.c
   4  * author: hhb@rock-chips.com
   5  * create date: 2013-07-17
   6  * debug sys/kernel/debug/rk616/mipi
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 //config
  18 #define MIPI_DSI_REGISTER_IO    0
  19 #define CONFIG_MIPI_DSI_LINUX   0
  20 //#define CONFIG_MIPI_DSI_FT    1
  21 //#define CONFIG_MFD_RK616      1
  22 //#define CONFIG_ARCH_RK319X    1
  23 #define CONFIG_ARCH_RK3288    1
  24
  25 #ifdef CONFIG_MIPI_DSI_LINUX
  26 #if defined(CONFIG_MFD_RK616)
  27 #define DWC_DSI_VERSION         0x3131302A
  28 #define DWC_DSI_VERSION_0x3131302A 1
  29 #elif defined(CONFIG_ARCH_RK319X)
  30 #define DWC_DSI_VERSION         0x3132312A
  31 #define DWC_DSI_VERSION_0x3132312A 1
  32 #elif defined(CONFIG_ARCH_RK3288)
  33 #define DWC_DSI_VERSION         0x3133302A
  34 #define DWC_DSI_VERSION_0x3133302A 1
  35 #else
  36 #define DWC_DSI_VERSION -1
  37 #endif  /* CONFIG_MFD_RK616 */
  38 #else
  39 #define DWC_DSI_VERSION         0x3131302A
  40 #endif  /* end of CONFIG_MIPI_DSI_LINUX*/
  41
  42
  43 #ifdef CONFIG_MIPI_DSI_LINUX
  44 #include <linux/kernel.h>
  45 #include <linux/init.h>
  46 #include <linux/platform_device.h>
  47 #include <linux/slab.h>
  48 #include <linux/mfd/rk616.h>
  49 #include <linux/rk_fb.h>
  50 #include <linux/rk_screen.h>
  51 #include <linux/delay.h>
  52 #include <linux/clk.h>
  53 #include <linux/interrupt.h>
  54 #include <asm/div64.h>
  55
  56 #include <linux/fs.h>
  57 #include <linux/debugfs.h>
  58 #include <linux/seq_file.h>
  59 #include <linux/regulator/machine.h>
  60
  61 #else
  62 #include "ft_lcd.h"
  63 #endif
  64 #include <linux/dma-mapping.h>
  65 #include "mipi_dsi.h"
  66 #include "rk616_mipi_dsi.h"
  67 #include <linux/rockchip/iomap.h>
  68
  69
  70
  71 #if 1
  72 #define MIPI_DBG(x...)  printk(KERN_INFO x)
  73 #else
  74 #ifdef CONFIG_MIPI_DSI_FT
  75 #define MIPI_DBG(...)    \
  76     do\
  77     {\
  78         printf(__VA_ARGS__);\
  79         printf("\n");\
  80     }while(0);
  81 #else
  82 #define MIPI_DBG(x...)
  83 #endif    /* end of CONFIG_MIPI_DSI_FT */
  84 #endif
  85
  86 #ifdef CONFIG_MIPI_DSI_LINUX
  87 #define MIPI_TRACE(x...)        printk(KERN_INFO x)
  88 #else
  89 #define MIPI_TRACE(...)    \
  90     do\
  91     {\
  92         printf(__VA_ARGS__);\
  93         printf("\n");\
  94     }while(0);
  95
  96 #endif
  97
  98 /*
  99 *                        Driver Version Note
 100 *
 101 *v1.0 : this driver is mipi dsi driver of rockchip;
 102 *v1.1 : add FT code
 103 *v1.2 : add rk_mipi_dsi_init_lite() for mclk variation
 104 *v1.3 : add clk_notifier function for mclk variation
 105 *v1.4 : add register temp to reduce the time driver resume takes when
 106                 use I2C.
 107 *v1.5 : change early suspend level (BLANK_SCREEN + 1)
 108 *v1.6 : add dsi_rk616->resume to reduce the time driver resume takes
 109 *v2.0 : add mipi dsi support for rk319x
 110 *v2.1 : add inset and unplug the hdmi, mipi's lcd will be reset.
 111 *v2.2 : fix bug of V1.4 register temp, dpicolom
 112 *v3.0 : support kernel 3.10 and device tree
 113 */
 114 #define RK_MIPI_DSI_VERSION_AND_TIME  "rockchip mipi_dsi v3.0 2014-03-06"
 115
 116 static struct dsi *dsi0;
 117 static struct dsi *dsi1;
 118
 119
 120 #ifdef CONFIG_MFD_RK616
 121 static struct mfd_rk616 *dsi_rk616;
 122 static struct rk29fb_screen *g_rk29fd_screen = NULL;
 123 #endif
 124
 125 #ifdef CONFIG_MIPI_DSI_FT
 126 #define udelay          DRVDelayUs
 127 #define msleep          DelayMs_nops
 128 static u32 fre_to_period(u32 fre);
 129 #endif
 130 static int rk_mipi_dsi_is_active(void *arg);
 131 static int rk_mipi_dsi_enable_hs_clk(void *arg, u32 enable);
 132 static int rk_mipi_dsi_enable_video_mode(void *arg, u32 enable);
 133 static int rk_mipi_dsi_enable_command_mode(void *arg, u32 enable);
 134 static int rk_mipi_dsi_send_dcs_packet(void *arg, unsigned char regs[], u32 n);
 135 static int rk_mipi_dsi_is_enable(void *arg, u32 enable);
 136 int rk_mipi_screen_standby(u8 enable);
 137
 138 #ifdef CONFIG_MFD_RK616
 139 static u32 *host_mem = NULL;
 140 static u32 *phy_mem = NULL;
 141 #endif
 142
 143 static int dsi_read_reg(struct dsi *dsi, u16 reg, u32 *pval)
 144 {
 145 #ifdef CONFIG_MIPI_DSI_LINUX
 146
 147 #if defined(CONFIG_MFD_RK616)
 148         return dsi_rk616->read_dev(dsi_rk616, reg, pval);
 149 #elif defined(CONFIG_ARCH_RK319X)
 150         if(reg >= MIPI_DSI_HOST_OFFSET)
 151                 *pval = __raw_readl(dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
 152         else if(reg >= MIPI_DSI_PHY_OFFSET)
 153                 *pval = __raw_readl(dsi->phy.membase + (reg - MIPI_DSI_PHY_OFFSET));
 154         return 0;
 155 #elif defined(CONFIG_ARCH_RK3288)
 156         *pval = __raw_readl(dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
 157         return 0;
 158 #endif  /* CONFIG_MFD_RK616 */
 159
 160 #else
 161
 162 #ifdef CONFIG_MIPI_DSI_FT
 163         return JETTA_ReadControlRegister(reg, pval);
 164 #endif  /* CONFIG_MIPI_DSI_FT */
 165
 166 #endif  /* end of CONFIG_MIPI_DSI_LINUX */
 167 }
 168
 169
 170 static int dsi_write_reg(struct dsi *dsi, u16 reg, u32 *pval)
 171 {
 172 #ifdef CONFIG_MIPI_DSI_LINUX
 173
 174 #if defined(CONFIG_MFD_RK616)
 175         return dsi_rk616->write_dev(dsi_rk616, reg, pval);
 176 #elif defined(CONFIG_ARCH_RK319X)
 177         if(reg >= MIPI_DSI_HOST_OFFSET)
 178                 __raw_writel(*pval, dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
 179         else if(reg >= MIPI_DSI_PHY_OFFSET)
 180                 __raw_writel(*pval, dsi->phy.membase + (reg - MIPI_DSI_PHY_OFFSET));
 181         return 0;
 182 #elif defined(CONFIG_ARCH_RK3288)
 183         __raw_writel(*pval, dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
 184         return 0;
 185 #endif  /* CONFIG_MFD_RK616 */
 186
 187 #else
 188
 189 #ifdef CONFIG_MIPI_DSI_FT
 190         return JETTA_WriteControlRegister(reg, *pval);
 191 #endif  /* CONFIG_MIPI_DSI_FT */
 192
 193 #endif  /* end of CONFIG_MIPI_DSI_LINUX */
 194 }
 195
 196 #ifdef CONFIG_MFD_RK616
 197 static int dsi_write_reg_bulk(u16 reg, u32 count, u32 *pval)
 198 {
 199         return dsi_rk616->write_bulk(dsi_rk616, reg, count, pval);
 200 }
 201 #endif
 202
 203 static int dsi_get_bits(struct dsi *dsi, u32 reg)
 204 {
 205         u32 val = 0;
 206         u32 bits = (reg >> 8) & 0xff;
 207         u16 reg_addr = (reg >> 16) & 0xffff;
 208         u8 offset = reg & 0xff;
 209         if(bits < 32)
 210                 bits = (1 << bits) - 1;
 211         else
 212                 bits = 0xffffffff;
 213         dsi_read_reg(dsi, reg_addr, &val);
 214         val >>= offset;
 215         val &= bits;
 216         return val;
 217 }
 218
 219 static int dsi_set_bits(struct dsi *dsi, u32 data, u32 reg)
 220 {
 221         u32 val = 0;
 222         u32 bits = (reg >> 8) & 0xff;
 223         u16 reg_addr = (reg >> 16) & 0xffff;
 224         u8 offset = reg & 0xff;
 225         if(bits < 32)
 226                 bits = (1 << bits) - 1;
 227         else
 228                 bits = 0xffffffff;
 229
 230         if(bits != 0xffffffff) {
 231 #ifdef CONFIG_MFD_RK616
 232                 if(reg_addr >= MIPI_DSI_HOST_OFFSET) {
 233                         val = host_mem[(reg_addr - MIPI_DSI_HOST_OFFSET)>>2];
 234                 } else if(reg_addr >= MIPI_DSI_PHY_OFFSET) {
 235                         val = phy_mem[(reg_addr - MIPI_DSI_PHY_OFFSET)>>2];
 236                 } else
 237                         dsi_read_reg(dsi, reg_addr, &val);
 238                 if(val == 0xaaaaaaaa)
 239                         dsi_read_reg(dsi, reg_addr, &val);
 240 #else
 241                 dsi_read_reg(dsi, reg_addr, &val);
 242 #endif
 243         }
 244
 245         val &= ~(bits << offset);
 246         val |= (data & bits) << offset;
 247         //printk("%s:%04x->%08x\n", __func__, reg_addr, val);
 248         dsi_write_reg(dsi, reg_addr, &val);
 249 #ifdef CONFIG_MFD_RK616
 250         if(reg_addr >= MIPI_DSI_HOST_OFFSET) {
 251                 host_mem[(reg_addr - MIPI_DSI_HOST_OFFSET)>>2] = val;
 252         } else if(reg_addr >= MIPI_DSI_PHY_OFFSET) {
 253                 phy_mem[(reg_addr - MIPI_DSI_PHY_OFFSET)>>2] = val;
 254         }
 255 #endif
 256
 257         if(data > bits) {
 258                 MIPI_TRACE("%s error reg_addr:0x%04x, offset:%d, bits:0x%04x, value:0x%04x\n",
 259                                 __func__, reg_addr, offset, bits, data);
 260         }
 261         return 0;
 262 }
 263
 264 static int dwc_phy_test_rd(struct dsi *dsi, unsigned char test_code)
 265 {
 266     int val = 0;
 267     dsi_set_bits(dsi, 1, phy_testclk);
 268     dsi_set_bits(dsi, test_code, phy_testdin);
 269     dsi_set_bits(dsi, 1, phy_testen);
 270         dsi_set_bits(dsi, 0, phy_testclk);
 271         dsi_set_bits(dsi, 0, phy_testen);;
 272
 273     dsi_set_bits(dsi, 0, phy_testen);
 274     val = dsi_get_bits(dsi,phy_testdout);
 275     dsi_set_bits(dsi, 1, phy_testclk);
 276     dsi_set_bits(dsi, 0, phy_testclk);
 277
 278     return val;
 279 }
 280
 281
 282 static int dwc_phy_test_wr(struct dsi *dsi, unsigned char test_code, unsigned char *test_data, unsigned char size)
 283 {
 284         int i = 0;
 285
 286     dsi_set_bits(dsi, 0x10000 | test_code, PHY_TEST_CTRL1);
 287     dsi_set_bits(dsi, 0x2, PHY_TEST_CTRL0);
 288     dsi_set_bits(dsi, 0x0, PHY_TEST_CTRL0);
 289
 290         for(i = 0; i < size; i++) {
 291         dsi_set_bits(dsi, test_data[i], PHY_TEST_CTRL1);
 292         dsi_set_bits(dsi, 0x2, PHY_TEST_CTRL0);
 293         dsi_set_bits(dsi, 0x0, PHY_TEST_CTRL0);
 294         MIPI_DBG("dwc_phy_test_wr:%08x\n", dsi_get_bits(dsi, PHY_TEST_CTRL1));
 295         }
 296         return 0;
 297 }
 298
 299 #ifdef CONFIG_MFD_RK616
 300 static int rk_mipi_recover_reg(void)
 301 {
 302         u32 reg_addr = 0, count = 0, i = 0;
 303
 304         for(i = 0x0c; i < MIPI_DSI_PHY_SIZE; i += 4) {
 305                 if(phy_mem[i>>2] != 0xaaaaaaaa) {
 306                         count++;
 307                 }
 308
 309                 if((phy_mem[i>>2] == 0xaaaaaaaa) && (phy_mem[(i-4) >> 2] != 0xaaaaaaaa)) {
 310 loop1:          reg_addr = i - (count<<2);
 311                         dsi_write_reg_bulk(reg_addr + MIPI_DSI_PHY_OFFSET, count,
 312                                                                 phy_mem+(reg_addr>>2));
 313                         //printk("%4x:%08x\n", reg_addr, phy_mem[reg_addr>>2]);
 314                         count = 0;
 315                 }
 316                 if((i == (MIPI_DSI_PHY_SIZE-4)) && (count != 0)) {
 317                         i = MIPI_DSI_PHY_SIZE;
 318                         goto loop1;
 319                 }
 320         }
 321         count = 0;
 322         for(i = 0x08; i < MIPI_DSI_HOST_SIZE; i += 4) {
 323                 if(host_mem[i>>2] != 0xaaaaaaaa) {
 324                         count++;
 325                 }
 326
 327                 if((host_mem[i>>2] == 0xaaaaaaaa) && (host_mem[(i-4) >> 2] != 0xaaaaaaaa)) {
 328 loop2:          reg_addr = i - (count<<2);
 329                         dsi_write_reg_bulk(reg_addr + MIPI_DSI_HOST_OFFSET, count,
 330                                                                 host_mem+(reg_addr>>2));
 331                         //printk("%4x:%08x\n", reg_addr, host_mem[reg_addr>>2]);
 332                         count = 0;
 333                 }
 334                 if((i == (MIPI_DSI_HOST_SIZE-4)) && (count != 0))
 335                         goto loop2;
 336         }
 337         return 0;
 338 }
 339 #endif
 340 #if defined(CONFIG_MFD_RK616) || defined(CONFIG_ARCH_RK319X)
 341 static int inno_phy_set_gotp(struct dsi *dsi, u32 offset)
 342 {
 343         u32 val = 0, temp = 0, Tlpx = 0;
 344         u32 ddr_clk = dsi->phy.ddr_clk;
 345         u32 Ttxbyte_clk = dsi->phy.Ttxbyte_clk;
 346         u32 Tsys_clk = dsi->phy.Tsys_clk;
 347         u32 Ttxclkesc = dsi->phy.Ttxclkesc;
 348
 349         switch(offset) {
 350                 case DPHY_CLOCK_OFFSET:
 351                         MIPI_DBG("******set DPHY_CLOCK_OFFSET gotp******\n");
 352                         break;
 353                 case DPHY_LANE0_OFFSET:
 354                         MIPI_DBG("******set DPHY_LANE0_OFFSET gotp******\n");
 355                         break;
 356                 case DPHY_LANE1_OFFSET:
 357                         MIPI_DBG("******set DPHY_LANE1_OFFSET gotp******\n");
 358                         break;
 359                 case DPHY_LANE2_OFFSET:
 360                         MIPI_DBG("******set DPHY_LANE2_OFFSET gotp******\n");
 361                         break;
 362                 case DPHY_LANE3_OFFSET:
 363                         MIPI_DBG("******set DPHY_LANE3_OFFSET gotp******\n");
 364                         break;
 365                 default:
 366                         break;
 367         }
 368
 369         if(ddr_clk < 110 * MHz)
 370                 val = 0;
 371         else if(ddr_clk < 150 * MHz)
 372                 val = 1;
 373         else if(ddr_clk < 200 * MHz)
 374                 val = 2;
 375         else if(ddr_clk < 250 * MHz)
 376                 val = 3;
 377         else if(ddr_clk < 300 * MHz)
 378                 val = 4;
 379         else if(ddr_clk < 400 * MHz)
 380                 val = 5;
 381         else if(ddr_clk < 500 * MHz)
 382                 val = 6;
 383         else if(ddr_clk < 600 * MHz)
 384                 val = 7;
 385         else if(ddr_clk < 700 * MHz)
 386                 val = 8;
 387         else if(ddr_clk < 800 * MHz)
 388                 val = 9;
 389         else if(ddr_clk <= 1000 * MHz)
 390                 val = 10;
 391         dsi_set_bits(dsi, val, reg_ths_settle + offset);
 392
 393         if(ddr_clk < 110 * MHz)
 394                 val = 0x20;
 395         else if(ddr_clk < 150 * MHz)
 396                 val = 0x06;
 397         else if(ddr_clk < 200 * MHz)
 398                 val = 0x18;
 399         else if(ddr_clk < 250 * MHz)
 400                 val = 0x05;
 401         else if(ddr_clk < 300 * MHz)
 402                 val = 0x51;
 403         else if(ddr_clk < 400 * MHz)
 404                 val = 0x64;
 405         else if(ddr_clk < 500 * MHz)
 406                 val = 0x59;
 407         else if(ddr_clk < 600 * MHz)
 408                 val = 0x6a;
 409         else if(ddr_clk < 700 * MHz)
 410                 val = 0x3e;
 411         else if(ddr_clk < 800 * MHz)
 412                 val = 0x21;
 413         else if(ddr_clk <= 1000 * MHz)
 414                 val = 0x09;
 415         dsi_set_bits(dsi, val, reg_hs_ths_prepare + offset);
 416
 417         if(offset != DPHY_CLOCK_OFFSET) {
 418
 419                 if(ddr_clk < 110 * MHz)
 420                         val = 2;
 421                 else if(ddr_clk < 150 * MHz)
 422                         val = 3;
 423                 else if(ddr_clk < 200 * MHz)
 424                         val = 4;
 425                 else if(ddr_clk < 250 * MHz)
 426                         val = 5;
 427                 else if(ddr_clk < 300 * MHz)
 428                         val = 6;
 429                 else if(ddr_clk < 400 * MHz)
 430                         val = 7;
 431                 else if(ddr_clk < 500 * MHz)
 432                         val = 7;
 433                 else if(ddr_clk < 600 * MHz)
 434                         val = 8;
 435                 else if(ddr_clk < 700 * MHz)
 436                         val = 8;
 437                 else if(ddr_clk < 800 * MHz)
 438                         val = 9;
 439                 else if(ddr_clk <= 1000 * MHz)
 440                         val = 9;
 441         } else {
 442
 443                 if(ddr_clk < 110 * MHz)
 444                         val = 0x16;
 445                 else if(ddr_clk < 150 * MHz)
 446                         val = 0x16;
 447                 else if(ddr_clk < 200 * MHz)
 448                         val = 0x17;
 449                 else if(ddr_clk < 250 * MHz)
 450                         val = 0x17;
 451                 else if(ddr_clk < 300 * MHz)
 452                         val = 0x18;
 453                 else if(ddr_clk < 400 * MHz)
 454                         val = 0x19;
 455                 else if(ddr_clk < 500 * MHz)
 456                         val = 0x1b;
 457                 else if(ddr_clk < 600 * MHz)
 458                         val = 0x1d;
 459                 else if(ddr_clk < 700 * MHz)
 460                         val = 0x1e;
 461                 else if(ddr_clk < 800 * MHz)
 462                         val = 0x1f;
 463                 else if(ddr_clk <= 1000 * MHz)
 464                         val = 0x20;
 465         }
 466         dsi_set_bits(dsi, val, reg_hs_the_zero + offset);
 467
 468         if(ddr_clk < 110 * MHz)
 469                 val = 0x22;
 470         else if(ddr_clk < 150 * MHz)
 471                 val = 0x45;
 472         else if(ddr_clk < 200 * MHz)
 473                 val = 0x0b;
 474         else if(ddr_clk < 250 * MHz)
 475                 val = 0x16;
 476         else if(ddr_clk < 300 * MHz)
 477                 val = 0x2c;
 478         else if(ddr_clk < 400 * MHz)
 479                 val = 0x33;
 480         else if(ddr_clk < 500 * MHz)
 481                 val = 0x4e;
 482         else if(ddr_clk < 600 * MHz)
 483                 val = 0x3a;
 484         else if(ddr_clk < 700 * MHz)
 485                 val = 0x6a;
 486         else if(ddr_clk < 800 * MHz)
 487                 val = 0x29;
 488         else if(ddr_clk <= 1000 * MHz)
 489                 val = 0x21;   //0x27
 490
 491         dsi_set_bits(dsi, val, reg_hs_ths_trail + offset);
 492         val = 120000 / Ttxbyte_clk + 1;
 493         MIPI_DBG("reg_hs_ths_exit: %d, %d\n", val, val*Ttxbyte_clk/1000);
 494         dsi_set_bits(dsi, val, reg_hs_ths_exit + offset);
 495
 496         if(offset == DPHY_CLOCK_OFFSET) {
 497                 val = (60000 + 52*dsi->phy.UI) / Ttxbyte_clk + 1;
 498                 MIPI_DBG("reg_hs_tclk_post: %d, %d\n", val, val*Ttxbyte_clk/1000);
 499                 dsi_set_bits(dsi, val, reg_hs_tclk_post + offset);
 500                 val = 10*dsi->phy.UI / Ttxbyte_clk + 1;
 501                 MIPI_DBG("reg_hs_tclk_pre: %d, %d\n", val, val*Ttxbyte_clk/1000);
 502                 dsi_set_bits(dsi, val, reg_hs_tclk_pre + offset);
 503         }
 504
 505         val = 1010000000 / Tsys_clk + 1;
 506         MIPI_DBG("reg_hs_twakup: %d, %d\n", val, val*Tsys_clk/1000);
 507         if(val > 0x3ff) {
 508                 val = 0x2ff;
 509                 MIPI_DBG("val is too large, 0x3ff is the largest\n");
 510         }
 511         temp = (val >> 8) & 0x03;
 512         val &= 0xff;
 513         dsi_set_bits(dsi, temp, reg_hs_twakup_h + offset);
 514         dsi_set_bits(dsi, val, reg_hs_twakup_l + offset);
 515
 516         if(Ttxclkesc > 50000) {
 517                 val = 2*Ttxclkesc;
 518                 MIPI_DBG("Ttxclkesc:%d\n", Ttxclkesc);
 519         }
 520         val = val / Ttxbyte_clk;
 521         Tlpx = val*Ttxbyte_clk;
 522         MIPI_DBG("reg_hs_tlpx: %d, %d\n", val, Tlpx);
 523         val -= 2;
 524         dsi_set_bits(dsi, val, reg_hs_tlpx + offset);
 525
 526         Tlpx = 2*Ttxclkesc;
 527         val = 4*Tlpx / Ttxclkesc;
 528         MIPI_DBG("reg_hs_tta_go: %d, %d\n", val, val*Ttxclkesc);
 529         dsi_set_bits(dsi, val, reg_hs_tta_go + offset);
 530         val = 3 * Tlpx / 2 / Ttxclkesc;
 531         MIPI_DBG("reg_hs_tta_sure: %d, %d\n", val, val*Ttxclkesc);
 532         dsi_set_bits(dsi, val, reg_hs_tta_sure + offset);
 533         val = 5 * Tlpx / Ttxclkesc;
 534         MIPI_DBG("reg_hs_tta_wait: %d, %d\n", val, val*Ttxclkesc);
 535         dsi_set_bits(dsi, val, reg_hs_tta_wait + offset);
 536         return 0;
 537 }
 538
 539 static int inno_set_hs_clk(struct dsi *dsi)
 540 {
 541         dsi_set_bits(dsi, dsi->phy.prediv, reg_prediv);
 542         dsi_set_bits(dsi, dsi->phy.fbdiv & 0xff, reg_fbdiv);
 543         dsi_set_bits(dsi, (dsi->phy.fbdiv >> 8) & 0x01, reg_fbdiv_8);
 544         return 0;
 545 }
 546
 547 static int inno_phy_power_up(struct dsi *dsi)
 548 {
 549         inno_set_hs_clk(dsi);
 550 #if defined(CONFIG_ARCH_RK319X)
 551         //enable ref clock
 552         clk_enable(dsi->phy.refclk);
 553         udelay(10);
 554 #endif
 555         dsi_set_bits(dsi, 0xe4, DPHY_REGISTER1);
 556         switch(dsi->host.lane) {
 557                 case 4:
 558                         dsi_set_bits(dsi, 1, lane_en_3);
 559                 case 3:
 560                         dsi_set_bits(dsi, 1, lane_en_2);
 561                 case 2:
 562                         dsi_set_bits(dsi, 1, lane_en_1);
 563                 case 1:
 564                         dsi_set_bits(dsi, 1, lane_en_0);
 565                         dsi_set_bits(dsi, 1, lane_en_ck);
 566                         break;
 567                 default:
 568                         break;
 569         }
 570
 571         dsi_set_bits(dsi, 0xe0, DPHY_REGISTER1);
 572         udelay(10);
 573
 574         dsi_set_bits(dsi, 0x1e, DPHY_REGISTER20);
 575         dsi_set_bits(dsi, 0x1f, DPHY_REGISTER20);
 576         return 0;
 577 }
 578
 579 static int inno_phy_power_down(struct dsi *dsi)
 580 {
 581         dsi_set_bits(dsi, 0x01, DPHY_REGISTER0);
 582         dsi_set_bits(dsi, 0xe3, DPHY_REGISTER1);
 583 #if defined(CONFIG_ARCH_RK319X)
 584         //disable ref clock
 585         clk_disable(dsi->phy.refclk);
 586 #endif
 587         return 0;
 588 }
 589
 590 static int inno_phy_init(struct dsi *dsi)
 591 {
 592         //DPHY init
 593         dsi_set_bits(dsi, 0x11, DSI_DPHY_BITS(0x06<<2, 32, 0));
 594         dsi_set_bits(dsi, 0x11, DSI_DPHY_BITS(0x07<<2, 32, 0));
 595         dsi_set_bits(dsi, 0xcc, DSI_DPHY_BITS(0x09<<2, 32, 0));
 596 #if 0
 597         dsi_set_bits(dsi, 0x4e, DSI_DPHY_BITS(0x08<<2, 32, 0));
 598         dsi_set_bits(dsi, 0x84, DSI_DPHY_BITS(0x0a<<2, 32, 0));
 599 #endif
 600
 601         /*reg1[4] 0: enable a function of "pll phase for serial data being captured
 602                                  inside analog part"
 603                   1: disable it
 604           we disable it here because reg5[6:4] is not compatible with the HS speed.
 605         */
 606
 607         if(dsi->phy.ddr_clk >= 800*MHz) {
 608                 dsi_set_bits(dsi, 0x30, DSI_DPHY_BITS(0x05<<2, 32, 0));
 609         } else {
 610                 dsi_set_bits(dsi, 1, reg_da_ppfc);
 611         }
 612
 613         switch(dsi->host.lane) {
 614                 case 4:
 615                         inno_phy_set_gotp(dsi, DPHY_LANE3_OFFSET);
 616                 case 3:
 617                         inno_phy_set_gotp(dsi, DPHY_LANE2_OFFSET);
 618                 case 2:
 619                         inno_phy_set_gotp(dsi, DPHY_LANE1_OFFSET);
 620                 case 1:
 621                         inno_phy_set_gotp(dsi, DPHY_LANE0_OFFSET);
 622                         inno_phy_set_gotp(dsi, DPHY_CLOCK_OFFSET);
 623                         break;
 624                 default:
 625                         break;
 626         }
 627         return 0;
 628 }
 629 #endif
 630 static int rk32_phy_power_up(struct dsi *dsi)
 631 {
 632     //enable ref clock
 633     clk_prepare_enable(dsi->phy.refclk);
 634     clk_prepare_enable(dsi->dsi_pclk);
 635     udelay(10);
 636
 637         switch(dsi->host.lane) {
 638                 case 4:
 639                         dsi_set_bits(dsi, 3, n_lanes);
 640                 case 3:
 641                         dsi_set_bits(dsi, 2, n_lanes);
 642                 case 2:
 643                         dsi_set_bits(dsi, 1, n_lanes);
 644                 case 1:
 645                         dsi_set_bits(dsi, 0, n_lanes);
 646                         break;
 647                 default:
 648                         break;
 649         }
 650     dsi_set_bits(dsi, 1, phy_shutdownz);
 651     dsi_set_bits(dsi, 1, phy_rstz);
 652     dsi_set_bits(dsi, 1, phy_enableclk);
 653     dsi_set_bits(dsi, 1, phy_forcepll);
 654     return 0;
 655 }
 656
 657 static int rk32_phy_power_down(struct dsi *dsi)
 658 {
 659     dsi_set_bits(dsi, 0, phy_shutdownz);
 660     clk_disable_unprepare(dsi->phy.refclk);
 661     clk_disable_unprepare(dsi->dsi_pclk);
 662     return 0;
 663 }
 664
 665 static int rk32_phy_init(struct dsi *dsi)
 666 {
 667     u32 val = 0;
 668     u32 ddr_clk = dsi->phy.ddr_clk;
 669     u16 prediv = dsi->phy.prediv;
 670     u16 fbdiv = dsi->phy.fbdiv;
 671     // u32 Ttxclkesc = dsi->phy.Ttxclkesc;
 672     unsigned char test_data[2] = {0};
 673
 674     if(ddr_clk < 90 * MHz)
 675         val = 0x01;
 676         else if(ddr_clk < 100 * MHz)
 677         val = 0x10;
 678         else if(ddr_clk < 110 * MHz)
 679         val = 0x20;
 680         else if(ddr_clk < 130 * MHz)
 681         val = 0x01;
 682         else if(ddr_clk < 140 * MHz)
 683         val = 0x11;
 684         else if(ddr_clk < 150 * MHz)
 685         val = 0x21;
 686         else if(ddr_clk < 170 * MHz)
 687         val = 0x02;
 688         else if(ddr_clk < 180 * MHz)
 689         val = 0x12;
 690         else if(ddr_clk < 200 * MHz)
 691         val = 0x22;
 692         else if(ddr_clk < 220 * MHz)
 693         val = 0x03;
 694         else if(ddr_clk < 240 * MHz)
 695         val = 0x13;
 696         else if(ddr_clk < 250 * MHz)
 697         val = 0x23;
 698         else if(ddr_clk < 270 * MHz)
 699         val = 0x04;
 700         else if(ddr_clk < 300 * MHz)
 701         val = 0x14;
 702         else if(ddr_clk < 330 * MHz)
 703         val = 0x05;
 704         else if(ddr_clk < 360 * MHz)
 705         val = 0x15;
 706         else if(ddr_clk < 400 * MHz)
 707         val = 0x25;
 708         else if(ddr_clk < 450 * MHz)
 709         val = 0x06;
 710         else if(ddr_clk < 500 * MHz)
 711         val = 0x16;
 712         else if(ddr_clk < 550 * MHz)
 713         val = 0x07;
 714         else if(ddr_clk < 600 * MHz)
 715         val = 0x17;
 716         else if(ddr_clk < 650 * MHz)
 717         val = 0x08;
 718         else if(ddr_clk < 700 * MHz)
 719         val = 0x18;
 720         else if(ddr_clk < 750 * MHz)
 721         val = 0x09;
 722         else if(ddr_clk < 800 * MHz)
 723         val = 0x19;
 724     else if(ddr_clk < 850 * MHz)
 725         val = 0x29;
 726     else if(ddr_clk < 900 * MHz)
 727         val = 0x39;
 728     else if(ddr_clk < 950 * MHz)
 729         val = 0x0a;
 730     else if(ddr_clk < 1000 * MHz)
 731         val = 0x1a;
 732     else if(ddr_clk < 1050 * MHz)
 733         val = 0x2a;
 734     else if(ddr_clk < 1100* MHz)
 735         val = 0x3a;
 736     else if(ddr_clk < 1150* MHz)
 737         val = 0x0b;
 738     else if(ddr_clk < 1200 * MHz)
 739         val = 0x1b;
 740     else if(ddr_clk < 1250 * MHz)
 741         val = 0x2b;
 742     else if(ddr_clk < 1300 * MHz)
 743         val = 0x3b;
 744     else if(ddr_clk < 1350 * MHz)
 745         val = 0x0c;
 746     else if(ddr_clk < 1400* MHz)
 747         val = 0x1c;
 748     else if(ddr_clk < 1450* MHz)
 749         val = 0x2c;
 750     else if(ddr_clk <= 1500* MHz)
 751         val = 0x3c;
 752
 753     //N=2,M=84
 754     test_data[0] = val << 1;
 755     dwc_phy_test_wr(dsi, code_hs_rx_lane0, test_data, 1);
 756
 757     test_data[0] = prediv- 1;
 758     dwc_phy_test_wr(dsi, code_pll_input_div_rat, test_data, 1);
 759
 760     test_data[0] = (fbdiv - 1) & 0x1f; //0x14;
 761     dwc_phy_test_wr(dsi, code_pll_loop_div_rat, test_data, 1);
 762
 763     test_data[0] = (fbdiv - 1) >> 5 | 0x80;  //0x82
 764     dwc_phy_test_wr(dsi, code_pll_loop_div_rat, test_data, 1);
 765
 766     test_data[0] = 0x30;
 767     dwc_phy_test_wr(dsi, code_pll_input_loop_div_rat, test_data, 1);
 768     mdelay(100);
 769
 770     test_data[0] = 0x00;
 771     // dwc_phy_test_wr(dsi, 0x60, test_data, 1);
 772
 773     test_data[0] = 0x81;
 774     // dwc_phy_test_wr(dsi, 0x61, test_data, 1);
 775
 776     test_data[0] = 0x0;
 777     // dwc_phy_test_wr(dsi, 0x62, test_data, 1);
 778
 779     test_data[0] = 0x80 | 15;
 780     dwc_phy_test_wr(dsi, code_hstxdatalanerequsetstatetime, test_data, 1);
 781
 782     test_data[0] = 0x80 | 85;
 783     dwc_phy_test_wr(dsi, code_hstxdatalanepreparestatetime, test_data, 1);
 784
 785     test_data[0] = 0x40 | 10;
 786     dwc_phy_test_wr(dsi, code_hstxdatalanehszerostatetime, test_data, 1);
 787
 788
 789     // test_data[0] = 0x80 | 127;
 790     // dwc_phy_test_wr(dsi, 0x71, test_data, 1);
 791
 792     // test_data[0] = 0x3;
 793     // dwc_phy_test_wr(dsi, 0x57, test_data, 1);
 794
 795     return 0;
 796 }
 797
 798 static int rk_mipi_dsi_phy_power_up(struct dsi *dsi)
 799 {
 800 #if defined(CONFIG_MFD_RK616) || defined(CONFIG_ARCH_RK319X)
 801         return inno_phy_power_up(dsi);
 802 #else
 803         return rk32_phy_power_up(dsi);
 804 #endif
 805 }
 806
 807
 808 static int rk_mipi_dsi_phy_power_down(struct dsi *dsi)
 809 {
 810 #if defined(CONFIG_MFD_RK616) || defined(CONFIG_ARCH_RK319X)
 811         return inno_phy_power_down(dsi);
 812 #else
 813         return rk32_phy_power_down(dsi);
 814 #endif
 815         return 0;
 816 }
 817
 818 static int rk_mipi_dsi_phy_init(struct dsi *dsi)
 819 {
 820 #if defined(CONFIG_MFD_RK616) || defined(CONFIG_ARCH_RK319X)
 821         return inno_phy_init(dsi);
 822 #else
 823         return rk32_phy_init(dsi);
 824 #endif
 825         return 0;
 826 }
 827
 828 static int rk_mipi_dsi_host_power_up(struct dsi *dsi)
 829 {
 830         int ret = 0;
 831         u32 val = 0;
 832
 833         //disable all interrupt
 834 #ifdef DWC_DSI_VERSION_0x3131302A
 835         dsi_set_bits(dsi, 0x1fffff, ERROR_MSK0);
 836         dsi_set_bits(dsi, 0x1ffff, ERROR_MSK1);
 837 #else
 838         dsi_set_bits(dsi, 0x1fffff, INT_MKS0);
 839         dsi_set_bits(dsi, 0x1ffff, INT_MKS1);
 840 #endif
 841
 842         rk_mipi_dsi_is_enable(dsi, 1);
 843
 844         val = 10;
 845         while(!dsi_get_bits(dsi, phylock) && val--) {
 846                 udelay(10);
 847         };
 848
 849         if(val == 0) {
 850                 ret = -1;
 851                 MIPI_TRACE("%s:phylock fail\n", __func__);
 852         }
 853
 854         val = 10;
 855         while(!dsi_get_bits(dsi, phystopstateclklane) && val--) {
 856                 udelay(10);
 857         };
 858
 859         return ret;
 860 }
 861
 862 static int rk_mipi_dsi_host_power_down(struct dsi *dsi)
 863 {
 864         rk_mipi_dsi_enable_video_mode(dsi, 0);
 865         rk_mipi_dsi_enable_hs_clk(dsi, 0);
 866         rk_mipi_dsi_is_enable(dsi, 0);
 867         return 0;
 868 }
 869
 870 static int rk_mipi_dsi_host_init(struct dsi *dsi)
 871 {
 872         u32 val = 0, bytes_px = 0;
 873         struct mipi_dsi_screen *screen = &dsi->screen;
 874         u32 decimals = dsi->phy.Ttxbyte_clk, temp = 0, i = 0;
 875         u32 m = 1, lane = dsi->host.lane, Tpclk = dsi->phy.Tpclk,
 876                         Ttxbyte_clk = dsi->phy.Ttxbyte_clk;
 877 #ifdef CONFIG_MFD_RK616
 878         val = 0x04000000;
 879         dsi_write_reg(dsi, CRU_CRU_CLKSEL1_CON, &val);
 880 #endif
 881         dsi_set_bits(dsi, dsi->host.lane - 1, n_lanes);
 882         dsi_set_bits(dsi, dsi->vid, dpi_vcid);
 883
 884         switch(screen->face) {
 885                 case OUT_P888:
 886                         dsi_set_bits(dsi, 5, dpi_color_coding);
 887                         bytes_px = 3;
 888                         break;
 889                 case OUT_D888_P666:
 890                 case OUT_P666:
 891                         dsi_set_bits(dsi, 3, dpi_color_coding);
 892                         dsi_set_bits(dsi, 1, en18_loosely);
 893                         bytes_px = 3;
 894                         break;
 895                 case OUT_P565:
 896                         dsi_set_bits(dsi, 0, dpi_color_coding);
 897                         bytes_px = 2;
 898                 default:
 899                         break;
 900         }
 901
 902         dsi_set_bits(dsi, 1, hsync_active_low);
 903         dsi_set_bits(dsi, 1, vsync_active_low);
 904
 905         dsi_set_bits(dsi, 0, dataen_active_low);
 906         dsi_set_bits(dsi, 0, colorm_active_low);
 907         dsi_set_bits(dsi, 0, shutd_active_low);
 908
 909         dsi_set_bits(dsi, dsi->host.video_mode, vid_mode_type);   //burst mode
 910         switch(dsi->host.video_mode) {
 911                 case VM_BM:
 912                     if(screen->type == SCREEN_DUAL_MIPI)
 913                             dsi_set_bits(dsi, screen->x_res / 2 + 4, vid_pkt_size);
 914                          else
 915                             dsi_set_bits(dsi, screen->x_res, vid_pkt_size);
 916                         break;
 917                 case VM_NBMWSE:
 918                 case VM_NBMWSP:
 919                         for(i = 8; i < 32; i++){
 920                                 temp = i * lane * Tpclk % Ttxbyte_clk;
 921                                 if(decimals > temp) {
 922                                         decimals = temp;
 923                                         m = i;
 924                                 }
 925                                 if(decimals == 0)
 926                                         break;
 927                         }
 928 #ifdef CONFIG_MFD_RK616
 929                         dsi_set_bits(dsi, 1, en_multi_pkt);
 930 #endif
 931                         dsi_set_bits(dsi, screen->x_res / m + 1, num_chunks);
 932                         dsi_set_bits(dsi, m, vid_pkt_size);
 933                         temp = m * lane * Tpclk / Ttxbyte_clk - m * bytes_px;
 934                         MIPI_DBG("%s:%d, %d\n", __func__, m, temp);
 935                         if(temp >= 12) {
 936 #ifdef CONFIG_MFD_RK616
 937                                 dsi_set_bits(dsi, 1, en_null_pkt);
 938 #endif
 939                                 dsi_set_bits(dsi, temp - 12, null_pkt_size);
 940                         }
 941                         break;
 942                 default:
 943                         break;
 944         }
 945
 946         //dsi_set_bits(dsi, 0, CMD_MODE_CFG << 16);
 947         if(rk_mipi_get_dsi_num() ==1){
 948                 dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->x_res + screen->left_margin +
 949                                         screen->hsync_len + screen->right_margin) \
 950                                                 / dsi->phy.Ttxbyte_clk, vid_hline_time);
 951         }
 952         else{
 953                 dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->x_res + 8 + screen->left_margin +
 954                                         screen->hsync_len + screen->right_margin) \
 955                                                 / dsi->phy.Ttxbyte_clk, vid_hline_time);
 956         }
 957                 dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->left_margin) / dsi->phy.Ttxbyte_clk,
 958                                         vid_hbp_time);
 959         dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->hsync_len) / dsi->phy.Ttxbyte_clk,
 960                                         vid_hsa_time);
 961
 962         dsi_set_bits(dsi, screen->y_res , vid_active_lines);
 963         dsi_set_bits(dsi, screen->lower_margin, vid_vfp_lines);
 964         dsi_set_bits(dsi, screen->upper_margin, vid_vbp_lines);
 965         dsi_set_bits(dsi, screen->vsync_len, vid_vsa_lines);
 966
 967         dsi->phy.txclkesc = 20 * MHz;
 968         val = dsi->phy.txbyte_clk / dsi->phy.txclkesc + 1;
 969         dsi->phy.txclkesc = dsi->phy.txbyte_clk / val;
 970         dsi_set_bits(dsi, val, TX_ESC_CLK_DIVISION);
 971
 972         dsi_set_bits(dsi, 10, TO_CLK_DIVISION);
 973     dsi_set_bits(dsi, 1000, hstx_to_cnt); //no sure
 974         dsi_set_bits(dsi, 1000, lprx_to_cnt);
 975         dsi_set_bits(dsi, 100, phy_stop_wait_time);
 976
 977         //dsi_set_bits(dsi, 0, outvact_lpcmd_time);   //byte
 978         //dsi_set_bits(dsi, 0, invact_lpcmd_time);
 979
 980         dsi_set_bits(dsi, 20, phy_hs2lp_time);
 981         dsi_set_bits(dsi, 16, phy_lp2hs_time);
 982
 983 #if defined(CONFIG_ARCH_RK3288)
 984    // dsi_set_bits(dsi, 87, phy_hs2lp_time_clk_lane); //no sure
 985   //  dsi_set_bits(dsi, 25, phy_hs2hs_time_clk_lane); //no sure
 986 #endif
 987
 988         dsi_set_bits(dsi, 10000, max_rd_time);
 989 #ifdef DWC_DSI_VERSION_0x3131302A
 990         dsi_set_bits(dsi, 1, dpicolom);
 991         dsi_set_bits(dsi, 1, dpishutdn);
 992 #endif
 993 #if 1
 994         dsi_set_bits(dsi, 1, lp_hfp_en);
 995         //dsi_set_bits(dsi, 1, lp_hbp_en); //no sure
 996         dsi_set_bits(dsi, 1, lp_vact_en);
 997         dsi_set_bits(dsi, 1, lp_vfp_en);
 998         dsi_set_bits(dsi, 1, lp_vbp_en);
 999         dsi_set_bits(dsi, 1, lp_vsa_en);
1000 #endif
1001         //dsi_set_bits(dsi, 1, frame_bta_ack_en);
1002         dsi_set_bits(dsi, 1, phy_enableclk);
1003         dsi_set_bits(dsi, 0, phy_tx_triggers);
1004         //dsi_set_bits(dsi, 1, phy_txexitulpslan);
1005         //dsi_set_bits(dsi, 1, phy_txexitulpsclk);
1006         return 0;
1007 }
1008
1009 /*
1010         mipi protocol layer definition
1011 */
1012 static int rk_mipi_dsi_init(void *arg, u32 n)
1013 {
1014         u32 decimals = 1000, i = 0, pre = 0;
1015         struct dsi *dsi = arg;
1016         struct mipi_dsi_screen *screen = &dsi->screen;
1017
1018         if(!screen)
1019                 return -1;
1020
1021         if((screen->type != SCREEN_MIPI) && (screen->type != SCREEN_DUAL_MIPI) ) {
1022                 MIPI_TRACE("only mipi dsi lcd is supported!\n");
1023                 return -1;
1024         }
1025
1026         if(((screen->type == SCREEN_DUAL_MIPI) && (rk_mipi_get_dsi_num() == 1)) ||  ((screen->type == SCREEN_MIPI) && (rk_mipi_get_dsi_num() == 2))){
1027         MIPI_TRACE("dsi number and mipi type not match!\n");
1028             return -1;
1029     }
1030
1031 #ifdef CONFIG_MIPI_DSI_FT
1032         dsi->phy.pclk = screen->pixclock;
1033         dsi->phy.ref_clk = MIPI_DSI_MCLK;
1034 #else
1035
1036         dsi->phy.Tpclk = rk_fb_get_prmry_screen_pixclock();
1037
1038         printk("dsi->phy.Tpclk=%d\n",dsi->phy.Tpclk);
1039
1040 #if defined(CONFIG_MFD_RK616)
1041         if(dsi_rk616->mclk)
1042                 dsi->phy.ref_clk = clk_get_rate(dsi_rk616->mclk);
1043 #elif defined(CONFIG_ARCH_RK319X)
1044         if(dsi->phy.refclk)
1045                 dsi->phy.ref_clk = clk_get_rate(dsi->phy.refclk) / 2;  // 1/2 of input refclk
1046 #endif   /* CONFIG_MFD_RK616 */
1047         //dsi->phy.ref_clk = 24 * MHz;
1048 #endif   /* CONFIG_MIPI_DSI_FT */
1049
1050     if(dsi->phy.refclk)
1051                 dsi->phy.ref_clk = clk_get_rate(dsi->phy.refclk) ;
1052
1053         dsi->phy.sys_clk = dsi->phy.ref_clk;
1054
1055         printk(
1056
1057 "dsi->phy.sys_clk =%d\n",dsi->phy.sys_clk );
1058
1059 #ifndef CONFIG_ARCH_RK3288
1060         if((screen->hs_tx_clk <= 80 * MHz) || (screen->hs_tx_clk >= 1000 * MHz))
1061                 dsi->phy.ddr_clk = 1000 * MHz;    //default is 1HGz
1062         else
1063                 dsi->phy.ddr_clk = screen->hs_tx_clk;
1064 #else
1065     if((screen->hs_tx_clk <= 90 * MHz) || (screen->hs_tx_clk >= 1500 * MHz))
1066         dsi->phy.ddr_clk = 1500 * MHz;    //default is 1.5HGz
1067     else
1068         dsi->phy.ddr_clk = screen->hs_tx_clk;
1069 #endif
1070
1071
1072 /*      if(n != 0) {
1073                 dsi->phy.ddr_clk = n;
1074         }
1075     */
1076
1077         decimals = dsi->phy.ref_clk;
1078         for(i = 1; i < 6; i++) {
1079                 pre = dsi->phy.ref_clk / i;
1080                 if((decimals > (dsi->phy.ddr_clk % pre)) && (dsi->phy.ddr_clk / pre < 512)) {
1081                         decimals = dsi->phy.ddr_clk % pre;
1082                         dsi->phy.prediv = i;
1083                         dsi->phy.fbdiv = dsi->phy.ddr_clk / pre;
1084                 }
1085                 if(decimals == 0)
1086                         break;
1087         }
1088
1089         MIPI_DBG("prediv:%d, fbdiv:%d,dsi->phy.ddr_clk:%d\n", dsi->phy.prediv, dsi->phy.fbdiv,dsi->phy.ref_clk / dsi->phy.prediv * dsi->phy.fbdiv);
1090
1091         dsi->phy.ddr_clk = dsi->phy.ref_clk / dsi->phy.prediv * dsi->phy.fbdiv;
1092         MIPI_DBG("dsi->phy.ddr_clk =%d\n",dsi->phy.ddr_clk);
1093         dsi->phy.txbyte_clk = dsi->phy.ddr_clk / 8;
1094
1095         dsi->phy.txclkesc = 20 * MHz;        // < 20MHz
1096         dsi->phy.txclkesc = dsi->phy.txbyte_clk / (dsi->phy.txbyte_clk / dsi->phy.txclkesc + 1);
1097
1098 #ifdef CONFIG_MIPI_DSI_FT
1099         dsi->phy.Tpclk = fre_to_period(dsi->phy.pclk);
1100         dsi->phy.Ttxclkesc = fre_to_period(dsi->phy.txclkesc);
1101         dsi->phy.Tsys_clk = fre_to_period(dsi->phy.sys_clk);
1102         dsi->phy.Tddr_clk = fre_to_period(dsi->phy.ddr_clk);
1103         dsi->phy.Ttxbyte_clk = fre_to_period(dsi->phy.txbyte_clk);
1104 #else
1105         dsi->phy.pclk = div_u64(1000000000000llu, dsi->phy.Tpclk);
1106         dsi->phy.Ttxclkesc = div_u64(1000000000000llu, dsi->phy.txclkesc);
1107         dsi->phy.Tsys_clk = div_u64(1000000000000llu, dsi->phy.sys_clk);
1108         dsi->phy.Tddr_clk = div_u64(1000000000000llu, dsi->phy.ddr_clk);
1109         dsi->phy.Ttxbyte_clk = div_u64(1000000000000llu, dsi->phy.txbyte_clk);
1110 #endif
1111
1112         dsi->phy.UI = dsi->phy.Tddr_clk;
1113         dsi->vid = 0;
1114
1115         if(screen->dsi_lane > 0 && screen->dsi_lane <= 4)
1116                 dsi->host.lane = screen->dsi_lane;
1117         else
1118                 dsi->host.lane = 4;
1119
1120         dsi->host.video_mode = VM_BM;
1121
1122         MIPI_DBG("UI:%d\n", dsi->phy.UI);
1123         MIPI_DBG("ref_clk:%d\n", dsi->phy.ref_clk);
1124         MIPI_DBG("pclk:%d, Tpclk:%d\n", dsi->phy.pclk, dsi->phy.Tpclk);
1125         MIPI_DBG("sys_clk:%d, Tsys_clk:%d\n", dsi->phy.sys_clk, dsi->phy.Tsys_clk);
1126         MIPI_DBG("ddr_clk:%d, Tddr_clk:%d\n", dsi->phy.ddr_clk, dsi->phy.Tddr_clk);
1127         MIPI_DBG("txbyte_clk:%d, Ttxbyte_clk:%d\n", dsi->phy.txbyte_clk,
1128                                 dsi->phy.Ttxbyte_clk);
1129         MIPI_DBG("txclkesc:%d, Ttxclkesc:%d\n", dsi->phy.txclkesc, dsi->phy.Ttxclkesc);
1130
1131         rk_mipi_dsi_phy_power_up(dsi);
1132         rk_mipi_dsi_host_power_up(dsi);
1133         rk_mipi_dsi_phy_init(dsi);
1134         rk_mipi_dsi_host_init(dsi);
1135
1136         /*
1137                 After the core reset, DPI waits for the first VSYNC active transition to start signal sampling, including
1138                 pixel data, and preventing image transmission in the middle of a frame.
1139         */
1140 #if 0
1141         dsi_set_bits(dsi, 0, shutdownz);
1142         rk_mipi_dsi_enable_video_mode(dsi, 1);
1143 #ifdef CONFIG_MFD_RK616
1144         rk616_display_router_cfg(dsi_rk616, g_rk29fd_screen, 0);
1145 #endif
1146         dsi_set_bits(dsi, 1, shutdownz);
1147 #endif
1148         return 0;
1149 }
1150
1151
1152 int rk_mipi_dsi_init_lite(struct dsi *dsi)
1153 {
1154         u32 decimals = 1000, i = 0, pre = 0, ref_clk = 0;
1155         struct mipi_dsi_screen *screen = &dsi->screen;
1156
1157         if(!screen)
1158                 return -1;
1159
1160         if(rk_mipi_dsi_is_active(dsi) == 0)
1161                 return -1;
1162 #if defined(CONFIG_MFD_RK616)
1163         ref_clk = clk_get_rate(dsi_rk616->mclk);
1164 #elif defined(CONFIG_ARCH_RK319X)
1165         ref_clk = clk_get_rate(dsi->phy.refclk);
1166 #endif
1167         if(dsi->phy.ref_clk == ref_clk)
1168                 return -1;
1169
1170         dsi->phy.ref_clk = ref_clk;
1171         dsi->phy.sys_clk = dsi->phy.ref_clk;
1172
1173         if((screen->hs_tx_clk <= 80 * MHz) || (screen->hs_tx_clk >= 1000 * MHz))
1174                 dsi->phy.ddr_clk = 1000 * MHz;    //default is 1HGz
1175         else
1176                 dsi->phy.ddr_clk = screen->hs_tx_clk;
1177
1178         decimals = dsi->phy.ref_clk;
1179         for(i = 1; i < 6; i++) {
1180                 pre = dsi->phy.ref_clk / i;
1181                 if((decimals > (dsi->phy.ddr_clk % pre)) && (dsi->phy.ddr_clk / pre < 512)) {
1182                         decimals = dsi->phy.ddr_clk % pre;
1183                         dsi->phy.prediv = i;
1184                         dsi->phy.fbdiv = dsi->phy.ddr_clk / pre;
1185                 }
1186                 if(decimals == 0)
1187                         break;
1188         }
1189
1190         MIPI_DBG("prediv:%d, fbdiv:%d\n", dsi->phy.prediv, dsi->phy.fbdiv);
1191         dsi->phy.ddr_clk = dsi->phy.ref_clk / dsi->phy.prediv * dsi->phy.fbdiv;
1192         dsi->phy.txbyte_clk = dsi->phy.ddr_clk / 8;
1193
1194         dsi->phy.txclkesc = 20 * MHz;        // < 20MHz
1195         dsi->phy.txclkesc = dsi->phy.txbyte_clk / (dsi->phy.txbyte_clk / dsi->phy.txclkesc + 1);
1196
1197         dsi->phy.pclk = div_u64(1000000000000llu, dsi->phy.Tpclk);
1198         dsi->phy.Ttxclkesc = div_u64(1000000000000llu, dsi->phy.txclkesc);
1199         dsi->phy.Tsys_clk = div_u64(1000000000000llu, dsi->phy.sys_clk);
1200         dsi->phy.Tddr_clk = div_u64(1000000000000llu, dsi->phy.ddr_clk);
1201         dsi->phy.Ttxbyte_clk = div_u64(1000000000000llu, dsi->phy.txbyte_clk);
1202         dsi->phy.UI = dsi->phy.Tddr_clk;
1203
1204         MIPI_DBG("UI:%d\n", dsi->phy.UI);
1205         MIPI_DBG("ref_clk:%d\n", dsi->phy.ref_clk);
1206         MIPI_DBG("pclk:%d, Tpclk:%d\n", dsi->phy.pclk, dsi->phy.Tpclk);
1207         MIPI_DBG("sys_clk:%d, Tsys_clk:%d\n", dsi->phy.sys_clk, dsi->phy.Tsys_clk);
1208         MIPI_DBG("ddr_clk:%d, Tddr_clk:%d\n", dsi->phy.ddr_clk, dsi->phy.Tddr_clk);
1209         MIPI_DBG("txbyte_clk:%d, Ttxbyte_clk:%d\n", dsi->phy.txbyte_clk, dsi->phy.Ttxbyte_clk);
1210         MIPI_DBG("txclkesc:%d, Ttxclkesc:%d\n", dsi->phy.txclkesc, dsi->phy.Ttxclkesc);
1211
1212         rk_mipi_dsi_host_power_down(dsi);
1213         rk_mipi_dsi_phy_power_down(dsi);
1214         rk_mipi_dsi_phy_power_up(dsi);
1215         rk_mipi_dsi_phy_init(dsi);
1216         //rk_mipi_dsi_host_power_up(dsi);
1217         //rk_mipi_dsi_host_init(dsi);
1218         //dsi_set_bits(dsi, 0, shutdownz);
1219         rk_mipi_dsi_enable_hs_clk(dsi, 1);
1220         rk_mipi_dsi_enable_video_mode(dsi, 1);
1221         rk_mipi_dsi_is_enable(dsi, 1);
1222         return 0;
1223 }
1224
1225 static int rk_mipi_dsi_is_enable(void *arg, u32 enable)
1226 {
1227         struct dsi *dsi = arg;
1228
1229         dsi_set_bits(dsi, enable, shutdownz);
1230
1231         return 0;
1232 }
1233
1234 static int rk_mipi_dsi_enable_video_mode(void *arg, u32 enable)
1235 {
1236         struct dsi *dsi = arg;
1237 #ifdef DWC_DSI_VERSION_0x3131302A
1238         dsi_set_bits(dsi, enable, en_video_mode);
1239 #else
1240         dsi_set_bits(dsi, !enable, cmd_video_mode);
1241 #endif
1242
1243         return 0;
1244 }
1245
1246 static int rk_mipi_dsi_enable_command_mode(void *arg, u32 enable)
1247 {
1248         struct dsi *dsi = arg;
1249 #ifdef DWC_DSI_VERSION_0x3131302A
1250         dsi_set_bits(dsi, enable, en_cmd_mode);
1251 #else
1252         dsi_set_bits(dsi, enable, cmd_video_mode);
1253 #endif
1254         return 0;
1255 }
1256
1257 static int rk_mipi_dsi_enable_hs_clk(void *arg, u32 enable)
1258 {
1259         struct dsi *dsi = arg;
1260         dsi_set_bits(dsi, enable, phy_txrequestclkhs);
1261         return 0;
1262 }
1263
1264 static int rk_mipi_dsi_is_active(void *arg)
1265 {
1266         struct dsi *dsi = arg;
1267         return dsi_get_bits(dsi, shutdownz);
1268 }
1269
1270 static int rk_mipi_dsi_send_packet(struct dsi *dsi, u32 type, unsigned char regs[], u32 n)
1271 {
1272         u32 data = 0, i = 0, j = 0;
1273 #ifdef DWC_DSI_VERSION_0x3131302A
1274         u32 flag = 0;
1275 #endif
1276         if((n == 0) && (type != DTYPE_GEN_SWRITE_0P))
1277                 return -1;
1278 #ifndef CONFIG_MFD_RK616
1279         if(dsi_get_bits(dsi, gen_cmd_full) == 1) {
1280                 MIPI_TRACE("gen_cmd_full\n");
1281                 return -1;
1282         }
1283 #endif
1284
1285 #ifdef DWC_DSI_VERSION_0x3131302A
1286         if(dsi_get_bits(dsi, en_video_mode) == 1) {
1287                 //rk_mipi_dsi_enable_video_mode(dsi, 0);
1288                 flag = 1;
1289         }
1290 #endif
1291         //rk_mipi_dsi_enable_command_mode(dsi, 1);
1292         udelay(10);
1293
1294          if(n <= 2) {
1295             if(type ==  0x29)
1296             {
1297             printk("type=0x%x\n", type);
1298             data = 0;
1299                 for(i = 0; i < n; i++) {
1300                         j = i % 4;
1301                         data |= regs[i] << (j * 8);
1302                         if(j == 3 || ((i + 1) == n)) {
1303                                 #ifndef CONFIG_MFD_RK616
1304                                 if(dsi_get_bits(dsi, gen_pld_w_full) == 1) {
1305                                         MIPI_TRACE("gen_pld_w_full :%d\n", i);
1306                                         break;
1307                                 }
1308                                 #endif
1309                                 dsi_set_bits(dsi, data, GEN_PLD_DATA);
1310                                 MIPI_DBG("write GEN_PLD_DATA:%d, %08x\n", i, data);
1311                                 data = 0;
1312                         }
1313                 }
1314                 data = (dsi->vid << 6) | type;
1315                 data |= (n & 0xffff) << 8;
1316             }
1317                 else
1318                 {
1319                     if(type == DTYPE_GEN_SWRITE_0P)
1320                             data = (dsi->vid << 6) | (n << 4) | type;
1321                     else
1322                             data = (dsi->vid << 6) | ((n-1) << 4) | type;
1323
1324                 data |= regs[0] << 8;
1325                 if(n == 2)
1326                         data |= regs[1] << 16;
1327         }
1328         } else {
1329                 data = 0;
1330                 for(i = 0; i < n; i++) {
1331                         j = i % 4;
1332                         data |= regs[i] << (j * 8);
1333                         if(j == 3 || ((i + 1) == n)) {
1334                                 #ifndef CONFIG_MFD_RK616
1335                                 if(dsi_get_bits(dsi, gen_pld_w_full) == 1) {
1336                                         MIPI_TRACE("gen_pld_w_full :%d\n", i);
1337                                         break;
1338                                 }
1339                                 #endif
1340                                 dsi_set_bits(dsi, data, GEN_PLD_DATA);
1341                                 MIPI_DBG("write GEN_PLD_DATA:%d, %08x\n", i, data);
1342                                 data = 0;
1343                         }
1344                 }
1345                 data = (dsi->vid << 6) | type;
1346                 data |= (n & 0xffff) << 8;
1347         }
1348
1349         MIPI_DBG("write GEN_HDR:%08x\n", data);
1350         dsi_set_bits(dsi, data, GEN_HDR);
1351 #ifndef CONFIG_MFD_RK616
1352         i = 10;
1353         while(!dsi_get_bits(dsi, gen_cmd_empty) && i--) {
1354                 MIPI_DBG(".");
1355                 udelay(10);
1356         }
1357         udelay(10);
1358 #endif
1359
1360 #ifdef DWC_DSI_VERSION_0x3131302A
1361         //rk_mipi_dsi_enable_command_mode(dsi, 0);
1362         if(flag == 1) {
1363         //      rk_mipi_dsi_enable_video_mode(dsi, 1);
1364         }
1365 #endif
1366         return 0;
1367 }
1368
1369 static int rk_mipi_dsi_send_dcs_packet(void *arg, unsigned char regs[], u32 n)
1370 {
1371         struct dsi *dsi = arg;
1372         n -= 1;
1373         if((regs[1] ==0x2c) || (regs[1] ==0x3c))
1374         {
1375             dsi_set_bits(dsi, regs[0], dcs_sw_0p_tx);
1376                 rk_mipi_dsi_send_packet(dsi, DTYPE_DCS_LWRITE, regs + 1, n);
1377         }else
1378         if(n <= 2) {
1379                 if(n == 1)
1380                         dsi_set_bits(dsi, regs[0], dcs_sw_0p_tx);
1381                 else
1382                         dsi_set_bits(dsi, regs[0], dcs_sw_1p_tx);
1383                 rk_mipi_dsi_send_packet(dsi, DTYPE_DCS_SWRITE_0P, regs + 1, n);
1384         } else {
1385                 dsi_set_bits(dsi, regs[0], dcs_lw_tx);
1386                 rk_mipi_dsi_send_packet(dsi, DTYPE_DCS_LWRITE, regs + 1, n);
1387         }
1388         MIPI_DBG("***%s:%d command sent in %s size:%d\n", __func__, __LINE__, regs[0] ? "LP mode" : "HS mode", n);
1389         return 0;
1390 }
1391
1392 static int rk_mipi_dsi_send_gen_packet(void *arg, void *data, u32 n)
1393 {
1394         struct dsi *dsi = arg;
1395         unsigned char *regs = data;
1396         n -= 1;
1397         if(regs[1] == 0xb3)
1398         {
1399             dsi_set_bits(dsi, regs[0], gen_sw_1p_tx);
1400                 rk_mipi_dsi_send_packet(dsi, DTYPE_GEN_LWRITE, regs + 1, n);
1401         }
1402         else{
1403         if(n <= 2) {
1404                 if(n == 2)
1405                         dsi_set_bits(dsi, regs[0], gen_sw_2p_tx);
1406                 else if(n == 1)
1407                         dsi_set_bits(dsi, regs[0], gen_sw_1p_tx);
1408                 else
1409                         dsi_set_bits(dsi, regs[0], gen_sw_0p_tx);
1410                 rk_mipi_dsi_send_packet(dsi, DTYPE_GEN_SWRITE_0P, regs + 1, n);
1411         } else {
1412                 dsi_set_bits(dsi, regs[0], gen_lw_tx);
1413                 rk_mipi_dsi_send_packet(dsi, DTYPE_GEN_LWRITE, regs + 1, n);
1414         }
1415         }
1416         MIPI_DBG("***%s:%d command sent in %s size:%d\n", __func__, __LINE__, regs[0] ? "LP mode" : "HS mode", n);
1417         return 0;
1418 }
1419
1420 static int rk_mipi_dsi_read_dcs_packet(void *arg, unsigned char *data1, u32 n)
1421 {
1422     struct dsi *dsi = arg;
1423         //DCS READ
1424         //unsigned char *regs = data;
1425         unsigned char regs[2];
1426         regs[0] = LPDT;
1427         regs[1] = 0x0a;
1428          n = n - 1;
1429         u32 data = 0;
1430
1431         dsi_set_bits(dsi, regs[0], dcs_sr_0p_tx);
1432         int type = 0x06;
1433
1434    /* if(type == DTYPE_GEN_SWRITE_0P)
1435         data = (dsi->vid << 6) | (n << 4) | type;
1436     else
1437         data = (dsi->vid << 6) | ((n-1) << 4) | type;*/
1438
1439     data |= regs[1] << 8 | type;
1440    // if(n == 2)
1441     //    data |= regs[1] << 16;
1442
1443     MIPI_DBG("write GEN_HDR:%08x\n", data);
1444         dsi_set_bits(dsi, data, GEN_HDR);
1445     msleep(100);
1446
1447    // dsi_set_bits(dsi, regs[0], gen_sr_0p_tx);
1448
1449     printk("rk_mipi_dsi_read_dcs_packet==0x%x\n",dsi_get_bits(dsi, GEN_PLD_DATA));
1450     msleep(100);
1451
1452   //  dsi_set_bits(dsi, regs[0], max_rd_pkt_size);
1453
1454     msleep(100);
1455     // printk("_____rk_mipi_dsi_read_dcs_packet==0x%x\n",dsi_get_bits(dsi, GEN_PLD_DATA));
1456
1457     msleep(100);
1458         return 0;
1459 }
1460
1461 static int rk_mipi_dsi_power_up(void *arg)
1462 {
1463         struct dsi *dsi = arg;
1464         rk_mipi_dsi_phy_power_up(dsi);
1465         rk_mipi_dsi_host_power_up(dsi);
1466         return 0;
1467 }
1468
1469 static int rk_mipi_dsi_power_down(void *arg)
1470 {
1471     u8 dcs[4] = {0};
1472         struct dsi *dsi = arg;
1473         struct mipi_dsi_screen *screen = &dsi->screen;
1474
1475         if(!screen)
1476                 return -1;
1477
1478         if(!screen->standby) {
1479                 rk_mipi_dsi_enable_video_mode(dsi, 0);
1480                 dcs[0] = HSDT;
1481                 dcs[1] = dcs_set_display_off;
1482                 rk_mipi_dsi_send_dcs_packet(dsi, dcs, 2);
1483                 msleep(1);
1484                 dcs[0] = HSDT;
1485                 dcs[1] = dcs_enter_sleep_mode;
1486                 rk_mipi_dsi_send_dcs_packet(dsi, dcs, 2);
1487                 msleep(1);
1488         } else {
1489                 screen->standby(1);
1490         }
1491
1492         rk_mipi_dsi_host_power_down(dsi);
1493         rk_mipi_dsi_phy_power_down(dsi);
1494 #if defined(CONFIG_ARCH_RK319X)
1495         clk_disable(dsi->dsi_pd);
1496         clk_disable(dsi->dsi_pclk);
1497 #endif
1498         MIPI_TRACE("%s:%d\n", __func__, __LINE__);
1499         return 0;
1500 }
1501
1502 static int rk_mipi_dsi_get_id(void *arg)
1503 {
1504         u32 id = 0;
1505         struct dsi *dsi = arg;
1506         id = dsi_get_bits(dsi, VERSION);
1507         return id;
1508 }
1509
1510 /* the most top level of mipi dsi init */
1511 static int rk_mipi_dsi_probe(struct dsi *dsi)
1512 {
1513         int ret = 0;
1514
1515         register_dsi_ops(dsi->dsi_id, &dsi->ops);
1516
1517         ret = dsi_probe_current_chip(dsi->dsi_id);
1518         if(ret) {
1519                 MIPI_TRACE("mipi dsi probe fail\n");
1520                 return -ENODEV;
1521         }
1522
1523         return 0;
1524 }
1525
1526 #ifdef MIPI_DSI_REGISTER_IO
1527 #include <linux/proc_fs.h>
1528 #include <asm/uaccess.h>
1529 #include <linux/slab.h>
1530
1531 int reg_proc_write(struct file *file, const char __user *buff, size_t count, loff_t *offp)
1532 {
1533         int ret = -1, i = 0;
1534         u32 read_val = 0;
1535         char *buf = kmalloc(count, GFP_KERNEL);
1536         char *data = buf;
1537         char str[32];
1538         char command = 0;
1539         u64 regs_val = 0;
1540         memset(buf, 0, count);
1541         ret = copy_from_user((void*)buf, buff, count);
1542         data = strstr(data, "-");
1543         if(data == NULL)
1544                 goto reg_proc_write_exit;
1545         command = *(++data);
1546         switch(command) {
1547                 case 'w':
1548                         while(1) {
1549                                 data = strstr(data, "0x");
1550                                 if(data == NULL)
1551                                         goto reg_proc_write_exit;
1552
1553                                 sscanf(data, "0x%llx", &regs_val);
1554                                 if((regs_val & 0xffff00000000ULL) == 0)
1555                                         goto reg_proc_write_exit;
1556                                 read_val = regs_val & 0xffffffff;
1557                                 printk("regs_val=0x%llx\n",regs_val);
1558                                 dsi_write_reg(dsi0, regs_val >> 32, &read_val);
1559                                 dsi_read_reg(dsi0, regs_val >> 32, &read_val);
1560                                 regs_val &= 0xffffffff;
1561                                 if(read_val != regs_val)
1562                                         MIPI_TRACE("%s fail:0x%08x\n", __func__, read_val);
1563                                 data += 3;
1564                                 msleep(1);
1565                         }
1566
1567                         break;
1568                 case 'r':
1569                                 data = strstr(data, "0x");
1570                                 if(data == NULL){
1571                                         goto reg_proc_write_exit;
1572                                 }
1573                                 sscanf(data, "0x%llx", &regs_val);
1574                                 dsi_read_reg(dsi0, (u16)regs_val, &read_val);
1575                                 MIPI_TRACE("*%04x : %08x\n", (u16)regs_val, read_val);
1576                                 msleep(1);
1577                         break;
1578
1579                 case 's':
1580                                 while(*(++data) == ' ');
1581                                 sscanf(data, "%d", &read_val);
1582                                 if(read_val == 11)
1583                                         read_val = 11289600;
1584                                 else
1585                                         read_val *= MHz;
1586 #ifdef CONFIG_MFD_RK616
1587                                 clk_set_rate(dsi_rk616->mclk, read_val);
1588 #endif
1589                                 //rk_mipi_dsi_init_lite(dsi);
1590                         break;
1591                 case 'd':
1592                 case 'g':
1593                 case 'c':
1594                                 while(*(++data) == ' ');
1595                                 i = 0;
1596                                 MIPI_TRACE("****%d:%d\n", data-buf, count);
1597
1598                                 do {
1599                                         if(i > 31) {
1600                                                 MIPI_TRACE("payload entry is larger than 32\n");
1601                                                 break;
1602                                         }
1603                                         sscanf(data, "%x,", str + i);   //-c 1,29,02,03,05,06,> pro
1604                                         data = strstr(data, ",");
1605                                         if(data == NULL)
1606                                                 break;
1607                                         data++;
1608                                         i++;
1609                                 } while(1);
1610                                 read_val = i;
1611
1612                                 i = 2;
1613                                 while(i--) {
1614                                         msleep(10);
1615                                         if(command == 'd')
1616                                                 rk_mipi_dsi_send_dcs_packet(dsi0, str, read_val);
1617                                         else
1618                                                 rk_mipi_dsi_send_gen_packet(dsi0, str, read_val);
1619                                 }
1620                                 i = 1;
1621                                 while(i--) {
1622                                         msleep(1000);
1623                                 }
1624                         break;
1625
1626                 default:
1627                         break;
1628         }
1629
1630 reg_proc_write_exit:
1631         kfree(buf);
1632         msleep(20);
1633         return count;
1634 }
1635
1636 int reg_proc_read(struct file *file, char __user *buff, size_t count,
1637                                         loff_t *offp)
1638 {
1639         int i = 0;
1640         u32 val = 0;
1641
1642
1643     for(i = VERSION; i < (VERSION + (0xdc<<16)); i += 4<<16) {
1644                 val = dsi_get_bits(dsi0, i);
1645                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1646                 msleep(1);
1647         }
1648
1649         MIPI_TRACE("\n");
1650         /*for(i = DPHY_REGISTER0; i <= DPHY_REGISTER4; i += 4<<16) {
1651                 val = dsi_get_bits(dsi0, i);
1652                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1653                 msleep(1);
1654         }
1655         MIPI_TRACE("\n");
1656         i = DPHY_REGISTER20;
1657         val = dsi_get_bits(dsi0, i);
1658         MIPI_TRACE("%04x: %08x\n", i>>16, val);
1659         msleep(1);
1660
1661         MIPI_TRACE("\n");
1662         for(i = (DPHY_CLOCK_OFFSET + DSI_DPHY_BITS(0x0000, 32, 0)); i <= ((DPHY_CLOCK_OFFSET + DSI_DPHY_BITS(0x0048, 32, 0))); i += 4<<16) {
1663                 val = dsi_get_bits(dsi0, i);
1664                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1665                 msleep(1);
1666         }
1667
1668         MIPI_TRACE("\n");
1669         for(i = (DPHY_LANE0_OFFSET + DSI_DPHY_BITS(0x0000, 32, 0)); i <= ((DPHY_LANE0_OFFSET + DSI_DPHY_BITS(0x0048, 32, 0))); i += 4<<16) {
1670                 val = dsi_get_bits(dsi0, i);
1671                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1672                 msleep(1);
1673         }
1674
1675         MIPI_TRACE("\n");
1676         for(i = (DPHY_LANE1_OFFSET + DSI_DPHY_BITS(0x0000, 32, 0)); i <= ((DPHY_LANE1_OFFSET + DSI_DPHY_BITS(0x0048, 32, 0))); i += 4<<16) {
1677                 val = dsi_get_bits(dsi0, i);
1678                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1679                 msleep(1);
1680         }
1681
1682         MIPI_TRACE("\n");
1683         for(i = (DPHY_LANE2_OFFSET + DSI_DPHY_BITS(0x0000, 32, 0)); i <= ((DPHY_LANE2_OFFSET + DSI_DPHY_BITS(0x0048, 32, 0))); i += 4<<16) {
1684                 val = dsi_get_bits(dsi0, i);
1685                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1686                 msleep(1);
1687         }
1688
1689         MIPI_TRACE("\n");
1690         for(i = (DPHY_LANE3_OFFSET + DSI_DPHY_BITS(0x0000, 32, 0)); i <= ((DPHY_LANE3_OFFSET + DSI_DPHY_BITS(0x0048, 32, 0))); i += 4<<16) {
1691                 val = dsi_get_bits(dsi0, i);
1692                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1693                 msleep(1);
1694         }*/
1695         return -1;
1696 }
1697
1698 int reg_proc_open(struct inode *inode, struct file *file)
1699 {
1700         return 0;
1701 }
1702
1703 int reg_proc_close(struct inode *inode, struct file *file)
1704 {
1705         return 0;
1706 }
1707
1708 struct file_operations reg_proc_fops = {
1709     .owner  = THIS_MODULE,
1710         .open   = reg_proc_open,
1711         .release= reg_proc_close,
1712         .write  = reg_proc_write,
1713         .read   = reg_proc_read,
1714 };
1715
1716
1717 int reg_proc_write1(struct file *file, const char __user *buff, size_t count, loff_t *offp)
1718 {
1719         int ret = -1, i = 0;
1720         u32 read_val = 0;
1721         char *buf = kmalloc(count, GFP_KERNEL);
1722         char *data = buf;
1723         char str[32];
1724         char command = 0;
1725         u64 regs_val = 0;
1726         memset(buf, 0, count);
1727         ret = copy_from_user((void*)buf, buff, count);
1728
1729         data = strstr(data, "-");
1730         if(data == NULL)
1731                 goto reg_proc_write_exit;
1732         command = *(++data);
1733
1734         switch(command) {
1735                 case 'w':
1736                         while(1) {
1737
1738                                 data = strstr(data, "0x");
1739                                 if(data == NULL)
1740                                         goto reg_proc_write_exit;
1741                                 sscanf(data, "0x%llx", &regs_val);
1742                                 if((regs_val & 0xffff00000000ULL) == 0)
1743                                         goto reg_proc_write_exit;
1744                                 read_val = regs_val & 0xffffffff;
1745                                 dsi_write_reg(dsi1, regs_val >> 32, &read_val);
1746                                 dsi_read_reg(dsi1, regs_val >> 32, &read_val);
1747                                 regs_val &= 0xffffffff;
1748                                 if(read_val != regs_val)
1749                                         MIPI_TRACE("%s fail:0x%08x\n", __func__, read_val);
1750
1751                                 data += 3;
1752                                 msleep(1);
1753                         }
1754
1755                         break;
1756                 case 'r':
1757                                 data = strstr(data, "0x");
1758                                 if(data == NULL)
1759                                         goto reg_proc_write_exit;
1760                                 sscanf(data, "0x%llx", &regs_val);
1761                                 dsi_read_reg(dsi1, (u16)regs_val, &read_val);
1762                                 MIPI_TRACE("*%04x : %08x\n", (u16)regs_val, read_val);
1763                                 msleep(1);
1764                         break;
1765
1766                 case 's':
1767                                 while(*(++data) == ' ');
1768                                 sscanf(data, "%d", &read_val);
1769                                 if(read_val == 11)
1770                                         read_val = 11289600;
1771                                 else
1772                                         read_val *= MHz;
1773 #ifdef CONFIG_MFD_RK616
1774                                 clk_set_rate(dsi_rk616->mclk, read_val);
1775 #endif
1776                                 //rk_mipi_dsi_init_lite(dsi);
1777                         break;
1778                 case 'd':
1779                 case 'g':
1780                 case 'c':
1781                                 while(*(++data) == ' ');
1782                                 i = 0;
1783                                 MIPI_TRACE("****%d:%d\n", data-buf, count);
1784
1785                                 do {
1786                                         if(i > 31) {
1787                                                 MIPI_TRACE("payload entry is larger than 32\n");
1788                                                 break;
1789                                         }
1790                                         sscanf(data, "%x,", str + i);   //-c 1,29,02,03,05,06,> pro
1791                                         data = strstr(data, ",");
1792                                         if(data == NULL)
1793                                                 break;
1794                                         data++;
1795                                         i++;
1796                                 } while(1);
1797                                 read_val = i;
1798
1799                                 i = 2;
1800                                 while(i--) {
1801                                         msleep(10);
1802                                         if(command == 'd')
1803                                                 rk_mipi_dsi_send_dcs_packet(dsi1, str, read_val);
1804                                         else
1805                                                 rk_mipi_dsi_send_gen_packet(dsi1, str, read_val);
1806                                 }
1807                                 i = 1;
1808                                 while(i--) {
1809                                         msleep(1000);
1810                                 }
1811                         break;
1812
1813                 default:
1814                         break;
1815         }
1816
1817 reg_proc_write_exit:
1818         kfree(buf);
1819         msleep(20);
1820         return count;
1821 }
1822
1823 int reg_proc_read1(struct file *file, char __user *buff, size_t count,
1824                                         loff_t *offp)
1825 {
1826         int i = 0;
1827         u32 val = 0;
1828
1829         for(i = VERSION; i < (VERSION + (0xdc<<16)); i += 4<<16) {
1830                 val = dsi_get_bits(dsi1, i);
1831                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1832                 msleep(1);
1833         }
1834
1835         MIPI_TRACE("\n");
1836 /*      for(i = DPHY_REGISTER0; i <= DPHY_REGISTER4; i += 4<<16) {
1837                 val = dsi_get_bits(dsi1, i);
1838                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1839                 msleep(1);
1840         }
1841         MIPI_TRACE("\n");
1842         i = DPHY_REGISTER20;
1843         val = dsi_get_bits(dsi1, i);
1844         MIPI_TRACE("%04x: %08x\n", i>>16, val);
1845         msleep(1);
1846
1847         MIPI_TRACE("\n");
1848         for(i = (DPHY_CLOCK_OFFSET + DSI_DPHY_BITS(0x0000, 32, 0)); i <= ((DPHY_CLOCK_OFFSET + DSI_DPHY_BITS(0x0048, 32, 0))); i += 4<<16) {
1849                 val = dsi_get_bits(dsi1, i);
1850                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1851                 msleep(1);
1852         }
1853
1854         MIPI_TRACE("\n");
1855         for(i = (DPHY_LANE0_OFFSET + DSI_DPHY_BITS(0x0000, 32, 0)); i <= ((DPHY_LANE0_OFFSET + DSI_DPHY_BITS(0x0048, 32, 0))); i += 4<<16) {
1856                 val = dsi_get_bits(dsi1, i);
1857                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1858                 msleep(1);
1859         }
1860
1861         MIPI_TRACE("\n");
1862         for(i = (DPHY_LANE1_OFFSET + DSI_DPHY_BITS(0x0000, 32, 0)); i <= ((DPHY_LANE1_OFFSET + DSI_DPHY_BITS(0x0048, 32, 0))); i += 4<<16) {
1863                 val = dsi_get_bits(dsi1, i);
1864                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1865                 msleep(1);
1866         }
1867
1868         MIPI_TRACE("\n");
1869         for(i = (DPHY_LANE2_OFFSET + DSI_DPHY_BITS(0x0000, 32, 0)); i <= ((DPHY_LANE2_OFFSET + DSI_DPHY_BITS(0x0048, 32, 0))); i += 4<<16) {
1870                 val = dsi_get_bits(dsi1, i);
1871                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1872                 msleep(1);
1873         }
1874
1875         MIPI_TRACE("\n");
1876         for(i = (DPHY_LANE3_OFFSET + DSI_DPHY_BITS(0x0000, 32, 0)); i <= ((DPHY_LANE3_OFFSET + DSI_DPHY_BITS(0x0048, 32, 0))); i += 4<<16) {
1877                 val = dsi_get_bits(dsi1, i);
1878                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1879                 msleep(1);
1880         }*/
1881         return -1;
1882 }
1883
1884 int reg_proc_open1(struct inode *inode, struct file *file)
1885 {
1886         return 0;
1887 }
1888
1889 int reg_proc_close1(struct inode *inode, struct file *file)
1890 {
1891         return 0;
1892 }
1893
1894 struct file_operations reg_proc_fops1 = {
1895     .owner  = THIS_MODULE,
1896         .open   = reg_proc_open1,
1897         .release= reg_proc_close1,
1898         .write  = reg_proc_write1,
1899         .read   = reg_proc_read1,
1900 };
1901
1902 #if 0
1903 static int reg_proc_init(char *name)
1904 {
1905         int ret = 0;
1906 #if 0
1907 #ifdef CONFIG_MFD_RK616
1908         //debugfs_create_file("mipi", S_IRUSR, dsi_rk616->debugfs_dir, dsi_rk616,
1909                                                         &reg_proc_fops);
1910 #endif
1911 #else
1912         static struct proc_dir_entry *reg_proc_entry;
1913         reg_proc_entry = create_proc_entry(name, 0666, NULL);
1914         /*if(reg_proc_entry == NULL) {
1915                 //MIPI_TRACE("Couldn't create proc entry : %s!\n", name);
1916                 ret = -ENOMEM;
1917                 return ret;
1918         }
1919         else {
1920                 MIPI_TRACE("Create proc entry:%s success!\n", name);
1921                 reg_proc_entry->proc_fops = &reg_proc_fops;
1922         }*/
1923 #endif
1924         return ret;
1925 }
1926
1927 static int __init rk_mipi_dsi_reg(void)
1928 {
1929         return 0;//reg_proc_init("mipi_dsi");
1930 }
1931 module_init(rk_mipi_dsi_reg);
1932 #endif
1933 #endif
1934
1935
1936 #ifdef CONFIG_MIPI_DSI_FT
1937 static struct mipi_dsi_screen ft_screen;
1938
1939 static u32 fre_to_period(u32 fre)
1940 {
1941         u32 interger = 0;
1942         u32 decimals = 0;
1943         interger = 1000000000UL / fre;
1944         decimals = 1000000000UL % fre;
1945         if(decimals <= 40000000)
1946                 decimals = (decimals * 100) / (fre/10);
1947         else if(decimals <= 400000000)
1948                 decimals = (decimals * 10) / (fre/100);
1949         else
1950                 decimals = decimals / (fre/1000);
1951         interger = interger * 1000 + decimals;
1952
1953         return interger;
1954 }
1955
1956 static int rk616_mipi_dsi_set_screen_info(void)
1957 {
1958         g_screen = &ft_screen;
1959         g_screen->type = SCREEN_MIPI;
1960         g_screen->face = MIPI_DSI_OUT_FACE;
1961         g_screen->pixclock = MIPI_DSI_DCLK;
1962         g_screen->left_margin = MIPI_DSI_H_BP;
1963         g_screen->right_margin = MIPI_DSI_H_FP;
1964         g_screen->hsync_len = MIPI_DSI_H_PW;
1965         g_screen->upper_margin = MIPI_DSI_V_BP;
1966         g_screen->lower_margin = MIPI_DSI_V_FP;
1967         g_screen->vsync_len = MIPI_DSI_V_PW;
1968         g_screen->x_res = MIPI_DSI_H_VD;
1969         g_screen->y_res = MIPI_DSI_V_VD;
1970         g_screen->pin_hsync = MIPI_DSI_HSYNC_POL;
1971         g_screen->pin_vsync = MIPI_DSI_VSYNC_POL;
1972         g_screen->pin_den = MIPI_DSI_DEN_POL;
1973         g_screen->pin_dclk = MIPI_DSI_DCLK_POL;
1974         g_screen->dsi_lane = MIPI_DSI_LANE;
1975         g_screen->hs_tx_clk = MIPI_DSI_HS_CLK;
1976         g_screen->init = NULL;
1977         g_screen->standby = NULL;
1978         return 0;
1979 }
1980
1981 int rk616_mipi_dsi_ft_init(void)
1982 {
1983         rk616_mipi_dsi_set_screen_info();
1984         rk_mipi_dsi_init(g_screen, 0);
1985         return 0;
1986 }
1987 #endif  /* end of CONFIG_MIPI_DSI_FT */
1988
1989 #ifdef CONFIG_MIPI_DSI_LINUX
1990
1991 #ifdef CONFIG_HAS_EARLYSUSPEND
1992 void  rk616_mipi_dsi_suspend(void)
1993 {
1994         u8 dcs[4] = {0};
1995
1996         if(!g_screen->standby) {
1997                 rk_mipi_dsi_enable_video_mode(dsi, 0);
1998                 dcs[0] = HSDT;
1999                 dcs[1] = dcs_set_display_off;
2000                 rk_mipi_dsi_send_dcs_packet(dsi, dcs, 2);
2001                 msleep(1);
2002                 dcs[0] = HSDT;
2003                 dcs[1] = dcs_enter_sleep_mode;
2004                 rk_mipi_dsi_send_dcs_packet(dsi, dcs, 2);
2005                 msleep(1);
2006         } else {
2007                 g_screen->standby(1);
2008         }
2009
2010         rk_mipi_dsi_host_power_down(dsi);
2011         rk_mipi_dsi_phy_power_down(dsi);
2012 #if defined(CONFIG_ARCH_RK319X)
2013         clk_disable(dsi->dsi_pd);
2014         clk_disable(dsi->dsi_pclk);
2015 #endif
2016         MIPI_TRACE("%s:%d\n", __func__, __LINE__);
2017 }
2018
2019 void rk616_mipi_dsi_resume(void)
2020 {
2021         u8 dcs[4] = {0};
2022 #if defined(CONFIG_ARCH_RK319X)
2023         clk_enable(dsi->dsi_pd);
2024         clk_enable(dsi->dsi_pclk);
2025 #endif
2026         rk_mipi_dsi_phy_power_up(dsi);
2027         rk_mipi_dsi_host_power_up(dsi);
2028
2029 #ifdef CONFIG_MFD_RK616
2030         rk_mipi_recover_reg();
2031 #else
2032         rk_mipi_dsi_phy_init(dsi);
2033         rk_mipi_dsi_host_init(dsi);
2034 #endif
2035
2036 /*      if(!g_screen->standby) {
2037                 rk_mipi_dsi_enable_hs_clk(dsi, 1);
2038                 dcs[0] = HSDT;
2039                 dcs[1] = dcs_exit_sleep_mode;
2040                 rk_mipi_dsi_send_dcs_packet(dsi, dcs, 2);
2041                 msleep(1);
2042                 dcs[0] = HSDT;
2043                 dcs[1] = dcs_set_display_on;
2044                 rk_mipi_dsi_send_dcs_packet(dsi, dcs, 2);
2045                 //msleep(10);
2046         } else {
2047                 g_screen->standby(0);
2048         }*/
2049
2050         rk_mipi_dsi_is_enable(dsi, 0);
2051         rk_mipi_dsi_enable_video_mode(dsi, 1);
2052
2053 #ifdef CONFIG_MFD_RK616
2054         dsi_rk616->resume = 1;
2055         rk616_display_router_cfg(dsi_rk616, g_rk29fd_screen, 0);
2056         dsi_rk616->resume = 0;
2057 #endif
2058         rk_mipi_dsi_is_enable(dsi, 1, shutdownz);
2059         MIPI_TRACE("%s:%d\n", __func__, __LINE__);
2060 }
2061
2062
2063 #ifdef CONFIG_HAS_EARLYSUSPEND
2064 static void rk616_mipi_dsi_early_suspend(struct early_suspend *h)
2065 {
2066     rk616_mipi_dsi_suspend();
2067 }
2068
2069 static void rk616_mipi_dsi_late_resume(struct early_suspend *h)
2070 {
2071     rk616_mipi_dsi_resume();
2072 }
2073 #endif  /* end of CONFIG_HAS_EARLYSUSPEND */
2074 #endif
2075
2076
2077 #ifdef CONFIG_MFD_RK616
2078 static int rk616_mipi_dsi_notifier_event(struct notifier_block *this,
2079                 unsigned long event, void *ptr) {
2080
2081 #ifdef CONFIG_RK616_MIPI_DSI_RST
2082    if(event == 1)
2083     {
2084         g_screen->standby(0);
2085         mdelay(5);
2086         rk616_mipi_dsi_suspend();
2087         mdelay(10);
2088     }
2089     else if(event == 2)
2090     {
2091         rk_mipi_dsi_init_lite(dsi);
2092         mdelay(5);
2093         g_screen->standby(1);
2094         mdelay(5);
2095         rk616_mipi_dsi_resume();
2096     }
2097 #else
2098         rk_mipi_dsi_init_lite(dsi);
2099 #endif
2100         return 0;
2101 }
2102
2103 struct notifier_block mipi_dsi_nb= {
2104         .notifier_call = rk616_mipi_dsi_notifier_event,
2105 };
2106 #endif
2107
2108 #ifndef CONFIG_MFD_RK616
2109 static irqreturn_t rk616_mipi_dsi_irq_handler(int irq, void *data)
2110 {
2111         return IRQ_HANDLED;
2112         //return IRQ_NONE;
2113 }
2114 #endif
2115
2116 static int rk32_dsi_enable(void)
2117 {
2118     MIPI_DBG("rk32_dsi_enable-------\n");
2119
2120     dsi_init(0, NULL, 0);
2121     if (rk_mipi_get_dsi_num() ==2)
2122         dsi_init(1, NULL, 0);
2123
2124     rk_mipi_screen_standby(0);
2125
2126         /*
2127                 After the core reset, DPI waits for the first VSYNC active transition to start signal sampling, including
2128                 pixel data, and preventing image transmission in the middle of a frame.
2129         */
2130     dsi_is_enable(0, 0);
2131     if (rk_mipi_get_dsi_num() ==2)
2132         dsi_is_enable(1, 0);
2133
2134     dsi_enable_video_mode(0, 1);
2135     dsi_enable_video_mode(1, 1);
2136
2137 #ifdef CONFIG_MFD_RK616
2138         rk616_display_router_cfg(dsi_rk616, g_rk29fd_screen, 0);
2139 #endif
2140
2141     dsi_is_enable(0, 1);
2142     if (rk_mipi_get_dsi_num() ==2)
2143         dsi_is_enable(1, 1);
2144
2145     return 0;
2146 }
2147
2148 static int rk32_dsi_disable(void)
2149 {
2150     MIPI_DBG("rk32_dsi_disable-------\n");
2151
2152         rk_mipi_screen_standby(1);
2153     dsi_power_off(0);
2154     if (rk_mipi_get_dsi_num() ==2)
2155         dsi_power_off(1);
2156
2157     return 0;
2158 }
2159
2160
2161 static struct rk_fb_trsm_ops trsm_dsi_ops =
2162 {
2163     .enable = rk32_dsi_enable,
2164     .disable = rk32_dsi_disable,
2165 };
2166
2167 static void rk32_init_phy_mode(int lcdc_id)
2168 {
2169     int val0 = 0, val1 = 0;
2170
2171     MIPI_DBG("rk32_init_phy_mode----------lcdc_id=%d\n",lcdc_id);
2172     //D-PHY mode select
2173     if( rk_mipi_get_dsi_num() ==1 ){
2174
2175         if(lcdc_id == 1)
2176         //val0 =0x1 << 25 | 0x1 << 9;
2177            val0 = 0x1 << 22 | 0x1 << 6;  //1'b1: VOP LIT output to DSI host0;1'b0: VOP BIG output to DSI host0
2178         else
2179            val0 = 0x1 << 22 | 0x0 << 6;
2180
2181         writel_relaxed(val0, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
2182     }
2183     else{
2184         if(lcdc_id == 1){
2185             val0 = 0x1 << 25 | 0x1 <<  9 | 0x1 << 22 | 0x1 <<  6;
2186             val1 = 0x1 << 31 | 0x1 << 30 | 0x0 << 15 | 0x1 << 14;
2187          }
2188          else{
2189             val0 = 0x1 << 25 | 0x0 <<  9 | 0x1 << 22 | 0x0 << 14;
2190             val1 = 0x1 << 31 | 0x1 << 30 | 0x0 << 15 | 0x1 << 14;
2191          }
2192
2193          writel_relaxed(val0, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
2194          writel_relaxed(val1, RK_GRF_VIRT + RK3288_GRF_SOC_CON14);
2195     }
2196
2197 }
2198
2199 static int rk616_mipi_dsi_probe(struct platform_device *pdev)
2200 {
2201         int ret = 0;
2202         struct dsi *dsi;
2203         struct mipi_dsi_ops *ops;
2204         struct rk_screen *screen;
2205         struct mipi_dsi_screen *dsi_screen;
2206         static int id = 0;
2207
2208 #if defined(CONFIG_ARCH_RK319X) || defined(CONFIG_ARCH_RK3288)
2209         struct resource *res_host, *res_phy, *res_irq;
2210 #endif
2211 #if defined(CONFIG_MFD_RK616)
2212         struct mfd_rk616 *rk616;
2213 #endif
2214         dsi = devm_kzalloc(&pdev->dev, sizeof(struct dsi), GFP_KERNEL);
2215         if(!dsi) {
2216                 dev_err(&pdev->dev,"request struct dsi fail!\n");
2217                 return -ENOMEM;
2218         }
2219
2220 #if defined(CONFIG_MFD_RK616)
2221         rk616 = dev_get_drvdata(pdev->dev.parent);
2222         if(!rk616) {
2223                 dev_err(&pdev->dev,"null mfd device rk616!\n");
2224                 ret = -ENODEV;
2225                 goto probe_err1;
2226         } else {
2227                 dsi_rk616 = rk616;
2228         }
2229         clk_notifier_register(rk616->mclk, &mipi_dsi_nb);
2230 #elif defined(CONFIG_ARCH_RK319X)
2231         res_host = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mipi_dsi_host");
2232         if (!res_host) {
2233                 dev_err(&pdev->dev, "get resource mipi_dsi_host fail\n");
2234                 ret = -EINVAL;
2235                 goto probe_err1;
2236         }
2237         if (!request_mem_region(res_host->start, resource_size(res_host), pdev->name)) {
2238                 dev_err(&pdev->dev, "host memory region already claimed\n");
2239                 ret = -EBUSY;
2240                 goto probe_err1;
2241         }
2242         dsi->host.iobase = res_host->start;
2243         dsi->host.membase = ioremap_nocache(res_host->start, resource_size(res_host));
2244         if (!dsi->host.membase) {
2245                 dev_err(&pdev->dev, "ioremap mipi_dsi_host fail\n");
2246                 ret = -ENXIO;
2247                 goto probe_err2;
2248         }
2249
2250         res_phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mipi_dsi_phy");
2251         if (!res_phy) {
2252                 dev_err(&pdev->dev, "get resource mipi_dsi_phy fail\n");
2253                 ret = -EINVAL;
2254                 goto probe_err3;
2255         }
2256         if (!request_mem_region(res_phy->start, resource_size(res_phy), pdev->name)) {
2257                 dev_err(&pdev->dev, "phy memory region already claimed\n");
2258                 ret = -EBUSY;
2259                 goto probe_err3;
2260         }
2261         dsi->phy.iobase = res_phy->start;
2262         dsi->phy.membase = ioremap_nocache(res_phy->start, resource_size(res_phy));
2263         if (!dsi->phy.membase) {
2264                 dev_err(&pdev->dev, "ioremap mipi_dsi_phy fail\n");
2265                 ret = -ENXIO;
2266                 goto probe_err4;
2267         }
2268
2269         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2270         if (!res_irq) {
2271                 dev_err(&pdev->dev, "get resource mipi_dsi irq fail\n");
2272                 ret = -EINVAL;
2273                 goto probe_err5;
2274         }
2275         dsi->host.irq = res_irq->start;
2276         ret = request_irq(dsi->host.irq, rk616_mipi_dsi_irq_handler, 0,
2277                                         dev_name(&pdev->dev), dsi);
2278         if(ret) {
2279                 dev_err(&pdev->dev, "request mipi_dsi irq fail\n");
2280                 ret = -EINVAL;
2281                 goto probe_err5;
2282         }
2283         disable_irq(dsi->host.irq);
2284
2285         dsi->phy.refclk = clk_get(NULL, "mipi_ref");
2286         if (unlikely(IS_ERR(dsi->phy.refclk))) {
2287                 dev_err(&pdev->dev, "get mipi_ref clock fail\n");
2288                 ret = PTR_ERR(dsi->phy.refclk);
2289                 goto probe_err6;
2290         }
2291         dsi->dsi_pclk = clk_get(NULL, "pclk_mipi_dsi");
2292         if (unlikely(IS_ERR(dsi->dsi_pclk))) {
2293                 dev_err(&pdev->dev, "get pclk_mipi_dsi clock fail\n");
2294                 ret = PTR_ERR(dsi->dsi_pclk);
2295                 goto probe_err7;
2296         }
2297         dsi->dsi_pd = clk_get(NULL, "pd_mipi_dsi");
2298         if (unlikely(IS_ERR(dsi->dsi_pd))) {
2299                 dev_err(&pdev->dev, "get pd_mipi_dsi clock fail\n");
2300                 ret = PTR_ERR(dsi->dsi_pd);
2301                 goto probe_err8;
2302         }
2303
2304         clk_enable(dsi->dsi_pd);
2305         clk_enable(dsi->dsi_pclk);
2306         clk_enable(clk_get(NULL, "pclk_mipiphy_dsi"));
2307
2308 #elif defined(CONFIG_ARCH_RK3288)
2309
2310         res_host = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2311         dsi->host.membase = devm_request_and_ioremap(&pdev->dev, res_host);
2312         if (!dsi->host.membase)
2313                 return -ENOMEM;
2314
2315     dsi->phy.refclk  = devm_clk_get(&pdev->dev, "clk_mipi_24m");
2316         if (unlikely(IS_ERR(dsi->phy.refclk))) {
2317                 dev_err(&pdev->dev, "get mipi_ref clock fail\n");
2318                 ret = PTR_ERR(dsi->phy.refclk);
2319                 //goto probe_err6;
2320         }
2321
2322    dsi->dsi_pclk = devm_clk_get(&pdev->dev, "pclk_mipi_dsi");
2323    if (unlikely(IS_ERR(dsi->dsi_pclk))) {
2324        dev_err(&pdev->dev, "get pclk_mipi_dsi clock fail\n");
2325        ret = PTR_ERR(dsi->dsi_pclk);
2326        //goto probe_err7;
2327    }
2328
2329
2330
2331    // printk("dsi->phy.refclk =%x\n",dsi->phy.refclk);
2332
2333     //clk_prepare_enable(dsi->phy.refclk);
2334
2335     //clk_disable_unprepare(dsi->phy.refclk);
2336
2337
2338         dsi->host.irq = platform_get_irq(pdev, 0);
2339         if (dsi->host.irq < 0) {
2340                 dev_err(&pdev->dev, "no irq resource?\n");
2341                 return dsi->host.irq;
2342         }
2343
2344         ret = request_irq(dsi->host.irq, rk616_mipi_dsi_irq_handler, 0,dev_name(&pdev->dev), dsi);
2345         if(ret) {
2346                 dev_err(&pdev->dev, "request mipi_dsi irq fail\n");
2347                 ret = -EINVAL;
2348                 goto probe_err1;
2349         }
2350     printk("dsi->host.irq =%d\n",dsi->host.irq);
2351
2352     disable_irq(dsi->host.irq);
2353
2354 #endif  /* CONFIG_MFD_RK616 */
2355
2356         screen = devm_kzalloc(&pdev->dev, sizeof(struct rk_screen), GFP_KERNEL);
2357         if(!screen) {
2358                 dev_err(&pdev->dev,"request struct rk_screen fail!\n");
2359                 goto probe_err9;
2360         }
2361         rk_fb_get_prmry_screen(screen);
2362
2363 #ifdef CONFIG_MFD_RK616
2364         g_rk29fd_screen = screen;
2365 #endif
2366
2367         dsi->pdev = pdev;
2368         ops = &dsi->ops;
2369         ops->dsi = dsi;
2370         ops->id = DWC_DSI_VERSION,
2371         ops->get_id = rk_mipi_dsi_get_id,
2372         ops->dsi_send_packet = rk_mipi_dsi_send_gen_packet,
2373         ops->dsi_send_dcs_packet = rk_mipi_dsi_send_dcs_packet,
2374         ops->dsi_read_dcs_packet = rk_mipi_dsi_read_dcs_packet,
2375         ops->dsi_enable_video_mode = rk_mipi_dsi_enable_video_mode,
2376         ops->dsi_enable_command_mode = rk_mipi_dsi_enable_command_mode,
2377         ops->dsi_enable_hs_clk = rk_mipi_dsi_enable_hs_clk,
2378         ops->dsi_is_active = rk_mipi_dsi_is_active,
2379         ops->dsi_is_enable= rk_mipi_dsi_is_enable,
2380         ops->power_up = rk_mipi_dsi_power_up,
2381         ops->power_down = rk_mipi_dsi_power_down,
2382         ops->dsi_init = rk_mipi_dsi_init,
2383
2384         dsi_screen = &dsi->screen;
2385         dsi_screen->type = screen->type;
2386         dsi_screen->face = screen->face;
2387         dsi_screen->lcdc_id = screen->lcdc_id;
2388         dsi_screen->screen_id = screen->screen_id;
2389         dsi_screen->pixclock = screen->mode.pixclock;
2390         dsi_screen->left_margin = screen->mode.left_margin;
2391         dsi_screen->right_margin = screen->mode.right_margin;
2392         dsi_screen->hsync_len = screen->mode.hsync_len;
2393         dsi_screen->upper_margin = screen->mode.upper_margin;
2394         dsi_screen->lower_margin = screen->mode.lower_margin;
2395         dsi_screen->vsync_len = screen->mode.vsync_len;
2396         dsi_screen->x_res = screen->mode.xres;
2397         dsi_screen->y_res = screen->mode.yres;
2398         dsi_screen->pin_hsync = screen->pin_hsync;
2399     dsi_screen->pin_vsync = screen->pin_vsync;
2400         dsi_screen->pin_den = screen->pin_den;
2401         dsi_screen->pin_dclk = screen->pin_dclk;
2402     dsi_screen->dsi_lane = rk_mipi_get_dsi_lane();
2403 //  dsi_screen->dsi_video_mode = screen->dsi_video_mode; //no sure
2404         dsi_screen->dsi_lane = rk_mipi_get_dsi_lane();
2405         dsi_screen->hs_tx_clk = rk_mipi_get_dsi_clk();
2406         dsi_screen->lcdc_id = 1;
2407
2408         dsi->dsi_id = id++;//of_alias_get_id(pdev->dev.of_node, "dsi");
2409
2410         sprintf(ops->name, "rk_mipi_dsi.%d", dsi->dsi_id);
2411         platform_set_drvdata(pdev, dsi);
2412
2413 #ifdef CONFIG_MFD_RK616
2414         host_mem = kzalloc(MIPI_DSI_HOST_SIZE, GFP_KERNEL);
2415         if(!host_mem) {
2416                 dev_err(&pdev->dev,"request host_mem fail!\n");
2417                 ret = -ENOMEM;
2418                 goto probe_err10;
2419         }
2420         phy_mem = kzalloc(MIPI_DSI_PHY_SIZE, GFP_KERNEL);
2421         if(!phy_mem) {
2422                 kfree(host_mem);
2423                 dev_err(&pdev->dev,"request phy_mem fail!\n");
2424                 ret = -ENOMEM;
2425                 goto probe_err10;
2426         }
2427
2428         memset(host_mem, 0xaa, MIPI_DSI_HOST_SIZE);
2429         memset(phy_mem, 0xaa, MIPI_DSI_PHY_SIZE);
2430 #endif
2431
2432         ret = rk_mipi_dsi_probe(dsi);
2433         if(ret) {
2434                 dev_err(&pdev->dev,"rk mipi_dsi probe fail!\n");
2435                 dev_err(&pdev->dev,"%s\n", RK_MIPI_DSI_VERSION_AND_TIME);
2436                 goto probe_err11;
2437         }
2438 #ifdef CONFIG_HAS_EARLYSUSPEND
2439         dsi->early_suspend.suspend = rk616_mipi_dsi_early_suspend;
2440         dsi->early_suspend.resume = rk616_mipi_dsi_late_resume;
2441         dsi->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1;
2442         register_early_suspend(&dsi->early_suspend);
2443 #endif
2444
2445     if(id == 1){
2446         rk32_init_phy_mode(dsi_screen->lcdc_id);
2447         rk_fb_trsm_ops_register(&trsm_dsi_ops, SCREEN_MIPI);
2448
2449 #ifdef MIPI_DSI_REGISTER_IO
2450                 debugfs_create_file("mipidsi0", S_IFREG | S_IRUGO, dsi->debugfs_dir, dsi,
2451                                                         &reg_proc_fops);
2452 #endif
2453         dsi0 = dsi;
2454
2455     }else{
2456         dsi1 = dsi;
2457
2458 #ifdef MIPI_DSI_REGISTER_IO
2459         debugfs_create_file("mipidsi1", S_IFREG | S_IRUGO, dsi->debugfs_dir, dsi,
2460                                                         &reg_proc_fops1);
2461 #endif
2462
2463     }
2464
2465         dev_info(&pdev->dev,"rk mipi_dsi probe success!\n");
2466         dev_info(&pdev->dev,"%s\n", RK_MIPI_DSI_VERSION_AND_TIME);
2467         return 0;
2468
2469 probe_err11:
2470 #ifdef CONFIG_MFD_RK616
2471         kfree(host_mem);
2472         kfree(phy_mem);
2473 probe_err10:
2474 #endif
2475
2476 probe_err9:
2477 #if defined(CONFIG_ARCH_RK319X)
2478         clk_put(dsi->dsi_pd);
2479 probe_err8:
2480         clk_put(dsi->dsi_pclk);
2481 probe_err7:
2482         clk_put(dsi->phy.refclk);
2483 probe_err6:
2484         free_irq(dsi->host.irq, dsi);
2485 probe_err5:
2486         iounmap(dsi->phy.membase);
2487 probe_err4:
2488         release_mem_region(res_phy->start, resource_size(res_phy));
2489 probe_err3:
2490         iounmap(dsi->host.membase);
2491 probe_err2:
2492         release_mem_region(res_host->start, resource_size(res_host));
2493 #endif
2494
2495 probe_err1:
2496
2497         return ret;
2498
2499 }
2500
2501 static int rk616_mipi_dsi_remove(struct platform_device *pdev)
2502 {
2503         //struct dsi *dsi = platform_get_drvdata(pdev);
2504 #ifdef CONFIG_MFD_RK616
2505         clk_notifier_unregister(dsi_rk616->mclk, &mipi_dsi_nb);
2506 #endif
2507         return 0;
2508 }
2509
2510 static void rk616_mipi_dsi_shutdown(struct platform_device *pdev)
2511 {
2512         u8 dcs[4] = {0};
2513         struct dsi *dsi = platform_get_drvdata(pdev);
2514
2515         if(!dsi->screen.standby) {
2516                 rk_mipi_dsi_enable_video_mode(dsi, 0);
2517                 dcs[0] = HSDT;
2518                 dcs[1] = dcs_set_display_off;
2519                 rk_mipi_dsi_send_dcs_packet(dsi, dcs, 2);
2520                 msleep(1);
2521                 dcs[0] = HSDT;
2522                 dcs[1] = dcs_enter_sleep_mode;
2523                 rk_mipi_dsi_send_dcs_packet(dsi, dcs, 2);
2524                 msleep(1);
2525         } else {
2526                 dsi->screen.standby(1);
2527         }
2528
2529         rk_mipi_dsi_host_power_down(dsi);
2530         rk_mipi_dsi_phy_power_down(dsi);
2531
2532         MIPI_TRACE("%s:%d\n", __func__, __LINE__);
2533         return;
2534 }
2535
2536 #ifdef CONFIG_OF
2537 static const struct of_device_id of_rk_mipi_dsi_match[] = {
2538         { .compatible = "rockchip,rk32-dsi" },
2539         { /* Sentinel */ }
2540 };
2541 #endif
2542
2543 static struct platform_driver rk616_mipi_dsi_driver = {
2544         .driver         = {
2545                 .name   = "rk616-mipi",
2546 #ifdef CONFIG_OF
2547                 .of_match_table = of_rk_mipi_dsi_match,
2548 #endif
2549                 .owner  = THIS_MODULE,
2550         },
2551         .probe          = rk616_mipi_dsi_probe,
2552         .remove         = rk616_mipi_dsi_remove,
2553         .shutdown       = rk616_mipi_dsi_shutdown,
2554 };
2555
2556 static int __init rk616_mipi_dsi_init(void)
2557 {
2558         return platform_driver_register(&rk616_mipi_dsi_driver);
2559 }
2560 fs_initcall(rk616_mipi_dsi_init);
2561
2562 static void __exit rk616_mipi_dsi_exit(void)
2563 {
2564         platform_driver_unregister(&rk616_mipi_dsi_driver);
2565 }
2566 module_exit(rk616_mipi_dsi_exit);
2567 #endif  /* end of CONFIG_MIPI_DSI_LINUX */