2 * Copyright (C) 2014 ROCKCHIP, Inc.
3 * drivers/video/display/transmitter/rk32_mipi_dsi.c
4 * author: libing@rock-chips.com
5 * create date: 2014-04-10
6 * debug /sys/kernel/debug/mipidsi*
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #ifndef CONFIG_RK32_MIPI_DSI
22 #ifdef CONFIG_RK32_MIPI_DSI
23 #define MIPI_DSI_REGISTER_IO 0
24 #define CONFIG_MIPI_DSI_LINUX 0
26 #define DWC_DSI_VERSION 0x3133302A
27 #define DWC_DSI_VERSION_RK312x 0x3132312A
28 #define DWC_DSI_VERSION_RK3368 0x3133302B
29 #define DWC_DSI_VERSION_ERR -1
31 #include <linux/kernel.h>
32 #include <linux/init.h>
33 #include <linux/platform_device.h>
34 #include <linux/slab.h>
35 #include <linux/rk_fb.h>
36 #include <linux/rk_screen.h>
37 #include <linux/delay.h>
38 #include <linux/clk.h>
39 #include <linux/interrupt.h>
40 #include <asm/div64.h>
43 #include <linux/debugfs.h>
44 #include <linux/seq_file.h>
45 #include <linux/regulator/machine.h>
47 #include <linux/dma-mapping.h>
49 #include "rk32_mipi_dsi.h"
50 #include <linux/rockchip/iomap.h>
51 #include <linux/rockchip/cpu.h>
53 #define MIPI_DBG(x...) /* printk(KERN_INFO x) */
55 #ifdef CONFIG_MIPI_DSI_LINUX
56 #define MIPI_TRACE(x...) /* printk(KERN_INFO x) */
58 #define MIPI_TRACE(...) \
69 *v1.0 : this driver is rk32 mipi dsi driver of rockchip;
70 *v1.1 : add test eye pattern;
74 #define RK_MIPI_DSI_VERSION_AND_TIME "rockchip mipi_dsi v1.1 2014-06-17"
76 static struct dsi *dsi0;
77 static struct dsi *dsi1;
79 static int rk32_mipi_dsi_is_active(void *arg);
80 static int rk32_mipi_dsi_enable_hs_clk(void *arg, u32 enable);
81 static int rk32_mipi_dsi_enable_video_mode(void *arg, u32 enable);
82 static int rk32_mipi_dsi_enable_command_mode(void *arg, u32 enable);
83 static int rk32_mipi_dsi_is_enable(void *arg, u32 enable);
84 static int rk32_mipi_power_down_DDR(void);
85 static int rk32_mipi_power_up_DDR(void);
86 int rk_mipi_screen_standby(u8 enable);
88 static int rk32_dsi_read_reg(struct dsi *dsi, u16 reg, u32 *pval)
90 if (dsi->ops.id == DWC_DSI_VERSION)
91 *pval = __raw_readl(dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
92 else if (dsi->ops.id == DWC_DSI_VERSION_RK312x ||
93 dsi->ops.id == DWC_DSI_VERSION_RK3368) {
94 if (reg >= MIPI_DSI_HOST_OFFSET)
95 *pval = __raw_readl(dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
96 else if (reg >= MIPI_DSI_PHY_OFFSET)
97 *pval = __raw_readl(dsi->phy.membase + (reg - MIPI_DSI_PHY_OFFSET));
102 static int rk32_dsi_write_reg(struct dsi *dsi, u16 reg, u32 *pval)
104 if (dsi->ops.id == DWC_DSI_VERSION)
105 __raw_writel(*pval, dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
106 else if (dsi->ops.id == DWC_DSI_VERSION_RK312x ||
107 dsi->ops.id == DWC_DSI_VERSION_RK3368) {
108 if (reg >= MIPI_DSI_HOST_OFFSET)
109 __raw_writel(*pval, dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
110 else if (reg >= MIPI_DSI_PHY_OFFSET)
111 __raw_writel(*pval, dsi->phy.membase + (reg - MIPI_DSI_PHY_OFFSET));
116 static int rk32_dsi_get_bits(struct dsi *dsi, u32 reg)
119 u32 bits = (reg >> 8) & 0xff;
120 u16 reg_addr = (reg >> 16) & 0xffff;
121 u8 offset = reg & 0xff;
124 bits = (1 << bits) - 1;
128 rk32_dsi_read_reg(dsi, reg_addr, &val);
134 static int rk32_dsi_set_bits(struct dsi *dsi, u32 data, u32 reg)
137 u32 bits = (reg >> 8) & 0xff;
138 u16 reg_addr = (reg >> 16) & 0xffff;
139 u8 offset = reg & 0xff;
142 bits = (1 << bits) - 1;
146 if (bits != 0xffffffff)
147 rk32_dsi_read_reg(dsi, reg_addr, &val);
149 val &= ~(bits << offset);
150 val |= (data & bits) << offset;
151 rk32_dsi_write_reg(dsi, reg_addr, &val);
153 if(data > ((1 << (bits+1)) - 1)) {
154 MIPI_TRACE("%s error reg_addr:0x%04x, offset:%d, bits:0x%04x, value:0x%04x\n",
155 __func__, reg_addr, offset, bits, data);
160 static int rk32_dwc_phy_test_rd(struct dsi *dsi, unsigned char test_code)
163 rk32_dsi_set_bits(dsi, 1, phy_testclk);
164 rk32_dsi_set_bits(dsi, test_code, phy_testdin);
165 rk32_dsi_set_bits(dsi, 1, phy_testen);
166 rk32_dsi_set_bits(dsi, 0, phy_testclk);
167 rk32_dsi_set_bits(dsi, 0, phy_testen);;
169 rk32_dsi_set_bits(dsi, 0, phy_testen);
170 val = rk32_dsi_get_bits(dsi, phy_testdout);
171 rk32_dsi_set_bits(dsi, 1, phy_testclk);
172 rk32_dsi_set_bits(dsi, 0, phy_testclk);
177 static int rk32_dwc_phy_test_wr(struct dsi *dsi, unsigned char test_code, unsigned char *test_data, unsigned char size)
181 MIPI_DBG("test_code=0x%x,test_data=0x%x\n", test_code, test_data[0]);
182 rk32_dsi_set_bits(dsi, 0x10000 | test_code, PHY_TEST_CTRL1);
183 rk32_dsi_set_bits(dsi, 0x2, PHY_TEST_CTRL0);
184 rk32_dsi_set_bits(dsi, 0x0, PHY_TEST_CTRL0);
186 for (i = 0; i < size; i++) {
187 rk32_dsi_set_bits(dsi, test_data[i], PHY_TEST_CTRL1);
188 rk32_dsi_set_bits(dsi, 0x2, PHY_TEST_CTRL0);
189 rk32_dsi_set_bits(dsi, 0x0, PHY_TEST_CTRL0);
190 MIPI_DBG("rk32_dwc_phy_test_wr:%08x\n", rk32_dsi_get_bits(dsi, PHY_TEST_CTRL1));
195 static int rk32_phy_power_up(struct dsi *dsi)
197 /* enable ref clock */
198 clk_prepare_enable(dsi->phy.refclk);
199 clk_prepare_enable(dsi->dsi_pclk);
200 clk_prepare_enable(dsi->dsi_pd);
203 switch (dsi->host.lane) {
205 rk32_dsi_set_bits(dsi, 3, n_lanes);
208 rk32_dsi_set_bits(dsi, 2, n_lanes);
211 rk32_dsi_set_bits(dsi, 1, n_lanes);
214 rk32_dsi_set_bits(dsi, 0, n_lanes);
219 rk32_dsi_set_bits(dsi, 1, phy_shutdownz);
220 rk32_dsi_set_bits(dsi, 1, phy_rstz);
221 rk32_dsi_set_bits(dsi, 1, phy_enableclk);
222 rk32_dsi_set_bits(dsi, 1, phy_forcepll);
227 static int rk312x_mipi_dsi_phy_set_gotp(struct dsi *dsi, u32 offset, int n)
229 u32 val = 0, temp = 0, Tlpx = 0;
230 u32 ddr_clk = dsi->phy.ddr_clk;
231 u32 Ttxbyte_clk = dsi->phy.Ttxbyte_clk;
232 u32 Tsys_clk = dsi->phy.Tsys_clk;
233 u32 Ttxclkesc = dsi->phy.Ttxclkesc;
234 printk("%s : ddr_clk %d\n", __func__, ddr_clk);
236 case DPHY_CLOCK_OFFSET:
237 MIPI_DBG("******set DPHY_CLOCK_OFFSET gotp******\n");
239 case DPHY_LANE0_OFFSET:
240 MIPI_DBG("******set DPHY_LANE0_OFFSET gotp******\n");
242 case DPHY_LANE1_OFFSET:
243 MIPI_DBG("******set DPHY_LANE1_OFFSET gotp******\n");
245 case DPHY_LANE2_OFFSET:
246 MIPI_DBG("******set DPHY_LANE2_OFFSET gotp******\n");
248 case DPHY_LANE3_OFFSET:
249 MIPI_DBG("******set DPHY_LANE3_OFFSET gotp******\n");
255 if (ddr_clk < 110 * MHz)
257 else if (ddr_clk < 150 * MHz)
259 else if (ddr_clk < 200 * MHz)
261 else if (ddr_clk < 250 * MHz)
263 else if (ddr_clk < 300 * MHz)
265 else if (ddr_clk < 400 * MHz)
267 else if (ddr_clk < 500 * MHz)
269 else if (ddr_clk < 600 * MHz)
271 else if (ddr_clk < 700 * MHz)
273 else if (ddr_clk < 800 * MHz)
275 else if (ddr_clk <= 1000 * MHz)
277 printk("%s reg_ths_settle = 0x%x\n", __func__, val);
278 rk32_dsi_set_bits(dsi, val, reg_ths_settle + offset);
280 if (ddr_clk < 110 * MHz)
282 else if (ddr_clk < 150 * MHz)
284 else if (ddr_clk < 200 * MHz)
286 else if (ddr_clk < 250 * MHz)
288 else if (ddr_clk < 300 * MHz)
290 else if (ddr_clk < 400 * MHz)
292 else if (ddr_clk < 500 * MHz)
294 else if (ddr_clk < 600 * MHz)
296 else if (ddr_clk < 700 * MHz)
298 else if (ddr_clk < 800 * MHz)
300 else if (ddr_clk <= 1000 * MHz)
302 printk("%s reg_hs_ths_prepare = 0x%x\n", __func__, val);
303 rk32_dsi_set_bits(dsi, val, reg_hs_ths_prepare + offset);
305 if (offset != DPHY_CLOCK_OFFSET) {
306 if (ddr_clk < 110 * MHz)
308 else if (ddr_clk < 150 * MHz)
310 else if (ddr_clk < 200 * MHz)
312 else if (ddr_clk < 250 * MHz)
314 else if (ddr_clk < 300 * MHz)
316 else if (ddr_clk < 400 * MHz)
318 else if (ddr_clk < 500 * MHz)
320 else if (ddr_clk < 600 * MHz)
322 else if (ddr_clk < 700 * MHz)
324 else if (ddr_clk < 800 * MHz)
326 else if (ddr_clk <= 1000 * MHz)
329 if (ddr_clk < 110 * MHz)
331 else if (ddr_clk < 150 * MHz)
333 else if (ddr_clk < 200 * MHz)
335 else if (ddr_clk < 250 * MHz)
337 else if (ddr_clk < 300 * MHz)
339 else if (ddr_clk < 400 * MHz)
341 else if (ddr_clk < 500 * MHz)
343 else if (ddr_clk < 600 * MHz)
345 else if (ddr_clk < 700 * MHz)
347 else if (ddr_clk < 800 * MHz)
349 else if (ddr_clk <= 1000 * MHz)
352 printk("%s reg_hs_the_zero = 0x%x\n", __func__, val);
353 rk32_dsi_set_bits(dsi, val, reg_hs_the_zero + offset);
355 if (ddr_clk < 110 * MHz)
357 else if (ddr_clk < 150 * MHz)
359 else if (ddr_clk < 200 * MHz)
361 else if (ddr_clk < 250 * MHz)
363 else if (ddr_clk < 300 * MHz)
365 else if (ddr_clk < 400 * MHz)
367 else if (ddr_clk < 500 * MHz)
369 else if (ddr_clk < 600 * MHz)
371 else if (ddr_clk < 700 * MHz)
373 else if (ddr_clk < 800 * MHz)
375 else if (ddr_clk <= 1000 * MHz)
376 val = 0x21; /* 0x27 */
378 printk("%s reg_hs_ths_trail = 0x%x\n", __func__, val);
380 rk32_dsi_set_bits(dsi, val, reg_hs_ths_trail + offset);
381 val = 120000 / Ttxbyte_clk + 1;
382 MIPI_DBG("reg_hs_ths_exit: %d, %d\n", val, val*Ttxbyte_clk/1000);
383 rk32_dsi_set_bits(dsi, val, reg_hs_ths_exit + offset);
385 if (offset == DPHY_CLOCK_OFFSET) {
386 val = (60000 + 52*dsi->phy.UI) / Ttxbyte_clk + 1;
387 MIPI_DBG("reg_hs_tclk_post: %d, %d\n", val, val*Ttxbyte_clk/1000);
388 rk32_dsi_set_bits(dsi, val, reg_hs_tclk_post + offset);
389 val = 10*dsi->phy.UI / Ttxbyte_clk + 1;
390 MIPI_DBG("reg_hs_tclk_pre: %d, %d\n", val, val*Ttxbyte_clk/1000);
391 rk32_dsi_set_bits(dsi, val, reg_hs_tclk_pre + offset);
394 val = 1010000000 / Tsys_clk + 1;
395 MIPI_DBG("reg_hs_twakup: %d, %d\n", val, val*Tsys_clk/1000);
398 MIPI_DBG("val is too large, 0x3ff is the largest\n");
400 temp = (val >> 8) & 0x03;
402 rk32_dsi_set_bits(dsi, temp, reg_hs_twakup_h + offset);
403 rk32_dsi_set_bits(dsi, val, reg_hs_twakup_l + offset);
405 if (Ttxclkesc > 50000) {
407 MIPI_DBG("Ttxclkesc:%d\n", Ttxclkesc);
409 val = val / Ttxbyte_clk;
410 Tlpx = val*Ttxbyte_clk;
411 MIPI_DBG("reg_hs_tlpx: %d, %d\n", val, Tlpx);
413 rk32_dsi_set_bits(dsi, val, reg_hs_tlpx + offset);
416 val = 4*Tlpx / Ttxclkesc;
417 MIPI_DBG("reg_hs_tta_go: %d, %d\n", val, val*Ttxclkesc);
418 rk32_dsi_set_bits(dsi, val, reg_hs_tta_go + offset);
419 val = 3 * Tlpx / 2 / Ttxclkesc;
420 MIPI_DBG("reg_hs_tta_sure: %d, %d\n", val, val*Ttxclkesc);
421 rk32_dsi_set_bits(dsi, val, reg_hs_tta_sure + offset);
422 val = 5 * Tlpx / Ttxclkesc;
423 MIPI_DBG("reg_hs_tta_wait: %d, %d\n", val, val*Ttxclkesc);
424 rk32_dsi_set_bits(dsi, val, reg_hs_tta_wait + offset);
428 static void rk312x_mipi_dsi_set_hs_clk(struct dsi *dsi)
430 rk32_dsi_set_bits(dsi, dsi->phy.prediv, reg_prediv);
431 rk32_dsi_set_bits(dsi, dsi->phy.fbdiv & 0xff, reg_fbdiv);
432 rk32_dsi_set_bits(dsi, (dsi->phy.fbdiv >> 8) & 0x01, reg_fbdiv_8);
435 static int rk312x_phy_power_up(struct dsi *dsi)
437 /* enable ref clock */
438 rk312x_mipi_dsi_set_hs_clk(dsi);
439 clk_prepare_enable(dsi->phy.refclk);
440 clk_prepare_enable(dsi->dsi_pclk);
441 clk_prepare_enable(dsi->dsi_host_pclk);
442 if (dsi->ops.id == DWC_DSI_VERSION_RK312x) {
443 clk_prepare_enable(dsi->h2p_hclk);
444 clk_prepare_enable(dsi->dsi_pd);
449 rk32_dsi_set_bits(dsi, 0xe4, DPHY_REGISTER1);
450 switch (dsi->host.lane) {
452 rk32_dsi_set_bits(dsi, 1, lane_en_3);
454 rk32_dsi_set_bits(dsi, 1, lane_en_2);
456 rk32_dsi_set_bits(dsi, 1, lane_en_1);
458 rk32_dsi_set_bits(dsi, 1, lane_en_0);
459 rk32_dsi_set_bits(dsi, 1, lane_en_ck);
465 rk32_dsi_set_bits(dsi, 0xe0, DPHY_REGISTER1);
468 rk32_dsi_set_bits(dsi, 0x1e, DPHY_REGISTER20);
469 rk32_dsi_set_bits(dsi, 0x1f, DPHY_REGISTER20);
471 rk32_dsi_set_bits(dsi, 1, phy_enableclk);
476 static int rk_phy_power_up(struct dsi *dsi)
478 if (dsi->ops.id == DWC_DSI_VERSION)
479 rk32_phy_power_up(dsi);
480 else if (dsi->ops.id == DWC_DSI_VERSION_RK312x ||
481 dsi->ops.id == DWC_DSI_VERSION_RK3368)
482 rk312x_phy_power_up(dsi);
486 static int rk32_phy_power_down(struct dsi *dsi)
488 rk32_dsi_set_bits(dsi, 0, phy_shutdownz);
489 clk_disable_unprepare(dsi->phy.refclk);
490 clk_disable_unprepare(dsi->dsi_pclk);
491 clk_disable_unprepare(dsi->dsi_pd);
495 static int rk312x_phy_power_down(struct dsi *dsi)
497 rk32_dsi_set_bits(dsi, 0x01, DPHY_REGISTER0);
498 rk32_dsi_set_bits(dsi, 0xe3, DPHY_REGISTER1);
500 clk_disable_unprepare(dsi->phy.refclk);
501 clk_disable_unprepare(dsi->dsi_pclk);
502 clk_disable_unprepare(dsi->dsi_host_pclk);
503 if (dsi->ops.id == DWC_DSI_VERSION_RK312x) {
504 clk_disable_unprepare(dsi->h2p_hclk);
505 clk_disable_unprepare(dsi->dsi_pd);
510 static int rk_phy_power_down(struct dsi *dsi)
512 if (dsi->ops.id == DWC_DSI_VERSION)
513 rk32_phy_power_down(dsi);
514 else if (dsi->ops.id == DWC_DSI_VERSION_RK312x ||
515 dsi->ops.id == DWC_DSI_VERSION_RK3368)
516 rk312x_phy_power_down(dsi);
520 static int rk32_phy_init(struct dsi *dsi)
522 u32 val = 0 , ddr_clk = 0, fbdiv = 0, prediv = 0;
523 unsigned char test_data[2] = {0};
525 ddr_clk = dsi->phy.ddr_clk;
526 prediv = dsi->phy.prediv;
527 fbdiv = dsi->phy.fbdiv;
529 if (ddr_clk < 200 * MHz)
531 else if (ddr_clk < 300 * MHz)
533 else if (ddr_clk < 500 * MHz)
535 else if (ddr_clk < 700 * MHz)
537 else if (ddr_clk < 900 * MHz)
539 else if (ddr_clk < 1100 * MHz)
541 else if (ddr_clk < 1300 * MHz)
543 else if (ddr_clk <= 1500 * MHz)
546 test_data[0] = 0x80 | val << 3 | 0x3;
547 rk32_dwc_phy_test_wr(dsi, 0x10, test_data, 1);
550 rk32_dwc_phy_test_wr(dsi, 0x11, test_data, 1);
552 test_data[0] = 0x80 | 0x40;
553 rk32_dwc_phy_test_wr(dsi, 0x12, test_data, 1);
555 if (ddr_clk < 90 * MHz)
557 else if (ddr_clk < 100 * MHz)
559 else if (ddr_clk < 110 * MHz)
561 else if (ddr_clk < 130 * MHz)
563 else if (ddr_clk < 140 * MHz)
565 else if (ddr_clk < 150 * MHz)
567 else if (ddr_clk < 170 * MHz)
569 else if (ddr_clk < 180 * MHz)
571 else if (ddr_clk < 200 * MHz)
573 else if (ddr_clk < 220 * MHz)
575 else if (ddr_clk < 240 * MHz)
577 else if (ddr_clk < 250 * MHz)
579 else if (ddr_clk < 270 * MHz)
581 else if (ddr_clk < 300 * MHz)
583 else if (ddr_clk < 330 * MHz)
585 else if (ddr_clk < 360 * MHz)
587 else if (ddr_clk < 400 * MHz)
589 else if (ddr_clk < 450 * MHz)
591 else if (ddr_clk < 500 * MHz)
593 else if (ddr_clk < 550 * MHz)
595 else if (ddr_clk < 600 * MHz)
597 else if (ddr_clk < 650 * MHz)
599 else if (ddr_clk < 700 * MHz)
601 else if (ddr_clk < 750 * MHz)
603 else if (ddr_clk < 800 * MHz)
605 else if (ddr_clk < 850 * MHz)
607 else if (ddr_clk < 900 * MHz)
609 else if (ddr_clk < 950 * MHz)
611 else if (ddr_clk < 1000 * MHz)
613 else if (ddr_clk < 1050 * MHz)
615 else if (ddr_clk < 1100 * MHz)
617 else if (ddr_clk < 1150 * MHz)
619 else if (ddr_clk < 1200 * MHz)
621 else if (ddr_clk < 1250 * MHz)
623 else if (ddr_clk < 1300 * MHz)
625 else if (ddr_clk < 1350 * MHz)
627 else if (ddr_clk < 1400 * MHz)
629 else if (ddr_clk < 1450 * MHz)
631 else if (ddr_clk <= 1500 * MHz)
634 test_data[0] = val << 1;
635 rk32_dwc_phy_test_wr(dsi, code_hs_rx_lane0, test_data, 1);
637 test_data[0] = prediv - 1;
638 rk32_dwc_phy_test_wr(dsi, code_pll_input_div_rat, test_data, 1);
640 test_data[0] = (fbdiv - 1) & 0x1f;
641 rk32_dwc_phy_test_wr(dsi, code_pll_loop_div_rat, test_data, 1);
643 test_data[0] = (fbdiv - 1) >> 5 | 0x80;
644 rk32_dwc_phy_test_wr(dsi, code_pll_loop_div_rat, test_data, 1);
647 rk32_dwc_phy_test_wr(dsi, code_pll_input_loop_div_rat, test_data, 1);
651 rk32_dwc_phy_test_wr(dsi, 0x20, test_data, 1);
654 rk32_dwc_phy_test_wr(dsi, 0x21, test_data, 1);
657 rk32_dwc_phy_test_wr(dsi, 0x21, test_data, 1);
660 rk32_dwc_phy_test_wr(dsi, 0x22, test_data, 1);
662 test_data[0] = 0x80 | 0x7;
663 rk32_dwc_phy_test_wr(dsi, 0x22, test_data, 1);
665 test_data[0] = 0x80 | 15;
666 rk32_dwc_phy_test_wr(dsi, code_hstxdatalanerequsetstatetime, test_data, 1);
668 test_data[0] = 0x80 | 85;
669 rk32_dwc_phy_test_wr(dsi, code_hstxdatalanepreparestatetime, test_data, 1);
671 test_data[0] = 0x40 | 10;
672 rk32_dwc_phy_test_wr(dsi, code_hstxdatalanehszerostatetime, test_data, 1);
677 static int rk312x_phy_init(struct dsi *dsi, int n)
680 rk32_dsi_set_bits(dsi, 0x11, DSI_DPHY_BITS(0x06<<2, 32, 0));
681 rk32_dsi_set_bits(dsi, 0x11, DSI_DPHY_BITS(0x07<<2, 32, 0));
682 rk32_dsi_set_bits(dsi, 0xcc, DSI_DPHY_BITS(0x09<<2, 32, 0));
684 dsi_set_bits(0x4e, DSI_DPHY_BITS(0x08<<2, 32, 0));
685 dsi_set_bits(0x84, DSI_DPHY_BITS(0x0a<<2, 32, 0));
688 /*reg1[4] 0: enable a function of "pll phase for serial data being captured
691 we disable it here because reg5[6:4] is not compatible with the HS speed.
694 if (dsi->phy.ddr_clk >= 800*MHz) {
695 rk32_dsi_set_bits(dsi, 0x30, DSI_DPHY_BITS(0x05<<2, 32, 0));
697 rk32_dsi_set_bits(dsi, 1, reg_da_ppfc);
700 switch (dsi->host.lane) {
702 rk312x_mipi_dsi_phy_set_gotp(dsi, DPHY_LANE3_OFFSET, n);
704 rk312x_mipi_dsi_phy_set_gotp(dsi, DPHY_LANE2_OFFSET, n);
706 rk312x_mipi_dsi_phy_set_gotp(dsi, DPHY_LANE1_OFFSET, n);
708 rk312x_mipi_dsi_phy_set_gotp(dsi, DPHY_LANE0_OFFSET, n);
709 rk312x_mipi_dsi_phy_set_gotp(dsi, DPHY_CLOCK_OFFSET, n);
715 rk32_dsi_set_bits(dsi, 0x00e4, reg1_phy);
716 rk32_dsi_set_bits(dsi, 0x007d, reg0_phy);
718 rk32_dsi_set_bits(dsi, 0x00e0, reg1_phy);
719 rk32_dsi_set_bits(dsi, 0x001e, reg20_phy);
721 rk32_dsi_set_bits(dsi, 0x001f, reg20_phy);
723 rk32_dsi_set_bits(dsi, 0x0063, reg10_phy);
726 rk32_dsi_set_bits(dsi, 0x06, reg5_phy);
727 rk32_dsi_set_bits(dsi, 0x6, reg10_4_6_phy);
728 rk32_dsi_set_bits(dsi, 0x9, regb_phy);
733 static int rk_phy_init(struct dsi *dsi)
735 if (dsi->ops.id == DWC_DSI_VERSION)
737 else if (dsi->ops.id == DWC_DSI_VERSION_RK312x ||
738 dsi->ops.id == DWC_DSI_VERSION_RK3368)
739 rk312x_phy_init(dsi, 4);
743 static int rk32_mipi_dsi_host_power_up(struct dsi *dsi)
748 /* disable all interrupt */
749 rk32_dsi_set_bits(dsi, 0x1fffff, INT_MKS0);
750 rk32_dsi_set_bits(dsi, 0x3ffff, INT_MKS1);
752 rk32_mipi_dsi_is_enable(dsi, 1);
755 while (!rk32_dsi_get_bits(dsi, phylock) && val--) {
761 MIPI_TRACE("%s:phylock fail.\n", __func__);
765 while (!rk32_dsi_get_bits(dsi, phystopstateclklane) && val--) {
772 static int rk32_mipi_dsi_host_power_down(struct dsi *dsi)
774 rk32_mipi_dsi_enable_video_mode(dsi, 0);
775 rk32_mipi_dsi_enable_hs_clk(dsi, 0);
776 rk32_mipi_dsi_is_enable(dsi, 0);
780 static int rk32_mipi_dsi_host_init(struct dsi *dsi)
782 u32 val = 0, bytes_px = 0;
783 struct mipi_dsi_screen *screen = &dsi->screen;
784 u32 decimals = dsi->phy.Ttxbyte_clk, temp = 0, i = 0;
785 u32 m = 1, lane = dsi->host.lane, Tpclk = dsi->phy.Tpclk,
786 Ttxbyte_clk = dsi->phy.Ttxbyte_clk;
788 rk32_dsi_set_bits(dsi, dsi->host.lane - 1, n_lanes);
789 rk32_dsi_set_bits(dsi, dsi->vid, dpi_vcid);
791 switch (screen->face) {
793 rk32_dsi_set_bits(dsi, 5, dpi_color_coding);
798 rk32_dsi_set_bits(dsi, 3, dpi_color_coding);
799 rk32_dsi_set_bits(dsi, 1, en18_loosely);
803 rk32_dsi_set_bits(dsi, 0, dpi_color_coding);
808 if (dsi->ops.id == DWC_DSI_VERSION ||
809 dsi->ops.id == DWC_DSI_VERSION_RK3368) {
810 rk32_dsi_set_bits(dsi, 1, hsync_active_low);
811 rk32_dsi_set_bits(dsi, 1, vsync_active_low);
813 rk32_dsi_set_bits(dsi, 0, dataen_active_low);
814 rk32_dsi_set_bits(dsi, 0, colorm_active_low);
815 rk32_dsi_set_bits(dsi, 0, shutd_active_low);
816 } else if (dsi->ops.id == DWC_DSI_VERSION_RK312x) {
817 rk32_dsi_set_bits(dsi, !screen->pin_hsync, hsync_active_low);
818 rk32_dsi_set_bits(dsi, !screen->pin_vsync, vsync_active_low);
820 rk32_dsi_set_bits(dsi, screen->pin_den, dataen_active_low);
821 rk32_dsi_set_bits(dsi, 1, colorm_active_low);
822 rk32_dsi_set_bits(dsi, 1, shutd_active_low);
825 rk32_dsi_set_bits(dsi, dsi->host.video_mode, vid_mode_type); /* burst mode */
827 switch (dsi->host.video_mode) {
829 if (screen->type == SCREEN_DUAL_MIPI)
830 rk32_dsi_set_bits(dsi, screen->x_res / 2 + 4, vid_pkt_size);
832 rk32_dsi_set_bits(dsi, screen->x_res, vid_pkt_size);
836 for (i = 8; i < 32; i++) {
837 temp = i * lane * Tpclk % Ttxbyte_clk;
838 if (decimals > temp) {
846 rk32_dsi_set_bits(dsi, screen->x_res / m + 1, num_chunks);
847 rk32_dsi_set_bits(dsi, m, vid_pkt_size);
848 temp = m * lane * Tpclk / Ttxbyte_clk - m * bytes_px;
849 MIPI_DBG("%s:%d, %d\n", __func__, m, temp);
852 rk32_dsi_set_bits(dsi, temp - 12, null_pkt_size);
858 /* rk32_dsi_set_bits(dsi, 0, CMD_MODE_CFG << 16); */
859 if (screen->type == SCREEN_MIPI) {
860 rk32_dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->x_res + screen->left_margin +
861 screen->hsync_len + screen->right_margin) \
862 / dsi->phy.Ttxbyte_clk, vid_hline_time);
863 } else { /* used for dual mipi screen */
864 rk32_dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->x_res + 8 + screen->left_margin +
865 screen->hsync_len + screen->right_margin) \
866 / dsi->phy.Ttxbyte_clk, vid_hline_time);
868 MIPI_DBG("dsi->phy.Tpclk = %d\n", dsi->phy.Tpclk);
869 MIPI_DBG("screen->left_margin = %d\n", screen->left_margin);
870 MIPI_DBG("dsi->phy.Ttxbyte_clk = %d\n", dsi->phy.Ttxbyte_clk);
871 MIPI_DBG("screen->hsync_len = %d\n", screen->hsync_len);
872 rk32_dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->left_margin) / dsi->phy.Ttxbyte_clk,
874 rk32_dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->hsync_len) / dsi->phy.Ttxbyte_clk,
877 rk32_dsi_set_bits(dsi, screen->y_res , vid_active_lines);
878 rk32_dsi_set_bits(dsi, screen->lower_margin, vid_vfp_lines);
879 rk32_dsi_set_bits(dsi, screen->upper_margin, vid_vbp_lines);
880 rk32_dsi_set_bits(dsi, screen->vsync_len, vid_vsa_lines);
882 dsi->phy.txclkesc = 20 * MHz;
883 val = dsi->phy.txbyte_clk / dsi->phy.txclkesc + 1;
884 dsi->phy.txclkesc = dsi->phy.txbyte_clk / val;
885 rk32_dsi_set_bits(dsi, val, TX_ESC_CLK_DIVISION);
887 rk32_dsi_set_bits(dsi, 10, TO_CLK_DIVISION);
888 rk32_dsi_set_bits(dsi, 1000, hstx_to_cnt); /* no sure */
889 rk32_dsi_set_bits(dsi, 1000, lprx_to_cnt);
890 rk32_dsi_set_bits(dsi, 100, phy_stop_wait_time);
892 /* enable send command in low power mode */
893 rk32_dsi_set_bits(dsi, 4, outvact_lpcmd_time);
894 rk32_dsi_set_bits(dsi, 4, invact_lpcmd_time);
895 rk32_dsi_set_bits(dsi, 1, lp_cmd_en);
897 rk32_dsi_set_bits(dsi, 20, phy_hs2lp_time);
898 rk32_dsi_set_bits(dsi, 16, phy_lp2hs_time);
900 rk32_dsi_set_bits(dsi, 87, phy_hs2lp_time_clk_lane);
901 rk32_dsi_set_bits(dsi, 25, phy_hs2hs_time_clk_lane);
903 rk32_dsi_set_bits(dsi, 10000, max_rd_time);
905 rk32_dsi_set_bits(dsi, 1, lp_hfp_en);
906 /* rk32_dsi_set_bits(dsi, 1, lp_hbp_en); */
907 rk32_dsi_set_bits(dsi, 1, lp_vact_en);
908 rk32_dsi_set_bits(dsi, 1, lp_vfp_en);
909 rk32_dsi_set_bits(dsi, 1, lp_vbp_en);
910 rk32_dsi_set_bits(dsi, 1, lp_vsa_en);
912 /* rk32_dsi_set_bits(dsi, 1, frame_bta_ack_en); */
913 rk32_dsi_set_bits(dsi, 1, phy_enableclk);
914 rk32_dsi_set_bits(dsi, 0, phy_tx_triggers);
916 /* enable non-continued function */
917 /* rk32_dsi_set_bits(dsi, 1, auto_clklane_ctrl); */
919 rk32_dsi_set_bits(dsi, 1, phy_txexitulpslan);
920 rk32_dsi_set_bits(dsi, 1, phy_txexitulpsclk);
926 * mipi protocol layer definition
928 static int rk_mipi_dsi_init(void *arg, u32 n)
930 u32 decimals = 1000, i = 0, pre = 0;
931 struct dsi *dsi = arg;
932 struct mipi_dsi_screen *screen = &dsi->screen;
937 if ((screen->type != SCREEN_MIPI) && (screen->type != SCREEN_DUAL_MIPI)) {
938 MIPI_TRACE("only mipi dsi lcd is supported!\n");
942 if (((screen->type == SCREEN_DUAL_MIPI) && (rk_mipi_get_dsi_num() == 1)) || ((screen->type == SCREEN_MIPI) && (rk_mipi_get_dsi_num() == 2))) {
943 MIPI_TRACE("dsi number and mipi type not match!\n");
947 dsi->phy.Tpclk = rk_fb_get_prmry_screen_pixclock();
950 dsi->phy.ref_clk = clk_get_rate(dsi->phy.refclk) ;
951 if (dsi->ops.id == DWC_DSI_VERSION_RK312x ||
952 dsi->ops.id == DWC_DSI_VERSION_RK3368)
953 dsi->phy.ref_clk = dsi->phy.ref_clk / 2; /* 1/2 of input refclk */
955 dsi->phy.sys_clk = dsi->phy.ref_clk;
957 printk("dsi->phy.sys_clk =%d\n", dsi->phy.sys_clk);
958 if (dsi->ops.id == DWC_DSI_VERSION) {
959 if ((screen->hs_tx_clk <= 90 * MHz) || (screen->hs_tx_clk >= 1500 * MHz))
960 dsi->phy.ddr_clk = 1500 * MHz; /* default is 1.5HGz */
962 dsi->phy.ddr_clk = screen->hs_tx_clk;
963 } else if (dsi->ops.id == DWC_DSI_VERSION_RK312x ||
964 dsi->ops.id == DWC_DSI_VERSION_RK3368) {
965 if ((screen->hs_tx_clk <= 80 * MHz) || (screen->hs_tx_clk >= 1000 * MHz))
966 dsi->phy.ddr_clk = 1000 * MHz; /* default is 1GHz */
968 dsi->phy.ddr_clk = screen->hs_tx_clk;
972 dsi->phy.ddr_clk = n;
974 decimals = dsi->phy.ref_clk;
975 for (i = 1; i < 6; i++) {
976 pre = dsi->phy.ref_clk / i;
977 if ((decimals > (dsi->phy.ddr_clk % pre)) && (dsi->phy.ddr_clk / pre < 512)) {
978 decimals = dsi->phy.ddr_clk % pre;
980 dsi->phy.fbdiv = dsi->phy.ddr_clk / pre;
986 MIPI_DBG("prediv:%d, fbdiv:%d,dsi->phy.ddr_clk:%d\n", dsi->phy.prediv, dsi->phy.fbdiv, dsi->phy.ref_clk / dsi->phy.prediv * dsi->phy.fbdiv);
988 dsi->phy.ddr_clk = dsi->phy.ref_clk / dsi->phy.prediv * dsi->phy.fbdiv;
990 MIPI_DBG("dsi->phy.ddr_clk =%d\n", dsi->phy.ddr_clk);
991 dsi->phy.txbyte_clk = dsi->phy.ddr_clk / 8;
993 dsi->phy.txclkesc = 20 * MHz; /* < 20MHz */
994 dsi->phy.txclkesc = dsi->phy.txbyte_clk / (dsi->phy.txbyte_clk / dsi->phy.txclkesc + 1);
996 dsi->phy.pclk = div_u64(1000000000000llu, dsi->phy.Tpclk);
997 dsi->phy.Ttxclkesc = div_u64(1000000000000llu, dsi->phy.txclkesc);
998 dsi->phy.Tsys_clk = div_u64(1000000000000llu, dsi->phy.sys_clk);
999 dsi->phy.Tddr_clk = div_u64(1000000000000llu, dsi->phy.ddr_clk);
1000 dsi->phy.Ttxbyte_clk = div_u64(1000000000000llu, dsi->phy.txbyte_clk);
1002 dsi->phy.UI = dsi->phy.Tddr_clk;
1005 if (screen->dsi_lane > 0 && screen->dsi_lane <= 4)
1006 dsi->host.lane = screen->dsi_lane;
1010 dsi->host.video_mode = VM_BM;
1012 MIPI_DBG("UI:%d\n", dsi->phy.UI);
1013 MIPI_DBG("ref_clk:%d\n", dsi->phy.ref_clk);
1014 MIPI_DBG("pclk:%d, Tpclk:%d\n", dsi->phy.pclk, dsi->phy.Tpclk);
1015 MIPI_DBG("sys_clk:%d, Tsys_clk:%d\n", dsi->phy.sys_clk, dsi->phy.Tsys_clk);
1016 MIPI_DBG("ddr_clk:%d, Tddr_clk:%d\n", dsi->phy.ddr_clk, dsi->phy.Tddr_clk);
1017 MIPI_DBG("txbyte_clk:%d, Ttxbyte_clk:%d\n", dsi->phy.txbyte_clk,
1018 dsi->phy.Ttxbyte_clk);
1019 MIPI_DBG("txclkesc:%d, Ttxclkesc:%d\n", dsi->phy.txclkesc, dsi->phy.Ttxclkesc);
1022 rk_phy_power_up(dsi);
1023 rk32_mipi_dsi_host_power_up(dsi);
1025 rk32_mipi_dsi_host_init(dsi);
1030 static int rk32_mipi_dsi_is_enable(void *arg, u32 enable)
1032 struct dsi *dsi = arg;
1034 rk32_dsi_set_bits(dsi, enable, shutdownz);
1038 static int rk32_mipi_dsi_enable_video_mode(void *arg, u32 enable)
1040 struct dsi *dsi = arg;
1042 rk32_dsi_set_bits(dsi, !enable, cmd_video_mode);
1046 static int rk32_mipi_dsi_enable_command_mode(void *arg, u32 enable)
1048 struct dsi *dsi = arg;
1050 rk32_dsi_set_bits(dsi, enable, cmd_video_mode);
1054 static int rk32_mipi_dsi_enable_hs_clk(void *arg, u32 enable)
1056 struct dsi *dsi = arg;
1058 rk32_dsi_set_bits(dsi, enable, phy_txrequestclkhs);
1062 static int rk32_mipi_dsi_is_active(void *arg)
1064 struct dsi *dsi = arg;
1066 return rk32_dsi_get_bits(dsi, shutdownz);
1069 static int rk32_mipi_dsi_send_packet(void *arg, unsigned char cmds[], u32 length)
1071 struct dsi *dsi = arg;
1072 unsigned char *regs;
1073 u32 type, liTmp = 0, i = 0, j = 0, data = 0;
1075 if (rk32_dsi_get_bits(dsi, gen_cmd_full) == 1) {
1076 MIPI_TRACE("gen_cmd_full\n");
1079 regs = kmalloc(0x400, GFP_KERNEL);
1081 printk("request regs fail!\n");
1084 memcpy(regs, cmds, length);
1090 case DTYPE_DCS_SWRITE_0P:
1091 rk32_dsi_set_bits(dsi, regs[0], dcs_sw_0p_tx);
1092 data = regs[2] << 8 | type;
1094 case DTYPE_DCS_SWRITE_1P:
1095 rk32_dsi_set_bits(dsi, regs[0], dcs_sw_1p_tx);
1096 data = regs[2] << 8 | type;
1097 data |= regs[3] << 16;
1099 case DTYPE_DCS_LWRITE:
1100 rk32_dsi_set_bits(dsi, regs[0], dcs_lw_tx);
1101 for (i = 0; i < liTmp; i++) {
1102 regs[i] = regs[i+2];
1104 for (i = 0; i < liTmp; i++) {
1106 data |= regs[i] << (j * 8);
1107 if (j == 3 || ((i + 1) == liTmp)) {
1108 if (rk32_dsi_get_bits(dsi, gen_pld_w_full) == 1) {
1109 MIPI_TRACE("gen_pld_w_full :%d\n", i);
1112 rk32_dsi_set_bits(dsi, data, GEN_PLD_DATA);
1113 MIPI_DBG("write GEN_PLD_DATA:%d, %08x\n", i, data);
1118 data |= (liTmp & 0xffff) << 8;
1120 case DTYPE_GEN_LWRITE:
1121 rk32_dsi_set_bits(dsi, regs[0], gen_lw_tx);
1122 for (i = 0; i < liTmp; i++) {
1123 regs[i] = regs[i+2];
1125 for (i = 0; i < liTmp; i++) {
1127 data |= regs[i] << (j * 8);
1128 if (j == 3 || ((i + 1) == liTmp)) {
1129 if (rk32_dsi_get_bits(dsi, gen_pld_w_full) == 1) {
1130 MIPI_TRACE("gen_pld_w_full :%d\n", i);
1133 rk32_dsi_set_bits(dsi, data, GEN_PLD_DATA);
1134 MIPI_DBG("write GEN_PLD_DATA:%d, %08x\n", i, data);
1138 data = (dsi->vid << 6) | type;
1139 data |= (liTmp & 0xffff) << 8;
1141 case DTYPE_GEN_SWRITE_2P: /* one command and one parameter */
1142 rk32_dsi_set_bits(dsi, regs[0], gen_sw_2p_tx);
1144 /* It is used for normal Generic Short WRITE Packet with 2 parameters. */
1146 data |= regs[2] << 8; /* dcs command */
1147 data |= regs[3] << 16; /* parameter of command */
1151 /* The below is used for Generic Short WRITE Packet with 2 parameters
1152 * that more than 2 parameters. Though it is illegal dcs command, we can't
1153 * make sure the users do not send that command.
1155 for (i = 0; i < liTmp; i++) {
1156 regs[i] = regs[i+2];
1158 for (i = 0; i < liTmp; i++) {
1160 data |= regs[i] << (j * 8);
1161 if (j == 3 || ((i + 1) == liTmp)) {
1162 if (rk32_dsi_get_bits(dsi, gen_pld_w_full) == 1) {
1163 MIPI_TRACE("gen_pld_w_full :%d\n", i);
1166 rk32_dsi_set_bits(dsi, data, GEN_PLD_DATA);
1167 MIPI_DBG("write GEN_PLD_DATA:%d, %08x\n", i, data);
1172 data |= (liTmp & 0xffff) << 8;
1174 case DTYPE_GEN_SWRITE_1P: /* one command without parameter */
1175 rk32_dsi_set_bits(dsi, regs[0], gen_sw_1p_tx);
1177 data |= regs[2] << 8;
1179 case DTYPE_GEN_SWRITE_0P: /* nop packet without command and parameter */
1180 rk32_dsi_set_bits(dsi, regs[0], gen_sw_0p_tx);
1184 printk("0x%x:this type not suppport!\n", type);
1187 MIPI_DBG("%d command sent in %s size:%d\n", __LINE__, regs[0] ? "LP mode" : "HS mode", liTmp);
1189 MIPI_DBG("write GEN_HDR:%08x\n", data);
1190 rk32_dsi_set_bits(dsi, data, GEN_HDR);
1193 while (!rk32_dsi_get_bits(dsi, gen_cmd_empty) && i--) {
1202 static int rk32_mipi_dsi_read_dcs_packet(void *arg, unsigned char *data1, u32 n)
1204 struct dsi *dsi = arg;
1205 unsigned char regs[2];
1212 rk32_dsi_set_bits(dsi, regs[0], dcs_sr_0p_tx);
1214 if(type == DTYPE_GEN_SWRITE_0P)
1215 data = (dsi->vid << 6) | (n << 4) | type;
1217 data = (dsi->vid << 6) | ((n-1) << 4) | type;
1220 data |= regs[1] << 8 | type;
1222 printk("write GEN_HDR:%08x\n", data);
1224 rk32_dsi_set_bits(dsi, 0xFFFF, bta_to_cnt);
1225 rk32_dsi_set_bits(dsi, 1, bta_en);
1226 rk32_dsi_set_bits(dsi, data, GEN_HDR);
1229 printk("rk32_mipi_dsi_read_dcs_packet==0x%x\n", rk32_dsi_get_bits(dsi, GEN_PLD_DATA));
1230 rk32_dsi_set_bits(dsi, 0, bta_en);
1235 static int rk32_mipi_dsi_power_up(void *arg)
1237 struct dsi *dsi = arg;
1239 rk32_phy_power_up(dsi);
1240 rk32_mipi_dsi_host_power_up(dsi);
1244 static int rk32_mipi_dsi_power_down(void *arg)
1246 struct dsi *dsi = arg;
1247 struct mipi_dsi_screen *screen = &dsi->screen;
1252 rk32_mipi_dsi_host_power_down(dsi);
1253 rk_phy_power_down(dsi);
1255 MIPI_TRACE("%s:%d\n", __func__, __LINE__);
1259 static int rk32_mipi_dsi_get_id(void *arg)
1262 struct dsi *dsi = arg;
1264 id = rk32_dsi_get_bits(dsi, VERSION);
1268 /* the most top level of mipi dsi init */
1269 static int rk_mipi_dsi_probe(struct dsi *dsi)
1273 register_dsi_ops(dsi->dsi_id, &dsi->ops);
1274 ret = dsi_probe_current_chip(dsi->dsi_id);
1276 MIPI_TRACE("mipi dsi probe fail\n");
1282 #ifdef MIPI_DSI_REGISTER_IO
1283 #include <linux/proc_fs.h>
1284 #include <asm/uaccess.h>
1285 #include <linux/slab.h>
1287 int reg_proc_write(struct file *file, const char __user *buff, size_t count, loff_t *offp)
1289 int ret = -1, i = 0;
1291 char *buf = kmalloc(count, GFP_KERNEL);
1296 memset(buf, 0, count);
1297 ret = copy_from_user((void *)buf, buff, count);
1298 data = strstr(data, "-");
1300 goto reg_proc_write_exit;
1301 command = *(++data);
1305 data = strstr(data, "0x");
1307 goto reg_proc_write_exit;
1308 sscanf(data, "0x%llx", ®s_val);
1309 if ((regs_val & 0xffff00000000ULL) == 0)
1310 goto reg_proc_write_exit;
1311 read_val = regs_val & 0xffffffff;
1312 printk("regs_val=0x%llx\n", regs_val);
1313 rk32_dsi_write_reg(dsi0, regs_val >> 32, &read_val);
1314 rk32_dsi_read_reg(dsi0, regs_val >> 32, &read_val);
1315 regs_val &= 0xffffffff;
1316 if (read_val != regs_val)
1317 MIPI_TRACE("%s fail:0x%08x\n", __func__, read_val);
1323 data = strstr(data, "0x");
1325 goto reg_proc_write_exit;
1327 sscanf(data, "0x%llx", ®s_val);
1328 rk32_dsi_read_reg(dsi0, (u16)regs_val, &read_val);
1329 MIPI_TRACE("*%04x : %08x\n", (u16)regs_val, read_val);
1333 while (*(++data) == ' ')
1335 sscanf(data, "%d", &read_val);
1337 read_val = 11289600;
1344 while (*(++data) == ' ')
1347 MIPI_TRACE("****%d:%d\n", data-buf, count);
1350 MIPI_TRACE("payload entry is larger than 32\n");
1353 sscanf(data, "%x,", (unsigned int *)(str + i)); /* -c 1,29,02,03,05,06,> pro */
1354 data = strstr(data, ",");
1365 rk32_mipi_dsi_send_packet(dsi0, str, read_val);
1367 rk32_mipi_dsi_send_packet(dsi0, str, read_val);
1378 reg_proc_write_exit:
1384 int reg_proc_read(struct seq_file *s, void *v)
1388 struct dsi *dsi = s->private;
1390 for (i = VERSION; i < (VERSION + (0xdc << 16)); i += 4<<16) {
1391 val = rk32_dsi_get_bits(dsi, i);
1392 seq_printf(s, "%04x: %08x\n", i>>16, val);
1396 static int reg_proc_open(struct inode *inode, struct file *file)
1398 struct dsi *dsi = inode->i_private;
1400 return single_open(file, reg_proc_read, dsi);
1403 int reg_proc_close(struct inode *inode, struct file *file)
1408 struct file_operations reg_proc_fops = {
1409 .owner = THIS_MODULE,
1410 .open = reg_proc_open,
1411 .release = reg_proc_close,
1412 .write = reg_proc_write,
1416 int reg_proc_write1(struct file *file, const char __user *buff, size_t count, loff_t *offp)
1418 int ret = -1, i = 0;
1420 char *buf = kmalloc(count, GFP_KERNEL);
1425 memset(buf, 0, count);
1426 ret = copy_from_user((void *)buf, buff, count);
1428 data = strstr(data, "-");
1430 goto reg_proc_write_exit;
1431 command = *(++data);
1436 data = strstr(data, "0x");
1438 goto reg_proc_write_exit;
1439 sscanf(data, "0x%llx", ®s_val);
1440 if ((regs_val & 0xffff00000000ULL) == 0)
1441 goto reg_proc_write_exit;
1442 read_val = regs_val & 0xffffffff;
1443 rk32_dsi_write_reg(dsi1, regs_val >> 32, &read_val);
1444 rk32_dsi_read_reg(dsi1, regs_val >> 32, &read_val);
1445 regs_val &= 0xffffffff;
1446 if (read_val != regs_val)
1447 MIPI_TRACE("%s fail:0x%08x\n", __func__, read_val);
1453 data = strstr(data, "0x");
1455 goto reg_proc_write_exit;
1456 sscanf(data, "0x%llx", ®s_val);
1457 rk32_dsi_read_reg(dsi1, (u16)regs_val, &read_val);
1458 MIPI_TRACE("*%04x : %08x\n", (u16)regs_val, read_val);
1462 while (*(++data) == ' ')
1464 sscanf(data, "%d", &read_val);
1466 read_val = 11289600;
1473 while (*(++data) == ' ')
1476 MIPI_TRACE("****%d:%d\n", data-buf, count);
1479 MIPI_TRACE("payload entry is larger than 32\n");
1482 sscanf(data, "%x,", (unsigned int *)(str + i)); /* -c 1,29,02,03,05,06,> pro */
1483 data = strstr(data, ",");
1494 rk32_mipi_dsi_send_packet(dsi1, str, read_val);
1496 rk32_mipi_dsi_send_packet(dsi1, str, read_val);
1507 reg_proc_write_exit:
1513 int reg_proc_close1(struct inode *inode, struct file *file)
1518 struct file_operations reg_proc_fops1 = {
1519 .owner = THIS_MODULE,
1520 .open = reg_proc_open,
1521 .release = reg_proc_close1,
1522 .write = reg_proc_write1,
1526 #if 0/* def CONFIG_MIPI_DSI_LINUX */
1527 static irqreturn_t rk32_mipi_dsi_irq_handler(int irq, void *data)
1529 printk("-------rk32_mipi_dsi_irq_handler-------\n");
1535 static int dwc_phy_test_rd(struct dsi *dsi, unsigned char test_code)
1539 rk32_dsi_set_bits(dsi, 0x10000 | test_code, PHY_TEST_CTRL1);
1540 rk32_dsi_set_bits(dsi, 0x2, PHY_TEST_CTRL0);
1541 rk32_dsi_set_bits(dsi, 0x0, PHY_TEST_CTRL0);
1543 val = rk32_dsi_get_bits(dsi, PHY_TEST_CTRL1);
1547 static int rk32_dsi_enable(void)
1549 MIPI_DBG("rk32_dsi_enable-------\n");
1550 rk_fb_get_prmry_screen(dsi0->screen.screen);
1551 dsi0->screen.lcdc_id = dsi0->screen.screen->lcdc_id;
1552 rk32_init_phy_mode(dsi0->screen.lcdc_id);
1555 if (rk_mipi_get_dsi_num() == 2)
1558 rk_mipi_screen_standby(0);
1561 After the core reset, DPI waits for the first VSYNC active transition to start signal sampling, including
1562 pixel data, and preventing image transmission in the middle of a frame.
1564 dsi_is_enable(0, 0);
1565 if (rk_mipi_get_dsi_num() == 2)
1566 dsi_is_enable(1, 0);
1568 dsi_enable_video_mode(0, 1);
1569 if (rk_mipi_get_dsi_num() == 2)
1570 dsi_enable_video_mode(1, 1);
1572 dsi_is_enable(0, 1);
1573 if (rk_mipi_get_dsi_num() == 2)
1574 dsi_is_enable(1, 1);
1578 #ifdef CONFIG_MIPI_DSI_LINUX
1579 static int rk32_dsi_disable(void)
1581 MIPI_DBG("rk32_dsi_disable-------\n");
1582 rk_mipi_screen_standby(1);
1584 if (rk_mipi_get_dsi_num() == 2)
1589 static struct rk_fb_trsm_ops trsm_dsi_ops = {
1590 .enable = rk32_dsi_enable,
1591 .disable = rk32_dsi_disable,
1592 .dsp_pwr_on = rk32_mipi_power_up_DDR,
1593 .dsp_pwr_off = rk32_mipi_power_down_DDR,
1596 static void rk32_init_phy_mode(int lcdc_id)
1598 int val0 = 0, val1 = 0;
1600 MIPI_DBG("rk32_init_phy_mode----------lcdc_id=%d\n", lcdc_id);
1602 /* Only the rk3288 VOP need setting the VOP output. */
1603 if (dsi0->ops.id != DWC_DSI_VERSION)
1606 /* D-PHY mode select */
1607 if (rk_mipi_get_dsi_num() == 1) {
1609 /* 1'b1: VOP LIT output to DSI host0;1'b0: VOP BIG output to DSI host0 */
1610 val0 = 0x1 << 22 | 0x1 << 6;
1612 val0 = 0x1 << 22 | 0x0 << 6;
1613 writel_relaxed(val0, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
1616 val0 = 0x1 << 25 | 0x1 << 9 | 0x1 << 22 | 0x1 << 6;
1617 val1 = 0x1 << 31 | 0x1 << 30 | 0x0 << 15 | 0x1 << 14;
1619 val0 = 0x1 << 25 | 0x0 << 9 | 0x1 << 22 | 0x0 << 14;
1620 val1 = 0x1 << 31 | 0x1 << 30 | 0x0 << 15 | 0x1 << 14;
1622 writel_relaxed(val0, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
1623 writel_relaxed(val1, RK_GRF_VIRT + RK3288_GRF_SOC_CON14);
1627 #ifdef CONFIG_MIPI_DSI_LINUX
1628 static int rk32_mipi_power_down_DDR(void)
1630 dsi_is_enable(0, 0);
1631 if (rk_mipi_get_dsi_num() == 2)
1632 dsi_is_enable(1, 0);
1636 static int rk32_mipi_power_up_DDR(void)
1638 dsi_is_enable(0, 0);
1639 if (rk_mipi_get_dsi_num() == 2)
1640 dsi_is_enable(1, 0);
1641 dsi_enable_video_mode(0, 1);
1642 dsi_enable_video_mode(1, 1);
1643 dsi_is_enable(0, 1);
1644 if (rk_mipi_get_dsi_num() == 2)
1645 dsi_is_enable(1, 1);
1654 static struct dsi_type dsi_rk312x = {
1655 .label = "rk312-dsi",
1656 .dsi_id = DWC_DSI_VERSION_RK312x,
1659 static struct dsi_type dsi_rk32 = {
1660 .label = "rk32-dsi",
1661 .dsi_id = DWC_DSI_VERSION,
1664 static struct dsi_type dsi_rk3368 = {
1665 .label = "rk3368-dsi",
1666 .dsi_id = DWC_DSI_VERSION_RK3368,
1669 static const struct of_device_id of_rk_mipi_dsi_match[] = {
1670 { .compatible = "rockchip,rk32-dsi", .data = &dsi_rk32},
1671 { .compatible = "rockchip,rk312x-dsi", .data = &dsi_rk312x},
1672 { .compatible = "rockchip,rk3368-dsi", .data = &dsi_rk3368},
1676 static int rk32_mipi_dsi_probe(struct platform_device *pdev)
1681 struct mipi_dsi_ops *ops;
1682 struct rk_screen *screen;
1683 struct mipi_dsi_screen *dsi_screen;
1684 struct resource *res_host, *res_phy;
1685 const struct dsi_type *data;
1686 const struct of_device_id *of_id =
1687 of_match_device(of_rk_mipi_dsi_match, &pdev->dev);
1689 dev_err(&pdev->dev, "failed to match device\n");
1694 dsi = devm_kzalloc(&pdev->dev, sizeof(struct dsi), GFP_KERNEL);
1696 dev_err(&pdev->dev, "request struct dsi fail!\n");
1699 dsi->ops.id = data->dsi_id;
1700 printk(KERN_INFO "%s\n", data->label);
1701 if (dsi->ops.id == DWC_DSI_VERSION) {
1702 res_host = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1703 dsi->host.membase = devm_request_and_ioremap(&pdev->dev, res_host);
1704 if (!dsi->host.membase) {
1705 dev_err(&pdev->dev, "get resource mipi host membase fail!\n");
1708 } else if (dsi->ops.id == DWC_DSI_VERSION_RK312x ||
1709 dsi->ops.id == DWC_DSI_VERSION_RK3368) {
1710 res_host = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mipi_dsi_host");
1711 dsi->host.membase = devm_request_and_ioremap(&pdev->dev, res_host);
1712 if (!dsi->host.membase) {
1713 dev_err(&pdev->dev, "get resource mipi host membase fail!\n");
1716 res_phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mipi_dsi_phy");
1717 dsi->phy.membase = devm_request_and_ioremap(&pdev->dev, res_phy);
1718 if (!dsi->phy.membase) {
1719 dev_err(&pdev->dev, "get resource mipi phy membase fail!\n");
1724 dsi->phy.refclk = devm_clk_get(&pdev->dev, "clk_mipi_24m");
1725 if (unlikely(IS_ERR(dsi->phy.refclk))) {
1726 dev_err(&pdev->dev, "get clk_mipi_24m clock fail\n");
1727 return PTR_ERR(dsi->phy.refclk);
1730 /* Get the APB bus clk access mipi phy */
1731 dsi->dsi_pclk = devm_clk_get(&pdev->dev, "pclk_mipi_dsi");
1732 if (unlikely(IS_ERR(dsi->dsi_pclk))) {
1733 dev_err(&pdev->dev, "get pclk_mipi_dsi clock fail\n");
1734 return PTR_ERR(dsi->dsi_pclk);
1737 if (dsi->ops.id == DWC_DSI_VERSION_RK3368) {
1738 /* Get the APB bus clk access mipi host */
1739 dsi->dsi_host_pclk = devm_clk_get(&pdev->dev, "pclk_mipi_dsi_host");
1740 if (unlikely(IS_ERR(dsi->dsi_host_pclk))) {
1741 dev_err(&pdev->dev, "get pclk_mipi_dsi_host clock fail\n");
1742 return PTR_ERR(dsi->dsi_host_pclk);
1746 if (dsi->ops.id == DWC_DSI_VERSION_RK312x) {
1747 /* Get the APB bus clk access mipi host */
1748 dsi->dsi_host_pclk = devm_clk_get(&pdev->dev, "pclk_mipi_dsi_host");
1749 if (unlikely(IS_ERR(dsi->dsi_host_pclk))) {
1750 dev_err(&pdev->dev, "get pclk_mipi_dsi_host clock fail\n");
1751 return PTR_ERR(dsi->dsi_host_pclk);
1753 /* Get the pd_vio AHB h2p bridge clock */
1754 dsi->h2p_hclk = devm_clk_get(&pdev->dev, "hclk_vio_h2p");
1755 if (unlikely(IS_ERR(dsi->h2p_hclk))) {
1756 dev_err(&pdev->dev, "get hclk_vio_h2p clock fail\n");
1757 return PTR_ERR(dsi->h2p_hclk);
1760 dsi->dsi_pd = devm_clk_get(&pdev->dev, "pd_mipi_dsi");
1761 if (unlikely(IS_ERR(dsi->dsi_pd))) {
1762 dev_err(&pdev->dev, "get pd_mipi_dsi clock fail\n");
1763 return PTR_ERR(dsi->dsi_pd);
1767 if (dsi->ops.id == DWC_DSI_VERSION) {
1768 dsi->dsi_pd = devm_clk_get(&pdev->dev, "pd_mipi_dsi");
1769 if (unlikely(IS_ERR(dsi->dsi_pd))) {
1770 dev_err(&pdev->dev, "get pd_mipi_dsi clock fail\n");
1771 return PTR_ERR(dsi->dsi_pd);
1774 dsi->host.irq = platform_get_irq(pdev, 0);
1775 if (dsi->host.irq < 0) {
1776 dev_err(&pdev->dev, "no irq resource?\n");
1777 return dsi->host.irq;
1780 ret = request_irq(dsi->host.irq, rk32_mipi_dsi_irq_handler, 0,dev_name(&pdev->dev), dsi);
1782 dev_err(&pdev->dev, "request mipi_dsi irq fail\n");
1786 printk("dsi->host.irq =%d\n", dsi->host.irq);
1788 disable_irq(dsi->host.irq);
1790 screen = devm_kzalloc(&pdev->dev, sizeof(struct rk_screen), GFP_KERNEL);
1792 dev_err(&pdev->dev, "request struct rk_screen fail!\n");
1795 rk_fb_get_prmry_screen(screen);
1801 ops->get_id = rk32_mipi_dsi_get_id,
1802 ops->dsi_send_packet = rk32_mipi_dsi_send_packet;
1803 ops->dsi_read_dcs_packet = rk32_mipi_dsi_read_dcs_packet,
1804 ops->dsi_enable_video_mode = rk32_mipi_dsi_enable_video_mode,
1805 ops->dsi_enable_command_mode = rk32_mipi_dsi_enable_command_mode,
1806 ops->dsi_enable_hs_clk = rk32_mipi_dsi_enable_hs_clk,
1807 ops->dsi_is_active = rk32_mipi_dsi_is_active,
1808 ops->dsi_is_enable = rk32_mipi_dsi_is_enable,
1809 ops->power_up = rk32_mipi_dsi_power_up,
1810 ops->power_down = rk32_mipi_dsi_power_down,
1811 ops->dsi_init = rk_mipi_dsi_init,
1813 dsi_screen = &dsi->screen;
1814 dsi_screen->screen = screen;
1815 dsi_screen->type = screen->type;
1816 dsi_screen->face = screen->face;
1817 dsi_screen->lcdc_id = screen->lcdc_id;
1818 dsi_screen->screen_id = screen->screen_id;
1819 dsi_screen->pixclock = screen->mode.pixclock;
1820 dsi_screen->left_margin = screen->mode.left_margin;
1821 dsi_screen->right_margin = screen->mode.right_margin;
1822 dsi_screen->hsync_len = screen->mode.hsync_len;
1823 dsi_screen->upper_margin = screen->mode.upper_margin;
1824 dsi_screen->lower_margin = screen->mode.lower_margin;
1825 dsi_screen->vsync_len = screen->mode.vsync_len;
1826 dsi_screen->x_res = screen->mode.xres;
1827 dsi_screen->y_res = screen->mode.yres;
1828 dsi_screen->pin_hsync = screen->pin_hsync;
1829 dsi_screen->pin_vsync = screen->pin_vsync;
1830 dsi_screen->pin_den = screen->pin_den;
1831 dsi_screen->pin_dclk = screen->pin_dclk;
1832 dsi_screen->dsi_lane = rk_mipi_get_dsi_lane();
1833 /* dsi_screen->dsi_video_mode = screen->dsi_video_mode; */
1834 dsi_screen->dsi_lane = rk_mipi_get_dsi_lane();
1835 dsi_screen->hs_tx_clk = rk_mipi_get_dsi_clk();
1836 /* dsi_screen->lcdc_id = 1; */
1840 sprintf(ops->name, "rk_mipi_dsi.%d", dsi->dsi_id);
1841 platform_set_drvdata(pdev, dsi);
1843 ret = rk_mipi_dsi_probe(dsi);
1845 dev_err(&pdev->dev, "rk mipi_dsi probe fail!\n");
1846 dev_err(&pdev->dev, "%s\n", RK_MIPI_DSI_VERSION_AND_TIME);
1852 if(!support_uboot_display())
1853 rk32_init_phy_mode(dsi_screen->lcdc_id);
1855 rk_fb_trsm_ops_register(&trsm_dsi_ops, SCREEN_MIPI);
1856 #ifdef MIPI_DSI_REGISTER_IO
1857 debugfs_create_file("mipidsi0", S_IFREG | S_IRUGO, dsi->debugfs_dir, dsi,
1863 #ifdef MIPI_DSI_REGISTER_IO
1864 debugfs_create_file("mipidsi1", S_IFREG | S_IRUGO, dsi->debugfs_dir, dsi,
1869 if (support_uboot_display()) {
1870 clk_prepare_enable(dsi->phy.refclk);
1871 clk_prepare_enable(dsi->dsi_pclk);
1872 if (dsi->ops.id == DWC_DSI_VERSION_RK312x) {
1873 clk_prepare_enable(dsi->dsi_host_pclk);
1874 clk_prepare_enable(dsi->h2p_hclk);
1876 clk_prepare_enable(dsi->dsi_pd);
1879 dev_info(&pdev->dev, "rk mipi_dsi probe success!\n");
1880 dev_info(&pdev->dev, "%s\n", RK_MIPI_DSI_VERSION_AND_TIME);
1885 static struct platform_driver rk32_mipi_dsi_driver = {
1886 .probe = rk32_mipi_dsi_probe,
1888 .name = "rk32-mipi",
1889 .owner = THIS_MODULE,
1891 .of_match_table = of_rk_mipi_dsi_match,
1896 static int __init rk32_mipi_dsi_init(void)
1898 return platform_driver_register(&rk32_mipi_dsi_driver);
1900 fs_initcall(rk32_mipi_dsi_init);
1902 static void __exit rk32_mipi_dsi_exit(void)
1904 platform_driver_unregister(&rk32_mipi_dsi_driver);
1906 module_exit(rk32_mipi_dsi_exit);