drivers/video/rockchip/transmitter/rk32_mipi_dsi.c

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  * drivers/video/display/transmitter/rk32_mipi_dsi.c
   4  * author: libing@rock-chips.com
   5  * create date: 2014-04-10
   6  * debug /sys/kernel/debug/mipidsi*
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 //config
  18 #ifndef CONFIG_RK32_MIPI_DSI
  19 #include <common.h>
  20 #endif
  21
  22 #ifdef CONFIG_RK32_MIPI_DSI
  23 #define MIPI_DSI_REGISTER_IO    0
  24 #define CONFIG_MIPI_DSI_LINUX   0
  25 #endif
  26 #define DWC_DSI_VERSION                 0x3133302A
  27
  28 #ifdef CONFIG_RK_3288_DSI_UBOOT
  29 #include <asm/io.h>
  30 #include <errno.h>
  31 #include <lcd.h>
  32 #include <div64.h>
  33 #include <linux/ctype.h>
  34 #include <linux/math64.h>
  35 #include "mipi_dsi.h"
  36 #include "rk32_mipi_dsi.h"
  37 #include "mipi_dsi.h"
  38 #include <asm/arch/rkplat.h>
  39 #include <fdtdec.h>
  40 #include <linux/fb.h>
  41 #include <linux/rk_screen.h>
  42 #include <malloc.h>
  43 #else
  44 #include <linux/kernel.h>
  45 #include <linux/init.h>
  46 #include <linux/platform_device.h>
  47 #include <linux/slab.h>
  48 #include <linux/rk_fb.h>
  49 #include <linux/rk_screen.h>
  50 #include <linux/delay.h>
  51 #include <linux/clk.h>
  52 #include <linux/interrupt.h>
  53 #include <asm/div64.h>
  54
  55 #include <linux/fs.h>
  56 #include <linux/debugfs.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/regulator/machine.h>
  59
  60 #include <linux/dma-mapping.h>
  61 #include "mipi_dsi.h"
  62 #include "rk32_mipi_dsi.h"
  63 #include <linux/rockchip/iomap.h>
  64 #endif
  65 #ifdef CONFIG_RK32_MIPI_DSI
  66 #define MIPI_DBG(x...)  //printk(KERN_INFO x)
  67 #elif defined CONFIG_RK_3288_DSI_UBOOT
  68 #define MIPI_DBG(x...)  //printf( x)
  69 #define printk(x...)    //printf( x)
  70 #else
  71 #define MIPI_DBG(x...)
  72 #endif
  73
  74 #ifdef CONFIG_MIPI_DSI_LINUX
  75 #define MIPI_TRACE(x...)        //printk(KERN_INFO x)
  76 #else
  77 #define MIPI_TRACE(...)    \
  78         do\
  79         {\
  80                 printf(__VA_ARGS__);\
  81                 printf("\n");\
  82         }while(0);
  83
  84 #endif
  85
  86 /*
  87 *                        Driver Version Note
  88 *
  89 *v1.0 : this driver is rk32 mipi dsi driver of rockchip;
  90 *v1.1 : add test eye pattern;
  91 *
  92 */
  93
  94 #define RK_MIPI_DSI_VERSION_AND_TIME  "rockchip mipi_dsi v1.1 2014-06-17"
  95
  96 static struct dsi *dsi0;
  97 static struct dsi *dsi1;
  98
  99 static int rk32_mipi_dsi_is_active(void *arg);
 100 static int rk32_mipi_dsi_enable_hs_clk(void *arg, u32 enable);
 101 static int rk32_mipi_dsi_enable_video_mode(void *arg, u32 enable);
 102 static int rk32_mipi_dsi_enable_command_mode(void *arg, u32 enable);
 103 static int rk32_mipi_dsi_is_enable(void *arg, u32 enable);
 104 static int rk32_mipi_power_down_DDR();
 105 static int rk32_mipi_power_up_DDR();
 106 int rk_mipi_screen_standby(u8 enable);
 107
 108 #ifdef CONFIG_RK_3288_DSI_UBOOT
 109 DECLARE_GLOBAL_DATA_PTR;
 110 extern int rk_mipi_screen_probe(void);
 111 extern void writel_relaxed(uint32 val, uint32 addr);
 112 #define msleep(a) udelay(a * 1000)
 113 /*
 114 dsihost0:
 115 clocks = <&clk_gates5 15>, <&clk_gates16 4>;
 116 clock-names = "clk_mipi_24m", "pclk_mipi_dsi";
 117
 118 dsihost1:
 119 clocks = <&clk_gates5 15>, <&clk_gates16 5>;
 120 clock-names = "clk_mipi_24m", "pclk_mipi_dsi";
 121
 122 */
 123 int rk32_mipi_dsi_clk_enable(struct dsi *dsi)
 124 {
 125         u32 val;
 126         val = 0x80000000;//bit31~bit16
 127         writel(val, RK3288_CRU_PHYS + 0x174); /*24M*/
 128         if(dsi->dsi_id == 0)
 129                 val = (1 << 20);
 130         else
 131                 val = (1 << 21);
 132         writel(val, RK3288_CRU_PHYS + 0x1a0); /*pclk*/
 133         return 0;
 134 }
 135 int rk32_mipi_dsi_clk_disable(struct dsi *dsi)
 136 {
 137         u32 val;
 138         if(dsi->dsi_id == 0)
 139                 val = (1 << 20)|(1 << 4);
 140         else
 141                 val = (1 << 21)|(1 << 5);
 142         writel(val, RK3288_CRU_PHYS + 0x1a0); /*pclk*/
 143
 144         val = 0x80008000;//bit31~bit16
 145         writel(val, RK3288_CRU_PHYS + 0x174); /*24M*/
 146         return 0;
 147 }
 148
 149 #endif
 150 static int rk32_dsi_read_reg(struct dsi *dsi, u16 reg, u32 *pval)
 151 {
 152         *pval = __raw_readl(dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
 153         return 0;
 154 }
 155
 156 static int rk32_dsi_write_reg(struct dsi *dsi, u16 reg, u32 *pval)
 157 {
 158         __raw_writel(*pval, dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
 159         return 0;
 160 }
 161
 162 static int rk32_dsi_get_bits(struct dsi *dsi, u32 reg)
 163 {
 164         u32 val = 0;
 165         u32 bits = (reg >> 8) & 0xff;
 166         u16 reg_addr = (reg >> 16) & 0xffff;
 167         u8 offset = reg & 0xff;
 168
 169         if(bits < 32)
 170                 bits = (1 << bits) - 1;
 171         else
 172                 bits = 0xffffffff;
 173
 174         rk32_dsi_read_reg(dsi, reg_addr, &val);
 175         val >>= offset;
 176         val &= bits;
 177
 178         return val;
 179 }
 180
 181 static int rk32_dsi_set_bits(struct dsi *dsi, u32 data, u32 reg)
 182 {
 183         static u32 val = 0;
 184         u32 bits = (reg >> 8) & 0xff;
 185         u16 reg_addr = (reg >> 16) & 0xffff;
 186         u8 offset = reg & 0xff;
 187
 188         if(bits < 32)
 189                 bits = (1 << bits) - 1;
 190         else
 191                 bits = 0xffffffff;
 192
 193         if(bits != 0xffffffff)
 194                 rk32_dsi_read_reg(dsi, reg_addr, &val);
 195
 196         val &= ~(bits << offset);
 197         val |= (data & bits) << offset;
 198         rk32_dsi_write_reg(dsi, reg_addr, &val);
 199
 200         if(data > bits) {
 201                 MIPI_TRACE("%s error reg_addr:0x%04x, offset:%d, bits:0x%04x, value:0x%04x\n",
 202                                 __func__, reg_addr, offset, bits, data);
 203         }
 204
 205         return 0;
 206 }
 207 #if 0
 208 static int rk32_dwc_phy_test_rd(struct dsi *dsi, unsigned char test_code)
 209 {
 210         int val = 0;
 211         rk32_dsi_set_bits(dsi, 1, phy_testclk);
 212         rk32_dsi_set_bits(dsi, test_code, phy_testdin);
 213         rk32_dsi_set_bits(dsi, 1, phy_testen);
 214         rk32_dsi_set_bits(dsi, 0, phy_testclk);
 215         rk32_dsi_set_bits(dsi, 0, phy_testen);;
 216
 217         rk32_dsi_set_bits(dsi, 0, phy_testen);
 218         val = rk32_dsi_get_bits(dsi,phy_testdout);
 219         rk32_dsi_set_bits(dsi, 1, phy_testclk);
 220         rk32_dsi_set_bits(dsi, 0, phy_testclk);
 221
 222         return val;
 223 }
 224 #endif
 225 static int rk32_dwc_phy_test_wr(struct dsi *dsi, unsigned char test_code, unsigned char *test_data, unsigned char size)
 226 {
 227         int i = 0;
 228
 229         MIPI_DBG("test_code=0x%x,test_data=0x%x\n", test_code,test_data[0]);
 230         rk32_dsi_set_bits(dsi, 0x10000 | test_code, PHY_TEST_CTRL1);
 231         rk32_dsi_set_bits(dsi, 0x2, PHY_TEST_CTRL0);
 232         rk32_dsi_set_bits(dsi, 0x0, PHY_TEST_CTRL0);
 233
 234         for(i = 0; i < size; i++) {
 235                 rk32_dsi_set_bits(dsi, test_data[i], PHY_TEST_CTRL1);
 236                 rk32_dsi_set_bits(dsi, 0x2, PHY_TEST_CTRL0);
 237                 rk32_dsi_set_bits(dsi, 0x0, PHY_TEST_CTRL0);
 238                 MIPI_DBG("rk32_dwc_phy_test_wr:%08x\n", rk32_dsi_get_bits(dsi, PHY_TEST_CTRL1));
 239         }
 240         return 0;
 241 }
 242
 243 static int rk32_phy_power_up(struct dsi *dsi)
 244 {
 245     //enable ref clock
 246     #ifdef CONFIG_RK_3288_DSI_UBOOT
 247     rk32_mipi_dsi_clk_enable(dsi);
 248     #else
 249     clk_prepare_enable(dsi->phy.refclk);
 250     clk_prepare_enable(dsi->dsi_pclk);
 251     clk_prepare_enable(dsi->dsi_pd);
 252     #endif
 253     udelay(10);
 254
 255         switch(dsi->host.lane) {
 256                 case 4:
 257                         rk32_dsi_set_bits(dsi, 3, n_lanes);
 258                         break;
 259                 case 3:
 260                         rk32_dsi_set_bits(dsi, 2, n_lanes);
 261                         break;
 262                 case 2:
 263                         rk32_dsi_set_bits(dsi, 1, n_lanes);
 264                         break;
 265                 case 1:
 266                         rk32_dsi_set_bits(dsi, 0, n_lanes);
 267                         break;
 268                 default:
 269                         break;
 270         }
 271         rk32_dsi_set_bits(dsi, 1, phy_shutdownz);
 272         rk32_dsi_set_bits(dsi, 1, phy_rstz);
 273         rk32_dsi_set_bits(dsi, 1, phy_enableclk);
 274         rk32_dsi_set_bits(dsi, 1, phy_forcepll);
 275
 276         return 0;
 277 }
 278
 279 static int rk32_phy_power_down(struct dsi *dsi)
 280 {
 281     rk32_dsi_set_bits(dsi, 0, phy_shutdownz);
 282     #ifdef CONFIG_RK_3288_DSI_UBOOT
 283     rk32_mipi_dsi_clk_disable(dsi);
 284     #else
 285     clk_disable_unprepare(dsi->phy.refclk);
 286     clk_disable_unprepare(dsi->dsi_pclk);
 287     clk_disable_unprepare(dsi->dsi_pd);
 288     #endif
 289     return 0;
 290 }
 291
 292 static int rk32_phy_init(struct dsi *dsi)
 293 {
 294         u32 val = 0 , ddr_clk = 0, fbdiv = 0, prediv = 0;
 295         unsigned char test_data[2] = {0};
 296
 297         ddr_clk = dsi->phy.ddr_clk;
 298         prediv  = dsi->phy.prediv;
 299         fbdiv   = dsi->phy.fbdiv;
 300
 301         if(ddr_clk < 200 * MHz)
 302                 val = 0x0;
 303         else if(ddr_clk < 300 * MHz)
 304                 val = 0x1;
 305         else if(ddr_clk < 500 * MHz)
 306                 val = 0x2;
 307         else if(ddr_clk < 700 * MHz)
 308                 val = 0x3;
 309         else if(ddr_clk < 900 * MHz)
 310                 val = 0x4;
 311         else if(ddr_clk < 1100 * MHz)
 312                 val = 0x5;
 313         else if(ddr_clk < 1300 * MHz)
 314                 val = 0x6;
 315         else if(ddr_clk <= 1500 * MHz)
 316                 val = 0x7;
 317
 318         test_data[0] = 0x80 | val << 3 | 0x3;
 319         rk32_dwc_phy_test_wr(dsi, 0x10, test_data, 1);
 320
 321         test_data[0] = 0x8;
 322         rk32_dwc_phy_test_wr(dsi, 0x11, test_data, 1);
 323
 324         test_data[0] = 0x80 | 0x40;
 325         rk32_dwc_phy_test_wr(dsi, 0x12, test_data, 1);
 326
 327         if(ddr_clk < 90 * MHz)
 328                 val = 0x01;
 329         else if(ddr_clk < 100 * MHz)
 330                 val = 0x10;
 331         else if(ddr_clk < 110 * MHz)
 332                 val = 0x20;
 333         else if(ddr_clk < 130 * MHz)
 334                 val = 0x01;
 335         else if(ddr_clk < 140 * MHz)
 336                 val = 0x11;
 337         else if(ddr_clk < 150 * MHz)
 338                 val = 0x21;
 339         else if(ddr_clk < 170 * MHz)
 340                 val = 0x02;
 341         else if(ddr_clk < 180 * MHz)
 342                 val = 0x12;
 343         else if(ddr_clk < 200 * MHz)
 344                 val = 0x22;
 345         else if(ddr_clk < 220 * MHz)
 346                 val = 0x03;
 347         else if(ddr_clk < 240 * MHz)
 348                 val = 0x13;
 349         else if(ddr_clk < 250 * MHz)
 350                 val = 0x23;
 351         else if(ddr_clk < 270 * MHz)
 352                 val = 0x04;
 353         else if(ddr_clk < 300 * MHz)
 354                 val = 0x14;
 355         else if(ddr_clk < 330 * MHz)
 356                 val = 0x05;
 357         else if(ddr_clk < 360 * MHz)
 358                 val = 0x15;
 359         else if(ddr_clk < 400 * MHz)
 360                 val = 0x25;
 361         else if(ddr_clk < 450 * MHz)
 362                 val = 0x06;
 363         else if(ddr_clk < 500 * MHz)
 364                 val = 0x16;
 365         else if(ddr_clk < 550 * MHz)
 366                 val = 0x07;
 367         else if(ddr_clk < 600 * MHz)
 368                 val = 0x17;
 369         else if(ddr_clk < 650 * MHz)
 370                 val = 0x08;
 371         else if(ddr_clk < 700 * MHz)
 372                 val = 0x18;
 373         else if(ddr_clk < 750 * MHz)
 374                 val = 0x09;
 375         else if(ddr_clk < 800 * MHz)
 376                 val = 0x19;
 377         else if(ddr_clk < 850 * MHz)
 378                 val = 0x29;
 379         else if(ddr_clk < 900 * MHz)
 380                 val = 0x39;
 381         else if(ddr_clk < 950 * MHz)
 382                 val = 0x0a;
 383         else if(ddr_clk < 1000 * MHz)
 384                 val = 0x1a;
 385         else if(ddr_clk < 1050 * MHz)
 386                 val = 0x2a;
 387         else if(ddr_clk < 1100* MHz)
 388                 val = 0x3a;
 389         else if(ddr_clk < 1150* MHz)
 390                 val = 0x0b;
 391         else if(ddr_clk < 1200 * MHz)
 392                 val = 0x1b;
 393         else if(ddr_clk < 1250 * MHz)
 394                 val = 0x2b;
 395         else if(ddr_clk < 1300 * MHz)
 396                 val = 0x3b;
 397         else if(ddr_clk < 1350 * MHz)
 398                 val = 0x0c;
 399         else if(ddr_clk < 1400* MHz)
 400                 val = 0x1c;
 401         else if(ddr_clk < 1450* MHz)
 402                 val = 0x2c;
 403         else if(ddr_clk <= 1500* MHz)
 404                 val = 0x3c;
 405
 406         test_data[0] = val << 1;
 407         rk32_dwc_phy_test_wr(dsi, code_hs_rx_lane0, test_data, 1);
 408
 409         test_data[0] = prediv- 1;
 410         rk32_dwc_phy_test_wr(dsi, code_pll_input_div_rat, test_data, 1);
 411         mdelay(2);
 412         test_data[0] = (fbdiv - 1) & 0x1f;
 413         rk32_dwc_phy_test_wr(dsi, code_pll_loop_div_rat, test_data, 1);
 414         mdelay(2);
 415         test_data[0] = (fbdiv - 1) >> 5 | 0x80;
 416         rk32_dwc_phy_test_wr(dsi, code_pll_loop_div_rat, test_data, 1);
 417         mdelay(2);
 418         test_data[0] = 0x30;
 419         rk32_dwc_phy_test_wr(dsi, code_pll_input_loop_div_rat, test_data, 1);
 420         mdelay(2);
 421
 422         test_data[0] = 0x4d;
 423         rk32_dwc_phy_test_wr(dsi, 0x20, test_data, 1);
 424
 425         test_data[0] = 0x3d;
 426         rk32_dwc_phy_test_wr(dsi, 0x21, test_data, 1);
 427
 428         test_data[0] = 0xdf;
 429         rk32_dwc_phy_test_wr(dsi, 0x21, test_data, 1);
 430
 431         test_data[0] =  0x7;
 432         rk32_dwc_phy_test_wr(dsi, 0x22, test_data, 1);
 433
 434         test_data[0] = 0x80 | 0x7;
 435         rk32_dwc_phy_test_wr(dsi, 0x22, test_data, 1);
 436
 437         test_data[0] = 0x80 | 15;
 438         rk32_dwc_phy_test_wr(dsi, code_hstxdatalanerequsetstatetime, test_data, 1);
 439
 440         test_data[0] = 0x80 | 85;
 441         rk32_dwc_phy_test_wr(dsi, code_hstxdatalanepreparestatetime, test_data, 1);
 442
 443         test_data[0] = 0x40 | 10;
 444         rk32_dwc_phy_test_wr(dsi, code_hstxdatalanehszerostatetime, test_data, 1);
 445
 446     return 0;
 447 }
 448
 449 static int rk32_mipi_dsi_host_power_up(struct dsi *dsi)
 450 {
 451         int ret = 0;
 452         u32 val;
 453
 454         //disable all interrupt
 455         rk32_dsi_set_bits(dsi, 0x1fffff, INT_MKS0);
 456         rk32_dsi_set_bits(dsi, 0x3ffff, INT_MKS1);
 457
 458         rk32_mipi_dsi_is_enable(dsi, 1);
 459
 460         val = 10;
 461         while(!rk32_dsi_get_bits(dsi, phylock) && val--) {
 462                 udelay(10);
 463         };
 464
 465         if(val == 0) {
 466                 ret = -1;
 467                 MIPI_TRACE("%s:phylock fail.\n", __func__);
 468         }
 469
 470         val = 10;
 471         while(!rk32_dsi_get_bits(dsi, phystopstateclklane) && val--) {
 472                 udelay(10);
 473         };
 474
 475         return ret;
 476 }
 477
 478 static int rk32_mipi_dsi_host_power_down(struct dsi *dsi)
 479 {
 480         rk32_mipi_dsi_enable_video_mode(dsi, 0);
 481         rk32_mipi_dsi_enable_hs_clk(dsi, 0);
 482         rk32_mipi_dsi_is_enable(dsi, 0);
 483         return 0;
 484 }
 485
 486 static int rk32_mipi_dsi_host_init(struct dsi *dsi)
 487 {
 488         u32 val = 0, bytes_px = 0;
 489         struct mipi_dsi_screen *screen = &dsi->screen;
 490         u32 decimals = dsi->phy.Ttxbyte_clk, temp = 0, i = 0;
 491         u32 m = 1, lane = dsi->host.lane, Tpclk = dsi->phy.Tpclk,
 492                         Ttxbyte_clk = dsi->phy.Ttxbyte_clk;
 493
 494         rk32_dsi_set_bits(dsi, dsi->host.lane - 1, n_lanes);
 495         rk32_dsi_set_bits(dsi, dsi->vid, dpi_vcid);
 496
 497         switch(screen->face) {
 498                 case OUT_P888:
 499                         rk32_dsi_set_bits(dsi, 5, dpi_color_coding);
 500                         bytes_px = 3;
 501                         break;
 502
 503                 case OUT_D888_P666:
 504
 505                 case OUT_P666:
 506                         rk32_dsi_set_bits(dsi, 3, dpi_color_coding);
 507                         rk32_dsi_set_bits(dsi, 1, en18_loosely);
 508                         bytes_px = 3;
 509                         break;
 510
 511                 case OUT_P565:
 512                         rk32_dsi_set_bits(dsi, 0, dpi_color_coding);
 513                         bytes_px = 2;
 514
 515                 default:
 516                         break;
 517         }
 518
 519         rk32_dsi_set_bits(dsi, 1, hsync_active_low);
 520         rk32_dsi_set_bits(dsi, 1, vsync_active_low);
 521
 522         rk32_dsi_set_bits(dsi, 0, dataen_active_low);
 523         rk32_dsi_set_bits(dsi, 0, colorm_active_low);
 524         rk32_dsi_set_bits(dsi, 0, shutd_active_low);
 525
 526         rk32_dsi_set_bits(dsi, dsi->host.video_mode, vid_mode_type);      //burst mode
 527
 528         switch(dsi->host.video_mode) {
 529
 530                 case VM_BM:
 531                     if(screen->type == SCREEN_DUAL_MIPI)
 532                             rk32_dsi_set_bits(dsi, screen->x_res / 2 + 4, vid_pkt_size);
 533                          else
 534                             rk32_dsi_set_bits(dsi, screen->x_res, vid_pkt_size);
 535                         break;
 536
 537                 case VM_NBMWSE:
 538
 539                 case VM_NBMWSP:
 540                         for(i = 8; i < 32; i++){
 541                                 temp = i * lane * Tpclk % Ttxbyte_clk;
 542                                 if(decimals > temp) {
 543                                         decimals = temp;
 544                                         m = i;
 545                                 }
 546                                 if(decimals == 0)
 547                                         break;
 548                         }
 549
 550                         rk32_dsi_set_bits(dsi, screen->x_res / m + 1, num_chunks);
 551                         rk32_dsi_set_bits(dsi, m, vid_pkt_size);
 552                         temp = m * lane * Tpclk / Ttxbyte_clk - m * bytes_px;
 553                         MIPI_DBG("%s:%d, %d\n", __func__, m, temp);
 554
 555                         if(temp >= 12)
 556                                 rk32_dsi_set_bits(dsi, temp - 12, null_pkt_size);
 557
 558                         break;
 559
 560                 default:
 561
 562                         break;
 563         }
 564
 565         //rk32_dsi_set_bits(dsi, 0, CMD_MODE_CFG << 16);
 566         if(screen->type == SCREEN_MIPI){
 567                 rk32_dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->x_res + screen->left_margin +
 568                                         screen->hsync_len + screen->right_margin) \
 569                                                 / dsi->phy.Ttxbyte_clk, vid_hline_time);
 570         }
 571         else{
 572                 rk32_dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->x_res + 8 + screen->left_margin +
 573                                         screen->hsync_len + screen->right_margin) \
 574                                                 / dsi->phy.Ttxbyte_clk, vid_hline_time);
 575         }
 576     rk32_dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->left_margin) / dsi->phy.Ttxbyte_clk,
 577                                         vid_hbp_time);
 578         rk32_dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->hsync_len) / dsi->phy.Ttxbyte_clk,
 579                                         vid_hsa_time);
 580
 581         rk32_dsi_set_bits(dsi, screen->y_res , vid_active_lines);
 582         rk32_dsi_set_bits(dsi, screen->lower_margin, vid_vfp_lines);
 583         rk32_dsi_set_bits(dsi, screen->upper_margin, vid_vbp_lines);
 584         rk32_dsi_set_bits(dsi, screen->vsync_len, vid_vsa_lines);
 585
 586         dsi->phy.txclkesc = 20 * MHz;
 587         val = dsi->phy.txbyte_clk / dsi->phy.txclkesc + 1;
 588         dsi->phy.txclkesc = dsi->phy.txbyte_clk / val;
 589         rk32_dsi_set_bits(dsi, val, TX_ESC_CLK_DIVISION);
 590
 591         rk32_dsi_set_bits(dsi, 10, TO_CLK_DIVISION);
 592     rk32_dsi_set_bits(dsi, 1000, hstx_to_cnt); //no sure
 593         rk32_dsi_set_bits(dsi, 1000, lprx_to_cnt);
 594         rk32_dsi_set_bits(dsi, 100, phy_stop_wait_time);
 595
 596         //rk32_dsi_set_bits(dsi, 0, outvact_lpcmd_time);   //byte
 597         //rk32_dsi_set_bits(dsi, 0, invact_lpcmd_time);
 598
 599         rk32_dsi_set_bits(dsi, 20, phy_hs2lp_time);
 600         rk32_dsi_set_bits(dsi, 16, phy_lp2hs_time);
 601
 602         // rk32_dsi_set_bits(dsi, 87, phy_hs2lp_time_clk_lane); //no sure
 603         //  rk32_dsi_set_bits(dsi, 25, phy_hs2hs_time_clk_lane); //no sure
 604
 605         rk32_dsi_set_bits(dsi, 10000, max_rd_time);
 606
 607         rk32_dsi_set_bits(dsi, 1, lp_hfp_en);
 608         //rk32_dsi_set_bits(dsi, 1, lp_hbp_en); //no sure
 609         rk32_dsi_set_bits(dsi, 1, lp_vact_en);
 610         rk32_dsi_set_bits(dsi, 1, lp_vfp_en);
 611         rk32_dsi_set_bits(dsi, 1, lp_vbp_en);
 612         rk32_dsi_set_bits(dsi, 1, lp_vsa_en);
 613
 614         //rk32_dsi_set_bits(dsi, 1, frame_bta_ack_en);
 615         rk32_dsi_set_bits(dsi, 1, phy_enableclk);
 616         rk32_dsi_set_bits(dsi, 0, phy_tx_triggers);
 617         //rk32_dsi_set_bits(dsi, 1, phy_txexitulpslan);
 618         //rk32_dsi_set_bits(dsi, 1, phy_txexitulpsclk);
 619         return 0;
 620 }
 621
 622 /*
 623  *      mipi protocol layer definition
 624  */
 625 static int rk_mipi_dsi_init(void *arg, u32 n)
 626 {
 627         u32 decimals = 1000, i = 0, pre = 0;
 628         struct dsi *dsi = arg;
 629         struct mipi_dsi_screen *screen = &dsi->screen;
 630
 631         if(!screen)
 632                 return -1;
 633
 634         if((screen->type != SCREEN_MIPI) && (screen->type != SCREEN_DUAL_MIPI) ) {
 635                 MIPI_TRACE("only mipi dsi lcd is supported!\n");
 636                 return -1;
 637         }
 638
 639         if(((screen->type == SCREEN_DUAL_MIPI) && (rk_mipi_get_dsi_num() == 1)) ||  ((screen->type == SCREEN_MIPI) && (rk_mipi_get_dsi_num() == 2))){
 640                 MIPI_TRACE("dsi number and mipi type not match!\n");
 641             return -1;
 642     }
 643 #ifdef CONFIG_RK_3288_DSI_UBOOT
 644         dsi->phy.Tpclk = div_u64(1000000000000llu, screen->pixclock);
 645         dsi->phy.ref_clk = 24*MHZ;
 646 #else
 647         dsi->phy.Tpclk = rk_fb_get_prmry_screen_pixclock();
 648
 649         if(dsi->phy.refclk)
 650                 dsi->phy.ref_clk = clk_get_rate(dsi->phy.refclk) ;
 651 #endif
 652         dsi->phy.sys_clk = dsi->phy.ref_clk;
 653
 654         printk("dsi->phy.sys_clk =%d\n",dsi->phy.sys_clk );
 655
 656         if((screen->hs_tx_clk <= 90 * MHz) || (screen->hs_tx_clk >= 1500 * MHz))
 657                 dsi->phy.ddr_clk = 1500 * MHz;    //default is 1.5HGz
 658         else
 659                 dsi->phy.ddr_clk = screen->hs_tx_clk;
 660
 661         if(n != 0)
 662                 dsi->phy.ddr_clk = n;
 663
 664         decimals = dsi->phy.ref_clk;
 665         for(i = 1; i < 6; i++) {
 666                 pre = dsi->phy.ref_clk / i;
 667                 if((decimals > (dsi->phy.ddr_clk % pre)) && (dsi->phy.ddr_clk / pre < 512)) {
 668                         decimals = dsi->phy.ddr_clk % pre;
 669                         dsi->phy.prediv = i;
 670                         dsi->phy.fbdiv = dsi->phy.ddr_clk / pre;
 671                 }
 672                 if(decimals == 0)
 673                         break;
 674         }
 675
 676         MIPI_DBG("prediv:%d, fbdiv:%d,dsi->phy.ddr_clk:%d\n", dsi->phy.prediv, dsi->phy.fbdiv,dsi->phy.ref_clk / dsi->phy.prediv * dsi->phy.fbdiv);
 677
 678         dsi->phy.ddr_clk = dsi->phy.ref_clk / dsi->phy.prediv * dsi->phy.fbdiv;
 679         MIPI_DBG("dsi->phy.ddr_clk =%d\n",dsi->phy.ddr_clk);
 680         dsi->phy.txbyte_clk = dsi->phy.ddr_clk / 8;
 681
 682         dsi->phy.txclkesc = 20 * MHz;        // < 20MHz
 683         dsi->phy.txclkesc = dsi->phy.txbyte_clk / (dsi->phy.txbyte_clk / dsi->phy.txclkesc + 1);
 684
 685         dsi->phy.pclk = div_u64(1000000000000llu, dsi->phy.Tpclk);
 686         dsi->phy.Ttxclkesc = div_u64(1000000000000llu, dsi->phy.txclkesc);
 687         dsi->phy.Tsys_clk = div_u64(1000000000000llu, dsi->phy.sys_clk);
 688         dsi->phy.Tddr_clk = div_u64(1000000000000llu, dsi->phy.ddr_clk);
 689         dsi->phy.Ttxbyte_clk = div_u64(1000000000000llu, dsi->phy.txbyte_clk);
 690
 691         dsi->phy.UI = dsi->phy.Tddr_clk;
 692         dsi->vid = 0;
 693
 694         if(screen->dsi_lane > 0 && screen->dsi_lane <= 4)
 695                 dsi->host.lane = screen->dsi_lane;
 696         else
 697                 dsi->host.lane = 4;
 698
 699         dsi->host.video_mode = VM_BM;
 700
 701         MIPI_DBG("UI:%d\n", dsi->phy.UI);
 702         MIPI_DBG("ref_clk:%d\n", dsi->phy.ref_clk);
 703         MIPI_DBG("pclk:%d, Tpclk:%d\n", dsi->phy.pclk, dsi->phy.Tpclk);
 704         MIPI_DBG("sys_clk:%d, Tsys_clk:%d\n", dsi->phy.sys_clk, dsi->phy.Tsys_clk);
 705         MIPI_DBG("ddr_clk:%d, Tddr_clk:%d\n", dsi->phy.ddr_clk, dsi->phy.Tddr_clk);
 706         MIPI_DBG("txbyte_clk:%d, Ttxbyte_clk:%d\n", dsi->phy.txbyte_clk,
 707                                 dsi->phy.Ttxbyte_clk);
 708         MIPI_DBG("txclkesc:%d, Ttxclkesc:%d\n", dsi->phy.txclkesc, dsi->phy.Ttxclkesc);
 709
 710         rk32_phy_power_up(dsi);
 711         rk32_mipi_dsi_host_power_up(dsi);
 712         rk32_phy_init(dsi);
 713         rk32_mipi_dsi_host_init(dsi);
 714
 715         return 0;
 716 }
 717
 718 static int rk32_mipi_dsi_is_enable(void *arg, u32 enable)
 719 {
 720         struct dsi *dsi = arg;
 721
 722         rk32_dsi_set_bits(dsi, enable, shutdownz);
 723
 724         return 0;
 725 }
 726
 727 static int rk32_mipi_dsi_enable_video_mode(void *arg, u32 enable)
 728 {
 729         struct dsi *dsi = arg;
 730
 731         rk32_dsi_set_bits(dsi, !enable, cmd_video_mode);
 732
 733         return 0;
 734 }
 735
 736 static int rk32_mipi_dsi_enable_command_mode(void *arg, u32 enable)
 737 {
 738         struct dsi *dsi = arg;
 739
 740         rk32_dsi_set_bits(dsi, enable, cmd_video_mode);
 741
 742         return 0;
 743 }
 744
 745 static int rk32_mipi_dsi_enable_hs_clk(void *arg, u32 enable)
 746 {
 747         struct dsi *dsi = arg;
 748
 749         rk32_dsi_set_bits(dsi, enable, phy_txrequestclkhs);
 750         return 0;
 751 }
 752
 753 static int rk32_mipi_dsi_is_active(void *arg)
 754 {
 755         struct dsi *dsi = arg;
 756
 757         return rk32_dsi_get_bits(dsi, shutdownz);
 758 }
 759
 760 static int rk32_mipi_dsi_send_packet(void *arg, unsigned char cmds[], u32 length)
 761 {
 762         struct dsi *dsi = arg;
 763         unsigned char *regs;
 764         u32 type, liTmp = 0, i = 0, j = 0, data = 0;
 765
 766         if(rk32_dsi_get_bits(dsi, gen_cmd_full) == 1) {
 767                 MIPI_TRACE("gen_cmd_full\n");
 768                 return -1;
 769         }
 770 #ifdef CONFIG_MIPI_DSI_LINUX
 771         regs = kmalloc(0x400, GFP_KERNEL);
 772         if(!regs) {
 773                 printk("request regs fail!\n");
 774                 return -ENOMEM;
 775         }
 776 #endif
 777 #ifdef CONFIG_RK_3288_DSI_UBOOT
 778         regs = calloc(1, 0x400);
 779         if(!regs) {
 780                 printf("request regs fail!\n");
 781                 return -ENOMEM;
 782         }
 783 #endif
 784         memcpy(regs,cmds,length);
 785
 786         liTmp   = length - 2;
 787         type    = regs[1];
 788
 789         switch(type)
 790         {
 791                 case DTYPE_DCS_SWRITE_0P:
 792                         rk32_dsi_set_bits(dsi, regs[0], dcs_sw_0p_tx);
 793                         data = regs[2] << 8 | type;
 794                         break;
 795
 796                 case DTYPE_DCS_SWRITE_1P:
 797                         rk32_dsi_set_bits(dsi, regs[0], dcs_sw_1p_tx);
 798                         data = regs[2] << 8 | type;
 799                         data |= regs[3] << 16;
 800                         break;
 801
 802                 case DTYPE_DCS_LWRITE:
 803                         rk32_dsi_set_bits(dsi, regs[0], dcs_lw_tx);
 804
 805                         for(i = 0; i < liTmp; i++){
 806                             regs[i] = regs[i+2];
 807                     }
 808
 809                         for(i = 0; i < liTmp; i++) {
 810                                 j = i % 4;
 811
 812                                 data |= regs[i] << (j * 8);
 813                                 if(j == 3 || ((i + 1) == liTmp)) {
 814                                         if(rk32_dsi_get_bits(dsi, gen_pld_w_full) == 1) {
 815                                                 MIPI_TRACE("gen_pld_w_full :%d\n", i);
 816                                                 break;
 817                                         }
 818
 819                                         rk32_dsi_set_bits(dsi, data, GEN_PLD_DATA);
 820                                         MIPI_DBG("write GEN_PLD_DATA:%d, %08x\n", i, data);
 821                                         data = 0;
 822                                 }
 823                         }
 824
 825                         data = type;
 826                         data |= (liTmp & 0xffff) << 8;
 827
 828                         break;
 829
 830                 case DTYPE_GEN_LWRITE:
 831                         rk32_dsi_set_bits(dsi, regs[0], gen_lw_tx);
 832
 833                         for(i = 0; i < liTmp; i++){
 834                                 regs[i] = regs[i+2];
 835                         }
 836
 837                         for(i = 0; i < liTmp; i++) {
 838                                 j = i % 4;
 839
 840                                 data |= regs[i] << (j * 8);
 841                                 if(j == 3 || ((i + 1) == liTmp)) {
 842                                         if(rk32_dsi_get_bits(dsi, gen_pld_w_full) == 1) {
 843                                                 MIPI_TRACE("gen_pld_w_full :%d\n", i);
 844                                                 break;
 845                                         }
 846
 847                                         rk32_dsi_set_bits(dsi, data, GEN_PLD_DATA);
 848                                         MIPI_DBG("write GEN_PLD_DATA:%d, %08x\n", i, data);
 849                                         data = 0;
 850                                 }
 851                         }
 852
 853                         data = (dsi->vid << 6) | type;
 854                         data |= (liTmp & 0xffff) << 8;
 855                         break;
 856
 857                 case DTYPE_GEN_SWRITE_2P:
 858
 859                         rk32_dsi_set_bits(dsi, regs[0], gen_sw_2p_tx);
 860                         for(i = 0; i < liTmp; i++){
 861                             regs[i] = regs[i+2];
 862                         }
 863
 864                         for(i = 0; i < liTmp; i++) {
 865                                 j = i % 4;
 866                                 data |= regs[i] << (j * 8);
 867                                 if(j == 3 || ((i + 1) == liTmp)) {
 868                                         if(rk32_dsi_get_bits(dsi, gen_pld_w_full) == 1) {
 869                                                 MIPI_TRACE("gen_pld_w_full :%d\n", i);
 870                                                 break;
 871                                         }
 872
 873                                         rk32_dsi_set_bits(dsi, data, GEN_PLD_DATA);
 874                                         MIPI_DBG("write GEN_PLD_DATA:%d, %08x\n", i, data);
 875                                         data = 0;
 876                                 }
 877                         }
 878                         data = type;
 879                         data |= (liTmp & 0xffff) << 8;
 880
 881                         break;
 882
 883                 case DTYPE_GEN_SWRITE_1P:
 884                         rk32_dsi_set_bits(dsi, regs[0], gen_sw_1p_tx);
 885                         data = type;
 886                         data |= regs[2] << 8;
 887                         data |= regs[3] << 16;
 888                         break;
 889
 890                 case DTYPE_GEN_SWRITE_0P:
 891                         rk32_dsi_set_bits(dsi, regs[0], gen_sw_0p_tx);
 892                         data =  type;
 893                         data |= regs[2] << 8;
 894                         break;
 895
 896                 default:
 897                    printk("0x%x:this type not suppport!\n",type);
 898
 899         }
 900
 901         MIPI_DBG("%d command sent in %s size:%d\n", __LINE__, regs[0] ? "LP mode" : "HS mode", liTmp);
 902
 903         MIPI_DBG("write GEN_HDR:%08x\n", data);
 904         rk32_dsi_set_bits(dsi, data, GEN_HDR);
 905
 906         i = 10;
 907         while(!rk32_dsi_get_bits(dsi, gen_cmd_empty) && i--) {
 908                 MIPI_DBG(".");
 909                 udelay(10);
 910         }
 911         udelay(10);
 912 #ifdef CONFIG_MIPI_DSI_LINUX
 913         kfree(regs);
 914 #endif
 915 #ifdef CONFIG_RK_3288_DSI_UBOOT
 916         free(regs);
 917 #endif
 918         return 0;
 919 }
 920
 921 static int rk32_mipi_dsi_read_dcs_packet(void *arg, unsigned char *data1, u32 n)
 922 {
 923         struct dsi *dsi = arg;
 924         //DCS READ
 925         //unsigned char *regs = data;
 926         unsigned char regs[2];
 927         u32 data = 0;
 928         int type = 0x06;
 929         regs[0] = LPDT;
 930         regs[1] = 0x0a;
 931         n = n - 1;
 932
 933
 934         rk32_dsi_set_bits(dsi, regs[0], dcs_sr_0p_tx);
 935
 936         /* if(type == DTYPE_GEN_SWRITE_0P)
 937                 data = (dsi->vid << 6) | (n << 4) | type;
 938         else
 939                 data = (dsi->vid << 6) | ((n-1) << 4) | type;*/
 940
 941         data |= regs[1] << 8 | type;
 942         // if(n == 2)
 943         //    data |= regs[1] << 16;
 944
 945         MIPI_DBG("write GEN_HDR:%08x\n", data);
 946         rk32_dsi_set_bits(dsi, data, GEN_HDR);
 947         msleep(100);
 948
 949         // rk32_dsi_set_bits(dsi, regs[0], gen_sr_0p_tx);
 950
 951         printk("rk32_mipi_dsi_read_dcs_packet==0x%x\n",rk32_dsi_get_bits(dsi, GEN_PLD_DATA));
 952         msleep(100);
 953
 954         //  rk32_dsi_set_bits(dsi, regs[0], max_rd_pkt_size);
 955
 956         msleep(100);
 957         // printk("_____rk32_mipi_dsi_read_dcs_packet==0x%x\n",rk32_dsi_get_bits(dsi, GEN_PLD_DATA));
 958
 959         msleep(100);
 960         return 0;
 961 }
 962
 963 static int rk32_mipi_dsi_power_up(void *arg)
 964 {
 965         struct dsi *dsi = arg;
 966
 967         rk32_phy_power_up(dsi);
 968         rk32_mipi_dsi_host_power_up(dsi);
 969         return 0;
 970 }
 971
 972 static int rk32_mipi_dsi_power_down(void *arg)
 973 {
 974         struct dsi *dsi = arg;
 975         struct mipi_dsi_screen *screen = &dsi->screen;
 976
 977         if(!screen)
 978                 return -1;
 979
 980         rk32_mipi_dsi_host_power_down(dsi);
 981         rk32_phy_power_down(dsi);
 982
 983         MIPI_TRACE("%s:%d\n", __func__, __LINE__);
 984         return 0;
 985 }
 986
 987 static int rk32_mipi_dsi_get_id(void *arg)
 988 {
 989         u32 id = 0;
 990         struct dsi *dsi = arg;
 991
 992         id      = rk32_dsi_get_bits(dsi, VERSION);
 993
 994         return id;
 995 }
 996
 997 /* the most top level of mipi dsi init */
 998 static int rk_mipi_dsi_probe(struct dsi *dsi)
 999 {
1000         int ret = 0;
1001
1002         register_dsi_ops(dsi->dsi_id, &dsi->ops);
1003
1004         ret = dsi_probe_current_chip(dsi->dsi_id);
1005         if(ret) {
1006                 MIPI_TRACE("mipi dsi probe fail\n");
1007                 return -ENODEV;
1008         }
1009
1010         return 0;
1011 }
1012
1013 #ifdef MIPI_DSI_REGISTER_IO
1014 #include <linux/proc_fs.h>
1015 #include <asm/uaccess.h>
1016 #include <linux/slab.h>
1017
1018 int reg_proc_write(struct file *file, const char __user *buff, size_t count, loff_t *offp)
1019 {
1020         int ret = -1, i = 0;
1021         u32 read_val = 0;
1022         char *buf = kmalloc(count, GFP_KERNEL);
1023         char *data = buf;
1024         char str[32];
1025         char command = 0;
1026         u64 regs_val = 0;
1027         memset(buf, 0, count);
1028         ret = copy_from_user((void*)buf, buff, count);
1029         data = strstr(data, "-");
1030         if(data == NULL)
1031                 goto reg_proc_write_exit;
1032         command = *(++data);
1033         switch(command) {
1034                 case 'w':
1035                         while(1) {
1036                                 data = strstr(data, "0x");
1037                                 if(data == NULL)
1038                                         goto reg_proc_write_exit;
1039
1040                                 sscanf(data, "0x%llx", &regs_val);
1041                                 if((regs_val & 0xffff00000000ULL) == 0)
1042                                         goto reg_proc_write_exit;
1043                                 read_val = regs_val & 0xffffffff;
1044                                 printk("regs_val=0x%llx\n",regs_val);
1045                                 rk32_dsi_write_reg(dsi0, regs_val >> 32, &read_val);
1046                                 rk32_dsi_read_reg(dsi0, regs_val >> 32, &read_val);
1047                                 regs_val &= 0xffffffff;
1048                                 if(read_val != regs_val)
1049                                         MIPI_TRACE("%s fail:0x%08x\n", __func__, read_val);
1050                                 data += 3;
1051                                 msleep(1);
1052                         }
1053
1054                         break;
1055                 case 'r':
1056                                 data = strstr(data, "0x");
1057                                 if(data == NULL){
1058                                         goto reg_proc_write_exit;
1059                                 }
1060                                 sscanf(data, "0x%llx", &regs_val);
1061                                 rk32_dsi_read_reg(dsi0, (u16)regs_val, &read_val);
1062                                 MIPI_TRACE("*%04x : %08x\n", (u16)regs_val, read_val);
1063                                 msleep(1);
1064                         break;
1065
1066                 case 's':
1067                                 while(*(++data) == ' ');
1068                                 sscanf(data, "%d", &read_val);
1069                                 if(read_val == 11)
1070                                         read_val = 11289600;
1071                                 else
1072                                         read_val *= MHz;
1073
1074                                 //rk32_mipi_dsi_init_lite(dsi);
1075                         break;
1076                 case 'd':
1077                 case 'g':
1078                 case 'c':
1079                                 while(*(++data) == ' ');
1080                                 i = 0;
1081                                 MIPI_TRACE("****%d:%d\n", data-buf, count);
1082
1083                                 do {
1084                                         if(i > 31) {
1085                                                 MIPI_TRACE("payload entry is larger than 32\n");
1086                                                 break;
1087                                         }
1088                                         sscanf(data, "%x,", (unsigned int *)(str + i));   //-c 1,29,02,03,05,06,> pro
1089                                         data = strstr(data, ",");
1090                                         if(data == NULL)
1091                                                 break;
1092                                         data++;
1093                                         i++;
1094                                 } while(1);
1095                                 read_val = i;
1096
1097                                 i = 2;
1098                                 while(i--) {
1099                                         msleep(10);
1100                                         if(command == 'd')
1101                                                 rk32_mipi_dsi_send_packet(dsi0, str, read_val);
1102                                         else
1103                                                 rk32_mipi_dsi_send_packet(dsi0, str, read_val);
1104                                 }
1105                                 i = 1;
1106                                 while(i--) {
1107                                         msleep(1000);
1108                                 }
1109                         break;
1110
1111                 default:
1112                         break;
1113         }
1114
1115 reg_proc_write_exit:
1116         kfree(buf);
1117         msleep(20);
1118         return count;
1119 }
1120
1121 int reg_proc_read(struct file *file, char __user *buff, size_t count,
1122                                         loff_t *offp)
1123 {
1124         int i = 0;
1125         u32 val = 0;
1126
1127     for(i = VERSION; i < (VERSION + (0xdc<<16)); i += 4<<16) {
1128                 val = rk32_dsi_get_bits(dsi0, i);
1129                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1130                 msleep(1);
1131         }
1132
1133         MIPI_TRACE("\n");
1134
1135         return -1;
1136 }
1137
1138 int reg_proc_open(struct inode *inode, struct file *file)
1139 {
1140         return 0;
1141 }
1142
1143 int reg_proc_close(struct inode *inode, struct file *file)
1144 {
1145         return 0;
1146 }
1147
1148 struct file_operations reg_proc_fops = {
1149         .owner  = THIS_MODULE,
1150         .open   = reg_proc_open,
1151         .release= reg_proc_close,
1152         .write  = reg_proc_write,
1153         .read   = reg_proc_read,
1154 };
1155
1156
1157 int reg_proc_write1(struct file *file, const char __user *buff, size_t count, loff_t *offp)
1158 {
1159         int ret = -1, i = 0;
1160         u32 read_val = 0;
1161         char *buf = kmalloc(count, GFP_KERNEL);
1162         char *data = buf;
1163         char str[32];
1164         char command = 0;
1165         u64 regs_val = 0;
1166         memset(buf, 0, count);
1167         ret = copy_from_user((void*)buf, buff, count);
1168
1169         data = strstr(data, "-");
1170         if(data == NULL)
1171                 goto reg_proc_write_exit;
1172         command = *(++data);
1173
1174         switch(command) {
1175                 case 'w':
1176                         while(1) {
1177
1178                                 data = strstr(data, "0x");
1179                                 if(data == NULL)
1180                                         goto reg_proc_write_exit;
1181                                 sscanf(data, "0x%llx", &regs_val);
1182                                 if((regs_val & 0xffff00000000ULL) == 0)
1183                                         goto reg_proc_write_exit;
1184                                 read_val = regs_val & 0xffffffff;
1185                                 rk32_dsi_write_reg(dsi1, regs_val >> 32, &read_val);
1186                                 rk32_dsi_read_reg(dsi1, regs_val >> 32, &read_val);
1187                                 regs_val &= 0xffffffff;
1188                                 if(read_val != regs_val)
1189                                         MIPI_TRACE("%s fail:0x%08x\n", __func__, read_val);
1190
1191                                 data += 3;
1192                                 msleep(1);
1193                         }
1194
1195                         break;
1196                 case 'r':
1197                                 data = strstr(data, "0x");
1198                                 if(data == NULL)
1199                                         goto reg_proc_write_exit;
1200                                 sscanf(data, "0x%llx", &regs_val);
1201                                 rk32_dsi_read_reg(dsi1, (u16)regs_val, &read_val);
1202                                 MIPI_TRACE("*%04x : %08x\n", (u16)regs_val, read_val);
1203                                 msleep(1);
1204                         break;
1205
1206                 case 's':
1207                                 while(*(++data) == ' ');
1208                                 sscanf(data, "%d", &read_val);
1209                                 if(read_val == 11)
1210                                         read_val = 11289600;
1211                                 else
1212                                         read_val *= MHz;
1213
1214                                 //rk32_mipi_dsi_init_lite(dsi);
1215                         break;
1216                 case 'd':
1217                 case 'g':
1218                 case 'c':
1219                                 while(*(++data) == ' ');
1220                                 i = 0;
1221                                 MIPI_TRACE("****%d:%d\n", data-buf, count);
1222
1223                                 do {
1224                                         if(i > 31) {
1225                                                 MIPI_TRACE("payload entry is larger than 32\n");
1226                                                 break;
1227                                         }
1228                                         sscanf(data, "%x,", (unsigned int *)(str + i));   //-c 1,29,02,03,05,06,> pro
1229                                         data = strstr(data, ",");
1230                                         if(data == NULL)
1231                                                 break;
1232                                         data++;
1233                                         i++;
1234                                 } while(1);
1235                                 read_val = i;
1236
1237                                 i = 2;
1238                                 while(i--) {
1239                                         msleep(10);
1240                                         if(command == 'd')
1241                                                 rk32_mipi_dsi_send_packet(dsi1, str, read_val);
1242                                         else
1243                                                 rk32_mipi_dsi_send_packet(dsi1, str, read_val);
1244                                 }
1245                                 i = 1;
1246                                 while(i--) {
1247                                         msleep(1000);
1248                                 }
1249                         break;
1250
1251                 default:
1252                         break;
1253         }
1254
1255 reg_proc_write_exit:
1256         kfree(buf);
1257         msleep(20);
1258         return count;
1259 }
1260
1261 int reg_proc_read1(struct file *file, char __user *buff, size_t count,
1262                                         loff_t *offp)
1263 {
1264         int i = 0;
1265         u32 val = 0;
1266
1267         for(i = VERSION; i < (VERSION + (0xdc<<16)); i += 4<<16) {
1268                 val = rk32_dsi_get_bits(dsi1, i);
1269                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1270                 msleep(1);
1271         }
1272
1273         MIPI_TRACE("\n");
1274         return -1;
1275 }
1276
1277 int reg_proc_open1(struct inode *inode, struct file *file)
1278 {
1279         return 0;
1280 }
1281
1282 int reg_proc_close1(struct inode *inode, struct file *file)
1283 {
1284         return 0;
1285 }
1286
1287 struct file_operations reg_proc_fops1 = {
1288         .owner  = THIS_MODULE,
1289         .open   = reg_proc_open1,
1290         .release= reg_proc_close1,
1291         .write  = reg_proc_write1,
1292         .read   = reg_proc_read1,
1293 };
1294 #endif
1295 #if 0//def CONFIG_MIPI_DSI_LINUX
1296 static irqreturn_t rk32_mipi_dsi_irq_handler(int irq, void *data)
1297 {
1298         printk("-------rk32_mipi_dsi_irq_handler-------\n");
1299         return IRQ_HANDLED;
1300 }
1301 #endif
1302 #ifdef CONFIG_RK_3288_DSI_UBOOT
1303 int rk32_dsi_sync(void)
1304 {
1305         /*
1306                 After the core reset, DPI waits for the first VSYNC active transition to start signal sampling, including
1307                 pixel data, and preventing image transmission in the middle of a frame.
1308         */
1309     dsi_is_enable(0, 0);
1310     if (rk_mipi_get_dsi_num() ==2)
1311         dsi_is_enable(1, 0);
1312
1313     dsi_enable_video_mode(0, 1);
1314     dsi_enable_video_mode(1, 1);
1315
1316     dsi_is_enable(0, 1);
1317     if (rk_mipi_get_dsi_num() ==2)
1318         dsi_is_enable(1, 1);
1319     return 0;
1320 }
1321
1322 #endif
1323 #if 0
1324 static int dwc_phy_test_rd(struct dsi *dsi, unsigned char test_code)
1325 {
1326     int val = 0;
1327
1328     rk32_dsi_set_bits(dsi, 0x10000 | test_code, PHY_TEST_CTRL1);
1329     rk32_dsi_set_bits(dsi, 0x2, PHY_TEST_CTRL0);
1330     rk32_dsi_set_bits(dsi, 0x0, PHY_TEST_CTRL0);
1331
1332         val = rk32_dsi_get_bits(dsi, PHY_TEST_CTRL1);
1333
1334
1335     return val;
1336 }
1337 #endif
1338 static int rk32_dsi_enable(void)
1339 {
1340         MIPI_DBG("rk32_dsi_enable-------\n");
1341         dsi_init(0, 0);
1342         if (rk_mipi_get_dsi_num() ==2)
1343                 dsi_init(1, 0);
1344
1345         rk_mipi_screen_standby(0);
1346
1347         /*
1348                 After the core reset, DPI waits for the first VSYNC active transition to start signal sampling, including
1349                 pixel data, and preventing image transmission in the middle of a frame.
1350         */
1351         dsi_is_enable(0, 0);
1352         if (rk_mipi_get_dsi_num() ==2)
1353                 dsi_is_enable(1, 0);
1354
1355         dsi_enable_video_mode(0, 1);
1356         dsi_enable_video_mode(1, 1);
1357
1358         dsi_is_enable(0, 1);
1359         if (rk_mipi_get_dsi_num() ==2)
1360                 dsi_is_enable(1, 1);
1361
1362         return 0;
1363 }
1364
1365 #ifdef CONFIG_MIPI_DSI_LINUX
1366 static int rk32_dsi_disable(void)
1367 {
1368         MIPI_DBG("rk32_dsi_disable-------\n");
1369
1370         rk_mipi_screen_standby(1);
1371         dsi_power_off(0);
1372         if (rk_mipi_get_dsi_num() ==2)
1373                 dsi_power_off(1);
1374
1375         return 0;
1376 }
1377
1378 static struct rk_fb_trsm_ops trsm_dsi_ops =
1379 {
1380         .enable = rk32_dsi_enable,
1381         .disable = rk32_dsi_disable,
1382         .dsp_pwr_on = rk32_mipi_power_up_DDR,
1383         .dsp_pwr_off = rk32_mipi_power_down_DDR,
1384 };
1385 #endif
1386 static void rk32_init_phy_mode(int lcdc_id)
1387 {
1388         int val0 = 0, val1 = 0;
1389
1390         MIPI_DBG("rk32_init_phy_mode----------lcdc_id=%d\n",lcdc_id);
1391         //D-PHY mode select
1392         if( rk_mipi_get_dsi_num() ==1 ){
1393
1394                 if(lcdc_id == 1)
1395                         //val0 =0x1 << 25 | 0x1 << 9;
1396                         val0 = 0x1 << 22 | 0x1 << 6;  //1'b1: VOP LIT output to DSI host0;1'b0: VOP BIG output to DSI host0
1397                 else
1398                         val0 = 0x1 << 22 | 0x0 << 6;
1399
1400                 writel_relaxed(val0, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
1401         }
1402         else{
1403                 if(lcdc_id == 1){
1404                         val0 = 0x1 << 25 | 0x1 <<  9 | 0x1 << 22 | 0x1 <<  6;
1405                         val1 = 0x1 << 31 | 0x1 << 30 | 0x0 << 15 | 0x1 << 14;
1406                 }
1407                 else{
1408                         val0 = 0x1 << 25 | 0x0 <<  9 | 0x1 << 22 | 0x0 << 14;
1409                         val1 = 0x1 << 31 | 0x1 << 30 | 0x0 << 15 | 0x1 << 14;
1410                 }
1411
1412                 writel_relaxed(val0, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
1413                 writel_relaxed(val1, RK_GRF_VIRT + RK3288_GRF_SOC_CON14);
1414         }
1415 }
1416 #ifdef CONFIG_RK_3288_DSI_UBOOT
1417 #ifdef CONFIG_OF_LIBFDT
1418 int rk_dsi_host_parse_dt(const void *blob, struct dsi *dsi)
1419 {
1420         int node;
1421
1422         node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_DSIHOST);
1423         if(node<0) {
1424                 printf("mipi dts get node failed, node = %d.\n", node);
1425                 return -1;
1426         }
1427
1428         do{
1429                 if(fdtdec_get_int(blob, node, "rockchip,prop", -1) != dsi->dsi_id){
1430                         node = fdtdec_next_compatible(blob, node, COMPAT_ROCKCHIP_DSIHOST);
1431                         if(node<0) {
1432                                 printf("mipi dts get node failed, node = %d.\n", node);
1433                                 return -1;
1434                         }
1435                 }else{
1436                         break;
1437                 }
1438         }while(1);
1439
1440         //fdtdec_get_addr_size(blob,node,"reg",&length);
1441         dsi->host.membase = (void __iomem *)fdtdec_get_int(blob, node, "reg", -1);
1442         //fdt_getprop(blob, node, "reg", &length);
1443         MIPI_DBG("dsi->host.membase 0x%08lx.\n",(unsigned long)dsi->host.membase);
1444         return 0;
1445 }
1446 #endif /* #ifdef CONFIG_OF_LIBFDT */
1447
1448 int rk32_mipi_enable(vidinfo_t *vid)
1449 {
1450         int ret = 0;
1451         struct dsi *dsi;
1452         struct mipi_dsi_ops *ops;
1453         struct rk_screen *screen;
1454         struct mipi_dsi_screen *dsi_screen;
1455         static int id = 0;
1456
1457         rk_mipi_screen_probe();
1458
1459         do{
1460                 dsi = calloc(1, sizeof(struct dsi));
1461                 if(!dsi) {
1462                   MIPI_DBG("request struct dsi.%d fail!\n",id);
1463                   return -ENOMEM;
1464                 }
1465
1466                 dsi->dsi_id = id;
1467 #ifdef CONFIG_OF_LIBFDT
1468                 rk_dsi_host_parse_dt(gd->fdt_blob,dsi);
1469 #endif /* #ifdef CONFIG_OF_LIBFDT */
1470                 screen = calloc(1, sizeof(struct rk_screen));
1471                 if(!screen) {
1472                   MIPI_DBG("request struct rk_screen fail!\n");
1473                 }
1474                 //rk_fb_get_prmry_screen(screen);
1475                 ops = &dsi->ops;
1476                 ops->dsi = dsi;
1477                 ops->id = DWC_DSI_VERSION,
1478                 ops->get_id = rk32_mipi_dsi_get_id,
1479                 ops->dsi_send_packet = rk32_mipi_dsi_send_packet;
1480                 ops->dsi_read_dcs_packet = rk32_mipi_dsi_read_dcs_packet,
1481                 ops->dsi_enable_video_mode = rk32_mipi_dsi_enable_video_mode,
1482                 ops->dsi_enable_command_mode = rk32_mipi_dsi_enable_command_mode,
1483                 ops->dsi_enable_hs_clk = rk32_mipi_dsi_enable_hs_clk,
1484                 ops->dsi_is_active = rk32_mipi_dsi_is_active,
1485                 ops->dsi_is_enable= rk32_mipi_dsi_is_enable,
1486                 ops->power_up = rk32_mipi_dsi_power_up,
1487                 ops->power_down = rk32_mipi_dsi_power_down,
1488                 ops->dsi_init = rk_mipi_dsi_init,
1489
1490                 dsi_screen = &dsi->screen;
1491                 dsi_screen->type = screen->type = vid->screen_type;
1492                 dsi_screen->face = screen->face = vid->lcd_face;
1493                 //dsi_screen->lcdc_id = screen->lcdc_id;
1494                 //dsi_screen->screen_id = screen->screen_id;
1495                 //printf("xjh:vid->vl_freq %d vid->real_freq %d\n",vid->vl_freq, vid->real_freq);
1496                 //dsi_screen->pixclock = screen->mode.pixclock = vid->vl_freq *MHZ ;
1497                 dsi_screen->pixclock = screen->mode.pixclock = vid->real_freq;
1498                 dsi_screen->left_margin = screen->mode.left_margin = vid->vl_hbpd;
1499                 dsi_screen->right_margin = screen->mode.right_margin = vid->vl_hfpd;
1500                 dsi_screen->hsync_len = screen->mode.hsync_len = vid->vl_hspw;
1501                 dsi_screen->upper_margin = screen->mode.upper_margin = vid->vl_vbpd;
1502                 dsi_screen->lower_margin = screen->mode.lower_margin = vid->vl_vfpd;
1503                 dsi_screen->vsync_len = screen->mode.vsync_len = vid->vl_vspw;
1504                 dsi_screen->x_res = screen->mode.xres = vid->vl_width;
1505                 dsi_screen->y_res = screen->mode.yres = vid->vl_height;
1506                 //dsi_screen->pin_hsync = screen->pin_hsync;
1507                 //dsi_screen->pin_vsync = screen->pin_vsync;
1508                 //dsi_screen->pin_den = screen->pin_den;
1509                 //dsi_screen->pin_dclk = screen->pin_dclk;
1510                 dsi_screen->dsi_lane = rk_mipi_get_dsi_lane();
1511                 //  dsi_screen->dsi_video_mode = screen->dsi_video_mode; //no sure
1512                 dsi_screen->dsi_lane = rk_mipi_get_dsi_lane();
1513                 dsi_screen->hs_tx_clk = rk_mipi_get_dsi_clk();
1514                 dsi_screen->lcdc_id = 1;
1515                 dsi->dsi_id = id++;//of_alias_get_id(pdev->dev.of_node, "dsi");
1516                 sprintf(ops->name, "rk_mipi_dsi.%d", dsi->dsi_id);
1517
1518                 ret = rk_mipi_dsi_probe(dsi);
1519                 if(ret) {
1520                   MIPI_DBG("rk mipi_dsi probe fail!\n");
1521                   MIPI_DBG("%s\n", RK_MIPI_DSI_VERSION_AND_TIME);
1522                 }
1523
1524                 if(id == 1){
1525                   rk32_init_phy_mode(dsi_screen->lcdc_id);
1526                   //rk_fb_trsm_ops_register(&trsm_dsi_ops, SCREEN_MIPI);
1527                   dsi0 = dsi;
1528                 }else{
1529                   dsi1 = dsi;
1530                 }
1531                 //if(vid->screen_type == SCREEN_DUAL_MIPI){
1532                 if( rk_mipi_get_dsi_num() == 2 ){
1533                     if(id==2)
1534                         break;
1535                 }else
1536                     break;
1537
1538         }while(1);
1539
1540         rk32_dsi_enable();
1541
1542 #if 0
1543
1544         int reg = 0;
1545
1546     // printf("MIPI HOST dump regs\n");
1547      for(reg=0x0;reg<0xc4;){
1548         // printf("reg[0x%04x]=0x%08x ",reg,
1549         // __raw_readl(dsi0->host.membase + reg));
1550          __raw_readl(dsi0->host.membase + reg);
1551          reg+=4;
1552 //       if(reg%16 == 0)
1553 //               printf("\n");
1554      }
1555
1556         MIPI_DBG("rk mipi_dsi probe success!\n");
1557         MIPI_DBG("%s\n", RK_MIPI_DSI_VERSION_AND_TIME);
1558         #endif
1559         return 0;
1560
1561 }
1562 #endif
1563 #ifdef CONFIG_MIPI_DSI_LINUX
1564 static int rk32_mipi_power_down_DDR(void)
1565 {
1566         dsi_is_enable(0, 0);
1567         if (rk_mipi_get_dsi_num() ==2)
1568                 dsi_is_enable(1, 0);
1569         return 0;
1570 }
1571
1572 static int rk32_mipi_power_up_DDR(void)
1573 {
1574         dsi_is_enable(0, 0);
1575         if (rk_mipi_get_dsi_num() ==2)
1576                 dsi_is_enable(1, 0);
1577         dsi_enable_video_mode(0, 1);
1578         dsi_enable_video_mode(1, 1);
1579         dsi_is_enable(0, 1);
1580         if (rk_mipi_get_dsi_num() ==2)
1581                 dsi_is_enable(1, 1);
1582         return 0;
1583 }
1584
1585 static int rk32_mipi_dsi_probe(struct platform_device *pdev)
1586 {
1587         int ret = 0;
1588         static int id = 0;
1589         struct dsi *dsi;
1590         struct mipi_dsi_ops *ops;
1591         struct rk_screen *screen;
1592         struct mipi_dsi_screen *dsi_screen;
1593         struct resource *res_host;
1594
1595         dsi = devm_kzalloc(&pdev->dev, sizeof(struct dsi), GFP_KERNEL);
1596         if(!dsi) {
1597                 dev_err(&pdev->dev,"request struct dsi fail!\n");
1598                 return -ENOMEM;
1599         }
1600
1601         res_host = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1602         dsi->host.membase = devm_request_and_ioremap(&pdev->dev, res_host);
1603         if (!dsi->host.membase){
1604                 dev_err(&pdev->dev, "get resource mipi host membase fail!\n");
1605                 return -ENOMEM;
1606         }
1607
1608         dsi->phy.refclk  = devm_clk_get(&pdev->dev, "clk_mipi_24m");
1609         if (unlikely(IS_ERR(dsi->phy.refclk))) {
1610                 dev_err(&pdev->dev, "get clk_mipi_24m clock fail\n");
1611                 return PTR_ERR(dsi->phy.refclk);
1612         }
1613
1614         dsi->dsi_pclk = devm_clk_get(&pdev->dev, "pclk_mipi_dsi");
1615         if (unlikely(IS_ERR(dsi->dsi_pclk))) {
1616                 dev_err(&pdev->dev, "get pclk_mipi_dsi clock fail\n");
1617                 return PTR_ERR(dsi->dsi_pclk);
1618         }
1619
1620         dsi->dsi_pd = devm_clk_get(&pdev->dev, "pd_mipi_dsi");
1621         if (unlikely(IS_ERR(dsi->dsi_pd))) {
1622                 dev_err(&pdev->dev, "get pd_mipi_dsi clock fail\n");
1623                 return PTR_ERR(dsi->dsi_pd);
1624         }
1625
1626         dsi->host.irq = platform_get_irq(pdev, 0);
1627         if (dsi->host.irq < 0) {
1628                 dev_err(&pdev->dev, "no irq resource?\n");
1629                 return dsi->host.irq;
1630         }
1631
1632         //ret = request_irq(dsi->host.irq, rk32_mipi_dsi_irq_handler, 0,dev_name(&pdev->dev), dsi);
1633         //if(ret) {
1634         //      dev_err(&pdev->dev, "request mipi_dsi irq fail\n");
1635         //      return -EINVAL;
1636         //}
1637         printk("dsi->host.irq =%d\n",dsi->host.irq);
1638
1639         disable_irq(dsi->host.irq);
1640
1641         screen = devm_kzalloc(&pdev->dev, sizeof(struct rk_screen), GFP_KERNEL);
1642         if(!screen) {
1643                 dev_err(&pdev->dev,"request struct rk_screen fail!\n");
1644                 return -1;
1645         }
1646         rk_fb_get_prmry_screen(screen);
1647
1648         dsi->pdev = pdev;
1649         ops = &dsi->ops;
1650         ops->dsi = dsi;
1651         ops->id = DWC_DSI_VERSION,
1652         ops->get_id = rk32_mipi_dsi_get_id,
1653         ops->dsi_send_packet = rk32_mipi_dsi_send_packet;
1654         ops->dsi_read_dcs_packet = rk32_mipi_dsi_read_dcs_packet,
1655         ops->dsi_enable_video_mode = rk32_mipi_dsi_enable_video_mode,
1656         ops->dsi_enable_command_mode = rk32_mipi_dsi_enable_command_mode,
1657         ops->dsi_enable_hs_clk = rk32_mipi_dsi_enable_hs_clk,
1658         ops->dsi_is_active = rk32_mipi_dsi_is_active,
1659         ops->dsi_is_enable= rk32_mipi_dsi_is_enable,
1660         ops->power_up = rk32_mipi_dsi_power_up,
1661         ops->power_down = rk32_mipi_dsi_power_down,
1662         ops->dsi_init = rk_mipi_dsi_init,
1663
1664         dsi_screen = &dsi->screen;
1665         dsi_screen->type = screen->type;
1666         dsi_screen->face = screen->face;
1667         dsi_screen->lcdc_id = screen->lcdc_id;
1668         dsi_screen->screen_id = screen->screen_id;
1669         dsi_screen->pixclock = screen->mode.pixclock;
1670         dsi_screen->left_margin = screen->mode.left_margin;
1671         dsi_screen->right_margin = screen->mode.right_margin;
1672         dsi_screen->hsync_len = screen->mode.hsync_len;
1673         dsi_screen->upper_margin = screen->mode.upper_margin;
1674         dsi_screen->lower_margin = screen->mode.lower_margin;
1675         dsi_screen->vsync_len = screen->mode.vsync_len;
1676         dsi_screen->x_res = screen->mode.xres;
1677         dsi_screen->y_res = screen->mode.yres;
1678         dsi_screen->pin_hsync = screen->pin_hsync;
1679         dsi_screen->pin_vsync = screen->pin_vsync;
1680         dsi_screen->pin_den = screen->pin_den;
1681         dsi_screen->pin_dclk = screen->pin_dclk;
1682         dsi_screen->dsi_lane = rk_mipi_get_dsi_lane();
1683 //  dsi_screen->dsi_video_mode = screen->dsi_video_mode; //no sure
1684         dsi_screen->dsi_lane = rk_mipi_get_dsi_lane();
1685         dsi_screen->hs_tx_clk = rk_mipi_get_dsi_clk();
1686         dsi_screen->lcdc_id = 1;
1687
1688         dsi->dsi_id = id++;
1689
1690         sprintf(ops->name, "rk_mipi_dsi.%d", dsi->dsi_id);
1691         platform_set_drvdata(pdev, dsi);
1692
1693         ret = rk_mipi_dsi_probe(dsi);
1694         if(ret) {
1695                 dev_err(&pdev->dev,"rk mipi_dsi probe fail!\n");
1696                 dev_err(&pdev->dev,"%s\n", RK_MIPI_DSI_VERSION_AND_TIME);
1697                 return -1;
1698         }
1699
1700         if(id == 1){
1701
1702                 if(!support_uboot_display())
1703                         rk32_init_phy_mode(dsi_screen->lcdc_id);
1704                 rk_fb_trsm_ops_register(&trsm_dsi_ops, SCREEN_MIPI);
1705
1706 #ifdef MIPI_DSI_REGISTER_IO
1707                 debugfs_create_file("mipidsi0", S_IFREG | S_IRUGO, dsi->debugfs_dir, dsi,
1708                                                         &reg_proc_fops);
1709 #endif
1710                 dsi0 = dsi;
1711         }else{
1712                 dsi1 = dsi;
1713
1714 #ifdef MIPI_DSI_REGISTER_IO
1715         debugfs_create_file("mipidsi1", S_IFREG | S_IRUGO, dsi->debugfs_dir, dsi,
1716                                                         &reg_proc_fops1);
1717 #endif
1718
1719         }
1720
1721     if(support_uboot_display()){
1722             clk_prepare_enable(dsi->phy.refclk);
1723             clk_prepare_enable(dsi->dsi_pclk);
1724             clk_prepare_enable(dsi->dsi_pd);
1725             udelay(10);
1726     }
1727         dev_info(&pdev->dev,"rk mipi_dsi probe success!\n");
1728         dev_info(&pdev->dev,"%s\n", RK_MIPI_DSI_VERSION_AND_TIME);
1729
1730         return ret;
1731 }
1732
1733 #ifdef CONFIG_OF
1734 static const struct of_device_id of_rk_mipi_dsi_match[] = {
1735         { .compatible = "rockchip,rk32-dsi" },
1736         { /* Sentinel */ }
1737 };
1738 #endif
1739
1740 static struct platform_driver rk32_mipi_dsi_driver = {
1741         .probe          = rk32_mipi_dsi_probe,
1742         .driver         = {
1743                 .name   = "rk32-mipi",
1744                 .owner  = THIS_MODULE,
1745 #ifdef CONFIG_OF
1746                 .of_match_table = of_rk_mipi_dsi_match,
1747 #endif
1748         },
1749 };
1750
1751 static int __init rk32_mipi_dsi_init(void)
1752 {
1753         return platform_driver_register(&rk32_mipi_dsi_driver);
1754 }
1755 fs_initcall(rk32_mipi_dsi_init);
1756
1757 static void __exit rk32_mipi_dsi_exit(void)
1758 {
1759         platform_driver_unregister(&rk32_mipi_dsi_driver);
1760 }
1761 module_exit(rk32_mipi_dsi_exit);
1762 #endif