drivers/video/rockchip/transmitter/rk32_mipi_dsi.c

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  * drivers/video/display/transmitter/rk32_mipi_dsi.c
   4  * author: libing@rock-chips.com
   5  * create date: 2014-04-10
   6  * debug /sys/kernel/debug/mipidsi*
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 //config
  18 #ifndef CONFIG_RK32_MIPI_DSI
  19 #include <common.h>
  20 #endif
  21
  22 #ifdef CONFIG_RK32_MIPI_DSI
  23 #define MIPI_DSI_REGISTER_IO    0
  24 #define CONFIG_MIPI_DSI_LINUX   0
  25 #endif
  26 #define DWC_DSI_VERSION                 0x3133302A
  27
  28 #ifdef CONFIG_RK_3288_DSI_UBOOT
  29 #include <asm/io.h>
  30 #include <errno.h>
  31 #include <lcd.h>
  32 #include <div64.h>
  33 #include <linux/ctype.h>
  34 #include <linux/math64.h>
  35 #include "mipi_dsi.h"
  36 #include "rk32_mipi_dsi.h"
  37 #include "mipi_dsi.h"
  38 #include <asm/arch/rkplat.h>
  39 #include <fdtdec.h>
  40 #include <linux/fb.h>
  41 #include <linux/rk_screen.h>
  42 #include <malloc.h>
  43 #else
  44 #include <linux/kernel.h>
  45 #include <linux/init.h>
  46 #include <linux/platform_device.h>
  47 #include <linux/slab.h>
  48 #include <linux/rk_fb.h>
  49 #include <linux/rk_screen.h>
  50 #include <linux/delay.h>
  51 #include <linux/clk.h>
  52 #include <linux/interrupt.h>
  53 #include <asm/div64.h>
  54
  55 #include <linux/fs.h>
  56 #include <linux/debugfs.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/regulator/machine.h>
  59
  60 #include <linux/dma-mapping.h>
  61 #include "mipi_dsi.h"
  62 #include "rk32_mipi_dsi.h"
  63 #include <linux/rockchip/iomap.h>
  64 #endif
  65 #ifdef CONFIG_RK32_MIPI_DSI
  66 #define MIPI_DBG(x...)  //printk(KERN_INFO x)
  67 #elif defined CONFIG_RK_3288_DSI_UBOOT
  68 #define MIPI_DBG(x...)  //printf( x)
  69 #define printk(x...)    //printf( x)
  70 #else
  71 #define MIPI_DBG(x...)
  72 #endif
  73
  74 #ifdef CONFIG_MIPI_DSI_LINUX
  75 #define MIPI_TRACE(x...)        //printk(KERN_INFO x)
  76 #else
  77 #define MIPI_TRACE(...)    \
  78         do\
  79         {\
  80                 printf(__VA_ARGS__);\
  81                 printf("\n");\
  82         }while(0);
  83
  84 #endif
  85
  86 /*
  87 *                        Driver Version Note
  88 *
  89 *v1.0 : this driver is rk32 mipi dsi driver of rockchip;
  90 *v1.1 : add test eye pattern;
  91 *
  92 */
  93
  94 #define RK_MIPI_DSI_VERSION_AND_TIME  "rockchip mipi_dsi v1.1 2014-06-17"
  95
  96 static struct dsi *dsi0;
  97 static struct dsi *dsi1;
  98
  99 static int rk32_mipi_dsi_is_active(void *arg);
 100 static int rk32_mipi_dsi_enable_hs_clk(void *arg, u32 enable);
 101 static int rk32_mipi_dsi_enable_video_mode(void *arg, u32 enable);
 102 static int rk32_mipi_dsi_enable_command_mode(void *arg, u32 enable);
 103 static int rk32_mipi_dsi_is_enable(void *arg, u32 enable);
 104 int rk_mipi_screen_standby(u8 enable);
 105
 106 #ifdef CONFIG_RK_3288_DSI_UBOOT
 107 DECLARE_GLOBAL_DATA_PTR;
 108 extern int rk_mipi_screen_probe(void);
 109 extern void writel_relaxed(uint32 val, uint32 addr);
 110 #define msleep(a) udelay(a * 1000)
 111 /*
 112 dsihost0:
 113 clocks = <&clk_gates5 15>, <&clk_gates16 4>;
 114 clock-names = "clk_mipi_24m", "pclk_mipi_dsi";
 115
 116 dsihost1:
 117 clocks = <&clk_gates5 15>, <&clk_gates16 5>;
 118 clock-names = "clk_mipi_24m", "pclk_mipi_dsi";
 119
 120 */
 121 int rk32_mipi_dsi_clk_enable(struct dsi *dsi)
 122 {
 123         u32 val;
 124         val = 0x80000000;//bit31~bit16
 125         writel(val, RK3288_CRU_PHYS + 0x174); /*24M*/
 126         if(dsi->dsi_id == 0)
 127                 val = (1 << 20);
 128         else
 129                 val = (1 << 21);
 130         writel(val, RK3288_CRU_PHYS + 0x1a0); /*pclk*/
 131         return 0;
 132 }
 133 int rk32_mipi_dsi_clk_disable(struct dsi *dsi)
 134 {
 135         u32 val;
 136         if(dsi->dsi_id == 0)
 137                 val = (1 << 20)|(1 << 4);
 138         else
 139                 val = (1 << 21)|(1 << 5);
 140         writel(val, RK3288_CRU_PHYS + 0x1a0); /*pclk*/
 141
 142         val = 0x80008000;//bit31~bit16
 143         writel(val, RK3288_CRU_PHYS + 0x174); /*24M*/
 144         return 0;
 145 }
 146
 147 #endif
 148 static int rk32_dsi_read_reg(struct dsi *dsi, u16 reg, u32 *pval)
 149 {
 150         *pval = __raw_readl(dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
 151         return 0;
 152 }
 153
 154 static int rk32_dsi_write_reg(struct dsi *dsi, u16 reg, u32 *pval)
 155 {
 156         __raw_writel(*pval, dsi->host.membase + (reg - MIPI_DSI_HOST_OFFSET));
 157         return 0;
 158 }
 159
 160 static int rk32_dsi_get_bits(struct dsi *dsi, u32 reg)
 161 {
 162         u32 val = 0;
 163         u32 bits = (reg >> 8) & 0xff;
 164         u16 reg_addr = (reg >> 16) & 0xffff;
 165         u8 offset = reg & 0xff;
 166
 167         if(bits < 32)
 168                 bits = (1 << bits) - 1;
 169         else
 170                 bits = 0xffffffff;
 171
 172         rk32_dsi_read_reg(dsi, reg_addr, &val);
 173         val >>= offset;
 174         val &= bits;
 175
 176         return val;
 177 }
 178
 179 static int rk32_dsi_set_bits(struct dsi *dsi, u32 data, u32 reg)
 180 {
 181         static u32 val = 0;
 182         u32 bits = (reg >> 8) & 0xff;
 183         u16 reg_addr = (reg >> 16) & 0xffff;
 184         u8 offset = reg & 0xff;
 185
 186         if(bits < 32)
 187                 bits = (1 << bits) - 1;
 188         else
 189                 bits = 0xffffffff;
 190
 191         if(bits != 0xffffffff)
 192                 rk32_dsi_read_reg(dsi, reg_addr, &val);
 193
 194         val &= ~(bits << offset);
 195         val |= (data & bits) << offset;
 196         rk32_dsi_write_reg(dsi, reg_addr, &val);
 197
 198         if(data > bits) {
 199                 MIPI_TRACE("%s error reg_addr:0x%04x, offset:%d, bits:0x%04x, value:0x%04x\n",
 200                                 __func__, reg_addr, offset, bits, data);
 201         }
 202
 203         return 0;
 204 }
 205 #if 0
 206 static int rk32_dwc_phy_test_rd(struct dsi *dsi, unsigned char test_code)
 207 {
 208         int val = 0;
 209         rk32_dsi_set_bits(dsi, 1, phy_testclk);
 210         rk32_dsi_set_bits(dsi, test_code, phy_testdin);
 211         rk32_dsi_set_bits(dsi, 1, phy_testen);
 212         rk32_dsi_set_bits(dsi, 0, phy_testclk);
 213         rk32_dsi_set_bits(dsi, 0, phy_testen);;
 214
 215         rk32_dsi_set_bits(dsi, 0, phy_testen);
 216         val = rk32_dsi_get_bits(dsi,phy_testdout);
 217         rk32_dsi_set_bits(dsi, 1, phy_testclk);
 218         rk32_dsi_set_bits(dsi, 0, phy_testclk);
 219
 220         return val;
 221 }
 222 #endif
 223 static int rk32_dwc_phy_test_wr(struct dsi *dsi, unsigned char test_code, unsigned char *test_data, unsigned char size)
 224 {
 225         int i = 0;
 226
 227         MIPI_DBG("test_code=0x%x,test_data=0x%x\n", test_code,test_data[0]);
 228         rk32_dsi_set_bits(dsi, 0x10000 | test_code, PHY_TEST_CTRL1);
 229         rk32_dsi_set_bits(dsi, 0x2, PHY_TEST_CTRL0);
 230         rk32_dsi_set_bits(dsi, 0x0, PHY_TEST_CTRL0);
 231
 232         for(i = 0; i < size; i++) {
 233                 rk32_dsi_set_bits(dsi, test_data[i], PHY_TEST_CTRL1);
 234                 rk32_dsi_set_bits(dsi, 0x2, PHY_TEST_CTRL0);
 235                 rk32_dsi_set_bits(dsi, 0x0, PHY_TEST_CTRL0);
 236                 MIPI_DBG("rk32_dwc_phy_test_wr:%08x\n", rk32_dsi_get_bits(dsi, PHY_TEST_CTRL1));
 237         }
 238         return 0;
 239 }
 240
 241 static int rk32_phy_power_up(struct dsi *dsi)
 242 {
 243     //enable ref clock
 244     #ifdef CONFIG_RK_3288_DSI_UBOOT
 245     rk32_mipi_dsi_clk_enable(dsi);
 246     #else
 247     clk_prepare_enable(dsi->phy.refclk);
 248     clk_prepare_enable(dsi->dsi_pclk);
 249     clk_prepare_enable(dsi->dsi_pd);
 250     #endif
 251     udelay(10);
 252
 253         switch(dsi->host.lane) {
 254                 case 4:
 255                         rk32_dsi_set_bits(dsi, 3, n_lanes);
 256                         break;
 257                 case 3:
 258                         rk32_dsi_set_bits(dsi, 2, n_lanes);
 259                         break;
 260                 case 2:
 261                         rk32_dsi_set_bits(dsi, 1, n_lanes);
 262                         break;
 263                 case 1:
 264                         rk32_dsi_set_bits(dsi, 0, n_lanes);
 265                         break;
 266                 default:
 267                         break;
 268         }
 269         rk32_dsi_set_bits(dsi, 1, phy_shutdownz);
 270         rk32_dsi_set_bits(dsi, 1, phy_rstz);
 271         rk32_dsi_set_bits(dsi, 1, phy_enableclk);
 272         rk32_dsi_set_bits(dsi, 1, phy_forcepll);
 273
 274         return 0;
 275 }
 276
 277 static int rk32_phy_power_down(struct dsi *dsi)
 278 {
 279     rk32_dsi_set_bits(dsi, 0, phy_shutdownz);
 280     #ifdef CONFIG_RK_3288_DSI_UBOOT
 281     rk32_mipi_dsi_clk_disable(dsi);
 282     #else
 283     clk_disable_unprepare(dsi->phy.refclk);
 284     clk_disable_unprepare(dsi->dsi_pclk);
 285     clk_disable_unprepare(dsi->dsi_pd);
 286     #endif
 287     return 0;
 288 }
 289
 290 static int rk32_phy_init(struct dsi *dsi)
 291 {
 292         u32 val = 0 , ddr_clk = 0, fbdiv = 0, prediv = 0;
 293         unsigned char test_data[2] = {0};
 294
 295         ddr_clk = dsi->phy.ddr_clk;
 296         prediv  = dsi->phy.prediv;
 297         fbdiv   = dsi->phy.fbdiv;
 298
 299         if(ddr_clk < 200 * MHz)
 300                 val = 0x0;
 301         else if(ddr_clk < 300 * MHz)
 302                 val = 0x1;
 303         else if(ddr_clk < 500 * MHz)
 304                 val = 0x2;
 305         else if(ddr_clk < 700 * MHz)
 306                 val = 0x3;
 307         else if(ddr_clk < 900 * MHz)
 308                 val = 0x4;
 309         else if(ddr_clk < 1100 * MHz)
 310                 val = 0x5;
 311         else if(ddr_clk < 1300 * MHz)
 312                 val = 0x6;
 313         else if(ddr_clk <= 1500 * MHz)
 314                 val = 0x7;
 315
 316         test_data[0] = 0x80 | val << 3 | 0x3;
 317         rk32_dwc_phy_test_wr(dsi, 0x10, test_data, 1);
 318
 319         test_data[0] = 0x8;
 320         rk32_dwc_phy_test_wr(dsi, 0x11, test_data, 1);
 321
 322         test_data[0] = 0x80 | 0x40;
 323         rk32_dwc_phy_test_wr(dsi, 0x12, test_data, 1);
 324
 325         if(ddr_clk < 90 * MHz)
 326                 val = 0x01;
 327         else if(ddr_clk < 100 * MHz)
 328                 val = 0x10;
 329         else if(ddr_clk < 110 * MHz)
 330                 val = 0x20;
 331         else if(ddr_clk < 130 * MHz)
 332                 val = 0x01;
 333         else if(ddr_clk < 140 * MHz)
 334                 val = 0x11;
 335         else if(ddr_clk < 150 * MHz)
 336                 val = 0x21;
 337         else if(ddr_clk < 170 * MHz)
 338                 val = 0x02;
 339         else if(ddr_clk < 180 * MHz)
 340                 val = 0x12;
 341         else if(ddr_clk < 200 * MHz)
 342                 val = 0x22;
 343         else if(ddr_clk < 220 * MHz)
 344                 val = 0x03;
 345         else if(ddr_clk < 240 * MHz)
 346                 val = 0x13;
 347         else if(ddr_clk < 250 * MHz)
 348                 val = 0x23;
 349         else if(ddr_clk < 270 * MHz)
 350                 val = 0x04;
 351         else if(ddr_clk < 300 * MHz)
 352                 val = 0x14;
 353         else if(ddr_clk < 330 * MHz)
 354                 val = 0x05;
 355         else if(ddr_clk < 360 * MHz)
 356                 val = 0x15;
 357         else if(ddr_clk < 400 * MHz)
 358                 val = 0x25;
 359         else if(ddr_clk < 450 * MHz)
 360                 val = 0x06;
 361         else if(ddr_clk < 500 * MHz)
 362                 val = 0x16;
 363         else if(ddr_clk < 550 * MHz)
 364                 val = 0x07;
 365         else if(ddr_clk < 600 * MHz)
 366                 val = 0x17;
 367         else if(ddr_clk < 650 * MHz)
 368                 val = 0x08;
 369         else if(ddr_clk < 700 * MHz)
 370                 val = 0x18;
 371         else if(ddr_clk < 750 * MHz)
 372                 val = 0x09;
 373         else if(ddr_clk < 800 * MHz)
 374                 val = 0x19;
 375         else if(ddr_clk < 850 * MHz)
 376                 val = 0x29;
 377         else if(ddr_clk < 900 * MHz)
 378                 val = 0x39;
 379         else if(ddr_clk < 950 * MHz)
 380                 val = 0x0a;
 381         else if(ddr_clk < 1000 * MHz)
 382                 val = 0x1a;
 383         else if(ddr_clk < 1050 * MHz)
 384                 val = 0x2a;
 385         else if(ddr_clk < 1100* MHz)
 386                 val = 0x3a;
 387         else if(ddr_clk < 1150* MHz)
 388                 val = 0x0b;
 389         else if(ddr_clk < 1200 * MHz)
 390                 val = 0x1b;
 391         else if(ddr_clk < 1250 * MHz)
 392                 val = 0x2b;
 393         else if(ddr_clk < 1300 * MHz)
 394                 val = 0x3b;
 395         else if(ddr_clk < 1350 * MHz)
 396                 val = 0x0c;
 397         else if(ddr_clk < 1400* MHz)
 398                 val = 0x1c;
 399         else if(ddr_clk < 1450* MHz)
 400                 val = 0x2c;
 401         else if(ddr_clk <= 1500* MHz)
 402                 val = 0x3c;
 403
 404         test_data[0] = val << 1;
 405         rk32_dwc_phy_test_wr(dsi, code_hs_rx_lane0, test_data, 1);
 406
 407         test_data[0] = prediv- 1;
 408         rk32_dwc_phy_test_wr(dsi, code_pll_input_div_rat, test_data, 1);
 409         mdelay(2);
 410         test_data[0] = (fbdiv - 1) & 0x1f;
 411         rk32_dwc_phy_test_wr(dsi, code_pll_loop_div_rat, test_data, 1);
 412         mdelay(2);
 413         test_data[0] = (fbdiv - 1) >> 5 | 0x80;
 414         rk32_dwc_phy_test_wr(dsi, code_pll_loop_div_rat, test_data, 1);
 415         mdelay(2);
 416         test_data[0] = 0x30;
 417         rk32_dwc_phy_test_wr(dsi, code_pll_input_loop_div_rat, test_data, 1);
 418         mdelay(2);
 419
 420         test_data[0] = 0x4d;
 421         rk32_dwc_phy_test_wr(dsi, 0x20, test_data, 1);
 422
 423         test_data[0] = 0x3d;
 424         rk32_dwc_phy_test_wr(dsi, 0x21, test_data, 1);
 425
 426         test_data[0] = 0xdf;
 427         rk32_dwc_phy_test_wr(dsi, 0x21, test_data, 1);
 428
 429         test_data[0] =  0x7;
 430         rk32_dwc_phy_test_wr(dsi, 0x22, test_data, 1);
 431
 432         test_data[0] = 0x80 | 0x7;
 433         rk32_dwc_phy_test_wr(dsi, 0x22, test_data, 1);
 434
 435         test_data[0] = 0x80 | 15;
 436         rk32_dwc_phy_test_wr(dsi, code_hstxdatalanerequsetstatetime, test_data, 1);
 437
 438         test_data[0] = 0x80 | 85;
 439         rk32_dwc_phy_test_wr(dsi, code_hstxdatalanepreparestatetime, test_data, 1);
 440
 441         test_data[0] = 0x40 | 10;
 442         rk32_dwc_phy_test_wr(dsi, code_hstxdatalanehszerostatetime, test_data, 1);
 443
 444     return 0;
 445 }
 446
 447 static int rk32_mipi_dsi_host_power_up(struct dsi *dsi)
 448 {
 449         int ret = 0;
 450         u32 val;
 451
 452         //disable all interrupt
 453         rk32_dsi_set_bits(dsi, 0x1fffff, INT_MKS0);
 454         rk32_dsi_set_bits(dsi, 0x3ffff, INT_MKS1);
 455
 456         rk32_mipi_dsi_is_enable(dsi, 1);
 457
 458         val = 10;
 459         while(!rk32_dsi_get_bits(dsi, phylock) && val--) {
 460                 udelay(10);
 461         };
 462
 463         if(val == 0) {
 464                 ret = -1;
 465                 MIPI_TRACE("%s:phylock fail.\n", __func__);
 466         }
 467
 468         val = 10;
 469         while(!rk32_dsi_get_bits(dsi, phystopstateclklane) && val--) {
 470                 udelay(10);
 471         };
 472
 473         return ret;
 474 }
 475
 476 static int rk32_mipi_dsi_host_power_down(struct dsi *dsi)
 477 {
 478         rk32_mipi_dsi_enable_video_mode(dsi, 0);
 479         rk32_mipi_dsi_enable_hs_clk(dsi, 0);
 480         rk32_mipi_dsi_is_enable(dsi, 0);
 481         return 0;
 482 }
 483
 484 static int rk32_mipi_dsi_host_init(struct dsi *dsi)
 485 {
 486         u32 val = 0, bytes_px = 0;
 487         struct mipi_dsi_screen *screen = &dsi->screen;
 488         u32 decimals = dsi->phy.Ttxbyte_clk, temp = 0, i = 0;
 489         u32 m = 1, lane = dsi->host.lane, Tpclk = dsi->phy.Tpclk,
 490                         Ttxbyte_clk = dsi->phy.Ttxbyte_clk;
 491
 492         rk32_dsi_set_bits(dsi, dsi->host.lane - 1, n_lanes);
 493         rk32_dsi_set_bits(dsi, dsi->vid, dpi_vcid);
 494
 495         switch(screen->face) {
 496                 case OUT_P888:
 497                         rk32_dsi_set_bits(dsi, 5, dpi_color_coding);
 498                         bytes_px = 3;
 499                         break;
 500
 501                 case OUT_D888_P666:
 502
 503                 case OUT_P666:
 504                         rk32_dsi_set_bits(dsi, 3, dpi_color_coding);
 505                         rk32_dsi_set_bits(dsi, 1, en18_loosely);
 506                         bytes_px = 3;
 507                         break;
 508
 509                 case OUT_P565:
 510                         rk32_dsi_set_bits(dsi, 0, dpi_color_coding);
 511                         bytes_px = 2;
 512
 513                 default:
 514                         break;
 515         }
 516
 517         rk32_dsi_set_bits(dsi, 1, hsync_active_low);
 518         rk32_dsi_set_bits(dsi, 1, vsync_active_low);
 519
 520         rk32_dsi_set_bits(dsi, 0, dataen_active_low);
 521         rk32_dsi_set_bits(dsi, 0, colorm_active_low);
 522         rk32_dsi_set_bits(dsi, 0, shutd_active_low);
 523
 524         rk32_dsi_set_bits(dsi, dsi->host.video_mode, vid_mode_type);      //burst mode
 525
 526         switch(dsi->host.video_mode) {
 527
 528                 case VM_BM:
 529                     if(screen->type == SCREEN_DUAL_MIPI)
 530                             rk32_dsi_set_bits(dsi, screen->x_res / 2 + 4, vid_pkt_size);
 531                          else
 532                             rk32_dsi_set_bits(dsi, screen->x_res, vid_pkt_size);
 533                         break;
 534
 535                 case VM_NBMWSE:
 536
 537                 case VM_NBMWSP:
 538                         for(i = 8; i < 32; i++){
 539                                 temp = i * lane * Tpclk % Ttxbyte_clk;
 540                                 if(decimals > temp) {
 541                                         decimals = temp;
 542                                         m = i;
 543                                 }
 544                                 if(decimals == 0)
 545                                         break;
 546                         }
 547
 548                         rk32_dsi_set_bits(dsi, screen->x_res / m + 1, num_chunks);
 549                         rk32_dsi_set_bits(dsi, m, vid_pkt_size);
 550                         temp = m * lane * Tpclk / Ttxbyte_clk - m * bytes_px;
 551                         MIPI_DBG("%s:%d, %d\n", __func__, m, temp);
 552
 553                         if(temp >= 12)
 554                                 rk32_dsi_set_bits(dsi, temp - 12, null_pkt_size);
 555
 556                         break;
 557
 558                 default:
 559
 560                         break;
 561         }
 562
 563         //rk32_dsi_set_bits(dsi, 0, CMD_MODE_CFG << 16);
 564         if(screen->type == SCREEN_MIPI){
 565                 rk32_dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->x_res + screen->left_margin +
 566                                         screen->hsync_len + screen->right_margin) \
 567                                                 / dsi->phy.Ttxbyte_clk, vid_hline_time);
 568         }
 569         else{
 570                 rk32_dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->x_res + 8 + screen->left_margin +
 571                                         screen->hsync_len + screen->right_margin) \
 572                                                 / dsi->phy.Ttxbyte_clk, vid_hline_time);
 573         }
 574     rk32_dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->left_margin) / dsi->phy.Ttxbyte_clk,
 575                                         vid_hbp_time);
 576         rk32_dsi_set_bits(dsi, dsi->phy.Tpclk * (screen->hsync_len) / dsi->phy.Ttxbyte_clk,
 577                                         vid_hsa_time);
 578
 579         rk32_dsi_set_bits(dsi, screen->y_res , vid_active_lines);
 580         rk32_dsi_set_bits(dsi, screen->lower_margin, vid_vfp_lines);
 581         rk32_dsi_set_bits(dsi, screen->upper_margin, vid_vbp_lines);
 582         rk32_dsi_set_bits(dsi, screen->vsync_len, vid_vsa_lines);
 583
 584         dsi->phy.txclkesc = 20 * MHz;
 585         val = dsi->phy.txbyte_clk / dsi->phy.txclkesc + 1;
 586         dsi->phy.txclkesc = dsi->phy.txbyte_clk / val;
 587         rk32_dsi_set_bits(dsi, val, TX_ESC_CLK_DIVISION);
 588
 589         rk32_dsi_set_bits(dsi, 10, TO_CLK_DIVISION);
 590     rk32_dsi_set_bits(dsi, 1000, hstx_to_cnt); //no sure
 591         rk32_dsi_set_bits(dsi, 1000, lprx_to_cnt);
 592         rk32_dsi_set_bits(dsi, 100, phy_stop_wait_time);
 593
 594         //rk32_dsi_set_bits(dsi, 0, outvact_lpcmd_time);   //byte
 595         //rk32_dsi_set_bits(dsi, 0, invact_lpcmd_time);
 596
 597         rk32_dsi_set_bits(dsi, 20, phy_hs2lp_time);
 598         rk32_dsi_set_bits(dsi, 16, phy_lp2hs_time);
 599
 600         // rk32_dsi_set_bits(dsi, 87, phy_hs2lp_time_clk_lane); //no sure
 601         //  rk32_dsi_set_bits(dsi, 25, phy_hs2hs_time_clk_lane); //no sure
 602
 603         rk32_dsi_set_bits(dsi, 10000, max_rd_time);
 604
 605         rk32_dsi_set_bits(dsi, 1, lp_hfp_en);
 606         //rk32_dsi_set_bits(dsi, 1, lp_hbp_en); //no sure
 607         rk32_dsi_set_bits(dsi, 1, lp_vact_en);
 608         rk32_dsi_set_bits(dsi, 1, lp_vfp_en);
 609         rk32_dsi_set_bits(dsi, 1, lp_vbp_en);
 610         rk32_dsi_set_bits(dsi, 1, lp_vsa_en);
 611
 612         //rk32_dsi_set_bits(dsi, 1, frame_bta_ack_en);
 613         rk32_dsi_set_bits(dsi, 1, phy_enableclk);
 614         rk32_dsi_set_bits(dsi, 0, phy_tx_triggers);
 615         //rk32_dsi_set_bits(dsi, 1, phy_txexitulpslan);
 616         //rk32_dsi_set_bits(dsi, 1, phy_txexitulpsclk);
 617         return 0;
 618 }
 619
 620 /*
 621  *      mipi protocol layer definition
 622  */
 623 static int rk_mipi_dsi_init(void *arg, u32 n)
 624 {
 625         u32 decimals = 1000, i = 0, pre = 0;
 626         struct dsi *dsi = arg;
 627         struct mipi_dsi_screen *screen = &dsi->screen;
 628
 629         if(!screen)
 630                 return -1;
 631
 632         if((screen->type != SCREEN_MIPI) && (screen->type != SCREEN_DUAL_MIPI) ) {
 633                 MIPI_TRACE("only mipi dsi lcd is supported!\n");
 634                 return -1;
 635         }
 636
 637         if(((screen->type == SCREEN_DUAL_MIPI) && (rk_mipi_get_dsi_num() == 1)) ||  ((screen->type == SCREEN_MIPI) && (rk_mipi_get_dsi_num() == 2))){
 638                 MIPI_TRACE("dsi number and mipi type not match!\n");
 639             return -1;
 640     }
 641 #ifdef CONFIG_RK_3288_DSI_UBOOT
 642         dsi->phy.Tpclk = div_u64(1000000000000llu, screen->pixclock);
 643         dsi->phy.ref_clk = 24*MHZ;
 644 #else
 645         dsi->phy.Tpclk = rk_fb_get_prmry_screen_pixclock();
 646
 647         if(dsi->phy.refclk)
 648                 dsi->phy.ref_clk = clk_get_rate(dsi->phy.refclk) ;
 649 #endif
 650         dsi->phy.sys_clk = dsi->phy.ref_clk;
 651
 652         printk("dsi->phy.sys_clk =%d\n",dsi->phy.sys_clk );
 653
 654         if((screen->hs_tx_clk <= 90 * MHz) || (screen->hs_tx_clk >= 1500 * MHz))
 655                 dsi->phy.ddr_clk = 1500 * MHz;    //default is 1.5HGz
 656         else
 657                 dsi->phy.ddr_clk = screen->hs_tx_clk;
 658
 659         if(n != 0)
 660                 dsi->phy.ddr_clk = n;
 661
 662         decimals = dsi->phy.ref_clk;
 663         for(i = 1; i < 6; i++) {
 664                 pre = dsi->phy.ref_clk / i;
 665                 if((decimals > (dsi->phy.ddr_clk % pre)) && (dsi->phy.ddr_clk / pre < 512)) {
 666                         decimals = dsi->phy.ddr_clk % pre;
 667                         dsi->phy.prediv = i;
 668                         dsi->phy.fbdiv = dsi->phy.ddr_clk / pre;
 669                 }
 670                 if(decimals == 0)
 671                         break;
 672         }
 673
 674         MIPI_DBG("prediv:%d, fbdiv:%d,dsi->phy.ddr_clk:%d\n", dsi->phy.prediv, dsi->phy.fbdiv,dsi->phy.ref_clk / dsi->phy.prediv * dsi->phy.fbdiv);
 675
 676         dsi->phy.ddr_clk = dsi->phy.ref_clk / dsi->phy.prediv * dsi->phy.fbdiv;
 677         MIPI_DBG("dsi->phy.ddr_clk =%d\n",dsi->phy.ddr_clk);
 678         dsi->phy.txbyte_clk = dsi->phy.ddr_clk / 8;
 679
 680         dsi->phy.txclkesc = 20 * MHz;        // < 20MHz
 681         dsi->phy.txclkesc = dsi->phy.txbyte_clk / (dsi->phy.txbyte_clk / dsi->phy.txclkesc + 1);
 682
 683         dsi->phy.pclk = div_u64(1000000000000llu, dsi->phy.Tpclk);
 684         dsi->phy.Ttxclkesc = div_u64(1000000000000llu, dsi->phy.txclkesc);
 685         dsi->phy.Tsys_clk = div_u64(1000000000000llu, dsi->phy.sys_clk);
 686         dsi->phy.Tddr_clk = div_u64(1000000000000llu, dsi->phy.ddr_clk);
 687         dsi->phy.Ttxbyte_clk = div_u64(1000000000000llu, dsi->phy.txbyte_clk);
 688
 689         dsi->phy.UI = dsi->phy.Tddr_clk;
 690         dsi->vid = 0;
 691
 692         if(screen->dsi_lane > 0 && screen->dsi_lane <= 4)
 693                 dsi->host.lane = screen->dsi_lane;
 694         else
 695                 dsi->host.lane = 4;
 696
 697         dsi->host.video_mode = VM_BM;
 698
 699         MIPI_DBG("UI:%d\n", dsi->phy.UI);
 700         MIPI_DBG("ref_clk:%d\n", dsi->phy.ref_clk);
 701         MIPI_DBG("pclk:%d, Tpclk:%d\n", dsi->phy.pclk, dsi->phy.Tpclk);
 702         MIPI_DBG("sys_clk:%d, Tsys_clk:%d\n", dsi->phy.sys_clk, dsi->phy.Tsys_clk);
 703         MIPI_DBG("ddr_clk:%d, Tddr_clk:%d\n", dsi->phy.ddr_clk, dsi->phy.Tddr_clk);
 704         MIPI_DBG("txbyte_clk:%d, Ttxbyte_clk:%d\n", dsi->phy.txbyte_clk,
 705                                 dsi->phy.Ttxbyte_clk);
 706         MIPI_DBG("txclkesc:%d, Ttxclkesc:%d\n", dsi->phy.txclkesc, dsi->phy.Ttxclkesc);
 707
 708         rk32_phy_power_up(dsi);
 709         rk32_mipi_dsi_host_power_up(dsi);
 710         rk32_phy_init(dsi);
 711         rk32_mipi_dsi_host_init(dsi);
 712
 713         return 0;
 714 }
 715
 716 static int rk32_mipi_dsi_is_enable(void *arg, u32 enable)
 717 {
 718         struct dsi *dsi = arg;
 719
 720         rk32_dsi_set_bits(dsi, enable, shutdownz);
 721
 722         return 0;
 723 }
 724
 725 static int rk32_mipi_dsi_enable_video_mode(void *arg, u32 enable)
 726 {
 727         struct dsi *dsi = arg;
 728
 729         rk32_dsi_set_bits(dsi, !enable, cmd_video_mode);
 730
 731         return 0;
 732 }
 733
 734 static int rk32_mipi_dsi_enable_command_mode(void *arg, u32 enable)
 735 {
 736         struct dsi *dsi = arg;
 737
 738         rk32_dsi_set_bits(dsi, enable, cmd_video_mode);
 739
 740         return 0;
 741 }
 742
 743 static int rk32_mipi_dsi_enable_hs_clk(void *arg, u32 enable)
 744 {
 745         struct dsi *dsi = arg;
 746
 747         rk32_dsi_set_bits(dsi, enable, phy_txrequestclkhs);
 748         return 0;
 749 }
 750
 751 static int rk32_mipi_dsi_is_active(void *arg)
 752 {
 753         struct dsi *dsi = arg;
 754
 755         return rk32_dsi_get_bits(dsi, shutdownz);
 756 }
 757
 758 static int rk32_mipi_dsi_send_packet(void *arg, unsigned char cmds[], u32 length)
 759 {
 760         struct dsi *dsi = arg;
 761         unsigned char *regs;
 762         u32 type, liTmp = 0, i = 0, j = 0, data = 0;
 763
 764         if(rk32_dsi_get_bits(dsi, gen_cmd_full) == 1) {
 765                 MIPI_TRACE("gen_cmd_full\n");
 766                 return -1;
 767         }
 768 #ifdef CONFIG_MIPI_DSI_LINUX
 769         regs = kmalloc(0x400, GFP_KERNEL);
 770         if(!regs) {
 771                 printk("request regs fail!\n");
 772                 return -ENOMEM;
 773         }
 774 #endif
 775 #ifdef CONFIG_RK_3288_DSI_UBOOT
 776         regs = calloc(1, 0x400);
 777         if(!regs) {
 778                 printf("request regs fail!\n");
 779                 return -ENOMEM;
 780         }
 781 #endif
 782         memcpy(regs,cmds,length);
 783
 784         liTmp   = length - 2;
 785         type    = regs[1];
 786
 787         switch(type)
 788         {
 789                 case DTYPE_DCS_SWRITE_0P:
 790                         rk32_dsi_set_bits(dsi, regs[0], dcs_sw_0p_tx);
 791                         data = regs[2] << 8 | type;
 792                         break;
 793
 794                 case DTYPE_DCS_SWRITE_1P:
 795                         rk32_dsi_set_bits(dsi, regs[0], dcs_sw_1p_tx);
 796                         data = regs[2] << 8 | type;
 797                         data |= regs[3] << 16;
 798                         break;
 799
 800                 case DTYPE_DCS_LWRITE:
 801                         rk32_dsi_set_bits(dsi, regs[0], dcs_lw_tx);
 802
 803                         for(i = 0; i < liTmp; i++){
 804                             regs[i] = regs[i+2];
 805                     }
 806
 807                         for(i = 0; i < liTmp; i++) {
 808                                 j = i % 4;
 809
 810                                 data |= regs[i] << (j * 8);
 811                                 if(j == 3 || ((i + 1) == liTmp)) {
 812                                         if(rk32_dsi_get_bits(dsi, gen_pld_w_full) == 1) {
 813                                                 MIPI_TRACE("gen_pld_w_full :%d\n", i);
 814                                                 break;
 815                                         }
 816
 817                                         rk32_dsi_set_bits(dsi, data, GEN_PLD_DATA);
 818                                         MIPI_DBG("write GEN_PLD_DATA:%d, %08x\n", i, data);
 819                                         data = 0;
 820                                 }
 821                         }
 822
 823                         data = type;
 824                         data |= (liTmp & 0xffff) << 8;
 825
 826                         break;
 827
 828                 case DTYPE_GEN_LWRITE:
 829                         rk32_dsi_set_bits(dsi, regs[0], gen_lw_tx);
 830
 831                         for(i = 0; i < liTmp; i++){
 832                                 regs[i] = regs[i+2];
 833                         }
 834
 835                         for(i = 0; i < liTmp; i++) {
 836                                 j = i % 4;
 837
 838                                 data |= regs[i] << (j * 8);
 839                                 if(j == 3 || ((i + 1) == liTmp)) {
 840                                         if(rk32_dsi_get_bits(dsi, gen_pld_w_full) == 1) {
 841                                                 MIPI_TRACE("gen_pld_w_full :%d\n", i);
 842                                                 break;
 843                                         }
 844
 845                                         rk32_dsi_set_bits(dsi, data, GEN_PLD_DATA);
 846                                         MIPI_DBG("write GEN_PLD_DATA:%d, %08x\n", i, data);
 847                                         data = 0;
 848                                 }
 849                         }
 850
 851                         data = (dsi->vid << 6) | type;
 852                         data |= (liTmp & 0xffff) << 8;
 853                         break;
 854
 855                 case DTYPE_GEN_SWRITE_2P:
 856
 857                         rk32_dsi_set_bits(dsi, regs[0], gen_sw_2p_tx);
 858                         for(i = 0; i < liTmp; i++){
 859                             regs[i] = regs[i+2];
 860                         }
 861
 862                         for(i = 0; i < liTmp; i++) {
 863                                 j = i % 4;
 864                                 data |= regs[i] << (j * 8);
 865                                 if(j == 3 || ((i + 1) == liTmp)) {
 866                                         if(rk32_dsi_get_bits(dsi, gen_pld_w_full) == 1) {
 867                                                 MIPI_TRACE("gen_pld_w_full :%d\n", i);
 868                                                 break;
 869                                         }
 870
 871                                         rk32_dsi_set_bits(dsi, data, GEN_PLD_DATA);
 872                                         MIPI_DBG("write GEN_PLD_DATA:%d, %08x\n", i, data);
 873                                         data = 0;
 874                                 }
 875                         }
 876                         data = type;
 877                         data |= (liTmp & 0xffff) << 8;
 878
 879                         break;
 880
 881                 case DTYPE_GEN_SWRITE_1P:
 882                         rk32_dsi_set_bits(dsi, regs[0], gen_sw_1p_tx);
 883                         data = type;
 884                         data |= regs[2] << 8;
 885                         data |= regs[3] << 16;
 886                         break;
 887
 888                 case DTYPE_GEN_SWRITE_0P:
 889                         rk32_dsi_set_bits(dsi, regs[0], gen_sw_0p_tx);
 890                         data =  type;
 891                         data |= regs[2] << 8;
 892                         break;
 893
 894                 default:
 895                    printk("0x%x:this type not suppport!\n",type);
 896
 897         }
 898
 899         MIPI_DBG("%d command sent in %s size:%d\n", __LINE__, regs[0] ? "LP mode" : "HS mode", liTmp);
 900
 901         MIPI_DBG("write GEN_HDR:%08x\n", data);
 902         rk32_dsi_set_bits(dsi, data, GEN_HDR);
 903
 904         i = 10;
 905         while(!rk32_dsi_get_bits(dsi, gen_cmd_empty) && i--) {
 906                 MIPI_DBG(".");
 907                 udelay(10);
 908         }
 909         udelay(10);
 910 #ifdef CONFIG_MIPI_DSI_LINUX
 911         kfree(regs);
 912 #endif
 913 #ifdef CONFIG_RK_3288_DSI_UBOOT
 914         free(regs);
 915 #endif
 916         return 0;
 917 }
 918
 919 static int rk32_mipi_dsi_read_dcs_packet(void *arg, unsigned char *data1, u32 n)
 920 {
 921         struct dsi *dsi = arg;
 922         //DCS READ
 923         //unsigned char *regs = data;
 924         unsigned char regs[2];
 925         u32 data = 0;
 926         int type = 0x06;
 927         regs[0] = LPDT;
 928         regs[1] = 0x0a;
 929         n = n - 1;
 930
 931
 932         rk32_dsi_set_bits(dsi, regs[0], dcs_sr_0p_tx);
 933
 934         /* if(type == DTYPE_GEN_SWRITE_0P)
 935                 data = (dsi->vid << 6) | (n << 4) | type;
 936         else
 937                 data = (dsi->vid << 6) | ((n-1) << 4) | type;*/
 938
 939         data |= regs[1] << 8 | type;
 940         // if(n == 2)
 941         //    data |= regs[1] << 16;
 942
 943         MIPI_DBG("write GEN_HDR:%08x\n", data);
 944         rk32_dsi_set_bits(dsi, data, GEN_HDR);
 945         msleep(100);
 946
 947         // rk32_dsi_set_bits(dsi, regs[0], gen_sr_0p_tx);
 948
 949         printk("rk32_mipi_dsi_read_dcs_packet==0x%x\n",rk32_dsi_get_bits(dsi, GEN_PLD_DATA));
 950         msleep(100);
 951
 952         //  rk32_dsi_set_bits(dsi, regs[0], max_rd_pkt_size);
 953
 954         msleep(100);
 955         // printk("_____rk32_mipi_dsi_read_dcs_packet==0x%x\n",rk32_dsi_get_bits(dsi, GEN_PLD_DATA));
 956
 957         msleep(100);
 958         return 0;
 959 }
 960
 961 static int rk32_mipi_dsi_power_up(void *arg)
 962 {
 963         struct dsi *dsi = arg;
 964
 965         rk32_phy_power_up(dsi);
 966         rk32_mipi_dsi_host_power_up(dsi);
 967         return 0;
 968 }
 969
 970 static int rk32_mipi_dsi_power_down(void *arg)
 971 {
 972         struct dsi *dsi = arg;
 973         struct mipi_dsi_screen *screen = &dsi->screen;
 974
 975         if(!screen)
 976                 return -1;
 977
 978         rk32_mipi_dsi_host_power_down(dsi);
 979         rk32_phy_power_down(dsi);
 980
 981         MIPI_TRACE("%s:%d\n", __func__, __LINE__);
 982         return 0;
 983 }
 984
 985 static int rk32_mipi_dsi_get_id(void *arg)
 986 {
 987         u32 id = 0;
 988         struct dsi *dsi = arg;
 989
 990         id      = rk32_dsi_get_bits(dsi, VERSION);
 991
 992         return id;
 993 }
 994
 995 /* the most top level of mipi dsi init */
 996 static int rk_mipi_dsi_probe(struct dsi *dsi)
 997 {
 998         int ret = 0;
 999
1000         register_dsi_ops(dsi->dsi_id, &dsi->ops);
1001
1002         ret = dsi_probe_current_chip(dsi->dsi_id);
1003         if(ret) {
1004                 MIPI_TRACE("mipi dsi probe fail\n");
1005                 return -ENODEV;
1006         }
1007
1008         return 0;
1009 }
1010
1011 #ifdef MIPI_DSI_REGISTER_IO
1012 #include <linux/proc_fs.h>
1013 #include <asm/uaccess.h>
1014 #include <linux/slab.h>
1015
1016 int reg_proc_write(struct file *file, const char __user *buff, size_t count, loff_t *offp)
1017 {
1018         int ret = -1, i = 0;
1019         u32 read_val = 0;
1020         char *buf = kmalloc(count, GFP_KERNEL);
1021         char *data = buf;
1022         char str[32];
1023         char command = 0;
1024         u64 regs_val = 0;
1025         memset(buf, 0, count);
1026         ret = copy_from_user((void*)buf, buff, count);
1027         data = strstr(data, "-");
1028         if(data == NULL)
1029                 goto reg_proc_write_exit;
1030         command = *(++data);
1031         switch(command) {
1032                 case 'w':
1033                         while(1) {
1034                                 data = strstr(data, "0x");
1035                                 if(data == NULL)
1036                                         goto reg_proc_write_exit;
1037
1038                                 sscanf(data, "0x%llx", &regs_val);
1039                                 if((regs_val & 0xffff00000000ULL) == 0)
1040                                         goto reg_proc_write_exit;
1041                                 read_val = regs_val & 0xffffffff;
1042                                 printk("regs_val=0x%llx\n",regs_val);
1043                                 rk32_dsi_write_reg(dsi0, regs_val >> 32, &read_val);
1044                                 rk32_dsi_read_reg(dsi0, regs_val >> 32, &read_val);
1045                                 regs_val &= 0xffffffff;
1046                                 if(read_val != regs_val)
1047                                         MIPI_TRACE("%s fail:0x%08x\n", __func__, read_val);
1048                                 data += 3;
1049                                 msleep(1);
1050                         }
1051
1052                         break;
1053                 case 'r':
1054                                 data = strstr(data, "0x");
1055                                 if(data == NULL){
1056                                         goto reg_proc_write_exit;
1057                                 }
1058                                 sscanf(data, "0x%llx", &regs_val);
1059                                 rk32_dsi_read_reg(dsi0, (u16)regs_val, &read_val);
1060                                 MIPI_TRACE("*%04x : %08x\n", (u16)regs_val, read_val);
1061                                 msleep(1);
1062                         break;
1063
1064                 case 's':
1065                                 while(*(++data) == ' ');
1066                                 sscanf(data, "%d", &read_val);
1067                                 if(read_val == 11)
1068                                         read_val = 11289600;
1069                                 else
1070                                         read_val *= MHz;
1071
1072                                 //rk32_mipi_dsi_init_lite(dsi);
1073                         break;
1074                 case 'd':
1075                 case 'g':
1076                 case 'c':
1077                                 while(*(++data) == ' ');
1078                                 i = 0;
1079                                 MIPI_TRACE("****%d:%d\n", data-buf, count);
1080
1081                                 do {
1082                                         if(i > 31) {
1083                                                 MIPI_TRACE("payload entry is larger than 32\n");
1084                                                 break;
1085                                         }
1086                                         sscanf(data, "%x,", (unsigned int *)(str + i));   //-c 1,29,02,03,05,06,> pro
1087                                         data = strstr(data, ",");
1088                                         if(data == NULL)
1089                                                 break;
1090                                         data++;
1091                                         i++;
1092                                 } while(1);
1093                                 read_val = i;
1094
1095                                 i = 2;
1096                                 while(i--) {
1097                                         msleep(10);
1098                                         if(command == 'd')
1099                                                 rk32_mipi_dsi_send_packet(dsi0, str, read_val);
1100                                         else
1101                                                 rk32_mipi_dsi_send_packet(dsi0, str, read_val);
1102                                 }
1103                                 i = 1;
1104                                 while(i--) {
1105                                         msleep(1000);
1106                                 }
1107                         break;
1108
1109                 default:
1110                         break;
1111         }
1112
1113 reg_proc_write_exit:
1114         kfree(buf);
1115         msleep(20);
1116         return count;
1117 }
1118
1119 int reg_proc_read(struct file *file, char __user *buff, size_t count,
1120                                         loff_t *offp)
1121 {
1122         int i = 0;
1123         u32 val = 0;
1124
1125     for(i = VERSION; i < (VERSION + (0xdc<<16)); i += 4<<16) {
1126                 val = rk32_dsi_get_bits(dsi0, i);
1127                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1128                 msleep(1);
1129         }
1130
1131         MIPI_TRACE("\n");
1132
1133         return -1;
1134 }
1135
1136 int reg_proc_open(struct inode *inode, struct file *file)
1137 {
1138         return 0;
1139 }
1140
1141 int reg_proc_close(struct inode *inode, struct file *file)
1142 {
1143         return 0;
1144 }
1145
1146 struct file_operations reg_proc_fops = {
1147         .owner  = THIS_MODULE,
1148         .open   = reg_proc_open,
1149         .release= reg_proc_close,
1150         .write  = reg_proc_write,
1151         .read   = reg_proc_read,
1152 };
1153
1154
1155 int reg_proc_write1(struct file *file, const char __user *buff, size_t count, loff_t *offp)
1156 {
1157         int ret = -1, i = 0;
1158         u32 read_val = 0;
1159         char *buf = kmalloc(count, GFP_KERNEL);
1160         char *data = buf;
1161         char str[32];
1162         char command = 0;
1163         u64 regs_val = 0;
1164         memset(buf, 0, count);
1165         ret = copy_from_user((void*)buf, buff, count);
1166
1167         data = strstr(data, "-");
1168         if(data == NULL)
1169                 goto reg_proc_write_exit;
1170         command = *(++data);
1171
1172         switch(command) {
1173                 case 'w':
1174                         while(1) {
1175
1176                                 data = strstr(data, "0x");
1177                                 if(data == NULL)
1178                                         goto reg_proc_write_exit;
1179                                 sscanf(data, "0x%llx", &regs_val);
1180                                 if((regs_val & 0xffff00000000ULL) == 0)
1181                                         goto reg_proc_write_exit;
1182                                 read_val = regs_val & 0xffffffff;
1183                                 rk32_dsi_write_reg(dsi1, regs_val >> 32, &read_val);
1184                                 rk32_dsi_read_reg(dsi1, regs_val >> 32, &read_val);
1185                                 regs_val &= 0xffffffff;
1186                                 if(read_val != regs_val)
1187                                         MIPI_TRACE("%s fail:0x%08x\n", __func__, read_val);
1188
1189                                 data += 3;
1190                                 msleep(1);
1191                         }
1192
1193                         break;
1194                 case 'r':
1195                                 data = strstr(data, "0x");
1196                                 if(data == NULL)
1197                                         goto reg_proc_write_exit;
1198                                 sscanf(data, "0x%llx", &regs_val);
1199                                 rk32_dsi_read_reg(dsi1, (u16)regs_val, &read_val);
1200                                 MIPI_TRACE("*%04x : %08x\n", (u16)regs_val, read_val);
1201                                 msleep(1);
1202                         break;
1203
1204                 case 's':
1205                                 while(*(++data) == ' ');
1206                                 sscanf(data, "%d", &read_val);
1207                                 if(read_val == 11)
1208                                         read_val = 11289600;
1209                                 else
1210                                         read_val *= MHz;
1211
1212                                 //rk32_mipi_dsi_init_lite(dsi);
1213                         break;
1214                 case 'd':
1215                 case 'g':
1216                 case 'c':
1217                                 while(*(++data) == ' ');
1218                                 i = 0;
1219                                 MIPI_TRACE("****%d:%d\n", data-buf, count);
1220
1221                                 do {
1222                                         if(i > 31) {
1223                                                 MIPI_TRACE("payload entry is larger than 32\n");
1224                                                 break;
1225                                         }
1226                                         sscanf(data, "%x,", (unsigned int *)(str + i));   //-c 1,29,02,03,05,06,> pro
1227                                         data = strstr(data, ",");
1228                                         if(data == NULL)
1229                                                 break;
1230                                         data++;
1231                                         i++;
1232                                 } while(1);
1233                                 read_val = i;
1234
1235                                 i = 2;
1236                                 while(i--) {
1237                                         msleep(10);
1238                                         if(command == 'd')
1239                                                 rk32_mipi_dsi_send_packet(dsi1, str, read_val);
1240                                         else
1241                                                 rk32_mipi_dsi_send_packet(dsi1, str, read_val);
1242                                 }
1243                                 i = 1;
1244                                 while(i--) {
1245                                         msleep(1000);
1246                                 }
1247                         break;
1248
1249                 default:
1250                         break;
1251         }
1252
1253 reg_proc_write_exit:
1254         kfree(buf);
1255         msleep(20);
1256         return count;
1257 }
1258
1259 int reg_proc_read1(struct file *file, char __user *buff, size_t count,
1260                                         loff_t *offp)
1261 {
1262         int i = 0;
1263         u32 val = 0;
1264
1265         for(i = VERSION; i < (VERSION + (0xdc<<16)); i += 4<<16) {
1266                 val = rk32_dsi_get_bits(dsi1, i);
1267                 MIPI_TRACE("%04x: %08x\n", i>>16, val);
1268                 msleep(1);
1269         }
1270
1271         MIPI_TRACE("\n");
1272         return -1;
1273 }
1274
1275 int reg_proc_open1(struct inode *inode, struct file *file)
1276 {
1277         return 0;
1278 }
1279
1280 int reg_proc_close1(struct inode *inode, struct file *file)
1281 {
1282         return 0;
1283 }
1284
1285 struct file_operations reg_proc_fops1 = {
1286         .owner  = THIS_MODULE,
1287         .open   = reg_proc_open1,
1288         .release= reg_proc_close1,
1289         .write  = reg_proc_write1,
1290         .read   = reg_proc_read1,
1291 };
1292 #endif
1293 #if 0//def CONFIG_MIPI_DSI_LINUX
1294 static irqreturn_t rk32_mipi_dsi_irq_handler(int irq, void *data)
1295 {
1296         printk("-------rk32_mipi_dsi_irq_handler-------\n");
1297         return IRQ_HANDLED;
1298 }
1299 #endif
1300 #ifdef CONFIG_RK_3288_DSI_UBOOT
1301 int rk32_dsi_sync(void)
1302 {
1303         /*
1304                 After the core reset, DPI waits for the first VSYNC active transition to start signal sampling, including
1305                 pixel data, and preventing image transmission in the middle of a frame.
1306         */
1307     dsi_is_enable(0, 0);
1308     if (rk_mipi_get_dsi_num() ==2)
1309         dsi_is_enable(1, 0);
1310
1311     dsi_enable_video_mode(0, 1);
1312     dsi_enable_video_mode(1, 1);
1313
1314     dsi_is_enable(0, 1);
1315     if (rk_mipi_get_dsi_num() ==2)
1316         dsi_is_enable(1, 1);
1317     return 0;
1318 }
1319
1320 #endif
1321 #if 0
1322 static int dwc_phy_test_rd(struct dsi *dsi, unsigned char test_code)
1323 {
1324     int val = 0;
1325
1326     rk32_dsi_set_bits(dsi, 0x10000 | test_code, PHY_TEST_CTRL1);
1327     rk32_dsi_set_bits(dsi, 0x2, PHY_TEST_CTRL0);
1328     rk32_dsi_set_bits(dsi, 0x0, PHY_TEST_CTRL0);
1329
1330         val = rk32_dsi_get_bits(dsi, PHY_TEST_CTRL1);
1331
1332
1333     return val;
1334 }
1335 #endif
1336 static int rk32_dsi_enable(void)
1337 {
1338         MIPI_DBG("rk32_dsi_enable-------\n");
1339         dsi_init(0, 0);
1340         if (rk_mipi_get_dsi_num() ==2)
1341                 dsi_init(1, 0);
1342
1343         rk_mipi_screen_standby(0);
1344
1345         /*
1346                 After the core reset, DPI waits for the first VSYNC active transition to start signal sampling, including
1347                 pixel data, and preventing image transmission in the middle of a frame.
1348         */
1349         dsi_is_enable(0, 0);
1350         if (rk_mipi_get_dsi_num() ==2)
1351                 dsi_is_enable(1, 0);
1352
1353         dsi_enable_video_mode(0, 1);
1354         dsi_enable_video_mode(1, 1);
1355
1356         dsi_is_enable(0, 1);
1357         if (rk_mipi_get_dsi_num() ==2)
1358                 dsi_is_enable(1, 1);
1359
1360         return 0;
1361 }
1362
1363 #ifdef CONFIG_MIPI_DSI_LINUX
1364 static int rk32_dsi_disable(void)
1365 {
1366         MIPI_DBG("rk32_dsi_disable-------\n");
1367
1368         rk_mipi_screen_standby(1);
1369         dsi_power_off(0);
1370         if (rk_mipi_get_dsi_num() ==2)
1371                 dsi_power_off(1);
1372
1373         return 0;
1374 }
1375
1376 static struct rk_fb_trsm_ops trsm_dsi_ops =
1377 {
1378         .enable = rk32_dsi_enable,
1379         .disable = rk32_dsi_disable,
1380 };
1381 #endif
1382 static void rk32_init_phy_mode(int lcdc_id)
1383 {
1384         int val0 = 0, val1 = 0;
1385
1386         MIPI_DBG("rk32_init_phy_mode----------lcdc_id=%d\n",lcdc_id);
1387         //D-PHY mode select
1388         if( rk_mipi_get_dsi_num() ==1 ){
1389
1390                 if(lcdc_id == 1)
1391                         //val0 =0x1 << 25 | 0x1 << 9;
1392                         val0 = 0x1 << 22 | 0x1 << 6;  //1'b1: VOP LIT output to DSI host0;1'b0: VOP BIG output to DSI host0
1393                 else
1394                         val0 = 0x1 << 22 | 0x0 << 6;
1395
1396                 writel_relaxed(val0, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
1397         }
1398         else{
1399                 if(lcdc_id == 1){
1400                         val0 = 0x1 << 25 | 0x1 <<  9 | 0x1 << 22 | 0x1 <<  6;
1401                         val1 = 0x1 << 31 | 0x1 << 30 | 0x0 << 15 | 0x1 << 14;
1402                 }
1403                 else{
1404                         val0 = 0x1 << 25 | 0x0 <<  9 | 0x1 << 22 | 0x0 << 14;
1405                         val1 = 0x1 << 31 | 0x1 << 30 | 0x0 << 15 | 0x1 << 14;
1406                 }
1407
1408                 writel_relaxed(val0, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
1409                 writel_relaxed(val1, RK_GRF_VIRT + RK3288_GRF_SOC_CON14);
1410         }
1411 }
1412 #ifdef CONFIG_RK_3288_DSI_UBOOT
1413 #ifdef CONFIG_OF_LIBFDT
1414 int rk_dsi_host_parse_dt(const void *blob, struct dsi *dsi)
1415 {
1416         int node;
1417
1418         node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_DSIHOST);
1419         if(node<0) {
1420                 printf("mipi dts get node failed, node = %d.\n", node);
1421                 return -1;
1422         }
1423
1424         do{
1425                 if(fdtdec_get_int(blob, node, "rockchip,prop", -1) != dsi->dsi_id){
1426                         node = fdtdec_next_compatible(blob, node, COMPAT_ROCKCHIP_DSIHOST);
1427                         if(node<0) {
1428                                 printf("mipi dts get node failed, node = %d.\n", node);
1429                                 return -1;
1430                         }
1431                 }else{
1432                         break;
1433                 }
1434         }while(1);
1435
1436         //fdtdec_get_addr_size(blob,node,"reg",&length);
1437         dsi->host.membase = (void __iomem *)fdtdec_get_int(blob, node, "reg", -1);
1438         //fdt_getprop(blob, node, "reg", &length);
1439         MIPI_DBG("dsi->host.membase 0x%08lx.\n",(unsigned long)dsi->host.membase);
1440         return 0;
1441 }
1442 #endif /* #ifdef CONFIG_OF_LIBFDT */
1443
1444 int rk32_mipi_enable(vidinfo_t *vid)
1445 {
1446         int ret = 0;
1447         struct dsi *dsi;
1448         struct mipi_dsi_ops *ops;
1449         struct rk_screen *screen;
1450         struct mipi_dsi_screen *dsi_screen;
1451         static int id = 0;
1452
1453         rk_mipi_screen_probe();
1454
1455         do{
1456                 dsi = calloc(1, sizeof(struct dsi));
1457                 if(!dsi) {
1458                   MIPI_DBG("request struct dsi.%d fail!\n",id);
1459                   return -ENOMEM;
1460                 }
1461
1462                 dsi->dsi_id = id;
1463 #ifdef CONFIG_OF_LIBFDT
1464                 rk_dsi_host_parse_dt(gd->fdt_blob,dsi);
1465 #endif /* #ifdef CONFIG_OF_LIBFDT */
1466                 screen = calloc(1, sizeof(struct rk_screen));
1467                 if(!screen) {
1468                   MIPI_DBG("request struct rk_screen fail!\n");
1469                 }
1470                 //rk_fb_get_prmry_screen(screen);
1471                 ops = &dsi->ops;
1472                 ops->dsi = dsi;
1473                 ops->id = DWC_DSI_VERSION,
1474                 ops->get_id = rk32_mipi_dsi_get_id,
1475                 ops->dsi_send_packet = rk32_mipi_dsi_send_packet;
1476                 ops->dsi_read_dcs_packet = rk32_mipi_dsi_read_dcs_packet,
1477                 ops->dsi_enable_video_mode = rk32_mipi_dsi_enable_video_mode,
1478                 ops->dsi_enable_command_mode = rk32_mipi_dsi_enable_command_mode,
1479                 ops->dsi_enable_hs_clk = rk32_mipi_dsi_enable_hs_clk,
1480                 ops->dsi_is_active = rk32_mipi_dsi_is_active,
1481                 ops->dsi_is_enable= rk32_mipi_dsi_is_enable,
1482                 ops->power_up = rk32_mipi_dsi_power_up,
1483                 ops->power_down = rk32_mipi_dsi_power_down,
1484                 ops->dsi_init = rk_mipi_dsi_init,
1485
1486                 dsi_screen = &dsi->screen;
1487                 dsi_screen->type = screen->type = vid->screen_type;
1488                 dsi_screen->face = screen->face = vid->lcd_face;
1489                 //dsi_screen->lcdc_id = screen->lcdc_id;
1490                 //dsi_screen->screen_id = screen->screen_id;
1491                 //printf("xjh:vid->vl_freq %d vid->real_freq %d\n",vid->vl_freq, vid->real_freq);
1492                 //dsi_screen->pixclock = screen->mode.pixclock = vid->vl_freq *MHZ ;
1493                 dsi_screen->pixclock = screen->mode.pixclock = vid->real_freq;
1494                 dsi_screen->left_margin = screen->mode.left_margin = vid->vl_hbpd;
1495                 dsi_screen->right_margin = screen->mode.right_margin = vid->vl_hfpd;
1496                 dsi_screen->hsync_len = screen->mode.hsync_len = vid->vl_hspw;
1497                 dsi_screen->upper_margin = screen->mode.upper_margin = vid->vl_vbpd;
1498                 dsi_screen->lower_margin = screen->mode.lower_margin = vid->vl_vfpd;
1499                 dsi_screen->vsync_len = screen->mode.vsync_len = vid->vl_vspw;
1500                 dsi_screen->x_res = screen->mode.xres = vid->vl_width;
1501                 dsi_screen->y_res = screen->mode.yres = vid->vl_height;
1502                 //dsi_screen->pin_hsync = screen->pin_hsync;
1503                 //dsi_screen->pin_vsync = screen->pin_vsync;
1504                 //dsi_screen->pin_den = screen->pin_den;
1505                 //dsi_screen->pin_dclk = screen->pin_dclk;
1506                 dsi_screen->dsi_lane = rk_mipi_get_dsi_lane();
1507                 //  dsi_screen->dsi_video_mode = screen->dsi_video_mode; //no sure
1508                 dsi_screen->dsi_lane = rk_mipi_get_dsi_lane();
1509                 dsi_screen->hs_tx_clk = rk_mipi_get_dsi_clk();
1510                 dsi_screen->lcdc_id = 1;
1511                 dsi->dsi_id = id++;//of_alias_get_id(pdev->dev.of_node, "dsi");
1512                 sprintf(ops->name, "rk_mipi_dsi.%d", dsi->dsi_id);
1513
1514                 ret = rk_mipi_dsi_probe(dsi);
1515                 if(ret) {
1516                   MIPI_DBG("rk mipi_dsi probe fail!\n");
1517                   MIPI_DBG("%s\n", RK_MIPI_DSI_VERSION_AND_TIME);
1518                 }
1519
1520                 if(id == 1){
1521                   rk32_init_phy_mode(dsi_screen->lcdc_id);
1522                   //rk_fb_trsm_ops_register(&trsm_dsi_ops, SCREEN_MIPI);
1523                   dsi0 = dsi;
1524                 }else{
1525                   dsi1 = dsi;
1526                 }
1527                 //if(vid->screen_type == SCREEN_DUAL_MIPI){
1528                 if( rk_mipi_get_dsi_num() == 2 ){
1529                     if(id==2)
1530                         break;
1531                 }else
1532                     break;
1533
1534         }while(1);
1535
1536         rk32_dsi_enable();
1537
1538 #if 0
1539
1540         int reg = 0;
1541
1542     // printf("MIPI HOST dump regs\n");
1543      for(reg=0x0;reg<0xc4;){
1544         // printf("reg[0x%04x]=0x%08x ",reg,
1545         // __raw_readl(dsi0->host.membase + reg));
1546          __raw_readl(dsi0->host.membase + reg);
1547          reg+=4;
1548 //       if(reg%16 == 0)
1549 //               printf("\n");
1550      }
1551
1552         MIPI_DBG("rk mipi_dsi probe success!\n");
1553         MIPI_DBG("%s\n", RK_MIPI_DSI_VERSION_AND_TIME);
1554         #endif
1555         return 0;
1556
1557 }
1558 #endif
1559 #ifdef CONFIG_MIPI_DSI_LINUX
1560 int rk32_mipi_power_down_DDR(void)
1561 {
1562         dsi_is_enable(0, 0);
1563         if (rk_mipi_get_dsi_num() ==2)
1564                 dsi_is_enable(1, 0);
1565         return 0;
1566 }
1567 EXPORT_SYMBOL(rk32_mipi_power_down_DDR);
1568 int rk32_mipi_power_up_DDR(void)
1569 {
1570         dsi_is_enable(0, 0);
1571         if (rk_mipi_get_dsi_num() ==2)
1572                 dsi_is_enable(1, 0);
1573         dsi_enable_video_mode(0, 1);
1574         dsi_enable_video_mode(1, 1);
1575         dsi_is_enable(0, 1);
1576         if (rk_mipi_get_dsi_num() ==2)
1577                 dsi_is_enable(1, 1);
1578         return 0;
1579 }
1580 EXPORT_SYMBOL(rk32_mipi_power_up_DDR);
1581
1582 static int rk32_mipi_dsi_probe(struct platform_device *pdev)
1583 {
1584         int ret = 0;
1585         static int id = 0;
1586         struct dsi *dsi;
1587         struct mipi_dsi_ops *ops;
1588         struct rk_screen *screen;
1589         struct mipi_dsi_screen *dsi_screen;
1590         struct resource *res_host;
1591
1592         dsi = devm_kzalloc(&pdev->dev, sizeof(struct dsi), GFP_KERNEL);
1593         if(!dsi) {
1594                 dev_err(&pdev->dev,"request struct dsi fail!\n");
1595                 return -ENOMEM;
1596         }
1597
1598         res_host = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1599         dsi->host.membase = devm_request_and_ioremap(&pdev->dev, res_host);
1600         if (!dsi->host.membase){
1601                 dev_err(&pdev->dev, "get resource mipi host membase fail!\n");
1602                 return -ENOMEM;
1603         }
1604
1605         dsi->phy.refclk  = devm_clk_get(&pdev->dev, "clk_mipi_24m");
1606         if (unlikely(IS_ERR(dsi->phy.refclk))) {
1607                 dev_err(&pdev->dev, "get clk_mipi_24m clock fail\n");
1608                 return PTR_ERR(dsi->phy.refclk);
1609         }
1610
1611         dsi->dsi_pclk = devm_clk_get(&pdev->dev, "pclk_mipi_dsi");
1612         if (unlikely(IS_ERR(dsi->dsi_pclk))) {
1613                 dev_err(&pdev->dev, "get pclk_mipi_dsi clock fail\n");
1614                 return PTR_ERR(dsi->dsi_pclk);
1615         }
1616
1617         dsi->dsi_pd = devm_clk_get(&pdev->dev, "pd_mipi_dsi");
1618         if (unlikely(IS_ERR(dsi->dsi_pd))) {
1619                 dev_err(&pdev->dev, "get pd_mipi_dsi clock fail\n");
1620                 return PTR_ERR(dsi->dsi_pd);
1621         }
1622
1623         dsi->host.irq = platform_get_irq(pdev, 0);
1624         if (dsi->host.irq < 0) {
1625                 dev_err(&pdev->dev, "no irq resource?\n");
1626                 return dsi->host.irq;
1627         }
1628
1629         //ret = request_irq(dsi->host.irq, rk32_mipi_dsi_irq_handler, 0,dev_name(&pdev->dev), dsi);
1630         //if(ret) {
1631         //      dev_err(&pdev->dev, "request mipi_dsi irq fail\n");
1632         //      return -EINVAL;
1633         //}
1634         printk("dsi->host.irq =%d\n",dsi->host.irq);
1635
1636         disable_irq(dsi->host.irq);
1637
1638         screen = devm_kzalloc(&pdev->dev, sizeof(struct rk_screen), GFP_KERNEL);
1639         if(!screen) {
1640                 dev_err(&pdev->dev,"request struct rk_screen fail!\n");
1641                 return -1;
1642         }
1643         rk_fb_get_prmry_screen(screen);
1644
1645         dsi->pdev = pdev;
1646         ops = &dsi->ops;
1647         ops->dsi = dsi;
1648         ops->id = DWC_DSI_VERSION,
1649         ops->get_id = rk32_mipi_dsi_get_id,
1650         ops->dsi_send_packet = rk32_mipi_dsi_send_packet;
1651         ops->dsi_read_dcs_packet = rk32_mipi_dsi_read_dcs_packet,
1652         ops->dsi_enable_video_mode = rk32_mipi_dsi_enable_video_mode,
1653         ops->dsi_enable_command_mode = rk32_mipi_dsi_enable_command_mode,
1654         ops->dsi_enable_hs_clk = rk32_mipi_dsi_enable_hs_clk,
1655         ops->dsi_is_active = rk32_mipi_dsi_is_active,
1656         ops->dsi_is_enable= rk32_mipi_dsi_is_enable,
1657         ops->power_up = rk32_mipi_dsi_power_up,
1658         ops->power_down = rk32_mipi_dsi_power_down,
1659         ops->dsi_init = rk_mipi_dsi_init,
1660
1661         dsi_screen = &dsi->screen;
1662         dsi_screen->type = screen->type;
1663         dsi_screen->face = screen->face;
1664         dsi_screen->lcdc_id = screen->lcdc_id;
1665         dsi_screen->screen_id = screen->screen_id;
1666         dsi_screen->pixclock = screen->mode.pixclock;
1667         dsi_screen->left_margin = screen->mode.left_margin;
1668         dsi_screen->right_margin = screen->mode.right_margin;
1669         dsi_screen->hsync_len = screen->mode.hsync_len;
1670         dsi_screen->upper_margin = screen->mode.upper_margin;
1671         dsi_screen->lower_margin = screen->mode.lower_margin;
1672         dsi_screen->vsync_len = screen->mode.vsync_len;
1673         dsi_screen->x_res = screen->mode.xres;
1674         dsi_screen->y_res = screen->mode.yres;
1675         dsi_screen->pin_hsync = screen->pin_hsync;
1676         dsi_screen->pin_vsync = screen->pin_vsync;
1677         dsi_screen->pin_den = screen->pin_den;
1678         dsi_screen->pin_dclk = screen->pin_dclk;
1679         dsi_screen->dsi_lane = rk_mipi_get_dsi_lane();
1680 //  dsi_screen->dsi_video_mode = screen->dsi_video_mode; //no sure
1681         dsi_screen->dsi_lane = rk_mipi_get_dsi_lane();
1682         dsi_screen->hs_tx_clk = rk_mipi_get_dsi_clk();
1683         dsi_screen->lcdc_id = 1;
1684
1685         dsi->dsi_id = id++;
1686
1687         sprintf(ops->name, "rk_mipi_dsi.%d", dsi->dsi_id);
1688         platform_set_drvdata(pdev, dsi);
1689
1690         ret = rk_mipi_dsi_probe(dsi);
1691         if(ret) {
1692                 dev_err(&pdev->dev,"rk mipi_dsi probe fail!\n");
1693                 dev_err(&pdev->dev,"%s\n", RK_MIPI_DSI_VERSION_AND_TIME);
1694                 return -1;
1695         }
1696
1697         if(id == 1){
1698
1699                 if(!support_uboot_display())
1700                         rk32_init_phy_mode(dsi_screen->lcdc_id);
1701                 rk_fb_trsm_ops_register(&trsm_dsi_ops, SCREEN_MIPI);
1702
1703 #ifdef MIPI_DSI_REGISTER_IO
1704                 debugfs_create_file("mipidsi0", S_IFREG | S_IRUGO, dsi->debugfs_dir, dsi,
1705                                                         &reg_proc_fops);
1706 #endif
1707                 dsi0 = dsi;
1708         }else{
1709                 dsi1 = dsi;
1710
1711 #ifdef MIPI_DSI_REGISTER_IO
1712         debugfs_create_file("mipidsi1", S_IFREG | S_IRUGO, dsi->debugfs_dir, dsi,
1713                                                         &reg_proc_fops1);
1714 #endif
1715
1716         }
1717
1718     if(support_uboot_display()){
1719             clk_prepare_enable(dsi->phy.refclk);
1720             clk_prepare_enable(dsi->dsi_pclk);
1721             clk_prepare_enable(dsi->dsi_pd);
1722             udelay(10);
1723     }
1724         dev_info(&pdev->dev,"rk mipi_dsi probe success!\n");
1725         dev_info(&pdev->dev,"%s\n", RK_MIPI_DSI_VERSION_AND_TIME);
1726
1727         return ret;
1728 }
1729
1730 #ifdef CONFIG_OF
1731 static const struct of_device_id of_rk_mipi_dsi_match[] = {
1732         { .compatible = "rockchip,rk32-dsi" },
1733         { /* Sentinel */ }
1734 };
1735 #endif
1736
1737 static struct platform_driver rk32_mipi_dsi_driver = {
1738         .probe          = rk32_mipi_dsi_probe,
1739         .driver         = {
1740                 .name   = "rk32-mipi",
1741                 .owner  = THIS_MODULE,
1742 #ifdef CONFIG_OF
1743                 .of_match_table = of_rk_mipi_dsi_match,
1744 #endif
1745         },
1746 };
1747
1748 static int __init rk32_mipi_dsi_init(void)
1749 {
1750         return platform_driver_register(&rk32_mipi_dsi_driver);
1751 }
1752 fs_initcall(rk32_mipi_dsi_init);
1753
1754 static void __exit rk32_mipi_dsi_exit(void)
1755 {
1756         platform_driver_unregister(&rk32_mipi_dsi_driver);
1757 }
1758 module_exit(rk32_mipi_dsi_exit);
1759 #endif