2 *RockChip DP (Display port) register interface driver.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
10 #include <linux/device.h>
11 #include <linux/delay.h>
13 #include <linux/rockchip/cpu.h>
14 #include <linux/rockchip/iomap.h>
15 #include <linux/rockchip/grf.h>
19 void rk32_edp_enable_video_mute(struct rk32_edp *edp, bool enable)
24 val = readl(edp->regs + VIDEO_CTL_1);
26 writel(val, edp->regs + VIDEO_CTL_1);
28 val = readl(edp->regs + VIDEO_CTL_1);
30 writel(val, edp->regs + VIDEO_CTL_1);
34 void rk32_edp_stop_video(struct rk32_edp *edp)
38 val = readl(edp->regs + VIDEO_CTL_1);
40 writel(val, edp->regs + VIDEO_CTL_1);
43 void rk32_edp_lane_swap(struct rk32_edp *edp, bool enable)
49 val = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
50 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
52 val = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
53 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
55 writel(val, edp->regs + LANE_MAP);
58 void rk32_edp_init_refclk(struct rk32_edp *edp)
61 /*struct rk32_edp_platdata *pdata = edp->dev->platform_data;
62 struct analog_param *analog_param = pdata->analog_param;
64 val = TX_TERMINAL_CTRL_50_OHM;
65 writel(val, edp->regs + ANALOG_CTL_1);*/
68 writel(val, edp->regs + ANALOG_CTL_2);
71 writel(val, edp->regs + PLL_REG_1);
74 writel(val, edp->regs + PLL_REG_2);
77 writel(val, edp->regs + PLL_REG_3);
80 writel(val, edp->regs + PLL_REG_4);
83 writel(val, edp->regs + PLL_REG_5);
86 writel(val, edp->regs + SSC_REG);
88 writel(val, edp->regs + TX_REG_COMMON);
90 writel(val, edp->regs + DP_AUX);
92 writel(val, edp->regs + DP_BIAS);
94 writel(val, edp->regs + DP_RESERVE2);
97 /*val = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
98 writel(val, edp->regs + ANALOG_CTL_3);
101 val = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
102 TX_CUR1_2X | TX_CUR_16_MA;
103 writel(val, edp->regs + PLL_FILTER_CTL_1);
105 val = CH3_AMP_400_MV | CH2_AMP_400_MV |
106 CH1_AMP_400_MV | CH0_AMP_400_MV;
107 writel(val, edp->regs + TX_AMP_TUNING_CTL);
111 val = PD_RING_OSC | TX_CUR1_2X | TX_CUR_16_MA;
112 switch (analog_param->aux_tx_terminal_resistor) {
113 case AUX_TX_37_5_OHM:
114 val |= AUX_TERMINAL_CTRL_37_5_OHM;
117 val |= AUX_TERMINAL_CTRL_45_OHM;
120 val |= AUX_TERMINAL_CTRL_50_OHM;
123 val |= AUX_TERMINAL_CTRL_65_OHM;
126 writel(val, edp->regs + PLL_FILTER_CTL_1);
128 tx_amp = analog_param->tx_amplitude;
129 if (tx_amp < 200000 || tx_amp > 500000) {
131 "TX amp out of range, defaulting to 400mV\n");
135 tx_amp = ((tx_amp - 400000) / 12500) & 0x1f;
137 val = (tx_amp << CH3_AMP_SHIFT) | (tx_amp << CH2_AMP_SHIFT) |
138 (tx_amp << CH1_AMP_SHIFT) | (tx_amp << CH0_AMP_SHIFT);
139 writel(val, edp->regs + TX_AMP_TUNING_CTL);
143 void rk32_edp_init_interrupt(struct rk32_edp *edp)
145 /* Set interrupt pin assertion polarity as high */
146 writel(INT_POL, edp->regs + INT_CTL);
148 /* Clear pending valisers */
149 writel(0xff, edp->regs + COMMON_INT_STA_1);
150 writel(0x4f, edp->regs + COMMON_INT_STA_2);
151 writel(0xff, edp->regs + COMMON_INT_STA_3);
152 writel(0x27, edp->regs + COMMON_INT_STA_4);
154 writel(0x7f, edp->regs + DP_INT_STA);
156 /* 0:mask,1: unmask */
157 writel(0x00, edp->regs + COMMON_INT_MASK_1);
158 writel(0x00, edp->regs + COMMON_INT_MASK_2);
159 writel(0x00, edp->regs + COMMON_INT_MASK_3);
160 writel(0x00, edp->regs + COMMON_INT_MASK_4);
161 writel(0x00, edp->regs + DP_INT_STA_MASK);
164 void rk32_edp_reset(struct rk32_edp *edp)
168 rk32_edp_stop_video(edp);
169 rk32_edp_enable_video_mute(edp, 0);
171 val = VID_CAP_FUNC_EN_N | AUD_FIFO_FUNC_EN_N |
172 AUD_FUNC_EN_N | HDCP_FUNC_EN_N | SW_FUNC_EN_N;
173 writel(val, edp->regs + FUNC_EN_1);
175 val = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
176 SERDES_FIFO_FUNC_EN_N |
177 LS_CLK_DOMAIN_FUNC_EN_N;
178 writel(val, edp->regs + FUNC_EN_2);
182 rk32_edp_lane_swap(edp, 0);
184 writel(0x0, edp->regs + SYS_CTL_1);
185 writel(0x40, edp->regs + SYS_CTL_2);
186 writel(0x0, edp->regs + SYS_CTL_3);
187 writel(0x0, edp->regs + SYS_CTL_4);
189 writel(0x0, edp->regs + PKT_SEND_CTL);
190 writel(0x0, edp->regs + HDCP_CTL);
192 writel(0x5e, edp->regs + HPD_DEGLITCH_L);
193 writel(0x1a, edp->regs + HPD_DEGLITCH_H);
195 writel(0x10, edp->regs + LINK_DEBUG_CTL);
197 writel(0x0, edp->regs + VIDEO_FIFO_THRD);
198 writel(0x20, edp->regs + AUDIO_MARGIN);
200 writel(0x4, edp->regs + M_VID_GEN_FILTER_TH);
201 writel(0x2, edp->regs + M_AUD_GEN_FILTER_TH);
203 writel(0x0, edp->regs + SOC_GENERAL_CTL);
207 void rk32_edp_config_interrupt(struct rk32_edp *edp)
211 /* 0: mask, 1: unmask */
213 writel(val, edp->regs + COMMON_INT_MASK_1);
215 writel(val, edp->regs + COMMON_INT_MASK_2);
217 writel(val, edp->regs + COMMON_INT_MASK_3);
219 writel(val, edp->regs + COMMON_INT_MASK_4);
221 writel(val, edp->regs + DP_INT_STA_MASK);
224 u32 rk32_edp_get_pll_lock_status(struct rk32_edp *edp)
228 val = readl(edp->regs + DEBUG_CTL);
230 return DP_PLL_LOCKED;
232 return DP_PLL_UNLOCKED;
236 void rk32_edp_analog_power_ctr(struct rk32_edp *edp, bool enable)
241 val = PD_EXP_BG | PD_AUX | PD_PLL |
242 PD_CH3 | PD_CH2 | PD_CH1 | PD_CH0;
243 writel(val, edp->regs + DP_PWRDN);
245 writel(0x0, edp->regs + DP_PWRDN);
247 val = PD_EXP_BG | PD_AUX | PD_PLL |
248 PD_CH3 | PD_CH2 | PD_CH1 | PD_CH0;
249 writel(val, edp->regs + DP_PWRDN);
254 void rk32_edp_init_analog_func(struct rk32_edp *edp)
258 rk32_edp_analog_power_ctr(edp, 1);
261 writel(val, edp->regs + COMMON_INT_STA_1);
263 val = readl(edp->regs + DEBUG_CTL);
264 val &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
265 writel(val, edp->regs + DEBUG_CTL);
269 if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_LOCKED) {
270 dev_info(edp->dev, "edp pll locked\n");
278 /* Enable Serdes FIFO function and Link symbol clock domain module */
279 val = readl(edp->regs + FUNC_EN_2);
280 val &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
281 | AUX_FUNC_EN_N | SSC_FUNC_EN_N);
282 writel(val, edp->regs + FUNC_EN_2);
285 void rk32_edp_init_hpd(struct rk32_edp *edp)
289 val = HOTPLUG_CHG | HPD_LOST | PLUG;
290 writel(val, edp->regs + COMMON_INT_STA_4);
293 writel(val, edp->regs + DP_INT_STA);
295 val = readl(edp->regs + SYS_CTL_3);
296 val |= (F_HPD | HPD_CTRL);
297 writel(val, edp->regs + SYS_CTL_3);
300 void rk32_edp_reset_aux(struct rk32_edp *edp)
304 /* Disable AUX channel module */
305 val = readl(edp->regs + FUNC_EN_2);
306 val |= AUX_FUNC_EN_N;
307 writel(val, edp->regs + FUNC_EN_2);
310 void rk32_edp_init_aux(struct rk32_edp *edp)
314 /* Clear inerrupts related to AUX channel */
315 val = RPLY_RECEIV | AUX_ERR;
316 writel(val, edp->regs + DP_INT_STA);
318 rk32_edp_reset_aux(edp);
320 /* Disable AUX transaction H/W retry */
321 /*val = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
322 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
323 writel(val, edp->regs + AUX_HW_RETRY_CTL) ;*/
325 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
326 val = DEFER_CTRL_EN | DEFER_COUNT(1);
327 writel(val, edp->regs + AUX_CH_DEFER_CTL);
329 /* Enable AUX channel module */
330 val = readl(edp->regs + FUNC_EN_2);
331 val &= ~AUX_FUNC_EN_N;
332 writel(val, edp->regs + FUNC_EN_2);
335 int rk32_edp_get_plug_in_status(struct rk32_edp *edp)
339 val = readl(edp->regs + SYS_CTL_3);
340 if (val & HPD_STATUS)
346 void rk32_edp_enable_sw_function(struct rk32_edp *edp)
349 val = readl(edp->regs + FUNC_EN_1);
350 val &= ~SW_FUNC_EN_N;
351 writel(val, edp->regs + FUNC_EN_1);
354 int rk32_edp_start_aux_transaction(struct rk32_edp *edp)
358 int timeout_loop = 0;
361 /* Enable AUX CH operation */
362 val = readl(edp->regs + AUX_CH_CTL_2);
364 writel(val, edp->regs + AUX_CH_CTL_2);
366 /* Is AUX CH operation enabled? */
367 val = readl(edp->regs + AUX_CH_CTL_2);
368 while (val & AUX_EN) {
370 if ((DP_TIMEOUT_LOOP_CNT * 10) < aux_timeout) {
371 dev_err(edp->dev, "AUX CH enable timeout!\n");
374 val = readl(edp->regs + AUX_CH_CTL_2);
378 /* Is AUX CH command redply received? */
379 val = readl(edp->regs + DP_INT_STA);
380 while (!(val & RPLY_RECEIV)) {
382 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
383 dev_err(edp->dev, "AUX CH command redply failed!\n");
386 val = readl(edp->regs + DP_INT_STA);
390 /* Clear interrupt source for AUX CH command redply */
391 writel(RPLY_RECEIV, edp->regs + DP_INT_STA);
393 /* Clear interrupt source for AUX CH access error */
394 val = readl(edp->regs + DP_INT_STA);
396 writel(AUX_ERR, edp->regs + DP_INT_STA);
400 /* Check AUX CH error access status */
401 val = readl(edp->regs + AUX_CH_STA);
402 if ((val & AUX_STATUS_MASK) != 0) {
403 dev_err(edp->dev, "AUX CH error happens: %d\n\n",
404 val & AUX_STATUS_MASK);
411 int rk32_edp_write_byte_to_dpcd(struct rk32_edp *edp,
412 unsigned int val_addr,
419 for (i = 0; i < 3; i++) {
420 /* Clear AUX CH data buffer */
422 writel(val, edp->regs + BUFFER_DATA_CTL);
424 /* Select DPCD device address */
425 val = AUX_ADDR_7_0(val_addr);
426 writel(val, edp->regs + DP_AUX_ADDR_7_0);
427 val = AUX_ADDR_15_8(val_addr);
428 writel(val, edp->regs + DP_AUX_ADDR_15_8);
429 val = AUX_ADDR_19_16(val_addr);
430 writel(val, edp->regs + DP_AUX_ADDR_19_16);
432 /* Write data buffer */
433 val = (unsigned int)data;
434 writel(val, edp->regs + BUF_DATA_0);
437 * Set DisplayPort transaction and write 1 byte
438 * If bit 3 is 1, DisplayPort transaction.
439 * If Bit 3 is 0, I2C transaction.
441 val = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
442 writel(val, edp->regs + AUX_CH_CTL_1);
444 /* Start AUX transaction */
445 retval = rk32_edp_start_aux_transaction(edp);
449 dev_dbg(edp->dev, "Aux Transaction fail!\n");
455 int rk32_edp_read_byte_from_dpcd(struct rk32_edp *edp,
456 unsigned int val_addr,
463 for (i = 0; i < 10; i++) {
464 /* Clear AUX CH data buffer */
466 writel(val, edp->regs + BUFFER_DATA_CTL);
468 /* Select DPCD device address */
469 val = AUX_ADDR_7_0(val_addr);
470 writel(val, edp->regs + DP_AUX_ADDR_7_0);
471 val = AUX_ADDR_15_8(val_addr);
472 writel(val, edp->regs + DP_AUX_ADDR_15_8);
473 val = AUX_ADDR_19_16(val_addr);
474 writel(val, edp->regs + DP_AUX_ADDR_19_16);
477 * Set DisplayPort transaction and read 1 byte
478 * If bit 3 is 1, DisplayPort transaction.
479 * If Bit 3 is 0, I2C transaction.
481 val = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
482 writel(val, edp->regs + AUX_CH_CTL_1);
484 /* Start AUX transaction */
485 retval = rk32_edp_start_aux_transaction(edp);
489 dev_dbg(edp->dev, "Aux Transaction fail!\n");
492 /* Read data buffer */
493 val = readl(edp->regs + BUF_DATA_0);
494 *data = (unsigned char)(val & 0xff);
499 int rk32_edp_write_bytes_to_dpcd(struct rk32_edp *edp,
500 unsigned int val_addr,
502 unsigned char data[])
505 unsigned int start_offset;
506 unsigned int cur_data_count;
507 unsigned int cur_data_idx;
511 /* Clear AUX CH data buffer */
513 writel(val, edp->regs + BUFFER_DATA_CTL);
516 while (start_offset < count) {
517 /* Buffer size of AUX CH is 16 * 4bytes */
518 if ((count - start_offset) > 16)
521 cur_data_count = count - start_offset;
523 for (i = 0; i < 10; i++) {
524 /* Select DPCD device address */
525 val = AUX_ADDR_7_0(val_addr + start_offset);
526 writel(val, edp->regs + DP_AUX_ADDR_7_0);
527 val = AUX_ADDR_15_8(val_addr + start_offset);
528 writel(val, edp->regs + DP_AUX_ADDR_15_8);
529 val = AUX_ADDR_19_16(val_addr + start_offset);
530 writel(val, edp->regs + DP_AUX_ADDR_19_16);
532 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
534 val = data[start_offset + cur_data_idx];
535 writel(val, edp->regs + BUF_DATA_0
540 * Set DisplayPort transaction and write
541 * If bit 3 is 1, DisplayPort transaction.
542 * If Bit 3 is 0, I2C transaction.
544 val = AUX_LENGTH(cur_data_count) |
545 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
546 writel(val, edp->regs + AUX_CH_CTL_1);
548 /* Start AUX transaction */
549 retval = rk32_edp_start_aux_transaction(edp);
553 dev_dbg(edp->dev, "Aux Transaction fail!\n");
556 start_offset += cur_data_count;
562 int rk32_edp_read_bytes_from_dpcd(struct rk32_edp *edp,
563 unsigned int val_addr,
565 unsigned char data[])
568 unsigned int start_offset;
569 unsigned int cur_data_count;
570 unsigned int cur_data_idx;
574 /* Clear AUX CH data buffer */
576 writel(val, edp->regs + BUFFER_DATA_CTL);
579 while (start_offset < count) {
580 /* Buffer size of AUX CH is 16 * 4bytes */
581 if ((count - start_offset) > 16)
584 cur_data_count = count - start_offset;
586 /* AUX CH Request Transaction process */
587 for (i = 0; i < 10; i++) {
588 /* Select DPCD device address */
589 val = AUX_ADDR_7_0(val_addr + start_offset);
590 writel(val, edp->regs + DP_AUX_ADDR_7_0);
591 val = AUX_ADDR_15_8(val_addr + start_offset);
592 writel(val, edp->regs + DP_AUX_ADDR_15_8);
593 val = AUX_ADDR_19_16(val_addr + start_offset);
594 writel(val, edp->regs + DP_AUX_ADDR_19_16);
597 * Set DisplayPort transaction and read
598 * If bit 3 is 1, DisplayPort transaction.
599 * If Bit 3 is 0, I2C transaction.
601 val = AUX_LENGTH(cur_data_count) |
602 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
603 writel(val, edp->regs + AUX_CH_CTL_1);
605 /* Start AUX transaction */
606 retval = rk32_edp_start_aux_transaction(edp);
610 dev_dbg(edp->dev, "Aux Transaction fail!\n");
613 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
615 val = readl(edp->regs + BUF_DATA_0
617 data[start_offset + cur_data_idx] =
621 start_offset += cur_data_count;
627 int rk32_edp_select_i2c_device(struct rk32_edp *edp,
628 unsigned int device_addr,
629 unsigned int val_addr)
634 /* Set EDID device address */
636 writel(val, edp->regs + DP_AUX_ADDR_7_0);
637 writel(0x0, edp->regs + DP_AUX_ADDR_15_8);
638 writel(0x0, edp->regs + DP_AUX_ADDR_19_16);
640 /* Set offset from base address of EDID device */
641 writel(val_addr, edp->regs + BUF_DATA_0);
644 * Set I2C transaction and write address
645 * If bit 3 is 1, DisplayPort transaction.
646 * If Bit 3 is 0, I2C transaction.
648 val = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
650 writel(val, edp->regs + AUX_CH_CTL_1);
652 /* Start AUX transaction */
653 retval = rk32_edp_start_aux_transaction(edp);
655 dev_dbg(edp->dev, "Aux Transaction fail!\n");
660 int rk32_edp_read_byte_from_i2c(struct rk32_edp *edp,
661 unsigned int device_addr,
662 unsigned int val_addr,
669 for (i = 0; i < 10; i++) {
670 /* Clear AUX CH data buffer */
672 writel(val, edp->regs + BUFFER_DATA_CTL);
674 /* Select EDID device */
675 retval = rk32_edp_select_i2c_device(edp, device_addr, val_addr);
677 dev_err(edp->dev, "Select EDID device fail!\n");
682 * Set I2C transaction and read data
683 * If bit 3 is 1, DisplayPort transaction.
684 * If Bit 3 is 0, I2C transaction.
686 val = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_READ;
687 writel(val, edp->regs + AUX_CH_CTL_1);
689 /* Start AUX transaction */
690 retval = rk32_edp_start_aux_transaction(edp);
694 dev_dbg(edp->dev, "Aux Transaction fail!\n");
699 *data = readl(edp->regs + BUF_DATA_0);
704 int rk32_edp_read_bytes_from_i2c(struct rk32_edp *edp,
705 unsigned int device_addr,
706 unsigned int val_addr,
708 unsigned char edid[])
712 unsigned int cur_data_idx;
713 unsigned int defer = 0;
716 for (i = 0; i < count; i += 16) {
717 for (j = 0; j < 100; j++) {
718 /* Clear AUX CH data buffer */
720 writel(val, edp->regs + BUFFER_DATA_CTL);
722 /* Set normal AUX CH command */
723 val = readl(edp->regs + AUX_CH_CTL_2);
725 writel(val, edp->regs + AUX_CH_CTL_2);
728 * If Rx sends defer, Tx sends only reads
729 * request without sending addres
732 retval = rk32_edp_select_i2c_device(edp,
733 device_addr, val_addr + i);
738 * Set I2C transaction and write data
739 * If bit 3 is 1, DisplayPort transaction.
740 * If Bit 3 is 0, I2C transaction.
742 val = AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
744 writel(val, edp->regs + AUX_CH_CTL_1);
746 /* Start AUX transaction */
747 retval = rk32_edp_start_aux_transaction(edp);
751 dev_dbg(edp->dev, "Aux Transaction fail!\n");
753 /* Check if Rx sends defer */
754 val = readl(edp->regs + AUX_RX_COMM);
755 if (val == AUX_RX_COMM_AUX_DEFER ||
756 val == AUX_RX_COMM_I2C_DEFER) {
757 dev_err(edp->dev, "Defer: %d\n\n", val);
762 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
763 val = readl(edp->regs + BUF_DATA_0 + 4 * cur_data_idx);
764 edid[i + cur_data_idx] = (unsigned char)val;
771 void rk32_edp_set_link_bandwidth(struct rk32_edp *edp, u32 bwtype)
776 if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
777 writel(val, edp->regs + LINK_BW_SET);
780 void rk32_edp_get_link_bandwidth(struct rk32_edp *edp, u32 *bwtype)
784 val = readl(edp->regs + LINK_BW_SET);
788 void rk32_edp_hw_link_training_en(struct rk32_edp *edp)
792 writel(val, edp->regs + HW_LT_CTL);
795 int rk32_edp_wait_hw_lt_done(struct rk32_edp *edp)
799 val = readl(edp->regs + HW_LT_CTL);
802 val = readl(edp->regs + DP_INT_STA);
803 if (val&HW_LT_DONE) {
804 writel(val, edp->regs + DP_INT_STA);
812 int rk32_edp_get_hw_lt_status(struct rk32_edp *edp)
815 val = readl(edp->regs + HW_LT_CTL);
816 return (val & HW_LT_ERR_CODE_MASK) >> 4;
818 void rk32_edp_set_lane_count(struct rk32_edp *edp, u32 count)
823 writel(val, edp->regs + LANE_CNT_SET);
826 void rk32_edp_get_lane_count(struct rk32_edp *edp, u32 *count)
830 val = readl(edp->regs + LANE_CNT_SET);
834 void rk32_edp_enable_enhanced_mode(struct rk32_edp *edp, bool enable)
839 val = readl(edp->regs + SYS_CTL_4);
841 writel(val, edp->regs + SYS_CTL_4);
843 val = readl(edp->regs + SYS_CTL_4);
845 writel(val, edp->regs + SYS_CTL_4);
849 void rk32_edp_set_training_pattern(struct rk32_edp *edp,
850 enum pattern_set pattern)
856 val = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
857 writel(val, edp->regs + TRAINING_PTN_SET);
860 val = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
861 writel(val, edp->regs + TRAINING_PTN_SET);
864 val = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
865 writel(val, edp->regs + TRAINING_PTN_SET);
868 val = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
869 writel(val, edp->regs + TRAINING_PTN_SET);
872 val = SCRAMBLING_ENABLE |
873 LINK_QUAL_PATTERN_SET_DISABLE |
874 SW_TRAINING_PATTERN_SET_DISABLE;
875 writel(val, edp->regs + TRAINING_PTN_SET);
882 void rk32_edp_set_lane0_pre_emphasis(struct rk32_edp *edp, u32 level)
886 val = level << PRE_EMPHASIS_SET_SHIFT;
887 writel(val, edp->regs + LN0_LINK_TRAINING_CTL);
890 void rk32_edp_set_lane1_pre_emphasis(struct rk32_edp *edp, u32 level)
894 val = level << PRE_EMPHASIS_SET_SHIFT;
895 writel(val, edp->regs + LN1_LINK_TRAINING_CTL);
898 void rk32_edp_set_lane2_pre_emphasis(struct rk32_edp *edp, u32 level)
902 val = level << PRE_EMPHASIS_SET_SHIFT;
903 writel(val, edp->regs + LN2_LINK_TRAINING_CTL);
906 void rk32_edp_set_lane3_pre_emphasis(struct rk32_edp *edp, u32 level)
910 val = level << PRE_EMPHASIS_SET_SHIFT;
911 writel(val, edp->regs + LN3_LINK_TRAINING_CTL);
914 void rk32_edp_set_lane0_link_training(struct rk32_edp *edp,
920 writel(val, edp->regs + LN0_LINK_TRAINING_CTL);
923 void rk32_edp_set_lane1_link_training(struct rk32_edp *edp,
929 writel(val, edp->regs + LN1_LINK_TRAINING_CTL);
932 void rk32_edp_set_lane2_link_training(struct rk32_edp *edp,
938 writel(val, edp->regs + LN2_LINK_TRAINING_CTL);
941 void rk32_edp_set_lane3_link_training(struct rk32_edp *edp,
947 writel(val, edp->regs + LN3_LINK_TRAINING_CTL);
950 u32 rk32_edp_get_lane0_link_training(struct rk32_edp *edp)
954 val = readl(edp->regs + LN0_LINK_TRAINING_CTL);
958 u32 rk32_edp_get_lane1_link_training(struct rk32_edp *edp)
962 val = readl(edp->regs + LN1_LINK_TRAINING_CTL);
966 u32 rk32_edp_get_lane2_link_training(struct rk32_edp *edp)
970 val = readl(edp->regs + LN2_LINK_TRAINING_CTL);
974 u32 rk32_edp_get_lane3_link_training(struct rk32_edp *edp)
978 val = readl(edp->regs + LN3_LINK_TRAINING_CTL);
982 void rk32_edp_reset_macro(struct rk32_edp *edp)
986 val = readl(edp->regs + PHY_TEST);
988 writel(val, edp->regs + PHY_TEST);
994 writel(val, edp->regs + PHY_TEST);*/
997 int rk32_edp_init_video(struct rk32_edp *edp)
1001 val = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1002 writel(val, edp->regs + COMMON_INT_STA_1);
1005 writel(val, edp->regs + SYS_CTL_1);
1007 val = CHA_CRI(4) | CHA_CTRL;
1008 writel(val, edp->regs + SYS_CTL_2);
1011 writel(val, edp->regs + SYS_CTL_3);*/
1013 val = VID_HRES_TH(2) | VID_VRES_TH(0);
1014 writel(val, edp->regs + VIDEO_CTL_8);
1019 void rk32_edp_set_video_color_format(struct rk32_edp *edp,
1027 /* Configure the input color dedpth, color space, dynamic range */
1028 val = (dynamic_range << IN_D_RANGE_SHIFT) |
1029 (color_dedpth << IN_BPC_SHIFT) |
1030 (color_space << IN_COLOR_F_SHIFT);
1031 writel(val, edp->regs + VIDEO_CTL_2);
1033 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1034 val = readl(edp->regs + VIDEO_CTL_3);
1035 val &= ~IN_YC_COEFFI_MASK;
1037 val |= IN_YC_COEFFI_ITU709;
1039 val |= IN_YC_COEFFI_ITU601;
1040 writel(val, edp->regs + VIDEO_CTL_3);
1043 int rk32_edp_is_slave_video_stream_clock_on(struct rk32_edp *edp)
1047 val = readl(edp->regs + SYS_CTL_1);
1048 writel(val, edp->regs + SYS_CTL_1);
1050 val = readl(edp->regs + SYS_CTL_1);
1052 if (!(val & DET_STA)) {
1053 dev_dbg(edp->dev, "Input stream clock not detected.\n");
1057 val = readl(edp->regs + SYS_CTL_2);
1058 writel(val, edp->regs + SYS_CTL_2);
1060 val = readl(edp->regs + SYS_CTL_2);
1061 if (val & CHA_STA) {
1062 dev_dbg(edp->dev, "Input stream clk is changing\n");
1070 void rk32_edp_set_video_cr_mn(struct rk32_edp *edp,
1071 enum clock_recovery_m_value_type type,
1077 if (type == REGISTER_M) {
1078 val = readl(edp->regs + SYS_CTL_4);
1080 writel(val, edp->regs + SYS_CTL_4);
1081 val = m_value & 0xff;
1082 writel(val, edp->regs + M_VID_0);
1083 val = (m_value >> 8) & 0xff;
1084 writel(val, edp->regs + M_VID_1);
1085 val = (m_value >> 16) & 0xff;
1086 writel(val, edp->regs + M_VID_2);
1088 val = n_value & 0xff;
1089 writel(val, edp->regs + N_VID_0);
1090 val = (n_value >> 8) & 0xff;
1091 writel(val, edp->regs + N_VID_1);
1092 val = (n_value >> 16) & 0xff;
1093 writel(val, edp->regs + N_VID_2);
1095 val = readl(edp->regs + SYS_CTL_4);
1097 writel(val, edp->regs + SYS_CTL_4);
1099 writel(0x00, edp->regs + N_VID_0);
1100 writel(0x80, edp->regs + N_VID_1);
1101 writel(0x00, edp->regs + N_VID_2);
1105 void rk32_edp_set_video_timing_mode(struct rk32_edp *edp, u32 type)
1109 if (type == VIDEO_TIMING_FROM_CAPTURE) {
1110 val = readl(edp->regs + VIDEO_CTL_10);
1112 writel(val, edp->regs + VIDEO_CTL_10);
1114 val = readl(edp->regs + VIDEO_CTL_10);
1116 writel(val, edp->regs + VIDEO_CTL_10);
1120 int rk32_edp_bist_cfg(struct rk32_edp *edp)
1122 struct video_info *video_info = &edp->video_info;
1123 struct rk_screen *screen = &edp->screen;
1124 u16 x_total, y_total, x_act;
1126 x_total = screen->mode.left_margin + screen->mode.right_margin +
1127 screen->mode.xres + screen->mode.hsync_len;
1128 y_total = screen->mode.upper_margin + screen->mode.lower_margin +
1129 screen->mode.yres + screen->mode.vsync_len;
1130 x_act = screen->mode.xres;
1132 rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1133 rk32_edp_set_video_color_format(edp, video_info->color_depth,
1134 video_info->color_space,
1135 video_info->dynamic_range,
1136 video_info->ycbcr_coeff);
1138 val = y_total & 0xff;
1139 writel(val, edp->regs + TOTAL_LINE_CFG_L);
1140 val = (y_total >> 8);
1141 writel(val, edp->regs + TOTAL_LINE_CFG_H);
1142 val = (screen->mode.yres & 0xff);
1143 writel(val, edp->regs + ATV_LINE_CFG_L);
1144 val = (screen->mode.yres >> 8);
1145 writel(val, edp->regs + ATV_LINE_CFG_H);
1146 val = screen->mode.lower_margin;
1147 writel(val, edp->regs + VF_PORCH_REG);
1148 val = screen->mode.vsync_len;
1149 writel(val, edp->regs + VSYNC_CFG_REG);
1150 val = screen->mode.upper_margin;
1151 writel(val, edp->regs + VB_PORCH_REG);
1152 val = x_total & 0xff;
1153 writel(val, edp->regs + TOTAL_PIXELL_REG);
1155 writel(val, edp->regs + TOTAL_PIXELH_REG);
1156 val = (x_act & 0xff);
1157 writel(val, edp->regs + ATV_PIXELL_REG);
1159 writel(val, edp->regs + ATV_PIXELH_REG);
1160 val = screen->mode.right_margin & 0xff;
1161 writel(val, edp->regs + HF_PORCHL_REG);
1162 val = screen->mode.right_margin >> 8;
1163 writel(val, edp->regs + HF_PORCHH_REG);
1164 val = screen->mode.hsync_len & 0xff;
1165 writel(val, edp->regs + HSYNC_CFGL_REG);
1166 val = screen->mode.hsync_len >> 8;
1167 writel(val, edp->regs + HSYNC_CFGH_REG);
1168 val = screen->mode.left_margin & 0xff;
1169 writel(val, edp->regs + HB_PORCHL_REG);
1170 val = screen->mode.left_margin >> 8;
1171 writel(val, edp->regs + HB_PORCHH_REG);
1173 val = BIST_EN | BIST_WH_64 | BIST_TYPE_COLR_BAR;
1174 writel(val, edp->regs + VIDEO_CTL_4);
1176 val = readl(edp->regs + VIDEO_CTL_10);
1178 writel(val, edp->regs + VIDEO_CTL_10);
1183 void rk32_edp_enable_video_master(struct rk32_edp *edp, bool enable)
1188 val = readl(edp->regs + SOC_GENERAL_CTL);
1189 val &= ~VIDEO_MODE_MASK;
1190 val |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1191 writel(val, edp->regs + SOC_GENERAL_CTL);
1193 val = readl(edp->regs + SOC_GENERAL_CTL);
1194 val &= ~VIDEO_MODE_MASK;
1195 val |= VIDEO_MODE_SLAVE_MODE;
1196 writel(val, edp->regs + SOC_GENERAL_CTL);
1200 void rk32_edp_start_video(struct rk32_edp *edp)
1204 val = readl(edp->regs + VIDEO_CTL_1);
1206 writel(val, edp->regs + VIDEO_CTL_1);
1209 int rk32_edp_is_video_stream_on(struct rk32_edp *edp)
1213 val = readl(edp->regs + SYS_CTL_3);
1214 writel(val, edp->regs + SYS_CTL_3);
1216 val = readl(edp->regs + SYS_CTL_3);
1217 if (!(val & STRM_VALID)) {
1218 dev_dbg(edp->dev, "Input video stream is not detected.\n");
1225 void rk32_edp_config_video_slave_mode(struct rk32_edp *edp,
1226 struct video_info *video_info)
1230 val = readl(edp->regs + FUNC_EN_1);
1231 val &= ~(VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
1232 writel(val, edp->regs + FUNC_EN_1);
1234 val = readl(edp->regs + VIDEO_CTL_10);
1235 val &= ~INTERACE_SCAN_CFG;
1236 val |= (video_info->interlaced << 2);
1237 writel(val, edp->regs + VIDEO_CTL_10);
1239 val = readl(edp->regs + VIDEO_CTL_10);
1240 val &= ~VSYNC_POLARITY_CFG;
1241 val |= (video_info->v_sync_polarity << 1);
1242 writel(val, edp->regs + VIDEO_CTL_10);
1244 val = readl(edp->regs + VIDEO_CTL_10);
1245 val &= ~HSYNC_POLARITY_CFG;
1246 val |= (video_info->h_sync_polarity << 0);
1247 writel(val, edp->regs + VIDEO_CTL_10);
1249 /*val = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1250 writel(val, edp->regs + SOC_GENERAL_CTL);*/
1253 void rk32_edp_enable_scrambling(struct rk32_edp *edp)
1257 val = readl(edp->regs + TRAINING_PTN_SET);
1258 val &= ~SCRAMBLING_DISABLE;
1259 writel(val, edp->regs + TRAINING_PTN_SET);
1262 void rk32_edp_disable_scrambling(struct rk32_edp *edp)
1266 val = readl(edp->regs + TRAINING_PTN_SET);
1267 val |= SCRAMBLING_DISABLE;
1268 writel(val, edp->regs + TRAINING_PTN_SET);
1271 enum dp_irq_type rk32_edp_get_irq_type(struct rk32_edp *edp)
1275 /* Parse hotplug interrupt status register */
1276 val = readl(edp->regs + COMMON_INT_STA_4);
1278 return DP_IRQ_TYPE_HP_CABLE_IN;
1281 return DP_IRQ_TYPE_HP_CABLE_OUT;
1283 if (val & HOTPLUG_CHG)
1284 return DP_IRQ_TYPE_HP_CHANGE;
1286 return DP_IRQ_TYPE_UNKNOWN;
1289 void rk32_edp_clear_hotplug_interrupts(struct rk32_edp *edp)
1293 val = HOTPLUG_CHG | HPD_LOST | PLUG;
1294 writel(val, edp->regs + COMMON_INT_STA_4);
1297 writel(val, edp->regs + DP_INT_STA);