drivers/video/rockchip/transmitter/rk32_dp_reg.c

   1 /*
   2  *RockChip DP (Display port) register interface driver.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  */
   9
  10 #include <linux/device.h>
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <linux/rockchip/cpu.h>
  14 #include <linux/rockchip/iomap.h>
  15 #include <linux/rockchip/grf.h>
  16 #include "rk32_dp.h"
  17
  18
  19 void rk32_edp_enable_video_mute(struct rk32_edp *edp, bool enable)
  20 {
  21         u32 val;
  22
  23         if (enable) {
  24                 val = readl(edp->regs + VIDEO_CTL_1);
  25                 val |= VIDEO_MUTE;
  26                 writel(val, edp->regs + VIDEO_CTL_1);
  27         } else {
  28                 val = readl(edp->regs + VIDEO_CTL_1);
  29                 val &= ~VIDEO_MUTE;
  30                 writel(val, edp->regs + VIDEO_CTL_1);
  31         }
  32 }
  33
  34 void rk32_edp_stop_video(struct rk32_edp *edp)
  35 {
  36         u32 val;
  37
  38         val = readl(edp->regs + VIDEO_CTL_1);
  39         val &= ~VIDEO_EN;
  40         writel(val, edp->regs + VIDEO_CTL_1);
  41 }
  42
  43 void rk32_edp_lane_swap(struct rk32_edp *edp, bool enable)
  44 {
  45         u32 val;
  46
  47
  48         if (enable)
  49                 val = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
  50                         LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
  51         else
  52                 val = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
  53                         LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
  54
  55         writel(val, edp->regs + LANE_MAP);
  56 }
  57
  58 void rk32_edp_init_refclk(struct rk32_edp *edp)
  59 {
  60         u32 val;
  61         /*struct rk32_edp_platdata *pdata = edp->dev->platform_data;
  62         struct analog_param *analog_param = pdata->analog_param;
  63
  64         val = TX_TERMINAL_CTRL_50_OHM;
  65         writel(val, edp->regs + ANALOG_CTL_1);*/
  66
  67         val = SEL_24M;
  68         writel(val, edp->regs + ANALOG_CTL_2);
  69
  70         if (edp->soctype == SOC_RK3399)
  71                 val = 0x1 << 0;
  72         else
  73                 val = REF_CLK_24M;
  74         writel(val, edp->regs + PLL_REG_1);
  75
  76         val = 0x95;
  77         writel(val, edp->regs + PLL_REG_2);
  78
  79         val = 0x40;
  80         writel(val, edp->regs + PLL_REG_3);
  81
  82         val = 0x58;
  83         writel(val, edp->regs + PLL_REG_4);
  84
  85         val = 0x22;
  86         writel(val, edp->regs + PLL_REG_5);
  87
  88         val = 0x19;
  89         writel(val, edp->regs + SSC_REG);
  90         val = 0x87;
  91         writel(val, edp->regs + TX_REG_COMMON);
  92         val = 0x03;
  93         writel(val, edp->regs + DP_AUX);
  94         val = 0x46;
  95         writel(val, edp->regs + DP_BIAS);
  96         val = 0x55;
  97         writel(val, edp->regs + DP_RESERVE2);
  98
  99
 100         /*val = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
 101         writel(val, edp->regs + ANALOG_CTL_3);
 102
 103         if (!analog_param) {
 104                 val = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
 105                         TX_CUR1_2X | TX_CUR_16_MA;
 106                 writel(val, edp->regs + PLL_FILTER_CTL_1);
 107
 108                 val = CH3_AMP_400_MV | CH2_AMP_400_MV |
 109                         CH1_AMP_400_MV | CH0_AMP_400_MV;
 110                 writel(val, edp->regs + TX_AMP_TUNING_CTL);
 111         } else {
 112                 int tx_amp;
 113
 114                 val = PD_RING_OSC | TX_CUR1_2X | TX_CUR_16_MA;
 115                 switch (analog_param->aux_tx_terminal_resistor) {
 116                 case AUX_TX_37_5_OHM:
 117                         val |= AUX_TERMINAL_CTRL_37_5_OHM;
 118                         break;
 119                 case AUX_TX_45_OHM:
 120                         val |= AUX_TERMINAL_CTRL_45_OHM;
 121                         break;
 122                 case AUX_TX_50_OHM:
 123                         val |= AUX_TERMINAL_CTRL_50_OHM;
 124                         break;
 125                 case AUX_TX_65_OHM:
 126                         val |= AUX_TERMINAL_CTRL_65_OHM;
 127                         break;
 128                 }
 129                 writel(val, edp->regs + PLL_FILTER_CTL_1);
 130
 131                 tx_amp = analog_param->tx_amplitude;
 132                 if (tx_amp < 200000 || tx_amp > 500000) {
 133                         dev_warn(edp->dev,
 134                                  "TX amp out of range, defaulting to 400mV\n");
 135                         tx_amp = 400000;
 136                 }
 137
 138                 tx_amp = ((tx_amp - 400000) / 12500) & 0x1f;
 139
 140                 val = (tx_amp << CH3_AMP_SHIFT) | (tx_amp << CH2_AMP_SHIFT) |
 141                         (tx_amp << CH1_AMP_SHIFT) | (tx_amp << CH0_AMP_SHIFT);
 142                 writel(val, edp->regs + TX_AMP_TUNING_CTL);
 143         }*/
 144 }
 145
 146 void rk32_edp_init_interrupt(struct rk32_edp *edp)
 147 {
 148         /* Set interrupt pin assertion polarity as high */
 149         writel(INT_POL, edp->regs + INT_CTL);
 150
 151         /* Clear pending valisers */
 152         writel(0xff, edp->regs + COMMON_INT_STA_1);
 153         writel(0x4f, edp->regs + COMMON_INT_STA_2);
 154         writel(0xff, edp->regs + COMMON_INT_STA_3);
 155         writel(0x27, edp->regs + COMMON_INT_STA_4);
 156
 157         writel(0x7f, edp->regs + DP_INT_STA);
 158
 159         /* 0:mask,1: unmask */
 160         writel(0x00, edp->regs + COMMON_INT_MASK_1);
 161         writel(0x00, edp->regs + COMMON_INT_MASK_2);
 162         writel(0x00, edp->regs + COMMON_INT_MASK_3);
 163         writel(0x00, edp->regs + COMMON_INT_MASK_4);
 164         writel(0x00, edp->regs + DP_INT_STA_MASK);
 165 }
 166
 167 void rk32_edp_reset(struct rk32_edp *edp)
 168 {
 169         u32 val;
 170
 171         rk32_edp_stop_video(edp);
 172         rk32_edp_enable_video_mute(edp, 0);
 173
 174         val = VID_CAP_FUNC_EN_N | AUD_FIFO_FUNC_EN_N |
 175                 AUD_FUNC_EN_N | HDCP_FUNC_EN_N | SW_FUNC_EN_N;
 176         writel(val, edp->regs + FUNC_EN_1);
 177
 178         val = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
 179                 SERDES_FIFO_FUNC_EN_N |
 180                 LS_CLK_DOMAIN_FUNC_EN_N;
 181         writel(val, edp->regs + FUNC_EN_2);
 182
 183         udelay(20);
 184
 185         rk32_edp_lane_swap(edp, 0);
 186
 187         writel(0x0, edp->regs + SYS_CTL_1);
 188         writel(0x40, edp->regs + SYS_CTL_2);
 189         writel(0x0, edp->regs + SYS_CTL_3);
 190         writel(0x0, edp->regs + SYS_CTL_4);
 191
 192         writel(0x0, edp->regs + PKT_SEND_CTL);
 193         writel(0x0, edp->regs + HDCP_CTL);
 194
 195         writel(0x5e, edp->regs + HPD_DEGLITCH_L);
 196         writel(0x1a, edp->regs + HPD_DEGLITCH_H);
 197
 198         writel(0x10, edp->regs + LINK_DEBUG_CTL);
 199
 200         writel(0x0, edp->regs + VIDEO_FIFO_THRD);
 201         writel(0x20, edp->regs + AUDIO_MARGIN);
 202
 203         writel(0x4, edp->regs + M_VID_GEN_FILTER_TH);
 204         writel(0x2, edp->regs + M_AUD_GEN_FILTER_TH);
 205
 206         writel(0x0, edp->regs + SOC_GENERAL_CTL);
 207
 208 }
 209
 210 void rk32_edp_config_interrupt(struct rk32_edp *edp)
 211 {
 212         u32 val;
 213
 214         /* 0: mask, 1: unmask */
 215         val = 0;
 216         writel(val, edp->regs + COMMON_INT_MASK_1);
 217
 218         writel(val, edp->regs + COMMON_INT_MASK_2);
 219
 220         writel(val, edp->regs + COMMON_INT_MASK_3);
 221
 222         writel(val, edp->regs + COMMON_INT_MASK_4);
 223
 224         writel(val, edp->regs + DP_INT_STA_MASK);
 225 }
 226
 227 u32 rk32_edp_get_pll_lock_status(struct rk32_edp *edp)
 228 {
 229         u32 val;
 230
 231         val = readl(edp->regs + DEBUG_CTL);
 232         if (val & PLL_LOCK)
 233                 return DP_PLL_LOCKED;
 234         else
 235                 return DP_PLL_UNLOCKED;
 236 }
 237
 238
 239 void rk32_edp_analog_power_ctr(struct rk32_edp *edp, bool enable)
 240 {
 241         u32 val;
 242
 243         if (enable) {
 244                 val = PD_EXP_BG | PD_AUX | PD_PLL |
 245                         PD_CH3 | PD_CH2 | PD_CH1 | PD_CH0;
 246                 writel(val, edp->regs + DP_PWRDN);
 247                 udelay(10);
 248                 writel(0x0, edp->regs + DP_PWRDN);
 249         } else {
 250                 val = PD_EXP_BG | PD_AUX | PD_PLL |
 251                         PD_CH3 | PD_CH2 | PD_CH1 | PD_CH0;
 252                 writel(val, edp->regs + DP_PWRDN);
 253         }
 254 }
 255
 256
 257 void rk32_edp_init_analog_func(struct rk32_edp *edp)
 258 {
 259         u32 val;
 260         int wt = 0;
 261         rk32_edp_analog_power_ctr(edp, 1);
 262
 263         val = PLL_LOCK_CHG;
 264         writel(val, edp->regs + COMMON_INT_STA_1);
 265
 266         val = readl(edp->regs + DEBUG_CTL);
 267         val &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 268         writel(val, edp->regs + DEBUG_CTL);
 269
 270         /* Power up PLL */
 271         while (wt < 100) {
 272                 if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_LOCKED) {
 273                         dev_info(edp->dev, "edp pll locked\n");
 274                         break;
 275                 } else {
 276                         wt++;
 277                         udelay(5);
 278                 }
 279         }
 280
 281         /* Enable Serdes FIFO function and Link symbol clock domain module */
 282         val = readl(edp->regs + FUNC_EN_2);
 283         val &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 284                 | AUX_FUNC_EN_N | SSC_FUNC_EN_N);
 285         writel(val, edp->regs + FUNC_EN_2);
 286 }
 287
 288 void rk32_edp_init_hpd(struct rk32_edp *edp)
 289 {
 290         u32 val;
 291
 292         val = HOTPLUG_CHG | HPD_LOST | PLUG;
 293         writel(val, edp->regs + COMMON_INT_STA_4);
 294
 295         val = INT_HPD;
 296         writel(val, edp->regs + DP_INT_STA);
 297
 298         val = readl(edp->regs + SYS_CTL_3);
 299         val |= (F_HPD | HPD_CTRL);
 300         writel(val, edp->regs + SYS_CTL_3);
 301 }
 302
 303 void rk32_edp_reset_aux(struct rk32_edp *edp)
 304 {
 305         u32 val;
 306
 307         /* Disable AUX channel module */
 308         val = readl(edp->regs + FUNC_EN_2);
 309         val |= AUX_FUNC_EN_N;
 310         writel(val, edp->regs + FUNC_EN_2);
 311 }
 312
 313 void rk32_edp_init_aux(struct rk32_edp *edp)
 314 {
 315         u32 val;
 316
 317         /* Clear inerrupts related to AUX channel */
 318         val = RPLY_RECEIV | AUX_ERR;
 319         writel(val, edp->regs + DP_INT_STA);
 320
 321         rk32_edp_reset_aux(edp);
 322
 323         /* Disable AUX transaction H/W retry */
 324         /*val = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
 325                 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 326         writel(val, edp->regs + AUX_HW_RETRY_CTL) ;*/
 327
 328         /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 329         val = DEFER_CTRL_EN | DEFER_COUNT(1);
 330         writel(val, edp->regs + AUX_CH_DEFER_CTL);
 331
 332         /* Enable AUX channel module */
 333         val = readl(edp->regs + FUNC_EN_2);
 334         val &= ~AUX_FUNC_EN_N;
 335         writel(val, edp->regs + FUNC_EN_2);
 336 }
 337
 338 int rk32_edp_get_plug_in_status(struct rk32_edp *edp)
 339 {
 340         u32 val;
 341
 342         val = readl(edp->regs + SYS_CTL_3);
 343         if (val & HPD_STATUS)
 344                 return 0;
 345
 346         return -EINVAL;
 347 }
 348
 349 void rk32_edp_enable_sw_function(struct rk32_edp *edp)
 350 {
 351         u32 val;
 352         val = readl(edp->regs + FUNC_EN_1);
 353         val &= ~SW_FUNC_EN_N;
 354         writel(val, edp->regs + FUNC_EN_1);
 355 }
 356
 357 int rk32_edp_start_aux_transaction(struct rk32_edp *edp)
 358 {
 359         int val;
 360         int retval = 0;
 361         int timeout_loop = 0;
 362         int aux_timeout = 0;
 363
 364         /* Enable AUX CH operation */
 365         val = readl(edp->regs + AUX_CH_CTL_2);
 366         val |= AUX_EN;
 367         writel(val, edp->regs + AUX_CH_CTL_2);
 368
 369         /* Is AUX CH operation enabled? */
 370         val = readl(edp->regs + AUX_CH_CTL_2);
 371         while (val & AUX_EN) {
 372                 aux_timeout++;
 373                 if ((DP_TIMEOUT_LOOP_CNT * 10) < aux_timeout) {
 374                         dev_err(edp->dev, "AUX CH enable timeout!\n");
 375                         return -ETIMEDOUT;
 376                 }
 377                 val = readl(edp->regs + AUX_CH_CTL_2);
 378                 udelay(100);
 379         }
 380
 381         /* Is AUX CH command redply received? */
 382         val = readl(edp->regs + DP_INT_STA);
 383         while (!(val & RPLY_RECEIV)) {
 384                 timeout_loop++;
 385                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 386                         dev_err(edp->dev, "AUX CH command redply failed!\n");
 387                         return -ETIMEDOUT;
 388                 }
 389                 val = readl(edp->regs + DP_INT_STA);
 390                 udelay(10);
 391         }
 392
 393         /* Clear interrupt source for AUX CH command redply */
 394         writel(RPLY_RECEIV, edp->regs + DP_INT_STA);
 395
 396         /* Clear interrupt source for AUX CH access error */
 397         val = readl(edp->regs + DP_INT_STA);
 398         if (val & AUX_ERR) {
 399                 writel(AUX_ERR, edp->regs + DP_INT_STA);
 400                 return -EREMOTEIO;
 401         }
 402
 403         /* Check AUX CH error access status */
 404         val = readl(edp->regs + AUX_CH_STA);
 405         if ((val & AUX_STATUS_MASK) != 0) {
 406                 dev_err(edp->dev, "AUX CH error happens: %d\n\n",
 407                         val & AUX_STATUS_MASK);
 408                 return -EREMOTEIO;
 409         }
 410
 411         return retval;
 412 }
 413
 414 int rk32_edp_write_byte_to_dpcd(struct rk32_edp *edp,
 415                                 unsigned int val_addr,
 416                                 unsigned char data)
 417 {
 418         u32 val;
 419         int i;
 420         int retval;
 421
 422         for (i = 0; i < 3; i++) {
 423                 /* Clear AUX CH data buffer */
 424                 val = BUF_CLR;
 425                 writel(val, edp->regs + BUFFER_DATA_CTL);
 426
 427                 /* Select DPCD device address */
 428                 val = AUX_ADDR_7_0(val_addr);
 429                 writel(val, edp->regs + DP_AUX_ADDR_7_0);
 430                 val = AUX_ADDR_15_8(val_addr);
 431                 writel(val, edp->regs + DP_AUX_ADDR_15_8);
 432                 val = AUX_ADDR_19_16(val_addr);
 433                 writel(val, edp->regs + DP_AUX_ADDR_19_16);
 434
 435                 /* Write data buffer */
 436                 val = (unsigned int)data;
 437                 writel(val, edp->regs + BUF_DATA_0);
 438
 439                 /*
 440                  * Set DisplayPort transaction and write 1 byte
 441                  * If bit 3 is 1, DisplayPort transaction.
 442                  * If Bit 3 is 0, I2C transaction.
 443                  */
 444                 val = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 445                 writel(val, edp->regs + AUX_CH_CTL_1);
 446
 447                 /* Start AUX transaction */
 448                 retval = rk32_edp_start_aux_transaction(edp);
 449                 if (retval == 0)
 450                         break;
 451                 else
 452                         dev_dbg(edp->dev, "Aux Transaction fail!\n");
 453         }
 454
 455         return retval;
 456 }
 457
 458 int rk32_edp_read_byte_from_dpcd(struct rk32_edp *edp,
 459                                 unsigned int val_addr,
 460                                 unsigned char *data)
 461 {
 462         u32 val;
 463         int i;
 464         int retval;
 465
 466         for (i = 0; i < 10; i++) {
 467                 /* Clear AUX CH data buffer */
 468                 val = BUF_CLR;
 469                 writel(val, edp->regs + BUFFER_DATA_CTL);
 470
 471                 /* Select DPCD device address */
 472                 val = AUX_ADDR_7_0(val_addr);
 473                 writel(val, edp->regs + DP_AUX_ADDR_7_0);
 474                 val = AUX_ADDR_15_8(val_addr);
 475                 writel(val, edp->regs + DP_AUX_ADDR_15_8);
 476                 val = AUX_ADDR_19_16(val_addr);
 477                 writel(val, edp->regs + DP_AUX_ADDR_19_16);
 478
 479                 /*
 480                  * Set DisplayPort transaction and read 1 byte
 481                  * If bit 3 is 1, DisplayPort transaction.
 482                  * If Bit 3 is 0, I2C transaction.
 483                  */
 484                 val = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 485                 writel(val, edp->regs + AUX_CH_CTL_1);
 486
 487                 /* Start AUX transaction */
 488                 retval = rk32_edp_start_aux_transaction(edp);
 489                 if (retval == 0)
 490                         break;
 491                 else
 492                         dev_dbg(edp->dev, "Aux Transaction fail!\n");
 493         }
 494
 495         /* Read data buffer */
 496         val = readl(edp->regs + BUF_DATA_0);
 497         *data = (unsigned char)(val & 0xff);
 498
 499         return retval;
 500 }
 501
 502 int rk32_edp_write_bytes_to_dpcd(struct rk32_edp *edp,
 503                                 unsigned int val_addr,
 504                                 unsigned int count,
 505                                 unsigned char data[])
 506 {
 507         u32 val;
 508         unsigned int start_offset;
 509         unsigned int cur_data_count;
 510         unsigned int cur_data_idx;
 511         int i;
 512         int retval = 0;
 513
 514         /* Clear AUX CH data buffer */
 515         val = BUF_CLR;
 516         writel(val, edp->regs + BUFFER_DATA_CTL);
 517
 518         start_offset = 0;
 519         while (start_offset < count) {
 520                 /* Buffer size of AUX CH is 16 * 4bytes */
 521                 if ((count - start_offset) > 16)
 522                         cur_data_count = 16;
 523                 else
 524                         cur_data_count = count - start_offset;
 525
 526                 for (i = 0; i < 10; i++) {
 527                         /* Select DPCD device address */
 528                         val = AUX_ADDR_7_0(val_addr + start_offset);
 529                         writel(val, edp->regs + DP_AUX_ADDR_7_0);
 530                         val = AUX_ADDR_15_8(val_addr + start_offset);
 531                         writel(val, edp->regs + DP_AUX_ADDR_15_8);
 532                         val = AUX_ADDR_19_16(val_addr + start_offset);
 533                         writel(val, edp->regs + DP_AUX_ADDR_19_16);
 534
 535                         for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 536                              cur_data_idx++) {
 537                                 val = data[start_offset + cur_data_idx];
 538                                 writel(val, edp->regs + BUF_DATA_0
 539                                                           + 4 * cur_data_idx);
 540                         }
 541
 542                         /*
 543                          * Set DisplayPort transaction and write
 544                          * If bit 3 is 1, DisplayPort transaction.
 545                          * If Bit 3 is 0, I2C transaction.
 546                          */
 547                         val = AUX_LENGTH(cur_data_count) |
 548                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 549                         writel(val, edp->regs + AUX_CH_CTL_1);
 550
 551                         /* Start AUX transaction */
 552                         retval = rk32_edp_start_aux_transaction(edp);
 553                         if (retval == 0)
 554                                 break;
 555                         else
 556                                 dev_dbg(edp->dev, "Aux Transaction fail!\n");
 557                 }
 558
 559                 start_offset += cur_data_count;
 560         }
 561
 562         return retval;
 563 }
 564
 565 int rk32_edp_read_bytes_from_dpcd(struct rk32_edp *edp,
 566                                 unsigned int val_addr,
 567                                 unsigned int count,
 568                                 unsigned char data[])
 569 {
 570         u32 val;
 571         unsigned int start_offset;
 572         unsigned int cur_data_count;
 573         unsigned int cur_data_idx;
 574         int i;
 575         int retval = 0;
 576
 577         /* Clear AUX CH data buffer */
 578         val = BUF_CLR;
 579         writel(val, edp->regs + BUFFER_DATA_CTL);
 580
 581         start_offset = 0;
 582         while (start_offset < count) {
 583                 /* Buffer size of AUX CH is 16 * 4bytes */
 584                 if ((count - start_offset) > 16)
 585                         cur_data_count = 16;
 586                 else
 587                         cur_data_count = count - start_offset;
 588
 589                 /* AUX CH Request Transaction process */
 590                 for (i = 0; i < 10; i++) {
 591                         /* Select DPCD device address */
 592                         val = AUX_ADDR_7_0(val_addr + start_offset);
 593                         writel(val, edp->regs + DP_AUX_ADDR_7_0);
 594                         val = AUX_ADDR_15_8(val_addr + start_offset);
 595                         writel(val, edp->regs + DP_AUX_ADDR_15_8);
 596                         val = AUX_ADDR_19_16(val_addr + start_offset);
 597                         writel(val, edp->regs + DP_AUX_ADDR_19_16);
 598
 599                         /*
 600                          * Set DisplayPort transaction and read
 601                          * If bit 3 is 1, DisplayPort transaction.
 602                          * If Bit 3 is 0, I2C transaction.
 603                          */
 604                         val = AUX_LENGTH(cur_data_count) |
 605                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 606                         writel(val, edp->regs + AUX_CH_CTL_1);
 607
 608                         /* Start AUX transaction */
 609                         retval = rk32_edp_start_aux_transaction(edp);
 610                         if (retval == 0)
 611                                 break;
 612                         else
 613                                 dev_dbg(edp->dev, "Aux Transaction fail!\n");
 614                 }
 615
 616                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 617                     cur_data_idx++) {
 618                         val = readl(edp->regs + BUF_DATA_0
 619                                                  + 4 * cur_data_idx);
 620                         data[start_offset + cur_data_idx] =
 621                                 (unsigned char)val;
 622                 }
 623
 624                 start_offset += cur_data_count;
 625         }
 626
 627         return retval;
 628 }
 629
 630 int rk32_edp_select_i2c_device(struct rk32_edp *edp,
 631                                 unsigned int device_addr,
 632                                 unsigned int val_addr)
 633 {
 634         u32 val;
 635         int retval;
 636
 637         /* Set EDID device address */
 638         val = device_addr;
 639         writel(val, edp->regs + DP_AUX_ADDR_7_0);
 640         writel(0x0, edp->regs + DP_AUX_ADDR_15_8);
 641         writel(0x0, edp->regs + DP_AUX_ADDR_19_16);
 642
 643         /* Set offset from base address of EDID device */
 644         writel(val_addr, edp->regs + BUF_DATA_0);
 645
 646         /*
 647          * Set I2C transaction and write address
 648          * If bit 3 is 1, DisplayPort transaction.
 649          * If Bit 3 is 0, I2C transaction.
 650          */
 651         val = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 652                 AUX_TX_COMM_WRITE;
 653         writel(val, edp->regs + AUX_CH_CTL_1);
 654
 655         /* Start AUX transaction */
 656         retval = rk32_edp_start_aux_transaction(edp);
 657         if (retval != 0)
 658                 dev_dbg(edp->dev, "Aux Transaction fail!\n");
 659
 660         return retval;
 661 }
 662
 663 int rk32_edp_read_byte_from_i2c(struct rk32_edp *edp,
 664                                 unsigned int device_addr,
 665                                 unsigned int val_addr,
 666                                 unsigned int *data)
 667 {
 668         u32 val;
 669         int i;
 670         int retval;
 671
 672         for (i = 0; i < 10; i++) {
 673                 /* Clear AUX CH data buffer */
 674                 val = BUF_CLR;
 675                 writel(val, edp->regs + BUFFER_DATA_CTL);
 676
 677                 /* Select EDID device */
 678                 retval = rk32_edp_select_i2c_device(edp, device_addr, val_addr);
 679                 if (retval != 0) {
 680                         dev_err(edp->dev, "Select EDID device fail!\n");
 681                         continue;
 682                 }
 683
 684                 /*
 685                  * Set I2C transaction and read data
 686                  * If bit 3 is 1, DisplayPort transaction.
 687                  * If Bit 3 is 0, I2C transaction.
 688                  */
 689                 val = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_READ;
 690                 writel(val, edp->regs + AUX_CH_CTL_1);
 691
 692                 /* Start AUX transaction */
 693                 retval = rk32_edp_start_aux_transaction(edp);
 694                 if (retval == 0)
 695                         break;
 696                 else
 697                         dev_dbg(edp->dev, "Aux Transaction fail!\n");
 698         }
 699
 700         /* Read data */
 701         if (retval == 0)
 702                 *data = readl(edp->regs + BUF_DATA_0);
 703
 704         return retval;
 705 }
 706
 707 int rk32_edp_read_bytes_from_i2c(struct rk32_edp *edp,
 708                                 unsigned int device_addr,
 709                                 unsigned int val_addr,
 710                                 unsigned int count,
 711                                 unsigned char edid[])
 712 {
 713         u32 val;
 714         unsigned int i, j;
 715         unsigned int cur_data_idx;
 716         unsigned int defer = 0;
 717         int retval = 0;
 718
 719         for (i = 0; i < count; i += 16) {
 720                 for (j = 0; j < 100; j++) {
 721                         /* Clear AUX CH data buffer */
 722                         val = BUF_CLR;
 723                         writel(val, edp->regs + BUFFER_DATA_CTL);
 724
 725                         /* Set normal AUX CH command */
 726                         val = readl(edp->regs + AUX_CH_CTL_2);
 727                         val &= ~ADDR_ONLY;
 728                         writel(val, edp->regs + AUX_CH_CTL_2);
 729
 730                         /*
 731                          * If Rx sends defer, Tx sends only reads
 732                          * request without sending addres
 733                          */
 734                         if (!defer)
 735                                 retval = rk32_edp_select_i2c_device(edp,
 736                                                 device_addr, val_addr + i);
 737                         else
 738                                 defer = 0;
 739
 740                         /*
 741                          * Set I2C transaction and write data
 742                          * If bit 3 is 1, DisplayPort transaction.
 743                          * If Bit 3 is 0, I2C transaction.
 744                          */
 745                         val = AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
 746                                 AUX_TX_COMM_READ;
 747                         writel(val, edp->regs + AUX_CH_CTL_1);
 748
 749                         /* Start AUX transaction */
 750                         retval = rk32_edp_start_aux_transaction(edp);
 751                         if (retval == 0)
 752                                 break;
 753                         else
 754                                 dev_dbg(edp->dev, "Aux Transaction fail!\n");
 755
 756                         /* Check if Rx sends defer */
 757                         val = readl(edp->regs + AUX_RX_COMM);
 758                         if (val == AUX_RX_COMM_AUX_DEFER ||
 759                                 val == AUX_RX_COMM_I2C_DEFER) {
 760                                 dev_err(edp->dev, "Defer: %d\n\n", val);
 761                                 defer = 1;
 762                         }
 763                 }
 764
 765                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 766                         val = readl(edp->regs + BUF_DATA_0 + 4 * cur_data_idx);
 767                         edid[i + cur_data_idx] = (unsigned char)val;
 768                 }
 769         }
 770
 771         return retval;
 772 }
 773
 774 void rk32_edp_set_link_bandwidth(struct rk32_edp *edp, u32 bwtype)
 775 {
 776         u32 val;
 777
 778         val = bwtype;
 779         if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
 780                 writel(val, edp->regs + LINK_BW_SET);
 781 }
 782
 783 void rk32_edp_get_link_bandwidth(struct rk32_edp *edp, u32 *bwtype)
 784 {
 785         u32 val;
 786
 787         val = readl(edp->regs + LINK_BW_SET);
 788         *bwtype = val;
 789 }
 790
 791 void rk32_edp_hw_link_training_en(struct rk32_edp *edp)
 792 {
 793         u32 val;
 794         val = HW_LT_EN;
 795         writel(val, edp->regs + HW_LT_CTL);
 796 }
 797
 798 int rk32_edp_wait_hw_lt_done(struct rk32_edp *edp)
 799 {
 800         u32 val;
 801 #if 0
 802         val = readl(edp->regs + HW_LT_CTL);
 803         return val&0x01;
 804 #else
 805         val = readl(edp->regs + DP_INT_STA);
 806         if (val&HW_LT_DONE) {
 807                 writel(val, edp->regs + DP_INT_STA);
 808                 return 0;
 809         } else {
 810                 return 1;
 811         }
 812 #endif
 813 }
 814
 815 int rk32_edp_get_hw_lt_status(struct rk32_edp *edp)
 816 {
 817         u32 val;
 818         val = readl(edp->regs + HW_LT_CTL);
 819         return (val & HW_LT_ERR_CODE_MASK) >> 4;
 820 }
 821 void rk32_edp_set_lane_count(struct rk32_edp *edp, u32 count)
 822 {
 823         u32 val;
 824
 825         val = count;
 826         writel(val, edp->regs + LANE_CNT_SET);
 827 }
 828
 829 void rk32_edp_get_lane_count(struct rk32_edp *edp, u32 *count)
 830 {
 831         u32 val;
 832
 833         val = readl(edp->regs + LANE_CNT_SET);
 834         *count = val;
 835 }
 836
 837 void rk32_edp_enable_enhanced_mode(struct rk32_edp *edp, bool enable)
 838 {
 839         u32 val;
 840
 841         if (enable) {
 842                 val = readl(edp->regs + SYS_CTL_4);
 843                 val |= ENHANCED;
 844                 writel(val, edp->regs + SYS_CTL_4);
 845         } else {
 846                 val = readl(edp->regs + SYS_CTL_4);
 847                 val &= ~ENHANCED;
 848                 writel(val, edp->regs + SYS_CTL_4);
 849         }
 850 }
 851
 852 void rk32_edp_set_training_pattern(struct rk32_edp *edp,
 853                                  enum pattern_set pattern)
 854 {
 855         u32 val;
 856
 857         switch (pattern) {
 858         case PRBS7:
 859                 val = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
 860                 writel(val, edp->regs + TRAINING_PTN_SET);
 861                 break;
 862         case D10_2:
 863                 val = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
 864                 writel(val, edp->regs + TRAINING_PTN_SET);
 865                 break;
 866         case TRAINING_PTN1:
 867                 val = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
 868                 writel(val, edp->regs + TRAINING_PTN_SET);
 869                 break;
 870         case TRAINING_PTN2:
 871                 val = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
 872                 writel(val, edp->regs + TRAINING_PTN_SET);
 873                 break;
 874         case DP_NONE:
 875                 val = SCRAMBLING_ENABLE |
 876                         LINK_QUAL_PATTERN_SET_DISABLE |
 877                         SW_TRAINING_PATTERN_SET_DISABLE;
 878                 writel(val, edp->regs + TRAINING_PTN_SET);
 879                 break;
 880         default:
 881                 break;
 882         }
 883 }
 884
 885 void rk32_edp_set_lane0_pre_emphasis(struct rk32_edp *edp, u32 level)
 886 {
 887         u32 val;
 888
 889         val = level << PRE_EMPHASIS_SET_SHIFT;
 890         writel(val, edp->regs + LN0_LINK_TRAINING_CTL);
 891 }
 892
 893 void rk32_edp_set_lane1_pre_emphasis(struct rk32_edp *edp, u32 level)
 894 {
 895         u32 val;
 896
 897         val = level << PRE_EMPHASIS_SET_SHIFT;
 898         writel(val, edp->regs + LN1_LINK_TRAINING_CTL);
 899 }
 900
 901 void rk32_edp_set_lane2_pre_emphasis(struct rk32_edp *edp, u32 level)
 902 {
 903         u32 val;
 904
 905         val = level << PRE_EMPHASIS_SET_SHIFT;
 906         writel(val, edp->regs + LN2_LINK_TRAINING_CTL);
 907 }
 908
 909 void rk32_edp_set_lane3_pre_emphasis(struct rk32_edp *edp, u32 level)
 910 {
 911         u32 val;
 912
 913         val = level << PRE_EMPHASIS_SET_SHIFT;
 914         writel(val, edp->regs + LN3_LINK_TRAINING_CTL);
 915 }
 916
 917 void rk32_edp_set_lane0_link_training(struct rk32_edp *edp,
 918                                         u32 training_lane)
 919 {
 920         u32 val;
 921
 922         val = training_lane;
 923         writel(val, edp->regs + LN0_LINK_TRAINING_CTL);
 924 }
 925
 926 void rk32_edp_set_lane1_link_training(struct rk32_edp *edp,
 927                                         u32 training_lane)
 928 {
 929         u32 val;
 930
 931         val = training_lane;
 932         writel(val, edp->regs + LN1_LINK_TRAINING_CTL);
 933 }
 934
 935 void rk32_edp_set_lane2_link_training(struct rk32_edp *edp,
 936                                         u32 training_lane)
 937 {
 938         u32 val;
 939
 940         val = training_lane;
 941         writel(val, edp->regs + LN2_LINK_TRAINING_CTL);
 942 }
 943
 944 void rk32_edp_set_lane3_link_training(struct rk32_edp *edp,
 945                                         u32 training_lane)
 946 {
 947         u32 val;
 948
 949         val = training_lane;
 950         writel(val, edp->regs + LN3_LINK_TRAINING_CTL);
 951 }
 952
 953 u32 rk32_edp_get_lane0_link_training(struct rk32_edp *edp)
 954 {
 955         u32 val;
 956
 957         val = readl(edp->regs + LN0_LINK_TRAINING_CTL);
 958         return val;
 959 }
 960
 961 u32 rk32_edp_get_lane1_link_training(struct rk32_edp *edp)
 962 {
 963         u32 val;
 964
 965         val = readl(edp->regs + LN1_LINK_TRAINING_CTL);
 966         return val;
 967 }
 968
 969 u32 rk32_edp_get_lane2_link_training(struct rk32_edp *edp)
 970 {
 971         u32 val;
 972
 973         val = readl(edp->regs + LN2_LINK_TRAINING_CTL);
 974         return val;
 975 }
 976
 977 u32 rk32_edp_get_lane3_link_training(struct rk32_edp *edp)
 978 {
 979         u32 val;
 980
 981         val = readl(edp->regs + LN3_LINK_TRAINING_CTL);
 982         return val;
 983 }
 984
 985 void rk32_edp_reset_macro(struct rk32_edp *edp)
 986 {
 987         /*u32 val;
 988
 989         val = readl(edp->regs + PHY_TEST);
 990         val |= MACRO_RST;
 991         writel(val, edp->regs + PHY_TEST);
 992
 993
 994         udelay(10);
 995
 996         val &= ~MACRO_RST;
 997         writel(val, edp->regs + PHY_TEST);*/
 998 }
 999
1000 int rk32_edp_init_video(struct rk32_edp *edp)
1001 {
1002         u32 val;
1003
1004         val = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1005         writel(val, edp->regs + COMMON_INT_STA_1);
1006
1007         val = 0x0;
1008         writel(val, edp->regs + SYS_CTL_1);
1009
1010         val = CHA_CRI(4) | CHA_CTRL;
1011         writel(val, edp->regs + SYS_CTL_2);
1012
1013         /*val = 0x0;
1014         writel(val, edp->regs + SYS_CTL_3);*/
1015
1016         val = VID_HRES_TH(2) | VID_VRES_TH(0);
1017         writel(val, edp->regs + VIDEO_CTL_8);
1018
1019         return 0;
1020 }
1021
1022 void rk32_edp_set_video_color_format(struct rk32_edp *edp,
1023                         u32 color_dedpth,
1024                         u32 color_space,
1025                         u32 dynamic_range,
1026                         u32 coeff)
1027 {
1028         u32 val;
1029
1030         /* Configure the input color dedpth, color space, dynamic range */
1031         val = (dynamic_range << IN_D_RANGE_SHIFT) |
1032                 (color_dedpth << IN_BPC_SHIFT) |
1033                 (color_space << IN_COLOR_F_SHIFT);
1034         writel(val, edp->regs + VIDEO_CTL_2);
1035
1036         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1037         val = readl(edp->regs + VIDEO_CTL_3);
1038         val &= ~IN_YC_COEFFI_MASK;
1039         if (coeff)
1040                 val |= IN_YC_COEFFI_ITU709;
1041         else
1042                 val |= IN_YC_COEFFI_ITU601;
1043         writel(val, edp->regs + VIDEO_CTL_3);
1044 }
1045
1046 int rk32_edp_is_slave_video_stream_clock_on(struct rk32_edp *edp)
1047 {
1048         u32 val;
1049
1050         val = readl(edp->regs + SYS_CTL_1);
1051         writel(val, edp->regs + SYS_CTL_1);
1052
1053         val = readl(edp->regs + SYS_CTL_1);
1054
1055         if (!(val & DET_STA)) {
1056                 dev_dbg(edp->dev, "Input stream clock not detected.\n");
1057                 return -EINVAL;
1058         }
1059
1060         val = readl(edp->regs + SYS_CTL_2);
1061         writel(val, edp->regs + SYS_CTL_2);
1062
1063         val = readl(edp->regs + SYS_CTL_2);
1064         if (val & CHA_STA) {
1065                 dev_dbg(edp->dev, "Input stream clk is changing\n");
1066                 return -EINVAL;
1067         }
1068
1069         return 0;
1070 }
1071
1072
1073 void rk32_edp_set_video_cr_mn(struct rk32_edp *edp,
1074                 enum clock_recovery_m_value_type type,
1075                 u32 m_value,
1076                 u32 n_value)
1077 {
1078         u32 val;
1079
1080         if (type == REGISTER_M) {
1081                 val = readl(edp->regs + SYS_CTL_4);
1082                 val |= FIX_M_VID;
1083                 writel(val, edp->regs + SYS_CTL_4);
1084                 val = m_value & 0xff;
1085                 writel(val, edp->regs + M_VID_0);
1086                 val = (m_value >> 8) & 0xff;
1087                 writel(val, edp->regs + M_VID_1);
1088                 val = (m_value >> 16) & 0xff;
1089                 writel(val, edp->regs + M_VID_2);
1090
1091                 val = n_value & 0xff;
1092                 writel(val, edp->regs + N_VID_0);
1093                 val = (n_value >> 8) & 0xff;
1094                 writel(val, edp->regs + N_VID_1);
1095                 val = (n_value >> 16) & 0xff;
1096                 writel(val, edp->regs + N_VID_2);
1097         } else  {
1098                 val = readl(edp->regs + SYS_CTL_4);
1099                 val &= ~FIX_M_VID;
1100                 writel(val, edp->regs + SYS_CTL_4);
1101
1102                 writel(0x00, edp->regs + N_VID_0);
1103                 writel(0x80, edp->regs + N_VID_1);
1104                 writel(0x00, edp->regs + N_VID_2);
1105         }
1106 }
1107
1108 void rk32_edp_set_video_timing_mode(struct rk32_edp *edp, u32 type)
1109 {
1110         u32 val;
1111
1112         if (type == VIDEO_TIMING_FROM_CAPTURE) {
1113                 val = readl(edp->regs + VIDEO_CTL_10);
1114                 val &= ~F_SEL;
1115                 writel(val, edp->regs + VIDEO_CTL_10);
1116         } else {
1117                 val = readl(edp->regs + VIDEO_CTL_10);
1118                 val |= F_SEL;
1119                 writel(val, edp->regs + VIDEO_CTL_10);
1120         }
1121 }
1122
1123 int rk32_edp_bist_cfg(struct rk32_edp *edp)
1124 {
1125         struct video_info *video_info = &edp->video_info;
1126         struct rk_screen *screen = &edp->screen;
1127         u16 x_total, y_total, x_act;
1128         u32 val;
1129         x_total = screen->mode.left_margin + screen->mode.right_margin +
1130                         screen->mode.xres + screen->mode.hsync_len;
1131         y_total = screen->mode.upper_margin + screen->mode.lower_margin +
1132                         screen->mode.yres + screen->mode.vsync_len;
1133         x_act = screen->mode.xres;
1134
1135         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1136         rk32_edp_set_video_color_format(edp, video_info->color_depth,
1137                                         video_info->color_space,
1138                                         video_info->dynamic_range,
1139                                         video_info->ycbcr_coeff);
1140
1141         val = y_total & 0xff;
1142         writel(val, edp->regs + TOTAL_LINE_CFG_L);
1143         val = (y_total >> 8);
1144         writel(val, edp->regs + TOTAL_LINE_CFG_H);
1145         val = (screen->mode.yres & 0xff);
1146         writel(val, edp->regs + ATV_LINE_CFG_L);
1147         val = (screen->mode.yres >> 8);
1148         writel(val, edp->regs + ATV_LINE_CFG_H);
1149         val = screen->mode.lower_margin;
1150         writel(val, edp->regs + VF_PORCH_REG);
1151         val = screen->mode.vsync_len;
1152         writel(val, edp->regs + VSYNC_CFG_REG);
1153         val = screen->mode.upper_margin;
1154         writel(val, edp->regs + VB_PORCH_REG);
1155         val = x_total & 0xff;
1156         writel(val, edp->regs + TOTAL_PIXELL_REG);
1157         val = x_total >> 8;
1158         writel(val, edp->regs + TOTAL_PIXELH_REG);
1159         val = (x_act & 0xff);
1160         writel(val, edp->regs + ATV_PIXELL_REG);
1161         val = (x_act >> 8);
1162         writel(val, edp->regs + ATV_PIXELH_REG);
1163         val = screen->mode.right_margin & 0xff;
1164         writel(val, edp->regs + HF_PORCHL_REG);
1165         val = screen->mode.right_margin >> 8;
1166         writel(val, edp->regs + HF_PORCHH_REG);
1167         val = screen->mode.hsync_len & 0xff;
1168         writel(val, edp->regs + HSYNC_CFGL_REG);
1169         val = screen->mode.hsync_len >> 8;
1170         writel(val, edp->regs + HSYNC_CFGH_REG);
1171         val = screen->mode.left_margin & 0xff;
1172         writel(val, edp->regs + HB_PORCHL_REG);
1173         val = screen->mode.left_margin  >> 8;
1174         writel(val, edp->regs + HB_PORCHH_REG);
1175
1176         val = BIST_EN | BIST_WH_64 | BIST_TYPE_COLR_BAR;
1177         writel(val, edp->regs + VIDEO_CTL_4);
1178
1179         val = readl(edp->regs + VIDEO_CTL_10);
1180         val &= ~F_SEL;
1181         writel(val, edp->regs + VIDEO_CTL_10);
1182         return 0;
1183
1184 }
1185
1186 void rk32_edp_enable_video_master(struct rk32_edp *edp, bool enable)
1187 {
1188         /*u32 val;
1189
1190         if (enable) {
1191                 val = readl(edp->regs + SOC_GENERAL_CTL);
1192                 val &= ~VIDEO_MODE_MASK;
1193                 val |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1194                 writel(val, edp->regs + SOC_GENERAL_CTL);
1195         } else {
1196                 val = readl(edp->regs + SOC_GENERAL_CTL);
1197                 val &= ~VIDEO_MODE_MASK;
1198                 val |= VIDEO_MODE_SLAVE_MODE;
1199                 writel(val, edp->regs + SOC_GENERAL_CTL);
1200         }*/
1201 }
1202
1203 void rk32_edp_start_video(struct rk32_edp *edp)
1204 {
1205         u32 val;
1206
1207         val = readl(edp->regs + VIDEO_CTL_1);
1208         val |= VIDEO_EN;
1209         writel(val, edp->regs + VIDEO_CTL_1);
1210 }
1211
1212 int rk32_edp_is_video_stream_on(struct rk32_edp *edp)
1213 {
1214         u32 val;
1215
1216         val = readl(edp->regs + SYS_CTL_3);
1217         writel(val, edp->regs + SYS_CTL_3);
1218
1219         val = readl(edp->regs + SYS_CTL_3);
1220         if (!(val & STRM_VALID)) {
1221                 dev_dbg(edp->dev, "Input video stream is not detected.\n");
1222                 return -EINVAL;
1223         }
1224
1225         return 0;
1226 }
1227
1228 void rk32_edp_config_video_slave_mode(struct rk32_edp *edp,
1229                         struct video_info *video_info)
1230 {
1231         u32 val;
1232
1233         val = readl(edp->regs + FUNC_EN_1);
1234         val &= ~(VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
1235         writel(val, edp->regs + FUNC_EN_1);
1236
1237         val = readl(edp->regs + VIDEO_CTL_10);
1238         val &= ~INTERACE_SCAN_CFG;
1239         val |= (video_info->interlaced << 2);
1240         writel(val, edp->regs + VIDEO_CTL_10);
1241
1242         val = readl(edp->regs + VIDEO_CTL_10);
1243         val &= ~VSYNC_POLARITY_CFG;
1244         val |= (video_info->v_sync_polarity << 1);
1245         writel(val, edp->regs + VIDEO_CTL_10);
1246
1247         val = readl(edp->regs + VIDEO_CTL_10);
1248         val &= ~HSYNC_POLARITY_CFG;
1249         val |= (video_info->h_sync_polarity << 0);
1250         writel(val, edp->regs + VIDEO_CTL_10);
1251
1252         /*val = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1253         writel(val, edp->regs + SOC_GENERAL_CTL);*/
1254 }
1255
1256 void rk32_edp_enable_scrambling(struct rk32_edp *edp)
1257 {
1258         u32 val;
1259
1260         val = readl(edp->regs + TRAINING_PTN_SET);
1261         val &= ~SCRAMBLING_DISABLE;
1262         writel(val, edp->regs + TRAINING_PTN_SET);
1263 }
1264
1265 void rk32_edp_disable_scrambling(struct rk32_edp *edp)
1266 {
1267         u32 val;
1268
1269         val = readl(edp->regs + TRAINING_PTN_SET);
1270         val |= SCRAMBLING_DISABLE;
1271         writel(val, edp->regs + TRAINING_PTN_SET);
1272 }
1273
1274 enum dp_irq_type rk32_edp_get_irq_type(struct rk32_edp *edp)
1275 {
1276         u32 val;
1277
1278         /* Parse hotplug interrupt status register */
1279         val = readl(edp->regs + COMMON_INT_STA_4);
1280         if (val & PLUG)
1281                 return DP_IRQ_TYPE_HP_CABLE_IN;
1282
1283         if (val & HPD_LOST)
1284                 return DP_IRQ_TYPE_HP_CABLE_OUT;
1285
1286         if (val & HOTPLUG_CHG)
1287                 return DP_IRQ_TYPE_HP_CHANGE;
1288
1289         return DP_IRQ_TYPE_UNKNOWN;
1290 }
1291
1292 void rk32_edp_clear_hotplug_interrupts(struct rk32_edp *edp)
1293 {
1294         u32 val;
1295
1296         val = HOTPLUG_CHG | HPD_LOST | PLUG;
1297         writel(val, edp->regs + COMMON_INT_STA_4);
1298
1299         val = INT_HPD;
1300         writel(val, edp->regs + DP_INT_STA);
1301 }