drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/rockchip/cpu.h>
  24 #include <linux/rockchip/iomap.h>
  25 #include <linux/rockchip/grf.h>
  26 #include <linux/string.h>
  27 #include <linux/slab.h>
  28 #include <linux/uaccess.h>
  29
  30 #if defined(CONFIG_OF)
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #endif
  34
  35 #if defined(CONFIG_DEBUG_FS)
  36 #include <linux/fs.h>
  37 #include <linux/debugfs.h>
  38 #include <linux/seq_file.h>
  39 #endif
  40
  41 #include "rk32_dp.h"
  42
  43 /*#define EDP_BIST_MODE*/
  44 /*#define SW_LT*/
  45
  46 #define RK3368_GRF_SOC_CON4     0x410
  47 #define RK3399_GRF_SOC_CON20    0x6250
  48
  49 static struct rk32_edp *rk32_edp;
  50
  51 static int rk32_edp_clk_enable(struct rk32_edp *edp)
  52 {
  53         int ret;
  54
  55         if (!edp->clk_on) {
  56                 if (edp->pd)
  57                         clk_prepare_enable(edp->pd);
  58                 clk_prepare_enable(edp->pclk);
  59                 clk_prepare_enable(edp->clk_edp);
  60
  61                 if (edp->soctype != SOC_RK3399) {
  62                         ret = clk_set_rate(edp->clk_24m, 24000000);
  63                         if (ret < 0)
  64                                 pr_err("cannot set edp clk_24m %d\n", ret);
  65                         clk_prepare_enable(edp->clk_24m);
  66                 }
  67                 edp->clk_on = true;
  68         }
  69
  70         return 0;
  71 }
  72
  73 static int rk32_edp_clk_disable(struct rk32_edp *edp)
  74 {
  75         if (edp->clk_on) {
  76                 clk_disable_unprepare(edp->pclk);
  77                 clk_disable_unprepare(edp->clk_edp);
  78
  79                 if (edp->soctype != SOC_RK3399)
  80                         clk_disable_unprepare(edp->clk_24m);
  81
  82                 if (edp->pd)
  83                         clk_disable_unprepare(edp->pd);
  84                 edp->clk_on = false;
  85         }
  86
  87         return 0;
  88 }
  89
  90 static int rk32_edp_pre_init(struct rk32_edp *edp)
  91 {
  92         u32 val;
  93
  94         if (cpu_is_rk3288()) {
  95                 val = GRF_EDP_REF_CLK_SEL_INTER |
  96                         (GRF_EDP_REF_CLK_SEL_INTER << 16);
  97                 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
  98
  99                 val = 0x80008000;
 100                 writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
 101                 dsb(sy);
 102                 udelay(1);
 103                 val = 0x80000000;
 104                 writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
 105                 dsb(sy);
 106                 udelay(1);
 107         } else {
 108                 /* The rk3368 reset the edp 24M clock and apb bus
 109                  * according to the CRU_SOFTRST6_CON and CRU_SOFTRST7_CON.
 110                  */
 111                 if (edp->soctype != SOC_RK3399) {
 112                         val = 0x01 | (0x01 << 16);
 113                         regmap_write(edp->grf, RK3368_GRF_SOC_CON4, val);
 114
 115                         reset_control_assert(edp->rst_24m);
 116                         usleep_range(10, 20);
 117                         reset_control_deassert(edp->rst_24m);
 118                 }
 119
 120                 reset_control_assert(edp->rst_apb);
 121                 usleep_range(10, 20);
 122                 reset_control_deassert(edp->rst_apb);
 123         }
 124         return 0;
 125 }
 126
 127 static int rk32_edp_init_edp(struct rk32_edp *edp)
 128 {
 129         struct rk_screen *screen = &edp->screen;
 130         u32 val = 0;
 131
 132         rk_fb_get_prmry_screen(screen);
 133
 134         if (cpu_is_rk3288()) {
 135                 if (screen->lcdc_id == 1)  /*select lcdc*/
 136                         val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
 137                 else
 138                         val = EDP_SEL_VOP_LIT << 16;
 139                 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
 140         }
 141
 142         if (edp->soctype == SOC_RK3399) {
 143                 if (screen->lcdc_id == 1)  /*select lcdc*/
 144                         val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
 145                 else
 146                         val = EDP_SEL_VOP_LIT << 16;
 147                 clk_prepare_enable(edp->grf_clk);
 148                 regmap_write(edp->grf, RK3399_GRF_SOC_CON20, val);
 149                 clk_disable_unprepare(edp->grf_clk);
 150         }
 151
 152         rk32_edp_reset(edp);
 153         rk32_edp_init_refclk(edp);
 154         rk32_edp_init_interrupt(edp);
 155         rk32_edp_enable_sw_function(edp);
 156         rk32_edp_init_analog_func(edp);
 157         rk32_edp_init_hpd(edp);
 158         rk32_edp_init_aux(edp);
 159
 160         return 0;
 161 }
 162
 163 /*#if 0
 164 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
 165 {
 166         int timeout_loop = 0;
 167
 168         rk32_edp_init_hpd(edp);
 169
 170         udelay(200);
 171
 172         while (rk32_edp_get_plug_in_status(edp) != 0) {
 173                 timeout_loop++;
 174                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 175                         dev_err(edp->dev, "failed to get hpd plug status\n");
 176                         return -ETIMEDOUT;
 177                 }
 178                 udelay(10);
 179         }
 180
 181         return 0;
 182 }
 183 #endif*/
 184
 185 static int rk32_edp_read_edid(struct rk32_edp *edp)
 186 {
 187         unsigned char edid[EDID_LENGTH * 2];
 188         unsigned int extend_block = 0;
 189         unsigned char sum;
 190         unsigned char test_vector;
 191         int retval;
 192
 193         /*
 194          * EDID device address is 0x50.
 195          * However, if necessary, you must have set upper address
 196          * into E-EDID in I2C device, 0x30.
 197          */
 198
 199         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 200         retval = rk32_edp_read_byte_from_i2c
 201                         (edp,
 202                          EDID_ADDR, EDID_EXTENSION_FLAG, &extend_block);
 203         if (retval < 0) {
 204                 dev_err(edp->dev, "EDID extension flag failed!\n");
 205                 return -EIO;
 206         }
 207
 208         if (extend_block > 0) {
 209                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
 210
 211                 /* Read EDID data */
 212                 retval = rk32_edp_read_bytes_from_i2c
 213                                (edp,
 214                                 EDID_ADDR, EDID_HEADER,
 215                                 EDID_LENGTH, &edid[EDID_HEADER]);
 216                 if (retval != 0) {
 217                         dev_err(edp->dev, "EDID Read failed!\n");
 218                         return -EIO;
 219                 }
 220                 sum = edp_calc_edid_check_sum(edid);
 221                 if (sum != 0) {
 222                         dev_warn(edp->dev, "EDID bad checksum!\n");
 223                         return 0;
 224                 }
 225
 226                 /* Read additional EDID data */
 227                 retval = rk32_edp_read_bytes_from_i2c
 228                                (edp,
 229                                 EDID_ADDR, EDID_LENGTH,
 230                                 EDID_LENGTH, &edid[EDID_LENGTH]);
 231                 if (retval != 0) {
 232                         dev_err(edp->dev, "EDID Read failed!\n");
 233                         return -EIO;
 234                 }
 235                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
 236                 if (sum != 0) {
 237                         dev_warn(edp->dev, "EDID bad checksum!\n");
 238                         return 0;
 239                 }
 240
 241                 retval = rk32_edp_read_byte_from_dpcd
 242                                 (edp,
 243                                  DPCD_TEST_REQUEST, &test_vector);
 244                 if (retval < 0) {
 245                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 246                         return retval;
 247                 }
 248
 249                 if (test_vector & DPCD_TEST_EDID_READ) {
 250                         retval = rk32_edp_write_byte_to_dpcd
 251                                        (edp,
 252                                         DPCD_TEST_EDID_CHECKSUM,
 253                                         edid[EDID_LENGTH + EDID_CHECKSUM]);
 254                         if (retval < 0) {
 255                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 256                                 return retval;
 257                         }
 258                         retval = rk32_edp_write_byte_to_dpcd
 259                                        (edp,
 260                                         DPCD_TEST_RESPONSE,
 261                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 262                         if (retval < 0) {
 263                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 264                                 return retval;
 265                         }
 266                 }
 267         } else {
 268                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 269
 270                 /* Read EDID data */
 271                 retval = rk32_edp_read_bytes_from_i2c
 272                                (edp,
 273                                 EDID_ADDR, EDID_HEADER,
 274                                 EDID_LENGTH, &edid[EDID_HEADER]);
 275                 if (retval != 0) {
 276                         dev_err(edp->dev, "EDID Read failed!\n");
 277                         return -EIO;
 278                 }
 279                 sum = edp_calc_edid_check_sum(edid);
 280                 if (sum != 0) {
 281                         dev_warn(edp->dev, "EDID bad checksum!\n");
 282                         return 0;
 283                 }
 284
 285                 retval = rk32_edp_read_byte_from_dpcd
 286                                 (edp,
 287                                  DPCD_TEST_REQUEST, &test_vector);
 288                 if (retval < 0) {
 289                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 290                         return retval;
 291                 }
 292
 293                 if (test_vector & DPCD_TEST_EDID_READ) {
 294                         retval = rk32_edp_write_byte_to_dpcd
 295                                         (edp,
 296                                          DPCD_TEST_EDID_CHECKSUM,
 297                                          edid[EDID_CHECKSUM]);
 298                         if (retval < 0) {
 299                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 300                                 return retval;
 301                         }
 302                         retval = rk32_edp_write_byte_to_dpcd
 303                                        (edp,
 304                                         DPCD_TEST_RESPONSE,
 305                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 306                         if (retval < 0) {
 307                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 308                                 return retval;
 309                         }
 310                 }
 311         }
 312         fb_edid_to_monspecs(edid, &edp->specs);
 313         dev_err(edp->dev, "EDID Read success!\n");
 314         return 0;
 315 }
 316 #define open_t 0
 317 #if open_t
 318 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 319 {
 320         u8 buf[12];
 321         int i;
 322         int retval;
 323
 324         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 325         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
 326         if (retval < 0)
 327                 return retval;
 328
 329         for (i = 0; i < 12; i++)
 330                 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
 331         /* Read EDID */
 332         for (i = 0; i < 3; i++) {
 333                 retval = rk32_edp_read_edid(edp);
 334                 if (retval == 0)
 335                         break;
 336         }
 337
 338         return retval;
 339 }
 340
 341
 342 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 343                                                bool enable)
 344 {
 345         u8 data;
 346         int retval;
 347
 348         retval = rk32_edp_read_byte_from_dpcd
 349                         (edp,
 350                          DPCD_LANE_CNT_SET, &data);
 351         if (retval < 0)
 352                 return retval;
 353
 354         if (enable) {
 355                 retval = rk32_edp_write_byte_to_dpcd
 356                                 (edp,
 357                                  DPCD_LANE_CNT_SET,
 358                                  DPCD_ENHANCED_FRAME_EN |
 359                                  DPCD_LANE_COUNT_SET(data));
 360         } else {
 361                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 362                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 363
 364                 retval = rk32_edp_write_byte_to_dpcd
 365                                 (edp,
 366                                  DPCD_LANE_CNT_SET,
 367                                  DPCD_LANE_COUNT_SET(data));
 368         }
 369
 370         return retval;
 371 }
 372
 373 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 374 {
 375         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 376         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 377
 378         if (enable) {
 379                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 380                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 381         } else {
 382                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 383         }*/
 384 }
 385
 386
 387 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 388 {
 389         u8 data;
 390         int retval;
 391
 392         retval = rk32_edp_read_byte_from_dpcd
 393                         (edp,
 394                          DPCD_MAX_LANE_CNT, &data);
 395         if (retval < 0)
 396                 return retval;
 397
 398         return DPCD_ENHANCED_FRAME_CAP(data);
 399 }
 400
 401
 402 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 403 {
 404         /*rk32_edp_write_byte_to_dpcd(edp,
 405                         DPCD_ADDR_USER_DEFINED1, 0);
 406         rk32_edp_write_byte_to_dpcd(edp,
 407                         DPCD_ADDR_USER_DEFINED2, 0x83);
 408         rk32_edp_write_byte_to_dpcd(edp,
 409                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 410 }
 411
 412 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 413 {
 414         u8 data;
 415         int retval;
 416
 417         retval = rk32_edp_is_enhanced_mode_available(edp);
 418         if (retval < 0)
 419                 return retval;
 420
 421         data = (u8)retval;
 422         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 423         if (retval < 0)
 424                 return retval;
 425
 426         rk32_edp_enable_enhanced_mode(edp, data);
 427
 428         return 0;
 429 }
 430 #endif
 431
 432
 433 #if defined(SW_LT)
 434 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 435 {
 436         int retval;
 437
 438         rk32_edp_set_training_pattern(edp, DP_NONE);
 439
 440         retval = rk32_edp_write_byte_to_dpcd(edp,
 441                                              DPCD_TRAINING_PATTERN_SET,
 442                                              DPCD_TRAINING_PATTERN_DISABLED);
 443         if (retval < 0)
 444                 return retval;
 445
 446         return 0;
 447 }
 448
 449 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 450                                                 int pre_emphasis, int lane)
 451 {
 452         switch (lane) {
 453         case 0:
 454                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 455                 break;
 456         case 1:
 457                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 458                 break;
 459
 460         case 2:
 461                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 462                 break;
 463
 464         case 3:
 465                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 466                 break;
 467         }
 468 }
 469
 470 static int rk32_edp_link_start(struct rk32_edp *edp)
 471 {
 472         u8 buf[4];
 473         int lane;
 474         int lane_count;
 475         int retval;
 476
 477         lane_count = edp->link_train.lane_count;
 478
 479         edp->link_train.lt_state = LT_CLK_RECOVERY;
 480         edp->link_train.eq_loop = 0;
 481
 482         for (lane = 0; lane < lane_count; lane++)
 483                 edp->link_train.cr_loop[lane] = 0;
 484
 485         /* Set sink to D0 (Sink Not Ready) mode. */
 486         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
 487                                              DPCD_SET_POWER_STATE_D0);
 488         if (retval < 0) {
 489                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 490                 return retval;
 491         }
 492
 493         /* Set link rate and count as you want to establish*/
 494         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 495         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 496
 497         /* Setup RX configuration */
 498         buf[0] = edp->link_train.link_rate;
 499         buf[1] = edp->link_train.lane_count;
 500         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
 501                                               2, buf);
 502         if (retval < 0) {
 503                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 504                 return retval;
 505         }
 506
 507         /* Set TX pre-emphasis to level1 */
 508         for (lane = 0; lane < lane_count; lane++)
 509                 rk32_edp_set_lane_lane_pre_emphasis
 510                         (edp,
 511                          PRE_EMPHASIS_LEVEL_1, lane);
 512
 513         /* Set training pattern 1 */
 514         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 515
 516         /* Set RX training pattern */
 517         retval = rk32_edp_write_byte_to_dpcd(edp,
 518                                              DPCD_TRAINING_PATTERN_SET,
 519                                              DPCD_SCRAMBLING_DISABLED |
 520                                              DPCD_TRAINING_PATTERN_1);
 521         if (retval < 0) {
 522                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 523                 return retval;
 524         }
 525
 526         for (lane = 0; lane < lane_count; lane++)
 527                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 528                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 529         retval = rk32_edp_write_bytes_to_dpcd(edp,
 530                                               DPCD_TRAINING_LANE0_SET,
 531                                               lane_count, buf);
 532         if (retval < 0) {
 533                 dev_err(edp->dev, "failed to set training lane!\n");
 534                 return retval;
 535         }
 536
 537         return 0;
 538 }
 539
 540 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 541 {
 542         int shift = (lane & 1) * 4;
 543         u8 link_value = link_status[lane>>1];
 544
 545         return (link_value >> shift) & 0xf;
 546 }
 547
 548 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 549 {
 550         int lane;
 551         u8 lane_status;
 552
 553         for (lane = 0; lane < lane_count; lane++) {
 554                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 555                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 556                         return -EINVAL;
 557         }
 558         return 0;
 559 }
 560
 561 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 562 {
 563         int lane;
 564         u8 lane_align;
 565         u8 lane_status;
 566
 567         lane_align = link_align[2];
 568         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 569                 return -EINVAL;
 570
 571         for (lane = 0; lane < lane_count; lane++) {
 572                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 573                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 574                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 575                         return -EINVAL;
 576         }
 577
 578         return 0;
 579 }
 580
 581 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 582                                                          int lane)
 583 {
 584         int shift = (lane & 1) * 4;
 585         u8 link_value = adjust_request[lane>>1];
 586
 587         return (link_value >> shift) & 0x3;
 588 }
 589
 590 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 591                                         u8 adjust_request[2],
 592                                         int lane)
 593 {
 594         int shift = (lane & 1) * 4;
 595         u8 link_value = adjust_request[lane>>1];
 596
 597         return ((link_value >> shift) & 0xc) >> 2;
 598 }
 599
 600 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 601                                             u8 training_lane_set, int lane)
 602 {
 603         switch (lane) {
 604         case 0:
 605                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 606                 break;
 607         case 1:
 608                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 609                 break;
 610
 611         case 2:
 612                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 613                 break;
 614
 615         case 3:
 616                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 617                 break;
 618         }
 619 }
 620
 621 static unsigned int rk32_edp_get_lane_link_training(
 622                                                     struct rk32_edp *edp,
 623                                                     int lane)
 624 {
 625         u32 reg;
 626
 627         switch (lane) {
 628         case 0:
 629                 reg = rk32_edp_get_lane0_link_training(edp);
 630                 break;
 631         case 1:
 632                 reg = rk32_edp_get_lane1_link_training(edp);
 633                 break;
 634         case 2:
 635                 reg = rk32_edp_get_lane2_link_training(edp);
 636                 break;
 637         case 3:
 638                 reg = rk32_edp_get_lane3_link_training(edp);
 639                 break;
 640         }
 641
 642         return reg;
 643 }
 644
 645 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 646 {
 647         rk32_edp_training_pattern_dis(edp);
 648
 649         edp->link_train.lt_state = FAILED;
 650 }
 651
 652 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 653 {
 654         u8 link_status[2];
 655         int lane;
 656         int lane_count;
 657
 658         u8 adjust_request[2];
 659         u8 voltage_swing;
 660         u8 pre_emphasis;
 661         u8 training_lane;
 662         int retval;
 663
 664         /*udelay(100);*/
 665         usleep_range(99, 100);
 666
 667         lane_count = edp->link_train.lane_count;
 668
 669         retval = rk32_edp_read_bytes_from_dpcd(edp,
 670                                                DPCD_LANE0_1_STATUS,
 671                                                2, link_status);
 672         if (retval < 0) {
 673                 dev_err(edp->dev, "failed to read lane status!\n");
 674                 return retval;
 675         }
 676
 677         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 678                 /* set training pattern 2 for EQ */
 679                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 680
 681                 for (lane = 0; lane < lane_count; lane++) {
 682                         retval = rk32_edp_read_bytes_from_dpcd
 683                                         (edp,
 684                                          DPCD_ADJUST_REQUEST_LANE0_1,
 685                                          2, adjust_request);
 686                         if (retval < 0) {
 687                                 dev_err(edp->dev, "failed to read adjust request!\n");
 688                                 return retval;
 689                         }
 690
 691                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 692                                                         adjust_request, lane);
 693                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 694                                                         adjust_request, lane);
 695                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 696                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 697
 698                         if (voltage_swing == VOLTAGE_LEVEL_3)
 699                                 training_lane |= DPCD_MAX_SWING_REACHED;
 700                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 701                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 702
 703                         edp->link_train.training_lane[lane] = training_lane;
 704
 705                         rk32_edp_set_lane_link_training
 706                                 (edp,
 707                                  edp->link_train.training_lane[lane],
 708                                  lane);
 709                 }
 710
 711                 retval = rk32_edp_write_byte_to_dpcd(edp,
 712                                                      DPCD_TRAINING_PATTERN_SET,
 713                                                      DPCD_SCRAMBLING_DISABLED |
 714                                                      DPCD_TRAINING_PATTERN_2);
 715                 if (retval < 0) {
 716                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 717                         return retval;
 718                 }
 719
 720                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 721                                                       DPCD_TRAINING_LANE0_SET,
 722                                                       lane_count,
 723                                 edp->link_train.training_lane);
 724                 if (retval < 0) {
 725                         dev_err(edp->dev, "failed to set training lane!\n");
 726                         return retval;
 727                 }
 728
 729                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 730                 edp->link_train.lt_state = LT_EQ_TRAINING;
 731         } else {
 732                 for (lane = 0; lane < lane_count; lane++) {
 733                         training_lane = rk32_edp_get_lane_link_training(
 734                                                         edp, lane);
 735                         retval = rk32_edp_read_bytes_from_dpcd
 736                                         (edp,
 737                                          DPCD_ADJUST_REQUEST_LANE0_1,
 738                                          2, adjust_request);
 739                         if (retval < 0) {
 740                                 dev_err(edp->dev, "failed to read adjust request!\n");
 741                                 return retval;
 742                         }
 743
 744                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 745                                                         adjust_request, lane);
 746                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 747                                                         adjust_request, lane);
 748
 749                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 750                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 751                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 752                                 goto reduce_link_rate;
 753                         }
 754
 755                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 756                                         voltage_swing) &&
 757                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 758                                         pre_emphasis)) {
 759                                 edp->link_train.cr_loop[lane]++;
 760                                 if (edp->link_train.cr_loop[lane] ==
 761                                         MAX_CR_LOOP) {
 762                                         dev_err(edp->dev, "CR Max loop\n");
 763                                         goto reduce_link_rate;
 764                                 }
 765                         }
 766
 767                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 768                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 769
 770                         if (voltage_swing == VOLTAGE_LEVEL_3)
 771                                 training_lane |= DPCD_MAX_SWING_REACHED;
 772                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 773                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 774
 775                         edp->link_train.training_lane[lane] = training_lane;
 776
 777                         rk32_edp_set_lane_link_training
 778                                 (edp,
 779                                  edp->link_train.training_lane[lane], lane);
 780                 }
 781
 782                 retval = rk32_edp_write_bytes_to_dpcd
 783                                 (edp,
 784                                  DPCD_TRAINING_LANE0_SET,
 785                                  lane_count,
 786                                  edp->link_train.training_lane);
 787                 if (retval < 0) {
 788                         dev_err(edp->dev, "failed to set training lane!\n");
 789                         return retval;
 790                 }
 791         }
 792
 793         return 0;
 794
 795 reduce_link_rate:
 796         rk32_edp_reduce_link_rate(edp);
 797         return -EIO;
 798 }
 799
 800 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 801 {
 802         u8 link_status[2];
 803         u8 link_align[3];
 804         int lane;
 805         int lane_count;
 806         u32 reg;
 807
 808         u8 adjust_request[2];
 809         u8 voltage_swing;
 810         u8 pre_emphasis;
 811         u8 training_lane;
 812         int retval;
 813
 814         /*udelay(400);*/
 815         usleep_range(399, 400);
 816
 817         lane_count = edp->link_train.lane_count;
 818
 819         retval = rk32_edp_read_bytes_from_dpcd(edp,
 820                                                DPCD_LANE0_1_STATUS,
 821                                                2, link_status);
 822         if (retval < 0) {
 823                 dev_err(edp->dev, "failed to read lane status!\n");
 824                 return retval;
 825         }
 826
 827         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 828                 link_align[0] = link_status[0];
 829                 link_align[1] = link_status[1];
 830
 831                 retval = rk32_edp_read_byte_from_dpcd
 832                                 (edp,
 833                                  DPCD_LANE_ALIGN_STATUS_UPDATED,
 834                                  &link_align[2]);
 835                 if (retval < 0) {
 836                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 837                         return retval;
 838                 }
 839
 840                 for (lane = 0; lane < lane_count; lane++) {
 841                         retval = rk32_edp_read_bytes_from_dpcd
 842                                         (edp,
 843                                          DPCD_ADJUST_REQUEST_LANE0_1,
 844                                          2, adjust_request);
 845                         if (retval < 0) {
 846                                 dev_err(edp->dev, "failed to read adjust request!\n");
 847                                 return retval;
 848                         }
 849
 850                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 851                                                         adjust_request, lane);
 852                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 853                                                         adjust_request, lane);
 854                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 855                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 856
 857                         if (voltage_swing == VOLTAGE_LEVEL_3)
 858                                 training_lane |= DPCD_MAX_SWING_REACHED;
 859                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 860                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 861
 862                         edp->link_train.training_lane[lane] = training_lane;
 863                 }
 864
 865                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 866                         /* traing pattern Set to Normal */
 867                         retval = rk32_edp_training_pattern_dis(edp);
 868                         if (retval < 0) {
 869                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 870                                 return retval;
 871                         }
 872
 873                         dev_info(edp->dev, "Link Training success!\n");
 874
 875                         rk32_edp_get_link_bandwidth(edp, &reg);
 876                         edp->link_train.link_rate = reg;
 877                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 878                                 edp->link_train.link_rate);
 879
 880                         rk32_edp_get_lane_count(edp, &reg);
 881                         edp->link_train.lane_count = reg;
 882                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 883                                 edp->link_train.lane_count);
 884
 885                         edp->link_train.lt_state = FINISHED;
 886                 } else {
 887                         /* not all locked */
 888                         edp->link_train.eq_loop++;
 889
 890                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 891                                 dev_err(edp->dev, "EQ Max loop\n");
 892                                 goto reduce_link_rate;
 893                         }
 894
 895                         for (lane = 0; lane < lane_count; lane++)
 896                                 rk32_edp_set_lane_link_training
 897                                 (edp,
 898                                  edp->link_train.training_lane[lane],
 899                                  lane);
 900
 901                         retval = rk32_edp_write_bytes_to_dpcd
 902                                         (edp,
 903                                          DPCD_TRAINING_LANE0_SET,
 904                                          lane_count,
 905                                          edp->link_train.training_lane);
 906                         if (retval < 0) {
 907                                 dev_err(edp->dev, "failed to set training lane!\n");
 908                                 return retval;
 909                         }
 910                 }
 911         } else {
 912                 goto reduce_link_rate;
 913         }
 914
 915         return 0;
 916
 917 reduce_link_rate:
 918         rk32_edp_reduce_link_rate(edp);
 919         return -EIO;
 920 }
 921 #endif
 922 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 923                                          u8 *bandwidth)
 924 {
 925         u8 data;
 926         int retval = 0;
 927
 928         /*
 929          * For DP rev.1.1, Maximum link rate of Main Link lanes
 930          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 931          */
 932         retval = rk32_edp_read_byte_from_dpcd(edp,
 933                                               DPCD_MAX_LINK_RATE, &data);
 934         if (retval < 0)
 935                 *bandwidth = 0;
 936         else
 937                 *bandwidth = data;
 938         return retval;
 939 }
 940
 941 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 942                                           u8 *lane_count)
 943 {
 944         u8 data;
 945         int retval;
 946
 947         /*
 948          * For DP rev.1.1, Maximum number of Main Link lanes
 949          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 950          */
 951         retval = rk32_edp_read_byte_from_dpcd(edp,
 952                                               DPCD_MAX_LANE_CNT, &data);
 953         if (retval < 0)
 954                 *lane_count = 0;
 955         else
 956                 *lane_count = DPCD_MAX_LANE_COUNT(data);
 957         return retval;
 958 }
 959
 960 static int rk32_edp_init_training(struct rk32_edp *edp)
 961 {
 962         int retval;
 963
 964         /*
 965          * MACRO_RST must be applied after the PLL_LOCK to avoid
 966          * the DP inter pair skew issue for at least 10 us
 967          */
 968         rk32_edp_reset_macro(edp);
 969
 970
 971         retval = rk32_edp_get_max_rx_bandwidth(edp,
 972                                                &edp->link_train.link_rate);
 973         retval = rk32_edp_get_max_rx_lane_count(edp,
 974                                                 &edp->link_train.lane_count);
 975         dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
 976                  edp->link_train.link_rate * 27/100,
 977                  edp->link_train.link_rate*27%100,
 978                  edp->link_train.lane_count);
 979
 980         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 981             (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 982                 dev_warn
 983                 (edp->dev,
 984                  "Rx Mx Link Rate is abnormal:%x!default link rate:%d.%dGps\n",
 985                  edp->link_train.link_rate,
 986                  edp->video_info.link_rate*27/100,
 987                  edp->video_info.link_rate*27%100);
 988                 edp->link_train.link_rate = edp->video_info.link_rate;
 989         }
 990
 991         if (edp->link_train.lane_count == 0) {
 992                 dev_err
 993                 (edp->dev,
 994                  "Rx Max Lane count is abnormal :%x !use default lanes:%d\n",
 995                  edp->link_train.lane_count,
 996                  edp->video_info.lane_count);
 997                 edp->link_train.lane_count = edp->video_info.lane_count;
 998         }
 999
1000         rk32_edp_analog_power_ctr(edp, 1);
1001
1002
1003         return 0;
1004 }
1005
1006 #if defined(SW_LT)
1007 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
1008 {
1009         int retval = 0;
1010         int training_finished = 0;
1011
1012         edp->link_train.lt_state = LT_START;
1013
1014         /* Process here */
1015         while (!training_finished) {
1016                 switch (edp->link_train.lt_state) {
1017                 case LT_START:
1018                         retval = rk32_edp_link_start(edp);
1019                         if (retval)
1020                                 dev_err(edp->dev, "LT Start failed\n");
1021                         break;
1022                 case LT_CLK_RECOVERY:
1023                         retval = rk32_edp_process_clock_recovery(edp);
1024                         if (retval)
1025                                 dev_err(edp->dev, "LT CR failed\n");
1026                         break;
1027                 case LT_EQ_TRAINING:
1028                         retval = rk32_edp_process_equalizer_training(edp);
1029                         if (retval)
1030                                 dev_err(edp->dev, "LT EQ failed\n");
1031                         break;
1032                 case FINISHED:
1033                         training_finished = 1;
1034                         break;
1035                 case FAILED:
1036                         return -EREMOTEIO;
1037                 }
1038         }
1039
1040         return retval;
1041 }
1042
1043 #else
1044 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
1045 {
1046         u32 cnt = 50;
1047         u32 val;
1048         /* Set link rate and count as you want to establish*/
1049         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1050         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1051         rk32_edp_hw_link_training_en(edp);
1052         val = rk32_edp_wait_hw_lt_done(edp);
1053         while (val) {
1054                 if (cnt-- <= 0) {
1055                         dev_err(edp->dev, "hw lt timeout");
1056                         return -ETIMEDOUT;
1057                 }
1058                 mdelay(1);
1059                 val = rk32_edp_wait_hw_lt_done(edp);
1060         }
1061
1062         val = rk32_edp_get_hw_lt_status(edp);
1063         if (val)
1064                 dev_err(edp->dev, "hw lt err:%d\n", val);
1065         return val;
1066 }
1067 #endif
1068
1069 static int rk32_edp_set_link_train(struct rk32_edp *edp)
1070 {
1071         int retval;
1072
1073         retval = rk32_edp_init_training(edp);
1074         if (retval < 0)
1075                 dev_err(edp->dev, "DP LT init failed!\n");
1076 #if defined(SW_LT)
1077         retval = rk32_edp_sw_link_training(edp);
1078 #else
1079         retval = rk32_edp_hw_link_training(edp);
1080 #endif
1081
1082         return retval;
1083 }
1084
1085 static int rk32_edp_config_video(struct rk32_edp *edp,
1086                                  struct video_info *video_info)
1087 {
1088         int retval = 0;
1089         int timeout_loop = 0;
1090         int done_count = 0;
1091
1092         rk32_edp_config_video_slave_mode(edp, video_info);
1093
1094         rk32_edp_set_video_color_format(edp, video_info->color_depth,
1095                                         video_info->color_space,
1096                                         video_info->dynamic_range,
1097                                         video_info->ycbcr_coeff);
1098
1099         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
1100                 dev_err(edp->dev, "PLL is not locked yet.\n");
1101                 return -EINVAL;
1102         }
1103
1104         for (;;) {
1105                 timeout_loop++;
1106                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
1107                         break;
1108                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1109                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1110                         return -ETIMEDOUT;
1111                 }
1112
1113                 udelay(1);
1114         }
1115
1116         /* Set to use the register calculated M/N video */
1117         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1118
1119         /* For video bist, Video timing must be generated by register */
1120 #ifndef EDP_BIST_MODE
1121         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
1122 #endif
1123         /* Disable video mute */
1124         rk32_edp_enable_video_mute(edp, 0);
1125
1126         /* Configure video slave mode */
1127         rk32_edp_enable_video_master(edp, 0);
1128
1129         /* Enable video */
1130         rk32_edp_start_video(edp);
1131
1132         timeout_loop = 0;
1133
1134         for (;;) {
1135                 timeout_loop++;
1136                 if (rk32_edp_is_video_stream_on(edp) == 0) {
1137                         done_count++;
1138                         if (done_count > 10)
1139                                 break;
1140                 } else if (done_count) {
1141                         done_count = 0;
1142                 }
1143                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1144                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1145                         return -ETIMEDOUT;
1146                 }
1147
1148                 mdelay(1);
1149         }
1150
1151         if (retval != 0)
1152                 dev_err(edp->dev, "Video stream is not detected!\n");
1153
1154         return retval;
1155 }
1156
1157 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1158 {
1159         struct rk32_edp *edp = arg;
1160         enum dp_irq_type irq_type;
1161
1162         irq_type = rk32_edp_get_irq_type(edp);
1163         switch (irq_type) {
1164         case DP_IRQ_TYPE_HP_CABLE_IN:
1165                 dev_info(edp->dev, "Received irq - cable in\n");
1166                 rk32_edp_clear_hotplug_interrupts(edp);
1167                 break;
1168         case DP_IRQ_TYPE_HP_CABLE_OUT:
1169                 dev_info(edp->dev, "Received irq - cable out\n");
1170                 rk32_edp_clear_hotplug_interrupts(edp);
1171                 break;
1172         case DP_IRQ_TYPE_HP_CHANGE:
1173                 /*
1174                  * We get these change notifications once in a while, but there
1175                  * is nothing we can do with them. Just ignore it for now and
1176                  * only handle cable changes.
1177                  */
1178                 dev_info(edp->dev, "Received irq - hotplug change; ignoring.\n");
1179                 rk32_edp_clear_hotplug_interrupts(edp);
1180                 break;
1181         default:
1182                 dev_err(edp->dev, "Received irq - unknown type!\n");
1183                 break;
1184         }
1185         return IRQ_HANDLED;
1186 }
1187
1188 static int rk32_edp_enable(void)
1189 {
1190         int ret = 0;
1191         struct rk32_edp *edp = rk32_edp;
1192
1193         if (!edp->edp_en) {
1194                 rk32_edp_clk_enable(edp);
1195                 pm_runtime_get_sync(edp->dev);
1196                 rk32_edp_pre_init(edp);
1197                 rk32_edp_init_edp(edp);
1198                 enable_irq(edp->irq);
1199                 /*ret = rk32_edp_handle_edid(edp);
1200                 if (ret) {
1201                         dev_err(edp->dev, "unable to handle edid\n");
1202                         //goto out;
1203                 }
1204
1205                 ret = rk32_edp_enable_scramble(edp, 0);
1206                 if (ret) {
1207                         dev_err(edp->dev, "unable to set scramble\n");
1208                         //goto out;
1209                 }
1210
1211                 ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1212                 if (ret) {
1213                         dev_err(edp->dev, "unable to set enhanced mode\n");
1214                         //goto out;
1215                 }
1216                 rk32_edp_enable_enhanced_mode(edp, 1);*/
1217
1218                 ret = rk32_edp_set_link_train(edp);
1219                 if (ret)
1220                         dev_err(edp->dev, "link train failed!\n");
1221                 else
1222                         dev_info(edp->dev, "link training success.\n");
1223
1224                 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1225                 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1226                 rk32_edp_init_video(edp);
1227
1228 #ifdef EDP_BIST_MODE
1229                 rk32_edp_bist_cfg(edp);
1230 #endif
1231                 ret = rk32_edp_config_video(edp, &edp->video_info);
1232                 if (ret)
1233                         dev_err(edp->dev, "unable to config video\n");
1234
1235                 edp->edp_en = true;
1236         }
1237         return ret;
1238 }
1239
1240 static int  rk32_edp_disable(void)
1241 {
1242         struct rk32_edp *edp = rk32_edp;
1243
1244         if (edp->edp_en) {
1245                 edp->edp_en = false;
1246                 disable_irq(edp->irq);
1247                 rk32_edp_reset(edp);
1248                 rk32_edp_analog_power_ctr(edp, 0);
1249                 rk32_edp_clk_disable(edp);
1250                 pm_runtime_put_sync(edp->dev);
1251         }
1252
1253         return 0;
1254 }
1255
1256
1257 static struct rk_fb_trsm_ops trsm_edp_ops = {
1258         .enable = rk32_edp_enable,
1259         .disable = rk32_edp_disable,
1260 };
1261
1262 /*#if 0
1263 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1264 {
1265         u8 data;
1266         int retval;
1267
1268         if (enable) {
1269                 rk32_edp_enable_scrambling(edp);
1270
1271                 retval = rk32_edp_read_byte_from_dpcd
1272                                 (edp,
1273                                  DPCD_TRAINING_PATTERN_SET,
1274                                  &data);
1275                 if (retval < 0)
1276                         return retval;
1277
1278                 retval = rk32_edp_write_byte_to_dpcd
1279                                 (edp,
1280                                  DPCD_TRAINING_PATTERN_SET,
1281                                  (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1282                 if (retval < 0)
1283                         return retval;
1284         } else {
1285                 rk32_edp_disable_scrambling(edp);
1286
1287                 retval = rk32_edp_read_byte_from_dpcd
1288                                 (edp,
1289                                  DPCD_TRAINING_PATTERN_SET,
1290                                  &data);
1291                 if (retval < 0)
1292                         return retval;
1293
1294                 retval = rk32_edp_write_byte_to_dpcd
1295                                 (edp,
1296                                  DPCD_TRAINING_PATTERN_SET,
1297                                  (u8)(data | DPCD_SCRAMBLING_DISABLED));
1298                 if (retval < 0)
1299                         return retval;
1300         }
1301
1302         return 0;
1303 }
1304 #endif*/
1305 static int rk32_edp_psr_enable(struct rk32_edp *edp)
1306 {
1307         u8 buf;
1308         int retval;
1309         char date, psr_version;
1310
1311         /*if support PSR*/
1312         retval = rk32_edp_read_byte_from_dpcd
1313                         (edp,
1314                          PANEL_SELF_REFRESH_CAPABILITY_SUPPORTED_AND_VERSION,
1315                          &psr_version);
1316         if (retval < 0) {
1317                 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1318                 return retval;
1319         } else {
1320                 pr_info("PSR supporter and version:%x\n", psr_version);
1321         }
1322
1323          /*PSR capabilities*/
1324         retval = rk32_edp_read_byte_from_dpcd
1325                         (edp,
1326                          PANEL_SELF_REFRESH_CAPABILITIES, &date);
1327         if (retval < 0) {
1328                 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1329                 return retval;
1330         } else {
1331                 pr_info("PSR capabilities:%x\n", date);
1332         }
1333
1334         if (psr_version & PSR_SUPPORT) {
1335                 pr_info("PSR config psr\n");
1336
1337                 /*config sink PSR*/
1338                 buf = 0x02;
1339                 retval = rk32_edp_write_bytes_to_dpcd(edp, PSR_ENABLE,
1340                                                       1, &buf);
1341                 if (retval < 0) {
1342                         dev_err(edp->dev, "PSR failed to config sink PSR!\n");
1343                         return retval;
1344                 } else {
1345                         /*enable the PSR*/
1346                         buf = 0x03;
1347                         retval = rk32_edp_write_bytes_to_dpcd(edp,
1348                                                               PSR_ENABLE,
1349                                                               1, &buf);
1350                         if (retval < 0) {
1351                                 dev_err(edp->dev, "PSR failed to enable the PSR!\n");
1352                                 return retval;
1353                         }
1354                         /*read sink config state*/
1355                         retval = rk32_edp_read_byte_from_dpcd
1356                                                 (edp,
1357                                                  PSR_ENABLE, &date);
1358                         if (retval < 0) {
1359                                 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1360                                 return retval;
1361                         } else {
1362                                 pr_info("PSR sink config state:%x\n", date);
1363                         }
1364                 }
1365
1366                 /*enable sink crc*/
1367                 retval = rk32_edp_read_byte_from_dpcd(edp, 0x270, &buf);
1368                 buf |= 0x01;
1369                 retval = rk32_edp_write_bytes_to_dpcd(edp, 0x270, 1, &buf);
1370         }
1371
1372                 return 0;
1373 }
1374 static int psr_header_HB_PB(struct rk32_edp *edp)
1375 {
1376         u32 val;
1377
1378         val = 0x0;
1379         writel(val, edp->regs + HB0);/*HB0*/
1380         val = 0x07;
1381         writel(val, edp->regs + HB1);/*HB1*/
1382         val = 0x02;
1383         writel(val, edp->regs + HB2);/*HB2*/
1384         val = 0x08;
1385         writel(val, edp->regs + HB3);/*HB3*/
1386         val = 0x00;
1387         writel(val, edp->regs + PB0);/*PB0*/
1388         val = 0x16;
1389         writel(val, edp->regs + PB1);/*PB1*/
1390         val = 0xce;
1391         writel(val, edp->regs + PB2);/*PB2*/
1392         val = 0x5d;
1393         writel(val, edp->regs + PB3);/*PB3*/
1394
1395         return 0;
1396 }
1397
1398 static int psr_enable_sdp(struct rk32_edp *edp)
1399 {
1400         u32 val;
1401
1402         val = readl(edp->regs + SPDIF_AUDIO_CTL_0);
1403         val |= 0x08;
1404         writel(val, edp->regs + SPDIF_AUDIO_CTL_0);/*enable SDP*/
1405         val = readl(edp->regs + SPDIF_AUDIO_CTL_0);
1406         pr_info("PSR reuse_spd_en:%x\n", val);
1407
1408         val = 0x83;
1409         writel(val, edp->regs + IF_TYPE);/*enable IF_TYPE*/
1410         val = readl(edp->regs + IF_TYPE);
1411         pr_info("PSR IF_TYPE :%x\n", val);
1412
1413         val = readl(edp->regs + PKT_SEND_CTL);
1414         val |= 0x10;
1415         writel(val, edp->regs + PKT_SEND_CTL);/*enable IF_UP*/
1416         val = readl(edp->regs + PKT_SEND_CTL);
1417         pr_info("PSR if_up :%x\n", val);
1418
1419         val = readl(edp->regs + PKT_SEND_CTL);
1420         val |= 0x01;
1421         writel(val, edp->regs + PKT_SEND_CTL);/*enable IF_EN*/
1422         val = readl(edp->regs + PKT_SEND_CTL);
1423         pr_info("PSR if_en:%x\n", val);
1424         return 0;
1425 }
1426 static int edp_disable_psr(struct rk32_edp *edp)
1427 {
1428         u8 buf;
1429         int retval;
1430         char date;
1431
1432         /*disable sink PSR*/
1433         retval = rk32_edp_read_byte_from_dpcd(edp,
1434                                               PSR_ENABLE, &date);
1435         if (retval < 0) {
1436                 dev_err(edp->dev, "PSR sink original config Read failed!\n");
1437                 return retval;
1438         }
1439         buf = date&0xfe;
1440         retval = rk32_edp_write_bytes_to_dpcd
1441                                         (edp,
1442                                          PSR_ENABLE,
1443                                          1, &buf);
1444         if (retval < 0) {
1445                 dev_err(edp->dev, "PSR failed to disable sink PSR!\n");
1446                 return retval;
1447         }
1448
1449         pr_info("PSR disable success!!\n");
1450         return 0;
1451 }
1452
1453 static int edp_psr_state(struct rk32_edp *edp, int state)
1454 {
1455                 u32 val;
1456                 /*wait for VD blank*/
1457                 if  (rk_fb_poll_wait_frame_complete()) {
1458                         psr_header_HB_PB(edp);
1459
1460                         val = state;
1461                         writel(val, edp->regs + DB1);
1462                         /*val = readl(edp->regs + DB1);
1463                         pr_info("PSR set DB1 state 0x0:%x\n", val);
1464
1465                         for (i = 0; i < 22; i++)
1466                                  writel(0, edp->regs + DB2 + 4 * i);*/
1467
1468                         psr_enable_sdp(edp);
1469                 }
1470         return 0;
1471 }
1472
1473
1474 static int phy_power_channel(struct rk32_edp *edp, int state)
1475 {
1476         u32 val;
1477
1478         val = state;
1479         writel(val, edp->regs + DP_PD);
1480
1481         return 0;
1482 }
1483
1484 #if defined(CONFIG_DEBUG_FS)
1485
1486 static int edp_dpcd_debugfs_show(struct seq_file *s, void *v)
1487 {
1488         int retval;
1489         unsigned char buf[12];
1490         struct rk32_edp *edp = s->private;
1491
1492         if (!edp) {
1493                 dev_err(edp->dev, "no edp device!\n");
1494                 return -ENODEV;
1495         }
1496
1497         retval = rk32_edp_read_byte_from_dpcd
1498                         (edp,
1499                          PANEL_SELF_REFRESH_CAPABILITY_SUPPORTED_AND_VERSION,
1500                          &buf[0]);
1501         seq_printf(s, "0x70 %x\n", buf[0]);
1502
1503         /*PSR capabilities*/
1504         retval = rk32_edp_read_byte_from_dpcd
1505                         (edp,
1506                          PANEL_SELF_REFRESH_CAPABILITIES, &buf[0]);
1507         seq_printf(s, "0x71 %x\n", buf[0]);
1508
1509         retval = rk32_edp_read_byte_from_dpcd
1510                         (edp,
1511                          PSR_ENABLE, &buf[0]);
1512         seq_printf(s, "0x170 %x\n", buf[0]);
1513
1514         retval = rk32_edp_read_byte_from_dpcd(edp, 0x2006, &buf[0]);
1515         seq_printf(s, "0x2006 %x\n", buf[0]);
1516
1517         retval = rk32_edp_read_byte_from_dpcd(edp, 0x2007, &buf[0]);
1518         seq_printf(s, "0x2007 %x\n", buf[0]);
1519
1520         retval = rk32_edp_read_byte_from_dpcd(edp, 0x2008, &buf[0]);
1521         seq_printf(s, "0x2008 %x\n", buf[0]);
1522         retval = rk32_edp_read_byte_from_dpcd(edp, 0x2009, &buf[0]);
1523         seq_printf(s, "0x2009 %x\n", buf[0]);
1524
1525         retval = rk32_edp_read_byte_from_dpcd(edp, 0x200a, &buf[0]);
1526         seq_printf(s, "0x200a %x\n", buf[0]);
1527
1528         retval = rk32_edp_read_byte_from_dpcd(edp, 0x240, &buf[0]);
1529         seq_printf(s, "0x240 %x\n", buf[0]);
1530         retval = rk32_edp_read_byte_from_dpcd(edp, 0x241, &buf[0]);
1531         seq_printf(s, "0x241 %x\n", buf[0]);
1532         retval = rk32_edp_read_byte_from_dpcd(edp, 0x242, &buf[0]);
1533         seq_printf(s, "0x242 %x\n", buf[0]);
1534         retval = rk32_edp_read_byte_from_dpcd(edp, 0x243, &buf[0]);
1535         seq_printf(s, "0x243 %x\n", buf[0]);
1536         retval = rk32_edp_read_byte_from_dpcd(edp, 0x244, &buf[0]);
1537         seq_printf(s, "0x244 %x\n", buf[0]);
1538         retval = rk32_edp_read_byte_from_dpcd(edp, 0x245, &buf[0]);
1539         seq_printf(s, "0x245 %x\n", buf[0]);
1540         retval = rk32_edp_read_byte_from_dpcd(edp, 0x270, &buf[0]);
1541         seq_printf(s, "0x270 %x\n", buf[0]);
1542         retval = rk32_edp_read_byte_from_dpcd(edp, 0x246, &buf[0]);
1543         seq_printf(s, "0x246 %x\n", buf[0]);
1544
1545         /*retval = rk32_edp_read_byte_from_dpcd(edp, 0x222, &buf[0]);
1546         seq_printf(s, "0x222 %x\n", buf[0]);
1547         retval = rk32_edp_read_byte_from_dpcd(edp, 0x223, &buf[0]);
1548         seq_printf(s, "0x223 %x\n", buf[0]);
1549         retval = rk32_edp_read_byte_from_dpcd(edp, 0x224, &buf[0]);
1550         seq_printf(s, "0x224 %x\n", buf[0]);
1551         retval = rk32_edp_read_byte_from_dpcd(edp, 0x225, &buf[0]);
1552         seq_printf(s, "0x225 %x\n", buf[0]);
1553         retval = rk32_edp_read_byte_from_dpcd(edp, 0x226, &buf[0]);
1554         seq_printf(s, "0x226 %x\n", buf[0]);
1555         retval = rk32_edp_read_byte_from_dpcd(edp, 0x227, &buf[0]);
1556         seq_printf(s, "0x227 %x\n", buf[0]);
1557         retval = rk32_edp_read_byte_from_dpcd(edp, 0x228, &buf[0]);
1558         seq_printf(s, "0x228 %x\n", buf[0]);
1559         retval = rk32_edp_read_byte_from_dpcd(edp, 0x229, &buf[0]);
1560         seq_printf(s, "0x229 %x\n", buf[0]);
1561         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22a, &buf[0]);
1562         seq_printf(s, "0x22a %x\n", buf[0]);
1563         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22b, &buf[0]);
1564         seq_printf(s, "0x22b %x\n", buf[0]);
1565         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22c, &buf[0]);
1566         seq_printf(s, "0x22c %x\n", buf[0]);
1567         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22d, &buf[0]);
1568         seq_printf(s, "0x22d %x\n", buf[0]);
1569         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22e, &buf[0]);
1570         seq_printf(s, "0x22e %x\n", buf[0]);
1571         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22f, &buf[0]);
1572         seq_printf(s, "0x22f %x\n", buf[0]);
1573         retval = rk32_edp_read_byte_from_dpcd(edp, 0x230, &buf[0]);
1574         seq_printf(s, "0x230 %x\n", buf[0]);
1575         retval = rk32_edp_read_byte_from_dpcd(edp, 0x231, &buf[0]);
1576         seq_printf(s, "0x231 %x\n", buf[0]);*/
1577
1578         /*rk32_edp_read_bytes_from_dpcd(edp,
1579                         DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
1580         for (i = 0; i < 12; i++)
1581                 seq_printf(s, "0x%02x>>0x%02x\n", 0x210 + i, buf[i]);*/
1582         return 0;
1583 }
1584
1585 static ssize_t edp_dpcd_write(struct file *file,
1586                               const char __user *buf,
1587                               size_t count,
1588                               loff_t *ppos)
1589 {
1590         return count;
1591 }
1592
1593 static int edp_edid_debugfs_show(struct seq_file *s, void *v)
1594 {
1595         struct rk32_edp *edp = s->private;
1596
1597         if (!edp) {
1598                 dev_err(edp->dev, "no edp device!\n");
1599                 return -ENODEV;
1600         }
1601         rk32_edp_read_edid(edp);
1602         seq_puts(s, "edid");
1603         return 0;
1604 }
1605
1606 static ssize_t edp_edid_write(struct file *file,
1607                               const char __user *buf,
1608                               size_t count,
1609                               loff_t *ppos)
1610 {
1611         struct rk32_edp *edp =
1612                 ((struct seq_file *)file->private_data)->private;
1613
1614         if (!edp) {
1615                 dev_err(edp->dev, "no edp device!\n");
1616                 return -ENODEV;
1617         }
1618         rk32_edp_disable();
1619         rk32_edp_enable();
1620         return count;
1621 }
1622
1623 static int edp_reg_debugfs_show(struct seq_file *s, void *v)
1624 {
1625         int i = 0;
1626         struct rk32_edp *edp = s->private;
1627
1628         if (!edp) {
1629                 dev_err(edp->dev, "no edp device!\n");
1630                 return -ENODEV;
1631         }
1632
1633         for (i = 0; i < 0x284; i++) {
1634                 if (!(i%4))
1635                         seq_printf(s, "\n%08x:  ", i*4);
1636                 seq_printf(s, "%08x ", readl(edp->regs + i*4));
1637         }
1638         return 0;
1639 }
1640
1641 static ssize_t edp_reg_write(struct file *file,
1642                              const char __user *buf, size_t count,
1643                              loff_t *ppos)
1644 {
1645         return count;
1646 }
1647
1648 static int edp_psr_debugfs_show(struct seq_file *s, void *v)
1649 {
1650         return 0;
1651 }
1652 static ssize_t edp_psr_write(struct file *file,
1653                              const char __user *buf,
1654                              size_t count, loff_t *ppos)
1655 {
1656         int a;
1657         char kbuf[25];
1658         int retval;
1659         struct rk32_edp *edp =
1660                 ((struct seq_file *)file->private_data)->private;
1661
1662         if (!edp) {
1663                 dev_err(edp->dev, "no edp device!\n");
1664                 return -ENODEV;
1665         }
1666         memset(kbuf, 0, 25);
1667         if (copy_from_user(kbuf, buf, count))
1668                 return -EFAULT;
1669         retval = kstrtoint(kbuf, 0, &a);
1670         if (retval)
1671                 return retval;
1672         /*retval = sscanf(kbuf, "%d", &a);
1673         if (retval < 0) {
1674                 dev_err(edp->dev, "PSR failed sscanf!\n");
1675                 return retval;
1676         }*/
1677         /*disable psr*/
1678         if (0 == a)
1679                 edp_disable_psr(edp);
1680         /*enable psr*/
1681         if (1 == a)
1682                 rk32_edp_psr_enable(edp);
1683         /*inactive psr*/
1684         if (2 == a)
1685                 edp_psr_state(edp, 0x0);
1686         /*sink state 2*/
1687         if  (3 == a)
1688                 edp_psr_state(edp, 0x01);
1689         /*sink state 3*/
1690         if  (4 == a)
1691                 edp_psr_state(edp, 0x03);
1692         /*open 4 lanes*/
1693         if  (5 == a) {
1694                 phy_power_channel(edp, 0xff);
1695                 usleep_range(9, 10);
1696                 phy_power_channel(edp, 0x7f);
1697                 usleep_range(9, 10);
1698                 phy_power_channel(edp, 0x0);
1699         }
1700         /*close 4 lanes*/
1701         if (6 == a) {
1702                 phy_power_channel(edp, 0x7f);
1703                 usleep_range(9, 10);
1704                 phy_power_channel(edp, 0x0f);
1705         }
1706
1707         return count;
1708 }
1709
1710 #define EDP_DEBUG_ENTRY(name) \
1711 static int edp_##name##_debugfs_open(struct inode *inode, struct file *file) \
1712 { \
1713         return single_open(file, edp_##name##_debugfs_show, inode->i_private); \
1714 } \
1715 \
1716 static const struct file_operations edp_##name##_debugfs_fops = { \
1717         .owner = THIS_MODULE, \
1718         .open = edp_##name##_debugfs_open, \
1719         .read = seq_read, \
1720         .write = edp_##name##_write,    \
1721         .llseek = seq_lseek, \
1722         .release = single_release, \
1723 }
1724
1725 EDP_DEBUG_ENTRY(psr);
1726 EDP_DEBUG_ENTRY(dpcd);
1727 EDP_DEBUG_ENTRY(edid);
1728 EDP_DEBUG_ENTRY(reg);
1729 #endif
1730
1731 static int rk32_edp_probe(struct platform_device *pdev)
1732 {
1733         struct rk32_edp *edp;
1734         struct resource *res;
1735         struct device_node *np = pdev->dev.of_node;
1736         int ret;
1737
1738         if (!np) {
1739                 dev_err(&pdev->dev, "Missing device tree node.\n");
1740                 return -EINVAL;
1741         }
1742
1743         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1744         if (!edp) {
1745                 dev_err(&pdev->dev, "no memory for state\n");
1746                 return -ENOMEM;
1747         }
1748         edp->dev = &pdev->dev;
1749         edp->video_info.h_sync_polarity = 0;
1750         edp->video_info.v_sync_polarity = 0;
1751         edp->video_info.interlaced      = 0;
1752         edp->video_info.color_space     = CS_RGB;
1753         edp->video_info.dynamic_range   = VESA;
1754         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1755         edp->video_info.color_depth     = COLOR_8;
1756
1757         edp->video_info.link_rate       = LINK_RATE_1_62GBPS;
1758         edp->video_info.lane_count      = LANE_CNT4;
1759         rk_fb_get_prmry_screen(&edp->screen);
1760         if (edp->screen.type != SCREEN_EDP) {
1761                 dev_err(&pdev->dev, "screen is not edp!\n");
1762                 return -EINVAL;
1763         }
1764
1765         edp->soctype = (unsigned long)of_device_get_match_data(&pdev->dev);
1766
1767         platform_set_drvdata(pdev, edp);
1768         dev_set_name(edp->dev, "rk32-edp");
1769
1770         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1771         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1772         if (IS_ERR(edp->regs)) {
1773                 dev_err(&pdev->dev, "ioremap reg failed\n");
1774                 return PTR_ERR(edp->regs);
1775         }
1776
1777         edp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1778         if (IS_ERR(edp->grf) && !cpu_is_rk3288()) {
1779                 dev_err(&pdev->dev, "can't find rockchip,grf property\n");
1780                 return PTR_ERR(edp->grf);
1781         }
1782
1783         if (edp->soctype == SOC_RK3399) {
1784                 edp->grf_clk = devm_clk_get(&pdev->dev, "clk_grf");
1785                 if (IS_ERR(edp->grf_clk)) {
1786                         dev_err(&pdev->dev, "cannot get grf clk\n");
1787                         return PTR_ERR(edp->grf_clk);
1788                 }
1789         }
1790
1791         edp->pd = devm_clk_get(&pdev->dev, "pd_edp");
1792         if (IS_ERR(edp->pd)) {
1793                 dev_err(&pdev->dev, "cannot get pd\n");
1794                 edp->pd = NULL;
1795         }
1796
1797         edp->clk_edp = devm_clk_get(&pdev->dev, "clk_edp");
1798         if (IS_ERR(edp->clk_edp)) {
1799                 dev_err(&pdev->dev, "cannot get clk_edp\n");
1800                 return PTR_ERR(edp->clk_edp);
1801         }
1802
1803         if (edp->soctype != SOC_RK3399) {
1804                 edp->clk_24m = devm_clk_get(&pdev->dev, "clk_edp_24m");
1805                 if (IS_ERR(edp->clk_24m)) {
1806                         dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1807                         return PTR_ERR(edp->clk_24m);
1808                 }
1809         }
1810
1811         edp->pclk = devm_clk_get(&pdev->dev, "pclk_edp");
1812         if (IS_ERR(edp->pclk)) {
1813                 dev_err(&pdev->dev, "cannot get pclk\n");
1814                 return PTR_ERR(edp->pclk);
1815         }
1816
1817         /* We use the reset API to control the software reset at this version
1818          * and later, and we reserve the code that setting the cru regs directly
1819          * in the rk3288.
1820          */
1821         if (edp->soctype != SOC_RK3399) {
1822                 /*edp 24m need sorft reset*/
1823                 edp->rst_24m = devm_reset_control_get(&pdev->dev, "edp_24m");
1824                 if (IS_ERR(edp->rst_24m))
1825                         dev_err(&pdev->dev, "failed to get reset\n");
1826         }
1827
1828         /* edp ctrl apb bus need sorft reset */
1829         edp->rst_apb = devm_reset_control_get(&pdev->dev, "edp_apb");
1830         if (IS_ERR(edp->rst_apb))
1831                 dev_err(&pdev->dev, "failed to get reset\n");
1832         rk32_edp_clk_enable(edp);
1833         if (!support_uboot_display())
1834                 rk32_edp_pre_init(edp);
1835         edp->irq = platform_get_irq(pdev, 0);
1836         if (edp->irq < 0) {
1837                 dev_err(&pdev->dev, "cannot find IRQ\n");
1838                 return edp->irq;
1839         }
1840         ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1841                                dev_name(&pdev->dev), edp);
1842         if (ret) {
1843                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1844                 return ret;
1845         }
1846         disable_irq_nosync(edp->irq);
1847         if (!support_uboot_display())
1848                 rk32_edp_clk_disable(edp);
1849
1850         pm_runtime_enable(&pdev->dev);
1851         if (support_uboot_display()) {
1852                 edp->edp_en = true;
1853                 pm_runtime_get_sync(&pdev->dev);
1854         }
1855
1856         rk32_edp = edp;
1857         rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1858 #if defined(CONFIG_DEBUG_FS)
1859         edp->debugfs_dir = debugfs_create_dir("edp", NULL);
1860         if (IS_ERR(edp->debugfs_dir)) {
1861                 dev_err(edp->dev, "failed to create debugfs dir for edp!\n");
1862         } else {
1863                 debugfs_create_file("dpcd", S_IRUSR, edp->debugfs_dir,
1864                                     edp, &edp_dpcd_debugfs_fops);
1865                 debugfs_create_file("edid", S_IRUSR, edp->debugfs_dir,
1866                                     edp, &edp_edid_debugfs_fops);
1867                 debugfs_create_file("reg", S_IRUSR, edp->debugfs_dir,
1868                                     edp, &edp_reg_debugfs_fops);
1869                 debugfs_create_file("psr", S_IRUSR, edp->debugfs_dir,
1870                                     edp, &edp_psr_debugfs_fops);
1871         }
1872
1873 #endif
1874         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1875
1876         return 0;
1877 }
1878
1879 static int rockchip_edp_remove(struct platform_device *pdev)
1880 {
1881         pm_runtime_disable(&pdev->dev);
1882         return 0;
1883 }
1884
1885 #if defined(CONFIG_OF)
1886 static const struct of_device_id rk32_edp_dt_ids[] = {
1887         {.compatible = "rockchip,rk32-edp", .data = (void *)SOC_COMMON},
1888         {.compatible = "rockchip,rk3399-edp-fb", .data = (void *)SOC_RK3399},
1889         {}
1890 };
1891
1892 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1893 #endif
1894
1895 static struct platform_driver rk32_edp_driver = {
1896         .probe = rk32_edp_probe,
1897         .remove = rockchip_edp_remove,
1898         .driver = {
1899                    .name = "rk32-edp",
1900                    .owner = THIS_MODULE,
1901 #if defined(CONFIG_OF)
1902                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1903 #endif
1904         },
1905 };
1906
1907 static int __init rk32_edp_module_init(void)
1908 {
1909         return platform_driver_register(&rk32_edp_driver);
1910 }
1911
1912 static void __exit rk32_edp_module_exit(void)
1913 {
1914 }
1915
1916 fs_initcall(rk32_edp_module_init);
1917 module_exit(rk32_edp_module_exit);