2 * DisplayPort driver for rk32xx
4 * Copyright (C) ROCKCHIP, Inc.
5 *Author:yxj<yxj@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/rockchip/cpu.h>
24 #include <linux/rockchip/iomap.h>
25 #include <linux/rockchip/grf.h>
26 #include <linux/string.h>
27 #include <linux/slab.h>
28 #include <linux/uaccess.h>
30 #if defined(CONFIG_OF)
32 #include <linux/of_device.h>
35 #if defined(CONFIG_DEBUG_FS)
37 #include <linux/debugfs.h>
38 #include <linux/seq_file.h>
43 /*#define EDP_BIST_MODE*/
46 #define RK3368_GRF_SOC_CON4 0x410
47 #define RK3399_GRF_SOC_CON20 0x6250
49 static struct rk32_edp *rk32_edp;
51 static int rk32_edp_clk_enable(struct rk32_edp *edp)
57 clk_prepare_enable(edp->pd);
58 clk_prepare_enable(edp->pclk);
59 clk_prepare_enable(edp->clk_edp);
61 if (edp->soctype != SOC_RK3399) {
62 ret = clk_set_rate(edp->clk_24m, 24000000);
64 pr_err("cannot set edp clk_24m %d\n", ret);
65 clk_prepare_enable(edp->clk_24m);
73 static int rk32_edp_clk_disable(struct rk32_edp *edp)
76 clk_disable_unprepare(edp->pclk);
77 clk_disable_unprepare(edp->clk_edp);
79 if (edp->soctype != SOC_RK3399)
80 clk_disable_unprepare(edp->clk_24m);
83 clk_disable_unprepare(edp->pd);
90 static int rk32_edp_pre_init(struct rk32_edp *edp)
94 if (cpu_is_rk3288()) {
95 val = GRF_EDP_REF_CLK_SEL_INTER |
96 (GRF_EDP_REF_CLK_SEL_INTER << 16);
97 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
100 writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
104 writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
108 /* The rk3368 reset the edp 24M clock and apb bus
109 * according to the CRU_SOFTRST6_CON and CRU_SOFTRST7_CON.
111 if (edp->soctype != SOC_RK3399) {
112 val = 0x01 | (0x01 << 16);
113 regmap_write(edp->grf, RK3368_GRF_SOC_CON4, val);
115 reset_control_assert(edp->rst_24m);
116 usleep_range(10, 20);
117 reset_control_deassert(edp->rst_24m);
120 reset_control_assert(edp->rst_apb);
121 usleep_range(10, 20);
122 reset_control_deassert(edp->rst_apb);
127 static int rk32_edp_init_edp(struct rk32_edp *edp)
129 struct rk_screen *screen = &edp->screen;
132 rk_fb_get_prmry_screen(screen);
134 if (cpu_is_rk3288()) {
135 if (screen->lcdc_id == 1) /*select lcdc*/
136 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
138 val = EDP_SEL_VOP_LIT << 16;
139 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
142 if (edp->soctype == SOC_RK3399) {
143 if (screen->lcdc_id == 1) /*select lcdc*/
144 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
146 val = EDP_SEL_VOP_LIT << 16;
147 clk_prepare_enable(edp->grf_clk);
148 regmap_write(edp->grf, RK3399_GRF_SOC_CON20, val);
149 clk_disable_unprepare(edp->grf_clk);
153 rk32_edp_init_refclk(edp);
154 rk32_edp_init_interrupt(edp);
155 rk32_edp_enable_sw_function(edp);
156 rk32_edp_init_analog_func(edp);
157 rk32_edp_init_hpd(edp);
158 rk32_edp_init_aux(edp);
164 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
166 int timeout_loop = 0;
168 rk32_edp_init_hpd(edp);
172 while (rk32_edp_get_plug_in_status(edp) != 0) {
174 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
175 dev_err(edp->dev, "failed to get hpd plug status\n");
185 static int rk32_edp_read_edid(struct rk32_edp *edp)
187 unsigned char edid[EDID_LENGTH * 2];
188 unsigned int extend_block = 0;
190 unsigned char test_vector;
194 * EDID device address is 0x50.
195 * However, if necessary, you must have set upper address
196 * into E-EDID in I2C device, 0x30.
199 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
200 retval = rk32_edp_read_byte_from_i2c
202 EDID_ADDR, EDID_EXTENSION_FLAG, &extend_block);
204 dev_err(edp->dev, "EDID extension flag failed!\n");
208 if (extend_block > 0) {
209 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
212 retval = rk32_edp_read_bytes_from_i2c
214 EDID_ADDR, EDID_HEADER,
215 EDID_LENGTH, &edid[EDID_HEADER]);
217 dev_err(edp->dev, "EDID Read failed!\n");
220 sum = edp_calc_edid_check_sum(edid);
222 dev_warn(edp->dev, "EDID bad checksum!\n");
226 /* Read additional EDID data */
227 retval = rk32_edp_read_bytes_from_i2c
229 EDID_ADDR, EDID_LENGTH,
230 EDID_LENGTH, &edid[EDID_LENGTH]);
232 dev_err(edp->dev, "EDID Read failed!\n");
235 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
237 dev_warn(edp->dev, "EDID bad checksum!\n");
241 retval = rk32_edp_read_byte_from_dpcd
243 DPCD_TEST_REQUEST, &test_vector);
245 dev_err(edp->dev, "DPCD EDID Read failed!\n");
249 if (test_vector & DPCD_TEST_EDID_READ) {
250 retval = rk32_edp_write_byte_to_dpcd
252 DPCD_TEST_EDID_CHECKSUM,
253 edid[EDID_LENGTH + EDID_CHECKSUM]);
255 dev_err(edp->dev, "DPCD EDID Write failed!\n");
258 retval = rk32_edp_write_byte_to_dpcd
261 DPCD_TEST_EDID_CHECKSUM_WRITE);
263 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
268 dev_info(edp->dev, "EDID data does not include any extensions.\n");
271 retval = rk32_edp_read_bytes_from_i2c
273 EDID_ADDR, EDID_HEADER,
274 EDID_LENGTH, &edid[EDID_HEADER]);
276 dev_err(edp->dev, "EDID Read failed!\n");
279 sum = edp_calc_edid_check_sum(edid);
281 dev_warn(edp->dev, "EDID bad checksum!\n");
285 retval = rk32_edp_read_byte_from_dpcd
287 DPCD_TEST_REQUEST, &test_vector);
289 dev_err(edp->dev, "DPCD EDID Read failed!\n");
293 if (test_vector & DPCD_TEST_EDID_READ) {
294 retval = rk32_edp_write_byte_to_dpcd
296 DPCD_TEST_EDID_CHECKSUM,
297 edid[EDID_CHECKSUM]);
299 dev_err(edp->dev, "DPCD EDID Write failed!\n");
302 retval = rk32_edp_write_byte_to_dpcd
305 DPCD_TEST_EDID_CHECKSUM_WRITE);
307 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
312 fb_edid_to_monspecs(edid, &edp->specs);
313 dev_err(edp->dev, "EDID Read success!\n");
318 static int rk32_edp_handle_edid(struct rk32_edp *edp)
324 /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
325 retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
329 for (i = 0; i < 12; i++)
330 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
332 for (i = 0; i < 3; i++) {
333 retval = rk32_edp_read_edid(edp);
342 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
348 retval = rk32_edp_read_byte_from_dpcd
350 DPCD_LANE_CNT_SET, &data);
355 retval = rk32_edp_write_byte_to_dpcd
358 DPCD_ENHANCED_FRAME_EN |
359 DPCD_LANE_COUNT_SET(data));
361 /*retval = rk32_edp_write_byte_to_dpcd(edp,
362 DPCD_ADDR_CONFIGURATION_SET, 0);*/
364 retval = rk32_edp_write_byte_to_dpcd
367 DPCD_LANE_COUNT_SET(data));
373 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
375 /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
376 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
379 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
380 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
382 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
387 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
392 retval = rk32_edp_read_byte_from_dpcd
394 DPCD_MAX_LANE_CNT, &data);
398 return DPCD_ENHANCED_FRAME_CAP(data);
402 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
404 /*rk32_edp_write_byte_to_dpcd(edp,
405 DPCD_ADDR_USER_DEFINED1, 0);
406 rk32_edp_write_byte_to_dpcd(edp,
407 DPCD_ADDR_USER_DEFINED2, 0x83);
408 rk32_edp_write_byte_to_dpcd(edp,
409 DPCD_ADDR_USER_DEFINED3, 0x27);*/
412 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
417 retval = rk32_edp_is_enhanced_mode_available(edp);
422 retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
426 rk32_edp_enable_enhanced_mode(edp, data);
434 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
438 rk32_edp_set_training_pattern(edp, DP_NONE);
440 retval = rk32_edp_write_byte_to_dpcd(edp,
441 DPCD_TRAINING_PATTERN_SET,
442 DPCD_TRAINING_PATTERN_DISABLED);
449 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
450 int pre_emphasis, int lane)
454 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
457 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
461 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
465 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
470 static int rk32_edp_link_start(struct rk32_edp *edp)
477 lane_count = edp->link_train.lane_count;
479 edp->link_train.lt_state = LT_CLK_RECOVERY;
480 edp->link_train.eq_loop = 0;
482 for (lane = 0; lane < lane_count; lane++)
483 edp->link_train.cr_loop[lane] = 0;
485 /* Set sink to D0 (Sink Not Ready) mode. */
486 retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
487 DPCD_SET_POWER_STATE_D0);
489 dev_err(edp->dev, "failed to set sink device to D0!\n");
493 /* Set link rate and count as you want to establish*/
494 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
495 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
497 /* Setup RX configuration */
498 buf[0] = edp->link_train.link_rate;
499 buf[1] = edp->link_train.lane_count;
500 retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
503 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
507 /* Set TX pre-emphasis to level1 */
508 for (lane = 0; lane < lane_count; lane++)
509 rk32_edp_set_lane_lane_pre_emphasis
511 PRE_EMPHASIS_LEVEL_1, lane);
513 /* Set training pattern 1 */
514 rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
516 /* Set RX training pattern */
517 retval = rk32_edp_write_byte_to_dpcd(edp,
518 DPCD_TRAINING_PATTERN_SET,
519 DPCD_SCRAMBLING_DISABLED |
520 DPCD_TRAINING_PATTERN_1);
522 dev_err(edp->dev, "failed to set training pattern 1!\n");
526 for (lane = 0; lane < lane_count; lane++)
527 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
528 DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
529 retval = rk32_edp_write_bytes_to_dpcd(edp,
530 DPCD_TRAINING_LANE0_SET,
533 dev_err(edp->dev, "failed to set training lane!\n");
540 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
542 int shift = (lane & 1) * 4;
543 u8 link_value = link_status[lane>>1];
545 return (link_value >> shift) & 0xf;
548 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
553 for (lane = 0; lane < lane_count; lane++) {
554 lane_status = rk32_edp_get_lane_status(link_status, lane);
555 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
561 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
567 lane_align = link_align[2];
568 if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
571 for (lane = 0; lane < lane_count; lane++) {
572 lane_status = rk32_edp_get_lane_status(link_align, lane);
573 lane_status &= DPCD_CHANNEL_EQ_BITS;
574 if (lane_status != DPCD_CHANNEL_EQ_BITS)
581 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
584 int shift = (lane & 1) * 4;
585 u8 link_value = adjust_request[lane>>1];
587 return (link_value >> shift) & 0x3;
590 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
591 u8 adjust_request[2],
594 int shift = (lane & 1) * 4;
595 u8 link_value = adjust_request[lane>>1];
597 return ((link_value >> shift) & 0xc) >> 2;
600 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
601 u8 training_lane_set, int lane)
605 rk32_edp_set_lane0_link_training(edp, training_lane_set);
608 rk32_edp_set_lane1_link_training(edp, training_lane_set);
612 rk32_edp_set_lane2_link_training(edp, training_lane_set);
616 rk32_edp_set_lane3_link_training(edp, training_lane_set);
621 static unsigned int rk32_edp_get_lane_link_training(
622 struct rk32_edp *edp,
629 reg = rk32_edp_get_lane0_link_training(edp);
632 reg = rk32_edp_get_lane1_link_training(edp);
635 reg = rk32_edp_get_lane2_link_training(edp);
638 reg = rk32_edp_get_lane3_link_training(edp);
645 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
647 rk32_edp_training_pattern_dis(edp);
649 edp->link_train.lt_state = FAILED;
652 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
658 u8 adjust_request[2];
665 usleep_range(99, 100);
667 lane_count = edp->link_train.lane_count;
669 retval = rk32_edp_read_bytes_from_dpcd(edp,
673 dev_err(edp->dev, "failed to read lane status!\n");
677 if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
678 /* set training pattern 2 for EQ */
679 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
681 for (lane = 0; lane < lane_count; lane++) {
682 retval = rk32_edp_read_bytes_from_dpcd
684 DPCD_ADJUST_REQUEST_LANE0_1,
687 dev_err(edp->dev, "failed to read adjust request!\n");
691 voltage_swing = rk32_edp_get_adjust_request_voltage(
692 adjust_request, lane);
693 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
694 adjust_request, lane);
695 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
696 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
698 if (voltage_swing == VOLTAGE_LEVEL_3)
699 training_lane |= DPCD_MAX_SWING_REACHED;
700 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
701 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
703 edp->link_train.training_lane[lane] = training_lane;
705 rk32_edp_set_lane_link_training
707 edp->link_train.training_lane[lane],
711 retval = rk32_edp_write_byte_to_dpcd(edp,
712 DPCD_TRAINING_PATTERN_SET,
713 DPCD_SCRAMBLING_DISABLED |
714 DPCD_TRAINING_PATTERN_2);
716 dev_err(edp->dev, "failed to set training pattern 2!\n");
720 retval = rk32_edp_write_bytes_to_dpcd(edp,
721 DPCD_TRAINING_LANE0_SET,
723 edp->link_train.training_lane);
725 dev_err(edp->dev, "failed to set training lane!\n");
729 dev_info(edp->dev, "Link Training Clock Recovery success\n");
730 edp->link_train.lt_state = LT_EQ_TRAINING;
732 for (lane = 0; lane < lane_count; lane++) {
733 training_lane = rk32_edp_get_lane_link_training(
735 retval = rk32_edp_read_bytes_from_dpcd
737 DPCD_ADJUST_REQUEST_LANE0_1,
740 dev_err(edp->dev, "failed to read adjust request!\n");
744 voltage_swing = rk32_edp_get_adjust_request_voltage(
745 adjust_request, lane);
746 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
747 adjust_request, lane);
749 if (voltage_swing == VOLTAGE_LEVEL_3 ||
750 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
751 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
752 goto reduce_link_rate;
755 if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
757 (DPCD_PRE_EMPHASIS_GET(training_lane) ==
759 edp->link_train.cr_loop[lane]++;
760 if (edp->link_train.cr_loop[lane] ==
762 dev_err(edp->dev, "CR Max loop\n");
763 goto reduce_link_rate;
767 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
768 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
770 if (voltage_swing == VOLTAGE_LEVEL_3)
771 training_lane |= DPCD_MAX_SWING_REACHED;
772 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
773 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
775 edp->link_train.training_lane[lane] = training_lane;
777 rk32_edp_set_lane_link_training
779 edp->link_train.training_lane[lane], lane);
782 retval = rk32_edp_write_bytes_to_dpcd
784 DPCD_TRAINING_LANE0_SET,
786 edp->link_train.training_lane);
788 dev_err(edp->dev, "failed to set training lane!\n");
796 rk32_edp_reduce_link_rate(edp);
800 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
808 u8 adjust_request[2];
815 usleep_range(399, 400);
817 lane_count = edp->link_train.lane_count;
819 retval = rk32_edp_read_bytes_from_dpcd(edp,
823 dev_err(edp->dev, "failed to read lane status!\n");
827 if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
828 link_align[0] = link_status[0];
829 link_align[1] = link_status[1];
831 retval = rk32_edp_read_byte_from_dpcd
833 DPCD_LANE_ALIGN_STATUS_UPDATED,
836 dev_err(edp->dev, "failed to read lane aligne status!\n");
840 for (lane = 0; lane < lane_count; lane++) {
841 retval = rk32_edp_read_bytes_from_dpcd
843 DPCD_ADJUST_REQUEST_LANE0_1,
846 dev_err(edp->dev, "failed to read adjust request!\n");
850 voltage_swing = rk32_edp_get_adjust_request_voltage(
851 adjust_request, lane);
852 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
853 adjust_request, lane);
854 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
855 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
857 if (voltage_swing == VOLTAGE_LEVEL_3)
858 training_lane |= DPCD_MAX_SWING_REACHED;
859 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
860 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
862 edp->link_train.training_lane[lane] = training_lane;
865 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
866 /* traing pattern Set to Normal */
867 retval = rk32_edp_training_pattern_dis(edp);
869 dev_err(edp->dev, "failed to disable training pattern!\n");
873 dev_info(edp->dev, "Link Training success!\n");
875 rk32_edp_get_link_bandwidth(edp, ®);
876 edp->link_train.link_rate = reg;
877 dev_dbg(edp->dev, "final bandwidth = %.2x\n",
878 edp->link_train.link_rate);
880 rk32_edp_get_lane_count(edp, ®);
881 edp->link_train.lane_count = reg;
882 dev_dbg(edp->dev, "final lane count = %.2x\n",
883 edp->link_train.lane_count);
885 edp->link_train.lt_state = FINISHED;
888 edp->link_train.eq_loop++;
890 if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
891 dev_err(edp->dev, "EQ Max loop\n");
892 goto reduce_link_rate;
895 for (lane = 0; lane < lane_count; lane++)
896 rk32_edp_set_lane_link_training
898 edp->link_train.training_lane[lane],
901 retval = rk32_edp_write_bytes_to_dpcd
903 DPCD_TRAINING_LANE0_SET,
905 edp->link_train.training_lane);
907 dev_err(edp->dev, "failed to set training lane!\n");
912 goto reduce_link_rate;
918 rk32_edp_reduce_link_rate(edp);
922 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
929 * For DP rev.1.1, Maximum link rate of Main Link lanes
930 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
932 retval = rk32_edp_read_byte_from_dpcd(edp,
933 DPCD_MAX_LINK_RATE, &data);
941 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
948 * For DP rev.1.1, Maximum number of Main Link lanes
949 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
951 retval = rk32_edp_read_byte_from_dpcd(edp,
952 DPCD_MAX_LANE_CNT, &data);
956 *lane_count = DPCD_MAX_LANE_COUNT(data);
960 static int rk32_edp_init_training(struct rk32_edp *edp)
965 * MACRO_RST must be applied after the PLL_LOCK to avoid
966 * the DP inter pair skew issue for at least 10 us
968 rk32_edp_reset_macro(edp);
971 retval = rk32_edp_get_max_rx_bandwidth(edp,
972 &edp->link_train.link_rate);
973 retval = rk32_edp_get_max_rx_lane_count(edp,
974 &edp->link_train.lane_count);
975 dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
976 edp->link_train.link_rate * 27/100,
977 edp->link_train.link_rate*27%100,
978 edp->link_train.lane_count);
980 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
981 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
984 "Rx Mx Link Rate is abnormal:%x!default link rate:%d.%dGps\n",
985 edp->link_train.link_rate,
986 edp->video_info.link_rate*27/100,
987 edp->video_info.link_rate*27%100);
988 edp->link_train.link_rate = edp->video_info.link_rate;
991 if (edp->link_train.lane_count == 0) {
994 "Rx Max Lane count is abnormal :%x !use default lanes:%d\n",
995 edp->link_train.lane_count,
996 edp->video_info.lane_count);
997 edp->link_train.lane_count = edp->video_info.lane_count;
1000 rk32_edp_analog_power_ctr(edp, 1);
1007 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
1010 int training_finished = 0;
1012 edp->link_train.lt_state = LT_START;
1015 while (!training_finished) {
1016 switch (edp->link_train.lt_state) {
1018 retval = rk32_edp_link_start(edp);
1020 dev_err(edp->dev, "LT Start failed\n");
1022 case LT_CLK_RECOVERY:
1023 retval = rk32_edp_process_clock_recovery(edp);
1025 dev_err(edp->dev, "LT CR failed\n");
1027 case LT_EQ_TRAINING:
1028 retval = rk32_edp_process_equalizer_training(edp);
1030 dev_err(edp->dev, "LT EQ failed\n");
1033 training_finished = 1;
1044 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
1048 /* Set link rate and count as you want to establish*/
1049 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1050 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1051 rk32_edp_hw_link_training_en(edp);
1052 val = rk32_edp_wait_hw_lt_done(edp);
1055 dev_err(edp->dev, "hw lt timeout");
1059 val = rk32_edp_wait_hw_lt_done(edp);
1062 val = rk32_edp_get_hw_lt_status(edp);
1064 dev_err(edp->dev, "hw lt err:%d\n", val);
1069 static int rk32_edp_set_link_train(struct rk32_edp *edp)
1073 retval = rk32_edp_init_training(edp);
1075 dev_err(edp->dev, "DP LT init failed!\n");
1077 retval = rk32_edp_sw_link_training(edp);
1079 retval = rk32_edp_hw_link_training(edp);
1085 static int rk32_edp_config_video(struct rk32_edp *edp,
1086 struct video_info *video_info)
1089 int timeout_loop = 0;
1092 rk32_edp_config_video_slave_mode(edp, video_info);
1094 rk32_edp_set_video_color_format(edp, video_info->color_depth,
1095 video_info->color_space,
1096 video_info->dynamic_range,
1097 video_info->ycbcr_coeff);
1099 if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
1100 dev_err(edp->dev, "PLL is not locked yet.\n");
1106 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
1108 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1109 dev_err(edp->dev, "Timeout of video streamclk ok\n");
1116 /* Set to use the register calculated M/N video */
1117 rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1119 /* For video bist, Video timing must be generated by register */
1120 #ifndef EDP_BIST_MODE
1121 rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
1123 /* Disable video mute */
1124 rk32_edp_enable_video_mute(edp, 0);
1126 /* Configure video slave mode */
1127 rk32_edp_enable_video_master(edp, 0);
1130 rk32_edp_start_video(edp);
1136 if (rk32_edp_is_video_stream_on(edp) == 0) {
1138 if (done_count > 10)
1140 } else if (done_count) {
1143 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1144 dev_err(edp->dev, "Timeout of video streamclk ok\n");
1152 dev_err(edp->dev, "Video stream is not detected!\n");
1157 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1159 struct rk32_edp *edp = arg;
1160 enum dp_irq_type irq_type;
1162 irq_type = rk32_edp_get_irq_type(edp);
1164 case DP_IRQ_TYPE_HP_CABLE_IN:
1165 dev_info(edp->dev, "Received irq - cable in\n");
1166 rk32_edp_clear_hotplug_interrupts(edp);
1168 case DP_IRQ_TYPE_HP_CABLE_OUT:
1169 dev_info(edp->dev, "Received irq - cable out\n");
1170 rk32_edp_clear_hotplug_interrupts(edp);
1172 case DP_IRQ_TYPE_HP_CHANGE:
1174 * We get these change notifications once in a while, but there
1175 * is nothing we can do with them. Just ignore it for now and
1176 * only handle cable changes.
1178 dev_info(edp->dev, "Received irq - hotplug change; ignoring.\n");
1179 rk32_edp_clear_hotplug_interrupts(edp);
1182 dev_err(edp->dev, "Received irq - unknown type!\n");
1188 static int rk32_edp_enable(void)
1191 struct rk32_edp *edp = rk32_edp;
1194 rk32_edp_clk_enable(edp);
1195 pm_runtime_get_sync(edp->dev);
1196 rk32_edp_pre_init(edp);
1197 rk32_edp_init_edp(edp);
1198 enable_irq(edp->irq);
1199 /*ret = rk32_edp_handle_edid(edp);
1201 dev_err(edp->dev, "unable to handle edid\n");
1205 ret = rk32_edp_enable_scramble(edp, 0);
1207 dev_err(edp->dev, "unable to set scramble\n");
1211 ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1213 dev_err(edp->dev, "unable to set enhanced mode\n");
1216 rk32_edp_enable_enhanced_mode(edp, 1);*/
1218 ret = rk32_edp_set_link_train(edp);
1220 dev_err(edp->dev, "link train failed!\n");
1222 dev_info(edp->dev, "link training success.\n");
1224 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1225 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1226 rk32_edp_init_video(edp);
1228 #ifdef EDP_BIST_MODE
1229 rk32_edp_bist_cfg(edp);
1231 ret = rk32_edp_config_video(edp, &edp->video_info);
1233 dev_err(edp->dev, "unable to config video\n");
1240 static int rk32_edp_disable(void)
1242 struct rk32_edp *edp = rk32_edp;
1245 edp->edp_en = false;
1246 disable_irq(edp->irq);
1247 rk32_edp_reset(edp);
1248 rk32_edp_analog_power_ctr(edp, 0);
1249 rk32_edp_clk_disable(edp);
1250 pm_runtime_put_sync(edp->dev);
1257 static struct rk_fb_trsm_ops trsm_edp_ops = {
1258 .enable = rk32_edp_enable,
1259 .disable = rk32_edp_disable,
1263 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1269 rk32_edp_enable_scrambling(edp);
1271 retval = rk32_edp_read_byte_from_dpcd
1273 DPCD_TRAINING_PATTERN_SET,
1278 retval = rk32_edp_write_byte_to_dpcd
1280 DPCD_TRAINING_PATTERN_SET,
1281 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1285 rk32_edp_disable_scrambling(edp);
1287 retval = rk32_edp_read_byte_from_dpcd
1289 DPCD_TRAINING_PATTERN_SET,
1294 retval = rk32_edp_write_byte_to_dpcd
1296 DPCD_TRAINING_PATTERN_SET,
1297 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1305 static int rk32_edp_psr_enable(struct rk32_edp *edp)
1309 char date, psr_version;
1312 retval = rk32_edp_read_byte_from_dpcd
1314 PANEL_SELF_REFRESH_CAPABILITY_SUPPORTED_AND_VERSION,
1317 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1320 pr_info("PSR supporter and version:%x\n", psr_version);
1323 /*PSR capabilities*/
1324 retval = rk32_edp_read_byte_from_dpcd
1326 PANEL_SELF_REFRESH_CAPABILITIES, &date);
1328 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1331 pr_info("PSR capabilities:%x\n", date);
1334 if (psr_version & PSR_SUPPORT) {
1335 pr_info("PSR config psr\n");
1339 retval = rk32_edp_write_bytes_to_dpcd(edp, PSR_ENABLE,
1342 dev_err(edp->dev, "PSR failed to config sink PSR!\n");
1347 retval = rk32_edp_write_bytes_to_dpcd(edp,
1351 dev_err(edp->dev, "PSR failed to enable the PSR!\n");
1354 /*read sink config state*/
1355 retval = rk32_edp_read_byte_from_dpcd
1359 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1362 pr_info("PSR sink config state:%x\n", date);
1367 retval = rk32_edp_read_byte_from_dpcd(edp, 0x270, &buf);
1369 retval = rk32_edp_write_bytes_to_dpcd(edp, 0x270, 1, &buf);
1374 static int psr_header_HB_PB(struct rk32_edp *edp)
1379 writel(val, edp->regs + HB0);/*HB0*/
1381 writel(val, edp->regs + HB1);/*HB1*/
1383 writel(val, edp->regs + HB2);/*HB2*/
1385 writel(val, edp->regs + HB3);/*HB3*/
1387 writel(val, edp->regs + PB0);/*PB0*/
1389 writel(val, edp->regs + PB1);/*PB1*/
1391 writel(val, edp->regs + PB2);/*PB2*/
1393 writel(val, edp->regs + PB3);/*PB3*/
1398 static int psr_enable_sdp(struct rk32_edp *edp)
1402 val = readl(edp->regs + SPDIF_AUDIO_CTL_0);
1404 writel(val, edp->regs + SPDIF_AUDIO_CTL_0);/*enable SDP*/
1405 val = readl(edp->regs + SPDIF_AUDIO_CTL_0);
1406 pr_info("PSR reuse_spd_en:%x\n", val);
1409 writel(val, edp->regs + IF_TYPE);/*enable IF_TYPE*/
1410 val = readl(edp->regs + IF_TYPE);
1411 pr_info("PSR IF_TYPE :%x\n", val);
1413 val = readl(edp->regs + PKT_SEND_CTL);
1415 writel(val, edp->regs + PKT_SEND_CTL);/*enable IF_UP*/
1416 val = readl(edp->regs + PKT_SEND_CTL);
1417 pr_info("PSR if_up :%x\n", val);
1419 val = readl(edp->regs + PKT_SEND_CTL);
1421 writel(val, edp->regs + PKT_SEND_CTL);/*enable IF_EN*/
1422 val = readl(edp->regs + PKT_SEND_CTL);
1423 pr_info("PSR if_en:%x\n", val);
1426 static int edp_disable_psr(struct rk32_edp *edp)
1432 /*disable sink PSR*/
1433 retval = rk32_edp_read_byte_from_dpcd(edp,
1436 dev_err(edp->dev, "PSR sink original config Read failed!\n");
1440 retval = rk32_edp_write_bytes_to_dpcd
1445 dev_err(edp->dev, "PSR failed to disable sink PSR!\n");
1449 pr_info("PSR disable success!!\n");
1453 static int edp_psr_state(struct rk32_edp *edp, int state)
1456 /*wait for VD blank*/
1457 if (rk_fb_poll_wait_frame_complete()) {
1458 psr_header_HB_PB(edp);
1461 writel(val, edp->regs + DB1);
1462 /*val = readl(edp->regs + DB1);
1463 pr_info("PSR set DB1 state 0x0:%x\n", val);
1465 for (i = 0; i < 22; i++)
1466 writel(0, edp->regs + DB2 + 4 * i);*/
1468 psr_enable_sdp(edp);
1474 static int phy_power_channel(struct rk32_edp *edp, int state)
1479 writel(val, edp->regs + DP_PD);
1484 #if defined(CONFIG_DEBUG_FS)
1486 static int edp_dpcd_debugfs_show(struct seq_file *s, void *v)
1489 unsigned char buf[12];
1490 struct rk32_edp *edp = s->private;
1493 dev_err(edp->dev, "no edp device!\n");
1497 retval = rk32_edp_read_byte_from_dpcd
1499 PANEL_SELF_REFRESH_CAPABILITY_SUPPORTED_AND_VERSION,
1501 seq_printf(s, "0x70 %x\n", buf[0]);
1503 /*PSR capabilities*/
1504 retval = rk32_edp_read_byte_from_dpcd
1506 PANEL_SELF_REFRESH_CAPABILITIES, &buf[0]);
1507 seq_printf(s, "0x71 %x\n", buf[0]);
1509 retval = rk32_edp_read_byte_from_dpcd
1511 PSR_ENABLE, &buf[0]);
1512 seq_printf(s, "0x170 %x\n", buf[0]);
1514 retval = rk32_edp_read_byte_from_dpcd(edp, 0x2006, &buf[0]);
1515 seq_printf(s, "0x2006 %x\n", buf[0]);
1517 retval = rk32_edp_read_byte_from_dpcd(edp, 0x2007, &buf[0]);
1518 seq_printf(s, "0x2007 %x\n", buf[0]);
1520 retval = rk32_edp_read_byte_from_dpcd(edp, 0x2008, &buf[0]);
1521 seq_printf(s, "0x2008 %x\n", buf[0]);
1522 retval = rk32_edp_read_byte_from_dpcd(edp, 0x2009, &buf[0]);
1523 seq_printf(s, "0x2009 %x\n", buf[0]);
1525 retval = rk32_edp_read_byte_from_dpcd(edp, 0x200a, &buf[0]);
1526 seq_printf(s, "0x200a %x\n", buf[0]);
1528 retval = rk32_edp_read_byte_from_dpcd(edp, 0x240, &buf[0]);
1529 seq_printf(s, "0x240 %x\n", buf[0]);
1530 retval = rk32_edp_read_byte_from_dpcd(edp, 0x241, &buf[0]);
1531 seq_printf(s, "0x241 %x\n", buf[0]);
1532 retval = rk32_edp_read_byte_from_dpcd(edp, 0x242, &buf[0]);
1533 seq_printf(s, "0x242 %x\n", buf[0]);
1534 retval = rk32_edp_read_byte_from_dpcd(edp, 0x243, &buf[0]);
1535 seq_printf(s, "0x243 %x\n", buf[0]);
1536 retval = rk32_edp_read_byte_from_dpcd(edp, 0x244, &buf[0]);
1537 seq_printf(s, "0x244 %x\n", buf[0]);
1538 retval = rk32_edp_read_byte_from_dpcd(edp, 0x245, &buf[0]);
1539 seq_printf(s, "0x245 %x\n", buf[0]);
1540 retval = rk32_edp_read_byte_from_dpcd(edp, 0x270, &buf[0]);
1541 seq_printf(s, "0x270 %x\n", buf[0]);
1542 retval = rk32_edp_read_byte_from_dpcd(edp, 0x246, &buf[0]);
1543 seq_printf(s, "0x246 %x\n", buf[0]);
1545 /*retval = rk32_edp_read_byte_from_dpcd(edp, 0x222, &buf[0]);
1546 seq_printf(s, "0x222 %x\n", buf[0]);
1547 retval = rk32_edp_read_byte_from_dpcd(edp, 0x223, &buf[0]);
1548 seq_printf(s, "0x223 %x\n", buf[0]);
1549 retval = rk32_edp_read_byte_from_dpcd(edp, 0x224, &buf[0]);
1550 seq_printf(s, "0x224 %x\n", buf[0]);
1551 retval = rk32_edp_read_byte_from_dpcd(edp, 0x225, &buf[0]);
1552 seq_printf(s, "0x225 %x\n", buf[0]);
1553 retval = rk32_edp_read_byte_from_dpcd(edp, 0x226, &buf[0]);
1554 seq_printf(s, "0x226 %x\n", buf[0]);
1555 retval = rk32_edp_read_byte_from_dpcd(edp, 0x227, &buf[0]);
1556 seq_printf(s, "0x227 %x\n", buf[0]);
1557 retval = rk32_edp_read_byte_from_dpcd(edp, 0x228, &buf[0]);
1558 seq_printf(s, "0x228 %x\n", buf[0]);
1559 retval = rk32_edp_read_byte_from_dpcd(edp, 0x229, &buf[0]);
1560 seq_printf(s, "0x229 %x\n", buf[0]);
1561 retval = rk32_edp_read_byte_from_dpcd(edp, 0x22a, &buf[0]);
1562 seq_printf(s, "0x22a %x\n", buf[0]);
1563 retval = rk32_edp_read_byte_from_dpcd(edp, 0x22b, &buf[0]);
1564 seq_printf(s, "0x22b %x\n", buf[0]);
1565 retval = rk32_edp_read_byte_from_dpcd(edp, 0x22c, &buf[0]);
1566 seq_printf(s, "0x22c %x\n", buf[0]);
1567 retval = rk32_edp_read_byte_from_dpcd(edp, 0x22d, &buf[0]);
1568 seq_printf(s, "0x22d %x\n", buf[0]);
1569 retval = rk32_edp_read_byte_from_dpcd(edp, 0x22e, &buf[0]);
1570 seq_printf(s, "0x22e %x\n", buf[0]);
1571 retval = rk32_edp_read_byte_from_dpcd(edp, 0x22f, &buf[0]);
1572 seq_printf(s, "0x22f %x\n", buf[0]);
1573 retval = rk32_edp_read_byte_from_dpcd(edp, 0x230, &buf[0]);
1574 seq_printf(s, "0x230 %x\n", buf[0]);
1575 retval = rk32_edp_read_byte_from_dpcd(edp, 0x231, &buf[0]);
1576 seq_printf(s, "0x231 %x\n", buf[0]);*/
1578 /*rk32_edp_read_bytes_from_dpcd(edp,
1579 DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
1580 for (i = 0; i < 12; i++)
1581 seq_printf(s, "0x%02x>>0x%02x\n", 0x210 + i, buf[i]);*/
1585 static ssize_t edp_dpcd_write(struct file *file,
1586 const char __user *buf,
1593 static int edp_edid_debugfs_show(struct seq_file *s, void *v)
1595 struct rk32_edp *edp = s->private;
1598 dev_err(edp->dev, "no edp device!\n");
1601 rk32_edp_read_edid(edp);
1602 seq_puts(s, "edid");
1606 static ssize_t edp_edid_write(struct file *file,
1607 const char __user *buf,
1611 struct rk32_edp *edp =
1612 ((struct seq_file *)file->private_data)->private;
1615 dev_err(edp->dev, "no edp device!\n");
1623 static int edp_reg_debugfs_show(struct seq_file *s, void *v)
1626 struct rk32_edp *edp = s->private;
1629 dev_err(edp->dev, "no edp device!\n");
1633 for (i = 0; i < 0x284; i++) {
1635 seq_printf(s, "\n%08x: ", i*4);
1636 seq_printf(s, "%08x ", readl(edp->regs + i*4));
1641 static ssize_t edp_reg_write(struct file *file,
1642 const char __user *buf, size_t count,
1648 static int edp_psr_debugfs_show(struct seq_file *s, void *v)
1652 static ssize_t edp_psr_write(struct file *file,
1653 const char __user *buf,
1654 size_t count, loff_t *ppos)
1659 struct rk32_edp *edp =
1660 ((struct seq_file *)file->private_data)->private;
1663 dev_err(edp->dev, "no edp device!\n");
1666 memset(kbuf, 0, 25);
1667 if (copy_from_user(kbuf, buf, count))
1669 retval = kstrtoint(kbuf, 0, &a);
1672 /*retval = sscanf(kbuf, "%d", &a);
1674 dev_err(edp->dev, "PSR failed sscanf!\n");
1679 edp_disable_psr(edp);
1682 rk32_edp_psr_enable(edp);
1685 edp_psr_state(edp, 0x0);
1688 edp_psr_state(edp, 0x01);
1691 edp_psr_state(edp, 0x03);
1694 phy_power_channel(edp, 0xff);
1695 usleep_range(9, 10);
1696 phy_power_channel(edp, 0x7f);
1697 usleep_range(9, 10);
1698 phy_power_channel(edp, 0x0);
1702 phy_power_channel(edp, 0x7f);
1703 usleep_range(9, 10);
1704 phy_power_channel(edp, 0x0f);
1710 #define EDP_DEBUG_ENTRY(name) \
1711 static int edp_##name##_debugfs_open(struct inode *inode, struct file *file) \
1713 return single_open(file, edp_##name##_debugfs_show, inode->i_private); \
1716 static const struct file_operations edp_##name##_debugfs_fops = { \
1717 .owner = THIS_MODULE, \
1718 .open = edp_##name##_debugfs_open, \
1720 .write = edp_##name##_write, \
1721 .llseek = seq_lseek, \
1722 .release = single_release, \
1725 EDP_DEBUG_ENTRY(psr);
1726 EDP_DEBUG_ENTRY(dpcd);
1727 EDP_DEBUG_ENTRY(edid);
1728 EDP_DEBUG_ENTRY(reg);
1731 static int rk32_edp_probe(struct platform_device *pdev)
1733 struct rk32_edp *edp;
1734 struct resource *res;
1735 struct device_node *np = pdev->dev.of_node;
1739 dev_err(&pdev->dev, "Missing device tree node.\n");
1743 edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1745 dev_err(&pdev->dev, "no memory for state\n");
1748 edp->dev = &pdev->dev;
1749 edp->video_info.h_sync_polarity = 0;
1750 edp->video_info.v_sync_polarity = 0;
1751 edp->video_info.interlaced = 0;
1752 edp->video_info.color_space = CS_RGB;
1753 edp->video_info.dynamic_range = VESA;
1754 edp->video_info.ycbcr_coeff = COLOR_YCBCR601;
1755 edp->video_info.color_depth = COLOR_8;
1757 edp->video_info.link_rate = LINK_RATE_1_62GBPS;
1758 edp->video_info.lane_count = LANE_CNT4;
1759 rk_fb_get_prmry_screen(&edp->screen);
1760 if (edp->screen.type != SCREEN_EDP) {
1761 dev_err(&pdev->dev, "screen is not edp!\n");
1765 edp->soctype = (unsigned long)of_device_get_match_data(&pdev->dev);
1767 platform_set_drvdata(pdev, edp);
1768 dev_set_name(edp->dev, "rk32-edp");
1770 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1771 edp->regs = devm_ioremap_resource(&pdev->dev, res);
1772 if (IS_ERR(edp->regs)) {
1773 dev_err(&pdev->dev, "ioremap reg failed\n");
1774 return PTR_ERR(edp->regs);
1777 edp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1778 if (IS_ERR(edp->grf) && !cpu_is_rk3288()) {
1779 dev_err(&pdev->dev, "can't find rockchip,grf property\n");
1780 return PTR_ERR(edp->grf);
1783 if (edp->soctype == SOC_RK3399) {
1784 edp->grf_clk = devm_clk_get(&pdev->dev, "clk_grf");
1785 if (IS_ERR(edp->grf_clk)) {
1786 dev_err(&pdev->dev, "cannot get grf clk\n");
1787 return PTR_ERR(edp->grf_clk);
1791 edp->pd = devm_clk_get(&pdev->dev, "pd_edp");
1792 if (IS_ERR(edp->pd)) {
1793 dev_err(&pdev->dev, "cannot get pd\n");
1797 edp->clk_edp = devm_clk_get(&pdev->dev, "clk_edp");
1798 if (IS_ERR(edp->clk_edp)) {
1799 dev_err(&pdev->dev, "cannot get clk_edp\n");
1800 return PTR_ERR(edp->clk_edp);
1803 if (edp->soctype != SOC_RK3399) {
1804 edp->clk_24m = devm_clk_get(&pdev->dev, "clk_edp_24m");
1805 if (IS_ERR(edp->clk_24m)) {
1806 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1807 return PTR_ERR(edp->clk_24m);
1811 edp->pclk = devm_clk_get(&pdev->dev, "pclk_edp");
1812 if (IS_ERR(edp->pclk)) {
1813 dev_err(&pdev->dev, "cannot get pclk\n");
1814 return PTR_ERR(edp->pclk);
1817 /* We use the reset API to control the software reset at this version
1818 * and later, and we reserve the code that setting the cru regs directly
1821 if (edp->soctype != SOC_RK3399) {
1822 /*edp 24m need sorft reset*/
1823 edp->rst_24m = devm_reset_control_get(&pdev->dev, "edp_24m");
1824 if (IS_ERR(edp->rst_24m))
1825 dev_err(&pdev->dev, "failed to get reset\n");
1828 /* edp ctrl apb bus need sorft reset */
1829 edp->rst_apb = devm_reset_control_get(&pdev->dev, "edp_apb");
1830 if (IS_ERR(edp->rst_apb))
1831 dev_err(&pdev->dev, "failed to get reset\n");
1832 rk32_edp_clk_enable(edp);
1833 if (!support_uboot_display())
1834 rk32_edp_pre_init(edp);
1835 edp->irq = platform_get_irq(pdev, 0);
1837 dev_err(&pdev->dev, "cannot find IRQ\n");
1840 ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1841 dev_name(&pdev->dev), edp);
1843 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1846 disable_irq_nosync(edp->irq);
1847 if (!support_uboot_display())
1848 rk32_edp_clk_disable(edp);
1850 pm_runtime_enable(&pdev->dev);
1851 if (support_uboot_display()) {
1853 pm_runtime_get_sync(&pdev->dev);
1857 rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1858 #if defined(CONFIG_DEBUG_FS)
1859 edp->debugfs_dir = debugfs_create_dir("edp", NULL);
1860 if (IS_ERR(edp->debugfs_dir)) {
1861 dev_err(edp->dev, "failed to create debugfs dir for edp!\n");
1863 debugfs_create_file("dpcd", S_IRUSR, edp->debugfs_dir,
1864 edp, &edp_dpcd_debugfs_fops);
1865 debugfs_create_file("edid", S_IRUSR, edp->debugfs_dir,
1866 edp, &edp_edid_debugfs_fops);
1867 debugfs_create_file("reg", S_IRUSR, edp->debugfs_dir,
1868 edp, &edp_reg_debugfs_fops);
1869 debugfs_create_file("psr", S_IRUSR, edp->debugfs_dir,
1870 edp, &edp_psr_debugfs_fops);
1874 dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1879 static int rockchip_edp_remove(struct platform_device *pdev)
1881 pm_runtime_disable(&pdev->dev);
1885 #if defined(CONFIG_OF)
1886 static const struct of_device_id rk32_edp_dt_ids[] = {
1887 {.compatible = "rockchip,rk32-edp", .data = (void *)SOC_COMMON},
1888 {.compatible = "rockchip,rk3399-edp-fb", .data = (void *)SOC_RK3399},
1892 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1895 static struct platform_driver rk32_edp_driver = {
1896 .probe = rk32_edp_probe,
1897 .remove = rockchip_edp_remove,
1900 .owner = THIS_MODULE,
1901 #if defined(CONFIG_OF)
1902 .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1907 static int __init rk32_edp_module_init(void)
1909 return platform_driver_register(&rk32_edp_driver);
1912 static void __exit rk32_edp_module_exit(void)
1916 fs_initcall(rk32_edp_module_init);
1917 module_exit(rk32_edp_module_exit);