2 * DisplayPort driver for rk32xx
4 * Copyright (C) ROCKCHIP, Inc.
5 *Author:yxj<yxj@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/rockchip/cpu.h>
24 #include <linux/rockchip/iomap.h>
25 #include <linux/rockchip/grf.h>
26 #include <linux/string.h>
27 #include <linux/slab.h>
28 #include <linux/uaccess.h>
30 #if defined(CONFIG_OF)
32 #include <linux/of_device.h>
35 #if defined(CONFIG_DEBUG_FS)
37 #include <linux/debugfs.h>
38 #include <linux/seq_file.h>
43 /*#define EDP_BIST_MODE*/
46 #define RK3368_GRF_SOC_CON4 0x410
48 static struct rk32_edp *rk32_edp;
50 static int rk32_edp_clk_enable(struct rk32_edp *edp)
56 clk_prepare_enable(edp->pd);
57 clk_prepare_enable(edp->pclk);
58 clk_prepare_enable(edp->clk_edp);
60 if (edp->soctype != SOC_RK3399) {
61 ret = clk_set_rate(edp->clk_24m, 24000000);
63 pr_err("cannot set edp clk_24m %d\n", ret);
64 clk_prepare_enable(edp->clk_24m);
72 static int rk32_edp_clk_disable(struct rk32_edp *edp)
75 clk_disable_unprepare(edp->pclk);
76 clk_disable_unprepare(edp->clk_edp);
78 if (edp->soctype != SOC_RK3399)
79 clk_disable_unprepare(edp->clk_24m);
82 clk_disable_unprepare(edp->pd);
89 static int rk32_edp_pre_init(struct rk32_edp *edp)
93 if (cpu_is_rk3288()) {
94 val = GRF_EDP_REF_CLK_SEL_INTER |
95 (GRF_EDP_REF_CLK_SEL_INTER << 16);
96 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
99 writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
103 writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
107 /* The rk3368 reset the edp 24M clock and apb bus
108 * according to the CRU_SOFTRST6_CON and CRU_SOFTRST7_CON.
110 if (edp->soctype != SOC_RK3399) {
111 val = 0x01 | (0x01 << 16);
112 regmap_write(edp->grf, RK3368_GRF_SOC_CON4, val);
114 reset_control_assert(edp->rst_24m);
115 usleep_range(10, 20);
116 reset_control_deassert(edp->rst_24m);
119 reset_control_assert(edp->rst_apb);
120 usleep_range(10, 20);
121 reset_control_deassert(edp->rst_apb);
126 static int rk32_edp_init_edp(struct rk32_edp *edp)
128 struct rk_screen *screen = &edp->screen;
131 rk_fb_get_prmry_screen(screen);
133 if (cpu_is_rk3288()) {
134 if (screen->lcdc_id == 1) /*select lcdc*/
135 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
137 val = EDP_SEL_VOP_LIT << 16;
138 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
142 rk32_edp_init_refclk(edp);
143 rk32_edp_init_interrupt(edp);
144 rk32_edp_enable_sw_function(edp);
145 rk32_edp_init_analog_func(edp);
146 rk32_edp_init_hpd(edp);
147 rk32_edp_init_aux(edp);
153 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
155 int timeout_loop = 0;
157 rk32_edp_init_hpd(edp);
161 while (rk32_edp_get_plug_in_status(edp) != 0) {
163 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
164 dev_err(edp->dev, "failed to get hpd plug status\n");
174 static int rk32_edp_read_edid(struct rk32_edp *edp)
176 unsigned char edid[EDID_LENGTH * 2];
177 unsigned int extend_block = 0;
179 unsigned char test_vector;
183 * EDID device address is 0x50.
184 * However, if necessary, you must have set upper address
185 * into E-EDID in I2C device, 0x30.
188 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
189 retval = rk32_edp_read_byte_from_i2c
191 EDID_ADDR, EDID_EXTENSION_FLAG, &extend_block);
193 dev_err(edp->dev, "EDID extension flag failed!\n");
197 if (extend_block > 0) {
198 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
201 retval = rk32_edp_read_bytes_from_i2c
203 EDID_ADDR, EDID_HEADER,
204 EDID_LENGTH, &edid[EDID_HEADER]);
206 dev_err(edp->dev, "EDID Read failed!\n");
209 sum = edp_calc_edid_check_sum(edid);
211 dev_warn(edp->dev, "EDID bad checksum!\n");
215 /* Read additional EDID data */
216 retval = rk32_edp_read_bytes_from_i2c
218 EDID_ADDR, EDID_LENGTH,
219 EDID_LENGTH, &edid[EDID_LENGTH]);
221 dev_err(edp->dev, "EDID Read failed!\n");
224 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
226 dev_warn(edp->dev, "EDID bad checksum!\n");
230 retval = rk32_edp_read_byte_from_dpcd
232 DPCD_TEST_REQUEST, &test_vector);
234 dev_err(edp->dev, "DPCD EDID Read failed!\n");
238 if (test_vector & DPCD_TEST_EDID_READ) {
239 retval = rk32_edp_write_byte_to_dpcd
241 DPCD_TEST_EDID_CHECKSUM,
242 edid[EDID_LENGTH + EDID_CHECKSUM]);
244 dev_err(edp->dev, "DPCD EDID Write failed!\n");
247 retval = rk32_edp_write_byte_to_dpcd
250 DPCD_TEST_EDID_CHECKSUM_WRITE);
252 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
257 dev_info(edp->dev, "EDID data does not include any extensions.\n");
260 retval = rk32_edp_read_bytes_from_i2c
262 EDID_ADDR, EDID_HEADER,
263 EDID_LENGTH, &edid[EDID_HEADER]);
265 dev_err(edp->dev, "EDID Read failed!\n");
268 sum = edp_calc_edid_check_sum(edid);
270 dev_warn(edp->dev, "EDID bad checksum!\n");
274 retval = rk32_edp_read_byte_from_dpcd
276 DPCD_TEST_REQUEST, &test_vector);
278 dev_err(edp->dev, "DPCD EDID Read failed!\n");
282 if (test_vector & DPCD_TEST_EDID_READ) {
283 retval = rk32_edp_write_byte_to_dpcd
285 DPCD_TEST_EDID_CHECKSUM,
286 edid[EDID_CHECKSUM]);
288 dev_err(edp->dev, "DPCD EDID Write failed!\n");
291 retval = rk32_edp_write_byte_to_dpcd
294 DPCD_TEST_EDID_CHECKSUM_WRITE);
296 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
301 fb_edid_to_monspecs(edid, &edp->specs);
302 dev_err(edp->dev, "EDID Read success!\n");
307 static int rk32_edp_handle_edid(struct rk32_edp *edp)
313 /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
314 retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
318 for (i = 0; i < 12; i++)
319 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
321 for (i = 0; i < 3; i++) {
322 retval = rk32_edp_read_edid(edp);
331 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
337 retval = rk32_edp_read_byte_from_dpcd
339 DPCD_LANE_CNT_SET, &data);
344 retval = rk32_edp_write_byte_to_dpcd
347 DPCD_ENHANCED_FRAME_EN |
348 DPCD_LANE_COUNT_SET(data));
350 /*retval = rk32_edp_write_byte_to_dpcd(edp,
351 DPCD_ADDR_CONFIGURATION_SET, 0);*/
353 retval = rk32_edp_write_byte_to_dpcd
356 DPCD_LANE_COUNT_SET(data));
362 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
364 /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
365 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
368 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
369 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
371 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
376 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
381 retval = rk32_edp_read_byte_from_dpcd
383 DPCD_MAX_LANE_CNT, &data);
387 return DPCD_ENHANCED_FRAME_CAP(data);
391 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
393 /*rk32_edp_write_byte_to_dpcd(edp,
394 DPCD_ADDR_USER_DEFINED1, 0);
395 rk32_edp_write_byte_to_dpcd(edp,
396 DPCD_ADDR_USER_DEFINED2, 0x83);
397 rk32_edp_write_byte_to_dpcd(edp,
398 DPCD_ADDR_USER_DEFINED3, 0x27);*/
401 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
406 retval = rk32_edp_is_enhanced_mode_available(edp);
411 retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
415 rk32_edp_enable_enhanced_mode(edp, data);
423 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
427 rk32_edp_set_training_pattern(edp, DP_NONE);
429 retval = rk32_edp_write_byte_to_dpcd(edp,
430 DPCD_TRAINING_PATTERN_SET,
431 DPCD_TRAINING_PATTERN_DISABLED);
438 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
439 int pre_emphasis, int lane)
443 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
446 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
450 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
454 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
459 static int rk32_edp_link_start(struct rk32_edp *edp)
466 lane_count = edp->link_train.lane_count;
468 edp->link_train.lt_state = LT_CLK_RECOVERY;
469 edp->link_train.eq_loop = 0;
471 for (lane = 0; lane < lane_count; lane++)
472 edp->link_train.cr_loop[lane] = 0;
474 /* Set sink to D0 (Sink Not Ready) mode. */
475 retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
476 DPCD_SET_POWER_STATE_D0);
478 dev_err(edp->dev, "failed to set sink device to D0!\n");
482 /* Set link rate and count as you want to establish*/
483 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
484 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
486 /* Setup RX configuration */
487 buf[0] = edp->link_train.link_rate;
488 buf[1] = edp->link_train.lane_count;
489 retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
492 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
496 /* Set TX pre-emphasis to level1 */
497 for (lane = 0; lane < lane_count; lane++)
498 rk32_edp_set_lane_lane_pre_emphasis
500 PRE_EMPHASIS_LEVEL_1, lane);
502 /* Set training pattern 1 */
503 rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
505 /* Set RX training pattern */
506 retval = rk32_edp_write_byte_to_dpcd(edp,
507 DPCD_TRAINING_PATTERN_SET,
508 DPCD_SCRAMBLING_DISABLED |
509 DPCD_TRAINING_PATTERN_1);
511 dev_err(edp->dev, "failed to set training pattern 1!\n");
515 for (lane = 0; lane < lane_count; lane++)
516 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
517 DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
518 retval = rk32_edp_write_bytes_to_dpcd(edp,
519 DPCD_TRAINING_LANE0_SET,
522 dev_err(edp->dev, "failed to set training lane!\n");
529 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
531 int shift = (lane & 1) * 4;
532 u8 link_value = link_status[lane>>1];
534 return (link_value >> shift) & 0xf;
537 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
542 for (lane = 0; lane < lane_count; lane++) {
543 lane_status = rk32_edp_get_lane_status(link_status, lane);
544 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
550 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
556 lane_align = link_align[2];
557 if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
560 for (lane = 0; lane < lane_count; lane++) {
561 lane_status = rk32_edp_get_lane_status(link_align, lane);
562 lane_status &= DPCD_CHANNEL_EQ_BITS;
563 if (lane_status != DPCD_CHANNEL_EQ_BITS)
570 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
573 int shift = (lane & 1) * 4;
574 u8 link_value = adjust_request[lane>>1];
576 return (link_value >> shift) & 0x3;
579 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
580 u8 adjust_request[2],
583 int shift = (lane & 1) * 4;
584 u8 link_value = adjust_request[lane>>1];
586 return ((link_value >> shift) & 0xc) >> 2;
589 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
590 u8 training_lane_set, int lane)
594 rk32_edp_set_lane0_link_training(edp, training_lane_set);
597 rk32_edp_set_lane1_link_training(edp, training_lane_set);
601 rk32_edp_set_lane2_link_training(edp, training_lane_set);
605 rk32_edp_set_lane3_link_training(edp, training_lane_set);
610 static unsigned int rk32_edp_get_lane_link_training(
611 struct rk32_edp *edp,
618 reg = rk32_edp_get_lane0_link_training(edp);
621 reg = rk32_edp_get_lane1_link_training(edp);
624 reg = rk32_edp_get_lane2_link_training(edp);
627 reg = rk32_edp_get_lane3_link_training(edp);
634 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
636 rk32_edp_training_pattern_dis(edp);
638 edp->link_train.lt_state = FAILED;
641 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
647 u8 adjust_request[2];
654 usleep_range(99, 100);
656 lane_count = edp->link_train.lane_count;
658 retval = rk32_edp_read_bytes_from_dpcd(edp,
662 dev_err(edp->dev, "failed to read lane status!\n");
666 if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
667 /* set training pattern 2 for EQ */
668 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
670 for (lane = 0; lane < lane_count; lane++) {
671 retval = rk32_edp_read_bytes_from_dpcd
673 DPCD_ADJUST_REQUEST_LANE0_1,
676 dev_err(edp->dev, "failed to read adjust request!\n");
680 voltage_swing = rk32_edp_get_adjust_request_voltage(
681 adjust_request, lane);
682 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
683 adjust_request, lane);
684 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
685 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
687 if (voltage_swing == VOLTAGE_LEVEL_3)
688 training_lane |= DPCD_MAX_SWING_REACHED;
689 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
690 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
692 edp->link_train.training_lane[lane] = training_lane;
694 rk32_edp_set_lane_link_training
696 edp->link_train.training_lane[lane],
700 retval = rk32_edp_write_byte_to_dpcd(edp,
701 DPCD_TRAINING_PATTERN_SET,
702 DPCD_SCRAMBLING_DISABLED |
703 DPCD_TRAINING_PATTERN_2);
705 dev_err(edp->dev, "failed to set training pattern 2!\n");
709 retval = rk32_edp_write_bytes_to_dpcd(edp,
710 DPCD_TRAINING_LANE0_SET,
712 edp->link_train.training_lane);
714 dev_err(edp->dev, "failed to set training lane!\n");
718 dev_info(edp->dev, "Link Training Clock Recovery success\n");
719 edp->link_train.lt_state = LT_EQ_TRAINING;
721 for (lane = 0; lane < lane_count; lane++) {
722 training_lane = rk32_edp_get_lane_link_training(
724 retval = rk32_edp_read_bytes_from_dpcd
726 DPCD_ADJUST_REQUEST_LANE0_1,
729 dev_err(edp->dev, "failed to read adjust request!\n");
733 voltage_swing = rk32_edp_get_adjust_request_voltage(
734 adjust_request, lane);
735 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
736 adjust_request, lane);
738 if (voltage_swing == VOLTAGE_LEVEL_3 ||
739 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
740 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
741 goto reduce_link_rate;
744 if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
746 (DPCD_PRE_EMPHASIS_GET(training_lane) ==
748 edp->link_train.cr_loop[lane]++;
749 if (edp->link_train.cr_loop[lane] ==
751 dev_err(edp->dev, "CR Max loop\n");
752 goto reduce_link_rate;
756 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
757 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
759 if (voltage_swing == VOLTAGE_LEVEL_3)
760 training_lane |= DPCD_MAX_SWING_REACHED;
761 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
762 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
764 edp->link_train.training_lane[lane] = training_lane;
766 rk32_edp_set_lane_link_training
768 edp->link_train.training_lane[lane], lane);
771 retval = rk32_edp_write_bytes_to_dpcd
773 DPCD_TRAINING_LANE0_SET,
775 edp->link_train.training_lane);
777 dev_err(edp->dev, "failed to set training lane!\n");
785 rk32_edp_reduce_link_rate(edp);
789 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
797 u8 adjust_request[2];
804 usleep_range(399, 400);
806 lane_count = edp->link_train.lane_count;
808 retval = rk32_edp_read_bytes_from_dpcd(edp,
812 dev_err(edp->dev, "failed to read lane status!\n");
816 if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
817 link_align[0] = link_status[0];
818 link_align[1] = link_status[1];
820 retval = rk32_edp_read_byte_from_dpcd
822 DPCD_LANE_ALIGN_STATUS_UPDATED,
825 dev_err(edp->dev, "failed to read lane aligne status!\n");
829 for (lane = 0; lane < lane_count; lane++) {
830 retval = rk32_edp_read_bytes_from_dpcd
832 DPCD_ADJUST_REQUEST_LANE0_1,
835 dev_err(edp->dev, "failed to read adjust request!\n");
839 voltage_swing = rk32_edp_get_adjust_request_voltage(
840 adjust_request, lane);
841 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
842 adjust_request, lane);
843 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
844 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
846 if (voltage_swing == VOLTAGE_LEVEL_3)
847 training_lane |= DPCD_MAX_SWING_REACHED;
848 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
849 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
851 edp->link_train.training_lane[lane] = training_lane;
854 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
855 /* traing pattern Set to Normal */
856 retval = rk32_edp_training_pattern_dis(edp);
858 dev_err(edp->dev, "failed to disable training pattern!\n");
862 dev_info(edp->dev, "Link Training success!\n");
864 rk32_edp_get_link_bandwidth(edp, ®);
865 edp->link_train.link_rate = reg;
866 dev_dbg(edp->dev, "final bandwidth = %.2x\n",
867 edp->link_train.link_rate);
869 rk32_edp_get_lane_count(edp, ®);
870 edp->link_train.lane_count = reg;
871 dev_dbg(edp->dev, "final lane count = %.2x\n",
872 edp->link_train.lane_count);
874 edp->link_train.lt_state = FINISHED;
877 edp->link_train.eq_loop++;
879 if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
880 dev_err(edp->dev, "EQ Max loop\n");
881 goto reduce_link_rate;
884 for (lane = 0; lane < lane_count; lane++)
885 rk32_edp_set_lane_link_training
887 edp->link_train.training_lane[lane],
890 retval = rk32_edp_write_bytes_to_dpcd
892 DPCD_TRAINING_LANE0_SET,
894 edp->link_train.training_lane);
896 dev_err(edp->dev, "failed to set training lane!\n");
901 goto reduce_link_rate;
907 rk32_edp_reduce_link_rate(edp);
911 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
918 * For DP rev.1.1, Maximum link rate of Main Link lanes
919 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
921 retval = rk32_edp_read_byte_from_dpcd(edp,
922 DPCD_MAX_LINK_RATE, &data);
930 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
937 * For DP rev.1.1, Maximum number of Main Link lanes
938 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
940 retval = rk32_edp_read_byte_from_dpcd(edp,
941 DPCD_MAX_LANE_CNT, &data);
945 *lane_count = DPCD_MAX_LANE_COUNT(data);
949 static int rk32_edp_init_training(struct rk32_edp *edp)
954 * MACRO_RST must be applied after the PLL_LOCK to avoid
955 * the DP inter pair skew issue for at least 10 us
957 rk32_edp_reset_macro(edp);
960 retval = rk32_edp_get_max_rx_bandwidth(edp,
961 &edp->link_train.link_rate);
962 retval = rk32_edp_get_max_rx_lane_count(edp,
963 &edp->link_train.lane_count);
964 dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
965 edp->link_train.link_rate * 27/100,
966 edp->link_train.link_rate*27%100,
967 edp->link_train.lane_count);
969 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
970 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
973 "Rx Mx Link Rate is abnormal:%x!default link rate:%d.%dGps\n",
974 edp->link_train.link_rate,
975 edp->video_info.link_rate*27/100,
976 edp->video_info.link_rate*27%100);
977 edp->link_train.link_rate = edp->video_info.link_rate;
980 if (edp->link_train.lane_count == 0) {
983 "Rx Max Lane count is abnormal :%x !use default lanes:%d\n",
984 edp->link_train.lane_count,
985 edp->video_info.lane_count);
986 edp->link_train.lane_count = edp->video_info.lane_count;
989 rk32_edp_analog_power_ctr(edp, 1);
996 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
999 int training_finished = 0;
1001 edp->link_train.lt_state = LT_START;
1004 while (!training_finished) {
1005 switch (edp->link_train.lt_state) {
1007 retval = rk32_edp_link_start(edp);
1009 dev_err(edp->dev, "LT Start failed\n");
1011 case LT_CLK_RECOVERY:
1012 retval = rk32_edp_process_clock_recovery(edp);
1014 dev_err(edp->dev, "LT CR failed\n");
1016 case LT_EQ_TRAINING:
1017 retval = rk32_edp_process_equalizer_training(edp);
1019 dev_err(edp->dev, "LT EQ failed\n");
1022 training_finished = 1;
1033 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
1037 /* Set link rate and count as you want to establish*/
1038 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1039 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1040 rk32_edp_hw_link_training_en(edp);
1041 val = rk32_edp_wait_hw_lt_done(edp);
1044 dev_err(edp->dev, "hw lt timeout");
1048 val = rk32_edp_wait_hw_lt_done(edp);
1051 val = rk32_edp_get_hw_lt_status(edp);
1053 dev_err(edp->dev, "hw lt err:%d\n", val);
1058 static int rk32_edp_set_link_train(struct rk32_edp *edp)
1062 retval = rk32_edp_init_training(edp);
1064 dev_err(edp->dev, "DP LT init failed!\n");
1066 retval = rk32_edp_sw_link_training(edp);
1068 retval = rk32_edp_hw_link_training(edp);
1074 static int rk32_edp_config_video(struct rk32_edp *edp,
1075 struct video_info *video_info)
1078 int timeout_loop = 0;
1081 rk32_edp_config_video_slave_mode(edp, video_info);
1083 rk32_edp_set_video_color_format(edp, video_info->color_depth,
1084 video_info->color_space,
1085 video_info->dynamic_range,
1086 video_info->ycbcr_coeff);
1088 if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
1089 dev_err(edp->dev, "PLL is not locked yet.\n");
1095 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
1097 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1098 dev_err(edp->dev, "Timeout of video streamclk ok\n");
1105 /* Set to use the register calculated M/N video */
1106 rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1108 /* For video bist, Video timing must be generated by register */
1109 #ifndef EDP_BIST_MODE
1110 rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
1112 /* Disable video mute */
1113 rk32_edp_enable_video_mute(edp, 0);
1115 /* Configure video slave mode */
1116 rk32_edp_enable_video_master(edp, 0);
1119 rk32_edp_start_video(edp);
1125 if (rk32_edp_is_video_stream_on(edp) == 0) {
1127 if (done_count > 10)
1129 } else if (done_count) {
1132 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1133 dev_err(edp->dev, "Timeout of video streamclk ok\n");
1141 dev_err(edp->dev, "Video stream is not detected!\n");
1146 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1148 struct rk32_edp *edp = arg;
1149 enum dp_irq_type irq_type;
1151 irq_type = rk32_edp_get_irq_type(edp);
1153 case DP_IRQ_TYPE_HP_CABLE_IN:
1154 dev_info(edp->dev, "Received irq - cable in\n");
1155 rk32_edp_clear_hotplug_interrupts(edp);
1157 case DP_IRQ_TYPE_HP_CABLE_OUT:
1158 dev_info(edp->dev, "Received irq - cable out\n");
1159 rk32_edp_clear_hotplug_interrupts(edp);
1161 case DP_IRQ_TYPE_HP_CHANGE:
1163 * We get these change notifications once in a while, but there
1164 * is nothing we can do with them. Just ignore it for now and
1165 * only handle cable changes.
1167 dev_info(edp->dev, "Received irq - hotplug change; ignoring.\n");
1168 rk32_edp_clear_hotplug_interrupts(edp);
1171 dev_err(edp->dev, "Received irq - unknown type!\n");
1177 static int rk32_edp_enable(void)
1180 struct rk32_edp *edp = rk32_edp;
1183 rk32_edp_clk_enable(edp);
1184 pm_runtime_get_sync(edp->dev);
1185 rk32_edp_pre_init(edp);
1186 rk32_edp_init_edp(edp);
1187 enable_irq(edp->irq);
1188 /*ret = rk32_edp_handle_edid(edp);
1190 dev_err(edp->dev, "unable to handle edid\n");
1194 ret = rk32_edp_enable_scramble(edp, 0);
1196 dev_err(edp->dev, "unable to set scramble\n");
1200 ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1202 dev_err(edp->dev, "unable to set enhanced mode\n");
1205 rk32_edp_enable_enhanced_mode(edp, 1);*/
1207 ret = rk32_edp_set_link_train(edp);
1209 dev_err(edp->dev, "link train failed!\n");
1211 dev_info(edp->dev, "link training success.\n");
1213 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1214 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1215 rk32_edp_init_video(edp);
1217 #ifdef EDP_BIST_MODE
1218 rk32_edp_bist_cfg(edp);
1220 ret = rk32_edp_config_video(edp, &edp->video_info);
1222 dev_err(edp->dev, "unable to config video\n");
1229 static int rk32_edp_disable(void)
1231 struct rk32_edp *edp = rk32_edp;
1234 pm_runtime_put(edp->dev);
1235 disable_irq(edp->irq);
1236 rk32_edp_reset(edp);
1237 rk32_edp_analog_power_ctr(edp, 0);
1238 rk32_edp_clk_disable(edp);
1239 edp->edp_en = false;
1246 static struct rk_fb_trsm_ops trsm_edp_ops = {
1247 .enable = rk32_edp_enable,
1248 .disable = rk32_edp_disable,
1252 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1258 rk32_edp_enable_scrambling(edp);
1260 retval = rk32_edp_read_byte_from_dpcd
1262 DPCD_TRAINING_PATTERN_SET,
1267 retval = rk32_edp_write_byte_to_dpcd
1269 DPCD_TRAINING_PATTERN_SET,
1270 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1274 rk32_edp_disable_scrambling(edp);
1276 retval = rk32_edp_read_byte_from_dpcd
1278 DPCD_TRAINING_PATTERN_SET,
1283 retval = rk32_edp_write_byte_to_dpcd
1285 DPCD_TRAINING_PATTERN_SET,
1286 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1294 static int rk32_edp_psr_enable(struct rk32_edp *edp)
1298 char date, psr_version;
1301 retval = rk32_edp_read_byte_from_dpcd
1303 PANEL_SELF_REFRESH_CAPABILITY_SUPPORTED_AND_VERSION,
1306 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1309 pr_info("PSR supporter and version:%x\n", psr_version);
1312 /*PSR capabilities*/
1313 retval = rk32_edp_read_byte_from_dpcd
1315 PANEL_SELF_REFRESH_CAPABILITIES, &date);
1317 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1320 pr_info("PSR capabilities:%x\n", date);
1323 if (psr_version & PSR_SUPPORT) {
1324 pr_info("PSR config psr\n");
1328 retval = rk32_edp_write_bytes_to_dpcd(edp, PSR_ENABLE,
1331 dev_err(edp->dev, "PSR failed to config sink PSR!\n");
1336 retval = rk32_edp_write_bytes_to_dpcd(edp,
1340 dev_err(edp->dev, "PSR failed to enable the PSR!\n");
1343 /*read sink config state*/
1344 retval = rk32_edp_read_byte_from_dpcd
1348 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1351 pr_info("PSR sink config state:%x\n", date);
1356 retval = rk32_edp_read_byte_from_dpcd(edp, 0x270, &buf);
1358 retval = rk32_edp_write_bytes_to_dpcd(edp, 0x270, 1, &buf);
1363 static int psr_header_HB_PB(struct rk32_edp *edp)
1368 writel(val, edp->regs + HB0);/*HB0*/
1370 writel(val, edp->regs + HB1);/*HB1*/
1372 writel(val, edp->regs + HB2);/*HB2*/
1374 writel(val, edp->regs + HB3);/*HB3*/
1376 writel(val, edp->regs + PB0);/*PB0*/
1378 writel(val, edp->regs + PB1);/*PB1*/
1380 writel(val, edp->regs + PB2);/*PB2*/
1382 writel(val, edp->regs + PB3);/*PB3*/
1387 static int psr_enable_sdp(struct rk32_edp *edp)
1391 val = readl(edp->regs + SPDIF_AUDIO_CTL_0);
1393 writel(val, edp->regs + SPDIF_AUDIO_CTL_0);/*enable SDP*/
1394 val = readl(edp->regs + SPDIF_AUDIO_CTL_0);
1395 pr_info("PSR reuse_spd_en:%x\n", val);
1398 writel(val, edp->regs + IF_TYPE);/*enable IF_TYPE*/
1399 val = readl(edp->regs + IF_TYPE);
1400 pr_info("PSR IF_TYPE :%x\n", val);
1402 val = readl(edp->regs + PKT_SEND_CTL);
1404 writel(val, edp->regs + PKT_SEND_CTL);/*enable IF_UP*/
1405 val = readl(edp->regs + PKT_SEND_CTL);
1406 pr_info("PSR if_up :%x\n", val);
1408 val = readl(edp->regs + PKT_SEND_CTL);
1410 writel(val, edp->regs + PKT_SEND_CTL);/*enable IF_EN*/
1411 val = readl(edp->regs + PKT_SEND_CTL);
1412 pr_info("PSR if_en:%x\n", val);
1415 static int edp_disable_psr(struct rk32_edp *edp)
1421 /*disable sink PSR*/
1422 retval = rk32_edp_read_byte_from_dpcd(edp,
1425 dev_err(edp->dev, "PSR sink original config Read failed!\n");
1429 retval = rk32_edp_write_bytes_to_dpcd
1434 dev_err(edp->dev, "PSR failed to disable sink PSR!\n");
1438 pr_info("PSR disable success!!\n");
1442 static int edp_psr_state(struct rk32_edp *edp, int state)
1445 /*wait for VD blank*/
1446 if (rk_fb_poll_wait_frame_complete()) {
1447 psr_header_HB_PB(edp);
1450 writel(val, edp->regs + DB1);
1451 /*val = readl(edp->regs + DB1);
1452 pr_info("PSR set DB1 state 0x0:%x\n", val);
1454 for (i = 0; i < 22; i++)
1455 writel(0, edp->regs + DB2 + 4 * i);*/
1457 psr_enable_sdp(edp);
1463 static int phy_power_channel(struct rk32_edp *edp, int state)
1468 writel(val, edp->regs + DP_PD);
1473 #if defined(CONFIG_DEBUG_FS)
1475 static int edp_dpcd_debugfs_show(struct seq_file *s, void *v)
1478 unsigned char buf[12];
1479 struct rk32_edp *edp = s->private;
1482 dev_err(edp->dev, "no edp device!\n");
1486 retval = rk32_edp_read_byte_from_dpcd
1488 PANEL_SELF_REFRESH_CAPABILITY_SUPPORTED_AND_VERSION,
1490 seq_printf(s, "0x70 %x\n", buf[0]);
1492 /*PSR capabilities*/
1493 retval = rk32_edp_read_byte_from_dpcd
1495 PANEL_SELF_REFRESH_CAPABILITIES, &buf[0]);
1496 seq_printf(s, "0x71 %x\n", buf[0]);
1498 retval = rk32_edp_read_byte_from_dpcd
1500 PSR_ENABLE, &buf[0]);
1501 seq_printf(s, "0x170 %x\n", buf[0]);
1503 retval = rk32_edp_read_byte_from_dpcd(edp, 0x2006, &buf[0]);
1504 seq_printf(s, "0x2006 %x\n", buf[0]);
1506 retval = rk32_edp_read_byte_from_dpcd(edp, 0x2007, &buf[0]);
1507 seq_printf(s, "0x2007 %x\n", buf[0]);
1509 retval = rk32_edp_read_byte_from_dpcd(edp, 0x2008, &buf[0]);
1510 seq_printf(s, "0x2008 %x\n", buf[0]);
1511 retval = rk32_edp_read_byte_from_dpcd(edp, 0x2009, &buf[0]);
1512 seq_printf(s, "0x2009 %x\n", buf[0]);
1514 retval = rk32_edp_read_byte_from_dpcd(edp, 0x200a, &buf[0]);
1515 seq_printf(s, "0x200a %x\n", buf[0]);
1517 retval = rk32_edp_read_byte_from_dpcd(edp, 0x240, &buf[0]);
1518 seq_printf(s, "0x240 %x\n", buf[0]);
1519 retval = rk32_edp_read_byte_from_dpcd(edp, 0x241, &buf[0]);
1520 seq_printf(s, "0x241 %x\n", buf[0]);
1521 retval = rk32_edp_read_byte_from_dpcd(edp, 0x242, &buf[0]);
1522 seq_printf(s, "0x242 %x\n", buf[0]);
1523 retval = rk32_edp_read_byte_from_dpcd(edp, 0x243, &buf[0]);
1524 seq_printf(s, "0x243 %x\n", buf[0]);
1525 retval = rk32_edp_read_byte_from_dpcd(edp, 0x244, &buf[0]);
1526 seq_printf(s, "0x244 %x\n", buf[0]);
1527 retval = rk32_edp_read_byte_from_dpcd(edp, 0x245, &buf[0]);
1528 seq_printf(s, "0x245 %x\n", buf[0]);
1529 retval = rk32_edp_read_byte_from_dpcd(edp, 0x270, &buf[0]);
1530 seq_printf(s, "0x270 %x\n", buf[0]);
1531 retval = rk32_edp_read_byte_from_dpcd(edp, 0x246, &buf[0]);
1532 seq_printf(s, "0x246 %x\n", buf[0]);
1534 /*retval = rk32_edp_read_byte_from_dpcd(edp, 0x222, &buf[0]);
1535 seq_printf(s, "0x222 %x\n", buf[0]);
1536 retval = rk32_edp_read_byte_from_dpcd(edp, 0x223, &buf[0]);
1537 seq_printf(s, "0x223 %x\n", buf[0]);
1538 retval = rk32_edp_read_byte_from_dpcd(edp, 0x224, &buf[0]);
1539 seq_printf(s, "0x224 %x\n", buf[0]);
1540 retval = rk32_edp_read_byte_from_dpcd(edp, 0x225, &buf[0]);
1541 seq_printf(s, "0x225 %x\n", buf[0]);
1542 retval = rk32_edp_read_byte_from_dpcd(edp, 0x226, &buf[0]);
1543 seq_printf(s, "0x226 %x\n", buf[0]);
1544 retval = rk32_edp_read_byte_from_dpcd(edp, 0x227, &buf[0]);
1545 seq_printf(s, "0x227 %x\n", buf[0]);
1546 retval = rk32_edp_read_byte_from_dpcd(edp, 0x228, &buf[0]);
1547 seq_printf(s, "0x228 %x\n", buf[0]);
1548 retval = rk32_edp_read_byte_from_dpcd(edp, 0x229, &buf[0]);
1549 seq_printf(s, "0x229 %x\n", buf[0]);
1550 retval = rk32_edp_read_byte_from_dpcd(edp, 0x22a, &buf[0]);
1551 seq_printf(s, "0x22a %x\n", buf[0]);
1552 retval = rk32_edp_read_byte_from_dpcd(edp, 0x22b, &buf[0]);
1553 seq_printf(s, "0x22b %x\n", buf[0]);
1554 retval = rk32_edp_read_byte_from_dpcd(edp, 0x22c, &buf[0]);
1555 seq_printf(s, "0x22c %x\n", buf[0]);
1556 retval = rk32_edp_read_byte_from_dpcd(edp, 0x22d, &buf[0]);
1557 seq_printf(s, "0x22d %x\n", buf[0]);
1558 retval = rk32_edp_read_byte_from_dpcd(edp, 0x22e, &buf[0]);
1559 seq_printf(s, "0x22e %x\n", buf[0]);
1560 retval = rk32_edp_read_byte_from_dpcd(edp, 0x22f, &buf[0]);
1561 seq_printf(s, "0x22f %x\n", buf[0]);
1562 retval = rk32_edp_read_byte_from_dpcd(edp, 0x230, &buf[0]);
1563 seq_printf(s, "0x230 %x\n", buf[0]);
1564 retval = rk32_edp_read_byte_from_dpcd(edp, 0x231, &buf[0]);
1565 seq_printf(s, "0x231 %x\n", buf[0]);*/
1567 /*rk32_edp_read_bytes_from_dpcd(edp,
1568 DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
1569 for (i = 0; i < 12; i++)
1570 seq_printf(s, "0x%02x>>0x%02x\n", 0x210 + i, buf[i]);*/
1574 static ssize_t edp_dpcd_write(struct file *file,
1575 const char __user *buf,
1582 static int edp_edid_debugfs_show(struct seq_file *s, void *v)
1584 struct rk32_edp *edp = s->private;
1587 dev_err(edp->dev, "no edp device!\n");
1590 rk32_edp_read_edid(edp);
1591 seq_puts(s, "edid");
1595 static ssize_t edp_edid_write(struct file *file,
1596 const char __user *buf,
1600 struct rk32_edp *edp =
1601 ((struct seq_file *)file->private_data)->private;
1604 dev_err(edp->dev, "no edp device!\n");
1612 static int edp_reg_debugfs_show(struct seq_file *s, void *v)
1615 struct rk32_edp *edp = s->private;
1618 dev_err(edp->dev, "no edp device!\n");
1622 for (i = 0; i < 0x284; i++) {
1624 seq_printf(s, "\n%08x: ", i*4);
1625 seq_printf(s, "%08x ", readl(edp->regs + i*4));
1630 static ssize_t edp_reg_write(struct file *file,
1631 const char __user *buf, size_t count,
1637 static int edp_psr_debugfs_show(struct seq_file *s, void *v)
1641 static ssize_t edp_psr_write(struct file *file,
1642 const char __user *buf,
1643 size_t count, loff_t *ppos)
1648 struct rk32_edp *edp =
1649 ((struct seq_file *)file->private_data)->private;
1652 dev_err(edp->dev, "no edp device!\n");
1655 memset(kbuf, 0, 25);
1656 if (copy_from_user(kbuf, buf, count))
1658 retval = kstrtoint(kbuf, 0, &a);
1661 /*retval = sscanf(kbuf, "%d", &a);
1663 dev_err(edp->dev, "PSR failed sscanf!\n");
1668 edp_disable_psr(edp);
1671 rk32_edp_psr_enable(edp);
1674 edp_psr_state(edp, 0x0);
1677 edp_psr_state(edp, 0x01);
1680 edp_psr_state(edp, 0x03);
1683 phy_power_channel(edp, 0xff);
1684 usleep_range(9, 10);
1685 phy_power_channel(edp, 0x7f);
1686 usleep_range(9, 10);
1687 phy_power_channel(edp, 0x0);
1691 phy_power_channel(edp, 0x7f);
1692 usleep_range(9, 10);
1693 phy_power_channel(edp, 0x0f);
1699 #define EDP_DEBUG_ENTRY(name) \
1700 static int edp_##name##_debugfs_open(struct inode *inode, struct file *file) \
1702 return single_open(file, edp_##name##_debugfs_show, inode->i_private); \
1705 static const struct file_operations edp_##name##_debugfs_fops = { \
1706 .owner = THIS_MODULE, \
1707 .open = edp_##name##_debugfs_open, \
1709 .write = edp_##name##_write, \
1710 .llseek = seq_lseek, \
1711 .release = single_release, \
1714 EDP_DEBUG_ENTRY(psr);
1715 EDP_DEBUG_ENTRY(dpcd);
1716 EDP_DEBUG_ENTRY(edid);
1717 EDP_DEBUG_ENTRY(reg);
1720 static int rk32_edp_probe(struct platform_device *pdev)
1722 struct rk32_edp *edp;
1723 struct resource *res;
1724 struct device_node *np = pdev->dev.of_node;
1728 dev_err(&pdev->dev, "Missing device tree node.\n");
1732 edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1734 dev_err(&pdev->dev, "no memory for state\n");
1737 edp->dev = &pdev->dev;
1738 edp->video_info.h_sync_polarity = 0;
1739 edp->video_info.v_sync_polarity = 0;
1740 edp->video_info.interlaced = 0;
1741 edp->video_info.color_space = CS_RGB;
1742 edp->video_info.dynamic_range = VESA;
1743 edp->video_info.ycbcr_coeff = COLOR_YCBCR601;
1744 edp->video_info.color_depth = COLOR_8;
1746 edp->video_info.link_rate = LINK_RATE_1_62GBPS;
1747 edp->video_info.lane_count = LANE_CNT4;
1748 rk_fb_get_prmry_screen(&edp->screen);
1749 if (edp->screen.type != SCREEN_EDP) {
1750 dev_err(&pdev->dev, "screen is not edp!\n");
1754 edp->soctype = (unsigned long)of_device_get_match_data(&pdev->dev);
1756 platform_set_drvdata(pdev, edp);
1757 dev_set_name(edp->dev, "rk32-edp");
1759 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1760 edp->regs = devm_ioremap_resource(&pdev->dev, res);
1761 if (IS_ERR(edp->regs)) {
1762 dev_err(&pdev->dev, "ioremap reg failed\n");
1763 return PTR_ERR(edp->regs);
1766 edp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1767 if (IS_ERR(edp->grf) && !cpu_is_rk3288()) {
1768 dev_err(&pdev->dev, "can't find rockchip,grf property\n");
1769 return PTR_ERR(edp->grf);
1772 edp->pd = devm_clk_get(&pdev->dev, "pd_edp");
1773 if (IS_ERR(edp->pd)) {
1774 dev_err(&pdev->dev, "cannot get pd\n");
1778 edp->clk_edp = devm_clk_get(&pdev->dev, "clk_edp");
1779 if (IS_ERR(edp->clk_edp)) {
1780 dev_err(&pdev->dev, "cannot get clk_edp\n");
1781 return PTR_ERR(edp->clk_edp);
1784 if (edp->soctype != SOC_RK3399) {
1785 edp->clk_24m = devm_clk_get(&pdev->dev, "clk_edp_24m");
1786 if (IS_ERR(edp->clk_24m)) {
1787 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1788 return PTR_ERR(edp->clk_24m);
1792 edp->pclk = devm_clk_get(&pdev->dev, "pclk_edp");
1793 if (IS_ERR(edp->pclk)) {
1794 dev_err(&pdev->dev, "cannot get pclk\n");
1795 return PTR_ERR(edp->pclk);
1798 /* We use the reset API to control the software reset at this version
1799 * and later, and we reserve the code that setting the cru regs directly
1802 if (edp->soctype != SOC_RK3399) {
1803 /*edp 24m need sorft reset*/
1804 edp->rst_24m = devm_reset_control_get(&pdev->dev, "edp_24m");
1805 if (IS_ERR(edp->rst_24m))
1806 dev_err(&pdev->dev, "failed to get reset\n");
1809 /* edp ctrl apb bus need sorft reset */
1810 edp->rst_apb = devm_reset_control_get(&pdev->dev, "edp_apb");
1811 if (IS_ERR(edp->rst_apb))
1812 dev_err(&pdev->dev, "failed to get reset\n");
1813 rk32_edp_clk_enable(edp);
1814 if (!support_uboot_display())
1815 rk32_edp_pre_init(edp);
1816 edp->irq = platform_get_irq(pdev, 0);
1818 dev_err(&pdev->dev, "cannot find IRQ\n");
1821 ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1822 dev_name(&pdev->dev), edp);
1824 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1827 disable_irq_nosync(edp->irq);
1828 if (!support_uboot_display())
1829 rk32_edp_clk_disable(edp);
1831 pm_runtime_enable(&pdev->dev);
1834 rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1835 #if defined(CONFIG_DEBUG_FS)
1836 edp->debugfs_dir = debugfs_create_dir("edp", NULL);
1837 if (IS_ERR(edp->debugfs_dir)) {
1838 dev_err(edp->dev, "failed to create debugfs dir for edp!\n");
1840 debugfs_create_file("dpcd", S_IRUSR, edp->debugfs_dir,
1841 edp, &edp_dpcd_debugfs_fops);
1842 debugfs_create_file("edid", S_IRUSR, edp->debugfs_dir,
1843 edp, &edp_edid_debugfs_fops);
1844 debugfs_create_file("reg", S_IRUSR, edp->debugfs_dir,
1845 edp, &edp_reg_debugfs_fops);
1846 debugfs_create_file("psr", S_IRUSR, edp->debugfs_dir,
1847 edp, &edp_psr_debugfs_fops);
1851 dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1856 static int rockchip_edp_remove(struct platform_device *pdev)
1858 pm_runtime_disable(&pdev->dev);
1862 #if defined(CONFIG_OF)
1863 static const struct of_device_id rk32_edp_dt_ids[] = {
1864 {.compatible = "rockchip,rk32-edp", .data = (void *)SOC_COMMON},
1865 {.compatible = "rockchip,rk3399-edp-fb", .data = (void *)SOC_RK3399},
1869 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1872 static struct platform_driver rk32_edp_driver = {
1873 .probe = rk32_edp_probe,
1874 .remove = rockchip_edp_remove,
1877 .owner = THIS_MODULE,
1878 #if defined(CONFIG_OF)
1879 .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1884 static int __init rk32_edp_module_init(void)
1886 return platform_driver_register(&rk32_edp_driver);
1889 static void __exit rk32_edp_module_exit(void)
1893 fs_initcall(rk32_edp_module_init);
1894 module_exit(rk32_edp_module_exit);