drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/rockchip/cpu.h>
  24 #include <linux/rockchip/iomap.h>
  25 #include <linux/rockchip/grf.h>
  26 #include <linux/string.h>
  27 #include <linux/slab.h>
  28 #include <linux/uaccess.h>
  29
  30 #if defined(CONFIG_OF)
  31 #include <linux/of.h>
  32 #endif
  33
  34 #if defined(CONFIG_DEBUG_FS)
  35 #include <linux/fs.h>
  36 #include <linux/debugfs.h>
  37 #include <linux/seq_file.h>
  38 #endif
  39
  40 #include "rk32_dp.h"
  41
  42 /*#define EDP_BIST_MODE*/
  43 /*#define SW_LT*/
  44
  45 #define RK3368_GRF_SOC_CON4     0x410
  46
  47 static struct rk32_edp *rk32_edp;
  48
  49 static int rk32_edp_clk_enable(struct rk32_edp *edp)
  50 {
  51         int ret;
  52
  53         if (!edp->clk_on) {
  54                 if (edp->pd)
  55                         clk_prepare_enable(edp->pd);
  56                 clk_prepare_enable(edp->pclk);
  57                 clk_prepare_enable(edp->clk_edp);
  58                 ret = clk_set_rate(edp->clk_24m, 24000000);
  59                 if (ret < 0)
  60                         dev_err(edp->dev, "cannot set edp clk_24m %d\n", ret);
  61                 clk_prepare_enable(edp->clk_24m);
  62                 edp->clk_on = true;
  63         }
  64
  65         return 0;
  66 }
  67
  68 static int rk32_edp_clk_disable(struct rk32_edp *edp)
  69 {
  70         if (edp->clk_on) {
  71                 clk_disable_unprepare(edp->pclk);
  72                 clk_disable_unprepare(edp->clk_edp);
  73                 clk_disable_unprepare(edp->clk_24m);
  74                 if (edp->pd)
  75                         clk_disable_unprepare(edp->pd);
  76                 edp->clk_on = false;
  77         }
  78
  79         return 0;
  80 }
  81
  82 static int rk32_edp_pre_init(struct rk32_edp *edp)
  83 {
  84         u32 val;
  85
  86         if (cpu_is_rk3288()) {
  87                 val = GRF_EDP_REF_CLK_SEL_INTER |
  88                         (GRF_EDP_REF_CLK_SEL_INTER << 16);
  89                 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
  90
  91                 val = 0x80008000;
  92                 writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
  93                 dsb(sy);
  94                 udelay(1);
  95                 val = 0x80000000;
  96                 writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
  97                 dsb(sy);
  98                 udelay(1);
  99         } else {
 100                 val = 0x01 | (0x01 << 16);
 101                 regmap_write(edp->grf, RK3368_GRF_SOC_CON4, val);
 102
 103                 reset_control_assert(edp->rst_24m);
 104                 usleep_range(10, 20);
 105                 reset_control_deassert(edp->rst_24m);
 106         }
 107         return 0;
 108 }
 109
 110 static int rk32_edp_init_edp(struct rk32_edp *edp)
 111 {
 112         struct rk_screen *screen = &edp->screen;
 113         u32 val = 0;
 114
 115         rk_fb_get_prmry_screen(screen);
 116
 117         if (cpu_is_rk3288()) {
 118                 if (screen->lcdc_id == 1)  /*select lcdc*/
 119                         val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
 120                 else
 121                         val = EDP_SEL_VOP_LIT << 16;
 122                 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
 123         }
 124
 125         rk32_edp_reset(edp);
 126         rk32_edp_init_refclk(edp);
 127         rk32_edp_init_interrupt(edp);
 128         rk32_edp_enable_sw_function(edp);
 129         rk32_edp_init_analog_func(edp);
 130         rk32_edp_init_hpd(edp);
 131         rk32_edp_init_aux(edp);
 132
 133         return 0;
 134 }
 135
 136 #if 0
 137 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
 138 {
 139         int timeout_loop = 0;
 140
 141         rk32_edp_init_hpd(edp);
 142
 143         udelay(200);
 144
 145         while (rk32_edp_get_plug_in_status(edp) != 0) {
 146                 timeout_loop++;
 147                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 148                         dev_err(edp->dev, "failed to get hpd plug status\n");
 149                         return -ETIMEDOUT;
 150                 }
 151                 udelay(10);
 152         }
 153
 154         return 0;
 155 }
 156 #endif
 157 static int rk32_edp_read_edid(struct rk32_edp *edp)
 158 {
 159         unsigned char edid[EDID_LENGTH * 2];
 160         unsigned int extend_block = 0;
 161         unsigned char sum;
 162         unsigned char test_vector;
 163         int retval;
 164
 165         /*
 166          * EDID device address is 0x50.
 167          * However, if necessary, you must have set upper address
 168          * into E-EDID in I2C device, 0x30.
 169          */
 170
 171         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 172         retval = rk32_edp_read_byte_from_i2c(edp,
 173                 EDID_ADDR, EDID_EXTENSION_FLAG, &extend_block);
 174         if (retval < 0) {
 175                 dev_err(edp->dev, "EDID extension flag failed!\n");
 176                 return -EIO;
 177         }
 178
 179         if (extend_block > 0) {
 180                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
 181
 182                 /* Read EDID data */
 183                 retval = rk32_edp_read_bytes_from_i2c(edp,
 184                                 EDID_ADDR, EDID_HEADER,
 185                                 EDID_LENGTH, &edid[EDID_HEADER]);
 186                 if (retval != 0) {
 187                         dev_err(edp->dev, "EDID Read failed!\n");
 188                         return -EIO;
 189                 }
 190                 sum = edp_calc_edid_check_sum(edid);
 191                 if (sum != 0) {
 192                         dev_warn(edp->dev, "EDID bad checksum!\n");
 193                         return 0;
 194                 }
 195
 196                 /* Read additional EDID data */
 197                 retval = rk32_edp_read_bytes_from_i2c(edp,
 198                                 EDID_ADDR, EDID_LENGTH,
 199                                 EDID_LENGTH, &edid[EDID_LENGTH]);
 200                 if (retval != 0) {
 201                         dev_err(edp->dev, "EDID Read failed!\n");
 202                         return -EIO;
 203                 }
 204                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
 205                 if (sum != 0) {
 206                         dev_warn(edp->dev, "EDID bad checksum!\n");
 207                         return 0;
 208                 }
 209
 210                 retval = rk32_edp_read_byte_from_dpcd(edp,
 211                                 DPCD_TEST_REQUEST, &test_vector);
 212                 if (retval < 0) {
 213                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 214                         return retval;
 215                 }
 216
 217                 if (test_vector & DPCD_TEST_EDID_READ) {
 218                         retval = rk32_edp_write_byte_to_dpcd(edp,
 219                                         DPCD_TEST_EDID_CHECKSUM,
 220                                         edid[EDID_LENGTH + EDID_CHECKSUM]);
 221                         if (retval < 0) {
 222                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 223                                 return retval;
 224                         }
 225                         retval = rk32_edp_write_byte_to_dpcd(edp,
 226                                         DPCD_TEST_RESPONSE,
 227                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 228                         if (retval < 0) {
 229                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 230                                 return retval;
 231                         }
 232                 }
 233         } else {
 234                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 235
 236                 /* Read EDID data */
 237                 retval = rk32_edp_read_bytes_from_i2c(edp,
 238                                 EDID_ADDR, EDID_HEADER,
 239                                 EDID_LENGTH, &edid[EDID_HEADER]);
 240                 if (retval != 0) {
 241                         dev_err(edp->dev, "EDID Read failed!\n");
 242                         return -EIO;
 243                 }
 244                 sum = edp_calc_edid_check_sum(edid);
 245                 if (sum != 0) {
 246                         dev_warn(edp->dev, "EDID bad checksum!\n");
 247                         return 0;
 248                 }
 249
 250                 retval = rk32_edp_read_byte_from_dpcd(edp,
 251                                 DPCD_TEST_REQUEST, &test_vector);
 252                 if (retval < 0) {
 253                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 254                         return retval;
 255                 }
 256
 257                 if (test_vector & DPCD_TEST_EDID_READ) {
 258                         retval = rk32_edp_write_byte_to_dpcd(edp,
 259                                         DPCD_TEST_EDID_CHECKSUM,
 260                                         edid[EDID_CHECKSUM]);
 261                         if (retval < 0) {
 262                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 263                                 return retval;
 264                         }
 265                         retval = rk32_edp_write_byte_to_dpcd(edp,
 266                                         DPCD_TEST_RESPONSE,
 267                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 268                         if (retval < 0) {
 269                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 270                                 return retval;
 271                         }
 272                 }
 273         }
 274         fb_edid_to_monspecs(edid, &edp->specs);
 275         dev_err(edp->dev, "EDID Read success!\n");
 276         return 0;
 277 }
 278
 279 #if 0
 280 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 281 {
 282         u8 buf[12];
 283         int i;
 284         int retval;
 285
 286         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 287         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
 288         if (retval < 0)
 289                 return retval;
 290
 291         for (i = 0; i < 12; i++)
 292                 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
 293         /* Read EDID */
 294         for (i = 0; i < 3; i++) {
 295                 retval = rk32_edp_read_edid(edp);
 296                 if (retval == 0)
 297                         break;
 298         }
 299
 300         return retval;
 301 }
 302
 303
 304 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 305                                                 bool enable)
 306 {
 307         u8 data;
 308         int retval;
 309
 310         retval = rk32_edp_read_byte_from_dpcd(edp,
 311                         DPCD_LANE_CNT_SET, &data);
 312         if (retval < 0)
 313                 return retval;
 314
 315         if (enable) {
 316                 retval = rk32_edp_write_byte_to_dpcd(edp,
 317                                 DPCD_LANE_CNT_SET,
 318                                 DPCD_ENHANCED_FRAME_EN |
 319                                 DPCD_LANE_COUNT_SET(data));
 320         } else {
 321                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 322                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 323
 324                 retval = rk32_edp_write_byte_to_dpcd(edp,
 325                                 DPCD_LANE_CNT_SET,
 326                                 DPCD_LANE_COUNT_SET(data));
 327         }
 328
 329         return retval;
 330 }
 331
 332 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 333 {
 334         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 335         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 336
 337         if (enable) {
 338                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 339                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 340         } else {
 341                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 342         }*/
 343 }
 344
 345
 346 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 347 {
 348         u8 data;
 349         int retval;
 350
 351         retval = rk32_edp_read_byte_from_dpcd(edp,
 352                         DPCD_MAX_LANE_CNT, &data);
 353         if (retval < 0)
 354                 return retval;
 355
 356         return DPCD_ENHANCED_FRAME_CAP(data);
 357 }
 358
 359
 360 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 361 {
 362         /*rk32_edp_write_byte_to_dpcd(edp,
 363                         DPCD_ADDR_USER_DEFINED1, 0);
 364         rk32_edp_write_byte_to_dpcd(edp,
 365                         DPCD_ADDR_USER_DEFINED2, 0x83);
 366         rk32_edp_write_byte_to_dpcd(edp,
 367                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 368 }
 369
 370 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 371 {
 372         u8 data;
 373         int retval;
 374
 375         retval = rk32_edp_is_enhanced_mode_available(edp);
 376         if (retval < 0)
 377                 return retval;
 378
 379         data = (u8)retval;
 380         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 381         if (retval < 0)
 382                 return retval;
 383
 384         rk32_edp_enable_enhanced_mode(edp, data);
 385
 386         return 0;
 387 }
 388 #endif
 389
 390 #if defined(SW_LT)
 391 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 392 {
 393         int retval;
 394
 395         rk32_edp_set_training_pattern(edp, DP_NONE);
 396
 397         retval = rk32_edp_write_byte_to_dpcd(edp,
 398                         DPCD_TRAINING_PATTERN_SET,
 399                         DPCD_TRAINING_PATTERN_DISABLED);
 400         if (retval < 0)
 401                 return retval;
 402
 403         return 0;
 404 }
 405
 406 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 407                                         int pre_emphasis, int lane)
 408 {
 409         switch (lane) {
 410         case 0:
 411                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 412                 break;
 413         case 1:
 414                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 415                 break;
 416
 417         case 2:
 418                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 419                 break;
 420
 421         case 3:
 422                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 423                 break;
 424         }
 425 }
 426
 427 static int rk32_edp_link_start(struct rk32_edp *edp)
 428 {
 429         u8 buf[4];
 430         int lane;
 431         int lane_count;
 432         int retval;
 433
 434         lane_count = edp->link_train.lane_count;
 435
 436         edp->link_train.lt_state = LT_CLK_RECOVERY;
 437         edp->link_train.eq_loop = 0;
 438
 439         for (lane = 0; lane < lane_count; lane++)
 440                 edp->link_train.cr_loop[lane] = 0;
 441
 442         /* Set sink to D0 (Sink Not Ready) mode. */
 443         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
 444                                 DPCD_SET_POWER_STATE_D0);
 445         if (retval < 0) {
 446                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 447                 return retval;
 448         }
 449
 450         /* Set link rate and count as you want to establish*/
 451         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 452         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 453
 454         /* Setup RX configuration */
 455         buf[0] = edp->link_train.link_rate;
 456         buf[1] = edp->link_train.lane_count;
 457         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
 458                                         2, buf);
 459         if (retval < 0) {
 460                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 461                 return retval;
 462         }
 463
 464         /* Set TX pre-emphasis to level1 */
 465         for (lane = 0; lane < lane_count; lane++)
 466                 rk32_edp_set_lane_lane_pre_emphasis(edp,
 467                         PRE_EMPHASIS_LEVEL_1, lane);
 468
 469         /* Set training pattern 1 */
 470         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 471
 472         /* Set RX training pattern */
 473         retval = rk32_edp_write_byte_to_dpcd(edp,
 474                         DPCD_TRAINING_PATTERN_SET,
 475                         DPCD_SCRAMBLING_DISABLED |
 476                         DPCD_TRAINING_PATTERN_1);
 477         if (retval < 0) {
 478                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 479                 return retval;
 480         }
 481
 482         for (lane = 0; lane < lane_count; lane++)
 483                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 484                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 485         retval = rk32_edp_write_bytes_to_dpcd(edp,
 486                         DPCD_TRAINING_LANE0_SET,
 487                         lane_count, buf);
 488         if (retval < 0) {
 489                 dev_err(edp->dev, "failed to set training lane!\n");
 490                 return retval;
 491         }
 492
 493         return 0;
 494 }
 495
 496 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 497 {
 498         int shift = (lane & 1) * 4;
 499         u8 link_value = link_status[lane>>1];
 500
 501         return (link_value >> shift) & 0xf;
 502 }
 503
 504 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 505 {
 506         int lane;
 507         u8 lane_status;
 508
 509         for (lane = 0; lane < lane_count; lane++) {
 510                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 511                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 512                         return -EINVAL;
 513         }
 514         return 0;
 515 }
 516
 517 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 518 {
 519         int lane;
 520         u8 lane_align;
 521         u8 lane_status;
 522
 523         lane_align = link_align[2];
 524         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 525                 return -EINVAL;
 526
 527         for (lane = 0; lane < lane_count; lane++) {
 528                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 529                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 530                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 531                         return -EINVAL;
 532         }
 533
 534         return 0;
 535 }
 536
 537 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 538                                                         int lane)
 539 {
 540         int shift = (lane & 1) * 4;
 541         u8 link_value = adjust_request[lane>>1];
 542
 543         return (link_value >> shift) & 0x3;
 544 }
 545
 546 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 547                                         u8 adjust_request[2],
 548                                         int lane)
 549 {
 550         int shift = (lane & 1) * 4;
 551         u8 link_value = adjust_request[lane>>1];
 552
 553         return ((link_value >> shift) & 0xc) >> 2;
 554 }
 555
 556 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 557                                         u8 training_lane_set, int lane)
 558 {
 559         switch (lane) {
 560         case 0:
 561                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 562                 break;
 563         case 1:
 564                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 565                 break;
 566
 567         case 2:
 568                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 569                 break;
 570
 571         case 3:
 572                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 573                 break;
 574         }
 575 }
 576
 577 static unsigned int rk32_edp_get_lane_link_training(
 578                                 struct rk32_edp *edp,
 579                                 int lane)
 580 {
 581         u32 reg;
 582
 583         switch (lane) {
 584         case 0:
 585                 reg = rk32_edp_get_lane0_link_training(edp);
 586                 break;
 587         case 1:
 588                 reg = rk32_edp_get_lane1_link_training(edp);
 589                 break;
 590         case 2:
 591                 reg = rk32_edp_get_lane2_link_training(edp);
 592                 break;
 593         case 3:
 594                 reg = rk32_edp_get_lane3_link_training(edp);
 595                 break;
 596         }
 597
 598         return reg;
 599 }
 600
 601 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 602 {
 603         rk32_edp_training_pattern_dis(edp);
 604
 605         edp->link_train.lt_state = FAILED;
 606 }
 607
 608 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 609 {
 610         u8 link_status[2];
 611         int lane;
 612         int lane_count;
 613
 614         u8 adjust_request[2];
 615         u8 voltage_swing;
 616         u8 pre_emphasis;
 617         u8 training_lane;
 618         int retval;
 619
 620         udelay(100);
 621
 622         lane_count = edp->link_train.lane_count;
 623
 624         retval = rk32_edp_read_bytes_from_dpcd(edp,
 625                         DPCD_LANE0_1_STATUS,
 626                         2, link_status);
 627         if (retval < 0) {
 628                 dev_err(edp->dev, "failed to read lane status!\n");
 629                 return retval;
 630         }
 631
 632         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 633                 /* set training pattern 2 for EQ */
 634                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 635
 636                 for (lane = 0; lane < lane_count; lane++) {
 637                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 638                                         DPCD_ADJUST_REQUEST_LANE0_1,
 639                                         2, adjust_request);
 640                         if (retval < 0) {
 641                                 dev_err(edp->dev, "failed to read adjust request!\n");
 642                                 return retval;
 643                         }
 644
 645                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 646                                                         adjust_request, lane);
 647                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 648                                                         adjust_request, lane);
 649                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 650                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 651
 652                         if (voltage_swing == VOLTAGE_LEVEL_3)
 653                                 training_lane |= DPCD_MAX_SWING_REACHED;
 654                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 655                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 656
 657                         edp->link_train.training_lane[lane] = training_lane;
 658
 659                         rk32_edp_set_lane_link_training(edp,
 660                                 edp->link_train.training_lane[lane],
 661                                 lane);
 662                 }
 663
 664                 retval = rk32_edp_write_byte_to_dpcd(edp,
 665                                 DPCD_TRAINING_PATTERN_SET,
 666                                 DPCD_SCRAMBLING_DISABLED |
 667                                 DPCD_TRAINING_PATTERN_2);
 668                 if (retval < 0) {
 669                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 670                         return retval;
 671                 }
 672
 673                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 674                                 DPCD_TRAINING_LANE0_SET,
 675                                 lane_count,
 676                                 edp->link_train.training_lane);
 677                 if (retval < 0) {
 678                         dev_err(edp->dev, "failed to set training lane!\n");
 679                         return retval;
 680                 }
 681
 682                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 683                 edp->link_train.lt_state = LT_EQ_TRAINING;
 684         } else {
 685                 for (lane = 0; lane < lane_count; lane++) {
 686                         training_lane = rk32_edp_get_lane_link_training(
 687                                                         edp, lane);
 688                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 689                                         DPCD_ADJUST_REQUEST_LANE0_1,
 690                                         2, adjust_request);
 691                         if (retval < 0) {
 692                                 dev_err(edp->dev, "failed to read adjust request!\n");
 693                                 return retval;
 694                         }
 695
 696                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 697                                                         adjust_request, lane);
 698                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 699                                                         adjust_request, lane);
 700
 701                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 702                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 703                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 704                                 goto reduce_link_rate;
 705                         }
 706
 707                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 708                                         voltage_swing) &&
 709                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 710                                         pre_emphasis)) {
 711                                 edp->link_train.cr_loop[lane]++;
 712                                 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
 713                                         dev_err(edp->dev, "CR Max loop\n");
 714                                         goto reduce_link_rate;
 715                                 }
 716                         }
 717
 718                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 719                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 720
 721                         if (voltage_swing == VOLTAGE_LEVEL_3)
 722                                 training_lane |= DPCD_MAX_SWING_REACHED;
 723                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 724                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 725
 726                         edp->link_train.training_lane[lane] = training_lane;
 727
 728                         rk32_edp_set_lane_link_training(edp,
 729                                 edp->link_train.training_lane[lane], lane);
 730                 }
 731
 732                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 733                                 DPCD_TRAINING_LANE0_SET,
 734                                 lane_count,
 735                                 edp->link_train.training_lane);
 736                 if (retval < 0) {
 737                         dev_err(edp->dev, "failed to set training lane!\n");
 738                         return retval;
 739                 }
 740         }
 741
 742         return 0;
 743
 744 reduce_link_rate:
 745         rk32_edp_reduce_link_rate(edp);
 746         return -EIO;
 747 }
 748
 749 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 750 {
 751         u8 link_status[2];
 752         u8 link_align[3];
 753         int lane;
 754         int lane_count;
 755         u32 reg;
 756
 757         u8 adjust_request[2];
 758         u8 voltage_swing;
 759         u8 pre_emphasis;
 760         u8 training_lane;
 761         int retval;
 762
 763         udelay(400);
 764
 765         lane_count = edp->link_train.lane_count;
 766
 767         retval = rk32_edp_read_bytes_from_dpcd(edp,
 768                         DPCD_LANE0_1_STATUS,
 769                         2, link_status);
 770         if (retval < 0) {
 771                 dev_err(edp->dev, "failed to read lane status!\n");
 772                 return retval;
 773         }
 774
 775         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 776                 link_align[0] = link_status[0];
 777                 link_align[1] = link_status[1];
 778
 779                 retval = rk32_edp_read_byte_from_dpcd(edp,
 780                                 DPCD_LANE_ALIGN_STATUS_UPDATED,
 781                                 &link_align[2]);
 782                 if (retval < 0) {
 783                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 784                         return retval;
 785                 }
 786
 787                 for (lane = 0; lane < lane_count; lane++) {
 788                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 789                                         DPCD_ADJUST_REQUEST_LANE0_1,
 790                                         2, adjust_request);
 791                         if (retval < 0) {
 792                                 dev_err(edp->dev, "failed to read adjust request!\n");
 793                                 return retval;
 794                         }
 795
 796                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 797                                                         adjust_request, lane);
 798                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 799                                                         adjust_request, lane);
 800                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 801                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 802
 803                         if (voltage_swing == VOLTAGE_LEVEL_3)
 804                                 training_lane |= DPCD_MAX_SWING_REACHED;
 805                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 806                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 807
 808                         edp->link_train.training_lane[lane] = training_lane;
 809                 }
 810
 811                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 812                         /* traing pattern Set to Normal */
 813                         retval = rk32_edp_training_pattern_dis(edp);
 814                         if (retval < 0) {
 815                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 816                                 return retval;
 817                         }
 818
 819                         dev_info(edp->dev, "Link Training success!\n");
 820
 821                         rk32_edp_get_link_bandwidth(edp, &reg);
 822                         edp->link_train.link_rate = reg;
 823                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 824                                 edp->link_train.link_rate);
 825
 826                         rk32_edp_get_lane_count(edp, &reg);
 827                         edp->link_train.lane_count = reg;
 828                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 829                                 edp->link_train.lane_count);
 830
 831                         edp->link_train.lt_state = FINISHED;
 832                 } else {
 833                         /* not all locked */
 834                         edp->link_train.eq_loop++;
 835
 836                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 837                                 dev_err(edp->dev, "EQ Max loop\n");
 838                                 goto reduce_link_rate;
 839                         }
 840
 841                         for (lane = 0; lane < lane_count; lane++)
 842                                 rk32_edp_set_lane_link_training(edp,
 843                                         edp->link_train.training_lane[lane],
 844                                         lane);
 845
 846                         retval = rk32_edp_write_bytes_to_dpcd(edp,
 847                                         DPCD_TRAINING_LANE0_SET,
 848                                         lane_count,
 849                                         edp->link_train.training_lane);
 850                         if (retval < 0) {
 851                                 dev_err(edp->dev, "failed to set training lane!\n");
 852                                 return retval;
 853                         }
 854                 }
 855         } else {
 856                 goto reduce_link_rate;
 857         }
 858
 859         return 0;
 860
 861 reduce_link_rate:
 862         rk32_edp_reduce_link_rate(edp);
 863         return -EIO;
 864 }
 865 #endif
 866 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 867                                         u8 *bandwidth)
 868 {
 869         u8 data;
 870         int retval = 0;
 871
 872         /*
 873          * For DP rev.1.1, Maximum link rate of Main Link lanes
 874          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 875          */
 876         retval = rk32_edp_read_byte_from_dpcd(edp,
 877                         DPCD_MAX_LINK_RATE, &data);
 878         if (retval < 0)
 879                 *bandwidth = 0;
 880         else
 881                 *bandwidth = data;
 882         return retval;
 883
 884 }
 885
 886 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 887                                         u8 *lane_count)
 888 {
 889         u8 data;
 890         int retval;
 891
 892         /*
 893          * For DP rev.1.1, Maximum number of Main Link lanes
 894          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 895          */
 896         retval = rk32_edp_read_byte_from_dpcd(edp,
 897                         DPCD_MAX_LANE_CNT, &data);
 898         if (retval < 0)
 899                 *lane_count = 0;
 900         else
 901                 *lane_count = DPCD_MAX_LANE_COUNT(data);
 902         return retval;
 903 }
 904
 905 static int rk32_edp_init_training(struct rk32_edp *edp)
 906 {
 907         int retval;
 908
 909         /*
 910          * MACRO_RST must be applied after the PLL_LOCK to avoid
 911          * the DP inter pair skew issue for at least 10 us
 912          */
 913         rk32_edp_reset_macro(edp);
 914
 915
 916         retval = rk32_edp_get_max_rx_bandwidth(edp,
 917                                 &edp->link_train.link_rate);
 918         retval = rk32_edp_get_max_rx_lane_count(edp,
 919                                 &edp->link_train.lane_count);
 920         dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
 921                         edp->link_train.link_rate * 27/100,
 922                         edp->link_train.link_rate*27%100,
 923                         edp->link_train.lane_count);
 924
 925         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 926            (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 927                 dev_warn(edp->dev, "Rx Max Link Rate is abnormal :%x !"
 928                         "use default link rate:%d.%dGps\n",
 929                         edp->link_train.link_rate,
 930                         edp->video_info.link_rate*27/100,
 931                         edp->video_info.link_rate*27%100);
 932                 edp->link_train.link_rate = edp->video_info.link_rate;
 933         }
 934
 935         if (edp->link_train.lane_count == 0) {
 936                 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !"
 937                         "use default lanes:%d\n",
 938                         edp->link_train.lane_count,
 939                         edp->video_info.lane_count);
 940                 edp->link_train.lane_count = edp->video_info.lane_count;
 941         }
 942
 943         rk32_edp_analog_power_ctr(edp, 1);
 944
 945
 946         return 0;
 947 }
 948
 949 #if defined(SW_LT)
 950 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
 951 {
 952         int retval = 0;
 953         int training_finished = 0;
 954
 955         edp->link_train.lt_state = LT_START;
 956
 957         /* Process here */
 958         while (!training_finished) {
 959                 switch (edp->link_train.lt_state) {
 960                 case LT_START:
 961                         retval = rk32_edp_link_start(edp);
 962                         if (retval)
 963                                 dev_err(edp->dev, "LT Start failed\n");
 964                         break;
 965                 case LT_CLK_RECOVERY:
 966                         retval = rk32_edp_process_clock_recovery(edp);
 967                         if (retval)
 968                                 dev_err(edp->dev, "LT CR failed\n");
 969                         break;
 970                 case LT_EQ_TRAINING:
 971                         retval = rk32_edp_process_equalizer_training(edp);
 972                         if (retval)
 973                                 dev_err(edp->dev, "LT EQ failed\n");
 974                         break;
 975                 case FINISHED:
 976                         training_finished = 1;
 977                         break;
 978                 case FAILED:
 979                         return -EREMOTEIO;
 980                 }
 981         }
 982
 983         return retval;
 984 }
 985
 986 #else
 987 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
 988 {
 989         u32 cnt = 50;
 990         u32 val;
 991         /* Set link rate and count as you want to establish*/
 992         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 993         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 994         rk32_edp_hw_link_training_en(edp);
 995         val = rk32_edp_wait_hw_lt_done(edp);
 996         while (val) {
 997                 if (cnt-- <= 0) {
 998                         dev_err(edp->dev, "hw lt timeout");
 999                         return -ETIMEDOUT;
1000                 }
1001                 mdelay(1);
1002                 val = rk32_edp_wait_hw_lt_done(edp);
1003         }
1004
1005         val = rk32_edp_get_hw_lt_status(edp);
1006         if (val)
1007                 dev_err(edp->dev, "hw lt err:%d\n", val);
1008         return val;
1009
1010 }
1011 #endif
1012
1013 static int rk32_edp_set_link_train(struct rk32_edp *edp)
1014 {
1015         int retval;
1016
1017         retval = rk32_edp_init_training(edp);
1018         if (retval < 0)
1019                 dev_err(edp->dev, "DP LT init failed!\n");
1020 #if defined(SW_LT)
1021         retval = rk32_edp_sw_link_training(edp);
1022 #else
1023         retval = rk32_edp_hw_link_training(edp);
1024 #endif
1025
1026         return retval;
1027 }
1028
1029 static int rk32_edp_config_video(struct rk32_edp *edp,
1030                         struct video_info *video_info)
1031 {
1032         int retval = 0;
1033         int timeout_loop = 0;
1034         int done_count = 0;
1035
1036         rk32_edp_config_video_slave_mode(edp, video_info);
1037
1038         rk32_edp_set_video_color_format(edp, video_info->color_depth,
1039                         video_info->color_space,
1040                         video_info->dynamic_range,
1041                         video_info->ycbcr_coeff);
1042
1043         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
1044                 dev_err(edp->dev, "PLL is not locked yet.\n");
1045                 return -EINVAL;
1046         }
1047
1048         for (;;) {
1049                 timeout_loop++;
1050                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
1051                         break;
1052                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1053                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1054                         return -ETIMEDOUT;
1055                 }
1056
1057                 udelay(1);
1058         }
1059
1060         /* Set to use the register calculated M/N video */
1061         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1062
1063         /* For video bist, Video timing must be generated by register */
1064 #ifndef EDP_BIST_MODE
1065         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
1066 #endif
1067         /* Disable video mute */
1068         rk32_edp_enable_video_mute(edp, 0);
1069
1070         /* Configure video slave mode */
1071         rk32_edp_enable_video_master(edp, 0);
1072
1073         /* Enable video */
1074         rk32_edp_start_video(edp);
1075
1076         timeout_loop = 0;
1077
1078         for (;;) {
1079                 timeout_loop++;
1080                 if (rk32_edp_is_video_stream_on(edp) == 0) {
1081                         done_count++;
1082                         if (done_count > 10)
1083                                 break;
1084                 } else if (done_count) {
1085                         done_count = 0;
1086                 }
1087                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1088                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1089                         return -ETIMEDOUT;
1090                 }
1091
1092                 mdelay(1);
1093         }
1094
1095         if (retval != 0)
1096                 dev_err(edp->dev, "Video stream is not detected!\n");
1097
1098         return retval;
1099 }
1100
1101 #if 0
1102 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1103 {
1104         u8 data;
1105         int retval;
1106
1107         if (enable) {
1108                 rk32_edp_enable_scrambling(edp);
1109
1110                 retval = rk32_edp_read_byte_from_dpcd(edp,
1111                                 DPCD_TRAINING_PATTERN_SET,
1112                                 &data);
1113                 if (retval < 0)
1114                         return retval;
1115
1116                 retval = rk32_edp_write_byte_to_dpcd(edp,
1117                                 DPCD_TRAINING_PATTERN_SET,
1118                                 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1119                 if (retval < 0)
1120                         return retval;
1121         } else {
1122                 rk32_edp_disable_scrambling(edp);
1123
1124                 retval = rk32_edp_read_byte_from_dpcd(edp,
1125                                 DPCD_TRAINING_PATTERN_SET,
1126                                 &data);
1127                 if (retval < 0)
1128                         return retval;
1129
1130                 retval = rk32_edp_write_byte_to_dpcd(edp,
1131                                 DPCD_TRAINING_PATTERN_SET,
1132                                 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1133                 if (retval < 0)
1134                         return retval;
1135         }
1136
1137         return 0;
1138 }
1139 #endif
1140
1141 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1142 {
1143         struct rk32_edp *edp = arg;
1144         enum dp_irq_type irq_type;
1145
1146         irq_type = rk32_edp_get_irq_type(edp);
1147         switch (irq_type) {
1148         case DP_IRQ_TYPE_HP_CABLE_IN:
1149                 dev_info(edp->dev, "Received irq - cable in\n");
1150                 rk32_edp_clear_hotplug_interrupts(edp);
1151                 break;
1152         case DP_IRQ_TYPE_HP_CABLE_OUT:
1153                 dev_info(edp->dev, "Received irq - cable out\n");
1154                 rk32_edp_clear_hotplug_interrupts(edp);
1155                 break;
1156         case DP_IRQ_TYPE_HP_CHANGE:
1157                 /*
1158                  * We get these change notifications once in a while, but there
1159                  * is nothing we can do with them. Just ignore it for now and
1160                  * only handle cable changes.
1161                  */
1162                 dev_info(edp->dev, "Received irq - hotplug change; ignoring.\n");
1163                 rk32_edp_clear_hotplug_interrupts(edp);
1164                 break;
1165         default:
1166                 dev_err(edp->dev, "Received irq - unknown type!\n");
1167                 break;
1168         }
1169         return IRQ_HANDLED;
1170 }
1171
1172 static int rk32_edp_enable(void)
1173 {
1174         int ret = 0;
1175         struct rk32_edp *edp = rk32_edp;
1176
1177
1178         rk32_edp_clk_enable(edp);
1179         rk32_edp_pre_init(edp);
1180         rk32_edp_init_edp(edp);
1181         enable_irq(edp->irq);
1182         /*ret = rk32_edp_handle_edid(edp);
1183         if (ret) {
1184                 dev_err(edp->dev, "unable to handle edid\n");
1185                 //goto out;
1186         }
1187
1188
1189         ret = rk32_edp_enable_scramble(edp, 0);
1190         if (ret) {
1191                 dev_err(edp->dev, "unable to set scramble\n");
1192                 //goto out;
1193         }
1194
1195         ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1196         if (ret) {
1197                 dev_err(edp->dev, "unable to set enhanced mode\n");
1198                 //goto out;
1199         }
1200         rk32_edp_enable_enhanced_mode(edp, 1);*/
1201
1202         ret = rk32_edp_set_link_train(edp);
1203         if (ret)
1204                 dev_err(edp->dev, "link train failed!\n");
1205         else
1206                 dev_info(edp->dev, "link training success.\n");
1207
1208         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1209         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1210         rk32_edp_init_video(edp);
1211
1212 #ifdef EDP_BIST_MODE
1213         rk32_edp_bist_cfg(edp);
1214 #endif
1215         ret = rk32_edp_config_video(edp, &edp->video_info);
1216         if (ret)
1217                 dev_err(edp->dev, "unable to config video\n");
1218
1219         return ret;
1220
1221
1222
1223 }
1224
1225 static int  rk32_edp_disable(void)
1226 {
1227         struct rk32_edp *edp = rk32_edp;
1228
1229         disable_irq(edp->irq);
1230         rk32_edp_reset(edp);
1231         rk32_edp_analog_power_ctr(edp, 0);
1232         rk32_edp_clk_disable(edp);
1233
1234         return 0;
1235 }
1236
1237
1238 static struct rk_fb_trsm_ops trsm_edp_ops = {
1239         .enable = rk32_edp_enable,
1240         .disable = rk32_edp_disable,
1241 };
1242
1243
1244 #if defined(CONFIG_DEBUG_FS)
1245
1246 static int edp_dpcd_debugfs_show(struct seq_file *s, void *v)
1247 {
1248         int i = 0;
1249         unsigned char buf[12];
1250         struct rk32_edp *edp = s->private;
1251         if (!edp) {
1252                 dev_err(edp->dev, "no edp device!\n");
1253                 return -ENODEV;
1254         }
1255
1256
1257         rk32_edp_read_bytes_from_dpcd(edp,
1258                         DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
1259         for (i = 0; i < 12; i++)
1260                 seq_printf(s, "0x%02x>>0x%02x\n", 0x210 + i, buf[i]);
1261         return 0;
1262 }
1263
1264 static ssize_t edp_dpcd_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos)
1265 {
1266         return count;
1267 }
1268
1269 static int edp_edid_debugfs_show(struct seq_file *s, void *v)
1270 {
1271         struct rk32_edp *edp = s->private;
1272         if (!edp) {
1273                 dev_err(edp->dev, "no edp device!\n");
1274                 return -ENODEV;
1275         }
1276         rk32_edp_read_edid(edp);
1277         seq_puts(s, "edid");
1278         return 0;
1279 }
1280
1281 static ssize_t edp_edid_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos)
1282 {
1283         struct rk32_edp *edp =  ((struct seq_file *)file->private_data)->private;
1284         if (!edp) {
1285                 dev_err(edp->dev, "no edp device!\n");
1286                 return -ENODEV;
1287         }
1288         rk32_edp_disable();
1289         rk32_edp_enable();
1290         return count;
1291 }
1292
1293 static int edp_reg_debugfs_show(struct seq_file *s, void *v)
1294 {
1295         int i = 0;
1296         struct rk32_edp *edp = s->private;
1297         if (!edp) {
1298                 dev_err(edp->dev, "no edp device!\n");
1299                 return -ENODEV;
1300         }
1301
1302         for (i = 0; i < 0x284; i++) {
1303                 if (!(i%4))
1304                         seq_printf(s, "\n%08x:  ", i*4);
1305                 seq_printf(s, "%08x ", readl(edp->regs + i*4));
1306         }
1307         return 0;
1308 }
1309
1310 static ssize_t edp_reg_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos)
1311 {
1312         return count;
1313 }
1314
1315 #define EDP_DEBUG_ENTRY(name) \
1316 static int edp_##name##_debugfs_open(struct inode *inode, struct file *file) \
1317 { \
1318         return single_open(file, edp_##name##_debugfs_show, inode->i_private); \
1319 } \
1320 \
1321 static const struct file_operations edp_##name##_debugfs_fops = { \
1322         .owner = THIS_MODULE, \
1323         .open = edp_##name##_debugfs_open, \
1324         .read = seq_read, \
1325         .write = edp_##name##_write,    \
1326         .llseek = seq_lseek, \
1327         .release = single_release, \
1328 }
1329
1330 EDP_DEBUG_ENTRY(dpcd);
1331 EDP_DEBUG_ENTRY(edid);
1332 EDP_DEBUG_ENTRY(reg);
1333 #endif
1334
1335 static int rk32_edp_probe(struct platform_device *pdev)
1336 {
1337         struct rk32_edp *edp;
1338         struct resource *res;
1339         struct device_node *np = pdev->dev.of_node;
1340         int ret;
1341
1342         if (!np) {
1343                 dev_err(&pdev->dev, "Missing device tree node.\n");
1344                 return -EINVAL;
1345         }
1346
1347         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1348         if (!edp) {
1349                 dev_err(&pdev->dev, "no memory for state\n");
1350                 return -ENOMEM;
1351         }
1352         edp->dev = &pdev->dev;
1353         edp->video_info.h_sync_polarity = 0;
1354         edp->video_info.v_sync_polarity = 0;
1355         edp->video_info.interlaced      = 0;
1356         edp->video_info.color_space     = CS_RGB;
1357         edp->video_info.dynamic_range   = VESA;
1358         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1359         edp->video_info.color_depth     = COLOR_8;
1360
1361         edp->video_info.link_rate       = LINK_RATE_1_62GBPS;
1362         edp->video_info.lane_count      = LANE_CNT4;
1363         rk_fb_get_prmry_screen(&edp->screen);
1364         if (edp->screen.type != SCREEN_EDP) {
1365                 dev_err(&pdev->dev, "screen is not edp!\n");
1366                 return -EINVAL;
1367         }
1368         platform_set_drvdata(pdev, edp);
1369         dev_set_name(edp->dev, "rk32-edp");
1370
1371         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1372         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1373         if (IS_ERR(edp->regs)) {
1374                 dev_err(&pdev->dev, "ioremap reg failed\n");
1375                 return PTR_ERR(edp->regs);
1376         }
1377
1378         edp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1379         if (IS_ERR(edp->grf)) {
1380                 dev_err(&pdev->dev, "can't find rockchip,grf property\n");
1381                 return PTR_ERR(edp->grf);
1382         }
1383
1384         edp->pd = devm_clk_get(&pdev->dev, "pd_edp");
1385         if (IS_ERR(edp->pd)) {
1386                 dev_err(&pdev->dev, "cannot get pd\n");
1387                 edp->pd = NULL;
1388         }
1389
1390         edp->clk_edp = devm_clk_get(&pdev->dev, "clk_edp");
1391         if (IS_ERR(edp->clk_edp)) {
1392                 dev_err(&pdev->dev, "cannot get clk_edp\n");
1393                 return PTR_ERR(edp->clk_edp);
1394         }
1395
1396         edp->clk_24m = devm_clk_get(&pdev->dev, "clk_edp_24m");
1397         if (IS_ERR(edp->clk_24m)) {
1398                 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1399                 return PTR_ERR(edp->clk_24m);
1400         }
1401
1402         edp->pclk = devm_clk_get(&pdev->dev, "pclk_edp");
1403         if (IS_ERR(edp->pclk)) {
1404                 dev_err(&pdev->dev, "cannot get pclk\n");
1405                 return PTR_ERR(edp->pclk);
1406         }
1407
1408         /*edp 24m need sorft reset*/
1409         edp->rst_24m = devm_reset_control_get(&pdev->dev, "edp_24m");
1410         if (IS_ERR(edp->rst_24m)) {
1411                 dev_err(&pdev->dev, "failed to get reset\n");
1412                 return PTR_ERR(edp->rst_24m);
1413         }
1414
1415         rk32_edp_clk_enable(edp);
1416         if (!support_uboot_display())
1417                 rk32_edp_pre_init(edp);
1418         edp->irq = platform_get_irq(pdev, 0);
1419         if (edp->irq < 0) {
1420                 dev_err(&pdev->dev, "cannot find IRQ\n");
1421                 return edp->irq;
1422         }
1423         ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1424                         dev_name(&pdev->dev), edp);
1425         if (ret) {
1426                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1427                 return ret;
1428         }
1429         disable_irq_nosync(edp->irq);
1430         if (!support_uboot_display())
1431                 rk32_edp_clk_disable(edp);
1432         rk32_edp = edp;
1433         rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1434 #if defined(CONFIG_DEBUG_FS)
1435         edp->debugfs_dir = debugfs_create_dir("edp", NULL);
1436         if (IS_ERR(edp->debugfs_dir)) {
1437                 dev_err(edp->dev, "failed to create debugfs dir for edp!\n");
1438         } else {
1439                 debugfs_create_file("dpcd", S_IRUSR, edp->debugfs_dir,
1440                                         edp, &edp_dpcd_debugfs_fops);
1441                 debugfs_create_file("edid", S_IRUSR, edp->debugfs_dir,
1442                                         edp, &edp_edid_debugfs_fops);
1443                 debugfs_create_file("reg", S_IRUSR, edp->debugfs_dir,
1444                                         edp, &edp_reg_debugfs_fops);
1445         }
1446
1447 #endif
1448         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1449
1450         return 0;
1451 }
1452
1453 static void rk32_edp_shutdown(struct platform_device *pdev)
1454 {
1455
1456 }
1457
1458 #if defined(CONFIG_OF)
1459 static const struct of_device_id rk32_edp_dt_ids[] = {
1460         {.compatible = "rockchip,rk32-edp",},
1461         {}
1462 };
1463
1464 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1465 #endif
1466
1467 static struct platform_driver rk32_edp_driver = {
1468         .probe = rk32_edp_probe,
1469         .driver = {
1470                    .name = "rk32-edp",
1471                    .owner = THIS_MODULE,
1472 #if defined(CONFIG_OF)
1473                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1474 #endif
1475         },
1476         .shutdown = rk32_edp_shutdown,
1477 };
1478
1479 static int __init rk32_edp_module_init(void)
1480 {
1481         return platform_driver_register(&rk32_edp_driver);
1482 }
1483
1484 static void __exit rk32_edp_module_exit(void)
1485 {
1486
1487 }
1488
1489 fs_initcall(rk32_edp_module_init);
1490 module_exit(rk32_edp_module_exit);