2 * DisplayPort driver for rk32xx
4 * Copyright (C) ROCKCHIP, Inc.
5 *Author:yxj<yxj@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/rockchip/cpu.h>
24 #include <linux/rockchip/iomap.h>
25 #include <linux/rockchip/grf.h>
26 #include <linux/string.h>
27 #include <linux/slab.h>
28 #include <linux/uaccess.h>
30 #if defined(CONFIG_OF)
34 #if defined(CONFIG_DEBUG_FS)
36 #include <linux/debugfs.h>
37 #include <linux/seq_file.h>
42 /*#define EDP_BIST_MODE*/
45 #define RK3368_GRF_SOC_CON4 0x410
47 static struct rk32_edp *rk32_edp;
49 static int rk32_edp_clk_enable(struct rk32_edp *edp)
55 clk_prepare_enable(edp->pd);
56 clk_prepare_enable(edp->pclk);
57 clk_prepare_enable(edp->clk_edp);
58 ret = clk_set_rate(edp->clk_24m, 24000000);
60 dev_err(edp->dev, "cannot set edp clk_24m %d\n", ret);
61 clk_prepare_enable(edp->clk_24m);
68 static int rk32_edp_clk_disable(struct rk32_edp *edp)
71 clk_disable_unprepare(edp->pclk);
72 clk_disable_unprepare(edp->clk_edp);
73 clk_disable_unprepare(edp->clk_24m);
75 clk_disable_unprepare(edp->pd);
82 static int rk32_edp_pre_init(struct rk32_edp *edp)
86 if (cpu_is_rk3288()) {
87 val = GRF_EDP_REF_CLK_SEL_INTER |
88 (GRF_EDP_REF_CLK_SEL_INTER << 16);
89 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
92 writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
96 writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
100 val = 0x01 | (0x01 << 16);
101 regmap_write(edp->grf, RK3368_GRF_SOC_CON4, val);
103 reset_control_assert(edp->rst_24m);
104 usleep_range(10, 20);
105 reset_control_deassert(edp->rst_24m);
110 static int rk32_edp_init_edp(struct rk32_edp *edp)
112 struct rk_screen *screen = &edp->screen;
115 rk_fb_get_prmry_screen(screen);
117 if (cpu_is_rk3288()) {
118 if (screen->lcdc_id == 1) /*select lcdc*/
119 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
121 val = EDP_SEL_VOP_LIT << 16;
122 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
126 rk32_edp_init_refclk(edp);
127 rk32_edp_init_interrupt(edp);
128 rk32_edp_enable_sw_function(edp);
129 rk32_edp_init_analog_func(edp);
130 rk32_edp_init_hpd(edp);
131 rk32_edp_init_aux(edp);
137 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
139 int timeout_loop = 0;
141 rk32_edp_init_hpd(edp);
145 while (rk32_edp_get_plug_in_status(edp) != 0) {
147 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
148 dev_err(edp->dev, "failed to get hpd plug status\n");
157 static int rk32_edp_read_edid(struct rk32_edp *edp)
159 unsigned char edid[EDID_LENGTH * 2];
160 unsigned int extend_block = 0;
162 unsigned char test_vector;
166 * EDID device address is 0x50.
167 * However, if necessary, you must have set upper address
168 * into E-EDID in I2C device, 0x30.
171 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
172 retval = rk32_edp_read_byte_from_i2c(edp,
173 EDID_ADDR, EDID_EXTENSION_FLAG, &extend_block);
175 dev_err(edp->dev, "EDID extension flag failed!\n");
179 if (extend_block > 0) {
180 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
183 retval = rk32_edp_read_bytes_from_i2c(edp,
184 EDID_ADDR, EDID_HEADER,
185 EDID_LENGTH, &edid[EDID_HEADER]);
187 dev_err(edp->dev, "EDID Read failed!\n");
190 sum = edp_calc_edid_check_sum(edid);
192 dev_warn(edp->dev, "EDID bad checksum!\n");
196 /* Read additional EDID data */
197 retval = rk32_edp_read_bytes_from_i2c(edp,
198 EDID_ADDR, EDID_LENGTH,
199 EDID_LENGTH, &edid[EDID_LENGTH]);
201 dev_err(edp->dev, "EDID Read failed!\n");
204 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
206 dev_warn(edp->dev, "EDID bad checksum!\n");
210 retval = rk32_edp_read_byte_from_dpcd(edp,
211 DPCD_TEST_REQUEST, &test_vector);
213 dev_err(edp->dev, "DPCD EDID Read failed!\n");
217 if (test_vector & DPCD_TEST_EDID_READ) {
218 retval = rk32_edp_write_byte_to_dpcd(edp,
219 DPCD_TEST_EDID_CHECKSUM,
220 edid[EDID_LENGTH + EDID_CHECKSUM]);
222 dev_err(edp->dev, "DPCD EDID Write failed!\n");
225 retval = rk32_edp_write_byte_to_dpcd(edp,
227 DPCD_TEST_EDID_CHECKSUM_WRITE);
229 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
234 dev_info(edp->dev, "EDID data does not include any extensions.\n");
237 retval = rk32_edp_read_bytes_from_i2c(edp,
238 EDID_ADDR, EDID_HEADER,
239 EDID_LENGTH, &edid[EDID_HEADER]);
241 dev_err(edp->dev, "EDID Read failed!\n");
244 sum = edp_calc_edid_check_sum(edid);
246 dev_warn(edp->dev, "EDID bad checksum!\n");
250 retval = rk32_edp_read_byte_from_dpcd(edp,
251 DPCD_TEST_REQUEST, &test_vector);
253 dev_err(edp->dev, "DPCD EDID Read failed!\n");
257 if (test_vector & DPCD_TEST_EDID_READ) {
258 retval = rk32_edp_write_byte_to_dpcd(edp,
259 DPCD_TEST_EDID_CHECKSUM,
260 edid[EDID_CHECKSUM]);
262 dev_err(edp->dev, "DPCD EDID Write failed!\n");
265 retval = rk32_edp_write_byte_to_dpcd(edp,
267 DPCD_TEST_EDID_CHECKSUM_WRITE);
269 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
274 fb_edid_to_monspecs(edid, &edp->specs);
275 dev_err(edp->dev, "EDID Read success!\n");
280 static int rk32_edp_handle_edid(struct rk32_edp *edp)
286 /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
287 retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
291 for (i = 0; i < 12; i++)
292 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
294 for (i = 0; i < 3; i++) {
295 retval = rk32_edp_read_edid(edp);
304 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
310 retval = rk32_edp_read_byte_from_dpcd(edp,
311 DPCD_LANE_CNT_SET, &data);
316 retval = rk32_edp_write_byte_to_dpcd(edp,
318 DPCD_ENHANCED_FRAME_EN |
319 DPCD_LANE_COUNT_SET(data));
321 /*retval = rk32_edp_write_byte_to_dpcd(edp,
322 DPCD_ADDR_CONFIGURATION_SET, 0);*/
324 retval = rk32_edp_write_byte_to_dpcd(edp,
326 DPCD_LANE_COUNT_SET(data));
332 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
334 /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
335 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
338 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
339 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
341 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
346 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
351 retval = rk32_edp_read_byte_from_dpcd(edp,
352 DPCD_MAX_LANE_CNT, &data);
356 return DPCD_ENHANCED_FRAME_CAP(data);
360 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
362 /*rk32_edp_write_byte_to_dpcd(edp,
363 DPCD_ADDR_USER_DEFINED1, 0);
364 rk32_edp_write_byte_to_dpcd(edp,
365 DPCD_ADDR_USER_DEFINED2, 0x83);
366 rk32_edp_write_byte_to_dpcd(edp,
367 DPCD_ADDR_USER_DEFINED3, 0x27);*/
370 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
375 retval = rk32_edp_is_enhanced_mode_available(edp);
380 retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
384 rk32_edp_enable_enhanced_mode(edp, data);
391 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
395 rk32_edp_set_training_pattern(edp, DP_NONE);
397 retval = rk32_edp_write_byte_to_dpcd(edp,
398 DPCD_TRAINING_PATTERN_SET,
399 DPCD_TRAINING_PATTERN_DISABLED);
406 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
407 int pre_emphasis, int lane)
411 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
414 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
418 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
422 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
427 static int rk32_edp_link_start(struct rk32_edp *edp)
434 lane_count = edp->link_train.lane_count;
436 edp->link_train.lt_state = LT_CLK_RECOVERY;
437 edp->link_train.eq_loop = 0;
439 for (lane = 0; lane < lane_count; lane++)
440 edp->link_train.cr_loop[lane] = 0;
442 /* Set sink to D0 (Sink Not Ready) mode. */
443 retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
444 DPCD_SET_POWER_STATE_D0);
446 dev_err(edp->dev, "failed to set sink device to D0!\n");
450 /* Set link rate and count as you want to establish*/
451 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
452 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
454 /* Setup RX configuration */
455 buf[0] = edp->link_train.link_rate;
456 buf[1] = edp->link_train.lane_count;
457 retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
460 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
464 /* Set TX pre-emphasis to level1 */
465 for (lane = 0; lane < lane_count; lane++)
466 rk32_edp_set_lane_lane_pre_emphasis(edp,
467 PRE_EMPHASIS_LEVEL_1, lane);
469 /* Set training pattern 1 */
470 rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
472 /* Set RX training pattern */
473 retval = rk32_edp_write_byte_to_dpcd(edp,
474 DPCD_TRAINING_PATTERN_SET,
475 DPCD_SCRAMBLING_DISABLED |
476 DPCD_TRAINING_PATTERN_1);
478 dev_err(edp->dev, "failed to set training pattern 1!\n");
482 for (lane = 0; lane < lane_count; lane++)
483 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
484 DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
485 retval = rk32_edp_write_bytes_to_dpcd(edp,
486 DPCD_TRAINING_LANE0_SET,
489 dev_err(edp->dev, "failed to set training lane!\n");
496 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
498 int shift = (lane & 1) * 4;
499 u8 link_value = link_status[lane>>1];
501 return (link_value >> shift) & 0xf;
504 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
509 for (lane = 0; lane < lane_count; lane++) {
510 lane_status = rk32_edp_get_lane_status(link_status, lane);
511 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
517 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
523 lane_align = link_align[2];
524 if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
527 for (lane = 0; lane < lane_count; lane++) {
528 lane_status = rk32_edp_get_lane_status(link_align, lane);
529 lane_status &= DPCD_CHANNEL_EQ_BITS;
530 if (lane_status != DPCD_CHANNEL_EQ_BITS)
537 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
540 int shift = (lane & 1) * 4;
541 u8 link_value = adjust_request[lane>>1];
543 return (link_value >> shift) & 0x3;
546 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
547 u8 adjust_request[2],
550 int shift = (lane & 1) * 4;
551 u8 link_value = adjust_request[lane>>1];
553 return ((link_value >> shift) & 0xc) >> 2;
556 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
557 u8 training_lane_set, int lane)
561 rk32_edp_set_lane0_link_training(edp, training_lane_set);
564 rk32_edp_set_lane1_link_training(edp, training_lane_set);
568 rk32_edp_set_lane2_link_training(edp, training_lane_set);
572 rk32_edp_set_lane3_link_training(edp, training_lane_set);
577 static unsigned int rk32_edp_get_lane_link_training(
578 struct rk32_edp *edp,
585 reg = rk32_edp_get_lane0_link_training(edp);
588 reg = rk32_edp_get_lane1_link_training(edp);
591 reg = rk32_edp_get_lane2_link_training(edp);
594 reg = rk32_edp_get_lane3_link_training(edp);
601 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
603 rk32_edp_training_pattern_dis(edp);
605 edp->link_train.lt_state = FAILED;
608 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
614 u8 adjust_request[2];
622 lane_count = edp->link_train.lane_count;
624 retval = rk32_edp_read_bytes_from_dpcd(edp,
628 dev_err(edp->dev, "failed to read lane status!\n");
632 if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
633 /* set training pattern 2 for EQ */
634 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
636 for (lane = 0; lane < lane_count; lane++) {
637 retval = rk32_edp_read_bytes_from_dpcd(edp,
638 DPCD_ADJUST_REQUEST_LANE0_1,
641 dev_err(edp->dev, "failed to read adjust request!\n");
645 voltage_swing = rk32_edp_get_adjust_request_voltage(
646 adjust_request, lane);
647 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
648 adjust_request, lane);
649 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
650 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
652 if (voltage_swing == VOLTAGE_LEVEL_3)
653 training_lane |= DPCD_MAX_SWING_REACHED;
654 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
655 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
657 edp->link_train.training_lane[lane] = training_lane;
659 rk32_edp_set_lane_link_training(edp,
660 edp->link_train.training_lane[lane],
664 retval = rk32_edp_write_byte_to_dpcd(edp,
665 DPCD_TRAINING_PATTERN_SET,
666 DPCD_SCRAMBLING_DISABLED |
667 DPCD_TRAINING_PATTERN_2);
669 dev_err(edp->dev, "failed to set training pattern 2!\n");
673 retval = rk32_edp_write_bytes_to_dpcd(edp,
674 DPCD_TRAINING_LANE0_SET,
676 edp->link_train.training_lane);
678 dev_err(edp->dev, "failed to set training lane!\n");
682 dev_info(edp->dev, "Link Training Clock Recovery success\n");
683 edp->link_train.lt_state = LT_EQ_TRAINING;
685 for (lane = 0; lane < lane_count; lane++) {
686 training_lane = rk32_edp_get_lane_link_training(
688 retval = rk32_edp_read_bytes_from_dpcd(edp,
689 DPCD_ADJUST_REQUEST_LANE0_1,
692 dev_err(edp->dev, "failed to read adjust request!\n");
696 voltage_swing = rk32_edp_get_adjust_request_voltage(
697 adjust_request, lane);
698 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
699 adjust_request, lane);
701 if (voltage_swing == VOLTAGE_LEVEL_3 ||
702 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
703 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
704 goto reduce_link_rate;
707 if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
709 (DPCD_PRE_EMPHASIS_GET(training_lane) ==
711 edp->link_train.cr_loop[lane]++;
712 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
713 dev_err(edp->dev, "CR Max loop\n");
714 goto reduce_link_rate;
718 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
719 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
721 if (voltage_swing == VOLTAGE_LEVEL_3)
722 training_lane |= DPCD_MAX_SWING_REACHED;
723 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
724 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
726 edp->link_train.training_lane[lane] = training_lane;
728 rk32_edp_set_lane_link_training(edp,
729 edp->link_train.training_lane[lane], lane);
732 retval = rk32_edp_write_bytes_to_dpcd(edp,
733 DPCD_TRAINING_LANE0_SET,
735 edp->link_train.training_lane);
737 dev_err(edp->dev, "failed to set training lane!\n");
745 rk32_edp_reduce_link_rate(edp);
749 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
757 u8 adjust_request[2];
765 lane_count = edp->link_train.lane_count;
767 retval = rk32_edp_read_bytes_from_dpcd(edp,
771 dev_err(edp->dev, "failed to read lane status!\n");
775 if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
776 link_align[0] = link_status[0];
777 link_align[1] = link_status[1];
779 retval = rk32_edp_read_byte_from_dpcd(edp,
780 DPCD_LANE_ALIGN_STATUS_UPDATED,
783 dev_err(edp->dev, "failed to read lane aligne status!\n");
787 for (lane = 0; lane < lane_count; lane++) {
788 retval = rk32_edp_read_bytes_from_dpcd(edp,
789 DPCD_ADJUST_REQUEST_LANE0_1,
792 dev_err(edp->dev, "failed to read adjust request!\n");
796 voltage_swing = rk32_edp_get_adjust_request_voltage(
797 adjust_request, lane);
798 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
799 adjust_request, lane);
800 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
801 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
803 if (voltage_swing == VOLTAGE_LEVEL_3)
804 training_lane |= DPCD_MAX_SWING_REACHED;
805 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
806 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
808 edp->link_train.training_lane[lane] = training_lane;
811 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
812 /* traing pattern Set to Normal */
813 retval = rk32_edp_training_pattern_dis(edp);
815 dev_err(edp->dev, "failed to disable training pattern!\n");
819 dev_info(edp->dev, "Link Training success!\n");
821 rk32_edp_get_link_bandwidth(edp, ®);
822 edp->link_train.link_rate = reg;
823 dev_dbg(edp->dev, "final bandwidth = %.2x\n",
824 edp->link_train.link_rate);
826 rk32_edp_get_lane_count(edp, ®);
827 edp->link_train.lane_count = reg;
828 dev_dbg(edp->dev, "final lane count = %.2x\n",
829 edp->link_train.lane_count);
831 edp->link_train.lt_state = FINISHED;
834 edp->link_train.eq_loop++;
836 if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
837 dev_err(edp->dev, "EQ Max loop\n");
838 goto reduce_link_rate;
841 for (lane = 0; lane < lane_count; lane++)
842 rk32_edp_set_lane_link_training(edp,
843 edp->link_train.training_lane[lane],
846 retval = rk32_edp_write_bytes_to_dpcd(edp,
847 DPCD_TRAINING_LANE0_SET,
849 edp->link_train.training_lane);
851 dev_err(edp->dev, "failed to set training lane!\n");
856 goto reduce_link_rate;
862 rk32_edp_reduce_link_rate(edp);
866 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
873 * For DP rev.1.1, Maximum link rate of Main Link lanes
874 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
876 retval = rk32_edp_read_byte_from_dpcd(edp,
877 DPCD_MAX_LINK_RATE, &data);
886 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
893 * For DP rev.1.1, Maximum number of Main Link lanes
894 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
896 retval = rk32_edp_read_byte_from_dpcd(edp,
897 DPCD_MAX_LANE_CNT, &data);
901 *lane_count = DPCD_MAX_LANE_COUNT(data);
905 static int rk32_edp_init_training(struct rk32_edp *edp)
910 * MACRO_RST must be applied after the PLL_LOCK to avoid
911 * the DP inter pair skew issue for at least 10 us
913 rk32_edp_reset_macro(edp);
916 retval = rk32_edp_get_max_rx_bandwidth(edp,
917 &edp->link_train.link_rate);
918 retval = rk32_edp_get_max_rx_lane_count(edp,
919 &edp->link_train.lane_count);
920 dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
921 edp->link_train.link_rate * 27/100,
922 edp->link_train.link_rate*27%100,
923 edp->link_train.lane_count);
925 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
926 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
927 dev_warn(edp->dev, "Rx Max Link Rate is abnormal :%x !"
928 "use default link rate:%d.%dGps\n",
929 edp->link_train.link_rate,
930 edp->video_info.link_rate*27/100,
931 edp->video_info.link_rate*27%100);
932 edp->link_train.link_rate = edp->video_info.link_rate;
935 if (edp->link_train.lane_count == 0) {
936 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !"
937 "use default lanes:%d\n",
938 edp->link_train.lane_count,
939 edp->video_info.lane_count);
940 edp->link_train.lane_count = edp->video_info.lane_count;
943 rk32_edp_analog_power_ctr(edp, 1);
950 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
953 int training_finished = 0;
955 edp->link_train.lt_state = LT_START;
958 while (!training_finished) {
959 switch (edp->link_train.lt_state) {
961 retval = rk32_edp_link_start(edp);
963 dev_err(edp->dev, "LT Start failed\n");
965 case LT_CLK_RECOVERY:
966 retval = rk32_edp_process_clock_recovery(edp);
968 dev_err(edp->dev, "LT CR failed\n");
971 retval = rk32_edp_process_equalizer_training(edp);
973 dev_err(edp->dev, "LT EQ failed\n");
976 training_finished = 1;
987 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
991 /* Set link rate and count as you want to establish*/
992 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
993 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
994 rk32_edp_hw_link_training_en(edp);
995 val = rk32_edp_wait_hw_lt_done(edp);
998 dev_err(edp->dev, "hw lt timeout");
1002 val = rk32_edp_wait_hw_lt_done(edp);
1005 val = rk32_edp_get_hw_lt_status(edp);
1007 dev_err(edp->dev, "hw lt err:%d\n", val);
1013 static int rk32_edp_set_link_train(struct rk32_edp *edp)
1017 retval = rk32_edp_init_training(edp);
1019 dev_err(edp->dev, "DP LT init failed!\n");
1021 retval = rk32_edp_sw_link_training(edp);
1023 retval = rk32_edp_hw_link_training(edp);
1029 static int rk32_edp_config_video(struct rk32_edp *edp,
1030 struct video_info *video_info)
1033 int timeout_loop = 0;
1036 rk32_edp_config_video_slave_mode(edp, video_info);
1038 rk32_edp_set_video_color_format(edp, video_info->color_depth,
1039 video_info->color_space,
1040 video_info->dynamic_range,
1041 video_info->ycbcr_coeff);
1043 if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
1044 dev_err(edp->dev, "PLL is not locked yet.\n");
1050 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
1052 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1053 dev_err(edp->dev, "Timeout of video streamclk ok\n");
1060 /* Set to use the register calculated M/N video */
1061 rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1063 /* For video bist, Video timing must be generated by register */
1064 #ifndef EDP_BIST_MODE
1065 rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
1067 /* Disable video mute */
1068 rk32_edp_enable_video_mute(edp, 0);
1070 /* Configure video slave mode */
1071 rk32_edp_enable_video_master(edp, 0);
1074 rk32_edp_start_video(edp);
1080 if (rk32_edp_is_video_stream_on(edp) == 0) {
1082 if (done_count > 10)
1084 } else if (done_count) {
1087 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1088 dev_err(edp->dev, "Timeout of video streamclk ok\n");
1096 dev_err(edp->dev, "Video stream is not detected!\n");
1102 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1108 rk32_edp_enable_scrambling(edp);
1110 retval = rk32_edp_read_byte_from_dpcd(edp,
1111 DPCD_TRAINING_PATTERN_SET,
1116 retval = rk32_edp_write_byte_to_dpcd(edp,
1117 DPCD_TRAINING_PATTERN_SET,
1118 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1122 rk32_edp_disable_scrambling(edp);
1124 retval = rk32_edp_read_byte_from_dpcd(edp,
1125 DPCD_TRAINING_PATTERN_SET,
1130 retval = rk32_edp_write_byte_to_dpcd(edp,
1131 DPCD_TRAINING_PATTERN_SET,
1132 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1141 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1143 struct rk32_edp *edp = arg;
1144 enum dp_irq_type irq_type;
1146 irq_type = rk32_edp_get_irq_type(edp);
1148 case DP_IRQ_TYPE_HP_CABLE_IN:
1149 dev_info(edp->dev, "Received irq - cable in\n");
1150 rk32_edp_clear_hotplug_interrupts(edp);
1152 case DP_IRQ_TYPE_HP_CABLE_OUT:
1153 dev_info(edp->dev, "Received irq - cable out\n");
1154 rk32_edp_clear_hotplug_interrupts(edp);
1156 case DP_IRQ_TYPE_HP_CHANGE:
1158 * We get these change notifications once in a while, but there
1159 * is nothing we can do with them. Just ignore it for now and
1160 * only handle cable changes.
1162 dev_info(edp->dev, "Received irq - hotplug change; ignoring.\n");
1163 rk32_edp_clear_hotplug_interrupts(edp);
1166 dev_err(edp->dev, "Received irq - unknown type!\n");
1172 static int rk32_edp_enable(void)
1175 struct rk32_edp *edp = rk32_edp;
1178 rk32_edp_clk_enable(edp);
1179 rk32_edp_pre_init(edp);
1180 rk32_edp_init_edp(edp);
1181 enable_irq(edp->irq);
1182 /*ret = rk32_edp_handle_edid(edp);
1184 dev_err(edp->dev, "unable to handle edid\n");
1189 ret = rk32_edp_enable_scramble(edp, 0);
1191 dev_err(edp->dev, "unable to set scramble\n");
1195 ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1197 dev_err(edp->dev, "unable to set enhanced mode\n");
1200 rk32_edp_enable_enhanced_mode(edp, 1);*/
1202 ret = rk32_edp_set_link_train(edp);
1204 dev_err(edp->dev, "link train failed!\n");
1206 dev_info(edp->dev, "link training success.\n");
1208 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1209 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1210 rk32_edp_init_video(edp);
1212 #ifdef EDP_BIST_MODE
1213 rk32_edp_bist_cfg(edp);
1215 ret = rk32_edp_config_video(edp, &edp->video_info);
1217 dev_err(edp->dev, "unable to config video\n");
1225 static int rk32_edp_disable(void)
1227 struct rk32_edp *edp = rk32_edp;
1229 disable_irq(edp->irq);
1230 rk32_edp_reset(edp);
1231 rk32_edp_analog_power_ctr(edp, 0);
1232 rk32_edp_clk_disable(edp);
1238 static struct rk_fb_trsm_ops trsm_edp_ops = {
1239 .enable = rk32_edp_enable,
1240 .disable = rk32_edp_disable,
1244 #if defined(CONFIG_DEBUG_FS)
1246 static int edp_dpcd_debugfs_show(struct seq_file *s, void *v)
1249 unsigned char buf[12];
1250 struct rk32_edp *edp = s->private;
1252 dev_err(edp->dev, "no edp device!\n");
1257 rk32_edp_read_bytes_from_dpcd(edp,
1258 DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
1259 for (i = 0; i < 12; i++)
1260 seq_printf(s, "0x%02x>>0x%02x\n", 0x210 + i, buf[i]);
1264 static ssize_t edp_dpcd_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos)
1269 static int edp_edid_debugfs_show(struct seq_file *s, void *v)
1271 struct rk32_edp *edp = s->private;
1273 dev_err(edp->dev, "no edp device!\n");
1276 rk32_edp_read_edid(edp);
1277 seq_puts(s, "edid");
1281 static ssize_t edp_edid_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos)
1283 struct rk32_edp *edp = ((struct seq_file *)file->private_data)->private;
1285 dev_err(edp->dev, "no edp device!\n");
1293 static int edp_reg_debugfs_show(struct seq_file *s, void *v)
1296 struct rk32_edp *edp = s->private;
1298 dev_err(edp->dev, "no edp device!\n");
1302 for (i = 0; i < 0x284; i++) {
1304 seq_printf(s, "\n%08x: ", i*4);
1305 seq_printf(s, "%08x ", readl(edp->regs + i*4));
1310 static ssize_t edp_reg_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos)
1315 #define EDP_DEBUG_ENTRY(name) \
1316 static int edp_##name##_debugfs_open(struct inode *inode, struct file *file) \
1318 return single_open(file, edp_##name##_debugfs_show, inode->i_private); \
1321 static const struct file_operations edp_##name##_debugfs_fops = { \
1322 .owner = THIS_MODULE, \
1323 .open = edp_##name##_debugfs_open, \
1325 .write = edp_##name##_write, \
1326 .llseek = seq_lseek, \
1327 .release = single_release, \
1330 EDP_DEBUG_ENTRY(dpcd);
1331 EDP_DEBUG_ENTRY(edid);
1332 EDP_DEBUG_ENTRY(reg);
1335 static int rk32_edp_probe(struct platform_device *pdev)
1337 struct rk32_edp *edp;
1338 struct resource *res;
1339 struct device_node *np = pdev->dev.of_node;
1343 dev_err(&pdev->dev, "Missing device tree node.\n");
1347 edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1349 dev_err(&pdev->dev, "no memory for state\n");
1352 edp->dev = &pdev->dev;
1353 edp->video_info.h_sync_polarity = 0;
1354 edp->video_info.v_sync_polarity = 0;
1355 edp->video_info.interlaced = 0;
1356 edp->video_info.color_space = CS_RGB;
1357 edp->video_info.dynamic_range = VESA;
1358 edp->video_info.ycbcr_coeff = COLOR_YCBCR601;
1359 edp->video_info.color_depth = COLOR_8;
1361 edp->video_info.link_rate = LINK_RATE_1_62GBPS;
1362 edp->video_info.lane_count = LANE_CNT4;
1363 rk_fb_get_prmry_screen(&edp->screen);
1364 if (edp->screen.type != SCREEN_EDP) {
1365 dev_err(&pdev->dev, "screen is not edp!\n");
1368 platform_set_drvdata(pdev, edp);
1369 dev_set_name(edp->dev, "rk32-edp");
1371 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1372 edp->regs = devm_ioremap_resource(&pdev->dev, res);
1373 if (IS_ERR(edp->regs)) {
1374 dev_err(&pdev->dev, "ioremap reg failed\n");
1375 return PTR_ERR(edp->regs);
1378 edp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1379 if (IS_ERR(edp->grf)) {
1380 dev_err(&pdev->dev, "can't find rockchip,grf property\n");
1381 return PTR_ERR(edp->grf);
1384 edp->pd = devm_clk_get(&pdev->dev, "pd_edp");
1385 if (IS_ERR(edp->pd)) {
1386 dev_err(&pdev->dev, "cannot get pd\n");
1390 edp->clk_edp = devm_clk_get(&pdev->dev, "clk_edp");
1391 if (IS_ERR(edp->clk_edp)) {
1392 dev_err(&pdev->dev, "cannot get clk_edp\n");
1393 return PTR_ERR(edp->clk_edp);
1396 edp->clk_24m = devm_clk_get(&pdev->dev, "clk_edp_24m");
1397 if (IS_ERR(edp->clk_24m)) {
1398 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1399 return PTR_ERR(edp->clk_24m);
1402 edp->pclk = devm_clk_get(&pdev->dev, "pclk_edp");
1403 if (IS_ERR(edp->pclk)) {
1404 dev_err(&pdev->dev, "cannot get pclk\n");
1405 return PTR_ERR(edp->pclk);
1408 /*edp 24m need sorft reset*/
1409 edp->rst_24m = devm_reset_control_get(&pdev->dev, "edp_24m");
1410 if (IS_ERR(edp->rst_24m)) {
1411 dev_err(&pdev->dev, "failed to get reset\n");
1412 return PTR_ERR(edp->rst_24m);
1415 rk32_edp_clk_enable(edp);
1416 if (!support_uboot_display())
1417 rk32_edp_pre_init(edp);
1418 edp->irq = platform_get_irq(pdev, 0);
1420 dev_err(&pdev->dev, "cannot find IRQ\n");
1423 ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1424 dev_name(&pdev->dev), edp);
1426 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1429 disable_irq_nosync(edp->irq);
1430 if (!support_uboot_display())
1431 rk32_edp_clk_disable(edp);
1433 rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1434 #if defined(CONFIG_DEBUG_FS)
1435 edp->debugfs_dir = debugfs_create_dir("edp", NULL);
1436 if (IS_ERR(edp->debugfs_dir)) {
1437 dev_err(edp->dev, "failed to create debugfs dir for edp!\n");
1439 debugfs_create_file("dpcd", S_IRUSR, edp->debugfs_dir,
1440 edp, &edp_dpcd_debugfs_fops);
1441 debugfs_create_file("edid", S_IRUSR, edp->debugfs_dir,
1442 edp, &edp_edid_debugfs_fops);
1443 debugfs_create_file("reg", S_IRUSR, edp->debugfs_dir,
1444 edp, &edp_reg_debugfs_fops);
1448 dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1453 static void rk32_edp_shutdown(struct platform_device *pdev)
1458 #if defined(CONFIG_OF)
1459 static const struct of_device_id rk32_edp_dt_ids[] = {
1460 {.compatible = "rockchip,rk32-edp",},
1464 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1467 static struct platform_driver rk32_edp_driver = {
1468 .probe = rk32_edp_probe,
1471 .owner = THIS_MODULE,
1472 #if defined(CONFIG_OF)
1473 .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1476 .shutdown = rk32_edp_shutdown,
1479 static int __init rk32_edp_module_init(void)
1481 return platform_driver_register(&rk32_edp_driver);
1484 static void __exit rk32_edp_module_exit(void)
1489 fs_initcall(rk32_edp_module_init);
1490 module_exit(rk32_edp_module_exit);