drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/rockchip/cpu.h>
  24 #include <linux/rockchip/iomap.h>
  25 #include <linux/rockchip/grf.h>
  26 #include <linux/string.h>
  27 #include <linux/slab.h>
  28 #include <linux/uaccess.h>
  29
  30 #if defined(CONFIG_OF)
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #endif
  34
  35 #if defined(CONFIG_DEBUG_FS)
  36 #include <linux/fs.h>
  37 #include <linux/debugfs.h>
  38 #include <linux/seq_file.h>
  39 #endif
  40
  41 #include "rk32_dp.h"
  42
  43 /*#define EDP_BIST_MODE*/
  44 /*#define SW_LT*/
  45
  46 #define RK3368_GRF_SOC_CON4     0x410
  47
  48 static struct rk32_edp *rk32_edp;
  49
  50 static int rk32_edp_clk_enable(struct rk32_edp *edp)
  51 {
  52         int ret;
  53
  54         if (!edp->clk_on) {
  55                 if (edp->pd)
  56                         clk_prepare_enable(edp->pd);
  57                 clk_prepare_enable(edp->pclk);
  58                 clk_prepare_enable(edp->clk_edp);
  59
  60                 if (edp->soctype != SOC_RK3399) {
  61                         ret = clk_set_rate(edp->clk_24m, 24000000);
  62                         if (ret < 0)
  63                                 pr_err("cannot set edp clk_24m %d\n", ret);
  64                         clk_prepare_enable(edp->clk_24m);
  65                 }
  66                 edp->clk_on = true;
  67         }
  68
  69         return 0;
  70 }
  71
  72 static int rk32_edp_clk_disable(struct rk32_edp *edp)
  73 {
  74         if (edp->clk_on) {
  75                 clk_disable_unprepare(edp->pclk);
  76                 clk_disable_unprepare(edp->clk_edp);
  77
  78                 if (edp->soctype != SOC_RK3399)
  79                         clk_disable_unprepare(edp->clk_24m);
  80
  81                 if (edp->pd)
  82                         clk_disable_unprepare(edp->pd);
  83                 edp->clk_on = false;
  84         }
  85
  86         return 0;
  87 }
  88
  89 static int rk32_edp_pre_init(struct rk32_edp *edp)
  90 {
  91         u32 val;
  92
  93         if (cpu_is_rk3288()) {
  94                 val = GRF_EDP_REF_CLK_SEL_INTER |
  95                         (GRF_EDP_REF_CLK_SEL_INTER << 16);
  96                 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
  97
  98                 val = 0x80008000;
  99                 writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
 100                 dsb(sy);
 101                 udelay(1);
 102                 val = 0x80000000;
 103                 writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
 104                 dsb(sy);
 105                 udelay(1);
 106         } else {
 107                 /* The rk3368 reset the edp 24M clock and apb bus
 108                  * according to the CRU_SOFTRST6_CON and CRU_SOFTRST7_CON.
 109                  */
 110                 if (edp->soctype != SOC_RK3399) {
 111                         val = 0x01 | (0x01 << 16);
 112                         regmap_write(edp->grf, RK3368_GRF_SOC_CON4, val);
 113
 114                         reset_control_assert(edp->rst_24m);
 115                         usleep_range(10, 20);
 116                         reset_control_deassert(edp->rst_24m);
 117                 }
 118
 119                 reset_control_assert(edp->rst_apb);
 120                 usleep_range(10, 20);
 121                 reset_control_deassert(edp->rst_apb);
 122         }
 123         return 0;
 124 }
 125
 126 static int rk32_edp_init_edp(struct rk32_edp *edp)
 127 {
 128         struct rk_screen *screen = &edp->screen;
 129         u32 val = 0;
 130
 131         rk_fb_get_prmry_screen(screen);
 132
 133         if (cpu_is_rk3288()) {
 134                 if (screen->lcdc_id == 1)  /*select lcdc*/
 135                         val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
 136                 else
 137                         val = EDP_SEL_VOP_LIT << 16;
 138                 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
 139         }
 140
 141         rk32_edp_reset(edp);
 142         rk32_edp_init_refclk(edp);
 143         rk32_edp_init_interrupt(edp);
 144         rk32_edp_enable_sw_function(edp);
 145         rk32_edp_init_analog_func(edp);
 146         rk32_edp_init_hpd(edp);
 147         rk32_edp_init_aux(edp);
 148
 149         return 0;
 150 }
 151
 152 /*#if 0
 153 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
 154 {
 155         int timeout_loop = 0;
 156
 157         rk32_edp_init_hpd(edp);
 158
 159         udelay(200);
 160
 161         while (rk32_edp_get_plug_in_status(edp) != 0) {
 162                 timeout_loop++;
 163                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 164                         dev_err(edp->dev, "failed to get hpd plug status\n");
 165                         return -ETIMEDOUT;
 166                 }
 167                 udelay(10);
 168         }
 169
 170         return 0;
 171 }
 172 #endif*/
 173
 174 static int rk32_edp_read_edid(struct rk32_edp *edp)
 175 {
 176         unsigned char edid[EDID_LENGTH * 2];
 177         unsigned int extend_block = 0;
 178         unsigned char sum;
 179         unsigned char test_vector;
 180         int retval;
 181
 182         /*
 183          * EDID device address is 0x50.
 184          * However, if necessary, you must have set upper address
 185          * into E-EDID in I2C device, 0x30.
 186          */
 187
 188         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 189         retval = rk32_edp_read_byte_from_i2c
 190                         (edp,
 191                          EDID_ADDR, EDID_EXTENSION_FLAG, &extend_block);
 192         if (retval < 0) {
 193                 dev_err(edp->dev, "EDID extension flag failed!\n");
 194                 return -EIO;
 195         }
 196
 197         if (extend_block > 0) {
 198                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
 199
 200                 /* Read EDID data */
 201                 retval = rk32_edp_read_bytes_from_i2c
 202                                (edp,
 203                                 EDID_ADDR, EDID_HEADER,
 204                                 EDID_LENGTH, &edid[EDID_HEADER]);
 205                 if (retval != 0) {
 206                         dev_err(edp->dev, "EDID Read failed!\n");
 207                         return -EIO;
 208                 }
 209                 sum = edp_calc_edid_check_sum(edid);
 210                 if (sum != 0) {
 211                         dev_warn(edp->dev, "EDID bad checksum!\n");
 212                         return 0;
 213                 }
 214
 215                 /* Read additional EDID data */
 216                 retval = rk32_edp_read_bytes_from_i2c
 217                                (edp,
 218                                 EDID_ADDR, EDID_LENGTH,
 219                                 EDID_LENGTH, &edid[EDID_LENGTH]);
 220                 if (retval != 0) {
 221                         dev_err(edp->dev, "EDID Read failed!\n");
 222                         return -EIO;
 223                 }
 224                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
 225                 if (sum != 0) {
 226                         dev_warn(edp->dev, "EDID bad checksum!\n");
 227                         return 0;
 228                 }
 229
 230                 retval = rk32_edp_read_byte_from_dpcd
 231                                 (edp,
 232                                  DPCD_TEST_REQUEST, &test_vector);
 233                 if (retval < 0) {
 234                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 235                         return retval;
 236                 }
 237
 238                 if (test_vector & DPCD_TEST_EDID_READ) {
 239                         retval = rk32_edp_write_byte_to_dpcd
 240                                        (edp,
 241                                         DPCD_TEST_EDID_CHECKSUM,
 242                                         edid[EDID_LENGTH + EDID_CHECKSUM]);
 243                         if (retval < 0) {
 244                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 245                                 return retval;
 246                         }
 247                         retval = rk32_edp_write_byte_to_dpcd
 248                                        (edp,
 249                                         DPCD_TEST_RESPONSE,
 250                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 251                         if (retval < 0) {
 252                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 253                                 return retval;
 254                         }
 255                 }
 256         } else {
 257                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 258
 259                 /* Read EDID data */
 260                 retval = rk32_edp_read_bytes_from_i2c
 261                                (edp,
 262                                 EDID_ADDR, EDID_HEADER,
 263                                 EDID_LENGTH, &edid[EDID_HEADER]);
 264                 if (retval != 0) {
 265                         dev_err(edp->dev, "EDID Read failed!\n");
 266                         return -EIO;
 267                 }
 268                 sum = edp_calc_edid_check_sum(edid);
 269                 if (sum != 0) {
 270                         dev_warn(edp->dev, "EDID bad checksum!\n");
 271                         return 0;
 272                 }
 273
 274                 retval = rk32_edp_read_byte_from_dpcd
 275                                 (edp,
 276                                  DPCD_TEST_REQUEST, &test_vector);
 277                 if (retval < 0) {
 278                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 279                         return retval;
 280                 }
 281
 282                 if (test_vector & DPCD_TEST_EDID_READ) {
 283                         retval = rk32_edp_write_byte_to_dpcd
 284                                         (edp,
 285                                          DPCD_TEST_EDID_CHECKSUM,
 286                                          edid[EDID_CHECKSUM]);
 287                         if (retval < 0) {
 288                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 289                                 return retval;
 290                         }
 291                         retval = rk32_edp_write_byte_to_dpcd
 292                                        (edp,
 293                                         DPCD_TEST_RESPONSE,
 294                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 295                         if (retval < 0) {
 296                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 297                                 return retval;
 298                         }
 299                 }
 300         }
 301         fb_edid_to_monspecs(edid, &edp->specs);
 302         dev_err(edp->dev, "EDID Read success!\n");
 303         return 0;
 304 }
 305 #define open_t 0
 306 #if open_t
 307 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 308 {
 309         u8 buf[12];
 310         int i;
 311         int retval;
 312
 313         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 314         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
 315         if (retval < 0)
 316                 return retval;
 317
 318         for (i = 0; i < 12; i++)
 319                 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
 320         /* Read EDID */
 321         for (i = 0; i < 3; i++) {
 322                 retval = rk32_edp_read_edid(edp);
 323                 if (retval == 0)
 324                         break;
 325         }
 326
 327         return retval;
 328 }
 329
 330
 331 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 332                                                bool enable)
 333 {
 334         u8 data;
 335         int retval;
 336
 337         retval = rk32_edp_read_byte_from_dpcd
 338                         (edp,
 339                          DPCD_LANE_CNT_SET, &data);
 340         if (retval < 0)
 341                 return retval;
 342
 343         if (enable) {
 344                 retval = rk32_edp_write_byte_to_dpcd
 345                                 (edp,
 346                                  DPCD_LANE_CNT_SET,
 347                                  DPCD_ENHANCED_FRAME_EN |
 348                                  DPCD_LANE_COUNT_SET(data));
 349         } else {
 350                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 351                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 352
 353                 retval = rk32_edp_write_byte_to_dpcd
 354                                 (edp,
 355                                  DPCD_LANE_CNT_SET,
 356                                  DPCD_LANE_COUNT_SET(data));
 357         }
 358
 359         return retval;
 360 }
 361
 362 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 363 {
 364         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 365         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 366
 367         if (enable) {
 368                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 369                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 370         } else {
 371                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 372         }*/
 373 }
 374
 375
 376 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 377 {
 378         u8 data;
 379         int retval;
 380
 381         retval = rk32_edp_read_byte_from_dpcd
 382                         (edp,
 383                          DPCD_MAX_LANE_CNT, &data);
 384         if (retval < 0)
 385                 return retval;
 386
 387         return DPCD_ENHANCED_FRAME_CAP(data);
 388 }
 389
 390
 391 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 392 {
 393         /*rk32_edp_write_byte_to_dpcd(edp,
 394                         DPCD_ADDR_USER_DEFINED1, 0);
 395         rk32_edp_write_byte_to_dpcd(edp,
 396                         DPCD_ADDR_USER_DEFINED2, 0x83);
 397         rk32_edp_write_byte_to_dpcd(edp,
 398                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 399 }
 400
 401 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 402 {
 403         u8 data;
 404         int retval;
 405
 406         retval = rk32_edp_is_enhanced_mode_available(edp);
 407         if (retval < 0)
 408                 return retval;
 409
 410         data = (u8)retval;
 411         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 412         if (retval < 0)
 413                 return retval;
 414
 415         rk32_edp_enable_enhanced_mode(edp, data);
 416
 417         return 0;
 418 }
 419 #endif
 420
 421
 422 #if defined(SW_LT)
 423 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 424 {
 425         int retval;
 426
 427         rk32_edp_set_training_pattern(edp, DP_NONE);
 428
 429         retval = rk32_edp_write_byte_to_dpcd(edp,
 430                                              DPCD_TRAINING_PATTERN_SET,
 431                                              DPCD_TRAINING_PATTERN_DISABLED);
 432         if (retval < 0)
 433                 return retval;
 434
 435         return 0;
 436 }
 437
 438 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 439                                                 int pre_emphasis, int lane)
 440 {
 441         switch (lane) {
 442         case 0:
 443                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 444                 break;
 445         case 1:
 446                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 447                 break;
 448
 449         case 2:
 450                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 451                 break;
 452
 453         case 3:
 454                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 455                 break;
 456         }
 457 }
 458
 459 static int rk32_edp_link_start(struct rk32_edp *edp)
 460 {
 461         u8 buf[4];
 462         int lane;
 463         int lane_count;
 464         int retval;
 465
 466         lane_count = edp->link_train.lane_count;
 467
 468         edp->link_train.lt_state = LT_CLK_RECOVERY;
 469         edp->link_train.eq_loop = 0;
 470
 471         for (lane = 0; lane < lane_count; lane++)
 472                 edp->link_train.cr_loop[lane] = 0;
 473
 474         /* Set sink to D0 (Sink Not Ready) mode. */
 475         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
 476                                              DPCD_SET_POWER_STATE_D0);
 477         if (retval < 0) {
 478                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 479                 return retval;
 480         }
 481
 482         /* Set link rate and count as you want to establish*/
 483         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 484         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 485
 486         /* Setup RX configuration */
 487         buf[0] = edp->link_train.link_rate;
 488         buf[1] = edp->link_train.lane_count;
 489         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
 490                                               2, buf);
 491         if (retval < 0) {
 492                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 493                 return retval;
 494         }
 495
 496         /* Set TX pre-emphasis to level1 */
 497         for (lane = 0; lane < lane_count; lane++)
 498                 rk32_edp_set_lane_lane_pre_emphasis
 499                         (edp,
 500                          PRE_EMPHASIS_LEVEL_1, lane);
 501
 502         /* Set training pattern 1 */
 503         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 504
 505         /* Set RX training pattern */
 506         retval = rk32_edp_write_byte_to_dpcd(edp,
 507                                              DPCD_TRAINING_PATTERN_SET,
 508                                              DPCD_SCRAMBLING_DISABLED |
 509                                              DPCD_TRAINING_PATTERN_1);
 510         if (retval < 0) {
 511                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 512                 return retval;
 513         }
 514
 515         for (lane = 0; lane < lane_count; lane++)
 516                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 517                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 518         retval = rk32_edp_write_bytes_to_dpcd(edp,
 519                                               DPCD_TRAINING_LANE0_SET,
 520                                               lane_count, buf);
 521         if (retval < 0) {
 522                 dev_err(edp->dev, "failed to set training lane!\n");
 523                 return retval;
 524         }
 525
 526         return 0;
 527 }
 528
 529 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 530 {
 531         int shift = (lane & 1) * 4;
 532         u8 link_value = link_status[lane>>1];
 533
 534         return (link_value >> shift) & 0xf;
 535 }
 536
 537 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 538 {
 539         int lane;
 540         u8 lane_status;
 541
 542         for (lane = 0; lane < lane_count; lane++) {
 543                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 544                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 545                         return -EINVAL;
 546         }
 547         return 0;
 548 }
 549
 550 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 551 {
 552         int lane;
 553         u8 lane_align;
 554         u8 lane_status;
 555
 556         lane_align = link_align[2];
 557         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 558                 return -EINVAL;
 559
 560         for (lane = 0; lane < lane_count; lane++) {
 561                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 562                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 563                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 564                         return -EINVAL;
 565         }
 566
 567         return 0;
 568 }
 569
 570 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 571                                                          int lane)
 572 {
 573         int shift = (lane & 1) * 4;
 574         u8 link_value = adjust_request[lane>>1];
 575
 576         return (link_value >> shift) & 0x3;
 577 }
 578
 579 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 580                                         u8 adjust_request[2],
 581                                         int lane)
 582 {
 583         int shift = (lane & 1) * 4;
 584         u8 link_value = adjust_request[lane>>1];
 585
 586         return ((link_value >> shift) & 0xc) >> 2;
 587 }
 588
 589 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 590                                             u8 training_lane_set, int lane)
 591 {
 592         switch (lane) {
 593         case 0:
 594                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 595                 break;
 596         case 1:
 597                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 598                 break;
 599
 600         case 2:
 601                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 602                 break;
 603
 604         case 3:
 605                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 606                 break;
 607         }
 608 }
 609
 610 static unsigned int rk32_edp_get_lane_link_training(
 611                                                     struct rk32_edp *edp,
 612                                                     int lane)
 613 {
 614         u32 reg;
 615
 616         switch (lane) {
 617         case 0:
 618                 reg = rk32_edp_get_lane0_link_training(edp);
 619                 break;
 620         case 1:
 621                 reg = rk32_edp_get_lane1_link_training(edp);
 622                 break;
 623         case 2:
 624                 reg = rk32_edp_get_lane2_link_training(edp);
 625                 break;
 626         case 3:
 627                 reg = rk32_edp_get_lane3_link_training(edp);
 628                 break;
 629         }
 630
 631         return reg;
 632 }
 633
 634 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 635 {
 636         rk32_edp_training_pattern_dis(edp);
 637
 638         edp->link_train.lt_state = FAILED;
 639 }
 640
 641 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 642 {
 643         u8 link_status[2];
 644         int lane;
 645         int lane_count;
 646
 647         u8 adjust_request[2];
 648         u8 voltage_swing;
 649         u8 pre_emphasis;
 650         u8 training_lane;
 651         int retval;
 652
 653         /*udelay(100);*/
 654         usleep_range(99, 100);
 655
 656         lane_count = edp->link_train.lane_count;
 657
 658         retval = rk32_edp_read_bytes_from_dpcd(edp,
 659                                                DPCD_LANE0_1_STATUS,
 660                                                2, link_status);
 661         if (retval < 0) {
 662                 dev_err(edp->dev, "failed to read lane status!\n");
 663                 return retval;
 664         }
 665
 666         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 667                 /* set training pattern 2 for EQ */
 668                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 669
 670                 for (lane = 0; lane < lane_count; lane++) {
 671                         retval = rk32_edp_read_bytes_from_dpcd
 672                                         (edp,
 673                                          DPCD_ADJUST_REQUEST_LANE0_1,
 674                                          2, adjust_request);
 675                         if (retval < 0) {
 676                                 dev_err(edp->dev, "failed to read adjust request!\n");
 677                                 return retval;
 678                         }
 679
 680                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 681                                                         adjust_request, lane);
 682                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 683                                                         adjust_request, lane);
 684                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 685                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 686
 687                         if (voltage_swing == VOLTAGE_LEVEL_3)
 688                                 training_lane |= DPCD_MAX_SWING_REACHED;
 689                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 690                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 691
 692                         edp->link_train.training_lane[lane] = training_lane;
 693
 694                         rk32_edp_set_lane_link_training
 695                                 (edp,
 696                                  edp->link_train.training_lane[lane],
 697                                  lane);
 698                 }
 699
 700                 retval = rk32_edp_write_byte_to_dpcd(edp,
 701                                                      DPCD_TRAINING_PATTERN_SET,
 702                                                      DPCD_SCRAMBLING_DISABLED |
 703                                                      DPCD_TRAINING_PATTERN_2);
 704                 if (retval < 0) {
 705                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 706                         return retval;
 707                 }
 708
 709                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 710                                                       DPCD_TRAINING_LANE0_SET,
 711                                                       lane_count,
 712                                 edp->link_train.training_lane);
 713                 if (retval < 0) {
 714                         dev_err(edp->dev, "failed to set training lane!\n");
 715                         return retval;
 716                 }
 717
 718                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 719                 edp->link_train.lt_state = LT_EQ_TRAINING;
 720         } else {
 721                 for (lane = 0; lane < lane_count; lane++) {
 722                         training_lane = rk32_edp_get_lane_link_training(
 723                                                         edp, lane);
 724                         retval = rk32_edp_read_bytes_from_dpcd
 725                                         (edp,
 726                                          DPCD_ADJUST_REQUEST_LANE0_1,
 727                                          2, adjust_request);
 728                         if (retval < 0) {
 729                                 dev_err(edp->dev, "failed to read adjust request!\n");
 730                                 return retval;
 731                         }
 732
 733                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 734                                                         adjust_request, lane);
 735                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 736                                                         adjust_request, lane);
 737
 738                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 739                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 740                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 741                                 goto reduce_link_rate;
 742                         }
 743
 744                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 745                                         voltage_swing) &&
 746                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 747                                         pre_emphasis)) {
 748                                 edp->link_train.cr_loop[lane]++;
 749                                 if (edp->link_train.cr_loop[lane] ==
 750                                         MAX_CR_LOOP) {
 751                                         dev_err(edp->dev, "CR Max loop\n");
 752                                         goto reduce_link_rate;
 753                                 }
 754                         }
 755
 756                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 757                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 758
 759                         if (voltage_swing == VOLTAGE_LEVEL_3)
 760                                 training_lane |= DPCD_MAX_SWING_REACHED;
 761                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 762                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 763
 764                         edp->link_train.training_lane[lane] = training_lane;
 765
 766                         rk32_edp_set_lane_link_training
 767                                 (edp,
 768                                  edp->link_train.training_lane[lane], lane);
 769                 }
 770
 771                 retval = rk32_edp_write_bytes_to_dpcd
 772                                 (edp,
 773                                  DPCD_TRAINING_LANE0_SET,
 774                                  lane_count,
 775                                  edp->link_train.training_lane);
 776                 if (retval < 0) {
 777                         dev_err(edp->dev, "failed to set training lane!\n");
 778                         return retval;
 779                 }
 780         }
 781
 782         return 0;
 783
 784 reduce_link_rate:
 785         rk32_edp_reduce_link_rate(edp);
 786         return -EIO;
 787 }
 788
 789 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 790 {
 791         u8 link_status[2];
 792         u8 link_align[3];
 793         int lane;
 794         int lane_count;
 795         u32 reg;
 796
 797         u8 adjust_request[2];
 798         u8 voltage_swing;
 799         u8 pre_emphasis;
 800         u8 training_lane;
 801         int retval;
 802
 803         /*udelay(400);*/
 804         usleep_range(399, 400);
 805
 806         lane_count = edp->link_train.lane_count;
 807
 808         retval = rk32_edp_read_bytes_from_dpcd(edp,
 809                                                DPCD_LANE0_1_STATUS,
 810                                                2, link_status);
 811         if (retval < 0) {
 812                 dev_err(edp->dev, "failed to read lane status!\n");
 813                 return retval;
 814         }
 815
 816         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 817                 link_align[0] = link_status[0];
 818                 link_align[1] = link_status[1];
 819
 820                 retval = rk32_edp_read_byte_from_dpcd
 821                                 (edp,
 822                                  DPCD_LANE_ALIGN_STATUS_UPDATED,
 823                                  &link_align[2]);
 824                 if (retval < 0) {
 825                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 826                         return retval;
 827                 }
 828
 829                 for (lane = 0; lane < lane_count; lane++) {
 830                         retval = rk32_edp_read_bytes_from_dpcd
 831                                         (edp,
 832                                          DPCD_ADJUST_REQUEST_LANE0_1,
 833                                          2, adjust_request);
 834                         if (retval < 0) {
 835                                 dev_err(edp->dev, "failed to read adjust request!\n");
 836                                 return retval;
 837                         }
 838
 839                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 840                                                         adjust_request, lane);
 841                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 842                                                         adjust_request, lane);
 843                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 844                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 845
 846                         if (voltage_swing == VOLTAGE_LEVEL_3)
 847                                 training_lane |= DPCD_MAX_SWING_REACHED;
 848                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 849                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 850
 851                         edp->link_train.training_lane[lane] = training_lane;
 852                 }
 853
 854                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 855                         /* traing pattern Set to Normal */
 856                         retval = rk32_edp_training_pattern_dis(edp);
 857                         if (retval < 0) {
 858                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 859                                 return retval;
 860                         }
 861
 862                         dev_info(edp->dev, "Link Training success!\n");
 863
 864                         rk32_edp_get_link_bandwidth(edp, &reg);
 865                         edp->link_train.link_rate = reg;
 866                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 867                                 edp->link_train.link_rate);
 868
 869                         rk32_edp_get_lane_count(edp, &reg);
 870                         edp->link_train.lane_count = reg;
 871                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 872                                 edp->link_train.lane_count);
 873
 874                         edp->link_train.lt_state = FINISHED;
 875                 } else {
 876                         /* not all locked */
 877                         edp->link_train.eq_loop++;
 878
 879                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 880                                 dev_err(edp->dev, "EQ Max loop\n");
 881                                 goto reduce_link_rate;
 882                         }
 883
 884                         for (lane = 0; lane < lane_count; lane++)
 885                                 rk32_edp_set_lane_link_training
 886                                 (edp,
 887                                  edp->link_train.training_lane[lane],
 888                                  lane);
 889
 890                         retval = rk32_edp_write_bytes_to_dpcd
 891                                         (edp,
 892                                          DPCD_TRAINING_LANE0_SET,
 893                                          lane_count,
 894                                          edp->link_train.training_lane);
 895                         if (retval < 0) {
 896                                 dev_err(edp->dev, "failed to set training lane!\n");
 897                                 return retval;
 898                         }
 899                 }
 900         } else {
 901                 goto reduce_link_rate;
 902         }
 903
 904         return 0;
 905
 906 reduce_link_rate:
 907         rk32_edp_reduce_link_rate(edp);
 908         return -EIO;
 909 }
 910 #endif
 911 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 912                                          u8 *bandwidth)
 913 {
 914         u8 data;
 915         int retval = 0;
 916
 917         /*
 918          * For DP rev.1.1, Maximum link rate of Main Link lanes
 919          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 920          */
 921         retval = rk32_edp_read_byte_from_dpcd(edp,
 922                                               DPCD_MAX_LINK_RATE, &data);
 923         if (retval < 0)
 924                 *bandwidth = 0;
 925         else
 926                 *bandwidth = data;
 927         return retval;
 928 }
 929
 930 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 931                                           u8 *lane_count)
 932 {
 933         u8 data;
 934         int retval;
 935
 936         /*
 937          * For DP rev.1.1, Maximum number of Main Link lanes
 938          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 939          */
 940         retval = rk32_edp_read_byte_from_dpcd(edp,
 941                                               DPCD_MAX_LANE_CNT, &data);
 942         if (retval < 0)
 943                 *lane_count = 0;
 944         else
 945                 *lane_count = DPCD_MAX_LANE_COUNT(data);
 946         return retval;
 947 }
 948
 949 static int rk32_edp_init_training(struct rk32_edp *edp)
 950 {
 951         int retval;
 952
 953         /*
 954          * MACRO_RST must be applied after the PLL_LOCK to avoid
 955          * the DP inter pair skew issue for at least 10 us
 956          */
 957         rk32_edp_reset_macro(edp);
 958
 959
 960         retval = rk32_edp_get_max_rx_bandwidth(edp,
 961                                                &edp->link_train.link_rate);
 962         retval = rk32_edp_get_max_rx_lane_count(edp,
 963                                                 &edp->link_train.lane_count);
 964         dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
 965                  edp->link_train.link_rate * 27/100,
 966                  edp->link_train.link_rate*27%100,
 967                  edp->link_train.lane_count);
 968
 969         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 970             (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 971                 dev_warn
 972                 (edp->dev,
 973                  "Rx Mx Link Rate is abnormal:%x!default link rate:%d.%dGps\n",
 974                  edp->link_train.link_rate,
 975                  edp->video_info.link_rate*27/100,
 976                  edp->video_info.link_rate*27%100);
 977                 edp->link_train.link_rate = edp->video_info.link_rate;
 978         }
 979
 980         if (edp->link_train.lane_count == 0) {
 981                 dev_err
 982                 (edp->dev,
 983                  "Rx Max Lane count is abnormal :%x !use default lanes:%d\n",
 984                  edp->link_train.lane_count,
 985                  edp->video_info.lane_count);
 986                 edp->link_train.lane_count = edp->video_info.lane_count;
 987         }
 988
 989         rk32_edp_analog_power_ctr(edp, 1);
 990
 991
 992         return 0;
 993 }
 994
 995 #if defined(SW_LT)
 996 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
 997 {
 998         int retval = 0;
 999         int training_finished = 0;
1000
1001         edp->link_train.lt_state = LT_START;
1002
1003         /* Process here */
1004         while (!training_finished) {
1005                 switch (edp->link_train.lt_state) {
1006                 case LT_START:
1007                         retval = rk32_edp_link_start(edp);
1008                         if (retval)
1009                                 dev_err(edp->dev, "LT Start failed\n");
1010                         break;
1011                 case LT_CLK_RECOVERY:
1012                         retval = rk32_edp_process_clock_recovery(edp);
1013                         if (retval)
1014                                 dev_err(edp->dev, "LT CR failed\n");
1015                         break;
1016                 case LT_EQ_TRAINING:
1017                         retval = rk32_edp_process_equalizer_training(edp);
1018                         if (retval)
1019                                 dev_err(edp->dev, "LT EQ failed\n");
1020                         break;
1021                 case FINISHED:
1022                         training_finished = 1;
1023                         break;
1024                 case FAILED:
1025                         return -EREMOTEIO;
1026                 }
1027         }
1028
1029         return retval;
1030 }
1031
1032 #else
1033 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
1034 {
1035         u32 cnt = 50;
1036         u32 val;
1037         /* Set link rate and count as you want to establish*/
1038         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1039         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1040         rk32_edp_hw_link_training_en(edp);
1041         val = rk32_edp_wait_hw_lt_done(edp);
1042         while (val) {
1043                 if (cnt-- <= 0) {
1044                         dev_err(edp->dev, "hw lt timeout");
1045                         return -ETIMEDOUT;
1046                 }
1047                 mdelay(1);
1048                 val = rk32_edp_wait_hw_lt_done(edp);
1049         }
1050
1051         val = rk32_edp_get_hw_lt_status(edp);
1052         if (val)
1053                 dev_err(edp->dev, "hw lt err:%d\n", val);
1054         return val;
1055 }
1056 #endif
1057
1058 static int rk32_edp_set_link_train(struct rk32_edp *edp)
1059 {
1060         int retval;
1061
1062         retval = rk32_edp_init_training(edp);
1063         if (retval < 0)
1064                 dev_err(edp->dev, "DP LT init failed!\n");
1065 #if defined(SW_LT)
1066         retval = rk32_edp_sw_link_training(edp);
1067 #else
1068         retval = rk32_edp_hw_link_training(edp);
1069 #endif
1070
1071         return retval;
1072 }
1073
1074 static int rk32_edp_config_video(struct rk32_edp *edp,
1075                                  struct video_info *video_info)
1076 {
1077         int retval = 0;
1078         int timeout_loop = 0;
1079         int done_count = 0;
1080
1081         rk32_edp_config_video_slave_mode(edp, video_info);
1082
1083         rk32_edp_set_video_color_format(edp, video_info->color_depth,
1084                                         video_info->color_space,
1085                                         video_info->dynamic_range,
1086                                         video_info->ycbcr_coeff);
1087
1088         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
1089                 dev_err(edp->dev, "PLL is not locked yet.\n");
1090                 return -EINVAL;
1091         }
1092
1093         for (;;) {
1094                 timeout_loop++;
1095                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
1096                         break;
1097                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1098                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1099                         return -ETIMEDOUT;
1100                 }
1101
1102                 udelay(1);
1103         }
1104
1105         /* Set to use the register calculated M/N video */
1106         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1107
1108         /* For video bist, Video timing must be generated by register */
1109 #ifndef EDP_BIST_MODE
1110         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
1111 #endif
1112         /* Disable video mute */
1113         rk32_edp_enable_video_mute(edp, 0);
1114
1115         /* Configure video slave mode */
1116         rk32_edp_enable_video_master(edp, 0);
1117
1118         /* Enable video */
1119         rk32_edp_start_video(edp);
1120
1121         timeout_loop = 0;
1122
1123         for (;;) {
1124                 timeout_loop++;
1125                 if (rk32_edp_is_video_stream_on(edp) == 0) {
1126                         done_count++;
1127                         if (done_count > 10)
1128                                 break;
1129                 } else if (done_count) {
1130                         done_count = 0;
1131                 }
1132                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1133                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1134                         return -ETIMEDOUT;
1135                 }
1136
1137                 mdelay(1);
1138         }
1139
1140         if (retval != 0)
1141                 dev_err(edp->dev, "Video stream is not detected!\n");
1142
1143         return retval;
1144 }
1145
1146 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1147 {
1148         struct rk32_edp *edp = arg;
1149         enum dp_irq_type irq_type;
1150
1151         irq_type = rk32_edp_get_irq_type(edp);
1152         switch (irq_type) {
1153         case DP_IRQ_TYPE_HP_CABLE_IN:
1154                 dev_info(edp->dev, "Received irq - cable in\n");
1155                 rk32_edp_clear_hotplug_interrupts(edp);
1156                 break;
1157         case DP_IRQ_TYPE_HP_CABLE_OUT:
1158                 dev_info(edp->dev, "Received irq - cable out\n");
1159                 rk32_edp_clear_hotplug_interrupts(edp);
1160                 break;
1161         case DP_IRQ_TYPE_HP_CHANGE:
1162                 /*
1163                  * We get these change notifications once in a while, but there
1164                  * is nothing we can do with them. Just ignore it for now and
1165                  * only handle cable changes.
1166                  */
1167                 dev_info(edp->dev, "Received irq - hotplug change; ignoring.\n");
1168                 rk32_edp_clear_hotplug_interrupts(edp);
1169                 break;
1170         default:
1171                 dev_err(edp->dev, "Received irq - unknown type!\n");
1172                 break;
1173         }
1174         return IRQ_HANDLED;
1175 }
1176
1177 static int rk32_edp_enable(void)
1178 {
1179         int ret = 0;
1180         struct rk32_edp *edp = rk32_edp;
1181
1182         if (!edp->edp_en) {
1183                 rk32_edp_clk_enable(edp);
1184                 rk32_edp_pre_init(edp);
1185                 rk32_edp_init_edp(edp);
1186                 enable_irq(edp->irq);
1187                 /*ret = rk32_edp_handle_edid(edp);
1188                 if (ret) {
1189                         dev_err(edp->dev, "unable to handle edid\n");
1190                         //goto out;
1191                 }
1192
1193                 ret = rk32_edp_enable_scramble(edp, 0);
1194                 if (ret) {
1195                         dev_err(edp->dev, "unable to set scramble\n");
1196                         //goto out;
1197                 }
1198
1199                 ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1200                 if (ret) {
1201                         dev_err(edp->dev, "unable to set enhanced mode\n");
1202                         //goto out;
1203                 }
1204                 rk32_edp_enable_enhanced_mode(edp, 1);*/
1205
1206                 ret = rk32_edp_set_link_train(edp);
1207                 if (ret)
1208                         dev_err(edp->dev, "link train failed!\n");
1209                 else
1210                         dev_info(edp->dev, "link training success.\n");
1211
1212                 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1213                 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1214                 rk32_edp_init_video(edp);
1215
1216 #ifdef EDP_BIST_MODE
1217                 rk32_edp_bist_cfg(edp);
1218 #endif
1219                 ret = rk32_edp_config_video(edp, &edp->video_info);
1220                 if (ret)
1221                         dev_err(edp->dev, "unable to config video\n");
1222
1223                 edp->edp_en = true;
1224         }
1225         return ret;
1226 }
1227
1228 static int  rk32_edp_disable(void)
1229 {
1230         struct rk32_edp *edp = rk32_edp;
1231
1232         if (edp->edp_en) {
1233                 disable_irq(edp->irq);
1234                 rk32_edp_reset(edp);
1235                 rk32_edp_analog_power_ctr(edp, 0);
1236                 rk32_edp_clk_disable(edp);
1237                 edp->edp_en = false;
1238         }
1239
1240         return 0;
1241 }
1242
1243
1244 static struct rk_fb_trsm_ops trsm_edp_ops = {
1245         .enable = rk32_edp_enable,
1246         .disable = rk32_edp_disable,
1247 };
1248
1249 /*#if 0
1250 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1251 {
1252         u8 data;
1253         int retval;
1254
1255         if (enable) {
1256                 rk32_edp_enable_scrambling(edp);
1257
1258                 retval = rk32_edp_read_byte_from_dpcd
1259                                 (edp,
1260                                  DPCD_TRAINING_PATTERN_SET,
1261                                  &data);
1262                 if (retval < 0)
1263                         return retval;
1264
1265                 retval = rk32_edp_write_byte_to_dpcd
1266                                 (edp,
1267                                  DPCD_TRAINING_PATTERN_SET,
1268                                  (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1269                 if (retval < 0)
1270                         return retval;
1271         } else {
1272                 rk32_edp_disable_scrambling(edp);
1273
1274                 retval = rk32_edp_read_byte_from_dpcd
1275                                 (edp,
1276                                  DPCD_TRAINING_PATTERN_SET,
1277                                  &data);
1278                 if (retval < 0)
1279                         return retval;
1280
1281                 retval = rk32_edp_write_byte_to_dpcd
1282                                 (edp,
1283                                  DPCD_TRAINING_PATTERN_SET,
1284                                  (u8)(data | DPCD_SCRAMBLING_DISABLED));
1285                 if (retval < 0)
1286                         return retval;
1287         }
1288
1289         return 0;
1290 }
1291 #endif*/
1292 static int rk32_edp_psr_enable(struct rk32_edp *edp)
1293 {
1294         u8 buf;
1295         int retval;
1296         char date, psr_version;
1297
1298         /*if support PSR*/
1299         retval = rk32_edp_read_byte_from_dpcd
1300                         (edp,
1301                          PANEL_SELF_REFRESH_CAPABILITY_SUPPORTED_AND_VERSION,
1302                          &psr_version);
1303         if (retval < 0) {
1304                 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1305                 return retval;
1306         } else {
1307                 pr_info("PSR supporter and version:%x\n", psr_version);
1308         }
1309
1310          /*PSR capabilities*/
1311         retval = rk32_edp_read_byte_from_dpcd
1312                         (edp,
1313                          PANEL_SELF_REFRESH_CAPABILITIES, &date);
1314         if (retval < 0) {
1315                 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1316                 return retval;
1317         } else {
1318                 pr_info("PSR capabilities:%x\n", date);
1319         }
1320
1321         if (psr_version & PSR_SUPPORT) {
1322                 pr_info("PSR config psr\n");
1323
1324                 /*config sink PSR*/
1325                 buf = 0x02;
1326                 retval = rk32_edp_write_bytes_to_dpcd(edp, PSR_ENABLE,
1327                                                       1, &buf);
1328                 if (retval < 0) {
1329                         dev_err(edp->dev, "PSR failed to config sink PSR!\n");
1330                         return retval;
1331                 } else {
1332                         /*enable the PSR*/
1333                         buf = 0x03;
1334                         retval = rk32_edp_write_bytes_to_dpcd(edp,
1335                                                               PSR_ENABLE,
1336                                                               1, &buf);
1337                         if (retval < 0) {
1338                                 dev_err(edp->dev, "PSR failed to enable the PSR!\n");
1339                                 return retval;
1340                         }
1341                         /*read sink config state*/
1342                         retval = rk32_edp_read_byte_from_dpcd
1343                                                 (edp,
1344                                                  PSR_ENABLE, &date);
1345                         if (retval < 0) {
1346                                 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1347                                 return retval;
1348                         } else {
1349                                 pr_info("PSR sink config state:%x\n", date);
1350                         }
1351                 }
1352
1353                 /*enable sink crc*/
1354                 retval = rk32_edp_read_byte_from_dpcd(edp, 0x270, &buf);
1355                 buf |= 0x01;
1356                 retval = rk32_edp_write_bytes_to_dpcd(edp, 0x270, 1, &buf);
1357         }
1358
1359                 return 0;
1360 }
1361 static int psr_header_HB_PB(struct rk32_edp *edp)
1362 {
1363         u32 val;
1364
1365         val = 0x0;
1366         writel(val, edp->regs + HB0);/*HB0*/
1367         val = 0x07;
1368         writel(val, edp->regs + HB1);/*HB1*/
1369         val = 0x02;
1370         writel(val, edp->regs + HB2);/*HB2*/
1371         val = 0x08;
1372         writel(val, edp->regs + HB3);/*HB3*/
1373         val = 0x00;
1374         writel(val, edp->regs + PB0);/*PB0*/
1375         val = 0x16;
1376         writel(val, edp->regs + PB1);/*PB1*/
1377         val = 0xce;
1378         writel(val, edp->regs + PB2);/*PB2*/
1379         val = 0x5d;
1380         writel(val, edp->regs + PB3);/*PB3*/
1381
1382         return 0;
1383 }
1384
1385 static int psr_enable_sdp(struct rk32_edp *edp)
1386 {
1387         u32 val;
1388
1389         val = readl(edp->regs + SPDIF_AUDIO_CTL_0);
1390         val |= 0x08;
1391         writel(val, edp->regs + SPDIF_AUDIO_CTL_0);/*enable SDP*/
1392         val = readl(edp->regs + SPDIF_AUDIO_CTL_0);
1393         pr_info("PSR reuse_spd_en:%x\n", val);
1394
1395         val = 0x83;
1396         writel(val, edp->regs + IF_TYPE);/*enable IF_TYPE*/
1397         val = readl(edp->regs + IF_TYPE);
1398         pr_info("PSR IF_TYPE :%x\n", val);
1399
1400         val = readl(edp->regs + PKT_SEND_CTL);
1401         val |= 0x10;
1402         writel(val, edp->regs + PKT_SEND_CTL);/*enable IF_UP*/
1403         val = readl(edp->regs + PKT_SEND_CTL);
1404         pr_info("PSR if_up :%x\n", val);
1405
1406         val = readl(edp->regs + PKT_SEND_CTL);
1407         val |= 0x01;
1408         writel(val, edp->regs + PKT_SEND_CTL);/*enable IF_EN*/
1409         val = readl(edp->regs + PKT_SEND_CTL);
1410         pr_info("PSR if_en:%x\n", val);
1411         return 0;
1412 }
1413 static int edp_disable_psr(struct rk32_edp *edp)
1414 {
1415         u8 buf;
1416         int retval;
1417         char date;
1418
1419         /*disable sink PSR*/
1420         retval = rk32_edp_read_byte_from_dpcd(edp,
1421                                               PSR_ENABLE, &date);
1422         if (retval < 0) {
1423                 dev_err(edp->dev, "PSR sink original config Read failed!\n");
1424                 return retval;
1425         }
1426         buf = date&0xfe;
1427         retval = rk32_edp_write_bytes_to_dpcd
1428                                         (edp,
1429                                          PSR_ENABLE,
1430                                          1, &buf);
1431         if (retval < 0) {
1432                 dev_err(edp->dev, "PSR failed to disable sink PSR!\n");
1433                 return retval;
1434         }
1435
1436         pr_info("PSR disable success!!\n");
1437         return 0;
1438 }
1439
1440 static int edp_psr_state(struct rk32_edp *edp, int state)
1441 {
1442                 u32 val;
1443                 /*wait for VD blank*/
1444                 if  (rk_fb_poll_wait_frame_complete()) {
1445                         psr_header_HB_PB(edp);
1446
1447                         val = state;
1448                         writel(val, edp->regs + DB1);
1449                         /*val = readl(edp->regs + DB1);
1450                         pr_info("PSR set DB1 state 0x0:%x\n", val);
1451
1452                         for (i = 0; i < 22; i++)
1453                                  writel(0, edp->regs + DB2 + 4 * i);*/
1454
1455                         psr_enable_sdp(edp);
1456                 }
1457         return 0;
1458 }
1459
1460
1461 static int phy_power_channel(struct rk32_edp *edp, int state)
1462 {
1463         u32 val;
1464
1465         val = state;
1466         writel(val, edp->regs + DP_PD);
1467
1468         return 0;
1469 }
1470
1471 #if defined(CONFIG_DEBUG_FS)
1472
1473 static int edp_dpcd_debugfs_show(struct seq_file *s, void *v)
1474 {
1475         int retval;
1476         unsigned char buf[12];
1477         struct rk32_edp *edp = s->private;
1478
1479         if (!edp) {
1480                 dev_err(edp->dev, "no edp device!\n");
1481                 return -ENODEV;
1482         }
1483
1484         retval = rk32_edp_read_byte_from_dpcd
1485                         (edp,
1486                          PANEL_SELF_REFRESH_CAPABILITY_SUPPORTED_AND_VERSION,
1487                          &buf[0]);
1488         seq_printf(s, "0x70 %x\n", buf[0]);
1489
1490         /*PSR capabilities*/
1491         retval = rk32_edp_read_byte_from_dpcd
1492                         (edp,
1493                          PANEL_SELF_REFRESH_CAPABILITIES, &buf[0]);
1494         seq_printf(s, "0x71 %x\n", buf[0]);
1495
1496         retval = rk32_edp_read_byte_from_dpcd
1497                         (edp,
1498                          PSR_ENABLE, &buf[0]);
1499         seq_printf(s, "0x170 %x\n", buf[0]);
1500
1501         retval = rk32_edp_read_byte_from_dpcd(edp, 0x2006, &buf[0]);
1502         seq_printf(s, "0x2006 %x\n", buf[0]);
1503
1504         retval = rk32_edp_read_byte_from_dpcd(edp, 0x2007, &buf[0]);
1505         seq_printf(s, "0x2007 %x\n", buf[0]);
1506
1507         retval = rk32_edp_read_byte_from_dpcd(edp, 0x2008, &buf[0]);
1508         seq_printf(s, "0x2008 %x\n", buf[0]);
1509         retval = rk32_edp_read_byte_from_dpcd(edp, 0x2009, &buf[0]);
1510         seq_printf(s, "0x2009 %x\n", buf[0]);
1511
1512         retval = rk32_edp_read_byte_from_dpcd(edp, 0x200a, &buf[0]);
1513         seq_printf(s, "0x200a %x\n", buf[0]);
1514
1515         retval = rk32_edp_read_byte_from_dpcd(edp, 0x240, &buf[0]);
1516         seq_printf(s, "0x240 %x\n", buf[0]);
1517         retval = rk32_edp_read_byte_from_dpcd(edp, 0x241, &buf[0]);
1518         seq_printf(s, "0x241 %x\n", buf[0]);
1519         retval = rk32_edp_read_byte_from_dpcd(edp, 0x242, &buf[0]);
1520         seq_printf(s, "0x242 %x\n", buf[0]);
1521         retval = rk32_edp_read_byte_from_dpcd(edp, 0x243, &buf[0]);
1522         seq_printf(s, "0x243 %x\n", buf[0]);
1523         retval = rk32_edp_read_byte_from_dpcd(edp, 0x244, &buf[0]);
1524         seq_printf(s, "0x244 %x\n", buf[0]);
1525         retval = rk32_edp_read_byte_from_dpcd(edp, 0x245, &buf[0]);
1526         seq_printf(s, "0x245 %x\n", buf[0]);
1527         retval = rk32_edp_read_byte_from_dpcd(edp, 0x270, &buf[0]);
1528         seq_printf(s, "0x270 %x\n", buf[0]);
1529         retval = rk32_edp_read_byte_from_dpcd(edp, 0x246, &buf[0]);
1530         seq_printf(s, "0x246 %x\n", buf[0]);
1531
1532         /*retval = rk32_edp_read_byte_from_dpcd(edp, 0x222, &buf[0]);
1533         seq_printf(s, "0x222 %x\n", buf[0]);
1534         retval = rk32_edp_read_byte_from_dpcd(edp, 0x223, &buf[0]);
1535         seq_printf(s, "0x223 %x\n", buf[0]);
1536         retval = rk32_edp_read_byte_from_dpcd(edp, 0x224, &buf[0]);
1537         seq_printf(s, "0x224 %x\n", buf[0]);
1538         retval = rk32_edp_read_byte_from_dpcd(edp, 0x225, &buf[0]);
1539         seq_printf(s, "0x225 %x\n", buf[0]);
1540         retval = rk32_edp_read_byte_from_dpcd(edp, 0x226, &buf[0]);
1541         seq_printf(s, "0x226 %x\n", buf[0]);
1542         retval = rk32_edp_read_byte_from_dpcd(edp, 0x227, &buf[0]);
1543         seq_printf(s, "0x227 %x\n", buf[0]);
1544         retval = rk32_edp_read_byte_from_dpcd(edp, 0x228, &buf[0]);
1545         seq_printf(s, "0x228 %x\n", buf[0]);
1546         retval = rk32_edp_read_byte_from_dpcd(edp, 0x229, &buf[0]);
1547         seq_printf(s, "0x229 %x\n", buf[0]);
1548         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22a, &buf[0]);
1549         seq_printf(s, "0x22a %x\n", buf[0]);
1550         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22b, &buf[0]);
1551         seq_printf(s, "0x22b %x\n", buf[0]);
1552         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22c, &buf[0]);
1553         seq_printf(s, "0x22c %x\n", buf[0]);
1554         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22d, &buf[0]);
1555         seq_printf(s, "0x22d %x\n", buf[0]);
1556         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22e, &buf[0]);
1557         seq_printf(s, "0x22e %x\n", buf[0]);
1558         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22f, &buf[0]);
1559         seq_printf(s, "0x22f %x\n", buf[0]);
1560         retval = rk32_edp_read_byte_from_dpcd(edp, 0x230, &buf[0]);
1561         seq_printf(s, "0x230 %x\n", buf[0]);
1562         retval = rk32_edp_read_byte_from_dpcd(edp, 0x231, &buf[0]);
1563         seq_printf(s, "0x231 %x\n", buf[0]);*/
1564
1565         /*rk32_edp_read_bytes_from_dpcd(edp,
1566                         DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
1567         for (i = 0; i < 12; i++)
1568                 seq_printf(s, "0x%02x>>0x%02x\n", 0x210 + i, buf[i]);*/
1569         return 0;
1570 }
1571
1572 static ssize_t edp_dpcd_write(struct file *file,
1573                               const char __user *buf,
1574                               size_t count,
1575                               loff_t *ppos)
1576 {
1577         return count;
1578 }
1579
1580 static int edp_edid_debugfs_show(struct seq_file *s, void *v)
1581 {
1582         struct rk32_edp *edp = s->private;
1583
1584         if (!edp) {
1585                 dev_err(edp->dev, "no edp device!\n");
1586                 return -ENODEV;
1587         }
1588         rk32_edp_read_edid(edp);
1589         seq_puts(s, "edid");
1590         return 0;
1591 }
1592
1593 static ssize_t edp_edid_write(struct file *file,
1594                               const char __user *buf,
1595                               size_t count,
1596                               loff_t *ppos)
1597 {
1598         struct rk32_edp *edp =
1599                 ((struct seq_file *)file->private_data)->private;
1600
1601         if (!edp) {
1602                 dev_err(edp->dev, "no edp device!\n");
1603                 return -ENODEV;
1604         }
1605         rk32_edp_disable();
1606         rk32_edp_enable();
1607         return count;
1608 }
1609
1610 static int edp_reg_debugfs_show(struct seq_file *s, void *v)
1611 {
1612         int i = 0;
1613         struct rk32_edp *edp = s->private;
1614
1615         if (!edp) {
1616                 dev_err(edp->dev, "no edp device!\n");
1617                 return -ENODEV;
1618         }
1619
1620         for (i = 0; i < 0x284; i++) {
1621                 if (!(i%4))
1622                         seq_printf(s, "\n%08x:  ", i*4);
1623                 seq_printf(s, "%08x ", readl(edp->regs + i*4));
1624         }
1625         return 0;
1626 }
1627
1628 static ssize_t edp_reg_write(struct file *file,
1629                              const char __user *buf, size_t count,
1630                              loff_t *ppos)
1631 {
1632         return count;
1633 }
1634
1635 static int edp_psr_debugfs_show(struct seq_file *s, void *v)
1636 {
1637         return 0;
1638 }
1639 static ssize_t edp_psr_write(struct file *file,
1640                              const char __user *buf,
1641                              size_t count, loff_t *ppos)
1642 {
1643         int a;
1644         char kbuf[25];
1645         int retval;
1646         struct rk32_edp *edp =
1647                 ((struct seq_file *)file->private_data)->private;
1648
1649         if (!edp) {
1650                 dev_err(edp->dev, "no edp device!\n");
1651                 return -ENODEV;
1652         }
1653         memset(kbuf, 0, 25);
1654         if (copy_from_user(kbuf, buf, count))
1655                 return -EFAULT;
1656         retval = kstrtoint(kbuf, 0, &a);
1657         if (retval)
1658                 return retval;
1659         /*retval = sscanf(kbuf, "%d", &a);
1660         if (retval < 0) {
1661                 dev_err(edp->dev, "PSR failed sscanf!\n");
1662                 return retval;
1663         }*/
1664         /*disable psr*/
1665         if (0 == a)
1666                 edp_disable_psr(edp);
1667         /*enable psr*/
1668         if (1 == a)
1669                 rk32_edp_psr_enable(edp);
1670         /*inactive psr*/
1671         if (2 == a)
1672                 edp_psr_state(edp, 0x0);
1673         /*sink state 2*/
1674         if  (3 == a)
1675                 edp_psr_state(edp, 0x01);
1676         /*sink state 3*/
1677         if  (4 == a)
1678                 edp_psr_state(edp, 0x03);
1679         /*open 4 lanes*/
1680         if  (5 == a) {
1681                 phy_power_channel(edp, 0xff);
1682                 usleep_range(9, 10);
1683                 phy_power_channel(edp, 0x7f);
1684                 usleep_range(9, 10);
1685                 phy_power_channel(edp, 0x0);
1686         }
1687         /*close 4 lanes*/
1688         if (6 == a) {
1689                 phy_power_channel(edp, 0x7f);
1690                 usleep_range(9, 10);
1691                 phy_power_channel(edp, 0x0f);
1692         }
1693
1694         return count;
1695 }
1696
1697 #define EDP_DEBUG_ENTRY(name) \
1698 static int edp_##name##_debugfs_open(struct inode *inode, struct file *file) \
1699 { \
1700         return single_open(file, edp_##name##_debugfs_show, inode->i_private); \
1701 } \
1702 \
1703 static const struct file_operations edp_##name##_debugfs_fops = { \
1704         .owner = THIS_MODULE, \
1705         .open = edp_##name##_debugfs_open, \
1706         .read = seq_read, \
1707         .write = edp_##name##_write,    \
1708         .llseek = seq_lseek, \
1709         .release = single_release, \
1710 }
1711
1712 EDP_DEBUG_ENTRY(psr);
1713 EDP_DEBUG_ENTRY(dpcd);
1714 EDP_DEBUG_ENTRY(edid);
1715 EDP_DEBUG_ENTRY(reg);
1716 #endif
1717
1718 static int rk32_edp_probe(struct platform_device *pdev)
1719 {
1720         struct rk32_edp *edp;
1721         struct resource *res;
1722         struct device_node *np = pdev->dev.of_node;
1723         int ret;
1724
1725         if (!np) {
1726                 dev_err(&pdev->dev, "Missing device tree node.\n");
1727                 return -EINVAL;
1728         }
1729
1730         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1731         if (!edp) {
1732                 dev_err(&pdev->dev, "no memory for state\n");
1733                 return -ENOMEM;
1734         }
1735         edp->dev = &pdev->dev;
1736         edp->video_info.h_sync_polarity = 0;
1737         edp->video_info.v_sync_polarity = 0;
1738         edp->video_info.interlaced      = 0;
1739         edp->video_info.color_space     = CS_RGB;
1740         edp->video_info.dynamic_range   = VESA;
1741         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1742         edp->video_info.color_depth     = COLOR_8;
1743
1744         edp->video_info.link_rate       = LINK_RATE_1_62GBPS;
1745         edp->video_info.lane_count      = LANE_CNT4;
1746         rk_fb_get_prmry_screen(&edp->screen);
1747         if (edp->screen.type != SCREEN_EDP) {
1748                 dev_err(&pdev->dev, "screen is not edp!\n");
1749                 return -EINVAL;
1750         }
1751
1752         edp->soctype = (unsigned long)of_device_get_match_data(&pdev->dev);
1753
1754         platform_set_drvdata(pdev, edp);
1755         dev_set_name(edp->dev, "rk32-edp");
1756
1757         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1758         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1759         if (IS_ERR(edp->regs)) {
1760                 dev_err(&pdev->dev, "ioremap reg failed\n");
1761                 return PTR_ERR(edp->regs);
1762         }
1763
1764         edp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1765         if (IS_ERR(edp->grf) && !cpu_is_rk3288()) {
1766                 dev_err(&pdev->dev, "can't find rockchip,grf property\n");
1767                 return PTR_ERR(edp->grf);
1768         }
1769
1770         edp->pd = devm_clk_get(&pdev->dev, "pd_edp");
1771         if (IS_ERR(edp->pd)) {
1772                 dev_err(&pdev->dev, "cannot get pd\n");
1773                 edp->pd = NULL;
1774         }
1775
1776         edp->clk_edp = devm_clk_get(&pdev->dev, "clk_edp");
1777         if (IS_ERR(edp->clk_edp)) {
1778                 dev_err(&pdev->dev, "cannot get clk_edp\n");
1779                 return PTR_ERR(edp->clk_edp);
1780         }
1781
1782         if (edp->soctype != SOC_RK3399) {
1783                 edp->clk_24m = devm_clk_get(&pdev->dev, "clk_edp_24m");
1784                 if (IS_ERR(edp->clk_24m)) {
1785                         dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1786                         return PTR_ERR(edp->clk_24m);
1787                 }
1788         }
1789
1790         edp->pclk = devm_clk_get(&pdev->dev, "pclk_edp");
1791         if (IS_ERR(edp->pclk)) {
1792                 dev_err(&pdev->dev, "cannot get pclk\n");
1793                 return PTR_ERR(edp->pclk);
1794         }
1795
1796         /* We use the reset API to control the software reset at this version
1797          * and later, and we reserve the code that setting the cru regs directly
1798          * in the rk3288.
1799          */
1800         if (edp->soctype != SOC_RK3399) {
1801                 /*edp 24m need sorft reset*/
1802                 edp->rst_24m = devm_reset_control_get(&pdev->dev, "edp_24m");
1803                 if (IS_ERR(edp->rst_24m))
1804                         dev_err(&pdev->dev, "failed to get reset\n");
1805         }
1806
1807         /* edp ctrl apb bus need sorft reset */
1808         edp->rst_apb = devm_reset_control_get(&pdev->dev, "edp_apb");
1809         if (IS_ERR(edp->rst_apb))
1810                 dev_err(&pdev->dev, "failed to get reset\n");
1811         rk32_edp_clk_enable(edp);
1812         if (!support_uboot_display())
1813                 rk32_edp_pre_init(edp);
1814         edp->irq = platform_get_irq(pdev, 0);
1815         if (edp->irq < 0) {
1816                 dev_err(&pdev->dev, "cannot find IRQ\n");
1817                 return edp->irq;
1818         }
1819         ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1820                                dev_name(&pdev->dev), edp);
1821         if (ret) {
1822                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1823                 return ret;
1824         }
1825         disable_irq_nosync(edp->irq);
1826         if (!support_uboot_display())
1827                 rk32_edp_clk_disable(edp);
1828         rk32_edp = edp;
1829         rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1830 #if defined(CONFIG_DEBUG_FS)
1831         edp->debugfs_dir = debugfs_create_dir("edp", NULL);
1832         if (IS_ERR(edp->debugfs_dir)) {
1833                 dev_err(edp->dev, "failed to create debugfs dir for edp!\n");
1834         } else {
1835                 debugfs_create_file("dpcd", S_IRUSR, edp->debugfs_dir,
1836                                     edp, &edp_dpcd_debugfs_fops);
1837                 debugfs_create_file("edid", S_IRUSR, edp->debugfs_dir,
1838                                     edp, &edp_edid_debugfs_fops);
1839                 debugfs_create_file("reg", S_IRUSR, edp->debugfs_dir,
1840                                     edp, &edp_reg_debugfs_fops);
1841                 debugfs_create_file("psr", S_IRUSR, edp->debugfs_dir,
1842                                     edp, &edp_psr_debugfs_fops);
1843         }
1844
1845 #endif
1846         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1847
1848         return 0;
1849 }
1850
1851 static void rk32_edp_shutdown(struct platform_device *pdev)
1852 {
1853 }
1854
1855 #if defined(CONFIG_OF)
1856 static const struct of_device_id rk32_edp_dt_ids[] = {
1857         {.compatible = "rockchip,rk32-edp", .data = (void *)SOC_COMMON},
1858         {.compatible = "rockchip,rk3399-edp-fb", .data = (void *)SOC_RK3399},
1859         {}
1860 };
1861
1862 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1863 #endif
1864
1865 static struct platform_driver rk32_edp_driver = {
1866         .probe = rk32_edp_probe,
1867         .driver = {
1868                    .name = "rk32-edp",
1869                    .owner = THIS_MODULE,
1870 #if defined(CONFIG_OF)
1871                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1872 #endif
1873         },
1874         .shutdown = rk32_edp_shutdown,
1875 };
1876
1877 static int __init rk32_edp_module_init(void)
1878 {
1879         return platform_driver_register(&rk32_edp_driver);
1880 }
1881
1882 static void __exit rk32_edp_module_exit(void)
1883 {
1884 }
1885
1886 fs_initcall(rk32_edp_module_init);
1887 module_exit(rk32_edp_module_exit);