drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/rockchip/cpu.h>
  24 #include <linux/rockchip/iomap.h>
  25 #include <linux/rockchip/grf.h>
  26 #include <linux/string.h>
  27 #include <linux/slab.h>
  28 #include <linux/uaccess.h>
  29
  30 #if defined(CONFIG_OF)
  31 #include <linux/of.h>
  32 #endif
  33
  34 #if defined(CONFIG_DEBUG_FS)
  35 #include <linux/fs.h>
  36 #include <linux/debugfs.h>
  37 #include <linux/seq_file.h>
  38 #endif
  39
  40 #include "rk32_dp.h"
  41
  42 /*#define EDP_BIST_MODE*/
  43 /*#define SW_LT*/
  44
  45 #define RK3368_GRF_SOC_CON4     0x410
  46
  47 static struct rk32_edp *rk32_edp;
  48
  49 static int rk32_edp_clk_enable(struct rk32_edp *edp)
  50 {
  51         int ret;
  52
  53         if (!edp->clk_on) {
  54                 if (edp->pd)
  55                         clk_prepare_enable(edp->pd);
  56                 clk_prepare_enable(edp->pclk);
  57                 clk_prepare_enable(edp->clk_edp);
  58                 ret = clk_set_rate(edp->clk_24m, 24000000);
  59                 if (ret < 0)
  60                         dev_err(edp->dev, "cannot set edp clk_24m %d\n", ret);
  61                 clk_prepare_enable(edp->clk_24m);
  62                 edp->clk_on = true;
  63         }
  64
  65         return 0;
  66 }
  67
  68 static int rk32_edp_clk_disable(struct rk32_edp *edp)
  69 {
  70         if (edp->clk_on) {
  71                 clk_disable_unprepare(edp->pclk);
  72                 clk_disable_unprepare(edp->clk_edp);
  73                 clk_disable_unprepare(edp->clk_24m);
  74                 if (edp->pd)
  75                         clk_disable_unprepare(edp->pd);
  76                 edp->clk_on = false;
  77         }
  78
  79         return 0;
  80 }
  81
  82 static int rk32_edp_pre_init(struct rk32_edp *edp)
  83 {
  84         u32 val;
  85
  86         if (cpu_is_rk3288()) {
  87                 val = GRF_EDP_REF_CLK_SEL_INTER |
  88                         (GRF_EDP_REF_CLK_SEL_INTER << 16);
  89                 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
  90
  91                 val = 0x80008000;
  92                 writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
  93                 dsb(sy);
  94                 udelay(1);
  95                 val = 0x80000000;
  96                 writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
  97                 dsb(sy);
  98                 udelay(1);
  99         } else {
 100                 /* The rk3368 reset the edp 24M clock and apb bus
 101                  * according to the CRU_SOFTRST6_CON and CRU_SOFTRST7_CON.
 102                  */
 103                 val = 0x01 | (0x01 << 16);
 104                 regmap_write(edp->grf, RK3368_GRF_SOC_CON4, val);
 105
 106                 reset_control_assert(edp->rst_24m);
 107                 usleep_range(10, 20);
 108                 reset_control_deassert(edp->rst_24m);
 109
 110                 reset_control_assert(edp->rst_apb);
 111                 usleep_range(10, 20);
 112                 reset_control_deassert(edp->rst_apb);
 113         }
 114         return 0;
 115 }
 116
 117 static int rk32_edp_init_edp(struct rk32_edp *edp)
 118 {
 119         struct rk_screen *screen = &edp->screen;
 120         u32 val = 0;
 121
 122         rk_fb_get_prmry_screen(screen);
 123
 124         if (cpu_is_rk3288()) {
 125                 if (screen->lcdc_id == 1)  /*select lcdc*/
 126                         val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
 127                 else
 128                         val = EDP_SEL_VOP_LIT << 16;
 129                 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
 130         }
 131
 132         rk32_edp_reset(edp);
 133         rk32_edp_init_refclk(edp);
 134         rk32_edp_init_interrupt(edp);
 135         rk32_edp_enable_sw_function(edp);
 136         rk32_edp_init_analog_func(edp);
 137         rk32_edp_init_hpd(edp);
 138         rk32_edp_init_aux(edp);
 139
 140         return 0;
 141 }
 142
 143 /*#if 0
 144 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
 145 {
 146         int timeout_loop = 0;
 147
 148         rk32_edp_init_hpd(edp);
 149
 150         udelay(200);
 151
 152         while (rk32_edp_get_plug_in_status(edp) != 0) {
 153                 timeout_loop++;
 154                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 155                         dev_err(edp->dev, "failed to get hpd plug status\n");
 156                         return -ETIMEDOUT;
 157                 }
 158                 udelay(10);
 159         }
 160
 161         return 0;
 162 }
 163 #endif*/
 164
 165 static int rk32_edp_read_edid(struct rk32_edp *edp)
 166 {
 167         unsigned char edid[EDID_LENGTH * 2];
 168         unsigned int extend_block = 0;
 169         unsigned char sum;
 170         unsigned char test_vector;
 171         int retval;
 172
 173         /*
 174          * EDID device address is 0x50.
 175          * However, if necessary, you must have set upper address
 176          * into E-EDID in I2C device, 0x30.
 177          */
 178
 179         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 180         retval = rk32_edp_read_byte_from_i2c
 181                         (edp,
 182                          EDID_ADDR, EDID_EXTENSION_FLAG, &extend_block);
 183         if (retval < 0) {
 184                 dev_err(edp->dev, "EDID extension flag failed!\n");
 185                 return -EIO;
 186         }
 187
 188         if (extend_block > 0) {
 189                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
 190
 191                 /* Read EDID data */
 192                 retval = rk32_edp_read_bytes_from_i2c
 193                                (edp,
 194                                 EDID_ADDR, EDID_HEADER,
 195                                 EDID_LENGTH, &edid[EDID_HEADER]);
 196                 if (retval != 0) {
 197                         dev_err(edp->dev, "EDID Read failed!\n");
 198                         return -EIO;
 199                 }
 200                 sum = edp_calc_edid_check_sum(edid);
 201                 if (sum != 0) {
 202                         dev_warn(edp->dev, "EDID bad checksum!\n");
 203                         return 0;
 204                 }
 205
 206                 /* Read additional EDID data */
 207                 retval = rk32_edp_read_bytes_from_i2c
 208                                (edp,
 209                                 EDID_ADDR, EDID_LENGTH,
 210                                 EDID_LENGTH, &edid[EDID_LENGTH]);
 211                 if (retval != 0) {
 212                         dev_err(edp->dev, "EDID Read failed!\n");
 213                         return -EIO;
 214                 }
 215                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
 216                 if (sum != 0) {
 217                         dev_warn(edp->dev, "EDID bad checksum!\n");
 218                         return 0;
 219                 }
 220
 221                 retval = rk32_edp_read_byte_from_dpcd
 222                                 (edp,
 223                                  DPCD_TEST_REQUEST, &test_vector);
 224                 if (retval < 0) {
 225                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 226                         return retval;
 227                 }
 228
 229                 if (test_vector & DPCD_TEST_EDID_READ) {
 230                         retval = rk32_edp_write_byte_to_dpcd
 231                                        (edp,
 232                                         DPCD_TEST_EDID_CHECKSUM,
 233                                         edid[EDID_LENGTH + EDID_CHECKSUM]);
 234                         if (retval < 0) {
 235                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 236                                 return retval;
 237                         }
 238                         retval = rk32_edp_write_byte_to_dpcd
 239                                        (edp,
 240                                         DPCD_TEST_RESPONSE,
 241                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 242                         if (retval < 0) {
 243                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 244                                 return retval;
 245                         }
 246                 }
 247         } else {
 248                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 249
 250                 /* Read EDID data */
 251                 retval = rk32_edp_read_bytes_from_i2c
 252                                (edp,
 253                                 EDID_ADDR, EDID_HEADER,
 254                                 EDID_LENGTH, &edid[EDID_HEADER]);
 255                 if (retval != 0) {
 256                         dev_err(edp->dev, "EDID Read failed!\n");
 257                         return -EIO;
 258                 }
 259                 sum = edp_calc_edid_check_sum(edid);
 260                 if (sum != 0) {
 261                         dev_warn(edp->dev, "EDID bad checksum!\n");
 262                         return 0;
 263                 }
 264
 265                 retval = rk32_edp_read_byte_from_dpcd
 266                                 (edp,
 267                                  DPCD_TEST_REQUEST, &test_vector);
 268                 if (retval < 0) {
 269                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 270                         return retval;
 271                 }
 272
 273                 if (test_vector & DPCD_TEST_EDID_READ) {
 274                         retval = rk32_edp_write_byte_to_dpcd
 275                                         (edp,
 276                                          DPCD_TEST_EDID_CHECKSUM,
 277                                          edid[EDID_CHECKSUM]);
 278                         if (retval < 0) {
 279                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 280                                 return retval;
 281                         }
 282                         retval = rk32_edp_write_byte_to_dpcd
 283                                        (edp,
 284                                         DPCD_TEST_RESPONSE,
 285                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 286                         if (retval < 0) {
 287                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 288                                 return retval;
 289                         }
 290                 }
 291         }
 292         fb_edid_to_monspecs(edid, &edp->specs);
 293         dev_err(edp->dev, "EDID Read success!\n");
 294         return 0;
 295 }
 296 #define open_t 0
 297 #if open_t
 298 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 299 {
 300         u8 buf[12];
 301         int i;
 302         int retval;
 303
 304         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 305         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
 306         if (retval < 0)
 307                 return retval;
 308
 309         for (i = 0; i < 12; i++)
 310                 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
 311         /* Read EDID */
 312         for (i = 0; i < 3; i++) {
 313                 retval = rk32_edp_read_edid(edp);
 314                 if (retval == 0)
 315                         break;
 316         }
 317
 318         return retval;
 319 }
 320
 321
 322 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 323                                                bool enable)
 324 {
 325         u8 data;
 326         int retval;
 327
 328         retval = rk32_edp_read_byte_from_dpcd
 329                         (edp,
 330                          DPCD_LANE_CNT_SET, &data);
 331         if (retval < 0)
 332                 return retval;
 333
 334         if (enable) {
 335                 retval = rk32_edp_write_byte_to_dpcd
 336                                 (edp,
 337                                  DPCD_LANE_CNT_SET,
 338                                  DPCD_ENHANCED_FRAME_EN |
 339                                  DPCD_LANE_COUNT_SET(data));
 340         } else {
 341                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 342                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 343
 344                 retval = rk32_edp_write_byte_to_dpcd
 345                                 (edp,
 346                                  DPCD_LANE_CNT_SET,
 347                                  DPCD_LANE_COUNT_SET(data));
 348         }
 349
 350         return retval;
 351 }
 352
 353 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 354 {
 355         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 356         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 357
 358         if (enable) {
 359                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 360                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 361         } else {
 362                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 363         }*/
 364 }
 365
 366
 367 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 368 {
 369         u8 data;
 370         int retval;
 371
 372         retval = rk32_edp_read_byte_from_dpcd
 373                         (edp,
 374                          DPCD_MAX_LANE_CNT, &data);
 375         if (retval < 0)
 376                 return retval;
 377
 378         return DPCD_ENHANCED_FRAME_CAP(data);
 379 }
 380
 381
 382 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 383 {
 384         /*rk32_edp_write_byte_to_dpcd(edp,
 385                         DPCD_ADDR_USER_DEFINED1, 0);
 386         rk32_edp_write_byte_to_dpcd(edp,
 387                         DPCD_ADDR_USER_DEFINED2, 0x83);
 388         rk32_edp_write_byte_to_dpcd(edp,
 389                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 390 }
 391
 392 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 393 {
 394         u8 data;
 395         int retval;
 396
 397         retval = rk32_edp_is_enhanced_mode_available(edp);
 398         if (retval < 0)
 399                 return retval;
 400
 401         data = (u8)retval;
 402         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 403         if (retval < 0)
 404                 return retval;
 405
 406         rk32_edp_enable_enhanced_mode(edp, data);
 407
 408         return 0;
 409 }
 410 #endif
 411
 412
 413 #if defined(SW_LT)
 414 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 415 {
 416         int retval;
 417
 418         rk32_edp_set_training_pattern(edp, DP_NONE);
 419
 420         retval = rk32_edp_write_byte_to_dpcd(edp,
 421                                              DPCD_TRAINING_PATTERN_SET,
 422                                              DPCD_TRAINING_PATTERN_DISABLED);
 423         if (retval < 0)
 424                 return retval;
 425
 426         return 0;
 427 }
 428
 429 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 430                                                 int pre_emphasis, int lane)
 431 {
 432         switch (lane) {
 433         case 0:
 434                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 435                 break;
 436         case 1:
 437                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 438                 break;
 439
 440         case 2:
 441                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 442                 break;
 443
 444         case 3:
 445                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 446                 break;
 447         }
 448 }
 449
 450 static int rk32_edp_link_start(struct rk32_edp *edp)
 451 {
 452         u8 buf[4];
 453         int lane;
 454         int lane_count;
 455         int retval;
 456
 457         lane_count = edp->link_train.lane_count;
 458
 459         edp->link_train.lt_state = LT_CLK_RECOVERY;
 460         edp->link_train.eq_loop = 0;
 461
 462         for (lane = 0; lane < lane_count; lane++)
 463                 edp->link_train.cr_loop[lane] = 0;
 464
 465         /* Set sink to D0 (Sink Not Ready) mode. */
 466         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
 467                                              DPCD_SET_POWER_STATE_D0);
 468         if (retval < 0) {
 469                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 470                 return retval;
 471         }
 472
 473         /* Set link rate and count as you want to establish*/
 474         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 475         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 476
 477         /* Setup RX configuration */
 478         buf[0] = edp->link_train.link_rate;
 479         buf[1] = edp->link_train.lane_count;
 480         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
 481                                               2, buf);
 482         if (retval < 0) {
 483                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 484                 return retval;
 485         }
 486
 487         /* Set TX pre-emphasis to level1 */
 488         for (lane = 0; lane < lane_count; lane++)
 489                 rk32_edp_set_lane_lane_pre_emphasis
 490                         (edp,
 491                          PRE_EMPHASIS_LEVEL_1, lane);
 492
 493         /* Set training pattern 1 */
 494         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 495
 496         /* Set RX training pattern */
 497         retval = rk32_edp_write_byte_to_dpcd(edp,
 498                                              DPCD_TRAINING_PATTERN_SET,
 499                                              DPCD_SCRAMBLING_DISABLED |
 500                                              DPCD_TRAINING_PATTERN_1);
 501         if (retval < 0) {
 502                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 503                 return retval;
 504         }
 505
 506         for (lane = 0; lane < lane_count; lane++)
 507                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 508                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 509         retval = rk32_edp_write_bytes_to_dpcd(edp,
 510                                               DPCD_TRAINING_LANE0_SET,
 511                                               lane_count, buf);
 512         if (retval < 0) {
 513                 dev_err(edp->dev, "failed to set training lane!\n");
 514                 return retval;
 515         }
 516
 517         return 0;
 518 }
 519
 520 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 521 {
 522         int shift = (lane & 1) * 4;
 523         u8 link_value = link_status[lane>>1];
 524
 525         return (link_value >> shift) & 0xf;
 526 }
 527
 528 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 529 {
 530         int lane;
 531         u8 lane_status;
 532
 533         for (lane = 0; lane < lane_count; lane++) {
 534                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 535                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 536                         return -EINVAL;
 537         }
 538         return 0;
 539 }
 540
 541 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 542 {
 543         int lane;
 544         u8 lane_align;
 545         u8 lane_status;
 546
 547         lane_align = link_align[2];
 548         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 549                 return -EINVAL;
 550
 551         for (lane = 0; lane < lane_count; lane++) {
 552                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 553                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 554                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 555                         return -EINVAL;
 556         }
 557
 558         return 0;
 559 }
 560
 561 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 562                                                          int lane)
 563 {
 564         int shift = (lane & 1) * 4;
 565         u8 link_value = adjust_request[lane>>1];
 566
 567         return (link_value >> shift) & 0x3;
 568 }
 569
 570 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 571                                         u8 adjust_request[2],
 572                                         int lane)
 573 {
 574         int shift = (lane & 1) * 4;
 575         u8 link_value = adjust_request[lane>>1];
 576
 577         return ((link_value >> shift) & 0xc) >> 2;
 578 }
 579
 580 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 581                                             u8 training_lane_set, int lane)
 582 {
 583         switch (lane) {
 584         case 0:
 585                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 586                 break;
 587         case 1:
 588                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 589                 break;
 590
 591         case 2:
 592                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 593                 break;
 594
 595         case 3:
 596                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 597                 break;
 598         }
 599 }
 600
 601 static unsigned int rk32_edp_get_lane_link_training(
 602                                                     struct rk32_edp *edp,
 603                                                     int lane)
 604 {
 605         u32 reg;
 606
 607         switch (lane) {
 608         case 0:
 609                 reg = rk32_edp_get_lane0_link_training(edp);
 610                 break;
 611         case 1:
 612                 reg = rk32_edp_get_lane1_link_training(edp);
 613                 break;
 614         case 2:
 615                 reg = rk32_edp_get_lane2_link_training(edp);
 616                 break;
 617         case 3:
 618                 reg = rk32_edp_get_lane3_link_training(edp);
 619                 break;
 620         }
 621
 622         return reg;
 623 }
 624
 625 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 626 {
 627         rk32_edp_training_pattern_dis(edp);
 628
 629         edp->link_train.lt_state = FAILED;
 630 }
 631
 632 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 633 {
 634         u8 link_status[2];
 635         int lane;
 636         int lane_count;
 637
 638         u8 adjust_request[2];
 639         u8 voltage_swing;
 640         u8 pre_emphasis;
 641         u8 training_lane;
 642         int retval;
 643
 644         /*udelay(100);*/
 645         usleep_range(99, 100);
 646
 647         lane_count = edp->link_train.lane_count;
 648
 649         retval = rk32_edp_read_bytes_from_dpcd(edp,
 650                                                DPCD_LANE0_1_STATUS,
 651                                                2, link_status);
 652         if (retval < 0) {
 653                 dev_err(edp->dev, "failed to read lane status!\n");
 654                 return retval;
 655         }
 656
 657         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 658                 /* set training pattern 2 for EQ */
 659                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 660
 661                 for (lane = 0; lane < lane_count; lane++) {
 662                         retval = rk32_edp_read_bytes_from_dpcd
 663                                         (edp,
 664                                          DPCD_ADJUST_REQUEST_LANE0_1,
 665                                          2, adjust_request);
 666                         if (retval < 0) {
 667                                 dev_err(edp->dev, "failed to read adjust request!\n");
 668                                 return retval;
 669                         }
 670
 671                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 672                                                         adjust_request, lane);
 673                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 674                                                         adjust_request, lane);
 675                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 676                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 677
 678                         if (voltage_swing == VOLTAGE_LEVEL_3)
 679                                 training_lane |= DPCD_MAX_SWING_REACHED;
 680                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 681                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 682
 683                         edp->link_train.training_lane[lane] = training_lane;
 684
 685                         rk32_edp_set_lane_link_training
 686                                 (edp,
 687                                  edp->link_train.training_lane[lane],
 688                                  lane);
 689                 }
 690
 691                 retval = rk32_edp_write_byte_to_dpcd(edp,
 692                                                      DPCD_TRAINING_PATTERN_SET,
 693                                                      DPCD_SCRAMBLING_DISABLED |
 694                                                      DPCD_TRAINING_PATTERN_2);
 695                 if (retval < 0) {
 696                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 697                         return retval;
 698                 }
 699
 700                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 701                                                       DPCD_TRAINING_LANE0_SET,
 702                                                       lane_count,
 703                                 edp->link_train.training_lane);
 704                 if (retval < 0) {
 705                         dev_err(edp->dev, "failed to set training lane!\n");
 706                         return retval;
 707                 }
 708
 709                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 710                 edp->link_train.lt_state = LT_EQ_TRAINING;
 711         } else {
 712                 for (lane = 0; lane < lane_count; lane++) {
 713                         training_lane = rk32_edp_get_lane_link_training(
 714                                                         edp, lane);
 715                         retval = rk32_edp_read_bytes_from_dpcd
 716                                         (edp,
 717                                          DPCD_ADJUST_REQUEST_LANE0_1,
 718                                          2, adjust_request);
 719                         if (retval < 0) {
 720                                 dev_err(edp->dev, "failed to read adjust request!\n");
 721                                 return retval;
 722                         }
 723
 724                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 725                                                         adjust_request, lane);
 726                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 727                                                         adjust_request, lane);
 728
 729                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 730                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 731                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 732                                 goto reduce_link_rate;
 733                         }
 734
 735                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 736                                         voltage_swing) &&
 737                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 738                                         pre_emphasis)) {
 739                                 edp->link_train.cr_loop[lane]++;
 740                                 if (edp->link_train.cr_loop[lane] ==
 741                                         MAX_CR_LOOP) {
 742                                         dev_err(edp->dev, "CR Max loop\n");
 743                                         goto reduce_link_rate;
 744                                 }
 745                         }
 746
 747                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 748                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 749
 750                         if (voltage_swing == VOLTAGE_LEVEL_3)
 751                                 training_lane |= DPCD_MAX_SWING_REACHED;
 752                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 753                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 754
 755                         edp->link_train.training_lane[lane] = training_lane;
 756
 757                         rk32_edp_set_lane_link_training
 758                                 (edp,
 759                                  edp->link_train.training_lane[lane], lane);
 760                 }
 761
 762                 retval = rk32_edp_write_bytes_to_dpcd
 763                                 (edp,
 764                                  DPCD_TRAINING_LANE0_SET,
 765                                  lane_count,
 766                                  edp->link_train.training_lane);
 767                 if (retval < 0) {
 768                         dev_err(edp->dev, "failed to set training lane!\n");
 769                         return retval;
 770                 }
 771         }
 772
 773         return 0;
 774
 775 reduce_link_rate:
 776         rk32_edp_reduce_link_rate(edp);
 777         return -EIO;
 778 }
 779
 780 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 781 {
 782         u8 link_status[2];
 783         u8 link_align[3];
 784         int lane;
 785         int lane_count;
 786         u32 reg;
 787
 788         u8 adjust_request[2];
 789         u8 voltage_swing;
 790         u8 pre_emphasis;
 791         u8 training_lane;
 792         int retval;
 793
 794         /*udelay(400);*/
 795         usleep_range(399, 400);
 796
 797         lane_count = edp->link_train.lane_count;
 798
 799         retval = rk32_edp_read_bytes_from_dpcd(edp,
 800                                                DPCD_LANE0_1_STATUS,
 801                                                2, link_status);
 802         if (retval < 0) {
 803                 dev_err(edp->dev, "failed to read lane status!\n");
 804                 return retval;
 805         }
 806
 807         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 808                 link_align[0] = link_status[0];
 809                 link_align[1] = link_status[1];
 810
 811                 retval = rk32_edp_read_byte_from_dpcd
 812                                 (edp,
 813                                  DPCD_LANE_ALIGN_STATUS_UPDATED,
 814                                  &link_align[2]);
 815                 if (retval < 0) {
 816                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 817                         return retval;
 818                 }
 819
 820                 for (lane = 0; lane < lane_count; lane++) {
 821                         retval = rk32_edp_read_bytes_from_dpcd
 822                                         (edp,
 823                                          DPCD_ADJUST_REQUEST_LANE0_1,
 824                                          2, adjust_request);
 825                         if (retval < 0) {
 826                                 dev_err(edp->dev, "failed to read adjust request!\n");
 827                                 return retval;
 828                         }
 829
 830                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 831                                                         adjust_request, lane);
 832                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 833                                                         adjust_request, lane);
 834                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 835                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 836
 837                         if (voltage_swing == VOLTAGE_LEVEL_3)
 838                                 training_lane |= DPCD_MAX_SWING_REACHED;
 839                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 840                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 841
 842                         edp->link_train.training_lane[lane] = training_lane;
 843                 }
 844
 845                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 846                         /* traing pattern Set to Normal */
 847                         retval = rk32_edp_training_pattern_dis(edp);
 848                         if (retval < 0) {
 849                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 850                                 return retval;
 851                         }
 852
 853                         dev_info(edp->dev, "Link Training success!\n");
 854
 855                         rk32_edp_get_link_bandwidth(edp, &reg);
 856                         edp->link_train.link_rate = reg;
 857                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 858                                 edp->link_train.link_rate);
 859
 860                         rk32_edp_get_lane_count(edp, &reg);
 861                         edp->link_train.lane_count = reg;
 862                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 863                                 edp->link_train.lane_count);
 864
 865                         edp->link_train.lt_state = FINISHED;
 866                 } else {
 867                         /* not all locked */
 868                         edp->link_train.eq_loop++;
 869
 870                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 871                                 dev_err(edp->dev, "EQ Max loop\n");
 872                                 goto reduce_link_rate;
 873                         }
 874
 875                         for (lane = 0; lane < lane_count; lane++)
 876                                 rk32_edp_set_lane_link_training
 877                                 (edp,
 878                                  edp->link_train.training_lane[lane],
 879                                  lane);
 880
 881                         retval = rk32_edp_write_bytes_to_dpcd
 882                                         (edp,
 883                                          DPCD_TRAINING_LANE0_SET,
 884                                          lane_count,
 885                                          edp->link_train.training_lane);
 886                         if (retval < 0) {
 887                                 dev_err(edp->dev, "failed to set training lane!\n");
 888                                 return retval;
 889                         }
 890                 }
 891         } else {
 892                 goto reduce_link_rate;
 893         }
 894
 895         return 0;
 896
 897 reduce_link_rate:
 898         rk32_edp_reduce_link_rate(edp);
 899         return -EIO;
 900 }
 901 #endif
 902 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 903                                          u8 *bandwidth)
 904 {
 905         u8 data;
 906         int retval = 0;
 907
 908         /*
 909          * For DP rev.1.1, Maximum link rate of Main Link lanes
 910          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 911          */
 912         retval = rk32_edp_read_byte_from_dpcd(edp,
 913                                               DPCD_MAX_LINK_RATE, &data);
 914         if (retval < 0)
 915                 *bandwidth = 0;
 916         else
 917                 *bandwidth = data;
 918         return retval;
 919 }
 920
 921 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 922                                           u8 *lane_count)
 923 {
 924         u8 data;
 925         int retval;
 926
 927         /*
 928          * For DP rev.1.1, Maximum number of Main Link lanes
 929          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 930          */
 931         retval = rk32_edp_read_byte_from_dpcd(edp,
 932                                               DPCD_MAX_LANE_CNT, &data);
 933         if (retval < 0)
 934                 *lane_count = 0;
 935         else
 936                 *lane_count = DPCD_MAX_LANE_COUNT(data);
 937         return retval;
 938 }
 939
 940 static int rk32_edp_init_training(struct rk32_edp *edp)
 941 {
 942         int retval;
 943
 944         /*
 945          * MACRO_RST must be applied after the PLL_LOCK to avoid
 946          * the DP inter pair skew issue for at least 10 us
 947          */
 948         rk32_edp_reset_macro(edp);
 949
 950
 951         retval = rk32_edp_get_max_rx_bandwidth(edp,
 952                                                &edp->link_train.link_rate);
 953         retval = rk32_edp_get_max_rx_lane_count(edp,
 954                                                 &edp->link_train.lane_count);
 955         dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
 956                  edp->link_train.link_rate * 27/100,
 957                  edp->link_train.link_rate*27%100,
 958                  edp->link_train.lane_count);
 959
 960         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 961             (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 962                 dev_warn
 963                 (edp->dev,
 964                  "Rx Mx Link Rate is abnormal:%x!default link rate:%d.%dGps\n",
 965                  edp->link_train.link_rate,
 966                  edp->video_info.link_rate*27/100,
 967                  edp->video_info.link_rate*27%100);
 968                 edp->link_train.link_rate = edp->video_info.link_rate;
 969         }
 970
 971         if (edp->link_train.lane_count == 0) {
 972                 dev_err
 973                 (edp->dev,
 974                  "Rx Max Lane count is abnormal :%x !use default lanes:%d\n",
 975                  edp->link_train.lane_count,
 976                  edp->video_info.lane_count);
 977                 edp->link_train.lane_count = edp->video_info.lane_count;
 978         }
 979
 980         rk32_edp_analog_power_ctr(edp, 1);
 981
 982
 983         return 0;
 984 }
 985
 986 #if defined(SW_LT)
 987 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
 988 {
 989         int retval = 0;
 990         int training_finished = 0;
 991
 992         edp->link_train.lt_state = LT_START;
 993
 994         /* Process here */
 995         while (!training_finished) {
 996                 switch (edp->link_train.lt_state) {
 997                 case LT_START:
 998                         retval = rk32_edp_link_start(edp);
 999                         if (retval)
1000                                 dev_err(edp->dev, "LT Start failed\n");
1001                         break;
1002                 case LT_CLK_RECOVERY:
1003                         retval = rk32_edp_process_clock_recovery(edp);
1004                         if (retval)
1005                                 dev_err(edp->dev, "LT CR failed\n");
1006                         break;
1007                 case LT_EQ_TRAINING:
1008                         retval = rk32_edp_process_equalizer_training(edp);
1009                         if (retval)
1010                                 dev_err(edp->dev, "LT EQ failed\n");
1011                         break;
1012                 case FINISHED:
1013                         training_finished = 1;
1014                         break;
1015                 case FAILED:
1016                         return -EREMOTEIO;
1017                 }
1018         }
1019
1020         return retval;
1021 }
1022
1023 #else
1024 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
1025 {
1026         u32 cnt = 50;
1027         u32 val;
1028         /* Set link rate and count as you want to establish*/
1029         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1030         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1031         rk32_edp_hw_link_training_en(edp);
1032         val = rk32_edp_wait_hw_lt_done(edp);
1033         while (val) {
1034                 if (cnt-- <= 0) {
1035                         dev_err(edp->dev, "hw lt timeout");
1036                         return -ETIMEDOUT;
1037                 }
1038                 mdelay(1);
1039                 val = rk32_edp_wait_hw_lt_done(edp);
1040         }
1041
1042         val = rk32_edp_get_hw_lt_status(edp);
1043         if (val)
1044                 dev_err(edp->dev, "hw lt err:%d\n", val);
1045         return val;
1046 }
1047 #endif
1048
1049 static int rk32_edp_set_link_train(struct rk32_edp *edp)
1050 {
1051         int retval;
1052
1053         retval = rk32_edp_init_training(edp);
1054         if (retval < 0)
1055                 dev_err(edp->dev, "DP LT init failed!\n");
1056 #if defined(SW_LT)
1057         retval = rk32_edp_sw_link_training(edp);
1058 #else
1059         retval = rk32_edp_hw_link_training(edp);
1060 #endif
1061
1062         return retval;
1063 }
1064
1065 static int rk32_edp_config_video(struct rk32_edp *edp,
1066                                  struct video_info *video_info)
1067 {
1068         int retval = 0;
1069         int timeout_loop = 0;
1070         int done_count = 0;
1071
1072         rk32_edp_config_video_slave_mode(edp, video_info);
1073
1074         rk32_edp_set_video_color_format(edp, video_info->color_depth,
1075                                         video_info->color_space,
1076                                         video_info->dynamic_range,
1077                                         video_info->ycbcr_coeff);
1078
1079         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
1080                 dev_err(edp->dev, "PLL is not locked yet.\n");
1081                 return -EINVAL;
1082         }
1083
1084         for (;;) {
1085                 timeout_loop++;
1086                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
1087                         break;
1088                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1089                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1090                         return -ETIMEDOUT;
1091                 }
1092
1093                 udelay(1);
1094         }
1095
1096         /* Set to use the register calculated M/N video */
1097         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1098
1099         /* For video bist, Video timing must be generated by register */
1100 #ifndef EDP_BIST_MODE
1101         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
1102 #endif
1103         /* Disable video mute */
1104         rk32_edp_enable_video_mute(edp, 0);
1105
1106         /* Configure video slave mode */
1107         rk32_edp_enable_video_master(edp, 0);
1108
1109         /* Enable video */
1110         rk32_edp_start_video(edp);
1111
1112         timeout_loop = 0;
1113
1114         for (;;) {
1115                 timeout_loop++;
1116                 if (rk32_edp_is_video_stream_on(edp) == 0) {
1117                         done_count++;
1118                         if (done_count > 10)
1119                                 break;
1120                 } else if (done_count) {
1121                         done_count = 0;
1122                 }
1123                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1124                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1125                         return -ETIMEDOUT;
1126                 }
1127
1128                 mdelay(1);
1129         }
1130
1131         if (retval != 0)
1132                 dev_err(edp->dev, "Video stream is not detected!\n");
1133
1134         return retval;
1135 }
1136
1137 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1138 {
1139         struct rk32_edp *edp = arg;
1140         enum dp_irq_type irq_type;
1141
1142         irq_type = rk32_edp_get_irq_type(edp);
1143         switch (irq_type) {
1144         case DP_IRQ_TYPE_HP_CABLE_IN:
1145                 dev_info(edp->dev, "Received irq - cable in\n");
1146                 rk32_edp_clear_hotplug_interrupts(edp);
1147                 break;
1148         case DP_IRQ_TYPE_HP_CABLE_OUT:
1149                 dev_info(edp->dev, "Received irq - cable out\n");
1150                 rk32_edp_clear_hotplug_interrupts(edp);
1151                 break;
1152         case DP_IRQ_TYPE_HP_CHANGE:
1153                 /*
1154                  * We get these change notifications once in a while, but there
1155                  * is nothing we can do with them. Just ignore it for now and
1156                  * only handle cable changes.
1157                  */
1158                 dev_info(edp->dev, "Received irq - hotplug change; ignoring.\n");
1159                 rk32_edp_clear_hotplug_interrupts(edp);
1160                 break;
1161         default:
1162                 dev_err(edp->dev, "Received irq - unknown type!\n");
1163                 break;
1164         }
1165         return IRQ_HANDLED;
1166 }
1167
1168 static int rk32_edp_enable(void)
1169 {
1170         int ret = 0;
1171         struct rk32_edp *edp = rk32_edp;
1172
1173         if (!edp->edp_en) {
1174                 rk32_edp_clk_enable(edp);
1175                 rk32_edp_pre_init(edp);
1176                 rk32_edp_init_edp(edp);
1177                 enable_irq(edp->irq);
1178                 /*ret = rk32_edp_handle_edid(edp);
1179                 if (ret) {
1180                         dev_err(edp->dev, "unable to handle edid\n");
1181                         //goto out;
1182                 }
1183
1184                 ret = rk32_edp_enable_scramble(edp, 0);
1185                 if (ret) {
1186                         dev_err(edp->dev, "unable to set scramble\n");
1187                         //goto out;
1188                 }
1189
1190                 ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1191                 if (ret) {
1192                         dev_err(edp->dev, "unable to set enhanced mode\n");
1193                         //goto out;
1194                 }
1195                 rk32_edp_enable_enhanced_mode(edp, 1);*/
1196
1197                 ret = rk32_edp_set_link_train(edp);
1198                 if (ret)
1199                         dev_err(edp->dev, "link train failed!\n");
1200                 else
1201                         dev_info(edp->dev, "link training success.\n");
1202
1203                 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1204                 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1205                 rk32_edp_init_video(edp);
1206
1207 #ifdef EDP_BIST_MODE
1208                 rk32_edp_bist_cfg(edp);
1209 #endif
1210                 ret = rk32_edp_config_video(edp, &edp->video_info);
1211                 if (ret)
1212                         dev_err(edp->dev, "unable to config video\n");
1213
1214                 edp->edp_en = true;
1215         }
1216         return ret;
1217 }
1218
1219 static int  rk32_edp_disable(void)
1220 {
1221         struct rk32_edp *edp = rk32_edp;
1222
1223         if (edp->edp_en) {
1224                 disable_irq(edp->irq);
1225                 rk32_edp_reset(edp);
1226                 rk32_edp_analog_power_ctr(edp, 0);
1227                 rk32_edp_clk_disable(edp);
1228                 edp->edp_en = false;
1229         }
1230
1231         return 0;
1232 }
1233
1234
1235 static struct rk_fb_trsm_ops trsm_edp_ops = {
1236         .enable = rk32_edp_enable,
1237         .disable = rk32_edp_disable,
1238 };
1239
1240 /*#if 0
1241 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1242 {
1243         u8 data;
1244         int retval;
1245
1246         if (enable) {
1247                 rk32_edp_enable_scrambling(edp);
1248
1249                 retval = rk32_edp_read_byte_from_dpcd
1250                                 (edp,
1251                                  DPCD_TRAINING_PATTERN_SET,
1252                                  &data);
1253                 if (retval < 0)
1254                         return retval;
1255
1256                 retval = rk32_edp_write_byte_to_dpcd
1257                                 (edp,
1258                                  DPCD_TRAINING_PATTERN_SET,
1259                                  (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1260                 if (retval < 0)
1261                         return retval;
1262         } else {
1263                 rk32_edp_disable_scrambling(edp);
1264
1265                 retval = rk32_edp_read_byte_from_dpcd
1266                                 (edp,
1267                                  DPCD_TRAINING_PATTERN_SET,
1268                                  &data);
1269                 if (retval < 0)
1270                         return retval;
1271
1272                 retval = rk32_edp_write_byte_to_dpcd
1273                                 (edp,
1274                                  DPCD_TRAINING_PATTERN_SET,
1275                                  (u8)(data | DPCD_SCRAMBLING_DISABLED));
1276                 if (retval < 0)
1277                         return retval;
1278         }
1279
1280         return 0;
1281 }
1282 #endif*/
1283 static int rk32_edp_psr_enable(struct rk32_edp *edp)
1284 {
1285         u8 buf;
1286         int retval;
1287         char date, psr_version;
1288
1289         /*if support PSR*/
1290         retval = rk32_edp_read_byte_from_dpcd
1291                         (edp,
1292                          PANEL_SELF_REFRESH_CAPABILITY_SUPPORTED_AND_VERSION,
1293                          &psr_version);
1294         if (retval < 0) {
1295                 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1296                 return retval;
1297         } else {
1298                 pr_info("PSR supporter and version:%x\n", psr_version);
1299         }
1300
1301          /*PSR capabilities*/
1302         retval = rk32_edp_read_byte_from_dpcd
1303                         (edp,
1304                          PANEL_SELF_REFRESH_CAPABILITIES, &date);
1305         if (retval < 0) {
1306                 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1307                 return retval;
1308         } else {
1309                 pr_info("PSR capabilities:%x\n", date);
1310         }
1311
1312         if (psr_version & PSR_SUPPORT) {
1313                 pr_info("PSR config psr\n");
1314
1315                 /*config sink PSR*/
1316                 buf = 0x02;
1317                 retval = rk32_edp_write_bytes_to_dpcd(edp, PSR_ENABLE,
1318                                                       1, &buf);
1319                 if (retval < 0) {
1320                         dev_err(edp->dev, "PSR failed to config sink PSR!\n");
1321                         return retval;
1322                 } else {
1323                         /*enable the PSR*/
1324                         buf = 0x03;
1325                         retval = rk32_edp_write_bytes_to_dpcd(edp,
1326                                                               PSR_ENABLE,
1327                                                               1, &buf);
1328                         if (retval < 0) {
1329                                 dev_err(edp->dev, "PSR failed to enable the PSR!\n");
1330                                 return retval;
1331                         }
1332                         /*read sink config state*/
1333                         retval = rk32_edp_read_byte_from_dpcd
1334                                                 (edp,
1335                                                  PSR_ENABLE, &date);
1336                         if (retval < 0) {
1337                                 dev_err(edp->dev, "PSR DPCD Read failed!\n");
1338                                 return retval;
1339                         } else {
1340                                 pr_info("PSR sink config state:%x\n", date);
1341                         }
1342                 }
1343
1344                 /*enable sink crc*/
1345                 retval = rk32_edp_read_byte_from_dpcd(edp, 0x270, &buf);
1346                 buf |= 0x01;
1347                 retval = rk32_edp_write_bytes_to_dpcd(edp, 0x270, 1, &buf);
1348         }
1349
1350                 return 0;
1351 }
1352 static int psr_header_HB_PB(struct rk32_edp *edp)
1353 {
1354         u32 val;
1355
1356         val = 0x0;
1357         writel(val, edp->regs + HB0);/*HB0*/
1358         val = 0x07;
1359         writel(val, edp->regs + HB1);/*HB1*/
1360         val = 0x02;
1361         writel(val, edp->regs + HB2);/*HB2*/
1362         val = 0x08;
1363         writel(val, edp->regs + HB3);/*HB3*/
1364         val = 0x00;
1365         writel(val, edp->regs + PB0);/*PB0*/
1366         val = 0x16;
1367         writel(val, edp->regs + PB1);/*PB1*/
1368         val = 0xce;
1369         writel(val, edp->regs + PB2);/*PB2*/
1370         val = 0x5d;
1371         writel(val, edp->regs + PB3);/*PB3*/
1372
1373         return 0;
1374 }
1375
1376 static int psr_enable_sdp(struct rk32_edp *edp)
1377 {
1378         u32 val;
1379
1380         val = readl(edp->regs + SPDIF_AUDIO_CTL_0);
1381         val |= 0x08;
1382         writel(val, edp->regs + SPDIF_AUDIO_CTL_0);/*enable SDP*/
1383         val = readl(edp->regs + SPDIF_AUDIO_CTL_0);
1384         pr_info("PSR reuse_spd_en:%x\n", val);
1385
1386         val = 0x83;
1387         writel(val, edp->regs + IF_TYPE);/*enable IF_TYPE*/
1388         val = readl(edp->regs + IF_TYPE);
1389         pr_info("PSR IF_TYPE :%x\n", val);
1390
1391         val = readl(edp->regs + PKT_SEND_CTL);
1392         val |= 0x10;
1393         writel(val, edp->regs + PKT_SEND_CTL);/*enable IF_UP*/
1394         val = readl(edp->regs + PKT_SEND_CTL);
1395         pr_info("PSR if_up :%x\n", val);
1396
1397         val = readl(edp->regs + PKT_SEND_CTL);
1398         val |= 0x01;
1399         writel(val, edp->regs + PKT_SEND_CTL);/*enable IF_EN*/
1400         val = readl(edp->regs + PKT_SEND_CTL);
1401         pr_info("PSR if_en:%x\n", val);
1402         return 0;
1403 }
1404 static int edp_disable_psr(struct rk32_edp *edp)
1405 {
1406         u8 buf;
1407         int retval;
1408         char date;
1409
1410         /*disable sink PSR*/
1411         retval = rk32_edp_read_byte_from_dpcd(edp,
1412                                               PSR_ENABLE, &date);
1413         if (retval < 0) {
1414                 dev_err(edp->dev, "PSR sink original config Read failed!\n");
1415                 return retval;
1416         }
1417         buf = date&0xfe;
1418         retval = rk32_edp_write_bytes_to_dpcd
1419                                         (edp,
1420                                          PSR_ENABLE,
1421                                          1, &buf);
1422         if (retval < 0) {
1423                 dev_err(edp->dev, "PSR failed to disable sink PSR!\n");
1424                 return retval;
1425         }
1426
1427         pr_info("PSR disable success!!\n");
1428         return 0;
1429 }
1430
1431 static int edp_psr_state(struct rk32_edp *edp, int state)
1432 {
1433                 u32 val;
1434                 /*wait for VD blank*/
1435                 if  (rk_fb_poll_wait_frame_complete()) {
1436                         psr_header_HB_PB(edp);
1437
1438                         val = state;
1439                         writel(val, edp->regs + DB1);
1440                         /*val = readl(edp->regs + DB1);
1441                         pr_info("PSR set DB1 state 0x0:%x\n", val);
1442
1443                         for (i = 0; i < 22; i++)
1444                                  writel(0, edp->regs + DB2 + 4 * i);*/
1445
1446                         psr_enable_sdp(edp);
1447                 }
1448         return 0;
1449 }
1450
1451
1452 static int phy_power_channel(struct rk32_edp *edp, int state)
1453 {
1454         u32 val;
1455
1456         val = state;
1457         writel(val, edp->regs + DP_PD);
1458
1459         return 0;
1460 }
1461
1462 #if defined(CONFIG_DEBUG_FS)
1463
1464 static int edp_dpcd_debugfs_show(struct seq_file *s, void *v)
1465 {
1466         int retval;
1467         unsigned char buf[12];
1468         struct rk32_edp *edp = s->private;
1469
1470         if (!edp) {
1471                 dev_err(edp->dev, "no edp device!\n");
1472                 return -ENODEV;
1473         }
1474
1475         retval = rk32_edp_read_byte_from_dpcd
1476                         (edp,
1477                          PANEL_SELF_REFRESH_CAPABILITY_SUPPORTED_AND_VERSION,
1478                          &buf[0]);
1479         seq_printf(s, "0x70 %x\n", buf[0]);
1480
1481         /*PSR capabilities*/
1482         retval = rk32_edp_read_byte_from_dpcd
1483                         (edp,
1484                          PANEL_SELF_REFRESH_CAPABILITIES, &buf[0]);
1485         seq_printf(s, "0x71 %x\n", buf[0]);
1486
1487         retval = rk32_edp_read_byte_from_dpcd
1488                         (edp,
1489                          PSR_ENABLE, &buf[0]);
1490         seq_printf(s, "0x170 %x\n", buf[0]);
1491
1492         retval = rk32_edp_read_byte_from_dpcd(edp, 0x2006, &buf[0]);
1493         seq_printf(s, "0x2006 %x\n", buf[0]);
1494
1495         retval = rk32_edp_read_byte_from_dpcd(edp, 0x2007, &buf[0]);
1496         seq_printf(s, "0x2007 %x\n", buf[0]);
1497
1498         retval = rk32_edp_read_byte_from_dpcd(edp, 0x2008, &buf[0]);
1499         seq_printf(s, "0x2008 %x\n", buf[0]);
1500         retval = rk32_edp_read_byte_from_dpcd(edp, 0x2009, &buf[0]);
1501         seq_printf(s, "0x2009 %x\n", buf[0]);
1502
1503         retval = rk32_edp_read_byte_from_dpcd(edp, 0x200a, &buf[0]);
1504         seq_printf(s, "0x200a %x\n", buf[0]);
1505
1506         retval = rk32_edp_read_byte_from_dpcd(edp, 0x240, &buf[0]);
1507         seq_printf(s, "0x240 %x\n", buf[0]);
1508         retval = rk32_edp_read_byte_from_dpcd(edp, 0x241, &buf[0]);
1509         seq_printf(s, "0x241 %x\n", buf[0]);
1510         retval = rk32_edp_read_byte_from_dpcd(edp, 0x242, &buf[0]);
1511         seq_printf(s, "0x242 %x\n", buf[0]);
1512         retval = rk32_edp_read_byte_from_dpcd(edp, 0x243, &buf[0]);
1513         seq_printf(s, "0x243 %x\n", buf[0]);
1514         retval = rk32_edp_read_byte_from_dpcd(edp, 0x244, &buf[0]);
1515         seq_printf(s, "0x244 %x\n", buf[0]);
1516         retval = rk32_edp_read_byte_from_dpcd(edp, 0x245, &buf[0]);
1517         seq_printf(s, "0x245 %x\n", buf[0]);
1518         retval = rk32_edp_read_byte_from_dpcd(edp, 0x270, &buf[0]);
1519         seq_printf(s, "0x270 %x\n", buf[0]);
1520         retval = rk32_edp_read_byte_from_dpcd(edp, 0x246, &buf[0]);
1521         seq_printf(s, "0x246 %x\n", buf[0]);
1522
1523         /*retval = rk32_edp_read_byte_from_dpcd(edp, 0x222, &buf[0]);
1524         seq_printf(s, "0x222 %x\n", buf[0]);
1525         retval = rk32_edp_read_byte_from_dpcd(edp, 0x223, &buf[0]);
1526         seq_printf(s, "0x223 %x\n", buf[0]);
1527         retval = rk32_edp_read_byte_from_dpcd(edp, 0x224, &buf[0]);
1528         seq_printf(s, "0x224 %x\n", buf[0]);
1529         retval = rk32_edp_read_byte_from_dpcd(edp, 0x225, &buf[0]);
1530         seq_printf(s, "0x225 %x\n", buf[0]);
1531         retval = rk32_edp_read_byte_from_dpcd(edp, 0x226, &buf[0]);
1532         seq_printf(s, "0x226 %x\n", buf[0]);
1533         retval = rk32_edp_read_byte_from_dpcd(edp, 0x227, &buf[0]);
1534         seq_printf(s, "0x227 %x\n", buf[0]);
1535         retval = rk32_edp_read_byte_from_dpcd(edp, 0x228, &buf[0]);
1536         seq_printf(s, "0x228 %x\n", buf[0]);
1537         retval = rk32_edp_read_byte_from_dpcd(edp, 0x229, &buf[0]);
1538         seq_printf(s, "0x229 %x\n", buf[0]);
1539         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22a, &buf[0]);
1540         seq_printf(s, "0x22a %x\n", buf[0]);
1541         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22b, &buf[0]);
1542         seq_printf(s, "0x22b %x\n", buf[0]);
1543         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22c, &buf[0]);
1544         seq_printf(s, "0x22c %x\n", buf[0]);
1545         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22d, &buf[0]);
1546         seq_printf(s, "0x22d %x\n", buf[0]);
1547         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22e, &buf[0]);
1548         seq_printf(s, "0x22e %x\n", buf[0]);
1549         retval = rk32_edp_read_byte_from_dpcd(edp, 0x22f, &buf[0]);
1550         seq_printf(s, "0x22f %x\n", buf[0]);
1551         retval = rk32_edp_read_byte_from_dpcd(edp, 0x230, &buf[0]);
1552         seq_printf(s, "0x230 %x\n", buf[0]);
1553         retval = rk32_edp_read_byte_from_dpcd(edp, 0x231, &buf[0]);
1554         seq_printf(s, "0x231 %x\n", buf[0]);*/
1555
1556         /*rk32_edp_read_bytes_from_dpcd(edp,
1557                         DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
1558         for (i = 0; i < 12; i++)
1559                 seq_printf(s, "0x%02x>>0x%02x\n", 0x210 + i, buf[i]);*/
1560         return 0;
1561 }
1562
1563 static ssize_t edp_dpcd_write(struct file *file,
1564                               const char __user *buf,
1565                               size_t count,
1566                               loff_t *ppos)
1567 {
1568         return count;
1569 }
1570
1571 static int edp_edid_debugfs_show(struct seq_file *s, void *v)
1572 {
1573         struct rk32_edp *edp = s->private;
1574
1575         if (!edp) {
1576                 dev_err(edp->dev, "no edp device!\n");
1577                 return -ENODEV;
1578         }
1579         rk32_edp_read_edid(edp);
1580         seq_puts(s, "edid");
1581         return 0;
1582 }
1583
1584 static ssize_t edp_edid_write(struct file *file,
1585                               const char __user *buf,
1586                               size_t count,
1587                               loff_t *ppos)
1588 {
1589         struct rk32_edp *edp =
1590                 ((struct seq_file *)file->private_data)->private;
1591
1592         if (!edp) {
1593                 dev_err(edp->dev, "no edp device!\n");
1594                 return -ENODEV;
1595         }
1596         rk32_edp_disable();
1597         rk32_edp_enable();
1598         return count;
1599 }
1600
1601 static int edp_reg_debugfs_show(struct seq_file *s, void *v)
1602 {
1603         int i = 0;
1604         struct rk32_edp *edp = s->private;
1605
1606         if (!edp) {
1607                 dev_err(edp->dev, "no edp device!\n");
1608                 return -ENODEV;
1609         }
1610
1611         for (i = 0; i < 0x284; i++) {
1612                 if (!(i%4))
1613                         seq_printf(s, "\n%08x:  ", i*4);
1614                 seq_printf(s, "%08x ", readl(edp->regs + i*4));
1615         }
1616         return 0;
1617 }
1618
1619 static ssize_t edp_reg_write(struct file *file,
1620                              const char __user *buf, size_t count,
1621                              loff_t *ppos)
1622 {
1623         return count;
1624 }
1625
1626 static int edp_psr_debugfs_show(struct seq_file *s, void *v)
1627 {
1628         return 0;
1629 }
1630 static ssize_t edp_psr_write(struct file *file,
1631                              const char __user *buf,
1632                              size_t count, loff_t *ppos)
1633 {
1634         int a;
1635         char kbuf[25];
1636         int retval;
1637         struct rk32_edp *edp =
1638                 ((struct seq_file *)file->private_data)->private;
1639
1640         if (!edp) {
1641                 dev_err(edp->dev, "no edp device!\n");
1642                 return -ENODEV;
1643         }
1644         memset(kbuf, 0, 25);
1645         if (copy_from_user(kbuf, buf, count))
1646                 return -EFAULT;
1647         retval = kstrtoint(kbuf, 0, &a);
1648         if (retval)
1649                 return retval;
1650         /*retval = sscanf(kbuf, "%d", &a);
1651         if (retval < 0) {
1652                 dev_err(edp->dev, "PSR failed sscanf!\n");
1653                 return retval;
1654         }*/
1655         /*disable psr*/
1656         if (0 == a)
1657                 edp_disable_psr(edp);
1658         /*enable psr*/
1659         if (1 == a)
1660                 rk32_edp_psr_enable(edp);
1661         /*inactive psr*/
1662         if (2 == a)
1663                 edp_psr_state(edp, 0x0);
1664         /*sink state 2*/
1665         if  (3 == a)
1666                 edp_psr_state(edp, 0x01);
1667         /*sink state 3*/
1668         if  (4 == a)
1669                 edp_psr_state(edp, 0x03);
1670         /*open 4 lanes*/
1671         if  (5 == a) {
1672                 phy_power_channel(edp, 0xff);
1673                 usleep_range(9, 10);
1674                 phy_power_channel(edp, 0x7f);
1675                 usleep_range(9, 10);
1676                 phy_power_channel(edp, 0x0);
1677         }
1678         /*close 4 lanes*/
1679         if (6 == a) {
1680                 phy_power_channel(edp, 0x7f);
1681                 usleep_range(9, 10);
1682                 phy_power_channel(edp, 0x0f);
1683         }
1684
1685         return count;
1686 }
1687
1688 #define EDP_DEBUG_ENTRY(name) \
1689 static int edp_##name##_debugfs_open(struct inode *inode, struct file *file) \
1690 { \
1691         return single_open(file, edp_##name##_debugfs_show, inode->i_private); \
1692 } \
1693 \
1694 static const struct file_operations edp_##name##_debugfs_fops = { \
1695         .owner = THIS_MODULE, \
1696         .open = edp_##name##_debugfs_open, \
1697         .read = seq_read, \
1698         .write = edp_##name##_write,    \
1699         .llseek = seq_lseek, \
1700         .release = single_release, \
1701 }
1702
1703 EDP_DEBUG_ENTRY(psr);
1704 EDP_DEBUG_ENTRY(dpcd);
1705 EDP_DEBUG_ENTRY(edid);
1706 EDP_DEBUG_ENTRY(reg);
1707 #endif
1708
1709 static int rk32_edp_probe(struct platform_device *pdev)
1710 {
1711         struct rk32_edp *edp;
1712         struct resource *res;
1713         struct device_node *np = pdev->dev.of_node;
1714         int ret;
1715
1716         if (!np) {
1717                 dev_err(&pdev->dev, "Missing device tree node.\n");
1718                 return -EINVAL;
1719         }
1720
1721         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1722         if (!edp) {
1723                 dev_err(&pdev->dev, "no memory for state\n");
1724                 return -ENOMEM;
1725         }
1726         edp->dev = &pdev->dev;
1727         edp->video_info.h_sync_polarity = 0;
1728         edp->video_info.v_sync_polarity = 0;
1729         edp->video_info.interlaced      = 0;
1730         edp->video_info.color_space     = CS_RGB;
1731         edp->video_info.dynamic_range   = VESA;
1732         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1733         edp->video_info.color_depth     = COLOR_8;
1734
1735         edp->video_info.link_rate       = LINK_RATE_1_62GBPS;
1736         edp->video_info.lane_count      = LANE_CNT4;
1737         rk_fb_get_prmry_screen(&edp->screen);
1738         if (edp->screen.type != SCREEN_EDP) {
1739                 dev_err(&pdev->dev, "screen is not edp!\n");
1740                 return -EINVAL;
1741         }
1742         platform_set_drvdata(pdev, edp);
1743         dev_set_name(edp->dev, "rk32-edp");
1744
1745         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1746         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1747         if (IS_ERR(edp->regs)) {
1748                 dev_err(&pdev->dev, "ioremap reg failed\n");
1749                 return PTR_ERR(edp->regs);
1750         }
1751
1752         edp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1753         if (IS_ERR(edp->grf) && !cpu_is_rk3288()) {
1754                 dev_err(&pdev->dev, "can't find rockchip,grf property\n");
1755                 return PTR_ERR(edp->grf);
1756         }
1757
1758         edp->pd = devm_clk_get(&pdev->dev, "pd_edp");
1759         if (IS_ERR(edp->pd)) {
1760                 dev_err(&pdev->dev, "cannot get pd\n");
1761                 edp->pd = NULL;
1762         }
1763
1764         edp->clk_edp = devm_clk_get(&pdev->dev, "clk_edp");
1765         if (IS_ERR(edp->clk_edp)) {
1766                 dev_err(&pdev->dev, "cannot get clk_edp\n");
1767                 return PTR_ERR(edp->clk_edp);
1768         }
1769
1770         edp->clk_24m = devm_clk_get(&pdev->dev, "clk_edp_24m");
1771         if (IS_ERR(edp->clk_24m)) {
1772                 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1773                 return PTR_ERR(edp->clk_24m);
1774         }
1775
1776         edp->pclk = devm_clk_get(&pdev->dev, "pclk_edp");
1777         if (IS_ERR(edp->pclk)) {
1778                 dev_err(&pdev->dev, "cannot get pclk\n");
1779                 return PTR_ERR(edp->pclk);
1780         }
1781
1782         /* We use the reset API to control the software reset at this version
1783          * and later, and we reserve the code that setting the cru regs directly
1784          * in the rk3288.
1785          */
1786         /*edp 24m need sorft reset*/
1787         edp->rst_24m = devm_reset_control_get(&pdev->dev, "edp_24m");
1788         if (IS_ERR(edp->rst_24m))
1789                 dev_err(&pdev->dev, "failed to get reset\n");
1790         /* edp ctrl apb bus need sorft reset */
1791         edp->rst_apb = devm_reset_control_get(&pdev->dev, "edp_apb");
1792         if (IS_ERR(edp->rst_apb))
1793                 dev_err(&pdev->dev, "failed to get reset\n");
1794         rk32_edp_clk_enable(edp);
1795         if (!support_uboot_display())
1796                 rk32_edp_pre_init(edp);
1797         edp->irq = platform_get_irq(pdev, 0);
1798         if (edp->irq < 0) {
1799                 dev_err(&pdev->dev, "cannot find IRQ\n");
1800                 return edp->irq;
1801         }
1802         ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1803                                dev_name(&pdev->dev), edp);
1804         if (ret) {
1805                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1806                 return ret;
1807         }
1808         disable_irq_nosync(edp->irq);
1809         if (!support_uboot_display())
1810                 rk32_edp_clk_disable(edp);
1811         rk32_edp = edp;
1812         rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1813 #if defined(CONFIG_DEBUG_FS)
1814         edp->debugfs_dir = debugfs_create_dir("edp", NULL);
1815         if (IS_ERR(edp->debugfs_dir)) {
1816                 dev_err(edp->dev, "failed to create debugfs dir for edp!\n");
1817         } else {
1818                 debugfs_create_file("dpcd", S_IRUSR, edp->debugfs_dir,
1819                                     edp, &edp_dpcd_debugfs_fops);
1820                 debugfs_create_file("edid", S_IRUSR, edp->debugfs_dir,
1821                                     edp, &edp_edid_debugfs_fops);
1822                 debugfs_create_file("reg", S_IRUSR, edp->debugfs_dir,
1823                                     edp, &edp_reg_debugfs_fops);
1824                 debugfs_create_file("psr", S_IRUSR, edp->debugfs_dir,
1825                                     edp, &edp_psr_debugfs_fops);
1826         }
1827
1828 #endif
1829         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1830
1831         return 0;
1832 }
1833
1834 static void rk32_edp_shutdown(struct platform_device *pdev)
1835 {
1836 }
1837
1838 #if defined(CONFIG_OF)
1839 static const struct of_device_id rk32_edp_dt_ids[] = {
1840         {.compatible = "rockchip,rk32-edp",},
1841         {}
1842 };
1843
1844 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1845 #endif
1846
1847 static struct platform_driver rk32_edp_driver = {
1848         .probe = rk32_edp_probe,
1849         .driver = {
1850                    .name = "rk32-edp",
1851                    .owner = THIS_MODULE,
1852 #if defined(CONFIG_OF)
1853                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1854 #endif
1855         },
1856         .shutdown = rk32_edp_shutdown,
1857 };
1858
1859 static int __init rk32_edp_module_init(void)
1860 {
1861         return platform_driver_register(&rk32_edp_driver);
1862 }
1863
1864 static void __exit rk32_edp_module_exit(void)
1865 {
1866 }
1867
1868 fs_initcall(rk32_edp_module_init);
1869 module_exit(rk32_edp_module_exit);