1 #ifndef __REG2_INFO_H__
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2 #define __REG2_INFO_H__
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5 //#include "chip_register.h"
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7 //#include "rga_struct.h"
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11 #define MIN(X, Y) ((X)<(Y)?(X):(Y))
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15 #define MAX(X, Y) ((X)>(Y)?(X):(Y))
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19 #define ABS(X) (((X) < 0) ? (-(X)) : (X))
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23 #define CLIP(x, a, b) ((x) < (a)) ? (a) : (((x) > (b)) ? (b) : (x))
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26 #define rRGA_SYS_CTRL (*(volatile u32 *)(RGA2_BASE + RGA2_SYS_CTRL_OFFSET ))
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27 #define rRGA_CMD_CTRL (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_CTRL_OFFSET ))
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28 #define rRGA_CMD_BASE (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_BASE_OFFSET ))
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29 #define rRGA_STATUS (*(volatile u32 *)(RGA2_BASE + RGA2_STATUS_OFFSET ))
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30 #define rRGA_INT (*(volatile u32 *)(RGA2_BASE + RGA2_INT_OFFSET ))
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31 #define rRGA_MMU_CTRL0 (*(volatile u32 *)(RGA2_BASE + RGA2_MMU_CTRL0_OFFSET ))
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32 #define rRGA_MMU_CMD_BASE (*(volatile u32 *)(RGA2_BASE + RGA2_MMU_CMD_BASE_OFFSET))
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33 #define rRGA_CMD_ADDR (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_ADDR))
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36 #define m_RGA2_INT_ALL_CMD_DONE_INT_EN ( 1<<10 )
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37 #define m_RGA2_INT_MMU_INT_EN ( 1<<9 )
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38 #define m_RGA2_INT_ERROR_INT_EN ( 1<<8 )
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39 #define m_RGA2_INT_NOW_CMD_DONE_INT_CLEAR ( 1<<7 )
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40 #define m_RGA2_INT_ALL_CMD_DONE_INT_CLEAR ( 1<<6 )
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41 #define m_RGA2_INT_MMU_INT_CLEAR ( 1<<5 )
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42 #define m_RGA2_INT_ERROR_INT_CLEAR ( 1<<4 )
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43 #define m_RGA2_INT_CUR_CMD_DONE_INT_FLAG ( 1<<3 )
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44 #define m_RGA2_INT_ALL_CMD_DONE_INT_FLAG ( 1<<2 )
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45 #define m_RGA2_INT_MMU_INT_FLAG ( 1<<1 )
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46 #define m_RGA2_INT_ERROR_INT_FLAG ( 1<<0 )
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48 #define s_RGA2_INT_ALL_CMD_DONE_INT_EN(x) ( (x&0x1)<<10 )
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49 #define s_RGA2_INT_MMU_INT_EN(x) ( (x&0x1)<<9 )
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50 #define s_RGA2_INT_ERROR_INT_EN(x) ( (x&0x1)<<8 )
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51 #define s_RGA2_INT_NOW_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<7 )
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52 #define s_RGA2_INT_ALL_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<6 )
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53 #define s_RGA2_INT_MMU_INT_CLEAR(x) ( (x&0x1)<<5 )
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54 #define s_RGA2_INT_ERROR_INT_CLEAR(x) ( (x&0x1)<<4 )
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59 #define m_RGA2_MODE_CTRL_SW_RENDER_MODE ( 0x7<<0 )
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60 #define m_RGA2_MODE_CTRL_SW_BITBLT_MODE ( 0x1<<3 )
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61 #define m_RGA2_MODE_CTRL_SW_CF_ROP4_PAT ( 0x1<<4 )
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62 #define m_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET ( 0x1<<5 )
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63 #define m_RGA2_MODE_CTRL_SW_GRADIENT_SAT ( 0x1<<6 )
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64 #define m_RGA2_MODE_CTRL_SW_INTR_CF_E ( 0x1<<7 )
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66 #define s_RGA2_MODE_CTRL_SW_RENDER_MODE(x) ( (x&0x7)<<0 )
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67 #define s_RGA2_MODE_CTRL_SW_BITBLT_MODE(x) ( (x&0x1)<<3 )
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68 #define s_RGA2_MODE_CTRL_SW_CF_ROP4_PAT(x) ( (x&0x1)<<4 )
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69 #define s_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET(x) ( (x&0x1)<<5 )
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70 #define s_RGA2_MODE_CTRL_SW_GRADIENT_SAT(x) ( (x&0x1)<<6 )
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71 #define s_RGA2_MODE_CTRL_SW_INTR_CF_E(x) ( (x&0x1)<<7 )
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74 #define m_RGA2_SRC_INFO_SW_SRC_FMT ( 0xf<<0 )
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75 #define m_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP ( 0x1<<4 )
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76 #define m_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP ( 0x1<<5 )
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77 #define m_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP ( 0x1<<6 )
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78 #define m_RGA2_SRC_INFO_SW_SW_CP_ENDAIN ( 0x1<<7 )
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79 #define m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE ( 0x3<<8 )
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80 #define m_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE ( 0x3<<10 )
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81 #define m_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE ( 0x3<<12 )
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82 #define m_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE ( 0x3<<14 )
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83 #define m_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE ( 0x3<<16 )
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84 #define m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE ( 0x1<<18 )
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85 #define m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E ( 0xf<<19 )
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86 #define m_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E ( 0x1<<23 )
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87 #define m_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER ( 0x3<<24 )
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88 #define m_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL ( 0x1<<26 )
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89 #define m_RGA2_SRC_INFO_SW_SW_YUV10_E ( 0x1<<27 )
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90 #define m_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E ( 0x1<<28 )
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96 #define s_RGA2_SRC_INFO_SW_SRC_FMT(x) ( (x&0xf)<<0 )
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97 #define s_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP(x) ( (x&0x1)<<4 )
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98 #define s_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP(x) ( (x&0x1)<<5 )
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99 #define s_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP(x) ( (x&0x1)<<6 )
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100 #define s_RGA2_SRC_INFO_SW_SW_CP_ENDAIN(x) ( (x&0x1)<<7 )
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101 #define s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(x) ( (x&0x3)<<8 )
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102 #define s_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE(x) ( (x&0x3)<<10 )
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103 #define s_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE(x) ( (x&0x3)<<12 )
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104 #define s_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE(x) ( (x&0x3)<<14 )
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105 #define s_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE(x) ( (x&0x3)<<16 )
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107 #define s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE(x) ( (x&0x1)<<18 )
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108 #define s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E(x) ( (x&0xf)<<19 )
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109 #define s_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E(x) ( (x&0x1)<<23 )
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110 #define s_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER(x) ( (x&0x3)<<24 )
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111 #define s_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL(x) ( (x&0x1)<<26 )
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112 #define s_RGA2_SRC_INFO_SW_SW_YUV10_E(x) ( (x&0x1)<<27 )
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113 #define s_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E(x) ( (x&0x1)<<28 )
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115 /* RGA_SRC_VIR_INFO */
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116 #define m_RGA2_SRC_VIR_INFO_SW_SRC_VIR_STRIDE ( 0x7fff<<0 ) //modify
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117 #define m_RGA2_SRC_VIR_INFO_SW_MASK_VIR_STRIDE ( 0x3ff<<16 ) //modify
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119 #define s_RGA2_SRC_VIR_INFO_SW_SRC_VIR_STRIDE(x) ( (x&0x7fff)<<0 ) //modify
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120 #define s_RGA2_SRC_VIR_INFO_SW_MASK_VIR_STRIDE(x) ( (x&0x3ff)<<16 ) //modify
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123 /* RGA_SRC_ACT_INFO */
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124 #define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH ( 0x1fff<<0 )
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125 #define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT ( 0x1fff<<16 )
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127 #define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH(x) ( (x&0x1fff)<<0 )
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128 #define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT(x) ( (x&0x1fff<)<16 )
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132 #define m_RGA2_DST_INFO_SW_DST_FMT ( 0xf<<0 )
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133 #define m_RGA2_DST_INFO_SW_DST_RB_SWAP ( 0x1<<4 )
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134 #define m_RGA2_DST_INFO_SW_ALPHA_SWAP ( 0x1<<5 )
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135 #define m_RGA2_DST_INFO_SW_DST_UV_SWAP ( 0x1<<6 )
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136 #define m_RGA2_DST_INFO_SW_SRC1_FMT ( 0x7<<7 )
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137 #define m_RGA2_DST_INFO_SW_SRC1_RB_SWP ( 0x1<<10)
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138 #define m_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP ( 0x1<<11)
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139 #define m_RGA2_DST_INFO_SW_DITHER_UP_E ( 0x1<<12)
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140 #define m_RGA2_DST_INFO_SW_DITHER_DOWN_E ( 0x1<<13)
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141 #define m_RGA2_DST_INFO_SW_DITHER_MODE ( 0x3<<14)
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142 #define m_RGA2_DST_INFO_SW_DST_CSC_MODE ( 0x3<<16) //add
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143 #define m_RGA2_DST_INFO_SW_CSC_CLIP_MODE ( 0x1<<18)
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145 #define s_RGA2_DST_INFO_SW_DST_FMT(x) ( (x&0xf)<<0 )
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146 #define s_RGA2_DST_INFO_SW_DST_RB_SWAP(x) ( (x&0x1)<<4 )
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147 #define s_RGA2_DST_INFO_SW_ALPHA_SWAP(x) ( (x&0x1)<<5 )
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148 #define s_RGA2_DST_INFO_SW_DST_UV_SWAP(x) ( (x&0x1)<<6 )
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149 #define s_RGA2_DST_INFO_SW_SRC1_FMT(x) ( (x&0x7)<<7 )
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150 #define s_RGA2_DST_INFO_SW_SRC1_RB_SWP(x) ( (x&0x1)<<10)
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151 #define s_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP(x) ( (x&0x1)<<11)
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152 #define s_RGA2_DST_INFO_SW_DITHER_UP_E(x) ( (x&0x1)<<12)
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153 #define s_RGA2_DST_INFO_SW_DITHER_DOWN_E(x) ( (x&0x1)<<13)
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154 #define s_RGA2_DST_INFO_SW_DITHER_MODE(x) ( (x&0x3)<<14)
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155 #define s_RGA2_DST_INFO_SW_DST_CSC_MODE(x) ( (x&0x3)<<16) //add
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156 #define s_RGA2_DST_INFO_SW_CSC_CLIP_MODE(x) ( (x&0x1)<<18)
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159 /* RGA_ALPHA_CTRL0 */
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160 #define m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0 ( 0x1<<0 )
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161 #define m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL ( 0x1<<1 )
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162 #define m_RGA2_ALPHA_CTRL0_SW_ROP_MODE ( 0x3<<2 )
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163 #define m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA ( 0xff<<4 )
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164 #define m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA ( 0xff<<12 )
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165 #define m_RGA2_ALPHA_CTRLO_SW_MASK_ENDIAN ( 0x1<<20 ) //add
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167 #define s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0(x) ( (x&0x1)<<0 )
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168 #define s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL(x) ( (x&0x1)<<1 )
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169 #define s_RGA2_ALPHA_CTRL0_SW_ROP_MODE(x) ( (x&0x3)<<2 )
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170 #define s_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA(x) ( (x&0xff)<<4 )
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171 #define s_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA(x) ( (x&0xff)<<12 )
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172 #define s_RGA2_ALPHA_CTRLO_SW_MASK_ENDIAN(x) ( (x&0x1)<<20 ) //add
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176 /* RGA_ALPHA_CTRL1 */
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177 #define m_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0 ( 0x1<<0 )
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178 #define m_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0 ( 0x1<<1 )
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179 #define m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0 ( 0x7<<2 )
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180 #define m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0 ( 0x7<<5 )
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181 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0 ( 0x1<<8 )
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182 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0 ( 0x1<<9 )
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183 #define m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0 ( 0x3<<10)
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184 #define m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0 ( 0x3<<12)
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185 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0 ( 0x1<<14)
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186 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0 ( 0x1<<15)
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187 #define m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1 ( 0x7<<16)
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188 #define m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1 ( 0x7<<19)
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189 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1 ( 0x1<<22)
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190 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1 ( 0x1<<23)
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191 #define m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1 ( 0x3<<24)
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192 #define m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1 ( 0x3<<26)
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193 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1 ( 0x1<<28)
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194 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1 ( 0x1<<29)
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196 #define s_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0(x) ( (x&0x1)<<0 )
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197 #define s_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0(x) ( (x&0x1)<<1 )
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198 #define s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0(x) ( (x&0x7)<<2 )
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199 #define s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0(x) ( (x&0x7)<<5 )
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200 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0(x) ( (x&0x1)<<8 )
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201 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0(x) ( (x&0x1)<<9 )
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202 #define s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0(x) ( (x&0x3)<<10)
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203 #define s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0(x) ( (x&0x3)<<12)
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204 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0(x) ( (x&0x1)<<14)
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205 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0(x) ( (x&0x1)<<15)
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206 #define s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1(x) ( (x&0x7)<<16)
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207 #define s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1(x) ( (x&0x7)<<19)
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208 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1(x) ( (x&0x1)<<22)
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209 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1(x) ( (x&0x1)<<23)
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210 #define s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1(x) ( (x&0x3)<<24)
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211 #define s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1(x) ( (x&0x3)<<26)
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212 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1(x) ( (x&0x1)<<28)
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213 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1(x) ( (x&0x1)<<29)
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217 /* RGA_MMU_CTRL1 */
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218 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_EN ( 0x1<<0 )
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219 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_FLUSH ( 0x1<<1 )
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220 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_EN ( 0x1<<2 )
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221 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_DIR ( 0x1<<3 )
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222 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_EN ( 0x1<<4 )
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223 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_FLUSH ( 0x1<<5 )
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224 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_EN ( 0x1<<6 )
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225 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_DIR ( 0x1<<7 )
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226 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_EN ( 0x1<<8 )
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227 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_FLUSH ( 0x1<<9 )
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228 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_EN ( 0x1<<10 )
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229 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_DIR ( 0x1<<11 )
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230 #define m_RGA2_MMU_CTRL1_SW_ELS_MMU_EN ( 0x1<<12 )
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231 #define m_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH ( 0x1<<13 )
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233 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_EN(x) ( (x&0x1)<<0 )
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234 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_FLUSH(x) ( (x&0x1)<<1 )
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235 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_EN(x) ( (x&0x1)<<2 )
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236 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_DIR(x) ( (x&0x1)<<3 )
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237 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_EN(x) ( (x&0x1)<<4 )
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238 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_FLUSH(x) ( (x&0x1)<<5 )
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239 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_EN(x) ( (x&0x1)<<6 )
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240 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_DIR(x) ( (x&0x1)<<7 )
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241 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_EN(x) ( (x&0x1)<<8 )
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242 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_FLUSH(x) ( (x&0x1)<<9 )
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243 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_EN(x) ( (x&0x1)<<10 )
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244 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_DIR(x) ( (x&0x1)<<11 )
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245 #define s_RGA2_MMU_CTRL1_SW_ELS_MMU_EN(x) ( (x&0x1)<<12 )
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246 #define s_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH(x) ( (x&0x1)<<13 )
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249 #define RGA2_SYS_CTRL_OFFSET 0x0
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250 #define RGA2_CMD_CTRL_OFFSET 0x4
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251 #define RGA2_CMD_BASE_OFFSET 0x8
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252 #define RGA2_STATUS_OFFSET 0xc
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253 #define RGA2_INT_OFFSET 0x10
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254 #define RGA2_MMU_CTRL0_OFFSET 0x14
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255 #define RGA2_MMU_CMD_BASE_OFFSET 0x18
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257 #define RGA2_MODE_CTRL_OFFSET 0x00
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258 #define RGA2_SRC_INFO_OFFSET 0x04
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259 #define RGA2_SRC_BASE0_OFFSET 0x08
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260 #define RGA2_SRC_BASE1_OFFSET 0x0c
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261 #define RGA2_SRC_BASE2_OFFSET 0x10
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262 #define RGA2_SRC_BASE3_OFFSET 0x14
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263 #define RGA2_SRC_VIR_INFO_OFFSET 0x18
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264 #define RGA2_SRC_ACT_INFO_OFFSET 0x1c
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265 #define RGA2_SRC_X_FACTOR_OFFSET 0x20
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266 #define RGA2_SRC_Y_FACTOR_OFFSET 0x24
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267 #define RGA2_SRC_BG_COLOR_OFFSET 0x28
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268 #define RGA2_SRC_FG_COLOR_OFFSET 0x2c
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269 #define RGA2_SRC_TR_COLOR0_OFFSET 0x30
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270 #define RGA2_CF_GR_A_OFFSET 0x30 // repeat
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271 #define RGA2_SRC_TR_COLOR1_OFFSET 0x34
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272 #define RGA2_CF_GR_B_OFFSET 0x34 // repeat
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273 #define RGA2_DST_INFO_OFFSET 0x38
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274 #define RGA2_DST_BASE0_OFFSET 0x3c
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275 #define RGA2_DST_BASE1_OFFSET 0x40
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276 #define RGA2_DST_BASE2_OFFSET 0x44
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277 #define RGA2_DST_VIR_INFO_OFFSET 0x48
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278 #define RGA2_DST_ACT_INFO_OFFSET 0x4c
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279 #define RGA2_ALPHA_CTRL0_OFFSET 0x50
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280 #define RGA2_ALPHA_CTRL1_OFFSET 0x54
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281 #define RGA2_FADING_CTRL_OFFSET 0x58
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282 #define RGA2_PAT_CON_OFFSET 0x5c
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283 #define RGA2_ROP_CTRL0_OFFSET 0x60
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284 #define RGA2_CF_GR_G_OFFSET 0x60 // repeat
\r
285 #define RGA2_ROP_CTRL1_OFFSET 0x64
\r
286 #define RGA2_CF_GR_R_OFFSET 0x64 // repeat
\r
287 #define RGA2_MASK_BASE_OFFSET 0x68
\r
288 #define RGA2_MMU_CTRL1_OFFSET 0x6c
\r
289 #define RGA2_MMU_SRC_BASE_OFFSET 0x70
\r
290 #define RGA2_MMU_SRC1_BASE_OFFSET 0x74
\r
291 #define RGA2_MMU_DST_BASE_OFFSET 0x78
\r
292 #define RGA2_MMU_ELS_BASE_OFFSET 0x7c
\r
294 int RGA2_gen_reg_info(unsigned char *base, struct rga2_req *msg);
\r
295 void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req);
\r
296 void RGA_MSG_2_RGA2_MSG_32(struct rga_req_32 *req_rga, struct rga2_req *req);
\r
projects / firefly-linux-kernel-4.4.55.git / blob