drivers/video/rockchip/lcdc/rk3368_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3368_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *Author:hjc<hjc@rock-chips.com>
   6  *This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk3368_lcdc.h"
  39
  40 #if defined(CONFIG_HAS_EARLYSUSPEND)
  41 #include <linux/earlysuspend.h>
  42 #endif
  43 /*#define CONFIG_RK_FPGA 1*/
  44
  45 static int dbg_thresd;
  46 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  47
  48 #define DBG(level, x...) do {                   \
  49         if (unlikely(dbg_thresd >= level))      \
  50                 pr_info(x);\
  51         } while (0)
  52
  53 static struct rk_lcdc_win lcdc_win[] = {
  54         [0] = {
  55                .name = "win0",
  56                .id = 0,
  57                .support_3d = false,
  58                },
  59         [1] = {
  60                .name = "win1",
  61                .id = 1,
  62                .support_3d = false,
  63                },
  64         [2] = {
  65                .name = "win2",
  66                .id = 2,
  67                .support_3d = false,
  68                },
  69         [3] = {
  70                .name = "win3",
  71                .id = 3,
  72                .support_3d = false,
  73                },
  74         [4] = {
  75                .name = "hwc",
  76                .id = 4,
  77                .support_3d = false,
  78                }
  79 };
  80
  81 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
  82
  83 /*#define WAIT_FOR_SYNC 1*/
  84 u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth)
  85 {
  86         u32 vscalednmult;
  87
  88         if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  89                 vscalednmult = 4;
  90         else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  91                 vscalednmult = 2;
  92         else
  93                 vscalednmult = 1;
  94
  95         return vscalednmult;
  96 }
  97
  98
  99 static int rk3368_set_cabc_lut(struct rk_lcdc_driver *dev_drv, int *cabc_lut)
 100 {
 101         int i;
 102         int __iomem *c;
 103         u32 v;
 104         struct lcdc_device *lcdc_dev =
 105             container_of(dev_drv, struct lcdc_device, driver);
 106
 107         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 108                      v_CABC_LUT_EN(0));
 109         lcdc_cfg_done(lcdc_dev);
 110         mdelay(25);
 111         for (i = 0; i < 256; i++) {
 112                 v = cabc_lut[i];
 113                 c = lcdc_dev->cabc_lut_addr_base + i;
 114                 writel_relaxed(v, c);
 115         }
 116         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 117                      v_CABC_LUT_EN(1));
 118         return 0;
 119 }
 120
 121
 122 static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
 123 {
 124         int i;
 125         int __iomem *c;
 126         u32 v;
 127         struct lcdc_device *lcdc_dev =
 128             container_of(dev_drv, struct lcdc_device, driver);
 129
 130         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 131                      v_DSP_LUT_EN(0));
 132         lcdc_cfg_done(lcdc_dev);
 133         mdelay(25);
 134         for (i = 0; i < 256; i++) {
 135                 v = dsp_lut[i];
 136                 c = lcdc_dev->dsp_lut_addr_base + i;
 137                 writel_relaxed(v, c);
 138         }
 139         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 140                      v_DSP_LUT_EN(1));
 141
 142         return 0;
 143 }
 144
 145 static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 146 {
 147 #ifdef CONFIG_RK_FPGA
 148         lcdc_dev->clk_on = 1;
 149         return 0;
 150 #endif
 151         if (!lcdc_dev->clk_on) {
 152                 clk_prepare_enable(lcdc_dev->hclk);
 153                 clk_prepare_enable(lcdc_dev->dclk);
 154                 clk_prepare_enable(lcdc_dev->aclk);
 155                 /*clk_prepare_enable(lcdc_dev->pd);*/
 156                 spin_lock(&lcdc_dev->reg_lock);
 157                 lcdc_dev->clk_on = 1;
 158                 spin_unlock(&lcdc_dev->reg_lock);
 159         }
 160
 161         return 0;
 162 }
 163
 164 static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 165 {
 166 #ifdef CONFIG_RK_FPGA
 167         lcdc_dev->clk_on = 0;
 168         return 0;
 169 #endif
 170         if (lcdc_dev->clk_on) {
 171                 spin_lock(&lcdc_dev->reg_lock);
 172                 lcdc_dev->clk_on = 0;
 173                 spin_unlock(&lcdc_dev->reg_lock);
 174                 mdelay(25);
 175                 clk_disable_unprepare(lcdc_dev->dclk);
 176                 clk_disable_unprepare(lcdc_dev->hclk);
 177                 clk_disable_unprepare(lcdc_dev->aclk);
 178                 /*clk_disable_unprepare(lcdc_dev->pd);*/
 179         }
 180
 181         return 0;
 182 }
 183
 184 static int __maybe_unused
 185         rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 186 {
 187         u32 mask, val;
 188
 189         spin_lock(&lcdc_dev->reg_lock);
 190         if (likely(lcdc_dev->clk_on)) {
 191                 mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN |
 192                     m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN |
 193                     m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN |
 194                     m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
 195                     m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
 196                     m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
 197                     m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN;
 198                 val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) |
 199                     v_ADDR_SAME_INTR_EN(0) |
 200                     v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) |
 201                     v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) |
 202                     v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) |
 203                     v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) |
 204                     v_POST_BUF_EMPTY_INTR_EN(0) |
 205                     v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0);
 206                 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
 207
 208                 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR |
 209                     m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
 210                     m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR |
 211                     m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
 212                     m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
 213                     m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
 214                     m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR;
 215                 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
 216                     v_ADDR_SAME_INTR_CLR(1) |
 217                     v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) |
 218                     v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) |
 219                     v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) |
 220                     v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) |
 221                     v_POST_BUF_EMPTY_INTR_CLR(1) |
 222                     v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1);
 223                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
 224                 lcdc_cfg_done(lcdc_dev);
 225                 spin_unlock(&lcdc_dev->reg_lock);
 226         } else {
 227                 spin_unlock(&lcdc_dev->reg_lock);
 228         }
 229         mdelay(1);
 230         return 0;
 231 }
 232
 233 static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
 234 {
 235         struct lcdc_device *lcdc_dev =
 236             container_of(dev_drv, struct lcdc_device, driver);
 237         int *cbase = (int *)lcdc_dev->regs;
 238         int *regsbak = (int *)lcdc_dev->regsbak;
 239         int i, j, val;
 240         char dbg_message[30];
 241         char buf[10];
 242
 243         pr_info("lcd back up reg:\n");
 244         memset(dbg_message, 0, sizeof(dbg_message));
 245         memset(buf, 0, sizeof(buf));
 246         for (i = 0; i <= (0x200 >> 4); i++) {
 247                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 248                 for (j = 0; j < 4; j++) {
 249                         val = sprintf(buf, "%08x  ", *(regsbak + i * 4 + j));
 250                         strcat(dbg_message, buf);
 251                 }
 252                 pr_info("%s\n", dbg_message);
 253                 memset(dbg_message, 0, sizeof(dbg_message));
 254                 memset(buf, 0, sizeof(buf));
 255         }
 256
 257         pr_info("lcdc reg:\n");
 258         for (i = 0; i <= (0x200 >> 4); i++) {
 259                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 260                 for (j = 0; j < 4; j++) {
 261                         sprintf(buf, "%08x  ",
 262                                 readl_relaxed(cbase + i * 4 + j));
 263                         strcat(dbg_message, buf);
 264                 }
 265                 pr_info("%s\n", dbg_message);
 266                 memset(dbg_message, 0, sizeof(dbg_message));
 267                 memset(buf, 0, sizeof(buf));
 268         }
 269
 270         return 0;
 271 }
 272
 273 #define WIN_EN(id)              \
 274 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en)       \
 275 { \
 276         u32 msk, val;                                                   \
 277         spin_lock(&lcdc_dev->reg_lock);                                 \
 278         msk =  m_WIN##id##_EN;                                          \
 279         val  =  v_WIN##id##_EN(en);                                     \
 280         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);              \
 281         lcdc_cfg_done(lcdc_dev);                                        \
 282         val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);            \
 283         while (val !=  (!!en))  {                                       \
 284                 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);    \
 285         }                                                               \
 286         spin_unlock(&lcdc_dev->reg_lock);                               \
 287         return 0;                                                       \
 288 }
 289
 290 WIN_EN(0);
 291 WIN_EN(1);
 292 WIN_EN(2);
 293 WIN_EN(3);
 294 /*enable/disable win directly*/
 295 static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv,
 296                                      int win_id, int en)
 297 {
 298         struct lcdc_device *lcdc_dev =
 299             container_of(drv, struct lcdc_device, driver);
 300         if (win_id == 0)
 301                 win0_enable(lcdc_dev, en);
 302         else if (win_id == 1)
 303                 win1_enable(lcdc_dev, en);
 304         else if (win_id == 2)
 305                 win2_enable(lcdc_dev, en);
 306         else if (win_id == 3)
 307                 win3_enable(lcdc_dev, en);
 308         else
 309                 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
 310         return 0;
 311 }
 312
 313 #define SET_WIN_ADDR(id) \
 314 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
 315 {                                                       \
 316         u32 msk, val;                                   \
 317         spin_lock(&lcdc_dev->reg_lock);                 \
 318         lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr);        \
 319         msk =  m_WIN##id##_EN;                          \
 320         val  =  v_WIN0_EN(1);                           \
 321         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);      \
 322         lcdc_cfg_done(lcdc_dev);                        \
 323         spin_unlock(&lcdc_dev->reg_lock);               \
 324         return 0;                                       \
 325 }
 326
 327 SET_WIN_ADDR(0);
 328 SET_WIN_ADDR(1);
 329 int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
 330                                     int win_id, u32 addr)
 331 {
 332         struct lcdc_device *lcdc_dev =
 333             container_of(dev_drv, struct lcdc_device, driver);
 334         if (win_id == 0)
 335                 set_win0_addr(lcdc_dev, addr);
 336         else
 337                 set_win1_addr(lcdc_dev, addr);
 338
 339         return 0;
 340 }
 341
 342 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 343 {
 344         int reg = 0;
 345         u32 val = 0;
 346         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 347         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 348         u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 349         u32 st_x, st_y;
 350         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 351
 352         spin_lock(&lcdc_dev->reg_lock);
 353         for (reg = 0; reg < SCAN_LINE_NUM; reg += 4) {
 354                 val = lcdc_readl_backup(lcdc_dev, reg);
 355                 switch (reg) {
 356                 case WIN0_ACT_INFO:
 357                         win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1;
 358                         win0->area[0].yact =
 359                             ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
 360                         break;
 361                 case WIN0_DSP_INFO:
 362                         win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1;
 363                         win0->area[0].ysize =
 364                             ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
 365                         break;
 366                 case WIN0_DSP_ST:
 367                         st_x = val & m_WIN0_DSP_XST;
 368                         st_y = (val & m_WIN0_DSP_YST) >> 16;
 369                         win0->area[0].xpos = st_x - h_pw_bp;
 370                         win0->area[0].ypos = st_y - v_pw_bp;
 371                         break;
 372                 case WIN0_CTRL0:
 373                         win0->state = val & m_WIN0_EN;
 374                         win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1;
 375                         win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
 376                         win0->area[0].format = win0->area[0].fmt_cfg;
 377                         break;
 378                 case WIN0_VIR:
 379                         win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE;
 380                         win0->area[0].uv_vir_stride =
 381                             (val & m_WIN0_VIR_STRIDE_UV) >> 16;
 382                         if (win0->area[0].format == ARGB888)
 383                                 win0->area[0].xvir = win0->area[0].y_vir_stride;
 384                         else if (win0->area[0].format == RGB888)
 385                                 win0->area[0].xvir =
 386                                     win0->area[0].y_vir_stride * 4 / 3;
 387                         else if (win0->area[0].format == RGB565)
 388                                 win0->area[0].xvir =
 389                                     2 * win0->area[0].y_vir_stride;
 390                         else    /* YUV */
 391                                 win0->area[0].xvir =
 392                                     4 * win0->area[0].y_vir_stride;
 393                         break;
 394                 case WIN0_YRGB_MST:
 395                         win0->area[0].smem_start = val;
 396                         break;
 397                 case WIN0_CBR_MST:
 398                         win0->area[0].cbr_start = val;
 399                         break;
 400                 default:
 401                         break;
 402                 }
 403         }
 404         spin_unlock(&lcdc_dev->reg_lock);
 405 }
 406
 407 /********do basic init*********/
 408 static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 409 {
 410         u32 mask, val, v;
 411         struct lcdc_device *lcdc_dev =
 412             container_of(dev_drv, struct lcdc_device, driver);
 413         if (lcdc_dev->pre_init)
 414                 return 0;
 415
 416         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 417         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 418         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 419         /*lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");*/
 420
 421         if (/*IS_ERR(lcdc_dev->pd) || */(IS_ERR(lcdc_dev->aclk)) ||
 422             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 423                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 424                         lcdc_dev->id);
 425         }
 426
 427         rk_disp_pwr_enable(dev_drv);
 428         rk3368_lcdc_clk_enable(lcdc_dev);
 429
 430         /*backup reg config at uboot */
 431         lcdc_read_reg_defalut_cfg(lcdc_dev);
 432         if (lcdc_dev->pwr18 == 1) {
 433                 v = 0x00200020; /*bit5: 1,1.8v;0,3.3v*/
 434                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 435                                 PMUGRF_SOC_CON0_VOP, v);
 436         } else {
 437                 v = 0x00200000; /*bit5: 1,1.8v;0,3.3v*/
 438                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 439                                 PMUGRF_SOC_CON0_VOP, v);
 440         }
 441         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_0, 0x15110903);
 442         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_1, 0x00030911);
 443         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_0, 0x1a150b04);
 444         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_1, 0x00040b15);
 445         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_0, 0x15110903);
 446         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_1, 0x00030911);
 447
 448         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 449         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 450         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696);
 451         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969);
 452         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 453         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 454
 455         mask = m_AUTO_GATING_EN;
 456         val = v_AUTO_GATING_EN(0);
 457         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 458         lcdc_cfg_done(lcdc_dev);
 459         /*disable win0 to workaround iommu pagefault */
 460         /*if (dev_drv->iommu_enabled) */
 461         /*      win0_enable(lcdc_dev, 0); */
 462         lcdc_dev->pre_init = true;
 463
 464         return 0;
 465 }
 466
 467 static void rk3368_lcdc_deint(struct lcdc_device *lcdc_dev)
 468 {
 469 }
 470
 471 static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
 472 {
 473         struct lcdc_device *lcdc_dev =
 474             container_of(dev_drv, struct lcdc_device, driver);
 475         struct rk_screen *screen = dev_drv->cur_screen;
 476         u16 x_res = screen->mode.xres;
 477         u16 y_res = screen->mode.yres;
 478         u32 mask, val;
 479         u16 h_total, v_total;
 480         u16 post_hsd_en, post_vsd_en;
 481         u16 post_dsp_hact_st, post_dsp_hact_end;
 482         u16 post_dsp_vact_st, post_dsp_vact_end;
 483         u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
 484         u16 post_h_fac, post_v_fac;
 485
 486         h_total = screen->mode.hsync_len + screen->mode.left_margin +
 487             x_res + screen->mode.right_margin;
 488         v_total = screen->mode.vsync_len + screen->mode.upper_margin +
 489             y_res + screen->mode.lower_margin;
 490
 491         if (screen->post_dsp_stx + screen->post_xsize > x_res) {
 492                 dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
 493                          screen->post_dsp_stx, screen->post_xsize, x_res);
 494                 screen->post_dsp_stx = x_res - screen->post_xsize;
 495         }
 496         if (screen->x_mirror == 0) {
 497                 post_dsp_hact_st = screen->post_dsp_stx +
 498                     screen->mode.hsync_len + screen->mode.left_margin;
 499                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 500         } else {
 501                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 502                     screen->post_dsp_stx;
 503                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 504         }
 505         if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
 506                 post_hsd_en = 1;
 507                 post_h_fac =
 508                     GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
 509         } else {
 510                 post_hsd_en = 0;
 511                 post_h_fac = 0x1000;
 512         }
 513
 514         if (screen->post_dsp_sty + screen->post_ysize > y_res) {
 515                 dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
 516                          screen->post_dsp_sty, screen->post_ysize, y_res);
 517                 screen->post_dsp_sty = y_res - screen->post_ysize;
 518         }
 519
 520         if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
 521                 post_vsd_en = 1;
 522                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
 523                                                       screen->post_ysize);
 524         } else {
 525                 post_vsd_en = 0;
 526                 post_v_fac = 0x1000;
 527         }
 528
 529         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
 530                 post_dsp_vact_st = screen->post_dsp_sty / 2 +
 531                                         screen->mode.vsync_len +
 532                                         screen->mode.upper_margin;
 533                 post_dsp_vact_end = post_dsp_vact_st +
 534                                         screen->post_ysize / 2;
 535
 536                 post_dsp_vact_st_f1 = screen->mode.vsync_len +
 537                                       screen->mode.upper_margin +
 538                                       y_res/2 +
 539                                       screen->mode.lower_margin +
 540                                       screen->mode.vsync_len +
 541                                       screen->mode.upper_margin +
 542                                       screen->post_dsp_sty / 2 +
 543                                       1;
 544                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
 545                                         screen->post_ysize/2;
 546         } else {
 547                 if (screen->y_mirror == 0) {
 548                         post_dsp_vact_st = screen->post_dsp_sty +
 549                             screen->mode.vsync_len +
 550                             screen->mode.upper_margin;
 551                         post_dsp_vact_end = post_dsp_vact_st +
 552                                 screen->post_ysize;
 553                 } else {
 554                         post_dsp_vact_end = v_total -
 555                                 screen->mode.lower_margin -
 556                             screen->post_dsp_sty;
 557                         post_dsp_vact_st = post_dsp_vact_end -
 558                                 screen->post_ysize;
 559                 }
 560                 post_dsp_vact_st_f1 = 0;
 561                 post_dsp_vact_end_f1 = 0;
 562         }
 563         DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
 564             screen->post_xsize, screen->post_ysize, screen->xpos);
 565         DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 566             screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
 567         mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
 568         val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
 569             v_DSP_HACT_ST_POST(post_dsp_hact_st);
 570         lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
 571
 572         mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
 573         val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
 574             v_DSP_VACT_ST_POST(post_dsp_vact_st);
 575         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
 576
 577         mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
 578         val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
 579             v_POST_VS_FACTOR_YRGB(post_v_fac);
 580         lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
 581
 582         mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
 583         val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
 584             v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
 585         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
 586
 587         mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
 588         val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
 589         lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
 590         return 0;
 591 }
 592
 593 static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 594 {
 595         struct lcdc_device *lcdc_dev =
 596             container_of(dev_drv, struct lcdc_device, driver);
 597         struct rk_lcdc_win *win;
 598         u32 colorkey_r, colorkey_g, colorkey_b;
 599         int i, key_val;
 600
 601         for (i = 0; i < 4; i++) {
 602                 win = dev_drv->win[i];
 603                 key_val = win->color_key_val;
 604                 colorkey_r = (key_val & 0xff) << 2;
 605                 colorkey_g = ((key_val >> 8) & 0xff) << 12;
 606                 colorkey_b = ((key_val >> 16) & 0xff) << 22;
 607                 /*color key dither 565/888->aaa */
 608                 key_val = colorkey_r | colorkey_g | colorkey_b;
 609                 switch (i) {
 610                 case 0:
 611                         lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
 612                         break;
 613                 case 1:
 614                         lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
 615                         break;
 616                 case 2:
 617                         lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
 618                         break;
 619                 case 3:
 620                         lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
 621                         break;
 622                 default:
 623                         pr_info("%s:un support win num:%d\n",
 624                                 __func__, i);
 625                         break;
 626                 }
 627         }
 628         return 0;
 629 }
 630
 631 static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
 632 {
 633         struct lcdc_device *lcdc_dev =
 634             container_of(dev_drv, struct lcdc_device, driver);
 635         struct rk_lcdc_win *win = dev_drv->win[win_id];
 636         struct alpha_config alpha_config;
 637         u32 mask, val;
 638         int ppixel_alpha = 0, global_alpha = 0, i;
 639         u32 src_alpha_ctl, dst_alpha_ctl;
 640
 641         for (i = 0; i < win->area_num; i++) {
 642                 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
 643                                  (win->area[i].format == FBDC_ARGB_888) ||
 644                                  (win->area[i].format == ABGR888)) ? 1 : 0;
 645         }
 646         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 647         alpha_config.src_global_alpha_val = win->g_alpha_val;
 648         win->alpha_mode = AB_SRC_OVER;
 649         /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
 650            __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,
 651            global_alpha); */
 652         switch (win->alpha_mode) {
 653         case AB_USER_DEFINE:
 654                 break;
 655         case AB_CLEAR:
 656                 alpha_config.src_factor_mode = AA_ZERO;
 657                 alpha_config.dst_factor_mode = AA_ZERO;
 658                 break;
 659         case AB_SRC:
 660                 alpha_config.src_factor_mode = AA_ONE;
 661                 alpha_config.dst_factor_mode = AA_ZERO;
 662                 break;
 663         case AB_DST:
 664                 alpha_config.src_factor_mode = AA_ZERO;
 665                 alpha_config.dst_factor_mode = AA_ONE;
 666                 break;
 667         case AB_SRC_OVER:
 668                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 669                 if (global_alpha)
 670                         alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 671                 else
 672                         alpha_config.src_factor_mode = AA_ONE;
 673                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 674                 break;
 675         case AB_DST_OVER:
 676                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 677                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 678                 alpha_config.dst_factor_mode = AA_ONE;
 679                 break;
 680         case AB_SRC_IN:
 681                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 682                 alpha_config.src_factor_mode = AA_SRC;
 683                 alpha_config.dst_factor_mode = AA_ZERO;
 684                 break;
 685         case AB_DST_IN:
 686                 alpha_config.src_factor_mode = AA_ZERO;
 687                 alpha_config.dst_factor_mode = AA_SRC;
 688                 break;
 689         case AB_SRC_OUT:
 690                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 691                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 692                 alpha_config.dst_factor_mode = AA_ZERO;
 693                 break;
 694         case AB_DST_OUT:
 695                 alpha_config.src_factor_mode = AA_ZERO;
 696                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 697                 break;
 698         case AB_SRC_ATOP:
 699                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 700                 alpha_config.src_factor_mode = AA_SRC;
 701                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 702                 break;
 703         case AB_DST_ATOP:
 704                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 705                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 706                 alpha_config.dst_factor_mode = AA_SRC;
 707                 break;
 708         case XOR:
 709                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 710                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 711                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 712                 break;
 713         case AB_SRC_OVER_GLOBAL:
 714                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 715                 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
 716                 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 717                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 718                 break;
 719         default:
 720                 pr_err("alpha mode error\n");
 721                 break;
 722         }
 723         if ((ppixel_alpha == 1) && (global_alpha == 1))
 724                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 725         else if (ppixel_alpha == 1)
 726                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 727         else if (global_alpha == 1)
 728                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 729         else
 730                 dev_warn(lcdc_dev->dev, "alpha_en should be 0\n");
 731         alpha_config.src_alpha_mode = AA_STRAIGHT;
 732         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 733
 734         switch (win_id) {
 735         case 0:
 736                 src_alpha_ctl = 0x60;
 737                 dst_alpha_ctl = 0x64;
 738                 break;
 739         case 1:
 740                 src_alpha_ctl = 0xa0;
 741                 dst_alpha_ctl = 0xa4;
 742                 break;
 743         case 2:
 744                 src_alpha_ctl = 0xdc;
 745                 dst_alpha_ctl = 0xec;
 746                 break;
 747         case 3:
 748                 src_alpha_ctl = 0x12c;
 749                 dst_alpha_ctl = 0x13c;
 750                 break;
 751         case 4:
 752                 src_alpha_ctl = 0x160;
 753                 dst_alpha_ctl = 0x164;
 754                 break;
 755         }
 756         mask = m_WIN0_DST_FACTOR_M0;
 757         val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
 758         lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
 759         mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
 760             m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
 761             m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 |
 762             m_WIN0_SRC_GLOBAL_ALPHA;
 763         val = v_WIN0_SRC_ALPHA_EN(1) |
 764             v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
 765             v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
 766             v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
 767             v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
 768             v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
 769             v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 770         lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
 771
 772         return 0;
 773 }
 774
 775 static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num)
 776 {
 777         struct rk_lcdc_win_area area_temp;
 778         int i, j;
 779
 780         for (i = 0; i < area_num; i++) {
 781                 for (j = i + 1; j < area_num; j++) {
 782                         if (win->area[i].dsp_stx >  win->area[j].dsp_stx) {
 783                                 memcpy(&area_temp, &win->area[i],
 784                                        sizeof(struct rk_lcdc_win_area));
 785                                 memcpy(&win->area[i], &win->area[j],
 786                                        sizeof(struct rk_lcdc_win_area));
 787                                 memcpy(&win->area[j], &area_temp,
 788                                        sizeof(struct rk_lcdc_win_area));
 789                         }
 790                 }
 791         }
 792
 793         return 0;
 794 }
 795
 796 static int __maybe_unused
 797         rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num)
 798 {
 799         struct rk_lcdc_win_area area_temp;
 800
 801         switch (area_num) {
 802         case 2:
 803                 area_temp = win->area[0];
 804                 win->area[0] = win->area[1];
 805                 win->area[1] = area_temp;
 806                 break;
 807         case 3:
 808                 area_temp = win->area[0];
 809                 win->area[0] = win->area[2];
 810                 win->area[2] = area_temp;
 811                 break;
 812         case 4:
 813                 area_temp = win->area[0];
 814                 win->area[0] = win->area[3];
 815                 win->area[3] = area_temp;
 816
 817                 area_temp = win->area[1];
 818                 win->area[1] = win->area[2];
 819                 win->area[2] = area_temp;
 820                 break;
 821         default:
 822                 pr_info("un supported area num!\n");
 823                 break;
 824         }
 825         return 0;
 826 }
 827
 828 static int __maybe_unused
 829 rk3368_win_area_check_var(int win_id, int area_num,
 830                           struct rk_lcdc_win_area *area_pre,
 831                           struct rk_lcdc_win_area *area_now)
 832 {
 833         if ((area_pre->xpos > area_now->xpos) ||
 834             ((area_pre->xpos + area_pre->xsize > area_now->xpos) &&
 835              (area_pre->ypos + area_pre->ysize > area_now->ypos))) {
 836                 area_now->state = 0;
 837                 pr_err("win[%d]:\n"
 838                        "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n"
 839                        "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n",
 840                        win_id,
 841                        area_num - 1, area_pre->xpos, area_pre->xsize,
 842                        area_pre->ypos, area_pre->ysize,
 843                        area_num, area_now->xpos, area_now->xsize,
 844                        area_now->ypos, area_now->ysize);
 845                 return -EINVAL;
 846         }
 847         return 0;
 848 }
 849
 850 static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv)
 851 {
 852         struct lcdc_device *lcdc_dev =
 853             container_of(dev_drv, struct lcdc_device, driver);
 854         u32 val, i;
 855
 856         for (i = 0; i < 100; i++) {
 857                 val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0);
 858                 val &= m_DBG_IFBDC_IDLE;
 859                 if (val)
 860                         continue;
 861                 else
 862                         mdelay(10);
 863         };
 864         return val;
 865 }
 866
 867 static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
 868 {
 869         struct lcdc_device *lcdc_dev =
 870             container_of(dev_drv, struct lcdc_device, driver);
 871         struct rk_lcdc_win *win = dev_drv->win[win_id];
 872         u32 mask, val;
 873
 874         mask = m_IFBDC_CTRL_FBDC_EN | m_IFBDC_CTRL_FBDC_COR_EN |
 875             m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE |
 876             m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO;
 877         val = v_IFBDC_CTRL_FBDC_EN(win->area[0].fbdc_en) |
 878             v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) |
 879             v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) |
 880             v_IFBDC_CTRL_FBDC_ROTATION_MODE(win->mirror_en << 1) |
 881             v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) |
 882             v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio);
 883         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
 884
 885         mask = m_IFBDC_TILES_NUM;
 886         val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles);
 887         lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val);
 888
 889         mask = m_IFBDC_BASE_ADDR;
 890         val = v_IFBDC_BASE_ADDR(win->area[0].y_addr);
 891         lcdc_msk_reg(lcdc_dev, IFBDC_BASE_ADDR, mask, val);
 892
 893         mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT;
 894         val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) |
 895             v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height);
 896         lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val);
 897
 898         mask = m_IFBDC_CMP_INDEX_INIT;
 899         val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init);
 900         lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val);
 901
 902         mask = m_IFBDC_MB_VIR_WIDTH;
 903         val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width);
 904         lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val);
 905
 906         return 0;
 907 }
 908
 909 static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id)
 910 {
 911         struct lcdc_device *lcdc_dev =
 912             container_of(dev_drv, struct lcdc_device, driver);
 913         struct rk_lcdc_win *win = dev_drv->win[win_id];
 914         u8 fbdc_dsp_width_ratio;
 915         u16 fbdc_mb_vir_width, fbdc_mb_vir_height;
 916         u16 fbdc_mb_width, fbdc_mb_height;
 917         u16 fbdc_mb_xst, fbdc_mb_yst, fbdc_num_tiles;
 918         u16 fbdc_cmp_index_init;
 919         u8 mb_w_size, mb_h_size;
 920         struct rk_screen *screen = dev_drv->cur_screen;
 921
 922         if (screen->mode.flag == FB_VMODE_INTERLACED) {
 923                 dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n");
 924                 return 0;
 925         }
 926
 927         switch (win->area[0].fmt_cfg) {
 928         case VOP_FORMAT_ARGB888:
 929                 fbdc_dsp_width_ratio = 0;
 930                 mb_w_size = 16;
 931                 break;
 932         case VOP_FORMAT_RGB888:
 933                 fbdc_dsp_width_ratio = 0;
 934                 mb_w_size = 16;
 935                 break;
 936         case VOP_FORMAT_RGB565:
 937                 fbdc_dsp_width_ratio = 1;
 938                 mb_w_size = 32;
 939                 break;
 940         default:
 941                 dev_err(lcdc_dev->dev,
 942                         "in fbdc mode,unsupport fmt:%d!\n",
 943                         win->area[0].fmt_cfg);
 944                 break;
 945         }
 946         mb_h_size = 4;
 947
 948         /*macro block xvir and yvir */
 949         if ((win->area[0].xvir % mb_w_size == 0) &&
 950             (win->area[0].yvir % mb_h_size == 0)) {
 951                 fbdc_mb_vir_width = win->area[0].xvir / mb_w_size;
 952                 fbdc_mb_vir_height = win->area[0].yvir / mb_h_size;
 953         } else {
 954                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 955                 pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n",
 956                        win->area[0].xvir, win->area[0].yvir,
 957                        mb_w_size, mb_h_size);
 958         }
 959         /*macro block xact and yact */
 960         if ((win->area[0].xact % mb_w_size == 0) &&
 961             (win->area[0].yact % mb_h_size == 0)) {
 962                 fbdc_mb_width = win->area[0].xact / mb_w_size;
 963                 fbdc_mb_height = win->area[0].yact / mb_h_size;
 964         } else {
 965                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 966                 pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n",
 967                        win->area[0].xact, win->area[0].yact,
 968                        mb_w_size, mb_h_size);
 969         }
 970         /*macro block xoff and yoff */
 971         if ((win->area[0].xoff % mb_w_size == 0) &&
 972             (win->area[0].yoff % mb_h_size == 0)) {
 973                 fbdc_mb_xst = win->area[0].xoff / mb_w_size;
 974                 fbdc_mb_yst = win->area[0].yoff / mb_h_size;
 975         } else {
 976                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 977                 pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n",
 978                        win->area[0].xoff, win->area[0].yoff,
 979                        mb_w_size, mb_h_size);
 980         }
 981
 982         /*FBDC tiles */
 983         fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height;
 984
 985         /*
 986            switch (fbdc_rotation_mode)  {
 987            case FBDC_ROT_NONE:
 988            fbdc_cmp_index_init =
 989            (fbdc_mb_yst*fbdc_mb_vir_width) +  fbdc_mb_xst;
 990            break;
 991            case FBDC_X_MIRROR:
 992            fbdc_cmp_index_init =
 993            (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+
 994            (fbdc_mb_width-1));
 995            break;
 996            case FBDC_Y_MIRROR:
 997            fbdc_cmp_index_init =
 998            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width)  +
 999            fbdc_mb_xst;
1000            break;
1001            case FBDC_ROT_180:
1002            fbdc_cmp_index_init =
1003            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
1004            (fbdc_mb_xst+(fbdc_mb_width-1));
1005            break;
1006            }
1007          */
1008         if ((win->mirror_en) && ((win_id == 2) || (win_id == 3))) {
1009                 fbdc_cmp_index_init =
1010                     ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) +
1011                     (fbdc_mb_xst + (fbdc_mb_width - 1));
1012         } else {
1013                 fbdc_cmp_index_init =
1014                     (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst;
1015         }
1016         /*fbdc fmt maybe need to change*/
1017         win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio;
1018         win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width;
1019         win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height;
1020         win->area[0].fbdc_mb_width = fbdc_mb_width;
1021         win->area[0].fbdc_mb_height = fbdc_mb_height;
1022         win->area[0].fbdc_mb_xst = fbdc_mb_xst;
1023         win->area[0].fbdc_mb_yst = fbdc_mb_yst;
1024         win->area[0].fbdc_num_tiles = fbdc_num_tiles;
1025         win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init;
1026
1027         return 0;
1028 }
1029
1030 static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev,
1031                                  struct rk_lcdc_win *win)
1032 {
1033         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1034         struct rk_screen *screen = dev_drv->cur_screen;
1035
1036         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1037                 switch (win->area[0].fmt_cfg) {
1038                 case VOP_FORMAT_ARGB888:
1039                 case VOP_FORMAT_RGB888:
1040                 case VOP_FORMAT_RGB565:
1041                         if ((screen->mode.xres < 1280) &&
1042                             (screen->mode.yres < 720)) {
1043                                 win->csc_mode = VOP_R2Y_CSC_BT601;
1044                         } else {
1045                                 win->csc_mode = VOP_R2Y_CSC_BT709;
1046                         }
1047                         break;
1048                 default:
1049                         break;
1050                 }
1051         } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
1052                 switch (win->area[0].fmt_cfg) {
1053                 case VOP_FORMAT_YCBCR420:
1054                         if ((win->id == 0) || (win->id == 1))
1055                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
1056                         break;
1057                 default:
1058                         break;
1059                 }
1060         }
1061 }
1062
1063 static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1064 {
1065         struct lcdc_device *lcdc_dev =
1066             container_of(dev_drv, struct lcdc_device, driver);
1067         struct rk_lcdc_win *win = dev_drv->win[win_id];
1068         unsigned int mask, val, off;
1069
1070         off = win_id * 0x40;
1071         /*if(win->win_lb_mode == 5)
1072            win->win_lb_mode = 4;
1073            for rk3288 to fix hw bug? */
1074
1075         if (win->state == 1) {
1076                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1077                 if (win->area[0].fbdc_en) {
1078                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1079                 } else {
1080                         mask = m_IFBDC_CTRL_FBDC_EN;
1081                         val = v_IFBDC_CTRL_FBDC_EN(0);
1082                         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1083                 }
1084                 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
1085                     m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR |
1086                     m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE;
1087                 val = v_WIN0_EN(win->state) |
1088                     v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1089                     v_WIN0_FMT_10(win->fmt_10) |
1090                     v_WIN0_LB_MODE(win->win_lb_mode) |
1091                     v_WIN0_RB_SWAP(win->area[0].swap_rb) |
1092                     v_WIN0_X_MIRROR(win->mirror_en) |
1093                     v_WIN0_Y_MIRROR(win->mirror_en) |
1094                     v_WIN0_CSC_MODE(win->csc_mode);
1095                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1096
1097                 mask = m_WIN0_BIC_COE_SEL |
1098                     m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
1099                     m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
1100                     m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
1101                     m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
1102                     m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
1103                     m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
1104                     m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
1105                 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1106                     v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1107                     v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1108                     v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1109                     v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1110                     v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1111                     v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1112                     v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1113                     v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1114                     v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1115                     v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1116                     v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1117                     v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1118                     v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1119                     v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1120                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val);
1121                 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1122                     v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1123                 lcdc_writel(lcdc_dev, WIN0_VIR + off, val);
1124                 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off,
1125                                 win->area[0].y_addr);
1126                    lcdc_writel(lcdc_dev, WIN0_CBR_MST+off,
1127                                 win->area[0].uv_addr); */
1128                 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
1129                     v_WIN0_ACT_HEIGHT(win->area[0].yact);
1130                 lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val);
1131
1132                 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
1133                     v_WIN0_DSP_HEIGHT(win->area[0].ysize);
1134                 lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val);
1135
1136                 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
1137                     v_WIN0_DSP_YST(win->area[0].dsp_sty);
1138                 lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val);
1139
1140                 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1141                     v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1142                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1143
1144                 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1145                     v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1146                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val);
1147                 if (win->alpha_en == 1) {
1148                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1149                 } else {
1150                         mask = m_WIN0_SRC_ALPHA_EN;
1151                         val = v_WIN0_SRC_ALPHA_EN(0);
1152                         lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off,
1153                                      mask, val);
1154                 }
1155         } else {
1156                 mask = m_WIN0_EN;
1157                 val = v_WIN0_EN(win->state);
1158                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1159         }
1160         return 0;
1161 }
1162
1163 static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1164 {
1165         struct lcdc_device *lcdc_dev =
1166             container_of(dev_drv, struct lcdc_device, driver);
1167         struct rk_lcdc_win *win = dev_drv->win[win_id];
1168         unsigned int mask, val, off;
1169
1170         off = (win_id - 2) * 0x50;
1171         rk3368_lcdc_area_xst(win, win->area_num);
1172
1173         if (win->state == 1) {
1174                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1175                 if (win->area[0].fbdc_en) {
1176                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1177                 } else {
1178                         mask = m_IFBDC_CTRL_FBDC_EN;
1179                         val = v_IFBDC_CTRL_FBDC_EN(0);
1180                         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1181                 }
1182
1183                 mask = m_WIN2_EN | m_WIN2_CSC_MODE;
1184                 val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode);
1185                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1186                 /*area 0 */
1187                 if (win->area[0].state == 1) {
1188                         mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 |
1189                             m_WIN2_RB_SWAP0;
1190                         val = v_WIN2_MST0_EN(win->area[0].state) |
1191                             v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1192                             v_WIN2_RB_SWAP0(win->area[0].swap_rb);
1193                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1194
1195                         mask = m_WIN2_VIR_STRIDE0;
1196                         val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1197                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1198
1199                         /*lcdc_writel(lcdc_dev,WIN2_MST0+off,
1200                            win->area[0].y_addr); */
1201                         val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1202                             v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1203                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val);
1204                         val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1205                             v_WIN2_DSP_YST0(win->area[0].dsp_sty);
1206                         lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val);
1207                 } else {
1208                         mask = m_WIN2_MST0_EN;
1209                         val = v_WIN2_MST0_EN(0);
1210                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1211                 }
1212                 /*area 1 */
1213                 if (win->area[1].state == 1) {
1214                         /*rk3368_win_area_check_var(win_id, 1,
1215                                                   &win->area[0], &win->area[1]);
1216                         */
1217
1218                         mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 |
1219                             m_WIN2_RB_SWAP1;
1220                         val = v_WIN2_MST1_EN(win->area[1].state) |
1221                             v_WIN2_DATA_FMT1(win->area[1].fmt_cfg) |
1222                             v_WIN2_RB_SWAP1(win->area[1].swap_rb);
1223                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1224
1225                         mask = m_WIN2_VIR_STRIDE1;
1226                         val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1227                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1228
1229                         /*lcdc_writel(lcdc_dev,WIN2_MST1+off,
1230                            win->area[1].y_addr); */
1231                         val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1232                             v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1233                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val);
1234                         val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1235                             v_WIN2_DSP_YST1(win->area[1].dsp_sty);
1236                         lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val);
1237                 } else {
1238                         mask = m_WIN2_MST1_EN;
1239                         val = v_WIN2_MST1_EN(0);
1240                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1241                 }
1242                 /*area 2 */
1243                 if (win->area[2].state == 1) {
1244                         /*rk3368_win_area_check_var(win_id, 2,
1245                                                   &win->area[1], &win->area[2]);
1246                         */
1247
1248                         mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 |
1249                             m_WIN2_RB_SWAP2;
1250                         val = v_WIN2_MST2_EN(win->area[2].state) |
1251                             v_WIN2_DATA_FMT2(win->area[2].fmt_cfg) |
1252                             v_WIN2_RB_SWAP2(win->area[2].swap_rb);
1253                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1254
1255                         mask = m_WIN2_VIR_STRIDE2;
1256                         val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1257                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1258
1259                         /*lcdc_writel(lcdc_dev,WIN2_MST2+off,
1260                            win->area[2].y_addr); */
1261                         val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1262                             v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1263                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val);
1264                         val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1265                             v_WIN2_DSP_YST2(win->area[2].dsp_sty);
1266                         lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val);
1267                 } else {
1268                         mask = m_WIN2_MST2_EN;
1269                         val = v_WIN2_MST2_EN(0);
1270                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1271                 }
1272                 /*area 3 */
1273                 if (win->area[3].state == 1) {
1274                         /*rk3368_win_area_check_var(win_id, 3,
1275                                                   &win->area[2], &win->area[3]);
1276                         */
1277
1278                         mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 |
1279                             m_WIN2_RB_SWAP3;
1280                         val = v_WIN2_MST3_EN(win->area[3].state) |
1281                             v_WIN2_DATA_FMT3(win->area[3].fmt_cfg) |
1282                             v_WIN2_RB_SWAP3(win->area[3].swap_rb);
1283                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1284
1285                         mask = m_WIN2_VIR_STRIDE3;
1286                         val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1287                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1288
1289                         /*lcdc_writel(lcdc_dev,WIN2_MST3+off,
1290                            win->area[3].y_addr); */
1291                         val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1292                             v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1293                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val);
1294                         val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1295                             v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1296                         lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val);
1297                 } else {
1298                         mask = m_WIN2_MST3_EN;
1299                         val = v_WIN2_MST3_EN(0);
1300                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1301                 }
1302
1303                 if (win->alpha_en == 1) {
1304                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1305                 } else {
1306                         mask = m_WIN2_SRC_ALPHA_EN;
1307                         val = v_WIN2_SRC_ALPHA_EN(0);
1308                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off,
1309                                      mask, val);
1310                 }
1311         } else {
1312                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1313                     m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1314                 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1315                     v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1316                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1317         }
1318         return 0;
1319 }
1320
1321 static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1322 {
1323         struct lcdc_device *lcdc_dev =
1324             container_of(dev_drv, struct lcdc_device, driver);
1325         struct rk_lcdc_win *win = dev_drv->win[win_id];
1326         unsigned int mask, val, hwc_size = 0;
1327
1328         if (win->state == 1) {
1329                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1330                 mask = m_HWC_EN | m_HWC_DATA_FMT |
1331                     m_HWC_RB_SWAP | m_WIN0_CSC_MODE;
1332                 val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1333                     v_HWC_RB_SWAP(win->area[0].swap_rb) |
1334                     v_WIN0_CSC_MODE(win->csc_mode);
1335                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1336
1337                 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1338                         hwc_size = 0;
1339                 else if ((win->area[0].xsize == 64) &&
1340                          (win->area[0].ysize == 64))
1341                         hwc_size = 1;
1342                 else if ((win->area[0].xsize == 96) &&
1343                          (win->area[0].ysize == 96))
1344                         hwc_size = 2;
1345                 else if ((win->area[0].xsize == 128) &&
1346                          (win->area[0].ysize == 128))
1347                         hwc_size = 3;
1348                 else
1349                         dev_err(lcdc_dev->dev, "un supported hwc size!\n");
1350
1351                 mask = m_HWC_SIZE;
1352                 val = v_HWC_SIZE(hwc_size);
1353                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1354
1355                 mask = m_HWC_DSP_XST | m_HWC_DSP_YST;
1356                 val = v_HWC_DSP_XST(win->area[0].dsp_stx) |
1357                     v_HWC_DSP_YST(win->area[0].dsp_sty);
1358                 lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val);
1359
1360                 if (win->alpha_en == 1) {
1361                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1362                 } else {
1363                         mask = m_WIN2_SRC_ALPHA_EN;
1364                         val = v_WIN2_SRC_ALPHA_EN(0);
1365                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val);
1366                 }
1367         } else {
1368                 mask = m_HWC_EN;
1369                 val = v_HWC_EN(win->state);
1370                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1371         }
1372         return 0;
1373 }
1374
1375 static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
1376                                          struct rk_lcdc_win *win)
1377 {
1378         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1379         int timeout;
1380         unsigned long flags;
1381
1382         spin_lock(&lcdc_dev->reg_lock);
1383         if (likely(lcdc_dev->clk_on)) {
1384                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1385                              v_STANDBY_EN(lcdc_dev->standby));
1386                 if ((win->id == 0) || (win->id == 1))
1387                         rk3368_win_0_1_reg_update(dev_drv, win->id);
1388                 else if ((win->id == 2) || (win->id == 3))
1389                         rk3368_win_2_3_reg_update(dev_drv, win->id);
1390                 else if (win->id == 4)
1391                         rk3368_hwc_reg_update(dev_drv, win->id);
1392                 /*rk3368_lcdc_post_cfg(dev_drv); */
1393                 lcdc_cfg_done(lcdc_dev);
1394         }
1395         spin_unlock(&lcdc_dev->reg_lock);
1396
1397         /*if (dev_drv->wait_fs) { */
1398         if (0) {
1399                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1400                 init_completion(&dev_drv->frame_done);
1401                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1402                 timeout =
1403                     wait_for_completion_timeout(&dev_drv->frame_done,
1404                                                 msecs_to_jiffies
1405                                                 (dev_drv->cur_screen->ft + 5));
1406                 if (!timeout && (!dev_drv->frame_done.done)) {
1407                         dev_warn(lcdc_dev->dev,
1408                                  "wait for new frame start time out!\n");
1409                         return -ETIMEDOUT;
1410                 }
1411         }
1412         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1413         return 0;
1414 }
1415
1416 static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1417 {
1418         memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x270);
1419         return 0;
1420 }
1421
1422 static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1423 {
1424         u32 mask, val;
1425         struct lcdc_device *lcdc_dev =
1426             container_of(dev_drv, struct lcdc_device, driver);
1427
1428 #if defined(CONFIG_ROCKCHIP_IOMMU)
1429         if (dev_drv->iommu_enabled) {
1430                 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1431                         if (likely(lcdc_dev->clk_on)) {
1432                                 mask = m_MMU_EN;
1433                                 val = v_MMU_EN(1);
1434                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1435                                 mask = m_AXI_MAX_OUTSTANDING_EN |
1436                                         m_AXI_OUTSTANDING_MAX_NUM;
1437                                 val = v_AXI_OUTSTANDING_MAX_NUM(31) |
1438                                         v_AXI_MAX_OUTSTANDING_EN(1);
1439                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1440                         }
1441                         lcdc_dev->iommu_status = 1;
1442                         rockchip_iovmm_activate(dev_drv->dev);
1443                 }
1444         }
1445 #endif
1446         return 0;
1447 }
1448
1449 static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
1450 {
1451         int ret = 0, fps = 0;
1452         struct lcdc_device *lcdc_dev =
1453             container_of(dev_drv, struct lcdc_device, driver);
1454         struct rk_screen *screen = dev_drv->cur_screen;
1455 #ifdef CONFIG_RK_FPGA
1456         return 0;
1457 #endif
1458
1459         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1460         if (ret)
1461                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1462         lcdc_dev->pixclock =
1463             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1464         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1465
1466         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1467         screen->ft = 1000 / fps;
1468         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1469                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1470         return 0;
1471 }
1472
1473 static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv)
1474 {
1475         struct lcdc_device *lcdc_dev =
1476             container_of(dev_drv, struct lcdc_device, driver);
1477         struct rk_screen *screen = dev_drv->cur_screen;
1478         u16 hsync_len = screen->mode.hsync_len;
1479         u16 left_margin = screen->mode.left_margin;
1480         u16 right_margin = screen->mode.right_margin;
1481         u16 vsync_len = screen->mode.vsync_len;
1482         u16 upper_margin = screen->mode.upper_margin;
1483         u16 lower_margin = screen->mode.lower_margin;
1484         u16 x_res = screen->mode.xres;
1485         u16 y_res = screen->mode.yres;
1486         u32 mask, val;
1487         u16 h_total, v_total;
1488         u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1489
1490         h_total = hsync_len + left_margin + x_res + right_margin;
1491         v_total = vsync_len + upper_margin + y_res + lower_margin;
1492
1493         screen->post_dsp_stx = x_res * (100 - screen->overscan.left) / 200;
1494         screen->post_dsp_sty = y_res * (100 - screen->overscan.top) / 200;
1495         screen->post_xsize = x_res *
1496             (screen->overscan.left + screen->overscan.right) / 200;
1497         screen->post_ysize = y_res *
1498             (screen->overscan.top + screen->overscan.bottom) / 200;
1499
1500         mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1501         val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1502         lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1503
1504         mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1505         val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1506             v_DSP_HACT_ST(hsync_len + left_margin);
1507         lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1508
1509         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1510                 /* First Field Timing */
1511                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1512                 val = v_DSP_VS_PW(vsync_len) |
1513                     v_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1514                                       lower_margin) + y_res + 1);
1515                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1516
1517                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1518                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1519                     v_DSP_VACT_ST(vsync_len + upper_margin);
1520                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1521
1522                 /* Second Field Timing */
1523                 mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1;
1524                 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1525                 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1526                     lower_margin;
1527                 val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1);
1528                 lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val);
1529
1530                 mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1;
1531                 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1532                     lower_margin + 1;
1533                 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1534                     lower_margin + 1;
1535                 val =
1536                     v_DSP_VACT_END_F1(vact_end_f1) |
1537                     v_DSP_VAC_ST_F1(vact_st_f1);
1538                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val);
1539
1540                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1541                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1542                              v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0));
1543                 mask =
1544                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1545                     m_WIN0_CBR_DEFLICK;
1546                 val =
1547                     v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(1) |
1548                     v_WIN0_CBR_DEFLICK(1);
1549                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1550
1551                 mask =
1552                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1553                     m_WIN1_CBR_DEFLICK;
1554                 val =
1555                     v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(1) |
1556                     v_WIN1_CBR_DEFLICK(1);
1557                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1558
1559                 mask = m_WIN2_INTERLACE_READ;
1560                 val = v_WIN2_INTERLACE_READ(1);
1561                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1562
1563                 mask = m_WIN3_INTERLACE_READ;
1564                 val = v_WIN3_INTERLACE_READ(1);
1565                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1566
1567                 mask = m_HWC_INTERLACE_READ;
1568                 val = v_HWC_INTERLACE_READ(1);
1569                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1570
1571                 mask = m_DSP_LINE_FLAG0_NUM;
1572                 val =
1573                     v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res / 2);
1574                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1575         } else {
1576                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1577                 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1578                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1579
1580                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1581                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1582                     v_DSP_VACT_ST(vsync_len + upper_margin);
1583                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1584
1585                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1586                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1587                              v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0));
1588
1589                 mask =
1590                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1591                     m_WIN0_CBR_DEFLICK;
1592                 val =
1593                     v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) |
1594                     v_WIN0_CBR_DEFLICK(0);
1595                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1596
1597                 mask =
1598                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1599                     m_WIN1_CBR_DEFLICK;
1600                 val =
1601                     v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) |
1602                     v_WIN1_CBR_DEFLICK(0);
1603                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1604
1605                 mask = m_WIN2_INTERLACE_READ;
1606                 val = v_WIN2_INTERLACE_READ(0);
1607                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1608
1609                 mask = m_WIN3_INTERLACE_READ;
1610                 val = v_WIN3_INTERLACE_READ(0);
1611                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1612
1613                 mask = m_HWC_INTERLACE_READ;
1614                 val = v_HWC_INTERLACE_READ(0);
1615                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1616
1617                 mask = m_DSP_LINE_FLAG0_NUM;
1618                 val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res);
1619                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1620         }
1621         rk3368_lcdc_post_cfg(dev_drv);
1622         return 0;
1623 }
1624
1625 static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1626 {
1627         struct lcdc_device *lcdc_dev =
1628             container_of(dev_drv, struct lcdc_device, driver);
1629         u32 bcsh_ctrl;
1630
1631         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_OVERLAY_MODE,
1632                      v_OVERLAY_MODE(dev_drv->overlay_mode));
1633         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1634                 if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1635                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1636                                      m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1637                                      v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1638                 else            /* YUV2RGB */
1639                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1640                                      m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1641                                      m_BCSH_R2Y_EN,
1642                                      v_BCSH_Y2R_EN(1) |
1643                                      v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1644                                      v_BCSH_R2Y_EN(0));
1645         } else {                /* overlay_mode=VOP_RGB_DOMAIN */
1646                 /* bypass  --need check,if bcsh close? */
1647                 if (dev_drv->output_color == COLOR_RGB) {
1648                         bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1649                         if (((bcsh_ctrl & m_BCSH_EN) == 1) ||
1650                             (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1651                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1652                                              m_BCSH_R2Y_EN |
1653                                              m_BCSH_Y2R_EN,
1654                                              v_BCSH_R2Y_EN(1) |
1655                                              v_BCSH_Y2R_EN(1));
1656                         else
1657                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1658                                              m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1659                                              v_BCSH_R2Y_EN(0) |
1660                                              v_BCSH_Y2R_EN(0));
1661                 } else          /* RGB2YUV */
1662                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1663                                      m_BCSH_R2Y_EN |
1664                                      m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1665                                      v_BCSH_R2Y_EN(1) |
1666                                      v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1667                                      v_BCSH_Y2R_EN(0));
1668         }
1669 }
1670
1671 static int rk3368_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1672                                   u16 *yact, int *format, u32 *dsp_addr)
1673 {
1674         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1675                                                     struct lcdc_device, driver);
1676         u32 val;
1677
1678         spin_lock(&lcdc_dev->reg_lock);
1679
1680         val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1681         *xact = (val & m_WIN0_ACT_WIDTH) + 1;
1682         *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1;
1683
1684         val = lcdc_readl(lcdc_dev, WIN0_CTRL0);
1685         *format = (val & m_WIN0_DATA_FMT) >> 1;
1686         *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1687
1688         spin_unlock(&lcdc_dev->reg_lock);
1689
1690         return 0;
1691 }
1692
1693 static int rk3368_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1694                               int format, u16 xact, u16 yact, u16 xvir)
1695 {
1696         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1697                                                     struct lcdc_device, driver);
1698         u32 val, mask;
1699         int swap = (format == RGB888) ? 1 : 0;
1700
1701         mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP;
1702         val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap);
1703         lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1704
1705         lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE,
1706                         v_WIN0_VIR_STRIDE(xvir));
1707         lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) |
1708                     v_WIN0_ACT_HEIGHT(yact));
1709
1710         lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1711
1712         lcdc_cfg_done(lcdc_dev);
1713
1714         return 0;
1715 }
1716
1717
1718 static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1719 {
1720         u16 face = 0;
1721         u16 dclk_ddr = 0;
1722         u32 v = 0;
1723         struct lcdc_device *lcdc_dev =
1724             container_of(dev_drv, struct lcdc_device, driver);
1725         struct rk_screen *screen = dev_drv->cur_screen;
1726         u32 mask, val;
1727
1728         spin_lock(&lcdc_dev->reg_lock);
1729         if (likely(lcdc_dev->clk_on)) {
1730                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1731                 if (!lcdc_dev->standby && !initscreen) {
1732                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1733                                      v_STANDBY_EN(1));
1734                         lcdc_cfg_done(lcdc_dev);
1735                         mdelay(50);
1736                 }
1737                 switch (screen->face) {
1738                 case OUT_P565:
1739                         face = OUT_P565;
1740                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1741                             m_DITHER_DOWN_SEL;
1742                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1743                             v_DITHER_DOWN_SEL(1);
1744                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1745                         break;
1746                 case OUT_P666:
1747                         face = OUT_P666;
1748                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1749                             m_DITHER_DOWN_SEL;
1750                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1751                             v_DITHER_DOWN_SEL(1);
1752                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1753                         break;
1754                 case OUT_D888_P565:
1755                         face = OUT_P888;
1756                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1757                             m_DITHER_DOWN_SEL;
1758                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1759                             v_DITHER_DOWN_SEL(1);
1760                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1761                         break;
1762                 case OUT_D888_P666:
1763                         face = OUT_P888;
1764                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1765                             m_DITHER_DOWN_SEL;
1766                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1767                             v_DITHER_DOWN_SEL(1);
1768                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1769                         break;
1770                 case OUT_P888:
1771                         face = OUT_P888;
1772                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1773                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1774                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1775                         break;
1776                 case OUT_YUV_420:
1777                         /*yuv420 output prefer yuv domain overlay */
1778                         face = OUT_YUV_420;
1779                         dclk_ddr = 1;
1780                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1781                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1782                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1783                         break;
1784                 default:
1785                         dev_err(lcdc_dev->dev, "un supported interface!\n");
1786                         break;
1787                 }
1788                 switch (screen->type) {
1789                 case SCREEN_RGB:
1790                         mask = m_RGB_OUT_EN;
1791                         val = v_RGB_OUT_EN(1);
1792                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1793                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1794                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1795                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1796                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1797                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1798                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1799                         v = 1 << 15 | (1 << (15 + 16));
1800
1801                         break;
1802                 case SCREEN_LVDS:
1803                         mask = m_RGB_OUT_EN;
1804                         val = v_RGB_OUT_EN(1);
1805                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1806                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1807                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1808                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1809                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1810                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1811                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1812                         v = 0 << 15 | (1 << (15 + 16));
1813                         break;
1814                 case SCREEN_HDMI:
1815                         /*face = OUT_RGB_AAA;*/
1816                         dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1817                         mask = m_HDMI_OUT_EN  | m_RGB_OUT_EN;
1818                         val = v_HDMI_OUT_EN(1) | v_RGB_OUT_EN(0);
1819                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1820                         mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
1821                             m_HDMI_DEN_POL | m_HDMI_DCLK_POL;
1822                         val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
1823                             v_HDMI_VSYNC_POL(screen->pin_vsync) |
1824                             v_HDMI_DEN_POL(screen->pin_den) |
1825                             v_HDMI_DCLK_POL(screen->pin_dclk);
1826                         break;
1827                 case SCREEN_MIPI:
1828                         mask = m_MIPI_OUT_EN  | m_RGB_OUT_EN;
1829                         val = v_MIPI_OUT_EN(1) | v_RGB_OUT_EN(0);
1830                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1831                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1832                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1833                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1834                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1835                             v_MIPI_DEN_POL(screen->pin_den) |
1836                             v_MIPI_DCLK_POL(screen->pin_dclk);
1837                         break;
1838                 case SCREEN_DUAL_MIPI:
1839                         mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN  |
1840                                 m_RGB_OUT_EN;
1841                         val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1) |
1842                                 v_RGB_OUT_EN(0);
1843                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1844                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1845                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1846                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1847                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1848                             v_MIPI_DEN_POL(screen->pin_den) |
1849                             v_MIPI_DCLK_POL(screen->pin_dclk);
1850                         break;
1851                 case SCREEN_EDP:
1852                         face = OUT_P888;        /*RGB 888 output */
1853
1854                         mask = m_EDP_OUT_EN | m_RGB_OUT_EN;
1855                         val = v_EDP_OUT_EN(1) | v_RGB_OUT_EN(0);
1856                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1857                         /*because edp have to sent aaa fmt */
1858                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1859                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1860
1861                         mask |= m_EDP_HSYNC_POL | m_EDP_VSYNC_POL |
1862                             m_EDP_DEN_POL | m_EDP_DCLK_POL;
1863                         val |= v_EDP_HSYNC_POL(screen->pin_hsync) |
1864                             v_EDP_VSYNC_POL(screen->pin_vsync) |
1865                             v_EDP_DEN_POL(screen->pin_den) |
1866                             v_EDP_DCLK_POL(screen->pin_dclk);
1867                         break;
1868                 }
1869                 /*hsync vsync den dclk polo,dither */
1870                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1871 #ifndef CONFIG_RK_FPGA
1872                 /*writel_relaxed(v, RK_GRF_VIRT + rk3368_GRF_SOC_CON7);
1873                 move to  lvds driver*/
1874                 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
1875 #endif
1876                 mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP |
1877                     m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1878                     m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1879                     m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
1880                 val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) |
1881                     v_DSP_BG_SWAP(screen->swap_gb) |
1882                     v_DSP_RB_SWAP(screen->swap_rb) |
1883                     v_DSP_RG_SWAP(screen->swap_rg) |
1884                     v_DSP_DELTA_SWAP(screen->swap_delta) |
1885                     v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1886                     v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1887                     v_DSP_X_MIR_EN(screen->x_mirror) |
1888                     v_DSP_Y_MIR_EN(screen->y_mirror);
1889                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1890                 /*BG color */
1891                 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1892                 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN)
1893                         val = v_DSP_BG_BLUE(0x80) | v_DSP_BG_GREEN(0x10) |
1894                                 v_DSP_BG_RED(0x80);
1895                 else
1896                         val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) |
1897                                 v_DSP_BG_RED(0);
1898                 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1899                 dev_drv->output_color = screen->color_mode;
1900                 if (screen->dsp_lut == NULL)
1901                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
1902                                      v_DSP_LUT_EN(0));
1903                 else
1904                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
1905                                      v_DSP_LUT_EN(1));
1906                 if (screen->cabc_lut == NULL) {
1907                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0, m_CABC_EN,
1908                                      v_CABC_EN(0));
1909                 } else {
1910                         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
1911                                      v_CABC_LUT_EN(1));
1912                 }
1913                 rk3368_lcdc_bcsh_path_sel(dev_drv);
1914                 rk3368_config_timing(dev_drv);
1915         }
1916         spin_unlock(&lcdc_dev->reg_lock);
1917         rk3368_lcdc_set_dclk(dev_drv);
1918         if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1919             dev_drv->trsm_ops->enable)
1920                 dev_drv->trsm_ops->enable();
1921         if (screen->init)
1922                 screen->init();
1923         if (!lcdc_dev->standby)
1924                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
1925         return 0;
1926 }
1927
1928
1929 /*enable layer,open:1,enable;0 disable*/
1930 static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev,
1931                                      unsigned int win_id, bool open)
1932 {
1933         spin_lock(&lcdc_dev->reg_lock);
1934         if (likely(lcdc_dev->clk_on) &&
1935             lcdc_dev->driver.win[win_id]->state != open) {
1936                 if (open) {
1937                         if (!lcdc_dev->atv_layer_cnt) {
1938                                 dev_info(lcdc_dev->dev,
1939                                          "wakeup from standby!\n");
1940                                 lcdc_dev->standby = 0;
1941                         }
1942                         lcdc_dev->atv_layer_cnt |= (1 << win_id);
1943                 } else {
1944                         if (lcdc_dev->atv_layer_cnt & (1 << win_id))
1945                                 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
1946                 }
1947                 lcdc_dev->driver.win[win_id]->state = open;
1948                 if (!open) {
1949                         /*rk3368_lcdc_reg_update(dev_drv);*/
1950                         rk3368_lcdc_layer_update_regs
1951                         (lcdc_dev, lcdc_dev->driver.win[win_id]);
1952                         lcdc_cfg_done(lcdc_dev);
1953                 }
1954                 /*if no layer used,disable lcdc */
1955                 if (!lcdc_dev->atv_layer_cnt) {
1956                         dev_info(lcdc_dev->dev,
1957                                  "no layer is used,go to standby!\n");
1958                         lcdc_dev->standby = 1;
1959                 }
1960         }
1961         spin_unlock(&lcdc_dev->reg_lock);
1962 }
1963
1964 static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1965 {
1966         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1967                                                     struct lcdc_device, driver);
1968         u32 mask, val;
1969         /*struct rk_screen *screen = dev_drv->cur_screen; */
1970
1971         mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
1972             m_LINE_FLAG1_INTR_CLR;
1973         val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
1974             v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1);
1975         lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
1976
1977         mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN | m_BUS_ERROR_INTR_EN;
1978         val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) |
1979             v_BUS_ERROR_INTR_EN(1);
1980         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1981
1982 #ifdef LCDC_IRQ_EMPTY_DEBUG
1983         mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
1984             m_WIN2_EMPTY_INTR_EN |
1985             m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN |
1986             m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN;
1987         val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) |
1988             v_WIN2_EMPTY_INTR_EN(1) |
1989             v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) |
1990             v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1);
1991         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1992 #endif
1993         return 0;
1994 }
1995
1996 static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1997                             bool open)
1998 {
1999         struct lcdc_device *lcdc_dev =
2000             container_of(dev_drv, struct lcdc_device, driver);
2001 #if 0/*ndef CONFIG_RK_FPGA*/
2002         int sys_status =
2003             (dev_drv->id == 0) ? SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
2004 #endif
2005         /*enable clk,when first layer open */
2006         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
2007                 /*rockchip_set_system_status(sys_status);*/
2008                 rk3368_lcdc_pre_init(dev_drv);
2009                 rk3368_lcdc_clk_enable(lcdc_dev);
2010 #if defined(CONFIG_ROCKCHIP_IOMMU)
2011                 if (dev_drv->iommu_enabled) {
2012                         if (!dev_drv->mmu_dev) {
2013                                 dev_drv->mmu_dev =
2014                                     rk_fb_get_sysmmu_device_by_compatible
2015                                     (dev_drv->mmu_dts_name);
2016                                 if (dev_drv->mmu_dev) {
2017                                         rk_fb_platform_set_sysmmu
2018                                             (dev_drv->mmu_dev, dev_drv->dev);
2019                                 } else {
2020                                         dev_err(dev_drv->dev,
2021                                                 "fail get rk iommu device\n");
2022                                         return -1;
2023                                 }
2024                         }
2025                         /*if (dev_drv->mmu_dev)
2026                            rockchip_iovmm_activate(dev_drv->dev); */
2027                 }
2028 #endif
2029                 rk3368_lcdc_reg_restore(lcdc_dev);
2030                 /*if (dev_drv->iommu_enabled)
2031                    rk3368_lcdc_mmu_en(dev_drv); */
2032                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
2033                         /*rk3368_lcdc_set_dclk(dev_drv); */
2034                         rk3368_lcdc_enable_irq(dev_drv);
2035                 } else {
2036                         rk3368_load_screen(dev_drv, 1);
2037                 }
2038                 if (dev_drv->bcsh.enable)
2039                         rk3368_lcdc_set_bcsh(dev_drv, 1);
2040                 spin_lock(&lcdc_dev->reg_lock);
2041                 if (dev_drv->cur_screen->dsp_lut)
2042                         rk3368_lcdc_set_lut(dev_drv,
2043                                             dev_drv->cur_screen->dsp_lut);
2044                 if (dev_drv->cur_screen->cabc_lut)
2045                         rk3368_set_cabc_lut(dev_drv,
2046                                             dev_drv->cur_screen->cabc_lut);
2047                 spin_unlock(&lcdc_dev->reg_lock);
2048         }
2049
2050         if (win_id < ARRAY_SIZE(lcdc_win))
2051                 rk3368_lcdc_layer_enable(lcdc_dev, win_id, open);
2052         else
2053                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
2054
2055
2056         /* when all layer closed,disable clk */
2057         /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
2058            rk3368_lcdc_disable_irq(lcdc_dev);
2059            rk3368_lcdc_reg_update(dev_drv);
2060            #if defined(CONFIG_ROCKCHIP_IOMMU)
2061            if (dev_drv->iommu_enabled) {
2062            if (dev_drv->mmu_dev)
2063            rockchip_iovmm_deactivate(dev_drv->dev);
2064            }
2065            #endif
2066            rk3368_lcdc_clk_disable(lcdc_dev);
2067            #ifndef CONFIG_RK_FPGA
2068            rockchip_clear_system_status(sys_status);
2069            #endif
2070            } */
2071
2072         return 0;
2073 }
2074
2075 static int win_0_1_display(struct lcdc_device *lcdc_dev,
2076                            struct rk_lcdc_win *win)
2077 {
2078         u32 y_addr;
2079         u32 uv_addr;
2080         unsigned int off;
2081
2082         off = win->id * 0x40;
2083         /*win->smem_start + win->y_offset; */
2084         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2085         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
2086         DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
2087             lcdc_dev->id, win->id, y_addr, uv_addr);
2088         DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
2089             win->area[0].y_offset, win->area[0].c_offset);
2090         spin_lock(&lcdc_dev->reg_lock);
2091         if (likely(lcdc_dev->clk_on)) {
2092                 win->area[0].y_addr = y_addr;
2093                 win->area[0].uv_addr = uv_addr;
2094                 lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
2095                 lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
2096                 /*lcdc_cfg_done(lcdc_dev); */
2097         }
2098         spin_unlock(&lcdc_dev->reg_lock);
2099
2100         return 0;
2101 }
2102
2103 static int win_2_3_display(struct lcdc_device *lcdc_dev,
2104                            struct rk_lcdc_win *win)
2105 {
2106         u32 i, y_addr;
2107         unsigned int off;
2108
2109         off = (win->id - 2) * 0x50;
2110         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2111         DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id);
2112
2113         spin_lock(&lcdc_dev->reg_lock);
2114         if (likely(lcdc_dev->clk_on)) {
2115                 for (i = 0; i < win->area_num; i++) {
2116                         DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2117                             i, win->area[i].y_addr, win->area[i].y_offset);
2118                         win->area[i].y_addr =
2119                             win->area[i].smem_start + win->area[i].y_offset;
2120                         }
2121                 lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr);
2122                 lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr);
2123                 lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr);
2124                 lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr);
2125         }
2126         spin_unlock(&lcdc_dev->reg_lock);
2127         return 0;
2128 }
2129
2130 static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win)
2131 {
2132         u32 y_addr;
2133
2134         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2135         DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2136             lcdc_dev->id, __func__, y_addr);
2137         spin_lock(&lcdc_dev->reg_lock);
2138         if (likely(lcdc_dev->clk_on)) {
2139                 win->area[0].y_addr = y_addr;
2140                 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
2141         }
2142         spin_unlock(&lcdc_dev->reg_lock);
2143
2144         return 0;
2145 }
2146
2147 static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2148 {
2149         struct lcdc_device *lcdc_dev =
2150             container_of(dev_drv, struct lcdc_device, driver);
2151         struct rk_lcdc_win *win = NULL;
2152         struct rk_screen *screen = dev_drv->cur_screen;
2153
2154 #if defined(WAIT_FOR_SYNC)
2155         int timeout;
2156         unsigned long flags;
2157 #endif
2158         win = dev_drv->win[win_id];
2159         if (!screen) {
2160                 dev_err(dev_drv->dev, "screen is null!\n");
2161                 return -ENOENT;
2162         }
2163         if (win_id == 0) {
2164                 win_0_1_display(lcdc_dev, win);
2165         } else if (win_id == 1) {
2166                 win_0_1_display(lcdc_dev, win);
2167         } else if (win_id == 2) {
2168                 win_2_3_display(lcdc_dev, win);
2169         } else if (win_id == 3) {
2170                 win_2_3_display(lcdc_dev, win);
2171         } else if (win_id == 4) {
2172                 hwc_display(lcdc_dev, win);
2173         } else {
2174                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2175                 return -EINVAL;
2176         }
2177
2178         /*this is the first frame of the system ,enable frame start interrupt */
2179         if ((dev_drv->first_frame)) {
2180                 dev_drv->first_frame = 0;
2181                 rk3368_lcdc_enable_irq(dev_drv);
2182         }
2183 #if defined(WAIT_FOR_SYNC)
2184         spin_lock_irqsave(&dev_drv->cpl_lock, flags);
2185         init_completion(&dev_drv->frame_done);
2186         spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
2187         timeout =
2188             wait_for_completion_timeout(&dev_drv->frame_done,
2189                                         msecs_to_jiffies(dev_drv->
2190                                                          cur_screen->ft + 5));
2191         if (!timeout && (!dev_drv->frame_done.done)) {
2192                 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
2193                 return -ETIMEDOUT;
2194         }
2195 #endif
2196         return 0;
2197 }
2198
2199 static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
2200 {
2201         u16 srcW;
2202         u16 srcH;
2203         u16 dstW;
2204         u16 dstH;
2205         u16 yrgb_srcW;
2206         u16 yrgb_srcH;
2207         u16 yrgb_dstW;
2208         u16 yrgb_dstH;
2209         u32 yrgb_vscalednmult;
2210         u32 yrgb_xscl_factor;
2211         u32 yrgb_yscl_factor;
2212         u8 yrgb_vsd_bil_gt2 = 0;
2213         u8 yrgb_vsd_bil_gt4 = 0;
2214
2215         u16 cbcr_srcW;
2216         u16 cbcr_srcH;
2217         u16 cbcr_dstW;
2218         u16 cbcr_dstH;
2219         u32 cbcr_vscalednmult;
2220         u32 cbcr_xscl_factor;
2221         u32 cbcr_yscl_factor;
2222         u8 cbcr_vsd_bil_gt2 = 0;
2223         u8 cbcr_vsd_bil_gt4 = 0;
2224         u8 yuv_fmt = 0;
2225
2226         srcW = win->area[0].xact;
2227         srcH = win->area[0].yact;
2228         dstW = win->area[0].xsize;
2229         dstH = win->area[0].ysize;
2230
2231         /*yrgb scl mode */
2232         yrgb_srcW = srcW;
2233         yrgb_srcH = srcH;
2234         yrgb_dstW = dstW;
2235         yrgb_dstH = dstH;
2236         if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2237                 pr_err("ERROR: yrgb scale exceed 8,");
2238                 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2239                        yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2240         }
2241         if (yrgb_srcW < yrgb_dstW)
2242                 win->yrgb_hor_scl_mode = SCALE_UP;
2243         else if (yrgb_srcW > yrgb_dstW)
2244                 win->yrgb_hor_scl_mode = SCALE_DOWN;
2245         else
2246                 win->yrgb_hor_scl_mode = SCALE_NONE;
2247
2248         if (yrgb_srcH < yrgb_dstH)
2249                 win->yrgb_ver_scl_mode = SCALE_UP;
2250         else if (yrgb_srcH > yrgb_dstH)
2251                 win->yrgb_ver_scl_mode = SCALE_DOWN;
2252         else
2253                 win->yrgb_ver_scl_mode = SCALE_NONE;
2254
2255         /*cbcr scl mode */
2256         switch (win->area[0].format) {
2257         case YUV422:
2258         case YUV422_A:
2259                 cbcr_srcW = srcW / 2;
2260                 cbcr_dstW = dstW;
2261                 cbcr_srcH = srcH;
2262                 cbcr_dstH = dstH;
2263                 yuv_fmt = 1;
2264                 break;
2265         case YUV420:
2266         case YUV420_A:
2267                 cbcr_srcW = srcW / 2;
2268                 cbcr_dstW = dstW;
2269                 cbcr_srcH = srcH / 2;
2270                 cbcr_dstH = dstH;
2271                 yuv_fmt = 1;
2272                 break;
2273         case YUV444:
2274         case YUV444_A:
2275                 cbcr_srcW = srcW;
2276                 cbcr_dstW = dstW;
2277                 cbcr_srcH = srcH;
2278                 cbcr_dstH = dstH;
2279                 yuv_fmt = 1;
2280                 break;
2281         default:
2282                 cbcr_srcW = 0;
2283                 cbcr_dstW = 0;
2284                 cbcr_srcH = 0;
2285                 cbcr_dstH = 0;
2286                 yuv_fmt = 0;
2287                 break;
2288         }
2289         if (yuv_fmt) {
2290                 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2291                     (cbcr_dstH * 8 <= cbcr_srcH)) {
2292                         pr_err("ERROR: cbcr scale exceed 8,");
2293                         pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2294                                cbcr_srcH, cbcr_dstW, cbcr_dstH);
2295                 }
2296         }
2297
2298         if (cbcr_srcW < cbcr_dstW)
2299                 win->cbr_hor_scl_mode = SCALE_UP;
2300         else if (cbcr_srcW > cbcr_dstW)
2301                 win->cbr_hor_scl_mode = SCALE_DOWN;
2302         else
2303                 win->cbr_hor_scl_mode = SCALE_NONE;
2304
2305         if (cbcr_srcH < cbcr_dstH)
2306                 win->cbr_ver_scl_mode = SCALE_UP;
2307         else if (cbcr_srcH > cbcr_dstH)
2308                 win->cbr_ver_scl_mode = SCALE_DOWN;
2309         else
2310                 win->cbr_ver_scl_mode = SCALE_NONE;
2311
2312         /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
2313             "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
2314             "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW,
2315             srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH,
2316             win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW,
2317             cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode,
2318             win->cbr_ver_scl_mode);*/
2319
2320         /*line buffer mode */
2321         if ((win->area[0].format == YUV422) ||
2322             (win->area[0].format == YUV420) ||
2323             (win->area[0].format == YUV422_A) ||
2324             (win->area[0].format == YUV420_A)) {
2325                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2326                         if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2327                             (cbcr_dstW == 0))
2328                                 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2329                                        cbcr_dstW);
2330                         else if (cbcr_dstW > 1280)
2331                                 win->win_lb_mode = LB_YUV_3840X5;
2332                         else
2333                                 win->win_lb_mode = LB_YUV_2560X8;
2334                 } else {        /*SCALE_UP or SCALE_NONE */
2335                         if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2336                             (cbcr_srcW == 0))
2337                                 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2338                                        cbcr_srcW);
2339                         else if (cbcr_srcW > 1280)
2340                                 win->win_lb_mode = LB_YUV_3840X5;
2341                         else
2342                                 win->win_lb_mode = LB_YUV_2560X8;
2343                 }
2344         } else {
2345                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2346                         if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2347                             (yrgb_dstW == 0))
2348                                 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2349                         else if (yrgb_dstW > 2560)
2350                                 win->win_lb_mode = LB_RGB_3840X2;
2351                         else if (yrgb_dstW > 1920)
2352                                 win->win_lb_mode = LB_RGB_2560X4;
2353                         else if (yrgb_dstW > 1280)
2354                                 win->win_lb_mode = LB_RGB_1920X5;
2355                         else
2356                                 win->win_lb_mode = LB_RGB_1280X8;
2357                 } else {        /*SCALE_UP or SCALE_NONE */
2358                         if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2359                             (yrgb_srcW == 0))
2360                                 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2361                         else if (yrgb_srcW > 2560)
2362                                 win->win_lb_mode = LB_RGB_3840X2;
2363                         else if (yrgb_srcW > 1920)
2364                                 win->win_lb_mode = LB_RGB_2560X4;
2365                         else if (yrgb_srcW > 1280)
2366                                 win->win_lb_mode = LB_RGB_1920X5;
2367                         else
2368                                 win->win_lb_mode = LB_RGB_1280X8;
2369                 }
2370         }
2371         DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2372
2373         /*vsd/vsu scale ALGORITHM */
2374         win->yrgb_hsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2375         win->cbr_hsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2376         win->yrgb_vsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2377         win->cbr_vsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2378         switch (win->win_lb_mode) {
2379         case LB_YUV_3840X5:
2380         case LB_YUV_2560X8:
2381         case LB_RGB_1920X5:
2382         case LB_RGB_1280X8:
2383                 win->yrgb_vsu_mode = SCALE_UP_BIC;
2384                 win->cbr_vsu_mode = SCALE_UP_BIC;
2385                 break;
2386         case LB_RGB_3840X2:
2387                 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2388                         pr_err("ERROR : not allow yrgb ver scale\n");
2389                 if (win->cbr_ver_scl_mode != SCALE_NONE)
2390                         pr_err("ERROR : not allow cbcr ver scale\n");
2391                 break;
2392         case LB_RGB_2560X4:
2393                 win->yrgb_vsu_mode = SCALE_UP_BIL;
2394                 win->cbr_vsu_mode = SCALE_UP_BIL;
2395                 break;
2396         default:
2397                 pr_info("%s:un supported win_lb_mode:%d\n",
2398                         __func__, win->win_lb_mode);
2399                 break;
2400         }
2401         if (win->mirror_en == 1) {      /*interlace mode must bill */
2402                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2403         }
2404
2405         if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2406             (win->area[0].fbdc_en == 1)) {
2407                 /*in this pattern,use bil mode,not support souble scd,
2408                 use avg mode, support double scd, but aclk should be
2409                 bigger than dclk,aclk>>dclk */
2410                 if (yrgb_srcH >= 2 * yrgb_dstH) {
2411                         pr_err("ERROR : fbdc mode,not support y scale down:");
2412                         pr_err("srcH[%d] > 2 *dstH[%d]\n",
2413                                yrgb_srcH, yrgb_dstH);
2414                 }
2415         }
2416         DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2417             win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2418             win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2419
2420         /*SCALE FACTOR */
2421
2422         /*(1.1)YRGB HOR SCALE FACTOR */
2423         switch (win->yrgb_hor_scl_mode) {
2424         case SCALE_NONE:
2425                 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2426                 break;
2427         case SCALE_UP:
2428                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2429                 break;
2430         case SCALE_DOWN:
2431                 switch (win->yrgb_hsd_mode) {
2432                 case SCALE_DOWN_BIL:
2433                         yrgb_xscl_factor =
2434                             GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2435                         break;
2436                 case SCALE_DOWN_AVG:
2437                         yrgb_xscl_factor =
2438                             GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2439                         break;
2440                 default:
2441                         pr_info(
2442                                 "%s:un supported yrgb_hsd_mode:%d\n", __func__,
2443                                win->yrgb_hsd_mode);
2444                         break;
2445                 }
2446                 break;
2447         default:
2448                 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2449                         __func__, win->yrgb_hor_scl_mode);
2450                 break;
2451         }                       /*win->yrgb_hor_scl_mode */
2452
2453         /*(1.2)YRGB VER SCALE FACTOR */
2454         switch (win->yrgb_ver_scl_mode) {
2455         case SCALE_NONE:
2456                 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2457                 break;
2458         case SCALE_UP:
2459                 switch (win->yrgb_vsu_mode) {
2460                 case SCALE_UP_BIL:
2461                         yrgb_yscl_factor =
2462                             GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2463                         break;
2464                 case SCALE_UP_BIC:
2465                         if (yrgb_srcH < 3) {
2466                                 pr_err("yrgb_srcH should be");
2467                                 pr_err(" greater than 3 !!!\n");
2468                         }
2469                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2470                                                                 yrgb_dstH);
2471                         break;
2472                 default:
2473                         pr_info("%s:un support yrgb_vsu_mode:%d\n",
2474                                 __func__, win->yrgb_vsu_mode);
2475                         break;
2476                 }
2477                 break;
2478         case SCALE_DOWN:
2479                 switch (win->yrgb_vsd_mode) {
2480                 case SCALE_DOWN_BIL:
2481                         yrgb_vscalednmult =
2482                             rk3368_get_hard_ware_vskiplines(yrgb_srcH,
2483                                                             yrgb_dstH);
2484                         yrgb_yscl_factor =
2485                             GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2486                                                            yrgb_vscalednmult);
2487                         if (yrgb_yscl_factor >= 0x2000) {
2488                                 pr_err("yrgb_yscl_factor should be ");
2489                                 pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n",
2490                                        yrgb_yscl_factor);
2491                         }
2492                         if (yrgb_vscalednmult == 4) {
2493                                 yrgb_vsd_bil_gt4 = 1;
2494                                 yrgb_vsd_bil_gt2 = 0;
2495                         } else if (yrgb_vscalednmult == 2) {
2496                                 yrgb_vsd_bil_gt4 = 0;
2497                                 yrgb_vsd_bil_gt2 = 1;
2498                         } else {
2499                                 yrgb_vsd_bil_gt4 = 0;
2500                                 yrgb_vsd_bil_gt2 = 0;
2501                         }
2502                         break;
2503                 case SCALE_DOWN_AVG:
2504                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2505                                                                  yrgb_dstH);
2506                         break;
2507                 default:
2508                         pr_info("%s:un support yrgb_vsd_mode:%d\n",
2509                                 __func__, win->yrgb_vsd_mode);
2510                         break;
2511                 }               /*win->yrgb_vsd_mode */
2512                 break;
2513         default:
2514                 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2515                         __func__, win->yrgb_ver_scl_mode);
2516                 break;
2517         }
2518         win->scale_yrgb_x = yrgb_xscl_factor;
2519         win->scale_yrgb_y = yrgb_yscl_factor;
2520         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2521         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2522         DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2523             yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2524
2525         /*(2.1)CBCR HOR SCALE FACTOR */
2526         switch (win->cbr_hor_scl_mode) {
2527         case SCALE_NONE:
2528                 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2529                 break;
2530         case SCALE_UP:
2531                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2532                 break;
2533         case SCALE_DOWN:
2534                 switch (win->cbr_hsd_mode) {
2535                 case SCALE_DOWN_BIL:
2536                         cbcr_xscl_factor =
2537                             GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2538                         break;
2539                 case SCALE_DOWN_AVG:
2540                         cbcr_xscl_factor =
2541                             GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2542                         break;
2543                 default:
2544                         pr_info("%s:un support cbr_hsd_mode:%d\n",
2545                                 __func__, win->cbr_hsd_mode);
2546                         break;
2547                 }
2548                 break;
2549         default:
2550                 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2551                         __func__, win->cbr_hor_scl_mode);
2552                 break;
2553         }                       /*win->cbr_hor_scl_mode */
2554
2555         /*(2.2)CBCR VER SCALE FACTOR */
2556         switch (win->cbr_ver_scl_mode) {
2557         case SCALE_NONE:
2558                 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2559                 break;
2560         case SCALE_UP:
2561                 switch (win->cbr_vsu_mode) {
2562                 case SCALE_UP_BIL:
2563                         cbcr_yscl_factor =
2564                             GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2565                         break;
2566                 case SCALE_UP_BIC:
2567                         if (cbcr_srcH < 3) {
2568                                 pr_err("cbcr_srcH should be ");
2569                                 pr_err("greater than 3 !!!\n");
2570                         }
2571                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2572                                                                 cbcr_dstH);
2573                         break;
2574                 default:
2575                         pr_info("%s:un support cbr_vsu_mode:%d\n",
2576                                 __func__, win->cbr_vsu_mode);
2577                         break;
2578                 }
2579                 break;
2580         case SCALE_DOWN:
2581                 switch (win->cbr_vsd_mode) {
2582                 case SCALE_DOWN_BIL:
2583                         cbcr_vscalednmult =
2584                             rk3368_get_hard_ware_vskiplines(cbcr_srcH,
2585                                                             cbcr_dstH);
2586                         cbcr_yscl_factor =
2587                             GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2588                                                            cbcr_vscalednmult);
2589                         if (cbcr_yscl_factor >= 0x2000) {
2590                                 pr_err("cbcr_yscl_factor should be less ");
2591                                 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2592                                        cbcr_yscl_factor);
2593                         }
2594
2595                         if (cbcr_vscalednmult == 4) {
2596                                 cbcr_vsd_bil_gt4 = 1;
2597                                 cbcr_vsd_bil_gt2 = 0;
2598                         } else if (cbcr_vscalednmult == 2) {
2599                                 cbcr_vsd_bil_gt4 = 0;
2600                                 cbcr_vsd_bil_gt2 = 1;
2601                         } else {
2602                                 cbcr_vsd_bil_gt4 = 0;
2603                                 cbcr_vsd_bil_gt2 = 0;
2604                         }
2605                         break;
2606                 case SCALE_DOWN_AVG:
2607                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2608                                                                  cbcr_dstH);
2609                         break;
2610                 default:
2611                         pr_info("%s:un support cbr_vsd_mode:%d\n",
2612                                 __func__, win->cbr_vsd_mode);
2613                         break;
2614                 }
2615                 break;
2616         default:
2617                 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2618                         __func__, win->cbr_ver_scl_mode);
2619                 break;
2620         }
2621         win->scale_cbcr_x = cbcr_xscl_factor;
2622         win->scale_cbcr_y = cbcr_yscl_factor;
2623         win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2624         win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2625
2626         DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2627             cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2628         return 0;
2629 }
2630
2631 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2632                      struct rk_lcdc_win_area *area)
2633 {
2634         int pos;
2635
2636         if (screen->x_mirror && mirror_en)
2637                 pr_err("not support both win and global mirror\n");
2638
2639         if ((!mirror_en) && (!screen->x_mirror))
2640                 pos = area->xpos + screen->mode.left_margin +
2641                         screen->mode.hsync_len;
2642         else
2643                 pos = screen->mode.xres - area->xpos -
2644                         area->xsize + screen->mode.left_margin +
2645                         screen->mode.hsync_len;
2646
2647         return pos;
2648 }
2649
2650 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2651                      struct rk_lcdc_win_area *area)
2652 {
2653         int pos;
2654
2655         if (screen->y_mirror && mirror_en)
2656                 pr_err("not support both win and global mirror\n");
2657         if (screen->mode.vmode == FB_VMODE_NONINTERLACED) {
2658                 if ((!mirror_en) && (!screen->y_mirror))
2659                         pos = area->ypos + screen->mode.upper_margin +
2660                                 screen->mode.vsync_len;
2661                 else
2662                         pos = screen->mode.yres - area->ypos -
2663                                 area->ysize + screen->mode.upper_margin +
2664                                 screen->mode.vsync_len;
2665         } else if (screen->mode.vmode == FB_VMODE_INTERLACED) {
2666                 pos = area->ypos / 2 + screen->mode.upper_margin +
2667                         screen->mode.vsync_len;
2668                 area->ysize /= 2;
2669         }
2670
2671         return pos;
2672 }
2673
2674 static int win_0_1_set_par(struct lcdc_device *lcdc_dev,
2675                            struct rk_screen *screen, struct rk_lcdc_win *win)
2676 {
2677         u32 xact, yact, xvir, yvir, xpos, ypos;
2678         u8 fmt_cfg = 0, swap_rb;
2679         char fmt[9] = "NULL";
2680
2681         xpos = dsp_x_pos(win->mirror_en, screen, &win->area[0]);
2682         ypos = dsp_y_pos(win->mirror_en, screen, &win->area[0]);
2683
2684         spin_lock(&lcdc_dev->reg_lock);
2685         if (likely(lcdc_dev->clk_on)) {
2686                 rk3368_lcdc_cal_scl_fac(win);   /*fac,lb,gt2,gt4 */
2687                 switch (win->area[0].format) {
2688                 case FBDC_RGB_565:
2689                         fmt_cfg = 2;
2690                         swap_rb = 0;
2691                         win->fmt_10 = 0;
2692                         win->area[0].fbdc_fmt_cfg = 0x05;
2693                         break;
2694                 case FBDC_ARGB_888:
2695                         fmt_cfg = 0;
2696                         swap_rb = 0;
2697                         win->fmt_10 = 0;
2698                         win->area[0].fbdc_fmt_cfg = 0x0c;
2699                         break;
2700                 case FBDC_RGBX_888:
2701                         fmt_cfg = 0;
2702                         swap_rb = 0;
2703                         win->fmt_10 = 0;
2704                         win->area[0].fbdc_fmt_cfg = 0x3a;
2705                         break;
2706                 case ARGB888:
2707                         fmt_cfg = 0;
2708                         swap_rb = 0;
2709                         win->fmt_10 = 0;
2710                         break;
2711                 case XBGR888:
2712                 case ABGR888:
2713                         fmt_cfg = 0;
2714                         swap_rb = 1;
2715                         win->fmt_10 = 0;
2716                         break;
2717                 case RGB888:
2718                         fmt_cfg = 1;
2719                         swap_rb = 0;
2720                         win->fmt_10 = 0;
2721                         break;
2722                 case RGB565:
2723                         fmt_cfg = 2;
2724                         swap_rb = 0;
2725                         win->fmt_10 = 0;
2726                         break;
2727                 case YUV422:
2728                         fmt_cfg = 5;
2729                         swap_rb = 0;
2730                         win->fmt_10 = 0;
2731                         break;
2732                 case YUV420:
2733                         fmt_cfg = 4;
2734                         swap_rb = 0;
2735                         win->fmt_10 = 0;
2736                         break;
2737                 case YUV444:
2738                         fmt_cfg = 6;
2739                         swap_rb = 0;
2740                         win->fmt_10 = 0;
2741                         break;
2742                 case YUV422_A:
2743                         fmt_cfg = 5;
2744                         swap_rb = 0;
2745                         win->fmt_10 = 1;
2746                         break;
2747                 case YUV420_A:
2748                         fmt_cfg = 4;
2749                         swap_rb = 0;
2750                         win->fmt_10 = 1;
2751                         break;
2752                 case YUV444_A:
2753                         fmt_cfg = 6;
2754                         swap_rb = 0;
2755                         win->fmt_10 = 1;
2756                         break;
2757                 default:
2758                         dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n",
2759                                 __func__);
2760                         break;
2761                 }
2762                 win->area[0].fmt_cfg = fmt_cfg;
2763                 win->area[0].swap_rb = swap_rb;
2764                 win->area[0].dsp_stx = xpos;
2765                 win->area[0].dsp_sty = ypos;
2766                 xact = win->area[0].xact;
2767                 yact = win->area[0].yact;
2768                 xvir = win->area[0].xvir;
2769                 yvir = win->area[0].yvir;
2770         }
2771         if (win->area[0].fbdc_en)
2772                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2773         rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id);
2774         spin_unlock(&lcdc_dev->reg_lock);
2775
2776         DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2777             lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2778             xact, yact, win->area[0].xsize);
2779         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2780             win->area[0].ysize, xvir, yvir, xpos, ypos);
2781
2782         return 0;
2783 }
2784
2785
2786 static int win_2_3_set_par(struct lcdc_device *lcdc_dev,
2787                            struct rk_screen *screen, struct rk_lcdc_win *win)
2788 {
2789         int i;
2790         u8 fmt_cfg, swap_rb;
2791         char fmt[9] = "NULL";
2792
2793         if (win->mirror_en)
2794                 pr_err("win[%d] not support y mirror\n", win->id);
2795         spin_lock(&lcdc_dev->reg_lock);
2796         if (likely(lcdc_dev->clk_on)) {
2797                 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id);
2798                 for (i = 0; i < win->area_num; i++) {
2799                         switch (win->area[i].format) {
2800                         case FBDC_RGB_565:
2801                                 fmt_cfg = 2;
2802                                 swap_rb = 0;
2803                                 win->fmt_10 = 0;
2804                                 win->area[0].fbdc_fmt_cfg = 0x05;
2805                                 break;
2806                         case FBDC_ARGB_888:
2807                                 fmt_cfg = 0;
2808                                 swap_rb = 0;
2809                                 win->fmt_10 = 0;
2810                                 win->area[0].fbdc_fmt_cfg = 0x0c;
2811                                 break;
2812                         case FBDC_RGBX_888:
2813                                 fmt_cfg = 0;
2814                                 swap_rb = 0;
2815                                 win->fmt_10 = 0;
2816                                 win->area[0].fbdc_fmt_cfg = 0x3a;
2817                                 break;
2818                         case ARGB888:
2819                                 fmt_cfg = 0;
2820                                 swap_rb = 0;
2821                                 break;
2822                         case XBGR888:
2823                         case ABGR888:
2824                                 fmt_cfg = 0;
2825                                 swap_rb = 1;
2826                                 break;
2827                         case RGB888:
2828                                 fmt_cfg = 1;
2829                                 swap_rb = 0;
2830                                 break;
2831                         case RGB565:
2832                                 fmt_cfg = 2;
2833                                 swap_rb = 0;
2834                                 break;
2835                         default:
2836                                 dev_err(lcdc_dev->driver.dev,
2837                                         "%s:un supported format!\n", __func__);
2838                                 break;
2839                         }
2840                         win->area[i].fmt_cfg = fmt_cfg;
2841                         win->area[i].swap_rb = swap_rb;
2842                         win->area[i].dsp_stx =
2843                                         dsp_x_pos(win->mirror_en, screen,
2844                                                   &win->area[i]);
2845                         win->area[i].dsp_sty =
2846                                         dsp_y_pos(win->mirror_en, screen,
2847                                                   &win->area[i]);
2848
2849                         DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
2850                             get_format_string(win->area[i].format, fmt),
2851                             win->area[i].xsize, win->area[i].ysize,
2852                             win->area[i].xpos, win->area[i].ypos);
2853                 }
2854         }
2855         if (win->area[0].fbdc_en)
2856                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2857         rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id);
2858         spin_unlock(&lcdc_dev->reg_lock);
2859         return 0;
2860 }
2861
2862 static int hwc_set_par(struct lcdc_device *lcdc_dev,
2863                        struct rk_screen *screen, struct rk_lcdc_win *win)
2864 {
2865         u32 xact, yact, xvir, yvir, xpos, ypos;
2866         u8 fmt_cfg = 0, swap_rb;
2867         char fmt[9] = "NULL";
2868
2869         xpos = win->area[0].xpos + screen->mode.left_margin +
2870             screen->mode.hsync_len;
2871         ypos = win->area[0].ypos + screen->mode.upper_margin +
2872             screen->mode.vsync_len;
2873
2874         spin_lock(&lcdc_dev->reg_lock);
2875         if (likely(lcdc_dev->clk_on)) {
2876                 /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */
2877                 switch (win->area[0].format) {
2878                 case ARGB888:
2879                         fmt_cfg = 0;
2880                         swap_rb = 0;
2881                         break;
2882                 case XBGR888:
2883                 case ABGR888:
2884                         fmt_cfg = 0;
2885                         swap_rb = 1;
2886                         break;
2887                 case RGB888:
2888                         fmt_cfg = 1;
2889                         swap_rb = 0;
2890                         break;
2891                 case RGB565:
2892                         fmt_cfg = 2;
2893                         swap_rb = 0;
2894                         break;
2895                 default:
2896                         dev_err(lcdc_dev->driver.dev,
2897                                 "%s:un supported format!\n", __func__);
2898                         break;
2899                 }
2900                 win->area[0].fmt_cfg = fmt_cfg;
2901                 win->area[0].swap_rb = swap_rb;
2902                 win->area[0].dsp_stx = xpos;
2903                 win->area[0].dsp_sty = ypos;
2904                 xact = win->area[0].xact;
2905                 yact = win->area[0].yact;
2906                 xvir = win->area[0].xvir;
2907                 yvir = win->area[0].yvir;
2908         }
2909         rk3368_hwc_reg_update(&lcdc_dev->driver, 4);
2910         spin_unlock(&lcdc_dev->reg_lock);
2911
2912         DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2913             lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt),
2914             xact, yact, win->area[0].xsize);
2915         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2916             win->area[0].ysize, xvir, yvir, xpos, ypos);
2917         return 0;
2918 }
2919
2920 static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
2921 {
2922         struct lcdc_device *lcdc_dev =
2923             container_of(dev_drv, struct lcdc_device, driver);
2924         struct rk_lcdc_win *win = NULL;
2925         struct rk_screen *screen = dev_drv->cur_screen;
2926
2927         win = dev_drv->win[win_id];
2928         switch (win_id) {
2929         case 0:
2930                 win_0_1_set_par(lcdc_dev, screen, win);
2931                 break;
2932         case 1:
2933                 win_0_1_set_par(lcdc_dev, screen, win);
2934                 break;
2935         case 2:
2936                 win_2_3_set_par(lcdc_dev, screen, win);
2937                 break;
2938         case 3:
2939                 win_2_3_set_par(lcdc_dev, screen, win);
2940                 break;
2941         case 4:
2942                 hwc_set_par(lcdc_dev, screen, win);
2943                 break;
2944         default:
2945                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2946                 break;
2947         }
2948         return 0;
2949 }
2950
2951 static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2952                              unsigned long arg, int win_id)
2953 {
2954         struct lcdc_device *lcdc_dev =
2955             container_of(dev_drv, struct lcdc_device, driver);
2956         u32 panel_size[2];
2957         void __user *argp = (void __user *)arg;
2958         struct color_key_cfg clr_key_cfg;
2959
2960         switch (cmd) {
2961         case RK_FBIOGET_PANEL_SIZE:
2962                 panel_size[0] = lcdc_dev->screen->mode.xres;
2963                 panel_size[1] = lcdc_dev->screen->mode.yres;
2964                 if (copy_to_user(argp, panel_size, 8))
2965                         return -EFAULT;
2966                 break;
2967         case RK_FBIOPUT_COLOR_KEY_CFG:
2968                 if (copy_from_user(&clr_key_cfg, argp,
2969                                    sizeof(struct color_key_cfg)))
2970                         return -EFAULT;
2971                 rk3368_lcdc_clr_key_cfg(dev_drv);
2972                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
2973                             clr_key_cfg.win0_color_key_cfg);
2974                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
2975                             clr_key_cfg.win1_color_key_cfg);
2976                 break;
2977
2978         default:
2979                 break;
2980         }
2981         return 0;
2982 }
2983
2984 static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
2985 {
2986         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2987                                                     struct lcdc_device, driver);
2988         /*struct device_node *backlight;*/
2989
2990         if (lcdc_dev->backlight)
2991                 return 0;
2992 #if 0
2993         backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0);
2994         if (backlight) {
2995                 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
2996                 if (!lcdc_dev->backlight)
2997                         dev_info(lcdc_dev->dev, "No find backlight device\n");
2998         } else {
2999                 dev_info(lcdc_dev->dev, "No find backlight device node\n");
3000         }
3001 #endif
3002         return 0;
3003 }
3004
3005 static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
3006 {
3007         struct lcdc_device *lcdc_dev =
3008             container_of(dev_drv, struct lcdc_device, driver);
3009         if (dev_drv->suspend_flag)
3010                 return 0;
3011         /* close the backlight */
3012         /*rk3368_lcdc_get_backlight_device(dev_drv);
3013         if (lcdc_dev->backlight) {
3014                 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
3015                 backlight_update_status(lcdc_dev->backlight);
3016         }*/
3017
3018         dev_drv->suspend_flag = 1;
3019         flush_kthread_worker(&dev_drv->update_regs_worker);
3020
3021         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3022                 dev_drv->trsm_ops->disable();
3023
3024         spin_lock(&lcdc_dev->reg_lock);
3025         if (likely(lcdc_dev->clk_on)) {
3026                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3027                              v_DSP_BLANK_EN(1));
3028                 lcdc_msk_reg(lcdc_dev,
3029                              INTR_CLEAR, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR,
3030                              v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1));
3031                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3032                              v_DSP_OUT_ZERO(1));
3033                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
3034                 lcdc_cfg_done(lcdc_dev);
3035
3036                 if (dev_drv->iommu_enabled) {
3037                         if (dev_drv->mmu_dev)
3038                                 rockchip_iovmm_deactivate(dev_drv->dev);
3039                 }
3040
3041                 spin_unlock(&lcdc_dev->reg_lock);
3042         } else {
3043                 spin_unlock(&lcdc_dev->reg_lock);
3044                 return 0;
3045         }
3046         rk3368_lcdc_clk_disable(lcdc_dev);
3047         rk_disp_pwr_disable(dev_drv);
3048         return 0;
3049 }
3050
3051 static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
3052 {
3053         struct lcdc_device *lcdc_dev =
3054             container_of(dev_drv, struct lcdc_device, driver);
3055
3056         if (!dev_drv->suspend_flag)
3057                 return 0;
3058         rk_disp_pwr_enable(dev_drv);
3059         dev_drv->suspend_flag = 0;
3060
3061         if (1/*lcdc_dev->atv_layer_cnt*/) {
3062                 rk3368_lcdc_clk_enable(lcdc_dev);
3063                 rk3368_lcdc_reg_restore(lcdc_dev);
3064
3065                 spin_lock(&lcdc_dev->reg_lock);
3066                 if (dev_drv->cur_screen->dsp_lut)
3067                         rk3368_lcdc_set_lut(dev_drv,
3068                                             dev_drv->cur_screen->dsp_lut);
3069                 if (dev_drv->cur_screen->cabc_lut)
3070                         rk3368_set_cabc_lut(dev_drv,
3071                                             dev_drv->cur_screen->cabc_lut);
3072
3073                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3074                              v_DSP_OUT_ZERO(0));
3075                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
3076                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3077                              v_DSP_BLANK_EN(0));
3078                 lcdc_cfg_done(lcdc_dev);
3079
3080                 if (dev_drv->iommu_enabled) {
3081                         if (dev_drv->mmu_dev)
3082                                 rockchip_iovmm_activate(dev_drv->dev);
3083                 }
3084
3085                 spin_unlock(&lcdc_dev->reg_lock);
3086         }
3087
3088         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3089                 dev_drv->trsm_ops->enable();
3090
3091         return 0;
3092 }
3093
3094 static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv,
3095                              int win_id, int blank_mode)
3096 {
3097         switch (blank_mode) {
3098         case FB_BLANK_UNBLANK:
3099                 rk3368_lcdc_early_resume(dev_drv);
3100                 break;
3101         case FB_BLANK_NORMAL:
3102                 rk3368_lcdc_early_suspend(dev_drv);
3103                 break;
3104         default:
3105                 rk3368_lcdc_early_suspend(dev_drv);
3106                 break;
3107         }
3108
3109         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
3110
3111         return 0;
3112 }
3113
3114 static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
3115 {
3116         return 0;
3117 }
3118
3119 /*overlay will be do at regupdate*/
3120 static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
3121                                bool set)
3122 {
3123         struct lcdc_device *lcdc_dev =
3124             container_of(dev_drv, struct lcdc_device, driver);
3125         struct rk_lcdc_win *win = NULL;
3126         int i, ovl;
3127         unsigned int mask, val;
3128         int z_order_num = 0;
3129         int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3130
3131         if (swap == 0) {
3132                 for (i = 0; i < 4; i++) {
3133                         win = dev_drv->win[i];
3134                         if (win->state == 1)
3135                                 z_order_num++;
3136                 }
3137                 for (i = 0; i < 4; i++) {
3138                         win = dev_drv->win[i];
3139                         if (win->state == 0)
3140                                 win->z_order = z_order_num++;
3141                         switch (win->z_order) {
3142                         case 0:
3143                                 layer0_sel = win->id;
3144                                 break;
3145                         case 1:
3146                                 layer1_sel = win->id;
3147                                 break;
3148                         case 2:
3149                                 layer2_sel = win->id;
3150                                 break;
3151                         case 3:
3152                                 layer3_sel = win->id;
3153                                 break;
3154                         default:
3155                                 break;
3156                         }
3157                 }
3158         } else {
3159                 layer0_sel = swap % 10;
3160                 layer1_sel = swap / 10 % 10;
3161                 layer2_sel = swap / 100 % 10;
3162                 layer3_sel = swap / 1000;
3163         }
3164
3165         spin_lock(&lcdc_dev->reg_lock);
3166         if (lcdc_dev->clk_on) {
3167                 if (set) {
3168                         mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
3169                             m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
3170                         val = v_DSP_LAYER0_SEL(layer0_sel) |
3171                             v_DSP_LAYER1_SEL(layer1_sel) |
3172                             v_DSP_LAYER2_SEL(layer2_sel) |
3173                             v_DSP_LAYER3_SEL(layer3_sel);
3174                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
3175                 } else {
3176                         layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3177                                                    m_DSP_LAYER0_SEL);
3178                         layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3179                                                    m_DSP_LAYER1_SEL);
3180                         layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3181                                                    m_DSP_LAYER2_SEL);
3182                         layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3183                                                    m_DSP_LAYER3_SEL);
3184                         ovl = layer3_sel * 1000 + layer2_sel * 100 +
3185                             layer1_sel * 10 + layer0_sel;
3186                 }
3187         } else {
3188                 ovl = -EPERM;
3189         }
3190         spin_unlock(&lcdc_dev->reg_lock);
3191
3192         return ovl;
3193 }
3194
3195 static char *rk3368_lcdc_format_to_string(int format, char *fmt)
3196 {
3197         if (!fmt)
3198                 return NULL;
3199
3200         switch (format) {
3201         case 0:
3202                 strcpy(fmt, "ARGB888");
3203                 break;
3204         case 1:
3205                 strcpy(fmt, "RGB888");
3206                 break;
3207         case 2:
3208                 strcpy(fmt, "RGB565");
3209                 break;
3210         case 4:
3211                 strcpy(fmt, "YCbCr420");
3212                 break;
3213         case 5:
3214                 strcpy(fmt, "YCbCr422");
3215                 break;
3216         case 6:
3217                 strcpy(fmt, "YCbCr444");
3218                 break;
3219         default:
3220                 strcpy(fmt, "invalid\n");
3221                 break;
3222         }
3223         return fmt;
3224 }
3225 static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
3226                                          char *buf, int win_id)
3227 {
3228         struct lcdc_device *lcdc_dev =
3229             container_of(dev_drv, struct lcdc_device, driver);
3230         struct rk_screen *screen = dev_drv->cur_screen;
3231         u16 hsync_len = screen->mode.hsync_len;
3232         u16 left_margin = screen->mode.left_margin;
3233         u16 vsync_len = screen->mode.vsync_len;
3234         u16 upper_margin = screen->mode.upper_margin;
3235         u32 h_pw_bp = hsync_len + left_margin;
3236         u32 v_pw_bp = vsync_len + upper_margin;
3237         u32 fmt_id;
3238         char format_w0[9] = "NULL";
3239         char format_w1[9] = "NULL";
3240         char format_w2_0[9] = "NULL";
3241         char format_w2_1[9] = "NULL";
3242         char format_w2_2[9] = "NULL";
3243         char format_w2_3[9] = "NULL";
3244         char format_w3_0[9] = "NULL";
3245         char format_w3_1[9] = "NULL";
3246         char format_w3_2[9] = "NULL";
3247         char format_w3_3[9] = "NULL";
3248         char dsp_buf[100];
3249         u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3250         u32 y_factor, uv_factor;
3251         u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3252         u8 w0_state, w1_state, w2_state, w3_state;
3253         u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3254         u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3255
3256         u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3257         u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3258         u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3259         u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3260         u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3261         u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3262
3263         u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3264         u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3265         u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3266         u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3267         u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3268         u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3269         u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3270
3271         u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3272         u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3273         u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3274         u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3275         u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3276         u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3277         u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3278         u32 dclk_freq;
3279         int size = 0;
3280
3281         dclk_freq = screen->mode.pixclock;
3282         /*rk3368_lcdc_reg_dump(dev_drv); */
3283
3284         spin_lock(&lcdc_dev->reg_lock);
3285         if (lcdc_dev->clk_on) {
3286                 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
3287                 layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8;
3288                 layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10;
3289                 layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12;
3290                 layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14;
3291                 /*WIN0 */
3292                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3293                 w0_state = win_ctrl & m_WIN0_EN;
3294                 fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1;
3295                 rk3368_lcdc_format_to_string(fmt_id, format_w0);
3296                 vir_info = lcdc_readl(lcdc_dev, WIN0_VIR);
3297                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
3298                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
3299                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
3300                 y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
3301                 uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR);
3302                 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
3303                 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16;
3304                 w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1;
3305                 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1;
3306                 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1;
3307                 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1;
3308                 if (w0_state) {
3309                         w0_st_x = dsp_st & m_WIN0_DSP_XST;
3310                         w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16;
3311                 }
3312                 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
3313                 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16;
3314                 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
3315                 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16;
3316
3317                 /*WIN1 */
3318                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3319                 w1_state = win_ctrl & m_WIN1_EN;
3320                 fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1;
3321                 rk3368_lcdc_format_to_string(fmt_id, format_w1);
3322                 vir_info = lcdc_readl(lcdc_dev, WIN1_VIR);
3323                 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
3324                 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
3325                 dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
3326                 y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB);
3327                 uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR);
3328                 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
3329                 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16;
3330                 w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1;
3331                 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1;
3332                 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1;
3333                 w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1;
3334                 if (w1_state) {
3335                         w1_st_x = dsp_st & m_WIN1_DSP_XST;
3336                         w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16;
3337                 }
3338                 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
3339                 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16;
3340                 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
3341                 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16;
3342                 /*WIN2 */
3343                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3344                 w2_state = win_ctrl & m_WIN2_EN;
3345                 w2_0_state = (win_ctrl & 0x10) >> 4;
3346                 w2_1_state = (win_ctrl & 0x100) >> 8;
3347                 w2_2_state = (win_ctrl & 0x1000) >> 12;
3348                 w2_3_state = (win_ctrl & 0x10000) >> 16;
3349                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1);
3350                 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3351                 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16;
3352                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3);
3353                 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3354                 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16;
3355
3356                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1;
3357                 rk3368_lcdc_format_to_string(fmt_id, format_w2_0);
3358                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1;
3359                 rk3368_lcdc_format_to_string(fmt_id, format_w2_1);
3360                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1;
3361                 rk3368_lcdc_format_to_string(fmt_id, format_w2_2);
3362                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1;
3363                 rk3368_lcdc_format_to_string(fmt_id, format_w2_3);
3364
3365                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0);
3366                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0);
3367                 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1;
3368                 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1;
3369                 if (w2_0_state) {
3370                         w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3371                         w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16;
3372                 }
3373                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1);
3374                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1);
3375                 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1;
3376                 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1;
3377                 if (w2_1_state) {
3378                         w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3379                         w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16;
3380                 }
3381                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2);
3382                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2);
3383                 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1;
3384                 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1;
3385                 if (w2_2_state) {
3386                         w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3387                         w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16;
3388                 }
3389                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3);
3390                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3);
3391                 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1;
3392                 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1;
3393                 if (w2_3_state) {
3394                         w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3395                         w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16;
3396                 }
3397
3398                 /*WIN3 */
3399                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3400                 w3_state = win_ctrl & m_WIN3_EN;
3401                 w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4;
3402                 w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 8;
3403                 w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 12;
3404                 w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 16;
3405                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1);
3406                 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3407                 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16;
3408                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3);
3409                 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3410                 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16;
3411                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1;
3412                 rk3368_lcdc_format_to_string(fmt_id, format_w3_0);
3413                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1;
3414                 rk3368_lcdc_format_to_string(fmt_id, format_w3_1);
3415                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1;
3416                 rk3368_lcdc_format_to_string(fmt_id, format_w3_2);
3417                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1;
3418                 rk3368_lcdc_format_to_string(fmt_id, format_w3_3);
3419                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0);
3420                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0);
3421                 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1;
3422                 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1;
3423                 if (w3_0_state) {
3424                         w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3425                         w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16;
3426                 }
3427
3428                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1);
3429                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1);
3430                 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1;
3431                 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1;
3432                 if (w3_1_state) {
3433                         w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3434                         w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16;
3435                 }
3436
3437                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2);
3438                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2);
3439                 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1;
3440                 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1;
3441                 if (w3_2_state) {
3442                         w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3443                         w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16;
3444                 }
3445
3446                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3);
3447                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3);
3448                 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1;
3449                 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1;
3450                 if (w3_3_state) {
3451                         w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3452                         w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16;
3453                 }
3454
3455         } else {
3456                 spin_unlock(&lcdc_dev->reg_lock);
3457                 return -EPERM;
3458         }
3459         spin_unlock(&lcdc_dev->reg_lock);
3460         size += snprintf(dsp_buf, 80,
3461                 "z-order:\n  win[%d]\n  win[%d]\n  win[%d]\n  win[%d]\n",
3462                 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3463         strcat(buf, dsp_buf);
3464         memset(dsp_buf, 0, sizeof(dsp_buf));
3465         /*win0*/
3466         size += snprintf(dsp_buf, 80,
3467                  "win0:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3468                  w0_state, format_w0, w0_vir_y, w0_vir_uv);
3469         strcat(buf, dsp_buf);
3470         memset(dsp_buf, 0, sizeof(dsp_buf));
3471
3472         size += snprintf(dsp_buf, 80,
3473                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3474                  w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3475         strcat(buf, dsp_buf);
3476         memset(dsp_buf, 0, sizeof(dsp_buf));
3477
3478         size += snprintf(dsp_buf, 80,
3479                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3480                  w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3481         strcat(buf, dsp_buf);
3482         memset(dsp_buf, 0, sizeof(dsp_buf));
3483
3484         size += snprintf(dsp_buf, 80,
3485                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3486                  w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3487                  lcdc_readl(lcdc_dev, WIN0_CBR_MST));
3488         strcat(buf, dsp_buf);
3489         memset(dsp_buf, 0, sizeof(dsp_buf));
3490
3491         /*win1*/
3492         size += snprintf(dsp_buf, 80,
3493                  "win1:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3494                  w1_state, format_w1, w1_vir_y, w1_vir_uv);
3495         strcat(buf, dsp_buf);
3496         memset(dsp_buf, 0, sizeof(dsp_buf));
3497
3498         size += snprintf(dsp_buf, 80,
3499                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3500                  w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3501         strcat(buf, dsp_buf);
3502         memset(dsp_buf, 0, sizeof(dsp_buf));
3503
3504         size += snprintf(dsp_buf, 80,
3505                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3506                  w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3507         strcat(buf, dsp_buf);
3508         memset(dsp_buf, 0, sizeof(dsp_buf));
3509
3510         size += snprintf(dsp_buf, 80,
3511                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3512                  w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3513                  lcdc_readl(lcdc_dev, WIN1_CBR_MST));
3514         strcat(buf, dsp_buf);
3515         memset(dsp_buf, 0, sizeof(dsp_buf));
3516
3517         /*win2*/
3518         size += snprintf(dsp_buf, 80,
3519                  "win2:\n  state:%d\n",
3520                  w2_state);
3521         strcat(buf, dsp_buf);
3522         memset(dsp_buf, 0, sizeof(dsp_buf));
3523         /*area 0*/
3524         size += snprintf(dsp_buf, 80,
3525                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3526                  w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3527         strcat(buf, dsp_buf);
3528         memset(dsp_buf, 0, sizeof(dsp_buf));
3529         size += snprintf(dsp_buf, 80,
3530                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3531                  w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3532                  lcdc_readl(lcdc_dev, WIN2_MST0));
3533         strcat(buf, dsp_buf);
3534         memset(dsp_buf, 0, sizeof(dsp_buf));
3535
3536         /*area 1*/
3537         size += snprintf(dsp_buf, 80,
3538                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3539                  w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3540         strcat(buf, dsp_buf);
3541         memset(dsp_buf, 0, sizeof(dsp_buf));
3542         size += snprintf(dsp_buf, 80,
3543                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3544                  w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3545                  lcdc_readl(lcdc_dev, WIN2_MST1));
3546         strcat(buf, dsp_buf);
3547         memset(dsp_buf, 0, sizeof(dsp_buf));
3548
3549         /*area 2*/
3550         size += snprintf(dsp_buf, 80,
3551                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3552                  w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3553         strcat(buf, dsp_buf);
3554         memset(dsp_buf, 0, sizeof(dsp_buf));
3555         size += snprintf(dsp_buf, 80,
3556                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3557                  w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3558                  lcdc_readl(lcdc_dev, WIN2_MST2));
3559         strcat(buf, dsp_buf);
3560         memset(dsp_buf, 0, sizeof(dsp_buf));
3561
3562         /*area 3*/
3563         size += snprintf(dsp_buf, 80,
3564                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3565                  w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3566         strcat(buf, dsp_buf);
3567         memset(dsp_buf, 0, sizeof(dsp_buf));
3568         size += snprintf(dsp_buf, 80,
3569                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3570                  w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3571                  lcdc_readl(lcdc_dev, WIN2_MST3));
3572         strcat(buf, dsp_buf);
3573         memset(dsp_buf, 0, sizeof(dsp_buf));
3574
3575         /*win3*/
3576         size += snprintf(dsp_buf, 80,
3577                  "win3:\n  state:%d\n",
3578                  w3_state);
3579         strcat(buf, dsp_buf);
3580         memset(dsp_buf, 0, sizeof(dsp_buf));
3581         /*area 0*/
3582         size += snprintf(dsp_buf, 80,
3583                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3584                  w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
3585         strcat(buf, dsp_buf);
3586         memset(dsp_buf, 0, sizeof(dsp_buf));
3587         size += snprintf(dsp_buf, 80,
3588                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3589                  w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
3590                  lcdc_readl(lcdc_dev, WIN3_MST0));
3591         strcat(buf, dsp_buf);
3592         memset(dsp_buf, 0, sizeof(dsp_buf));
3593
3594         /*area 1*/
3595         size += snprintf(dsp_buf, 80,
3596                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3597                  w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
3598         strcat(buf, dsp_buf);
3599         memset(dsp_buf, 0, sizeof(dsp_buf));
3600         size += snprintf(dsp_buf, 80,
3601                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3602                  w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
3603                  lcdc_readl(lcdc_dev, WIN3_MST1));
3604         strcat(buf, dsp_buf);
3605         memset(dsp_buf, 0, sizeof(dsp_buf));
3606
3607         /*area 2*/
3608         size += snprintf(dsp_buf, 80,
3609                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3610                  w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
3611         strcat(buf, dsp_buf);
3612         memset(dsp_buf, 0, sizeof(dsp_buf));
3613         size += snprintf(dsp_buf, 80,
3614                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3615                  w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
3616                  lcdc_readl(lcdc_dev, WIN3_MST2));
3617         strcat(buf, dsp_buf);
3618         memset(dsp_buf, 0, sizeof(dsp_buf));
3619
3620         /*area 3*/
3621         size += snprintf(dsp_buf, 80,
3622                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3623                  w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
3624         strcat(buf, dsp_buf);
3625         memset(dsp_buf, 0, sizeof(dsp_buf));
3626         size += snprintf(dsp_buf, 80,
3627                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3628                  w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
3629                  lcdc_readl(lcdc_dev, WIN3_MST3));
3630         strcat(buf, dsp_buf);
3631         memset(dsp_buf, 0, sizeof(dsp_buf));
3632
3633         return size;
3634 }
3635
3636 static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3637                                bool set)
3638 {
3639         struct lcdc_device *lcdc_dev =
3640             container_of(dev_drv, struct lcdc_device, driver);
3641         struct rk_screen *screen = dev_drv->cur_screen;
3642         u64 ft = 0;
3643         u32 dotclk;
3644         int ret;
3645         u32 pixclock;
3646         u32 x_total, y_total;
3647
3648         if (set) {
3649                 if (fps == 0) {
3650                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
3651                         return 0;
3652                 }
3653                 ft = div_u64(1000000000000llu, fps);
3654                 x_total =
3655                     screen->mode.upper_margin + screen->mode.lower_margin +
3656                     screen->mode.yres + screen->mode.vsync_len;
3657                 y_total =
3658                     screen->mode.left_margin + screen->mode.right_margin +
3659                     screen->mode.xres + screen->mode.hsync_len;
3660                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3661                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3662                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3663         }
3664
3665         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3666         lcdc_dev->pixclock = pixclock;
3667         dev_drv->pixclock = lcdc_dev->pixclock;
3668         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3669         screen->ft = 1000 / fps;        /*one frame time in ms */
3670
3671         if (set)
3672                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3673                          clk_get_rate(lcdc_dev->dclk), fps);
3674
3675         return fps;
3676 }
3677
3678 static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3679 {
3680         mutex_lock(&dev_drv->fb_win_id_mutex);
3681         if (order == FB_DEFAULT_ORDER)
3682                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
3683         dev_drv->fb4_win_id = order / 10000;
3684         dev_drv->fb3_win_id = (order / 1000) % 10;
3685         dev_drv->fb2_win_id = (order / 100) % 10;
3686         dev_drv->fb1_win_id = (order / 10) % 10;
3687         dev_drv->fb0_win_id = order % 10;
3688         mutex_unlock(&dev_drv->fb_win_id_mutex);
3689
3690         return 0;
3691 }
3692
3693 static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3694                                   const char *id)
3695 {
3696         int win_id = 0;
3697
3698         mutex_lock(&dev_drv->fb_win_id_mutex);
3699         if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
3700                 win_id = dev_drv->fb0_win_id;
3701         else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
3702                 win_id = dev_drv->fb1_win_id;
3703         else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
3704                 win_id = dev_drv->fb2_win_id;
3705         else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
3706                 win_id = dev_drv->fb3_win_id;
3707         else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
3708                 win_id = dev_drv->fb4_win_id;
3709         mutex_unlock(&dev_drv->fb_win_id_mutex);
3710
3711         return win_id;
3712 }
3713
3714 static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3715 {
3716         struct lcdc_device *lcdc_dev =
3717             container_of(dev_drv, struct lcdc_device, driver);
3718         int i;
3719         unsigned int mask, val;
3720         struct rk_lcdc_win *win = NULL;
3721
3722         spin_lock(&lcdc_dev->reg_lock);
3723         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3724                      v_STANDBY_EN(lcdc_dev->standby));
3725         for (i = 0; i < 4; i++) {
3726                 win = dev_drv->win[i];
3727                 if ((win->state == 0) && (win->last_state == 1)) {
3728                         switch (win->id) {
3729                         case 0:
3730                                 /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
3731                                    for rk3288 to fix hw bug? */
3732                                 mask = m_WIN0_EN;
3733                                 val = v_WIN0_EN(0);
3734                                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
3735                                 break;
3736                         case 1:
3737                                 /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
3738                                    for rk3288 to fix hw bug? */
3739                                 mask = m_WIN1_EN;
3740                                 val = v_WIN1_EN(0);
3741                                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
3742                                 break;
3743                         case 2:
3744                                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
3745                                     m_WIN2_MST1_EN |
3746                                     m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3747                                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
3748                                     v_WIN2_MST1_EN(0) |
3749                                     v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3750                                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
3751                                 break;
3752                         case 3:
3753                                 mask = m_WIN3_EN | m_WIN3_MST0_EN |
3754                                     m_WIN3_MST1_EN |
3755                                     m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3756                                 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |
3757                                     v_WIN3_MST1_EN(0) |
3758                                     v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3759                                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
3760                                 break;
3761                         case 4:
3762                                 mask = m_HWC_EN;
3763                                 val = v_HWC_EN(0);
3764                                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
3765                                 break;
3766                         default:
3767                                 break;
3768                         }
3769                 }
3770                 win->last_state = win->state;
3771         }
3772         lcdc_cfg_done(lcdc_dev);
3773         spin_unlock(&lcdc_dev->reg_lock);
3774         return 0;
3775 }
3776
3777 static int rk3368_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3778 {
3779         struct lcdc_device *lcdc_dev =
3780             container_of(dev_drv, struct lcdc_device, driver);
3781         spin_lock(&lcdc_dev->reg_lock);
3782         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3783                      v_DIRECT_PATH_EN(open));
3784         lcdc_cfg_done(lcdc_dev);
3785         spin_unlock(&lcdc_dev->reg_lock);
3786         return 0;
3787 }
3788
3789 static int rk3368_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3790 {
3791         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3792                                                     struct lcdc_device, driver);
3793         spin_lock(&lcdc_dev->reg_lock);
3794         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3795                      v_DIRECT_PATCH_SEL(win_id));
3796         lcdc_cfg_done(lcdc_dev);
3797         spin_unlock(&lcdc_dev->reg_lock);
3798         return 0;
3799 }
3800
3801 static int rk3368_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3802 {
3803         struct lcdc_device *lcdc_dev =
3804             container_of(dev_drv, struct lcdc_device, driver);
3805         int ovl;
3806
3807         spin_lock(&lcdc_dev->reg_lock);
3808         ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3809         spin_unlock(&lcdc_dev->reg_lock);
3810         return ovl;
3811 }
3812
3813 static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
3814                                       int enable)
3815 {
3816         struct lcdc_device *lcdc_dev =
3817             container_of(dev_drv, struct lcdc_device, driver);
3818         if (enable)
3819                 enable_irq(lcdc_dev->irq);
3820         else
3821                 disable_irq(lcdc_dev->irq);
3822         return 0;
3823 }
3824
3825 int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3826 {
3827         struct lcdc_device *lcdc_dev =
3828             container_of(dev_drv, struct lcdc_device, driver);
3829         u32 int_reg;
3830         int ret;
3831
3832         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
3833                 int_reg = lcdc_readl(lcdc_dev, INTR_STATUS);
3834                 if (int_reg & m_LINE_FLAG0_INTR_STS) {
3835                         lcdc_dev->driver.frame_time.last_framedone_t =
3836                             lcdc_dev->driver.frame_time.framedone_t;
3837                         lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3838                         lcdc_msk_reg(lcdc_dev, INTR_CLEAR,
3839                                      m_LINE_FLAG0_INTR_CLR,
3840                                      v_LINE_FLAG0_INTR_CLR(1));
3841                         ret = RK_LF_STATUS_FC;
3842                 } else {
3843                         ret = RK_LF_STATUS_FR;
3844                 }
3845         } else {
3846                 ret = RK_LF_STATUS_NC;
3847         }
3848
3849         return ret;
3850 }
3851
3852 static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3853                                     unsigned int *dsp_addr)
3854 {
3855         struct lcdc_device *lcdc_dev =
3856             container_of(dev_drv, struct lcdc_device, driver);
3857         spin_lock(&lcdc_dev->reg_lock);
3858         if (lcdc_dev->clk_on) {
3859                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3860                 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3861                 dsp_addr[2] = lcdc_readl(lcdc_dev, WIN2_MST0);
3862                 dsp_addr[3] = lcdc_readl(lcdc_dev, WIN3_MST0);
3863         }
3864         spin_unlock(&lcdc_dev->reg_lock);
3865         return 0;
3866 }
3867
3868 static struct lcdc_cabc_mode cabc_mode[4] = {
3869       /* calc,     up,     down,   global_limit   */
3870         {5,    256,  256,   256},  /*mode 1   0*/
3871         {5,    258,  253,   277},  /*mode 2   15%*/
3872         {5,    259,  252,   330},  /*mode 3   40%*/
3873         {5,    267,  244,   400},  /*mode 4   60%*/
3874 };
3875
3876 static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode)
3877 {
3878         struct lcdc_device *lcdc_dev =
3879             container_of(dev_drv, struct lcdc_device, driver);
3880         struct rk_screen *screen = dev_drv->cur_screen;
3881         u32 total_pixel, calc_pixel, stage_up, stage_down;
3882         u32 pixel_num, global_su;
3883         u32 stage_up_rec, stage_down_rec, global_su_rec, gamma_global_su_rec;
3884         u32 mask = 0, val = 0, cabc_en = 0;
3885         int *cabc_lut = NULL;
3886
3887         if (!screen->cabc_lut) {
3888                 pr_err("screen cabc lut not config, so not open cabc\n");
3889                 return 0;
3890         } else {
3891                 cabc_lut = screen->cabc_lut;
3892         }
3893
3894         dev_drv->cabc_mode = mode;
3895         cabc_en = (mode > 0) ? 1 : 0;
3896
3897         if (cabc_en == 0) {
3898                 spin_lock(&lcdc_dev->reg_lock);
3899                 if (lcdc_dev->clk_on) {
3900                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
3901                                      m_CABC_EN, v_CABC_EN(0));
3902                         lcdc_cfg_done(lcdc_dev);
3903                 }
3904                 spin_unlock(&lcdc_dev->reg_lock);
3905                 return 0;
3906         }
3907
3908         total_pixel = screen->mode.xres * screen->mode.yres;
3909         pixel_num = 1000 - (cabc_mode[mode - 1].pixel_num);
3910         calc_pixel = (total_pixel * pixel_num) / 1000;
3911         stage_up = cabc_mode[mode - 1].stage_up;
3912         stage_down = cabc_mode[mode - 1].stage_down;
3913         global_su = cabc_mode[mode - 1].global_su;
3914
3915         stage_up_rec = 256 * 256 / stage_up;
3916         stage_down_rec = 256 * 256 / stage_down;
3917         global_su_rec = (256 * 256 / global_su) - 1;
3918         gamma_global_su_rec = cabc_lut[global_su_rec];
3919
3920         spin_lock(&lcdc_dev->reg_lock);
3921         if (lcdc_dev->clk_on) {
3922                 mask = m_CABC_CALC_PIXEL_NUM | m_CABC_EN;
3923                 val = v_CABC_CALC_PIXEL_NUM(calc_pixel) |
3924                         v_CABC_EN(cabc_en);
3925                 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3926
3927                 mask = m_CABC_TOTAL_PIXEL_NUM | m_CABC_LUT_EN;
3928                 val = v_CABC_TOTAL_PIXEL_NUM(total_pixel) | v_CABC_LUT_EN(1);
3929                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3930
3931                 mask = m_CABC_STAGE_UP | m_CABC_STAGE_UP_REC |
3932                     m_CABC_GLOBAL_SU_LIMIT_EN | m_CABC_GLOBAL_SU_REC;
3933                 val = v_CABC_STAGE_UP(stage_up) |
3934                     v_CABC_STAGE_UP_REC(stage_up_rec) |
3935                     v_CABC_GLOBAL_SU_LIMIT_EN(1) |
3936                     v_CABC_GLOBAL_SU_REC(gamma_global_su_rec);
3937                 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
3938
3939                 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_DOWN_REC |
3940                     m_CABC_GLOBAL_SU;
3941                 val = v_CABC_STAGE_DOWN(stage_down) |
3942                     v_CABC_STAGE_DOWN_REC(stage_down_rec) |
3943                     v_CABC_GLOBAL_SU(global_su);
3944                 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
3945                 lcdc_cfg_done(lcdc_dev);
3946         }
3947         spin_unlock(&lcdc_dev->reg_lock);
3948
3949         return 0;
3950 }
3951
3952 /*
3953         a:[-30~0]:
3954             sin_hue = sin(a)*256 +0x100;
3955             cos_hue = cos(a)*256;
3956         a:[0~30]
3957             sin_hue = sin(a)*256;
3958             cos_hue = cos(a)*256;
3959 */
3960 static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3961                                     bcsh_hue_mode mode)
3962 {
3963         struct lcdc_device *lcdc_dev =
3964             container_of(dev_drv, struct lcdc_device, driver);
3965         u32 val;
3966
3967         spin_lock(&lcdc_dev->reg_lock);
3968         if (lcdc_dev->clk_on) {
3969                 val = lcdc_readl(lcdc_dev, BCSH_H);
3970                 switch (mode) {
3971                 case H_SIN:
3972                         val &= m_BCSH_SIN_HUE;
3973                         break;
3974                 case H_COS:
3975                         val &= m_BCSH_COS_HUE;
3976                         val >>= 16;
3977                         break;
3978                 default:
3979                         break;
3980                 }
3981         }
3982         spin_unlock(&lcdc_dev->reg_lock);
3983
3984         return val;
3985 }
3986
3987 static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3988                                     int sin_hue, int cos_hue)
3989 {
3990         struct lcdc_device *lcdc_dev =
3991             container_of(dev_drv, struct lcdc_device, driver);
3992         u32 mask, val;
3993
3994         spin_lock(&lcdc_dev->reg_lock);
3995         if (lcdc_dev->clk_on) {
3996                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
3997                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
3998                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
3999                 lcdc_cfg_done(lcdc_dev);
4000         }
4001         spin_unlock(&lcdc_dev->reg_lock);
4002
4003         return 0;
4004 }
4005
4006 static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4007                                     bcsh_bcs_mode mode, int value)
4008 {
4009         struct lcdc_device *lcdc_dev =
4010             container_of(dev_drv, struct lcdc_device, driver);
4011         u32 mask, val;
4012
4013         spin_lock(&lcdc_dev->reg_lock);
4014         if (lcdc_dev->clk_on) {
4015                 switch (mode) {
4016                 case BRIGHTNESS:
4017                         /*from 0 to 255,typical is 128 */
4018                         if (value < 0x80)
4019                                 value += 0x80;
4020                         else if (value >= 0x80)
4021                                 value = value - 0x80;
4022                         mask = m_BCSH_BRIGHTNESS;
4023                         val = v_BCSH_BRIGHTNESS(value);
4024                         break;
4025                 case CONTRAST:
4026                         /*from 0 to 510,typical is 256 */
4027                         mask = m_BCSH_CONTRAST;
4028                         val = v_BCSH_CONTRAST(value);
4029                         break;
4030                 case SAT_CON:
4031                         /*from 0 to 1015,typical is 256 */
4032                         mask = m_BCSH_SAT_CON;
4033                         val = v_BCSH_SAT_CON(value);
4034                         break;
4035                 default:
4036                         break;
4037                 }
4038                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
4039                 lcdc_cfg_done(lcdc_dev);
4040         }
4041         spin_unlock(&lcdc_dev->reg_lock);
4042         return val;
4043 }
4044
4045 static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4046                                     bcsh_bcs_mode mode)
4047 {
4048         struct lcdc_device *lcdc_dev =
4049             container_of(dev_drv, struct lcdc_device, driver);
4050         u32 val;
4051
4052         spin_lock(&lcdc_dev->reg_lock);
4053         if (lcdc_dev->clk_on) {
4054                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
4055                 switch (mode) {
4056                 case BRIGHTNESS:
4057                         val &= m_BCSH_BRIGHTNESS;
4058                         if (val > 0x80)
4059                                 val -= 0x80;
4060                         else
4061                                 val += 0x80;
4062                         break;
4063                 case CONTRAST:
4064                         val &= m_BCSH_CONTRAST;
4065                         val >>= 8;
4066                         break;
4067                 case SAT_CON:
4068                         val &= m_BCSH_SAT_CON;
4069                         val >>= 20;
4070                         break;
4071                 default:
4072                         break;
4073                 }
4074         }
4075         spin_unlock(&lcdc_dev->reg_lock);
4076         return val;
4077 }
4078
4079 static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
4080 {
4081         struct lcdc_device *lcdc_dev =
4082             container_of(dev_drv, struct lcdc_device, driver);
4083         u32 mask, val;
4084
4085         spin_lock(&lcdc_dev->reg_lock);
4086         if (lcdc_dev->clk_on) {
4087                 if (open) {
4088                         lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1);
4089                         lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
4090                         lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
4091                         dev_drv->bcsh.enable = 1;
4092                 } else {
4093                         mask = m_BCSH_EN;
4094                         val = v_BCSH_EN(0);
4095                         lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
4096                         dev_drv->bcsh.enable = 0;
4097                 }
4098                 rk3368_lcdc_bcsh_path_sel(dev_drv);
4099                 lcdc_cfg_done(lcdc_dev);
4100         }
4101         spin_unlock(&lcdc_dev->reg_lock);
4102         return 0;
4103 }
4104
4105 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4106 {
4107         if (!enable || !dev_drv->bcsh.enable) {
4108                 rk3368_lcdc_open_bcsh(dev_drv, false);
4109                 return 0;
4110         }
4111
4112         if (dev_drv->bcsh.brightness <= 255 ||
4113             dev_drv->bcsh.contrast <= 510 ||
4114             dev_drv->bcsh.sat_con <= 1015 ||
4115             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4116                 rk3368_lcdc_open_bcsh(dev_drv, true);
4117                 if (dev_drv->bcsh.brightness <= 255)
4118                         rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4119                                                  dev_drv->bcsh.brightness);
4120                 if (dev_drv->bcsh.contrast <= 510)
4121                         rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
4122                                                  dev_drv->bcsh.contrast);
4123                 if (dev_drv->bcsh.sat_con <= 1015)
4124                         rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
4125                                                  dev_drv->bcsh.sat_con);
4126                 if (dev_drv->bcsh.sin_hue <= 511 &&
4127                     dev_drv->bcsh.cos_hue <= 511)
4128                         rk3368_lcdc_set_bcsh_hue(dev_drv,
4129                                                  dev_drv->bcsh.sin_hue,
4130                                                  dev_drv->bcsh.cos_hue);
4131         }
4132         return 0;
4133 }
4134
4135 static int rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4136 {
4137         struct lcdc_device *lcdc_dev =
4138             container_of(dev_drv, struct lcdc_device, driver);
4139
4140         if (enable) {
4141                 spin_lock(&lcdc_dev->reg_lock);
4142                 if (likely(lcdc_dev->clk_on)) {
4143                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4144                                      v_DSP_BLACK_EN(1));
4145                         lcdc_cfg_done(lcdc_dev);
4146                 }
4147                 spin_unlock(&lcdc_dev->reg_lock);
4148         } else {
4149                 spin_lock(&lcdc_dev->reg_lock);
4150                 if (likely(lcdc_dev->clk_on)) {
4151                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4152                                      v_DSP_BLACK_EN(0));
4153
4154                         lcdc_cfg_done(lcdc_dev);
4155                 }
4156                 spin_unlock(&lcdc_dev->reg_lock);
4157         }
4158
4159         return 0;
4160 }
4161
4162
4163 static int rk3368_lcdc_backlight_close(struct rk_lcdc_driver *dev_drv,
4164                                        int enable)
4165 {
4166         struct lcdc_device *lcdc_dev =
4167             container_of(dev_drv, struct lcdc_device, driver);
4168
4169         rk3368_lcdc_get_backlight_device(dev_drv);
4170
4171         if (enable) {
4172                 /* close the backlight */
4173                 if (lcdc_dev->backlight) {
4174                         lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4175                         backlight_update_status(lcdc_dev->backlight);
4176                 }
4177                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4178                         dev_drv->trsm_ops->disable();
4179         } else {
4180                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4181                         dev_drv->trsm_ops->enable();
4182                 msleep(100);
4183                 /* open the backlight */
4184                 if (lcdc_dev->backlight) {
4185                         lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
4186                         backlight_update_status(lcdc_dev->backlight);
4187                 }
4188         }
4189
4190         return 0;
4191 }
4192
4193 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4194         .open = rk3368_lcdc_open,
4195         .win_direct_en = rk3368_lcdc_win_direct_en,
4196         .load_screen = rk3368_load_screen,
4197         .get_dspbuf_info = rk3368_get_dspbuf_info,
4198         .post_dspbuf = rk3368_post_dspbuf,
4199         .set_par = rk3368_lcdc_set_par,
4200         .pan_display = rk3368_lcdc_pan_display,
4201         .direct_set_addr = rk3368_lcdc_direct_set_win_addr,
4202         /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/
4203         .blank = rk3368_lcdc_blank,
4204         .ioctl = rk3368_lcdc_ioctl,
4205         .suspend = rk3368_lcdc_early_suspend,
4206         .resume = rk3368_lcdc_early_resume,
4207         .get_win_state = rk3368_lcdc_get_win_state,
4208         .ovl_mgr = rk3368_lcdc_ovl_mgr,
4209         .get_disp_info = rk3368_lcdc_get_disp_info,
4210         .fps_mgr = rk3368_lcdc_fps_mgr,
4211         .fb_get_win_id = rk3368_lcdc_get_win_id,
4212         .fb_win_remap = rk3368_fb_win_remap,
4213         .set_dsp_lut = rk3368_lcdc_set_lut,
4214         .set_cabc_lut = rk3368_set_cabc_lut,
4215         .poll_vblank = rk3368_lcdc_poll_vblank,
4216         .dpi_open = rk3368_lcdc_dpi_open,
4217         .dpi_win_sel = rk3368_lcdc_dpi_win_sel,
4218         .dpi_status = rk3368_lcdc_dpi_status,
4219         .get_dsp_addr = rk3368_lcdc_get_dsp_addr,
4220         .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc,
4221         .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue,
4222         .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs,
4223         .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue,
4224         .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs,
4225         .open_bcsh = rk3368_lcdc_open_bcsh,
4226         .dump_reg = rk3368_lcdc_reg_dump,
4227         .cfg_done = rk3368_lcdc_config_done,
4228         .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu,
4229         .dsp_black = rk3368_lcdc_dsp_black,
4230         .backlight_close = rk3368_lcdc_backlight_close,
4231         .mmu_en    = rk3368_lcdc_mmu_en,
4232 };
4233
4234 #ifdef LCDC_IRQ_EMPTY_DEBUG
4235 static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev,
4236                                  unsigned int intr_status)
4237 {
4238         if (intr_status & m_WIN0_EMPTY_INTR_STS) {
4239                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN0_EMPTY_INTR_CLR,
4240                              v_WIN0_EMPTY_INTR_CLR(1));
4241                 dev_warn(lcdc_dev->dev, "win0 empty irq!");
4242         } else if (intr_status & m_WIN1_EMPTY_INTR_STS) {
4243                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN1_EMPTY_INTR_CLR,
4244                              v_WIN1_EMPTY_INTR_CLR(1));
4245                 dev_warn(lcdc_dev->dev, "win1 empty irq!");
4246         } else if (intr_status & m_WIN2_EMPTY_INTR_STS) {
4247                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN2_EMPTY_INTR_CLR,
4248                              v_WIN2_EMPTY_INTR_CLR(1));
4249                 dev_warn(lcdc_dev->dev, "win2 empty irq!");
4250         } else if (intr_status & m_WIN3_EMPTY_INTR_STS) {
4251                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN3_EMPTY_INTR_CLR,
4252                              v_WIN3_EMPTY_INTR_CLR(1));
4253                 dev_warn(lcdc_dev->dev, "win3 empty irq!");
4254         } else if (intr_status & m_HWC_EMPTY_INTR_STS) {
4255                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_HWC_EMPTY_INTR_CLR,
4256                              v_HWC_EMPTY_INTR_CLR(1));
4257                 dev_warn(lcdc_dev->dev, "HWC empty irq!");
4258         } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) {
4259                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_POST_BUF_EMPTY_INTR_CLR,
4260                              v_POST_BUF_EMPTY_INTR_CLR(1));
4261                 dev_warn(lcdc_dev->dev, "post buf empty irq!");
4262         } else if (intr_status & m_PWM_GEN_INTR_STS) {
4263                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_PWM_GEN_INTR_CLR,
4264                              v_PWM_GEN_INTR_CLR(1));
4265                 dev_warn(lcdc_dev->dev, "PWM gen irq!");
4266         }
4267         return 0;
4268 }
4269 #endif
4270
4271 static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id)
4272 {
4273         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
4274         ktime_t timestamp = ktime_get();
4275         u32 intr_status;
4276
4277         intr_status = lcdc_readl(lcdc_dev, INTR_STATUS);
4278
4279         if (intr_status & m_FS_INTR_STS) {
4280                 timestamp = ktime_get();
4281                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_INTR_CLR,
4282                              v_FS_INTR_CLR(1));
4283                 /*if(lcdc_dev->driver.wait_fs){ */
4284                 if (0) {
4285                         spin_lock(&(lcdc_dev->driver.cpl_lock));
4286                         complete(&(lcdc_dev->driver.frame_done));
4287                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
4288                 }
4289 #ifdef CONFIG_DRM_ROCKCHIP
4290                 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
4291 #endif
4292                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4293                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
4294
4295         } else if (intr_status & m_LINE_FLAG0_INTR_STS) {
4296                 lcdc_dev->driver.frame_time.last_framedone_t =
4297                     lcdc_dev->driver.frame_time.framedone_t;
4298                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4299                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG0_INTR_CLR,
4300                              v_LINE_FLAG0_INTR_CLR(1));
4301         } else if (intr_status & m_LINE_FLAG1_INTR_STS) {
4302                 /*line flag1 */
4303                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG1_INTR_CLR,
4304                              v_LINE_FLAG1_INTR_CLR(1));
4305         } else if (intr_status & m_FS_NEW_INTR_STS) {
4306                 /*new frame start */
4307                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_NEW_INTR_CLR,
4308                              v_FS_NEW_INTR_CLR(1));
4309         } else if (intr_status & m_BUS_ERROR_INTR_STS) {
4310                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_BUS_ERROR_INTR_CLR,
4311                              v_BUS_ERROR_INTR_CLR(1));
4312                 dev_warn(lcdc_dev->dev, "bus error!");
4313         }
4314
4315         /* for win empty debug */
4316 #ifdef LCDC_IRQ_EMPTY_DEBUG
4317         rk3368_lcdc_parse_irq(lcdc_dev, intr_status);
4318 #endif
4319         return IRQ_HANDLED;
4320 }
4321
4322 #if defined(CONFIG_PM)
4323 static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
4324 {
4325         return 0;
4326 }
4327
4328 static int rk3368_lcdc_resume(struct platform_device *pdev)
4329 {
4330         return 0;
4331 }
4332 #else
4333 #define rk3368_lcdc_suspend NULL
4334 #define rk3368_lcdc_resume  NULL
4335 #endif
4336
4337 static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4338 {
4339         struct device_node *np = lcdc_dev->dev->of_node;
4340         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4341         int val;
4342
4343         if (of_property_read_u32(np, "rockchip,prop", &val))
4344                 lcdc_dev->prop = PRMRY; /*default set it as primary */
4345         else
4346                 lcdc_dev->prop = val;
4347
4348         if (of_property_read_u32(np, "rockchip,mirror", &val))
4349                 dev_drv->rotate_mode = NO_MIRROR;
4350         else
4351                 dev_drv->rotate_mode = val;
4352
4353         if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4354                 dev_drv->cabc_mode = 0; /* default set close cabc */
4355         else
4356                 dev_drv->cabc_mode = val;
4357
4358         if (of_property_read_u32(np, "rockchip,pwr18", &val))
4359                 /*default set it as 3.xv power supply */
4360                 lcdc_dev->pwr18 = false;
4361         else
4362                 lcdc_dev->pwr18 = (val ? true : false);
4363
4364         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4365                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4366         else
4367                 dev_drv->fb_win_map = val;
4368
4369         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4370                 dev_drv->bcsh.enable = false;
4371         else
4372                 dev_drv->bcsh.enable = (val ? true : false);
4373
4374         if (of_property_read_u32(np, "rockchip,brightness", &val))
4375                 dev_drv->bcsh.brightness = 0xffff;
4376         else
4377                 dev_drv->bcsh.brightness = val;
4378
4379         if (of_property_read_u32(np, "rockchip,contrast", &val))
4380                 dev_drv->bcsh.contrast = 0xffff;
4381         else
4382                 dev_drv->bcsh.contrast = val;
4383
4384         if (of_property_read_u32(np, "rockchip,sat-con", &val))
4385                 dev_drv->bcsh.sat_con = 0xffff;
4386         else
4387                 dev_drv->bcsh.sat_con = val;
4388
4389         if (of_property_read_u32(np, "rockchip,hue", &val)) {
4390                 dev_drv->bcsh.sin_hue = 0xffff;
4391                 dev_drv->bcsh.cos_hue = 0xffff;
4392         } else {
4393                 dev_drv->bcsh.sin_hue = val & 0xff;
4394                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4395         }
4396
4397 #if defined(CONFIG_ROCKCHIP_IOMMU)
4398         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4399                 dev_drv->iommu_enabled = 0;
4400         else
4401                 dev_drv->iommu_enabled = val;
4402 #else
4403         dev_drv->iommu_enabled = 0;
4404 #endif
4405         return 0;
4406 }
4407
4408 static int rk3368_lcdc_probe(struct platform_device *pdev)
4409 {
4410         struct lcdc_device *lcdc_dev = NULL;
4411         struct rk_lcdc_driver *dev_drv;
4412         struct device *dev = &pdev->dev;
4413         struct resource *res;
4414         struct device_node *np = pdev->dev.of_node;
4415         int prop;
4416         int ret = 0;
4417
4418         /*if the primary lcdc has not registered ,the extend
4419            lcdc register later */
4420         of_property_read_u32(np, "rockchip,prop", &prop);
4421         if (prop == EXTEND) {
4422                 if (!is_prmry_rk_lcdc_registered())
4423                         return -EPROBE_DEFER;
4424         }
4425         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
4426         if (!lcdc_dev) {
4427                 dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!");
4428                 return -ENOMEM;
4429         }
4430         platform_set_drvdata(pdev, lcdc_dev);
4431         lcdc_dev->dev = dev;
4432         rk3368_lcdc_parse_dt(lcdc_dev);
4433         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4434         lcdc_dev->reg_phy_base = res->start;
4435         lcdc_dev->len = resource_size(res);
4436         lcdc_dev->regs = devm_ioremap_resource(dev, res);
4437         if (IS_ERR(lcdc_dev->regs))
4438                 return PTR_ERR(lcdc_dev->regs);
4439         else
4440                 dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs);
4441
4442         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4443         if (IS_ERR(lcdc_dev->regsbak))
4444                 return PTR_ERR(lcdc_dev->regsbak);
4445         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4446         lcdc_dev->cabc_lut_addr_base = (lcdc_dev->regs + CABC_GAMMA_LUT_ADDR);
4447         lcdc_dev->grf_base =
4448                 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
4449         if (IS_ERR(lcdc_dev->grf_base)) {
4450                 dev_err(&pdev->dev, "can't find lcdc grf property\n");
4451                 return PTR_ERR(lcdc_dev->grf_base);
4452         }
4453         lcdc_dev->pmugrf_base =
4454                 syscon_regmap_lookup_by_phandle(np, "rockchip,pmugrf");
4455         if (IS_ERR(lcdc_dev->pmugrf_base)) {
4456                 dev_err(&pdev->dev, "can't find lcdc pmu grf property\n");
4457                 return PTR_ERR(lcdc_dev->pmugrf_base);
4458         }
4459         lcdc_dev->id = 0;
4460         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4461         dev_drv = &lcdc_dev->driver;
4462         dev_drv->dev = dev;
4463         dev_drv->prop = prop;
4464         dev_drv->id = lcdc_dev->id;
4465         dev_drv->ops = &lcdc_drv_ops;
4466         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4467         spin_lock_init(&lcdc_dev->reg_lock);
4468
4469         lcdc_dev->irq = platform_get_irq(pdev, 0);
4470         if (lcdc_dev->irq < 0) {
4471                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4472                         lcdc_dev->id);
4473                 return -ENXIO;
4474         }
4475
4476         ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr,
4477                                IRQF_DISABLED | IRQF_SHARED,
4478                                dev_name(dev), lcdc_dev);
4479         if (ret) {
4480                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4481                         lcdc_dev->irq, ret);
4482                 return ret;
4483         }
4484
4485         if (dev_drv->iommu_enabled) {
4486                 if (lcdc_dev->id == 0) {
4487                         strcpy(dev_drv->mmu_dts_name,
4488                                VOPB_IOMMU_COMPATIBLE_NAME);
4489                 } else {
4490                         strcpy(dev_drv->mmu_dts_name,
4491                                VOPL_IOMMU_COMPATIBLE_NAME);
4492                 }
4493         }
4494
4495         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4496         if (ret < 0) {
4497                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4498                 return ret;
4499         }
4500         lcdc_dev->screen = dev_drv->screen0;
4501         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4502                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4503
4504         return 0;
4505 }
4506
4507 static int rk3368_lcdc_remove(struct platform_device *pdev)
4508 {
4509         return 0;
4510 }
4511
4512 static void rk3368_lcdc_shutdown(struct platform_device *pdev)
4513 {
4514         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
4515
4516         rk3368_lcdc_early_suspend(&lcdc_dev->driver);
4517         rk3368_lcdc_deint(lcdc_dev);
4518 }
4519
4520 #if defined(CONFIG_OF)
4521 static const struct of_device_id rk3368_lcdc_dt_ids[] = {
4522         {.compatible = "rockchip,rk3368-lcdc",},
4523         {}
4524 };
4525 #endif
4526
4527 static struct platform_driver rk3368_lcdc_driver = {
4528         .probe = rk3368_lcdc_probe,
4529         .remove = rk3368_lcdc_remove,
4530         .driver = {
4531                    .name = "rk3368-lcdc",
4532                    .owner = THIS_MODULE,
4533                    .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids),
4534                    },
4535         .suspend = rk3368_lcdc_suspend,
4536         .resume = rk3368_lcdc_resume,
4537         .shutdown = rk3368_lcdc_shutdown,
4538 };
4539
4540 static int __init rk3368_lcdc_module_init(void)
4541 {
4542         return platform_driver_register(&rk3368_lcdc_driver);
4543 }
4544
4545 static void __exit rk3368_lcdc_module_exit(void)
4546 {
4547         platform_driver_unregister(&rk3368_lcdc_driver);
4548 }
4549
4550 fs_initcall(rk3368_lcdc_module_init);
4551 module_exit(rk3368_lcdc_module_exit);