drivers/video/rockchip/lcdc/rk3368_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3368_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *Author:hjc<hjc@rock-chips.com>
   6  *This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk3368_lcdc.h"
  39
  40 #if defined(CONFIG_HAS_EARLYSUSPEND)
  41 #include <linux/earlysuspend.h>
  42 #endif
  43 /*#define CONFIG_RK_FPGA 1*/
  44
  45 static int dbg_thresd;
  46 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  47
  48 #define DBG(level, x...) do {                   \
  49         if (unlikely(dbg_thresd >= level))      \
  50                 pr_info(x);\
  51         } while (0)
  52
  53 static struct rk_lcdc_win lcdc_win[] = {
  54         [0] = {
  55                .name = "win0",
  56                .id = 0,
  57                .support_3d = false,
  58                },
  59         [1] = {
  60                .name = "win1",
  61                .id = 1,
  62                .support_3d = false,
  63                },
  64         [2] = {
  65                .name = "win2",
  66                .id = 2,
  67                .support_3d = false,
  68                },
  69         [3] = {
  70                .name = "win3",
  71                .id = 3,
  72                .support_3d = false,
  73                },
  74         [4] = {
  75                .name = "hwc",
  76                .id = 4,
  77                .support_3d = false,
  78                }
  79 };
  80
  81 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
  82
  83 /*#define WAIT_FOR_SYNC 1*/
  84 u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth)
  85 {
  86         u32 vscalednmult;
  87
  88         if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  89                 vscalednmult = 4;
  90         else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  91                 vscalednmult = 2;
  92         else
  93                 vscalednmult = 1;
  94
  95         return vscalednmult;
  96 }
  97
  98 static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv)
  99 {
 100         int i, j;
 101         int __iomem *c;
 102         u32 v, r, g, b;
 103         struct lcdc_device *lcdc_dev =
 104             container_of(dev_drv, struct lcdc_device, driver);
 105         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
 106         lcdc_cfg_done(lcdc_dev);
 107         mdelay(25);
 108         for (i = 0; i < 256; i++) {
 109                 v = dev_drv->cur_screen->dsp_lut[i];
 110                 c = lcdc_dev->dsp_lut_addr_base + (i << 2);
 111                 b = (v & 0xff) << 2;
 112                 g = (v & 0xff00) << 4;
 113                 r = (v & 0xff0000) << 6;
 114                 v = r + g + b;
 115                 for (j = 0; j < 4; j++) {
 116                         writel_relaxed(v, c);
 117                         v += (1 + (1 << 10) + (1 << 20));
 118                         c++;
 119                 }
 120         }
 121         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
 122
 123         return 0;
 124 }
 125
 126 static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 127 {
 128 #ifdef CONFIG_RK_FPGA
 129         lcdc_dev->clk_on = 1;
 130         return 0;
 131 #endif
 132         if (!lcdc_dev->clk_on) {
 133                 clk_prepare_enable(lcdc_dev->hclk);
 134                 clk_prepare_enable(lcdc_dev->dclk);
 135                 clk_prepare_enable(lcdc_dev->aclk);
 136                 clk_prepare_enable(lcdc_dev->pd);
 137                 spin_lock(&lcdc_dev->reg_lock);
 138                 lcdc_dev->clk_on = 1;
 139                 spin_unlock(&lcdc_dev->reg_lock);
 140         }
 141
 142         return 0;
 143 }
 144
 145 static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 146 {
 147 #ifdef CONFIG_RK_FPGA
 148         lcdc_dev->clk_on = 0;
 149         return 0;
 150 #endif
 151         if (lcdc_dev->clk_on) {
 152                 spin_lock(&lcdc_dev->reg_lock);
 153                 lcdc_dev->clk_on = 0;
 154                 spin_unlock(&lcdc_dev->reg_lock);
 155                 mdelay(25);
 156                 clk_disable_unprepare(lcdc_dev->dclk);
 157                 clk_disable_unprepare(lcdc_dev->hclk);
 158                 clk_disable_unprepare(lcdc_dev->aclk);
 159                 clk_disable_unprepare(lcdc_dev->pd);
 160         }
 161
 162         return 0;
 163 }
 164
 165 static int rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 166 {
 167         u32 mask, val;
 168
 169         spin_lock(&lcdc_dev->reg_lock);
 170         if (likely(lcdc_dev->clk_on)) {
 171                 mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN |
 172                     m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN |
 173                     m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN |
 174                     m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
 175                     m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
 176                     m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
 177                     m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN;
 178                 val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) |
 179                     v_ADDR_SAME_INTR_EN(0) |
 180                     v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) |
 181                     v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) |
 182                     v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) |
 183                     v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) |
 184                     v_POST_BUF_EMPTY_INTR_EN(0) |
 185                     v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0);
 186                 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
 187
 188                 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR |
 189                     m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
 190                     m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR |
 191                     m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
 192                     m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
 193                     m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
 194                     m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR;
 195                 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
 196                     v_ADDR_SAME_INTR_CLR(1) |
 197                     v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) |
 198                     v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) |
 199                     v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) |
 200                     v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) |
 201                     v_POST_BUF_EMPTY_INTR_CLR(1) |
 202                     v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1);
 203                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
 204                 lcdc_cfg_done(lcdc_dev);
 205                 spin_unlock(&lcdc_dev->reg_lock);
 206         } else {
 207                 spin_unlock(&lcdc_dev->reg_lock);
 208         }
 209         mdelay(1);
 210         return 0;
 211 }
 212
 213 static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
 214 {
 215         struct lcdc_device *lcdc_dev =
 216             container_of(dev_drv, struct lcdc_device, driver);
 217         int *cbase = (int *)lcdc_dev->regs;
 218         int *regsbak = (int *)lcdc_dev->regsbak;
 219         int i, j, val;
 220         char dbg_message[30];
 221         char buf[10];
 222
 223         pr_info("lcd back up reg:\n");
 224         memset(dbg_message, 0, sizeof(dbg_message));
 225         memset(buf, 0, sizeof(buf));
 226         for (i = 0; i <= (0x200 >> 4); i++) {
 227                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 228                 for (j = 0; j < 4; j++) {
 229                         val = sprintf(buf, "%08x  ", *(regsbak + i * 4 + j));
 230                         strcat(dbg_message, buf);
 231                 }
 232                 pr_info("%s\n", dbg_message);
 233                 memset(dbg_message, 0, sizeof(dbg_message));
 234                 memset(buf, 0, sizeof(buf));
 235         }
 236
 237         pr_info("lcdc reg:\n");
 238         for (i = 0; i <= (0x200 >> 4); i++) {
 239                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 240                 for (j = 0; j < 4; j++) {
 241                         sprintf(buf, "%08x  ",
 242                                 readl_relaxed(cbase + i * 4 + j));
 243                         strcat(dbg_message, buf);
 244                 }
 245                 pr_info("%s\n", dbg_message);
 246                 memset(dbg_message, 0, sizeof(dbg_message));
 247                 memset(buf, 0, sizeof(buf));
 248         }
 249
 250         return 0;
 251 }
 252
 253 #define WIN_EN(id)              \
 254 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en)       \
 255 { \
 256         u32 msk, val;                                                   \
 257         spin_lock(&lcdc_dev->reg_lock);                                 \
 258         msk =  m_WIN##id##_EN;                                          \
 259         val  =  v_WIN##id##_EN(en);                                     \
 260         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);              \
 261         lcdc_cfg_done(lcdc_dev);                                        \
 262         val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);            \
 263         while (val !=  (!!en))  {                                       \
 264                 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);    \
 265         }                                                               \
 266         spin_unlock(&lcdc_dev->reg_lock);                               \
 267         return 0;                                                       \
 268 }
 269
 270 WIN_EN(0);
 271 WIN_EN(1);
 272 WIN_EN(2);
 273 WIN_EN(3);
 274 /*enable/disable win directly*/
 275 static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv,
 276                                      int win_id, int en)
 277 {
 278         struct lcdc_device *lcdc_dev =
 279             container_of(drv, struct lcdc_device, driver);
 280         if (win_id == 0)
 281                 win0_enable(lcdc_dev, en);
 282         else if (win_id == 1)
 283                 win1_enable(lcdc_dev, en);
 284         else if (win_id == 2)
 285                 win2_enable(lcdc_dev, en);
 286         else if (win_id == 3)
 287                 win3_enable(lcdc_dev, en);
 288         else
 289                 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
 290         return 0;
 291 }
 292
 293 #define SET_WIN_ADDR(id) \
 294 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
 295 {                                                       \
 296         u32 msk, val;                                   \
 297         spin_lock(&lcdc_dev->reg_lock);                 \
 298         lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr);        \
 299         msk =  m_WIN##id##_EN;                          \
 300         val  =  v_WIN0_EN(1);                           \
 301         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);      \
 302         lcdc_cfg_done(lcdc_dev);                        \
 303         spin_unlock(&lcdc_dev->reg_lock);               \
 304         return 0;                                       \
 305 }
 306
 307 SET_WIN_ADDR(0);
 308 SET_WIN_ADDR(1);
 309 int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
 310                                     int win_id, u32 addr)
 311 {
 312         struct lcdc_device *lcdc_dev =
 313             container_of(dev_drv, struct lcdc_device, driver);
 314         if (win_id == 0)
 315                 set_win0_addr(lcdc_dev, addr);
 316         else
 317                 set_win1_addr(lcdc_dev, addr);
 318
 319         return 0;
 320 }
 321
 322 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 323 {
 324         int reg = 0;
 325         u32 val = 0;
 326         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 327         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 328         u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 329         u32 st_x, st_y;
 330         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 331
 332         spin_lock(&lcdc_dev->reg_lock);
 333         for (reg = 0; reg < FRC_LOWER11_1; reg += 4) {
 334                 val = lcdc_readl_backup(lcdc_dev, reg);
 335                 switch (reg) {
 336                 case WIN0_ACT_INFO:
 337                         win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1;
 338                         win0->area[0].yact =
 339                             ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
 340                         break;
 341                 case WIN0_DSP_INFO:
 342                         win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1;
 343                         win0->area[0].ysize =
 344                             ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
 345                         break;
 346                 case WIN0_DSP_ST:
 347                         st_x = val & m_WIN0_DSP_XST;
 348                         st_y = (val & m_WIN0_DSP_YST) >> 16;
 349                         win0->area[0].xpos = st_x - h_pw_bp;
 350                         win0->area[0].ypos = st_y - v_pw_bp;
 351                         break;
 352                 case WIN0_CTRL0:
 353                         win0->state = val & m_WIN0_EN;
 354                         win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1;
 355                         win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
 356                         win0->area[0].format = win0->area[0].fmt_cfg;
 357                         break;
 358                 case WIN0_VIR:
 359                         win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE;
 360                         win0->area[0].uv_vir_stride =
 361                             (val & m_WIN0_VIR_STRIDE_UV) >> 16;
 362                         if (win0->area[0].format == ARGB888)
 363                                 win0->area[0].xvir = win0->area[0].y_vir_stride;
 364                         else if (win0->area[0].format == RGB888)
 365                                 win0->area[0].xvir =
 366                                     win0->area[0].y_vir_stride * 4 / 3;
 367                         else if (win0->area[0].format == RGB565)
 368                                 win0->area[0].xvir =
 369                                     2 * win0->area[0].y_vir_stride;
 370                         else    /* YUV */
 371                                 win0->area[0].xvir =
 372                                     4 * win0->area[0].y_vir_stride;
 373                         break;
 374                 case WIN0_YRGB_MST:
 375                         win0->area[0].smem_start = val;
 376                         break;
 377                 case WIN0_CBR_MST:
 378                         win0->area[0].cbr_start = val;
 379                         break;
 380                 default:
 381                         break;
 382                 }
 383         }
 384         spin_unlock(&lcdc_dev->reg_lock);
 385 }
 386
 387 /********do basic init*********/
 388 static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 389 {
 390         u32 mask, val;
 391         struct lcdc_device *lcdc_dev =
 392             container_of(dev_drv, struct lcdc_device, driver);
 393         if (lcdc_dev->pre_init)
 394                 return 0;
 395
 396         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 397         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 398         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 399         lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
 400
 401         if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||
 402             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 403                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 404                         lcdc_dev->id);
 405         }
 406
 407         rk_disp_pwr_enable(dev_drv);
 408         rk3368_lcdc_clk_enable(lcdc_dev);
 409
 410         /*backup reg config at uboot */
 411         lcdc_read_reg_defalut_cfg(lcdc_dev);
 412         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_0, 0x15110903);
 413         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_1, 0x00030911);
 414         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_0, 0x1a150b04);
 415         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_1, 0x00040b15);
 416         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_0, 0x15110903);
 417         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_1, 0x00030911);
 418
 419         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 420         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 421         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696);
 422         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969);
 423         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 424         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 425
 426         mask = m_AUTO_GATING_EN;
 427         val = v_AUTO_GATING_EN(0);
 428         lcdc_cfg_done(lcdc_dev);
 429         /*disable win0 to workaround iommu pagefault */
 430         /*if (dev_drv->iommu_enabled) */
 431         /*      win0_enable(lcdc_dev, 0); */
 432         lcdc_dev->pre_init = true;
 433
 434         return 0;
 435 }
 436
 437 static void rk3368_lcdc_deint(struct lcdc_device *lcdc_dev)
 438 {
 439         rk3368_lcdc_disable_irq(lcdc_dev);
 440         spin_lock(&lcdc_dev->reg_lock);
 441         if (likely(lcdc_dev->clk_on)) {
 442                 lcdc_dev->clk_on = 0;
 443                 lcdc_set_bit(lcdc_dev, SYS_CTRL, m_STANDBY_EN);
 444                 lcdc_cfg_done(lcdc_dev);
 445                 spin_unlock(&lcdc_dev->reg_lock);
 446         } else {
 447                 spin_unlock(&lcdc_dev->reg_lock);
 448         }
 449         mdelay(1);
 450 }
 451
 452 static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
 453 {
 454         struct lcdc_device *lcdc_dev =
 455             container_of(dev_drv, struct lcdc_device, driver);
 456         struct rk_screen *screen = dev_drv->cur_screen;
 457         u16 x_res = screen->mode.xres;
 458         u16 y_res = screen->mode.yres;
 459         u32 mask, val;
 460         u16 h_total, v_total;
 461         u16 post_hsd_en, post_vsd_en;
 462         u16 post_dsp_hact_st, post_dsp_hact_end;
 463         u16 post_dsp_vact_st, post_dsp_vact_end;
 464         u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
 465         u16 post_h_fac, post_v_fac;
 466
 467         h_total = screen->mode.hsync_len + screen->mode.left_margin +
 468             x_res + screen->mode.right_margin;
 469         v_total = screen->mode.vsync_len + screen->mode.upper_margin +
 470             y_res + screen->mode.lower_margin;
 471
 472         if (screen->post_dsp_stx + screen->post_xsize > x_res) {
 473                 dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
 474                          screen->post_dsp_stx, screen->post_xsize, x_res);
 475                 screen->post_dsp_stx = x_res - screen->post_xsize;
 476         }
 477         if (screen->x_mirror == 0) {
 478                 post_dsp_hact_st = screen->post_dsp_stx +
 479                     screen->mode.hsync_len + screen->mode.left_margin;
 480                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 481         } else {
 482                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 483                     screen->post_dsp_stx;
 484                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 485         }
 486         if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
 487                 post_hsd_en = 1;
 488                 post_h_fac =
 489                     GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
 490         } else {
 491                 post_hsd_en = 0;
 492                 post_h_fac = 0x1000;
 493         }
 494
 495         if (screen->post_dsp_sty + screen->post_ysize > y_res) {
 496                 dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
 497                          screen->post_dsp_sty, screen->post_ysize, y_res);
 498                 screen->post_dsp_sty = y_res - screen->post_ysize;
 499         }
 500
 501         if (screen->y_mirror == 0) {
 502                 post_dsp_vact_st = screen->post_dsp_sty +
 503                     screen->mode.vsync_len + screen->mode.upper_margin;
 504                 post_dsp_vact_end = post_dsp_vact_st + screen->post_ysize;
 505         } else {
 506                 post_dsp_vact_end = v_total - screen->mode.lower_margin -
 507                     screen->post_dsp_sty;
 508                 post_dsp_vact_st = post_dsp_vact_end - screen->post_ysize;
 509         }
 510         if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
 511                 post_vsd_en = 1;
 512                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
 513                                                       screen->post_ysize);
 514         } else {
 515                 post_vsd_en = 0;
 516                 post_v_fac = 0x1000;
 517         }
 518
 519         if (screen->interlace == 1) {
 520                 post_dsp_vact_st_f1 = v_total + post_dsp_vact_st;
 521                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 + screen->post_ysize;
 522         } else {
 523                 post_dsp_vact_st_f1 = 0;
 524                 post_dsp_vact_end_f1 = 0;
 525         }
 526         DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
 527             screen->post_xsize, screen->post_ysize, screen->xpos);
 528         DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 529             screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
 530         mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
 531         val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
 532             v_DSP_HACT_ST_POST(post_dsp_hact_st);
 533         lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
 534
 535         mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
 536         val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
 537             v_DSP_VACT_ST_POST(post_dsp_vact_st);
 538         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
 539
 540         mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
 541         val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
 542             v_POST_VS_FACTOR_YRGB(post_v_fac);
 543         lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
 544
 545         mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
 546         val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
 547             v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
 548         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
 549
 550         mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
 551         val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
 552         lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
 553         return 0;
 554 }
 555
 556 static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 557 {
 558         struct lcdc_device *lcdc_dev =
 559             container_of(dev_drv, struct lcdc_device, driver);
 560         struct rk_lcdc_win *win;
 561         u32 colorkey_r, colorkey_g, colorkey_b;
 562         int i, key_val;
 563
 564         for (i = 0; i < 4; i++) {
 565                 win = dev_drv->win[i];
 566                 key_val = win->color_key_val;
 567                 colorkey_r = (key_val & 0xff) << 2;
 568                 colorkey_g = ((key_val >> 8) & 0xff) << 12;
 569                 colorkey_b = ((key_val >> 16) & 0xff) << 22;
 570                 /*color key dither 565/888->aaa */
 571                 key_val = colorkey_r | colorkey_g | colorkey_b;
 572                 switch (i) {
 573                 case 0:
 574                         lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
 575                         break;
 576                 case 1:
 577                         lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
 578                         break;
 579                 case 2:
 580                         lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
 581                         break;
 582                 case 3:
 583                         lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
 584                         break;
 585                 default:
 586                         pr_info("%s:un support win num:%d\n",
 587                                 __func__, i);
 588                         break;
 589                 }
 590         }
 591         return 0;
 592 }
 593
 594 static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
 595 {
 596         struct lcdc_device *lcdc_dev =
 597             container_of(dev_drv, struct lcdc_device, driver);
 598         struct rk_lcdc_win *win = dev_drv->win[win_id];
 599         struct alpha_config alpha_config;
 600         u32 mask, val;
 601         int ppixel_alpha = 0, global_alpha = 0, i;
 602         u32 src_alpha_ctl, dst_alpha_ctl;
 603
 604         for (i = 0; i < win->area_num; i++) {
 605                 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
 606                                  (win->area[i].format == ABGR888)) ? 1 : 0;
 607         }
 608         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 609         alpha_config.src_global_alpha_val = win->g_alpha_val;
 610         win->alpha_mode = AB_SRC_OVER;
 611         /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
 612            __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,
 613            global_alpha); */
 614         switch (win->alpha_mode) {
 615         case AB_USER_DEFINE:
 616                 break;
 617         case AB_CLEAR:
 618                 alpha_config.src_factor_mode = AA_ZERO;
 619                 alpha_config.dst_factor_mode = AA_ZERO;
 620                 break;
 621         case AB_SRC:
 622                 alpha_config.src_factor_mode = AA_ONE;
 623                 alpha_config.dst_factor_mode = AA_ZERO;
 624                 break;
 625         case AB_DST:
 626                 alpha_config.src_factor_mode = AA_ZERO;
 627                 alpha_config.dst_factor_mode = AA_ONE;
 628                 break;
 629         case AB_SRC_OVER:
 630                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 631                 if (global_alpha)
 632                         alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 633                 else
 634                         alpha_config.src_factor_mode = AA_ONE;
 635                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 636                 break;
 637         case AB_DST_OVER:
 638                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 639                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 640                 alpha_config.dst_factor_mode = AA_ONE;
 641                 break;
 642         case AB_SRC_IN:
 643                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 644                 alpha_config.src_factor_mode = AA_SRC;
 645                 alpha_config.dst_factor_mode = AA_ZERO;
 646                 break;
 647         case AB_DST_IN:
 648                 alpha_config.src_factor_mode = AA_ZERO;
 649                 alpha_config.dst_factor_mode = AA_SRC;
 650                 break;
 651         case AB_SRC_OUT:
 652                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 653                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 654                 alpha_config.dst_factor_mode = AA_ZERO;
 655                 break;
 656         case AB_DST_OUT:
 657                 alpha_config.src_factor_mode = AA_ZERO;
 658                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 659                 break;
 660         case AB_SRC_ATOP:
 661                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 662                 alpha_config.src_factor_mode = AA_SRC;
 663                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 664                 break;
 665         case AB_DST_ATOP:
 666                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 667                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 668                 alpha_config.dst_factor_mode = AA_SRC;
 669                 break;
 670         case XOR:
 671                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 672                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 673                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 674                 break;
 675         case AB_SRC_OVER_GLOBAL:
 676                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 677                 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
 678                 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 679                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 680                 break;
 681         default:
 682                 pr_err("alpha mode error\n");
 683                 break;
 684         }
 685         if ((ppixel_alpha == 1) && (global_alpha == 1))
 686                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 687         else if (ppixel_alpha == 1)
 688                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 689         else if (global_alpha == 1)
 690                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 691         else
 692                 dev_warn(lcdc_dev->dev, "alpha_en should be 0\n");
 693         alpha_config.src_alpha_mode = AA_STRAIGHT;
 694         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 695
 696         switch (win_id) {
 697         case 0:
 698                 src_alpha_ctl = 0x60;
 699                 dst_alpha_ctl = 0x64;
 700                 break;
 701         case 1:
 702                 src_alpha_ctl = 0xa0;
 703                 dst_alpha_ctl = 0xa4;
 704                 break;
 705         case 2:
 706                 src_alpha_ctl = 0xdc;
 707                 dst_alpha_ctl = 0xec;
 708                 break;
 709         case 3:
 710                 src_alpha_ctl = 0x12c;
 711                 dst_alpha_ctl = 0x13c;
 712                 break;
 713         case 4:
 714                 src_alpha_ctl = 0x160;
 715                 dst_alpha_ctl = 0x164;
 716                 break;
 717         }
 718         mask = m_WIN0_DST_FACTOR_M0;
 719         val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
 720         lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
 721         mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
 722             m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
 723             m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 |
 724             m_WIN0_SRC_GLOBAL_ALPHA;
 725         val = v_WIN0_SRC_ALPHA_EN(1) |
 726             v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
 727             v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
 728             v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
 729             v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
 730             v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
 731             v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 732         lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
 733
 734         return 0;
 735 }
 736
 737 static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num)
 738 {
 739         struct rk_lcdc_win_area area_temp;
 740         int i, j;
 741
 742         for (i = 0; i < area_num; i++) {
 743                 for (j = i + 1; j < area_num; j++) {
 744                         if (win->area[i].dsp_stx >  win->area[j].dsp_stx) {
 745                                 memcpy(&area_temp, &win->area[i],
 746                                        sizeof(struct rk_lcdc_win_area));
 747                                 memcpy(&win->area[i], &win->area[j],
 748                                        sizeof(struct rk_lcdc_win_area));
 749                                 memcpy(&win->area[j], &area_temp,
 750                                        sizeof(struct rk_lcdc_win_area));
 751                         }
 752                 }
 753         }
 754
 755         return 0;
 756 }
 757
 758 static int rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num)
 759 {
 760         struct rk_lcdc_win_area area_temp;
 761
 762         switch (area_num) {
 763         case 2:
 764                 area_temp = win->area[0];
 765                 win->area[0] = win->area[1];
 766                 win->area[1] = area_temp;
 767                 break;
 768         case 3:
 769                 area_temp = win->area[0];
 770                 win->area[0] = win->area[2];
 771                 win->area[2] = area_temp;
 772                 break;
 773         case 4:
 774                 area_temp = win->area[0];
 775                 win->area[0] = win->area[3];
 776                 win->area[3] = area_temp;
 777
 778                 area_temp = win->area[1];
 779                 win->area[1] = win->area[2];
 780                 win->area[2] = area_temp;
 781                 break;
 782         default:
 783                 pr_info("un supported area num!\n");
 784                 break;
 785         }
 786         return 0;
 787 }
 788
 789 static int rk3368_win_area_check_var(int win_id, int area_num,
 790                                      struct rk_lcdc_win_area *area_pre,
 791                                      struct rk_lcdc_win_area *area_now)
 792 {
 793         if ((area_pre->xpos > area_now->xpos) ||
 794             ((area_pre->xpos + area_pre->xsize > area_now->xpos) &&
 795              (area_pre->ypos + area_pre->ysize > area_now->ypos))) {
 796                 area_now->state = 0;
 797                 pr_err("win[%d]:\n"
 798                        "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n"
 799                        "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n",
 800                        win_id,
 801                        area_num - 1, area_pre->xpos, area_pre->xsize,
 802                        area_pre->ypos, area_pre->ysize,
 803                        area_num, area_now->xpos, area_now->xsize,
 804                        area_now->ypos, area_now->ysize);
 805                 return -EINVAL;
 806         }
 807         return 0;
 808 }
 809
 810 static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv)
 811 {
 812         struct lcdc_device *lcdc_dev =
 813             container_of(dev_drv, struct lcdc_device, driver);
 814         u32 val, i;
 815
 816         for (i = 0; i < 100; i++) {
 817                 val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0);
 818                 val &= m_DBG_IFBDC_IDLE;
 819                 if (val)
 820                         continue;
 821                 else
 822                         mdelay(10);
 823         };
 824         return val;
 825 }
 826
 827 static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
 828 {
 829         struct lcdc_device *lcdc_dev =
 830             container_of(dev_drv, struct lcdc_device, driver);
 831         struct rk_lcdc_win *win = dev_drv->win[win_id];
 832         u32 mask, val;
 833
 834         mask = m_IFBDC_CTRL_FBDC_EN | m_IFBDC_CTRL_FBDC_COR_EN |
 835             m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE |
 836             m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO;
 837         val = v_IFBDC_CTRL_FBDC_EN(win->area[0].fbdc_en) |
 838             v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) |
 839             v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) |
 840             v_IFBDC_CTRL_FBDC_ROTATION_MODE(win->mirror_en << 1) |
 841             v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) |
 842             v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio);
 843         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
 844
 845         mask = m_IFBDC_TILES_NUM;
 846         val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles);
 847         lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val);
 848
 849         mask = m_IFBDC_BASE_ADDR;
 850         val = v_IFBDC_BASE_ADDR(win->area[0].y_addr);
 851         lcdc_msk_reg(lcdc_dev, IFBDC_BASE_ADDR, mask, val);
 852
 853         mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT;
 854         val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) |
 855             v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height);
 856         lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val);
 857
 858         mask = m_IFBDC_CMP_INDEX_INIT;
 859         val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init);
 860         lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val);
 861
 862         mask = m_IFBDC_MB_VIR_WIDTH;
 863         val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width);
 864         lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val);
 865
 866         return 0;
 867 }
 868
 869 static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id)
 870 {
 871         struct lcdc_device *lcdc_dev =
 872             container_of(dev_drv, struct lcdc_device, driver);
 873         struct rk_lcdc_win *win = dev_drv->win[win_id];
 874         u8 fbdc_dsp_width_ratio;
 875         u16 fbdc_mb_vir_width, fbdc_mb_vir_height;
 876         u16 fbdc_mb_width, fbdc_mb_height;
 877         u16 fbdc_mb_xst, fbdc_mb_yst, fbdc_num_tiles;
 878         u16 fbdc_cmp_index_init;
 879         u8 mb_w_size, mb_h_size;
 880         struct rk_screen *screen = dev_drv->cur_screen;
 881
 882         if (screen->mode.flag == FB_VMODE_INTERLACED) {
 883                 dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n");
 884                 return 0;
 885         }
 886
 887         switch (win->area[0].fmt_cfg) {
 888         case VOP_FORMAT_ARGB888:
 889                 fbdc_dsp_width_ratio = 0;
 890                 mb_w_size = 16;
 891                 break;
 892         case VOP_FORMAT_RGB888:
 893                 fbdc_dsp_width_ratio = 0;
 894                 mb_w_size = 16;
 895                 break;
 896         case VOP_FORMAT_RGB565:
 897                 mb_w_size = 32;
 898                 break;
 899         default:
 900                 dev_err(lcdc_dev->dev,
 901                         "in fbdc mode,unsupport fmt:%d!\n",
 902                         win->area[0].fmt_cfg);
 903                 break;
 904         }
 905         mb_h_size = 4;
 906
 907         /*macro block xvir and yvir */
 908         if ((win->area[0].xvir % mb_w_size == 0) &&
 909             (win->area[0].yvir % mb_h_size == 0)) {
 910                 fbdc_mb_vir_width = win->area[0].xvir / mb_w_size;
 911                 fbdc_mb_vir_height = win->area[0].yvir / mb_h_size;
 912         } else {
 913                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 914                 pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n",
 915                        win->area[0].xvir, win->area[0].yvir,
 916                        mb_w_size, mb_h_size);
 917         }
 918         /*macro block xact and yact */
 919         if ((win->area[0].xact % mb_w_size == 0) &&
 920             (win->area[0].yact % mb_h_size == 0)) {
 921                 fbdc_mb_width = win->area[0].xact / mb_w_size;
 922                 fbdc_mb_height = win->area[0].yact / mb_h_size;
 923         } else {
 924                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 925                 pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n",
 926                        win->area[0].xact, win->area[0].yact,
 927                        mb_w_size, mb_h_size);
 928         }
 929         /*macro block xoff and yoff */
 930         if ((win->area[0].xoff % mb_w_size == 0) &&
 931             (win->area[0].yoff % mb_h_size == 0)) {
 932                 fbdc_mb_xst = win->area[0].xoff / mb_w_size;
 933                 fbdc_mb_yst = win->area[0].yoff / mb_h_size;
 934         } else {
 935                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 936                 pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n",
 937                        win->area[0].xoff, win->area[0].yoff,
 938                        mb_w_size, mb_h_size);
 939         }
 940
 941         /*FBDC tiles */
 942         fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height;
 943
 944         /*
 945            switch (fbdc_rotation_mode)  {
 946            case FBDC_ROT_NONE:
 947            fbdc_cmp_index_init =
 948            (fbdc_mb_yst*fbdc_mb_vir_width) +  fbdc_mb_xst;
 949            break;
 950            case FBDC_X_MIRROR:
 951            fbdc_cmp_index_init =
 952            (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+
 953            (fbdc_mb_width-1));
 954            break;
 955            case FBDC_Y_MIRROR:
 956            fbdc_cmp_index_init =
 957            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width)  +
 958            fbdc_mb_xst;
 959            break;
 960            case FBDC_ROT_180:
 961            fbdc_cmp_index_init =
 962            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
 963            (fbdc_mb_xst+(fbdc_mb_width-1));
 964            break;
 965            }
 966          */
 967         if ((win->mirror_en) && ((win_id == 2) || (win_id == 3))) {
 968                 fbdc_cmp_index_init =
 969                     ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) +
 970                     (fbdc_mb_xst + (fbdc_mb_width - 1));
 971         } else {
 972                 fbdc_cmp_index_init =
 973                     (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst;
 974         }
 975         /*fbdc fmt maybe need to change*/
 976         win->area[0].fbdc_fmt_cfg = win->area[0].fbdc_data_format;
 977         win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio;
 978         win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width;
 979         win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height;
 980         win->area[0].fbdc_mb_width = fbdc_mb_width;
 981         win->area[0].fbdc_mb_height = fbdc_mb_height;
 982         win->area[0].fbdc_mb_xst = fbdc_mb_xst;
 983         win->area[0].fbdc_mb_yst = fbdc_mb_yst;
 984         win->area[0].fbdc_num_tiles = fbdc_num_tiles;
 985         win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init;
 986
 987         return 0;
 988 }
 989
 990 static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev,
 991                                  struct rk_lcdc_win *win)
 992 {
 993         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
 994         struct rk_screen *screen = dev_drv->cur_screen;
 995
 996         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
 997                 switch (win->area[0].fmt_cfg) {
 998                 case VOP_FORMAT_ARGB888:
 999                 case VOP_FORMAT_RGB888:
1000                 case VOP_FORMAT_RGB565:
1001                         if ((screen->mode.xres < 1280) &&
1002                             (screen->mode.yres < 720)) {
1003                                 win->csc_mode = VOP_R2Y_CSC_BT601;
1004                         } else {
1005                                 win->csc_mode = VOP_R2Y_CSC_BT709;
1006                         }
1007                         break;
1008                 default:
1009                         break;
1010                 }
1011         } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
1012                 switch (win->area[0].fmt_cfg) {
1013                 case VOP_FORMAT_YCBCR420:
1014                         if ((win->id == 0) || (win->id == 1))
1015                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
1016                         break;
1017                 default:
1018                         break;
1019                 }
1020         }
1021 }
1022
1023 static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1024 {
1025         struct lcdc_device *lcdc_dev =
1026             container_of(dev_drv, struct lcdc_device, driver);
1027         struct rk_lcdc_win *win = dev_drv->win[win_id];
1028         unsigned int mask, val, off;
1029
1030         off = win_id * 0x40;
1031         /*if(win->win_lb_mode == 5)
1032            win->win_lb_mode = 4;
1033            for rk3288 to fix hw bug? */
1034
1035         if (win->state == 1) {
1036                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1037                 if (win->area[0].fbdc_en)
1038                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1039                 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
1040                     m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR |
1041                     m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE;
1042                 val = v_WIN0_EN(win->state) |
1043                     v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1044                     v_WIN0_FMT_10(win->fmt_10) |
1045                     v_WIN0_LB_MODE(win->win_lb_mode) |
1046                     v_WIN0_RB_SWAP(win->area[0].swap_rb) |
1047                     v_WIN0_X_MIRROR(win->mirror_en) |
1048                     v_WIN0_Y_MIRROR(win->mirror_en) |
1049                     v_WIN0_CSC_MODE(win->csc_mode);
1050                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1051
1052                 mask = m_WIN0_BIC_COE_SEL |
1053                     m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
1054                     m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
1055                     m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
1056                     m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
1057                     m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
1058                     m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
1059                     m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
1060                 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1061                     v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1062                     v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1063                     v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1064                     v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1065                     v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1066                     v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1067                     v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1068                     v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1069                     v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1070                     v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1071                     v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1072                     v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1073                     v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1074                     v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1075                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val);
1076                 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1077                     v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1078                 lcdc_writel(lcdc_dev, WIN0_VIR + off, val);
1079                 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off,
1080                                 win->area[0].y_addr);
1081                    lcdc_writel(lcdc_dev, WIN0_CBR_MST+off,
1082                                 win->area[0].uv_addr); */
1083                 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
1084                     v_WIN0_ACT_HEIGHT(win->area[0].yact);
1085                 lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val);
1086
1087                 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
1088                     v_WIN0_DSP_HEIGHT(win->area[0].ysize);
1089                 lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val);
1090
1091                 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
1092                     v_WIN0_DSP_YST(win->area[0].dsp_sty);
1093                 lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val);
1094
1095                 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1096                     v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1097                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1098
1099                 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1100                     v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1101                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val);
1102                 if (win->alpha_en == 1) {
1103                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1104                 } else {
1105                         mask = m_WIN0_SRC_ALPHA_EN;
1106                         val = v_WIN0_SRC_ALPHA_EN(0);
1107                         lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off,
1108                                      mask, val);
1109                 }
1110         } else {
1111                 mask = m_WIN0_EN;
1112                 val = v_WIN0_EN(win->state);
1113                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1114         }
1115         return 0;
1116 }
1117
1118 static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1119 {
1120         struct lcdc_device *lcdc_dev =
1121             container_of(dev_drv, struct lcdc_device, driver);
1122         struct rk_lcdc_win *win = dev_drv->win[win_id];
1123         struct rk_screen *screen = dev_drv->cur_screen;
1124         unsigned int mask, val, off;
1125
1126         off = (win_id - 2) * 0x50;
1127         rk3368_lcdc_area_xst(win, win->area_num);
1128         if (((screen->y_mirror == 1) || (win->mirror_en)) &&
1129             (win->area_num > 1)) {
1130                 rk3368_lcdc_area_swap(win, win->area_num);
1131         }
1132
1133         if (win->state == 1) {
1134                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1135                 if (win->area[0].fbdc_en)
1136                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1137
1138                 mask = m_WIN2_EN | m_WIN2_CSC_MODE;
1139                 val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode);
1140                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1141                 /*area 0 */
1142                 if (win->area[0].state == 1) {
1143                         mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 |
1144                             m_WIN2_RB_SWAP0;
1145                         val = v_WIN2_MST0_EN(win->area[0].state) |
1146                             v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1147                             v_WIN2_RB_SWAP0(win->area[0].swap_rb);
1148                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1149
1150                         mask = m_WIN2_VIR_STRIDE0;
1151                         val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1152                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1153
1154                         /*lcdc_writel(lcdc_dev,WIN2_MST0+off,
1155                            win->area[0].y_addr); */
1156                         val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1157                             v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1158                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val);
1159                         val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1160                             v_WIN2_DSP_YST0(win->area[0].dsp_sty);
1161                         lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val);
1162                 } else {
1163                         mask = m_WIN2_MST0_EN;
1164                         val = v_WIN2_MST0_EN(0);
1165                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1166                 }
1167                 /*area 1 */
1168                 if (win->area[1].state == 1) {
1169                         rk3368_win_area_check_var(win_id, 1,
1170                                                   &win->area[0], &win->area[1]);
1171
1172                         mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 |
1173                             m_WIN2_RB_SWAP1;
1174                         val = v_WIN2_MST1_EN(win->area[1].state) |
1175                             v_WIN2_DATA_FMT0(win->area[1].fmt_cfg) |
1176                             v_WIN2_RB_SWAP0(win->area[1].swap_rb);
1177                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1178
1179                         mask = m_WIN2_VIR_STRIDE1;
1180                         val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1181                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1182
1183                         /*lcdc_writel(lcdc_dev,WIN2_MST1+off,
1184                            win->area[1].y_addr); */
1185                         val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1186                             v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1187                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val);
1188                         val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1189                             v_WIN2_DSP_YST1(win->area[1].dsp_sty);
1190                         lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val);
1191                 } else {
1192                         mask = m_WIN2_MST1_EN;
1193                         val = v_WIN2_MST1_EN(0);
1194                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1195                 }
1196                 /*area 2 */
1197                 if (win->area[2].state == 1) {
1198                         rk3368_win_area_check_var(win_id, 2,
1199                                                   &win->area[1], &win->area[2]);
1200
1201                         mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 |
1202                             m_WIN2_RB_SWAP2;
1203                         val = v_WIN2_MST2_EN(win->area[2].state) |
1204                             v_WIN2_DATA_FMT0(win->area[2].fmt_cfg) |
1205                             v_WIN2_RB_SWAP0(win->area[2].swap_rb);
1206                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1207
1208                         mask = m_WIN2_VIR_STRIDE2;
1209                         val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1210                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1211
1212                         /*lcdc_writel(lcdc_dev,WIN2_MST2+off,
1213                            win->area[2].y_addr); */
1214                         val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1215                             v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1216                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val);
1217                         val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1218                             v_WIN2_DSP_YST2(win->area[2].dsp_sty);
1219                         lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val);
1220                 } else {
1221                         mask = m_WIN2_MST2_EN;
1222                         val = v_WIN2_MST2_EN(0);
1223                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1224                 }
1225                 /*area 3 */
1226                 if (win->area[3].state == 1) {
1227                         rk3368_win_area_check_var(win_id, 3,
1228                                                   &win->area[2], &win->area[3]);
1229
1230                         mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 |
1231                             m_WIN2_RB_SWAP3;
1232                         val = v_WIN2_MST3_EN(win->area[3].state) |
1233                             v_WIN2_DATA_FMT0(win->area[3].fmt_cfg) |
1234                             v_WIN2_RB_SWAP0(win->area[3].swap_rb);
1235                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1236
1237                         mask = m_WIN2_VIR_STRIDE3;
1238                         val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1239                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1240
1241                         /*lcdc_writel(lcdc_dev,WIN2_MST3+off,
1242                            win->area[3].y_addr); */
1243                         val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1244                             v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1245                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val);
1246                         val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1247                             v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1248                         lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val);
1249                 } else {
1250                         mask = m_WIN2_MST3_EN;
1251                         val = v_WIN2_MST3_EN(0);
1252                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1253                 }
1254
1255                 if (win->alpha_en == 1) {
1256                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1257                 } else {
1258                         mask = m_WIN2_SRC_ALPHA_EN;
1259                         val = v_WIN2_SRC_ALPHA_EN(0);
1260                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off,
1261                                      mask, val);
1262                 }
1263         } else {
1264                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1265                     m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1266                 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1267                     v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1268                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1269         }
1270         return 0;
1271 }
1272
1273 static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1274 {
1275         struct lcdc_device *lcdc_dev =
1276             container_of(dev_drv, struct lcdc_device, driver);
1277         struct rk_lcdc_win *win = dev_drv->win[win_id];
1278         unsigned int mask, val, hwc_size = 0;
1279
1280         if (win->state == 1) {
1281                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1282                 mask = m_HWC_EN | m_HWC_DATA_FMT |
1283                     m_HWC_RB_SWAP | m_WIN0_CSC_MODE;
1284                 val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1285                     v_HWC_RB_SWAP(win->area[0].swap_rb) |
1286                     v_WIN0_CSC_MODE(win->csc_mode);
1287                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1288
1289                 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1290                         hwc_size = 0;
1291                 else if ((win->area[0].xsize == 64) &&
1292                          (win->area[0].ysize == 64))
1293                         hwc_size = 1;
1294                 else if ((win->area[0].xsize == 96) &&
1295                          (win->area[0].ysize == 96))
1296                         hwc_size = 2;
1297                 else if ((win->area[0].xsize == 128) &&
1298                          (win->area[0].ysize == 128))
1299                         hwc_size = 3;
1300                 else
1301                         dev_err(lcdc_dev->dev, "un supported hwc size!\n");
1302
1303                 mask = m_HWC_SIZE;
1304                 val = v_HWC_SIZE(hwc_size);
1305                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1306
1307                 mask = m_HWC_DSP_XST | m_HWC_DSP_YST;
1308                 val = v_HWC_DSP_XST(win->area[0].dsp_stx) |
1309                     v_HWC_DSP_YST(win->area[0].dsp_sty);
1310                 lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val);
1311
1312                 if (win->alpha_en == 1) {
1313                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1314                 } else {
1315                         mask = m_WIN2_SRC_ALPHA_EN;
1316                         val = v_WIN2_SRC_ALPHA_EN(0);
1317                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val);
1318                 }
1319         } else {
1320                 mask = m_HWC_EN;
1321                 val = v_HWC_EN(win->state);
1322                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1323         }
1324         return 0;
1325 }
1326
1327 static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
1328                                          struct rk_lcdc_win *win)
1329 {
1330         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1331         int timeout;
1332         unsigned long flags;
1333
1334         spin_lock(&lcdc_dev->reg_lock);
1335         if (likely(lcdc_dev->clk_on)) {
1336                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1337                              v_STANDBY_EN(lcdc_dev->standby));
1338                 if ((win->id == 0) || (win->id == 1))
1339                         rk3368_win_0_1_reg_update(dev_drv, win->id);
1340                 else if ((win->id == 2) || (win->id == 3))
1341                         rk3368_win_2_3_reg_update(dev_drv, win->id);
1342                 else if (win->id == 4)
1343                         rk3368_hwc_reg_update(dev_drv, win->id);
1344                 /*rk3368_lcdc_post_cfg(dev_drv); */
1345                 lcdc_cfg_done(lcdc_dev);
1346         }
1347         spin_unlock(&lcdc_dev->reg_lock);
1348
1349         /*if (dev_drv->wait_fs) { */
1350         if (0) {
1351                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1352                 init_completion(&dev_drv->frame_done);
1353                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1354                 timeout =
1355                     wait_for_completion_timeout(&dev_drv->frame_done,
1356                                                 msecs_to_jiffies
1357                                                 (dev_drv->cur_screen->ft + 5));
1358                 if (!timeout && (!dev_drv->frame_done.done)) {
1359                         dev_warn(lcdc_dev->dev,
1360                                  "wait for new frame start time out!\n");
1361                         return -ETIMEDOUT;
1362                 }
1363         }
1364         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1365         return 0;
1366 }
1367
1368 static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1369 {
1370         if (lcdc_dev->driver.iommu_enabled)
1371                 memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x330);
1372         else
1373                 memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x260);
1374         return 0;
1375 }
1376
1377 static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1378 {
1379         u32 mask, val;
1380         struct lcdc_device *lcdc_dev =
1381             container_of(dev_drv, struct lcdc_device, driver);
1382         /*spin_lock(&lcdc_dev->reg_lock); */
1383         if (likely(lcdc_dev->clk_on)) {
1384                 mask = m_MMU_EN;
1385                 val = v_MMU_EN(1);
1386                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1387                 mask = m_AXI_MAX_OUTSTANDING_EN | m_AXI_OUTSTANDING_MAX_NUM;
1388                 val = v_AXI_OUTSTANDING_MAX_NUM(31) |
1389                     v_AXI_MAX_OUTSTANDING_EN(1);
1390                 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1391         }
1392         /*spin_unlock(&lcdc_dev->reg_lock); */
1393 #if defined(CONFIG_ROCKCHIP_IOMMU)
1394         if (dev_drv->iommu_enabled) {
1395                 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1396                         lcdc_dev->iommu_status = 1;
1397                         rockchip_iovmm_activate(dev_drv->dev);
1398                 }
1399         }
1400 #endif
1401         return 0;
1402 }
1403
1404 static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
1405 {
1406         int ret = 0, fps = 0;
1407         struct lcdc_device *lcdc_dev =
1408             container_of(dev_drv, struct lcdc_device, driver);
1409         struct rk_screen *screen = dev_drv->cur_screen;
1410 #ifdef CONFIG_RK_FPGA
1411         return 0;
1412 #endif
1413
1414         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1415         if (ret)
1416                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1417         lcdc_dev->pixclock =
1418             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1419         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1420
1421         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1422         screen->ft = 1000 / fps;
1423         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1424                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1425         return 0;
1426 }
1427
1428 static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv)
1429 {
1430         struct lcdc_device *lcdc_dev =
1431             container_of(dev_drv, struct lcdc_device, driver);
1432         struct rk_screen *screen = dev_drv->cur_screen;
1433         u16 hsync_len = screen->mode.hsync_len;
1434         u16 left_margin = screen->mode.left_margin;
1435         u16 right_margin = screen->mode.right_margin;
1436         u16 vsync_len = screen->mode.vsync_len;
1437         u16 upper_margin = screen->mode.upper_margin;
1438         u16 lower_margin = screen->mode.lower_margin;
1439         u16 x_res = screen->mode.xres;
1440         u16 y_res = screen->mode.yres;
1441         u32 mask, val;
1442         u16 h_total, v_total;
1443         u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1444
1445         h_total = hsync_len + left_margin + x_res + right_margin;
1446         v_total = vsync_len + upper_margin + y_res + lower_margin;
1447
1448         screen->post_dsp_stx = x_res * (100 - screen->overscan.left) / 200;
1449         screen->post_dsp_sty = y_res * (100 - screen->overscan.top) / 200;
1450         screen->post_xsize = x_res *
1451             (screen->overscan.left + screen->overscan.right) / 200;
1452         screen->post_ysize = y_res *
1453             (screen->overscan.top + screen->overscan.bottom) / 200;
1454
1455         mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1456         val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1457         lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1458
1459         mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1460         val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1461             v_DSP_HACT_ST(hsync_len + left_margin);
1462         lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1463
1464         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1465                 /* First Field Timing */
1466                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1467                 val = v_DSP_VS_PW(vsync_len) |
1468                     v_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1469                                       lower_margin) + y_res + 1);
1470                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1471
1472                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1473                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1474                     v_DSP_VACT_ST(vsync_len + upper_margin);
1475                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1476
1477                 /* Second Field Timing */
1478                 mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1;
1479                 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1480                 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1481                     lower_margin;
1482                 val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1);
1483                 lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val);
1484
1485                 mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1;
1486                 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1487                     lower_margin + 1;
1488                 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1489                     lower_margin + 1;
1490                 val =
1491                     v_DSP_VACT_END_F1(vact_end_f1) |
1492                     v_DSP_VAC_ST_F1(vact_st_f1);
1493                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val);
1494
1495                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1496                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1497                              v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0));
1498                 mask =
1499                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1500                     m_WIN0_CBR_DEFLICK;
1501                 val =
1502                     v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(1) |
1503                     v_WIN0_CBR_DEFLICK(1);
1504                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1505
1506                 mask =
1507                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1508                     m_WIN1_CBR_DEFLICK;
1509                 val =
1510                     v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(1) |
1511                     v_WIN1_CBR_DEFLICK(1);
1512                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1513
1514                 mask = m_WIN2_INTERLACE_READ;
1515                 val = v_WIN2_INTERLACE_READ(1);
1516                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1517
1518                 mask = m_WIN3_INTERLACE_READ;
1519                 val = v_WIN3_INTERLACE_READ(1);
1520                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1521
1522                 mask = m_HWC_INTERLACE_READ;
1523                 val = v_HWC_INTERLACE_READ(1);
1524                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1525
1526                 mask = m_DSP_LINE_FLAG0_NUM;
1527                 val =
1528                     v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res / 2);
1529                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1530         } else {
1531                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1532                 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1533                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1534
1535                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1536                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1537                     v_DSP_VACT_ST(vsync_len + upper_margin);
1538                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1539
1540                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1541                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1542                              v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0));
1543
1544                 mask =
1545                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1546                     m_WIN0_CBR_DEFLICK;
1547                 val =
1548                     v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) |
1549                     v_WIN0_CBR_DEFLICK(0);
1550                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1551
1552                 mask =
1553                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1554                     m_WIN1_CBR_DEFLICK;
1555                 val =
1556                     v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) |
1557                     v_WIN1_CBR_DEFLICK(0);
1558                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1559
1560                 mask = m_WIN2_INTERLACE_READ;
1561                 val = v_WIN2_INTERLACE_READ(0);
1562                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1563
1564                 mask = m_WIN3_INTERLACE_READ;
1565                 val = v_WIN3_INTERLACE_READ(0);
1566                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1567
1568                 mask = m_HWC_INTERLACE_READ;
1569                 val = v_HWC_INTERLACE_READ(0);
1570                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1571
1572                 mask = m_DSP_LINE_FLAG0_NUM;
1573                 val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res);
1574                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1575         }
1576         rk3368_lcdc_post_cfg(dev_drv);
1577         return 0;
1578 }
1579
1580 static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1581 {
1582         struct lcdc_device *lcdc_dev =
1583             container_of(dev_drv, struct lcdc_device, driver);
1584         u32 bcsh_ctrl;
1585
1586         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1587                 if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1588                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1589                                      m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1590                                      v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1591                 else            /* YUV2RGB */
1592                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1593                                      m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1594                                      m_BCSH_R2Y_EN,
1595                                      v_BCSH_Y2R_EN(1) |
1596                                      v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1597                                      v_BCSH_R2Y_EN(0));
1598         } else {                /* overlay_mode=VOP_RGB_DOMAIN */
1599                 /* bypass  --need check,if bcsh close? */
1600                 if (dev_drv->output_color == COLOR_RGB) {
1601                         bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1602                         if (((bcsh_ctrl & m_BCSH_EN) == 1) ||
1603                             (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1604                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1605                                              m_BCSH_R2Y_EN |
1606                                              m_BCSH_Y2R_EN,
1607                                              v_BCSH_R2Y_EN(1) |
1608                                              v_BCSH_Y2R_EN(1));
1609                         else
1610                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1611                                              m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1612                                              v_BCSH_R2Y_EN(0) |
1613                                              v_BCSH_Y2R_EN(0));
1614                 } else          /* RGB2YUV */
1615                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1616                                      m_BCSH_R2Y_EN |
1617                                      m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1618                                      v_BCSH_R2Y_EN(1) |
1619                                      v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1620                                      v_BCSH_Y2R_EN(0));
1621         }
1622 }
1623
1624 static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1625 {
1626         u16 face = 0;
1627         u16 dclk_ddr = 0;
1628         u32 v = 0;
1629         struct lcdc_device *lcdc_dev =
1630             container_of(dev_drv, struct lcdc_device, driver);
1631         struct rk_screen *screen = dev_drv->cur_screen;
1632         u32 mask, val;
1633
1634         spin_lock(&lcdc_dev->reg_lock);
1635         if (likely(lcdc_dev->clk_on)) {
1636                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1637                 if (!lcdc_dev->standby && !initscreen) {
1638                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1639                                      v_STANDBY_EN(1));
1640                         lcdc_cfg_done(lcdc_dev);
1641                         mdelay(50);
1642                 }
1643                 switch (screen->face) {
1644                 case OUT_P565:
1645                         face = OUT_P565;
1646                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1647                             m_DITHER_DOWN_SEL;
1648                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1649                             v_DITHER_DOWN_SEL(1);
1650                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1651                         break;
1652                 case OUT_P666:
1653                         face = OUT_P666;
1654                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1655                             m_DITHER_DOWN_SEL;
1656                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1657                             v_DITHER_DOWN_SEL(1);
1658                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1659                         break;
1660                 case OUT_D888_P565:
1661                         face = OUT_P888;
1662                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1663                             m_DITHER_DOWN_SEL;
1664                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1665                             v_DITHER_DOWN_SEL(1);
1666                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1667                         break;
1668                 case OUT_D888_P666:
1669                         face = OUT_P888;
1670                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1671                             m_DITHER_DOWN_SEL;
1672                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1673                             v_DITHER_DOWN_SEL(1);
1674                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1675                         break;
1676                 case OUT_P888:
1677                         face = OUT_P888;
1678                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1679                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1680                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1681                         break;
1682                 case OUT_YUV_420:
1683                         /*yuv420 output prefer yuv domain overlay */
1684                         face = OUT_YUV_420;
1685                         dclk_ddr = 1;
1686                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1687                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1688                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1689                         break;
1690                 default:
1691                         dev_err(lcdc_dev->dev, "un supported interface!\n");
1692                         break;
1693                 }
1694                 switch (screen->type) {
1695                 case SCREEN_RGB:
1696                         mask = m_RGB_OUT_EN;
1697                         val = v_RGB_OUT_EN(1);
1698                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1699                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1700                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1701                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1702                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1703                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1704                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1705                         v = 1 << 15 | (1 << (15 + 16));
1706
1707                         break;
1708                 case SCREEN_LVDS:
1709                         mask = m_RGB_OUT_EN;
1710                         val = v_RGB_OUT_EN(1);
1711                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1712                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1713                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1714                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1715                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1716                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1717                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1718                         v = 0 << 15 | (1 << (15 + 16));
1719                         break;
1720                 case SCREEN_HDMI:
1721                         face = OUT_RGB_AAA;
1722                         mask = m_HDMI_OUT_EN;
1723                         val = v_HDMI_OUT_EN(1);
1724                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1725                         mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
1726                             m_HDMI_DEN_POL | m_HDMI_DCLK_POL;
1727                         val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
1728                             v_HDMI_VSYNC_POL(screen->pin_vsync) |
1729                             v_HDMI_DEN_POL(screen->pin_den) |
1730                             v_HDMI_DCLK_POL(screen->pin_dclk);
1731                         break;
1732                 case SCREEN_MIPI:
1733                         mask = m_MIPI_OUT_EN;
1734                         val = v_MIPI_OUT_EN(1);
1735                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1736                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1737                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1738                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1739                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1740                             v_MIPI_DEN_POL(screen->pin_den) |
1741                             v_MIPI_DCLK_POL(screen->pin_dclk);
1742                         break;
1743                 case SCREEN_DUAL_MIPI:
1744                         mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN;
1745                         val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1);
1746                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1747                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1748                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1749                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1750                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1751                             v_MIPI_DEN_POL(screen->pin_den) |
1752                             v_MIPI_DCLK_POL(screen->pin_dclk);
1753                         break;
1754                 case SCREEN_EDP:
1755                         face = OUT_RGB_AAA;     /*RGB AAA output */
1756
1757                         mask = m_EDP_OUT_EN;
1758                         val = v_EDP_OUT_EN(1);
1759                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1760                         /*because edp have to sent aaa fmt */
1761                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1762                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1763
1764                         mask |= m_EDP_HSYNC_POL | m_EDP_VSYNC_POL |
1765                             m_EDP_DEN_POL | m_EDP_DCLK_POL;
1766                         val |= v_EDP_HSYNC_POL(screen->pin_hsync) |
1767                             v_EDP_VSYNC_POL(screen->pin_vsync) |
1768                             v_EDP_DEN_POL(screen->pin_den) |
1769                             v_EDP_DCLK_POL(screen->pin_dclk);
1770                         break;
1771                 }
1772                 /*hsync vsync den dclk polo,dither */
1773                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1774 #ifndef CONFIG_RK_FPGA
1775                 /*writel_relaxed(v, RK_GRF_VIRT + rk3368_GRF_SOC_CON7);
1776                 move to  lvds driver*/
1777                 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
1778 #endif
1779                 mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP |
1780                     m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1781                     m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1782                     m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
1783                 val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) |
1784                     v_DSP_BG_SWAP(screen->swap_gb) |
1785                     v_DSP_RB_SWAP(screen->swap_rb) |
1786                     v_DSP_RG_SWAP(screen->swap_rg) |
1787                     v_DSP_DELTA_SWAP(screen->swap_delta) |
1788                     v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1789                     v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1790                     v_DSP_X_MIR_EN(screen->x_mirror) |
1791                     v_DSP_Y_MIR_EN(screen->y_mirror);
1792                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1793                 /*BG color */
1794                 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1795                 val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) | v_DSP_BG_RED(0);
1796                 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1797                 rk3368_lcdc_bcsh_path_sel(dev_drv);
1798                 rk3368_config_timing(dev_drv);
1799         }
1800         spin_unlock(&lcdc_dev->reg_lock);
1801         rk3368_lcdc_set_dclk(dev_drv);
1802         if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1803             dev_drv->trsm_ops->enable)
1804                 dev_drv->trsm_ops->enable();
1805         if (screen->init)
1806                 screen->init();
1807         if (!lcdc_dev->standby)
1808                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
1809         return 0;
1810 }
1811
1812
1813 /*enable layer,open:1,enable;0 disable*/
1814 static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev,
1815                                      unsigned int win_id, bool open)
1816 {
1817         spin_lock(&lcdc_dev->reg_lock);
1818         if (likely(lcdc_dev->clk_on) &&
1819             lcdc_dev->driver.win[win_id]->state != open) {
1820                 if (open) {
1821                         if (!lcdc_dev->atv_layer_cnt) {
1822                                 dev_info(lcdc_dev->dev,
1823                                          "wakeup from standby!\n");
1824                                 lcdc_dev->standby = 0;
1825                         }
1826                         lcdc_dev->atv_layer_cnt |= (1 << win_id);
1827                 } else {
1828                         if (lcdc_dev->atv_layer_cnt & (1 << win_id))
1829                                 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
1830                 }
1831                 lcdc_dev->driver.win[win_id]->state = open;
1832                 if (!open) {
1833                         /*rk3368_lcdc_reg_update(dev_drv);*/
1834                         rk3368_lcdc_layer_update_regs
1835                         (lcdc_dev, lcdc_dev->driver.win[win_id]);
1836                         lcdc_cfg_done(lcdc_dev);
1837                 }
1838                 /*if no layer used,disable lcdc */
1839                 if (!lcdc_dev->atv_layer_cnt) {
1840                         dev_info(lcdc_dev->dev,
1841                                  "no layer is used,go to standby!\n");
1842                         lcdc_dev->standby = 1;
1843                 }
1844         }
1845         spin_unlock(&lcdc_dev->reg_lock);
1846 }
1847
1848 static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1849 {
1850         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1851                                                     struct lcdc_device, driver);
1852         u32 mask, val;
1853         /*struct rk_screen *screen = dev_drv->cur_screen; */
1854
1855         mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
1856             m_LINE_FLAG1_INTR_CLR;
1857         val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
1858             v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1);
1859         lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
1860
1861         mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN | m_BUS_ERROR_INTR_EN;
1862         val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) |
1863             v_BUS_ERROR_INTR_EN(1);
1864         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1865
1866 #ifdef LCDC_IRQ_EMPTY_DEBUG
1867         mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
1868             m_WIN2_EMPTY_INTR_EN |
1869             m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN |
1870             m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN;
1871         val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) |
1872             v_WIN2_EMPTY_INTR_EN(1) |
1873             v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) |
1874             v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1);
1875         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1876 #endif
1877         return 0;
1878 }
1879
1880 static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1881                             bool open)
1882 {
1883         struct lcdc_device *lcdc_dev =
1884             container_of(dev_drv, struct lcdc_device, driver);
1885 #if 0/*ndef CONFIG_RK_FPGA*/
1886         int sys_status =
1887             (dev_drv->id == 0) ? SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
1888 #endif
1889         /*enable clk,when first layer open */
1890         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1891                 /*rockchip_set_system_status(sys_status);*/
1892                 rk3368_lcdc_pre_init(dev_drv);
1893                 rk3368_lcdc_clk_enable(lcdc_dev);
1894 #if defined(CONFIG_ROCKCHIP_IOMMU)
1895                 if (dev_drv->iommu_enabled) {
1896                         if (!dev_drv->mmu_dev) {
1897                                 dev_drv->mmu_dev =
1898                                     rk_fb_get_sysmmu_device_by_compatible
1899                                     (dev_drv->mmu_dts_name);
1900                                 if (dev_drv->mmu_dev) {
1901                                         rk_fb_platform_set_sysmmu
1902                                             (dev_drv->mmu_dev, dev_drv->dev);
1903                                 } else {
1904                                         dev_err(dev_drv->dev,
1905                                                 "fail get rk iommu device\n");
1906                                         return -1;
1907                                 }
1908                         }
1909                         /*if (dev_drv->mmu_dev)
1910                            rockchip_iovmm_activate(dev_drv->dev); */
1911                 }
1912 #endif
1913                 rk3368_lcdc_reg_restore(lcdc_dev);
1914                 /*if (dev_drv->iommu_enabled)
1915                    rk3368_lcdc_mmu_en(dev_drv); */
1916                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
1917                         /*rk3368_lcdc_set_dclk(dev_drv); */
1918                         rk3368_lcdc_enable_irq(dev_drv);
1919                 } else {
1920                         rk3368_load_screen(dev_drv, 1);
1921                 }
1922                 if (dev_drv->bcsh.enable)
1923                         rk3368_lcdc_set_bcsh(dev_drv, 1);
1924                 spin_lock(&lcdc_dev->reg_lock);
1925                 if (dev_drv->cur_screen->dsp_lut)
1926                         rk3368_lcdc_set_lut(dev_drv);
1927                 spin_unlock(&lcdc_dev->reg_lock);
1928         }
1929
1930         if (win_id < ARRAY_SIZE(lcdc_win))
1931                 rk3368_lcdc_layer_enable(lcdc_dev, win_id, open);
1932         else
1933                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1934
1935
1936         /* when all layer closed,disable clk */
1937         /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1938            rk3368_lcdc_disable_irq(lcdc_dev);
1939            rk3368_lcdc_reg_update(dev_drv);
1940            #if defined(CONFIG_ROCKCHIP_IOMMU)
1941            if (dev_drv->iommu_enabled) {
1942            if (dev_drv->mmu_dev)
1943            rockchip_iovmm_deactivate(dev_drv->dev);
1944            }
1945            #endif
1946            rk3368_lcdc_clk_disable(lcdc_dev);
1947            #ifndef CONFIG_RK_FPGA
1948            rockchip_clear_system_status(sys_status);
1949            #endif
1950            } */
1951
1952         return 0;
1953 }
1954
1955 static int win_0_1_display(struct lcdc_device *lcdc_dev,
1956                            struct rk_lcdc_win *win)
1957 {
1958         u32 y_addr;
1959         u32 uv_addr;
1960         unsigned int off;
1961
1962         off = win->id * 0x40;
1963         /*win->smem_start + win->y_offset; */
1964         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1965         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1966         DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
1967             lcdc_dev->id, win->id, y_addr, uv_addr);
1968         DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
1969             win->area[0].y_offset, win->area[0].c_offset);
1970         spin_lock(&lcdc_dev->reg_lock);
1971         if (likely(lcdc_dev->clk_on)) {
1972                 win->area[0].y_addr = y_addr;
1973                 win->area[0].uv_addr = uv_addr;
1974                 lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
1975                 lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
1976                 /*lcdc_cfg_done(lcdc_dev); */
1977         }
1978         spin_unlock(&lcdc_dev->reg_lock);
1979
1980         return 0;
1981 }
1982
1983 static int win_2_3_display(struct lcdc_device *lcdc_dev,
1984                            struct rk_lcdc_win *win)
1985 {
1986         u32 i, y_addr;
1987         unsigned int off;
1988
1989         off = (win->id - 2) * 0x50;
1990         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1991         DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id);
1992
1993         spin_lock(&lcdc_dev->reg_lock);
1994         if (likely(lcdc_dev->clk_on)) {
1995                 for (i = 0; i < win->area_num; i++) {
1996                         DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
1997                             i, win->area[i].y_addr, win->area[i].y_offset);
1998                         win->area[i].y_addr =
1999                             win->area[i].smem_start + win->area[i].y_offset;
2000                         }
2001                 lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr);
2002                 lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr);
2003                 lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr);
2004                 lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr);
2005         }
2006         spin_unlock(&lcdc_dev->reg_lock);
2007         return 0;
2008 }
2009
2010 static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win)
2011 {
2012         u32 y_addr;
2013
2014         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2015         DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2016             lcdc_dev->id, __func__, y_addr);
2017         spin_lock(&lcdc_dev->reg_lock);
2018         if (likely(lcdc_dev->clk_on)) {
2019                 win->area[0].y_addr = y_addr;
2020                 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
2021         }
2022         spin_unlock(&lcdc_dev->reg_lock);
2023
2024         return 0;
2025 }
2026
2027 static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2028 {
2029         struct lcdc_device *lcdc_dev =
2030             container_of(dev_drv, struct lcdc_device, driver);
2031         struct rk_lcdc_win *win = NULL;
2032         struct rk_screen *screen = dev_drv->cur_screen;
2033
2034 #if defined(WAIT_FOR_SYNC)
2035         int timeout;
2036         unsigned long flags;
2037 #endif
2038         win = dev_drv->win[win_id];
2039         if (!screen) {
2040                 dev_err(dev_drv->dev, "screen is null!\n");
2041                 return -ENOENT;
2042         }
2043         if (win_id == 0) {
2044                 win_0_1_display(lcdc_dev, win);
2045         } else if (win_id == 1) {
2046                 win_0_1_display(lcdc_dev, win);
2047         } else if (win_id == 2) {
2048                 win_2_3_display(lcdc_dev, win);
2049         } else if (win_id == 3) {
2050                 win_2_3_display(lcdc_dev, win);
2051         } else if (win_id == 4) {
2052                 hwc_display(lcdc_dev, win);
2053         } else {
2054                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2055                 return -EINVAL;
2056         }
2057
2058         /*this is the first frame of the system ,enable frame start interrupt */
2059         if ((dev_drv->first_frame)) {
2060                 dev_drv->first_frame = 0;
2061                 rk3368_lcdc_enable_irq(dev_drv);
2062         }
2063 #if defined(WAIT_FOR_SYNC)
2064         spin_lock_irqsave(&dev_drv->cpl_lock, flags);
2065         init_completion(&dev_drv->frame_done);
2066         spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
2067         timeout =
2068             wait_for_completion_timeout(&dev_drv->frame_done,
2069                                         msecs_to_jiffies(dev_drv->
2070                                                          cur_screen->ft + 5));
2071         if (!timeout && (!dev_drv->frame_done.done)) {
2072                 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
2073                 return -ETIMEDOUT;
2074         }
2075 #endif
2076         return 0;
2077 }
2078
2079 static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
2080 {
2081         u16 srcW;
2082         u16 srcH;
2083         u16 dstW;
2084         u16 dstH;
2085         u16 yrgb_srcW;
2086         u16 yrgb_srcH;
2087         u16 yrgb_dstW;
2088         u16 yrgb_dstH;
2089         u32 yrgb_vscalednmult;
2090         u32 yrgb_xscl_factor;
2091         u32 yrgb_yscl_factor;
2092         u8 yrgb_vsd_bil_gt2 = 0;
2093         u8 yrgb_vsd_bil_gt4 = 0;
2094
2095         u16 cbcr_srcW;
2096         u16 cbcr_srcH;
2097         u16 cbcr_dstW;
2098         u16 cbcr_dstH;
2099         u32 cbcr_vscalednmult;
2100         u32 cbcr_xscl_factor;
2101         u32 cbcr_yscl_factor;
2102         u8 cbcr_vsd_bil_gt2 = 0;
2103         u8 cbcr_vsd_bil_gt4 = 0;
2104         u8 yuv_fmt = 0;
2105
2106         srcW = win->area[0].xact;
2107         srcH = win->area[0].yact;
2108         dstW = win->area[0].xsize;
2109         dstH = win->area[0].ysize;
2110
2111         /*yrgb scl mode */
2112         yrgb_srcW = srcW;
2113         yrgb_srcH = srcH;
2114         yrgb_dstW = dstW;
2115         yrgb_dstH = dstH;
2116         if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2117                 pr_err("ERROR: yrgb scale exceed 8,");
2118                 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2119                        yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2120         }
2121         if (yrgb_srcW < yrgb_dstW)
2122                 win->yrgb_hor_scl_mode = SCALE_UP;
2123         else if (yrgb_srcW > yrgb_dstW)
2124                 win->yrgb_hor_scl_mode = SCALE_DOWN;
2125         else
2126                 win->yrgb_hor_scl_mode = SCALE_NONE;
2127
2128         if (yrgb_srcH < yrgb_dstH)
2129                 win->yrgb_ver_scl_mode = SCALE_UP;
2130         else if (yrgb_srcH > yrgb_dstH)
2131                 win->yrgb_ver_scl_mode = SCALE_DOWN;
2132         else
2133                 win->yrgb_ver_scl_mode = SCALE_NONE;
2134
2135         /*cbcr scl mode */
2136         switch (win->area[0].format) {
2137         case YUV422:
2138         case YUV422_A:
2139                 cbcr_srcW = srcW / 2;
2140                 cbcr_dstW = dstW;
2141                 cbcr_srcH = srcH;
2142                 cbcr_dstH = dstH;
2143                 yuv_fmt = 1;
2144                 break;
2145         case YUV420:
2146         case YUV420_A:
2147                 cbcr_srcW = srcW / 2;
2148                 cbcr_dstW = dstW;
2149                 cbcr_srcH = srcH / 2;
2150                 cbcr_dstH = dstH;
2151                 yuv_fmt = 1;
2152                 break;
2153         case YUV444:
2154         case YUV444_A:
2155                 cbcr_srcW = srcW;
2156                 cbcr_dstW = dstW;
2157                 cbcr_srcH = srcH;
2158                 cbcr_dstH = dstH;
2159                 yuv_fmt = 1;
2160                 break;
2161         default:
2162                 cbcr_srcW = 0;
2163                 cbcr_dstW = 0;
2164                 cbcr_srcH = 0;
2165                 cbcr_dstH = 0;
2166                 yuv_fmt = 0;
2167                 break;
2168         }
2169         if (yuv_fmt) {
2170                 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2171                     (cbcr_dstH * 8 <= cbcr_srcH)) {
2172                         pr_err("ERROR: cbcr scale exceed 8,");
2173                         pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2174                                cbcr_srcH, cbcr_dstW, cbcr_dstH);
2175                 }
2176         }
2177
2178         if (cbcr_srcW < cbcr_dstW)
2179                 win->cbr_hor_scl_mode = SCALE_UP;
2180         else if (cbcr_srcW > cbcr_dstW)
2181                 win->cbr_hor_scl_mode = SCALE_DOWN;
2182         else
2183                 win->cbr_hor_scl_mode = SCALE_NONE;
2184
2185         if (cbcr_srcH < cbcr_dstH)
2186                 win->cbr_ver_scl_mode = SCALE_UP;
2187         else if (cbcr_srcH > cbcr_dstH)
2188                 win->cbr_ver_scl_mode = SCALE_DOWN;
2189         else
2190                 win->cbr_ver_scl_mode = SCALE_NONE;
2191
2192         /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
2193             "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
2194             "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW,
2195             srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH,
2196             win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW,
2197             cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode,
2198             win->cbr_ver_scl_mode);*/
2199
2200         /*line buffer mode */
2201         if ((win->area[0].format == YUV422) ||
2202             (win->area[0].format == YUV420) ||
2203             (win->area[0].format == YUV422_A) ||
2204             (win->area[0].format == YUV420_A)) {
2205                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2206                         if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2207                             (cbcr_dstW == 0))
2208                                 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2209                                        cbcr_dstW);
2210                         else if (cbcr_dstW > 1280)
2211                                 win->win_lb_mode = LB_YUV_3840X5;
2212                         else
2213                                 win->win_lb_mode = LB_YUV_2560X8;
2214                 } else {        /*SCALE_UP or SCALE_NONE */
2215                         if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2216                             (cbcr_srcW == 0))
2217                                 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2218                                        cbcr_srcW);
2219                         else if (cbcr_srcW > 1280)
2220                                 win->win_lb_mode = LB_YUV_3840X5;
2221                         else
2222                                 win->win_lb_mode = LB_YUV_2560X8;
2223                 }
2224         } else {
2225                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2226                         if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2227                             (yrgb_dstW == 0))
2228                                 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2229                         else if (yrgb_dstW > 2560)
2230                                 win->win_lb_mode = LB_RGB_3840X2;
2231                         else if (yrgb_dstW > 1920)
2232                                 win->win_lb_mode = LB_RGB_2560X4;
2233                         else if (yrgb_dstW > 1280)
2234                                 win->win_lb_mode = LB_RGB_1920X5;
2235                         else
2236                                 win->win_lb_mode = LB_RGB_1280X8;
2237                 } else {        /*SCALE_UP or SCALE_NONE */
2238                         if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2239                             (yrgb_srcW == 0))
2240                                 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2241                         else if (yrgb_srcW > 2560)
2242                                 win->win_lb_mode = LB_RGB_3840X2;
2243                         else if (yrgb_srcW > 1920)
2244                                 win->win_lb_mode = LB_RGB_2560X4;
2245                         else if (yrgb_srcW > 1280)
2246                                 win->win_lb_mode = LB_RGB_1920X5;
2247                         else
2248                                 win->win_lb_mode = LB_RGB_1280X8;
2249                 }
2250         }
2251         DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2252
2253         /*vsd/vsu scale ALGORITHM */
2254         win->yrgb_hsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2255         win->cbr_hsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2256         win->yrgb_vsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2257         win->cbr_vsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2258         switch (win->win_lb_mode) {
2259         case LB_YUV_3840X5:
2260         case LB_YUV_2560X8:
2261         case LB_RGB_1920X5:
2262         case LB_RGB_1280X8:
2263                 win->yrgb_vsu_mode = SCALE_UP_BIC;
2264                 win->cbr_vsu_mode = SCALE_UP_BIC;
2265                 break;
2266         case LB_RGB_3840X2:
2267                 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2268                         pr_err("ERROR : not allow yrgb ver scale\n");
2269                 if (win->cbr_ver_scl_mode != SCALE_NONE)
2270                         pr_err("ERROR : not allow cbcr ver scale\n");
2271                 break;
2272         case LB_RGB_2560X4:
2273                 win->yrgb_vsu_mode = SCALE_UP_BIL;
2274                 win->cbr_vsu_mode = SCALE_UP_BIL;
2275                 break;
2276         default:
2277                 pr_info("%s:un supported win_lb_mode:%d\n",
2278                         __func__, win->win_lb_mode);
2279                 break;
2280         }
2281         if (win->mirror_en == 1) {      /*interlace mode must bill */
2282                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2283         }
2284
2285         if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2286             (win->area[0].fbdc_en == 1)) {
2287                 /*in this pattern,use bil mode,not support souble scd,
2288                 use avg mode, support double scd, but aclk should be
2289                 bigger than dclk,aclk>>dclk */
2290                 if (yrgb_srcH >= 2 * yrgb_dstH) {
2291                         pr_err("ERROR : fbdc mode,not support y scale down:");
2292                         pr_err("srcH[%d] > 2 *dstH[%d]\n",
2293                                yrgb_srcH, yrgb_dstH);
2294                 }
2295         }
2296         DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2297             win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2298             win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2299
2300         /*SCALE FACTOR */
2301
2302         /*(1.1)YRGB HOR SCALE FACTOR */
2303         switch (win->yrgb_hor_scl_mode) {
2304         case SCALE_NONE:
2305                 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2306                 break;
2307         case SCALE_UP:
2308                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2309                 break;
2310         case SCALE_DOWN:
2311                 switch (win->yrgb_hsd_mode) {
2312                 case SCALE_DOWN_BIL:
2313                         yrgb_xscl_factor =
2314                             GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2315                         break;
2316                 case SCALE_DOWN_AVG:
2317                         yrgb_xscl_factor =
2318                             GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2319                         break;
2320                 default:
2321                         pr_info(
2322                                 "%s:un supported yrgb_hsd_mode:%d\n", __func__,
2323                                win->yrgb_hsd_mode);
2324                         break;
2325                 }
2326                 break;
2327         default:
2328                 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2329                         __func__, win->yrgb_hor_scl_mode);
2330                 break;
2331         }                       /*win->yrgb_hor_scl_mode */
2332
2333         /*(1.2)YRGB VER SCALE FACTOR */
2334         switch (win->yrgb_ver_scl_mode) {
2335         case SCALE_NONE:
2336                 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2337                 break;
2338         case SCALE_UP:
2339                 switch (win->yrgb_vsu_mode) {
2340                 case SCALE_UP_BIL:
2341                         yrgb_yscl_factor =
2342                             GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2343                         break;
2344                 case SCALE_UP_BIC:
2345                         if (yrgb_srcH < 3) {
2346                                 pr_err("yrgb_srcH should be");
2347                                 pr_err(" greater than 3 !!!\n");
2348                         }
2349                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2350                                                                 yrgb_dstH);
2351                         break;
2352                 default:
2353                         pr_info("%s:un support yrgb_vsu_mode:%d\n",
2354                                 __func__, win->yrgb_vsu_mode);
2355                         break;
2356                 }
2357                 break;
2358         case SCALE_DOWN:
2359                 switch (win->yrgb_vsd_mode) {
2360                 case SCALE_DOWN_BIL:
2361                         yrgb_vscalednmult =
2362                             rk3368_get_hard_ware_vskiplines(yrgb_srcH,
2363                                                             yrgb_dstH);
2364                         yrgb_yscl_factor =
2365                             GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2366                                                            yrgb_vscalednmult);
2367                         if (yrgb_yscl_factor >= 0x2000) {
2368                                 pr_err("yrgb_yscl_factor should be ");
2369                                 pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n",
2370                                        yrgb_yscl_factor);
2371                         }
2372                         if (yrgb_vscalednmult == 4) {
2373                                 yrgb_vsd_bil_gt4 = 1;
2374                                 yrgb_vsd_bil_gt2 = 0;
2375                         } else if (yrgb_vscalednmult == 2) {
2376                                 yrgb_vsd_bil_gt4 = 0;
2377                                 yrgb_vsd_bil_gt2 = 1;
2378                         } else {
2379                                 yrgb_vsd_bil_gt4 = 0;
2380                                 yrgb_vsd_bil_gt2 = 0;
2381                         }
2382                         break;
2383                 case SCALE_DOWN_AVG:
2384                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2385                                                                  yrgb_dstH);
2386                         break;
2387                 default:
2388                         pr_info("%s:un support yrgb_vsd_mode:%d\n",
2389                                 __func__, win->yrgb_vsd_mode);
2390                         break;
2391                 }               /*win->yrgb_vsd_mode */
2392                 break;
2393         default:
2394                 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2395                         __func__, win->yrgb_ver_scl_mode);
2396                 break;
2397         }
2398         win->scale_yrgb_x = yrgb_xscl_factor;
2399         win->scale_yrgb_y = yrgb_yscl_factor;
2400         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2401         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2402         DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2403             yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2404
2405         /*(2.1)CBCR HOR SCALE FACTOR */
2406         switch (win->cbr_hor_scl_mode) {
2407         case SCALE_NONE:
2408                 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2409                 break;
2410         case SCALE_UP:
2411                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2412                 break;
2413         case SCALE_DOWN:
2414                 switch (win->cbr_hsd_mode) {
2415                 case SCALE_DOWN_BIL:
2416                         cbcr_xscl_factor =
2417                             GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2418                         break;
2419                 case SCALE_DOWN_AVG:
2420                         cbcr_xscl_factor =
2421                             GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2422                         break;
2423                 default:
2424                         pr_info("%s:un support cbr_hsd_mode:%d\n",
2425                                 __func__, win->cbr_hsd_mode);
2426                         break;
2427                 }
2428                 break;
2429         default:
2430                 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2431                         __func__, win->cbr_hor_scl_mode);
2432                 break;
2433         }                       /*win->cbr_hor_scl_mode */
2434
2435         /*(2.2)CBCR VER SCALE FACTOR */
2436         switch (win->cbr_ver_scl_mode) {
2437         case SCALE_NONE:
2438                 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2439                 break;
2440         case SCALE_UP:
2441                 switch (win->cbr_vsu_mode) {
2442                 case SCALE_UP_BIL:
2443                         cbcr_yscl_factor =
2444                             GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2445                         break;
2446                 case SCALE_UP_BIC:
2447                         if (cbcr_srcH < 3) {
2448                                 pr_err("cbcr_srcH should be ");
2449                                 pr_err("greater than 3 !!!\n");
2450                         }
2451                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2452                                                                 cbcr_dstH);
2453                         break;
2454                 default:
2455                         pr_info("%s:un support cbr_vsu_mode:%d\n",
2456                                 __func__, win->cbr_vsu_mode);
2457                         break;
2458                 }
2459                 break;
2460         case SCALE_DOWN:
2461                 switch (win->cbr_vsd_mode) {
2462                 case SCALE_DOWN_BIL:
2463                         cbcr_vscalednmult =
2464                             rk3368_get_hard_ware_vskiplines(cbcr_srcH,
2465                                                             cbcr_dstH);
2466                         cbcr_yscl_factor =
2467                             GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2468                                                            cbcr_vscalednmult);
2469                         if (cbcr_yscl_factor >= 0x2000) {
2470                                 pr_err("cbcr_yscl_factor should be less ");
2471                                 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2472                                        cbcr_yscl_factor);
2473                         }
2474
2475                         if (cbcr_vscalednmult == 4) {
2476                                 cbcr_vsd_bil_gt4 = 1;
2477                                 cbcr_vsd_bil_gt2 = 0;
2478                         } else if (cbcr_vscalednmult == 2) {
2479                                 cbcr_vsd_bil_gt4 = 0;
2480                                 cbcr_vsd_bil_gt2 = 1;
2481                         } else {
2482                                 cbcr_vsd_bil_gt4 = 0;
2483                                 cbcr_vsd_bil_gt2 = 0;
2484                         }
2485                         break;
2486                 case SCALE_DOWN_AVG:
2487                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2488                                                                  cbcr_dstH);
2489                         break;
2490                 default:
2491                         pr_info("%s:un support cbr_vsd_mode:%d\n",
2492                                 __func__, win->cbr_vsd_mode);
2493                         break;
2494                 }
2495                 break;
2496         default:
2497                 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2498                         __func__, win->cbr_ver_scl_mode);
2499                 break;
2500         }
2501         win->scale_cbcr_x = cbcr_xscl_factor;
2502         win->scale_cbcr_y = cbcr_yscl_factor;
2503         win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2504         win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2505
2506         DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2507             cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2508         return 0;
2509 }
2510
2511 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2512                      struct rk_lcdc_win_area *area)
2513 {
2514         int pos;
2515
2516         if (screen->x_mirror && mirror_en)
2517                 pr_err("not support both win and global mirror\n");
2518
2519         if ((!mirror_en) && (!screen->x_mirror))
2520                 pos = area->xpos + screen->mode.left_margin +
2521                         screen->mode.hsync_len;
2522         else
2523                 pos = screen->mode.xres - area->xpos -
2524                         area->xsize + screen->mode.left_margin +
2525                         screen->mode.hsync_len;
2526
2527         return pos;
2528 }
2529
2530 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2531                      struct rk_lcdc_win_area *area)
2532 {
2533         int pos;
2534
2535         if (screen->y_mirror && mirror_en)
2536                 pr_err("not support both win and global mirror\n");
2537
2538         if ((!mirror_en) && (!screen->y_mirror))
2539                 pos = area->ypos + screen->mode.upper_margin +
2540                         screen->mode.vsync_len;
2541         else
2542                 pos = screen->mode.yres - area->ypos -
2543                         area->ysize + screen->mode.upper_margin +
2544                         screen->mode.vsync_len;
2545
2546         return pos;
2547 }
2548
2549 static int win_0_1_set_par(struct lcdc_device *lcdc_dev,
2550                            struct rk_screen *screen, struct rk_lcdc_win *win)
2551 {
2552         u32 xact, yact, xvir, yvir, xpos, ypos;
2553         u8 fmt_cfg = 0, swap_rb;
2554         char fmt[9] = "NULL";
2555
2556         xpos = dsp_x_pos(win->mirror_en, screen, &win->area[0]);
2557         ypos = dsp_y_pos(win->mirror_en, screen, &win->area[0]);
2558
2559         spin_lock(&lcdc_dev->reg_lock);
2560         if (likely(lcdc_dev->clk_on)) {
2561                 rk3368_lcdc_cal_scl_fac(win);   /*fac,lb,gt2,gt4 */
2562                 switch (win->area[0].format) {
2563                 case ARGB888:
2564                         fmt_cfg = 0;
2565                         swap_rb = 0;
2566                         win->fmt_10 = 0;
2567                         break;
2568                 case XBGR888:
2569                 case ABGR888:
2570                         fmt_cfg = 0;
2571                         swap_rb = 1;
2572                         win->fmt_10 = 0;
2573                         break;
2574                 case RGB888:
2575                         fmt_cfg = 1;
2576                         swap_rb = 0;
2577                         win->fmt_10 = 0;
2578                         break;
2579                 case RGB565:
2580                         fmt_cfg = 2;
2581                         swap_rb = 0;
2582                         win->fmt_10 = 0;
2583                         break;
2584                 case YUV422:
2585                         fmt_cfg = 5;
2586                         swap_rb = 0;
2587                         win->fmt_10 = 0;
2588                         break;
2589                 case YUV420:
2590                         fmt_cfg = 4;
2591                         swap_rb = 0;
2592                         win->fmt_10 = 0;
2593                         break;
2594                 case YUV444:
2595                         fmt_cfg = 6;
2596                         swap_rb = 0;
2597                         win->fmt_10 = 0;
2598                         break;
2599                 case YUV422_A:
2600                         fmt_cfg = 5;
2601                         swap_rb = 0;
2602                         win->fmt_10 = 1;
2603                         break;
2604                 case YUV420_A:
2605                         fmt_cfg = 4;
2606                         swap_rb = 0;
2607                         win->fmt_10 = 1;
2608                         break;
2609                 case YUV444_A:
2610                         fmt_cfg = 6;
2611                         swap_rb = 0;
2612                         win->fmt_10 = 1;
2613                         break;
2614                 default:
2615                         dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n",
2616                                 __func__);
2617                         break;
2618                 }
2619                 win->area[0].fmt_cfg = fmt_cfg;
2620                 win->area[0].swap_rb = swap_rb;
2621                 win->area[0].dsp_stx = xpos;
2622                 win->area[0].dsp_sty = ypos;
2623                 xact = win->area[0].xact;
2624                 yact = win->area[0].yact;
2625                 xvir = win->area[0].xvir;
2626                 yvir = win->area[0].yvir;
2627         }
2628         if (win->area[0].fbdc_en)
2629                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2630         rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id);
2631         spin_unlock(&lcdc_dev->reg_lock);
2632
2633         DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2634             lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2635             xact, yact, win->area[0].xsize);
2636         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2637             win->area[0].ysize, xvir, yvir, xpos, ypos);
2638
2639         return 0;
2640 }
2641
2642
2643 static int win_2_3_set_par(struct lcdc_device *lcdc_dev,
2644                            struct rk_screen *screen, struct rk_lcdc_win *win)
2645 {
2646         int i;
2647         u8 fmt_cfg, swap_rb;
2648         char fmt[9] = "NULL";
2649
2650         if (win->mirror_en)
2651                 pr_err("win[%d] not support y mirror\n", win->id);
2652         spin_lock(&lcdc_dev->reg_lock);
2653         if (likely(lcdc_dev->clk_on)) {
2654                 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id);
2655                 for (i = 0; i < win->area_num; i++) {
2656                         switch (win->area[i].format) {
2657                         case ARGB888:
2658                                 fmt_cfg = 0;
2659                                 swap_rb = 0;
2660                                 break;
2661                         case XBGR888:
2662                         case ABGR888:
2663                                 fmt_cfg = 0;
2664                                 swap_rb = 1;
2665                                 break;
2666                         case RGB888:
2667                                 fmt_cfg = 1;
2668                                 swap_rb = 0;
2669                                 break;
2670                         case RGB565:
2671                                 fmt_cfg = 2;
2672                                 swap_rb = 0;
2673                                 break;
2674                         default:
2675                                 dev_err(lcdc_dev->driver.dev,
2676                                         "%s:un supported format!\n", __func__);
2677                                 break;
2678                         }
2679                         win->area[i].fmt_cfg = fmt_cfg;
2680                         win->area[i].swap_rb = swap_rb;
2681                         win->area[i].dsp_stx =
2682                                         dsp_x_pos(win->mirror_en, screen,
2683                                                   &win->area[i]);
2684                         win->area[i].dsp_sty =
2685                                         dsp_y_pos(win->mirror_en, screen,
2686                                                   &win->area[i]);
2687
2688                         DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
2689                             get_format_string(win->area[i].format, fmt),
2690                             win->area[i].xsize, win->area[i].ysize,
2691                             win->area[i].xpos, win->area[i].ypos);
2692                 }
2693         }
2694         if (win->area[0].fbdc_en)
2695                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2696         rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id);
2697         spin_unlock(&lcdc_dev->reg_lock);
2698         return 0;
2699 }
2700
2701 static int hwc_set_par(struct lcdc_device *lcdc_dev,
2702                        struct rk_screen *screen, struct rk_lcdc_win *win)
2703 {
2704         u32 xact, yact, xvir, yvir, xpos, ypos;
2705         u8 fmt_cfg = 0, swap_rb;
2706         char fmt[9] = "NULL";
2707
2708         xpos = win->area[0].xpos + screen->mode.left_margin +
2709             screen->mode.hsync_len;
2710         ypos = win->area[0].ypos + screen->mode.upper_margin +
2711             screen->mode.vsync_len;
2712
2713         spin_lock(&lcdc_dev->reg_lock);
2714         if (likely(lcdc_dev->clk_on)) {
2715                 /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */
2716                 switch (win->area[0].format) {
2717                 case ARGB888:
2718                         fmt_cfg = 0;
2719                         swap_rb = 0;
2720                         break;
2721                 case XBGR888:
2722                 case ABGR888:
2723                         fmt_cfg = 0;
2724                         swap_rb = 1;
2725                         break;
2726                 case RGB888:
2727                         fmt_cfg = 1;
2728                         swap_rb = 0;
2729                         break;
2730                 case RGB565:
2731                         fmt_cfg = 2;
2732                         swap_rb = 0;
2733                         break;
2734                 default:
2735                         dev_err(lcdc_dev->driver.dev,
2736                                 "%s:un supported format!\n", __func__);
2737                         break;
2738                 }
2739                 win->area[0].fmt_cfg = fmt_cfg;
2740                 win->area[0].swap_rb = swap_rb;
2741                 win->area[0].dsp_stx = xpos;
2742                 win->area[0].dsp_sty = ypos;
2743                 xact = win->area[0].xact;
2744                 yact = win->area[0].yact;
2745                 xvir = win->area[0].xvir;
2746                 yvir = win->area[0].yvir;
2747         }
2748         rk3368_hwc_reg_update(&lcdc_dev->driver, 4);
2749         spin_unlock(&lcdc_dev->reg_lock);
2750
2751         DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2752             lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt),
2753             xact, yact, win->area[0].xsize);
2754         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2755             win->area[0].ysize, xvir, yvir, xpos, ypos);
2756         return 0;
2757 }
2758
2759 static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
2760 {
2761         struct lcdc_device *lcdc_dev =
2762             container_of(dev_drv, struct lcdc_device, driver);
2763         struct rk_lcdc_win *win = NULL;
2764         struct rk_screen *screen = dev_drv->cur_screen;
2765
2766         win = dev_drv->win[win_id];
2767         switch (win_id) {
2768         case 0:
2769                 win_0_1_set_par(lcdc_dev, screen, win);
2770                 break;
2771         case 1:
2772                 win_0_1_set_par(lcdc_dev, screen, win);
2773                 break;
2774         case 2:
2775                 win_2_3_set_par(lcdc_dev, screen, win);
2776                 break;
2777         case 3:
2778                 win_2_3_set_par(lcdc_dev, screen, win);
2779                 break;
2780         case 4:
2781                 hwc_set_par(lcdc_dev, screen, win);
2782                 break;
2783         default:
2784                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2785                 break;
2786         }
2787         return 0;
2788 }
2789
2790 static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2791                              unsigned long arg, int win_id)
2792 {
2793         struct lcdc_device *lcdc_dev =
2794             container_of(dev_drv, struct lcdc_device, driver);
2795         u32 panel_size[2];
2796         void __user *argp = (void __user *)arg;
2797         struct color_key_cfg clr_key_cfg;
2798
2799         switch (cmd) {
2800         case RK_FBIOGET_PANEL_SIZE:
2801                 panel_size[0] = lcdc_dev->screen->mode.xres;
2802                 panel_size[1] = lcdc_dev->screen->mode.yres;
2803                 if (copy_to_user(argp, panel_size, 8))
2804                         return -EFAULT;
2805                 break;
2806         case RK_FBIOPUT_COLOR_KEY_CFG:
2807                 if (copy_from_user(&clr_key_cfg, argp,
2808                                    sizeof(struct color_key_cfg)))
2809                         return -EFAULT;
2810                 rk3368_lcdc_clr_key_cfg(dev_drv);
2811                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
2812                             clr_key_cfg.win0_color_key_cfg);
2813                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
2814                             clr_key_cfg.win1_color_key_cfg);
2815                 break;
2816
2817         default:
2818                 break;
2819         }
2820         return 0;
2821 }
2822
2823 static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
2824 {
2825         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2826                                                     struct lcdc_device, driver);
2827         /*struct device_node *backlight;*/
2828
2829         if (lcdc_dev->backlight)
2830                 return 0;
2831 #if 0
2832         backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0);
2833         if (backlight) {
2834                 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
2835                 if (!lcdc_dev->backlight)
2836                         dev_info(lcdc_dev->dev, "No find backlight device\n");
2837         } else {
2838                 dev_info(lcdc_dev->dev, "No find backlight device node\n");
2839         }
2840 #endif
2841         return 0;
2842 }
2843
2844 static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
2845 {
2846         u32 reg;
2847         struct lcdc_device *lcdc_dev =
2848             container_of(dev_drv, struct lcdc_device, driver);
2849         if (dev_drv->suspend_flag)
2850                 return 0;
2851         /* close the backlight */
2852         /*rk3368_lcdc_get_backlight_device(dev_drv);
2853         if (lcdc_dev->backlight) {
2854                 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
2855                 backlight_update_status(lcdc_dev->backlight);
2856         }*/
2857
2858         dev_drv->suspend_flag = 1;
2859         flush_kthread_worker(&dev_drv->update_regs_worker);
2860
2861         for (reg = MMU_DTE_ADDR; reg <= MMU_AUTO_GATING; reg += 4)
2862                 lcdc_readl_backup(lcdc_dev, reg);
2863         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
2864                 dev_drv->trsm_ops->disable();
2865
2866         spin_lock(&lcdc_dev->reg_lock);
2867         if (likely(lcdc_dev->clk_on)) {
2868                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2869                              v_DSP_BLANK_EN(1));
2870                 lcdc_msk_reg(lcdc_dev,
2871                              INTR_CLEAR, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR,
2872                              v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1));
2873                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2874                              v_DSP_OUT_ZERO(1));
2875                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
2876                 lcdc_cfg_done(lcdc_dev);
2877
2878                 if (dev_drv->iommu_enabled) {
2879                         if (dev_drv->mmu_dev)
2880                                 rockchip_iovmm_deactivate(dev_drv->dev);
2881                 }
2882
2883                 spin_unlock(&lcdc_dev->reg_lock);
2884         } else {
2885                 spin_unlock(&lcdc_dev->reg_lock);
2886                 return 0;
2887         }
2888         rk3368_lcdc_clk_disable(lcdc_dev);
2889         rk_disp_pwr_disable(dev_drv);
2890         return 0;
2891 }
2892
2893 static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
2894 {
2895         struct lcdc_device *lcdc_dev =
2896             container_of(dev_drv, struct lcdc_device, driver);
2897         int i, j;
2898         int __iomem *c;
2899         int v, r, g, b;
2900
2901         if (!dev_drv->suspend_flag)
2902                 return 0;
2903         rk_disp_pwr_enable(dev_drv);
2904         dev_drv->suspend_flag = 0;
2905
2906         if (1/*lcdc_dev->atv_layer_cnt*/) {
2907                 rk3368_lcdc_clk_enable(lcdc_dev);
2908                 rk3368_lcdc_reg_restore(lcdc_dev);
2909
2910                 spin_lock(&lcdc_dev->reg_lock);
2911                 if (dev_drv->cur_screen->dsp_lut) {
2912                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2913                                      v_DSP_LUT_EN(0));
2914                         lcdc_cfg_done(lcdc_dev);
2915                         mdelay(25);
2916                         for (i = 0; i < 256; i++) {
2917                                 v = dev_drv->cur_screen->dsp_lut[i];
2918                                 c = lcdc_dev->dsp_lut_addr_base + (i << 2);
2919                                 b = (v & 0xff);
2920                                 g = (v & 0xff00);
2921                                 r = (v & 0xff0000);
2922                                 v = r + g + b;
2923                                 for (j = 0; j < 4; j++) {
2924                                         writel_relaxed(v, c);
2925                                         v += (1 + (1 << 10) + (1 << 20));
2926                                         c++;
2927                                 }
2928                         }
2929                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2930                                      v_DSP_LUT_EN(1));
2931                 }
2932
2933                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2934                              v_DSP_OUT_ZERO(0));
2935                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
2936                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2937                              v_DSP_BLANK_EN(0));
2938                 lcdc_cfg_done(lcdc_dev);
2939
2940                 if (dev_drv->iommu_enabled) {
2941                         if (dev_drv->mmu_dev)
2942                                 rockchip_iovmm_activate(dev_drv->dev);
2943                 }
2944
2945                 spin_unlock(&lcdc_dev->reg_lock);
2946         }
2947
2948         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2949                 dev_drv->trsm_ops->enable();
2950
2951         return 0;
2952 }
2953
2954 static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv,
2955                              int win_id, int blank_mode)
2956 {
2957         switch (blank_mode) {
2958         case FB_BLANK_UNBLANK:
2959                 rk3368_lcdc_early_resume(dev_drv);
2960                 break;
2961         case FB_BLANK_NORMAL:
2962                 rk3368_lcdc_early_suspend(dev_drv);
2963                 break;
2964         default:
2965                 rk3368_lcdc_early_suspend(dev_drv);
2966                 break;
2967         }
2968
2969         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
2970
2971         return 0;
2972 }
2973
2974 static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
2975 {
2976         return 0;
2977 }
2978
2979 /*overlay will be do at regupdate*/
2980 static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
2981                                bool set)
2982 {
2983         struct lcdc_device *lcdc_dev =
2984             container_of(dev_drv, struct lcdc_device, driver);
2985         struct rk_lcdc_win *win = NULL;
2986         int i, ovl;
2987         unsigned int mask, val;
2988         int z_order_num = 0;
2989         int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
2990
2991         if (swap == 0) {
2992                 for (i = 0; i < 4; i++) {
2993                         win = dev_drv->win[i];
2994                         if (win->state == 1)
2995                                 z_order_num++;
2996                 }
2997                 for (i = 0; i < 4; i++) {
2998                         win = dev_drv->win[i];
2999                         if (win->state == 0)
3000                                 win->z_order = z_order_num++;
3001                         switch (win->z_order) {
3002                         case 0:
3003                                 layer0_sel = win->id;
3004                                 break;
3005                         case 1:
3006                                 layer1_sel = win->id;
3007                                 break;
3008                         case 2:
3009                                 layer2_sel = win->id;
3010                                 break;
3011                         case 3:
3012                                 layer3_sel = win->id;
3013                                 break;
3014                         default:
3015                                 break;
3016                         }
3017                 }
3018         } else {
3019                 layer0_sel = swap % 10;
3020                 layer1_sel = swap / 10 % 10;
3021                 layer2_sel = swap / 100 % 10;
3022                 layer3_sel = swap / 1000;
3023         }
3024
3025         spin_lock(&lcdc_dev->reg_lock);
3026         if (lcdc_dev->clk_on) {
3027                 if (set) {
3028                         mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
3029                             m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
3030                         val = v_DSP_LAYER0_SEL(layer0_sel) |
3031                             v_DSP_LAYER1_SEL(layer1_sel) |
3032                             v_DSP_LAYER2_SEL(layer2_sel) |
3033                             v_DSP_LAYER3_SEL(layer3_sel);
3034                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
3035                 } else {
3036                         layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3037                                                    m_DSP_LAYER0_SEL);
3038                         layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3039                                                    m_DSP_LAYER1_SEL);
3040                         layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3041                                                    m_DSP_LAYER2_SEL);
3042                         layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3043                                                    m_DSP_LAYER3_SEL);
3044                         ovl = layer3_sel * 1000 + layer2_sel * 100 +
3045                             layer1_sel * 10 + layer0_sel;
3046                 }
3047         } else {
3048                 ovl = -EPERM;
3049         }
3050         spin_unlock(&lcdc_dev->reg_lock);
3051
3052         return ovl;
3053 }
3054
3055 static char *rk3368_lcdc_format_to_string(int format, char *fmt)
3056 {
3057         if (!fmt)
3058                 return NULL;
3059
3060         switch (format) {
3061         case 0:
3062                 strcpy(fmt, "ARGB888");
3063                 break;
3064         case 1:
3065                 strcpy(fmt, "RGB888");
3066                 break;
3067         case 2:
3068                 strcpy(fmt, "RGB565");
3069                 break;
3070         case 4:
3071                 strcpy(fmt, "YCbCr420");
3072                 break;
3073         case 5:
3074                 strcpy(fmt, "YCbCr422");
3075                 break;
3076         case 6:
3077                 strcpy(fmt, "YCbCr444");
3078                 break;
3079         default:
3080                 strcpy(fmt, "invalid\n");
3081                 break;
3082         }
3083         return fmt;
3084 }
3085 static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
3086                                          char *buf, int win_id)
3087 {
3088         struct lcdc_device *lcdc_dev =
3089             container_of(dev_drv, struct lcdc_device, driver);
3090         struct rk_screen *screen = dev_drv->cur_screen;
3091         u16 hsync_len = screen->mode.hsync_len;
3092         u16 left_margin = screen->mode.left_margin;
3093         u16 vsync_len = screen->mode.vsync_len;
3094         u16 upper_margin = screen->mode.upper_margin;
3095         u32 h_pw_bp = hsync_len + left_margin;
3096         u32 v_pw_bp = vsync_len + upper_margin;
3097         u32 fmt_id;
3098         char format_w0[9] = "NULL";
3099         char format_w1[9] = "NULL";
3100         char format_w2_0[9] = "NULL";
3101         char format_w2_1[9] = "NULL";
3102         char format_w2_2[9] = "NULL";
3103         char format_w2_3[9] = "NULL";
3104         char format_w3_0[9] = "NULL";
3105         char format_w3_1[9] = "NULL";
3106         char format_w3_2[9] = "NULL";
3107         char format_w3_3[9] = "NULL";
3108         char dsp_buf[100];
3109         u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3110         u32 y_factor, uv_factor;
3111         u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3112         u8 w0_state, w1_state, w2_state, w3_state;
3113         u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3114         u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3115
3116         u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3117         u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3118         u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3119         u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3120         u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3121         u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3122
3123         u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3124         u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3125         u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3126         u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3127         u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3128         u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3129         u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3130
3131         u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3132         u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3133         u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3134         u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3135         u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3136         u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3137         u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3138         u32 dclk_freq;
3139         int size = 0;
3140
3141         dclk_freq = screen->mode.pixclock;
3142         /*rk3368_lcdc_reg_dump(dev_drv); */
3143
3144         spin_lock(&lcdc_dev->reg_lock);
3145         if (lcdc_dev->clk_on) {
3146                 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
3147                 layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8;
3148                 layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10;
3149                 layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12;
3150                 layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14;
3151                 /*WIN0 */
3152                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3153                 w0_state = win_ctrl & m_WIN0_EN;
3154                 fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1;
3155                 rk3368_lcdc_format_to_string(fmt_id, format_w0);
3156                 vir_info = lcdc_readl(lcdc_dev, WIN0_VIR);
3157                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
3158                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
3159                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
3160                 y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
3161                 uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR);
3162                 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
3163                 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16;
3164                 w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1;
3165                 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1;
3166                 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1;
3167                 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1;
3168                 if (w0_state) {
3169                         w0_st_x = dsp_st & m_WIN0_DSP_XST;
3170                         w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16;
3171                 }
3172                 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
3173                 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16;
3174                 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
3175                 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16;
3176
3177                 /*WIN1 */
3178                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3179                 w1_state = win_ctrl & m_WIN1_EN;
3180                 fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1;
3181                 rk3368_lcdc_format_to_string(fmt_id, format_w1);
3182                 vir_info = lcdc_readl(lcdc_dev, WIN1_VIR);
3183                 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
3184                 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
3185                 dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
3186                 y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB);
3187                 uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR);
3188                 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
3189                 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16;
3190                 w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1;
3191                 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1;
3192                 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1;
3193                 w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1;
3194                 if (w1_state) {
3195                         w1_st_x = dsp_st & m_WIN1_DSP_XST;
3196                         w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16;
3197                 }
3198                 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
3199                 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16;
3200                 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
3201                 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16;
3202                 /*WIN2 */
3203                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3204                 w2_state = win_ctrl & m_WIN2_EN;
3205                 w2_0_state = (win_ctrl & m_WIN2_MST0_EN) >> 4;
3206                 w2_1_state = (win_ctrl & m_WIN2_MST1_EN) >> 5;
3207                 w2_2_state = (win_ctrl & m_WIN2_MST2_EN) >> 6;
3208                 w2_3_state = (win_ctrl & m_WIN2_MST3_EN) >> 7;
3209                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1);
3210                 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3211                 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16;
3212                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3);
3213                 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3214                 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16;
3215
3216                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1;
3217                 rk3368_lcdc_format_to_string(fmt_id, format_w2_0);
3218                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1;
3219                 rk3368_lcdc_format_to_string(fmt_id, format_w2_1);
3220                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1;
3221                 rk3368_lcdc_format_to_string(fmt_id, format_w2_2);
3222                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1;
3223                 rk3368_lcdc_format_to_string(fmt_id, format_w2_3);
3224
3225                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0);
3226                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0);
3227                 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1;
3228                 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1;
3229                 if (w2_0_state) {
3230                         w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3231                         w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16;
3232                 }
3233                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1);
3234                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1);
3235                 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1;
3236                 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1;
3237                 if (w2_1_state) {
3238                         w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3239                         w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16;
3240                 }
3241                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2);
3242                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2);
3243                 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1;
3244                 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1;
3245                 if (w2_2_state) {
3246                         w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3247                         w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16;
3248                 }
3249                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3);
3250                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3);
3251                 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1;
3252                 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1;
3253                 if (w2_3_state) {
3254                         w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3255                         w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16;
3256                 }
3257
3258                 /*WIN3 */
3259                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3260                 w3_state = win_ctrl & m_WIN3_EN;
3261                 w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4;
3262                 w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 5;
3263                 w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 6;
3264                 w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 7;
3265                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1);
3266                 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3267                 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16;
3268                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3);
3269                 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3270                 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16;
3271                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1;
3272                 rk3368_lcdc_format_to_string(fmt_id, format_w3_0);
3273                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1;
3274                 rk3368_lcdc_format_to_string(fmt_id, format_w3_1);
3275                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1;
3276                 rk3368_lcdc_format_to_string(fmt_id, format_w3_2);
3277                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1;
3278                 rk3368_lcdc_format_to_string(fmt_id, format_w3_3);
3279                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0);
3280                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0);
3281                 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1;
3282                 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1;
3283                 if (w3_0_state) {
3284                         w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3285                         w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16;
3286                 }
3287
3288                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1);
3289                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1);
3290                 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1;
3291                 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1;
3292                 if (w3_1_state) {
3293                         w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3294                         w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16;
3295                 }
3296
3297                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2);
3298                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2);
3299                 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1;
3300                 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1;
3301                 if (w3_2_state) {
3302                         w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3303                         w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16;
3304                 }
3305
3306                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3);
3307                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3);
3308                 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1;
3309                 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1;
3310                 if (w3_3_state) {
3311                         w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3312                         w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16;
3313                 }
3314
3315         } else {
3316                 spin_unlock(&lcdc_dev->reg_lock);
3317                 return -EPERM;
3318         }
3319         spin_unlock(&lcdc_dev->reg_lock);
3320         size += snprintf(dsp_buf, 80,
3321                 "z-order:\n  win[%d]\n  win[%d]\n  win[%d]\n  win[%d]\n",
3322                 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3323         strcat(buf, dsp_buf);
3324         memset(dsp_buf, 0, sizeof(dsp_buf));
3325         /*win0*/
3326         size += snprintf(dsp_buf, 80,
3327                  "win0:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3328                  w0_state, format_w0, w0_vir_y, w0_vir_uv);
3329         strcat(buf, dsp_buf);
3330         memset(dsp_buf, 0, sizeof(dsp_buf));
3331
3332         size += snprintf(dsp_buf, 80,
3333                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3334                  w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3335         strcat(buf, dsp_buf);
3336         memset(dsp_buf, 0, sizeof(dsp_buf));
3337
3338         size += snprintf(dsp_buf, 80,
3339                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3340                  w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3341         strcat(buf, dsp_buf);
3342         memset(dsp_buf, 0, sizeof(dsp_buf));
3343
3344         size += snprintf(dsp_buf, 80,
3345                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3346                  w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3347                  lcdc_readl(lcdc_dev, WIN0_CBR_MST));
3348         strcat(buf, dsp_buf);
3349         memset(dsp_buf, 0, sizeof(dsp_buf));
3350
3351         /*win1*/
3352         size += snprintf(dsp_buf, 80,
3353                  "win1:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3354                  w1_state, format_w1, w1_vir_y, w1_vir_uv);
3355         strcat(buf, dsp_buf);
3356         memset(dsp_buf, 0, sizeof(dsp_buf));
3357
3358         size += snprintf(dsp_buf, 80,
3359                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3360                  w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3361         strcat(buf, dsp_buf);
3362         memset(dsp_buf, 0, sizeof(dsp_buf));
3363
3364         size += snprintf(dsp_buf, 80,
3365                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3366                  w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3367         strcat(buf, dsp_buf);
3368         memset(dsp_buf, 0, sizeof(dsp_buf));
3369
3370         size += snprintf(dsp_buf, 80,
3371                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3372                  w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3373                  lcdc_readl(lcdc_dev, WIN1_CBR_MST));
3374         strcat(buf, dsp_buf);
3375         memset(dsp_buf, 0, sizeof(dsp_buf));
3376
3377         /*win2*/
3378         size += snprintf(dsp_buf, 80,
3379                  "win2:\n  state:%d\n",
3380                  w2_state);
3381         strcat(buf, dsp_buf);
3382         memset(dsp_buf, 0, sizeof(dsp_buf));
3383         /*area 0*/
3384         size += snprintf(dsp_buf, 80,
3385                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3386                  w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3387         strcat(buf, dsp_buf);
3388         memset(dsp_buf, 0, sizeof(dsp_buf));
3389         size += snprintf(dsp_buf, 80,
3390                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3391                  w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3392                  lcdc_readl(lcdc_dev, WIN2_MST0));
3393         strcat(buf, dsp_buf);
3394         memset(dsp_buf, 0, sizeof(dsp_buf));
3395
3396         /*area 1*/
3397         size += snprintf(dsp_buf, 80,
3398                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3399                  w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3400         strcat(buf, dsp_buf);
3401         memset(dsp_buf, 0, sizeof(dsp_buf));
3402         size += snprintf(dsp_buf, 80,
3403                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3404                  w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3405                  lcdc_readl(lcdc_dev, WIN2_MST1));
3406         strcat(buf, dsp_buf);
3407         memset(dsp_buf, 0, sizeof(dsp_buf));
3408
3409         /*area 2*/
3410         size += snprintf(dsp_buf, 80,
3411                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3412                  w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3413         strcat(buf, dsp_buf);
3414         memset(dsp_buf, 0, sizeof(dsp_buf));
3415         size += snprintf(dsp_buf, 80,
3416                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3417                  w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3418                  lcdc_readl(lcdc_dev, WIN2_MST2));
3419         strcat(buf, dsp_buf);
3420         memset(dsp_buf, 0, sizeof(dsp_buf));
3421
3422         /*area 3*/
3423         size += snprintf(dsp_buf, 80,
3424                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3425                  w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3426         strcat(buf, dsp_buf);
3427         memset(dsp_buf, 0, sizeof(dsp_buf));
3428         size += snprintf(dsp_buf, 80,
3429                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3430                  w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3431                  lcdc_readl(lcdc_dev, WIN2_MST3));
3432         strcat(buf, dsp_buf);
3433         memset(dsp_buf, 0, sizeof(dsp_buf));
3434
3435         /*win3*/
3436         size += snprintf(dsp_buf, 80,
3437                  "win3:\n  state:%d\n",
3438                  w3_state);
3439         strcat(buf, dsp_buf);
3440         memset(dsp_buf, 0, sizeof(dsp_buf));
3441         /*area 0*/
3442         size += snprintf(dsp_buf, 80,
3443                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3444                  w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
3445         strcat(buf, dsp_buf);
3446         memset(dsp_buf, 0, sizeof(dsp_buf));
3447         size += snprintf(dsp_buf, 80,
3448                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3449                  w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
3450                  lcdc_readl(lcdc_dev, WIN3_MST0));
3451         strcat(buf, dsp_buf);
3452         memset(dsp_buf, 0, sizeof(dsp_buf));
3453
3454         /*area 1*/
3455         size += snprintf(dsp_buf, 80,
3456                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3457                  w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
3458         strcat(buf, dsp_buf);
3459         memset(dsp_buf, 0, sizeof(dsp_buf));
3460         size += snprintf(dsp_buf, 80,
3461                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3462                  w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
3463                  lcdc_readl(lcdc_dev, WIN3_MST1));
3464         strcat(buf, dsp_buf);
3465         memset(dsp_buf, 0, sizeof(dsp_buf));
3466
3467         /*area 2*/
3468         size += snprintf(dsp_buf, 80,
3469                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3470                  w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
3471         strcat(buf, dsp_buf);
3472         memset(dsp_buf, 0, sizeof(dsp_buf));
3473         size += snprintf(dsp_buf, 80,
3474                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3475                  w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
3476                  lcdc_readl(lcdc_dev, WIN3_MST2));
3477         strcat(buf, dsp_buf);
3478         memset(dsp_buf, 0, sizeof(dsp_buf));
3479
3480         /*area 3*/
3481         size += snprintf(dsp_buf, 80,
3482                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3483                  w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
3484         strcat(buf, dsp_buf);
3485         memset(dsp_buf, 0, sizeof(dsp_buf));
3486         size += snprintf(dsp_buf, 80,
3487                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3488                  w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
3489                  lcdc_readl(lcdc_dev, WIN3_MST3));
3490         strcat(buf, dsp_buf);
3491         memset(dsp_buf, 0, sizeof(dsp_buf));
3492
3493         return size;
3494 }
3495
3496 static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3497                                bool set)
3498 {
3499         struct lcdc_device *lcdc_dev =
3500             container_of(dev_drv, struct lcdc_device, driver);
3501         struct rk_screen *screen = dev_drv->cur_screen;
3502         u64 ft = 0;
3503         u32 dotclk;
3504         int ret;
3505         u32 pixclock;
3506         u32 x_total, y_total;
3507
3508         if (set) {
3509                 if (fps == 0) {
3510                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
3511                         return 0;
3512                 }
3513                 ft = div_u64(1000000000000llu, fps);
3514                 x_total =
3515                     screen->mode.upper_margin + screen->mode.lower_margin +
3516                     screen->mode.yres + screen->mode.vsync_len;
3517                 y_total =
3518                     screen->mode.left_margin + screen->mode.right_margin +
3519                     screen->mode.xres + screen->mode.hsync_len;
3520                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3521                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3522                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3523         }
3524
3525         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3526         lcdc_dev->pixclock = pixclock;
3527         dev_drv->pixclock = lcdc_dev->pixclock;
3528         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3529         screen->ft = 1000 / fps;        /*one frame time in ms */
3530
3531         if (set)
3532                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3533                          clk_get_rate(lcdc_dev->dclk), fps);
3534
3535         return fps;
3536 }
3537
3538 static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3539 {
3540         mutex_lock(&dev_drv->fb_win_id_mutex);
3541         if (order == FB_DEFAULT_ORDER)
3542                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
3543         dev_drv->fb4_win_id = order / 10000;
3544         dev_drv->fb3_win_id = (order / 1000) % 10;
3545         dev_drv->fb2_win_id = (order / 100) % 10;
3546         dev_drv->fb1_win_id = (order / 10) % 10;
3547         dev_drv->fb0_win_id = order % 10;
3548         mutex_unlock(&dev_drv->fb_win_id_mutex);
3549
3550         return 0;
3551 }
3552
3553 static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3554                                   const char *id)
3555 {
3556         int win_id = 0;
3557
3558         mutex_lock(&dev_drv->fb_win_id_mutex);
3559         if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
3560                 win_id = dev_drv->fb0_win_id;
3561         else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
3562                 win_id = dev_drv->fb1_win_id;
3563         else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
3564                 win_id = dev_drv->fb2_win_id;
3565         else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
3566                 win_id = dev_drv->fb3_win_id;
3567         else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
3568                 win_id = dev_drv->fb4_win_id;
3569         mutex_unlock(&dev_drv->fb_win_id_mutex);
3570
3571         return win_id;
3572 }
3573
3574 static int rk3368_set_dsp_lut(struct rk_lcdc_driver *dev_drv, int *lut)
3575 {
3576         int i, j;
3577         int __iomem *c;
3578         int v, r, g, b;
3579         int ret = 0;
3580
3581         struct lcdc_device *lcdc_dev =
3582             container_of(dev_drv, struct lcdc_device, driver);
3583         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
3584         lcdc_cfg_done(lcdc_dev);
3585         mdelay(25);
3586         if (dev_drv->cur_screen->dsp_lut) {
3587                 for (i = 0; i < 256; i++) {
3588                         dev_drv->cur_screen->dsp_lut[i] = lut[i];
3589                         v = dev_drv->cur_screen->dsp_lut[i];
3590                         c = lcdc_dev->dsp_lut_addr_base + (i << 2);
3591                         b = (v & 0xff) << 2;
3592                         g = (v & 0xff00) << 4;
3593                         r = (v & 0xff0000) << 6;
3594                         v = r + g + b;
3595                         for (j = 0; j < 4; j++) {
3596                                 writel_relaxed(v, c);
3597                                 v += (1 + (1 << 10) + (1 << 20));
3598                                 c++;
3599                         }
3600                 }
3601         } else {
3602                 dev_err(dev_drv->dev, "no buffer to backup lut data!\n");
3603                 ret = -1;
3604         }
3605
3606         do {
3607                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
3608                              v_DSP_LUT_EN(1));
3609                 lcdc_cfg_done(lcdc_dev);
3610         } while (!lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN));
3611         return ret;
3612 }
3613
3614 static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3615 {
3616         struct lcdc_device *lcdc_dev =
3617             container_of(dev_drv, struct lcdc_device, driver);
3618         int i;
3619         unsigned int mask, val;
3620         struct rk_lcdc_win *win = NULL;
3621
3622         spin_lock(&lcdc_dev->reg_lock);
3623         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3624                      v_STANDBY_EN(lcdc_dev->standby));
3625         for (i = 0; i < 4; i++) {
3626                 win = dev_drv->win[i];
3627                 if ((win->state == 0) && (win->last_state == 1)) {
3628                         switch (win->id) {
3629                         case 0:
3630                                 /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
3631                                    for rk3288 to fix hw bug? */
3632                                 mask = m_WIN0_EN;
3633                                 val = v_WIN0_EN(0);
3634                                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
3635                                 break;
3636                         case 1:
3637                                 /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
3638                                    for rk3288 to fix hw bug? */
3639                                 mask = m_WIN1_EN;
3640                                 val = v_WIN1_EN(0);
3641                                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
3642                                 break;
3643                         case 2:
3644                                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
3645                                     m_WIN2_MST1_EN |
3646                                     m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3647                                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
3648                                     v_WIN2_MST1_EN(0) |
3649                                     v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3650                                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
3651                                 break;
3652                         case 3:
3653                                 mask = m_WIN3_EN | m_WIN3_MST0_EN |
3654                                     m_WIN3_MST1_EN |
3655                                     m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3656                                 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |
3657                                     v_WIN3_MST1_EN(0) |
3658                                     v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3659                                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
3660                                 break;
3661                         case 4:
3662                                 mask = m_HWC_EN;
3663                                 val = v_HWC_EN(0);
3664                                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
3665                                 break;
3666                         default:
3667                                 break;
3668                         }
3669                 }
3670                 win->last_state = win->state;
3671         }
3672         lcdc_cfg_done(lcdc_dev);
3673         spin_unlock(&lcdc_dev->reg_lock);
3674         return 0;
3675 }
3676
3677 static int rk3368_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3678 {
3679         struct lcdc_device *lcdc_dev =
3680             container_of(dev_drv, struct lcdc_device, driver);
3681         spin_lock(&lcdc_dev->reg_lock);
3682         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3683                      v_DIRECT_PATH_EN(open));
3684         lcdc_cfg_done(lcdc_dev);
3685         spin_unlock(&lcdc_dev->reg_lock);
3686         return 0;
3687 }
3688
3689 static int rk3368_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3690 {
3691         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3692                                                     struct lcdc_device, driver);
3693         spin_lock(&lcdc_dev->reg_lock);
3694         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3695                      v_DIRECT_PATCH_SEL(win_id));
3696         lcdc_cfg_done(lcdc_dev);
3697         spin_unlock(&lcdc_dev->reg_lock);
3698         return 0;
3699 }
3700
3701 static int rk3368_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3702 {
3703         struct lcdc_device *lcdc_dev =
3704             container_of(dev_drv, struct lcdc_device, driver);
3705         int ovl;
3706
3707         spin_lock(&lcdc_dev->reg_lock);
3708         ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3709         spin_unlock(&lcdc_dev->reg_lock);
3710         return ovl;
3711 }
3712
3713 static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
3714                                       int enable)
3715 {
3716         struct lcdc_device *lcdc_dev =
3717             container_of(dev_drv, struct lcdc_device, driver);
3718         if (enable)
3719                 enable_irq(lcdc_dev->irq);
3720         else
3721                 disable_irq(lcdc_dev->irq);
3722         return 0;
3723 }
3724
3725 int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3726 {
3727         struct lcdc_device *lcdc_dev =
3728             container_of(dev_drv, struct lcdc_device, driver);
3729         u32 int_reg;
3730         int ret;
3731
3732         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
3733                 int_reg = lcdc_readl(lcdc_dev, INTR_STATUS);
3734                 if (int_reg & m_LINE_FLAG0_INTR_STS) {
3735                         lcdc_dev->driver.frame_time.last_framedone_t =
3736                             lcdc_dev->driver.frame_time.framedone_t;
3737                         lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3738                         lcdc_msk_reg(lcdc_dev, INTR_CLEAR,
3739                                      m_LINE_FLAG0_INTR_CLR,
3740                                      v_LINE_FLAG0_INTR_CLR(1));
3741                         ret = RK_LF_STATUS_FC;
3742                 } else {
3743                         ret = RK_LF_STATUS_FR;
3744                 }
3745         } else {
3746                 ret = RK_LF_STATUS_NC;
3747         }
3748
3749         return ret;
3750 }
3751
3752 static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3753                                     unsigned int *dsp_addr)
3754 {
3755         struct lcdc_device *lcdc_dev =
3756             container_of(dev_drv, struct lcdc_device, driver);
3757         spin_lock(&lcdc_dev->reg_lock);
3758         if (lcdc_dev->clk_on) {
3759                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3760                 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3761                 dsp_addr[2] = lcdc_readl(lcdc_dev, WIN2_MST0);
3762                 dsp_addr[3] = lcdc_readl(lcdc_dev, WIN3_MST0);
3763         }
3764         spin_unlock(&lcdc_dev->reg_lock);
3765         return 0;
3766 }
3767
3768 static struct lcdc_cabc_mode cabc_mode[4] = {
3769         /* pixel_num,8 stage_up, stage_down */
3770         {5, 148, 20, 300},      /*mode 1 */
3771         {10, 148, 20, 300},     /*mode 2 */
3772         {15, 148, 20, 300},     /*mode 3 */
3773         {20, 148, 20, 300},     /*mode 4 */
3774 };
3775
3776 static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode)
3777 {
3778         struct lcdc_device *lcdc_dev =
3779             container_of(dev_drv, struct lcdc_device, driver);
3780         struct rk_screen *screen = dev_drv->cur_screen;
3781         u32 total_pixel, calc_pixel, stage_up, stage_down;
3782         u32 pixel_num, global_su;
3783         u32 stage_up_rec, stage_down_rec, global_su_rec;
3784         u32 mask = 0, val = 0, cabc_en = 0;
3785         u32 __maybe_unused max_mode_num =
3786             sizeof(cabc_mode) / sizeof(struct lcdc_cabc_mode);
3787
3788         dev_drv->cabc_mode = mode;
3789 #if 0/*ndef CONFIG_RK_FPGA*/
3790         /* iomux connect to vop or pwm */
3791         if (mode == 0) {
3792                 DBG(3, "close cabc and select rk pwm\n");
3793                 val = 0x30002;
3794                 writel_relaxed(val, RK_GRF_VIRT + rk3368_GRF_GPIO3C_IOMUX);
3795                 cabc_en = 0;
3796         } else if (mode > 0 && mode <= max_mode_num) {
3797                 DBG(3, "open cabc and select vop pwm\n");
3798                 val = 0x30003;
3799                 writel_relaxed(val, RK_GRF_VIRT + rk3368_GRF_GPIO3C_IOMUX);
3800                 cabc_en = 1;
3801         } else if (mode > 0x10 && mode <= (max_mode_num + 0x10)) {
3802                 DBG(3, "open cabc and select rk pwm\n");
3803                 val = 0x30003;
3804                 writel_relaxed(val, RK_GRF_VIRT + rk3368_GRF_GPIO3C_IOMUX);
3805                 cabc_en = 1;
3806                 mode -= 0x10;
3807         } else if (mode == 0xff) {
3808                 DBG(3, "close cabc and select vop pwm\n");
3809                 val = 0x30002;
3810                 writel_relaxed(val, RK_GRF_VIRT + rk3368_GRF_GPIO3C_IOMUX);
3811                 cabc_en = 0;
3812         } else {
3813                 dev_err(lcdc_dev->dev, "invalid cabc mode value:%d", mode);
3814                 return 0;
3815         }
3816 #endif
3817         if (cabc_en == 0) {
3818                 spin_lock(&lcdc_dev->reg_lock);
3819                 if (lcdc_dev->clk_on) {
3820                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
3821                                      m_CABC_EN, v_CABC_EN(0));
3822                         lcdc_cfg_done(lcdc_dev);
3823                 }
3824                 spin_unlock(&lcdc_dev->reg_lock);
3825                 return 0;
3826         }
3827
3828         total_pixel = screen->mode.xres * screen->mode.yres;
3829         pixel_num = 1000 - (cabc_mode[mode - 1].pixel_num);
3830         calc_pixel = (total_pixel * pixel_num) / 1000;
3831         stage_up = cabc_mode[mode - 1].stage_up;
3832         stage_down = cabc_mode[mode - 1].stage_down;
3833         global_su = cabc_mode[mode - 1].global_su;
3834
3835         stage_up_rec = 256 * 256 / stage_up;
3836         stage_down_rec = 256 * 256 / stage_down;
3837         global_su_rec = 256 * 256 / global_su;
3838
3839         spin_lock(&lcdc_dev->reg_lock);
3840         if (lcdc_dev->clk_on) {
3841                 mask = m_CABC_CALC_PIXEL_NUM;
3842                 val = v_CABC_CALC_PIXEL_NUM(calc_pixel);
3843                 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3844
3845                 mask = m_CABC_TOTAL_PIXEL_NUM;
3846                 val = v_CABC_TOTAL_PIXEL_NUM(total_pixel);
3847                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3848
3849                 mask = m_CABC_STAGE_UP | m_CABC_STAGE_UP_REC |
3850                     m_CABC_GLOBAL_SU_LIMIT_EN | m_CABC_GLOBAL_SU_REC;
3851                 val = v_CABC_STAGE_UP(stage_up) |
3852                     v_CABC_STAGE_UP_REC(stage_up_rec) |
3853                     v_CABC_GLOBAL_SU_LIMIT_EN(1) |
3854                     v_CABC_GLOBAL_SU_REC(global_su_rec);
3855                 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
3856
3857                 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_DOWN_REC |
3858                     m_CABC_GLOBAL_SU;
3859                 val = v_CABC_STAGE_DOWN(stage_down) |
3860                     v_CABC_STAGE_DOWN_REC(stage_down_rec) |
3861                     v_CABC_GLOBAL_SU(global_su);
3862                 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
3863                 lcdc_cfg_done(lcdc_dev);
3864         }
3865         spin_unlock(&lcdc_dev->reg_lock);
3866
3867         return 0;
3868 }
3869
3870 /*
3871         a:[-30~0]:
3872             sin_hue = sin(a)*256 +0x100;
3873             cos_hue = cos(a)*256;
3874         a:[0~30]
3875             sin_hue = sin(a)*256;
3876             cos_hue = cos(a)*256;
3877 */
3878 static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3879                                     bcsh_hue_mode mode)
3880 {
3881         struct lcdc_device *lcdc_dev =
3882             container_of(dev_drv, struct lcdc_device, driver);
3883         u32 val;
3884
3885         spin_lock(&lcdc_dev->reg_lock);
3886         if (lcdc_dev->clk_on) {
3887                 val = lcdc_readl(lcdc_dev, BCSH_H);
3888                 switch (mode) {
3889                 case H_SIN:
3890                         val &= m_BCSH_SIN_HUE;
3891                         break;
3892                 case H_COS:
3893                         val &= m_BCSH_COS_HUE;
3894                         val >>= 16;
3895                         break;
3896                 default:
3897                         break;
3898                 }
3899         }
3900         spin_unlock(&lcdc_dev->reg_lock);
3901
3902         return val;
3903 }
3904
3905 static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3906                                     int sin_hue, int cos_hue)
3907 {
3908         struct lcdc_device *lcdc_dev =
3909             container_of(dev_drv, struct lcdc_device, driver);
3910         u32 mask, val;
3911
3912         spin_lock(&lcdc_dev->reg_lock);
3913         if (lcdc_dev->clk_on) {
3914                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
3915                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
3916                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
3917                 lcdc_cfg_done(lcdc_dev);
3918         }
3919         spin_unlock(&lcdc_dev->reg_lock);
3920
3921         return 0;
3922 }
3923
3924 static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
3925                                     bcsh_bcs_mode mode, int value)
3926 {
3927         struct lcdc_device *lcdc_dev =
3928             container_of(dev_drv, struct lcdc_device, driver);
3929         u32 mask, val;
3930
3931         spin_lock(&lcdc_dev->reg_lock);
3932         if (lcdc_dev->clk_on) {
3933                 switch (mode) {
3934                 case BRIGHTNESS:
3935                         /*from 0 to 255,typical is 128 */
3936                         if (value < 0x80)
3937                                 value += 0x80;
3938                         else if (value >= 0x80)
3939                                 value = value - 0x80;
3940                         mask = m_BCSH_BRIGHTNESS;
3941                         val = v_BCSH_BRIGHTNESS(value);
3942                         break;
3943                 case CONTRAST:
3944                         /*from 0 to 510,typical is 256 */
3945                         mask = m_BCSH_CONTRAST;
3946                         val = v_BCSH_CONTRAST(value);
3947                         break;
3948                 case SAT_CON:
3949                         /*from 0 to 1015,typical is 256 */
3950                         mask = m_BCSH_SAT_CON;
3951                         val = v_BCSH_SAT_CON(value);
3952                         break;
3953                 default:
3954                         break;
3955                 }
3956                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
3957                 lcdc_cfg_done(lcdc_dev);
3958         }
3959         spin_unlock(&lcdc_dev->reg_lock);
3960         return val;
3961 }
3962
3963 static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
3964                                     bcsh_bcs_mode mode)
3965 {
3966         struct lcdc_device *lcdc_dev =
3967             container_of(dev_drv, struct lcdc_device, driver);
3968         u32 val;
3969
3970         spin_lock(&lcdc_dev->reg_lock);
3971         if (lcdc_dev->clk_on) {
3972                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
3973                 switch (mode) {
3974                 case BRIGHTNESS:
3975                         val &= m_BCSH_BRIGHTNESS;
3976                         if (val > 0x80)
3977                                 val -= 0x80;
3978                         else
3979                                 val += 0x80;
3980                         break;
3981                 case CONTRAST:
3982                         val &= m_BCSH_CONTRAST;
3983                         val >>= 8;
3984                         break;
3985                 case SAT_CON:
3986                         val &= m_BCSH_SAT_CON;
3987                         val >>= 20;
3988                         break;
3989                 default:
3990                         break;
3991                 }
3992         }
3993         spin_unlock(&lcdc_dev->reg_lock);
3994         return val;
3995 }
3996
3997 static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
3998 {
3999         struct lcdc_device *lcdc_dev =
4000             container_of(dev_drv, struct lcdc_device, driver);
4001         u32 mask, val;
4002
4003         spin_lock(&lcdc_dev->reg_lock);
4004         if (lcdc_dev->clk_on) {
4005                 if (open) {
4006                         lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1);
4007                         lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
4008                         lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
4009                         dev_drv->bcsh.enable = 1;
4010                 } else {
4011                         mask = m_BCSH_EN;
4012                         val = v_BCSH_EN(0);
4013                         lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
4014                         dev_drv->bcsh.enable = 0;
4015                 }
4016                 rk3368_lcdc_bcsh_path_sel(dev_drv);
4017                 lcdc_cfg_done(lcdc_dev);
4018         }
4019         spin_unlock(&lcdc_dev->reg_lock);
4020         return 0;
4021 }
4022
4023 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4024 {
4025         if (!enable || !dev_drv->bcsh.enable) {
4026                 rk3368_lcdc_open_bcsh(dev_drv, false);
4027                 return 0;
4028         }
4029
4030         if (dev_drv->bcsh.brightness <= 255 ||
4031             dev_drv->bcsh.contrast <= 510 ||
4032             dev_drv->bcsh.sat_con <= 1015 ||
4033             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4034                 rk3368_lcdc_open_bcsh(dev_drv, true);
4035                 if (dev_drv->bcsh.brightness <= 255)
4036                         rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4037                                                  dev_drv->bcsh.brightness);
4038                 if (dev_drv->bcsh.contrast <= 510)
4039                         rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
4040                                                  dev_drv->bcsh.contrast);
4041                 if (dev_drv->bcsh.sat_con <= 1015)
4042                         rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
4043                                                  dev_drv->bcsh.sat_con);
4044                 if (dev_drv->bcsh.sin_hue <= 511 &&
4045                     dev_drv->bcsh.cos_hue <= 511)
4046                         rk3368_lcdc_set_bcsh_hue(dev_drv,
4047                                                  dev_drv->bcsh.sin_hue,
4048                                                  dev_drv->bcsh.cos_hue);
4049         }
4050         return 0;
4051 }
4052
4053 static int rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4054 {
4055         struct lcdc_device *lcdc_dev =
4056             container_of(dev_drv, struct lcdc_device, driver);
4057
4058         if (enable) {
4059                 spin_lock(&lcdc_dev->reg_lock);
4060                 if (likely(lcdc_dev->clk_on)) {
4061                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4062                                      v_DSP_BLACK_EN(1));
4063                         lcdc_cfg_done(lcdc_dev);
4064                 }
4065                 spin_unlock(&lcdc_dev->reg_lock);
4066         } else {
4067                 spin_lock(&lcdc_dev->reg_lock);
4068                 if (likely(lcdc_dev->clk_on)) {
4069                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4070                                      v_DSP_BLACK_EN(0));
4071
4072                         lcdc_cfg_done(lcdc_dev);
4073                 }
4074                 spin_unlock(&lcdc_dev->reg_lock);
4075         }
4076
4077         return 0;
4078 }
4079
4080
4081 static int rk3368_lcdc_backlight_close(struct rk_lcdc_driver *dev_drv,
4082                                        int enable)
4083 {
4084         struct lcdc_device *lcdc_dev =
4085             container_of(dev_drv, struct lcdc_device, driver);
4086
4087         rk3368_lcdc_get_backlight_device(dev_drv);
4088
4089         if (enable) {
4090                 /* close the backlight */
4091                 if (lcdc_dev->backlight) {
4092                         lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4093                         backlight_update_status(lcdc_dev->backlight);
4094                 }
4095                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4096                         dev_drv->trsm_ops->disable();
4097         } else {
4098                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4099                         dev_drv->trsm_ops->enable();
4100                 msleep(100);
4101                 /* open the backlight */
4102                 if (lcdc_dev->backlight) {
4103                         lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
4104                         backlight_update_status(lcdc_dev->backlight);
4105                 }
4106         }
4107
4108         return 0;
4109 }
4110
4111 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4112         .open = rk3368_lcdc_open,
4113         .win_direct_en = rk3368_lcdc_win_direct_en,
4114         .load_screen = rk3368_load_screen,
4115         .set_par = rk3368_lcdc_set_par,
4116         .pan_display = rk3368_lcdc_pan_display,
4117         .direct_set_addr = rk3368_lcdc_direct_set_win_addr,
4118         /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/
4119         .blank = rk3368_lcdc_blank,
4120         .ioctl = rk3368_lcdc_ioctl,
4121         .suspend = rk3368_lcdc_early_suspend,
4122         .resume = rk3368_lcdc_early_resume,
4123         .get_win_state = rk3368_lcdc_get_win_state,
4124         .ovl_mgr = rk3368_lcdc_ovl_mgr,
4125         .get_disp_info = rk3368_lcdc_get_disp_info,
4126         .fps_mgr = rk3368_lcdc_fps_mgr,
4127         .fb_get_win_id = rk3368_lcdc_get_win_id,
4128         .fb_win_remap = rk3368_fb_win_remap,
4129         .set_dsp_lut = rk3368_set_dsp_lut,
4130         .poll_vblank = rk3368_lcdc_poll_vblank,
4131         .dpi_open = rk3368_lcdc_dpi_open,
4132         .dpi_win_sel = rk3368_lcdc_dpi_win_sel,
4133         .dpi_status = rk3368_lcdc_dpi_status,
4134         .get_dsp_addr = rk3368_lcdc_get_dsp_addr,
4135         .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc,
4136         .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue,
4137         .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs,
4138         .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue,
4139         .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs,
4140         .open_bcsh = rk3368_lcdc_open_bcsh,
4141         .dump_reg = rk3368_lcdc_reg_dump,
4142         .cfg_done = rk3368_lcdc_config_done,
4143         .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu,
4144         .dsp_black = rk3368_lcdc_dsp_black,
4145         .backlight_close = rk3368_lcdc_backlight_close,
4146         .mmu_en    = rk3368_lcdc_mmu_en,
4147 };
4148
4149 #ifdef LCDC_IRQ_EMPTY_DEBUG
4150 static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev,
4151                                  unsigned int intr_status)
4152 {
4153         if (intr_status & m_WIN0_EMPTY_INTR_STS) {
4154                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN0_EMPTY_INTR_CLR,
4155                              v_WIN0_EMPTY_INTR_CLR(1));
4156                 dev_warn(lcdc_dev->dev, "win0 empty irq!");
4157         } else if (intr_status & m_WIN1_EMPTY_INTR_STS) {
4158                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN1_EMPTY_INTR_CLR,
4159                              v_WIN1_EMPTY_INTR_CLR(1));
4160                 dev_warn(lcdc_dev->dev, "win1 empty irq!");
4161         } else if (intr_status & m_WIN2_EMPTY_INTR_STS) {
4162                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN2_EMPTY_INTR_CLR,
4163                              v_WIN2_EMPTY_INTR_CLR(1));
4164                 dev_warn(lcdc_dev->dev, "win2 empty irq!");
4165         } else if (intr_status & m_WIN3_EMPTY_INTR_STS) {
4166                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN3_EMPTY_INTR_CLR,
4167                              v_WIN3_EMPTY_INTR_CLR(1));
4168                 dev_warn(lcdc_dev->dev, "win3 empty irq!");
4169         } else if (intr_status & m_HWC_EMPTY_INTR_STS) {
4170                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_HWC_EMPTY_INTR_CLR,
4171                              v_HWC_EMPTY_INTR_CLR(1));
4172                 dev_warn(lcdc_dev->dev, "HWC empty irq!");
4173         } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) {
4174                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_POST_BUF_EMPTY_INTR_CLR,
4175                              v_POST_BUF_EMPTY_INTR_CLR(1));
4176                 dev_warn(lcdc_dev->dev, "post buf empty irq!");
4177         } else if (intr_status & m_PWM_GEN_INTR_STS) {
4178                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_PWM_GEN_INTR_CLR,
4179                              v_PWM_GEN_INTR_CLR(1));
4180                 dev_warn(lcdc_dev->dev, "PWM gen irq!");
4181         }
4182         return 0;
4183 }
4184 #endif
4185
4186 static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id)
4187 {
4188         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
4189         ktime_t timestamp = ktime_get();
4190         u32 intr_status;
4191
4192         intr_status = lcdc_readl(lcdc_dev, INTR_STATUS);
4193
4194         if (intr_status & m_FS_INTR_STS) {
4195                 timestamp = ktime_get();
4196                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_INTR_CLR,
4197                              v_FS_INTR_CLR(1));
4198                 /*if(lcdc_dev->driver.wait_fs){ */
4199                 if (0) {
4200                         spin_lock(&(lcdc_dev->driver.cpl_lock));
4201                         complete(&(lcdc_dev->driver.frame_done));
4202                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
4203                 }
4204 #ifdef CONFIG_DRM_ROCKCHIP
4205                 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
4206 #endif
4207                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4208                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
4209
4210         } else if (intr_status & m_LINE_FLAG0_INTR_STS) {
4211                 lcdc_dev->driver.frame_time.last_framedone_t =
4212                     lcdc_dev->driver.frame_time.framedone_t;
4213                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4214                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG0_INTR_CLR,
4215                              v_LINE_FLAG0_INTR_CLR(1));
4216         } else if (intr_status & m_LINE_FLAG1_INTR_STS) {
4217                 /*line flag1 */
4218                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG1_INTR_CLR,
4219                              v_LINE_FLAG1_INTR_CLR(1));
4220         } else if (intr_status & m_FS_NEW_INTR_STS) {
4221                 /*new frame start */
4222                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_NEW_INTR_CLR,
4223                              v_FS_NEW_INTR_CLR(1));
4224         } else if (intr_status & m_BUS_ERROR_INTR_STS) {
4225                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_BUS_ERROR_INTR_CLR,
4226                              v_BUS_ERROR_INTR_CLR(1));
4227                 dev_warn(lcdc_dev->dev, "bus error!");
4228         }
4229
4230         /* for win empty debug */
4231 #ifdef LCDC_IRQ_EMPTY_DEBUG
4232         rk3368_lcdc_parse_irq(lcdc_dev, intr_status);
4233 #endif
4234         return IRQ_HANDLED;
4235 }
4236
4237 #if defined(CONFIG_PM)
4238 static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
4239 {
4240         return 0;
4241 }
4242
4243 static int rk3368_lcdc_resume(struct platform_device *pdev)
4244 {
4245         return 0;
4246 }
4247 #else
4248 #define rk3368_lcdc_suspend NULL
4249 #define rk3368_lcdc_resume  NULL
4250 #endif
4251
4252 static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4253 {
4254         struct device_node *np = lcdc_dev->dev->of_node;
4255         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4256         int val;
4257
4258         if (of_property_read_u32(np, "rockchip,prop", &val))
4259                 lcdc_dev->prop = PRMRY; /*default set it as primary */
4260         else
4261                 lcdc_dev->prop = val;
4262
4263         if (of_property_read_u32(np, "rockchip,mirror", &val))
4264                 dev_drv->rotate_mode = NO_MIRROR;
4265         else
4266                 dev_drv->rotate_mode = val;
4267
4268         if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4269                 dev_drv->cabc_mode = 0; /* default set close cabc */
4270         else
4271                 dev_drv->cabc_mode = val;
4272
4273         if (of_property_read_u32(np, "rockchip,pwr18", &val))
4274                 /*default set it as 3.xv power supply */
4275                 lcdc_dev->pwr18 = false;
4276         else
4277                 lcdc_dev->pwr18 = (val ? true : false);
4278
4279         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4280                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4281         else
4282                 dev_drv->fb_win_map = val;
4283
4284         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4285                 dev_drv->bcsh.enable = false;
4286         else
4287                 dev_drv->bcsh.enable = (val ? true : false);
4288
4289         if (of_property_read_u32(np, "rockchip,brightness", &val))
4290                 dev_drv->bcsh.brightness = 0xffff;
4291         else
4292                 dev_drv->bcsh.brightness = val;
4293
4294         if (of_property_read_u32(np, "rockchip,contrast", &val))
4295                 dev_drv->bcsh.contrast = 0xffff;
4296         else
4297                 dev_drv->bcsh.contrast = val;
4298
4299         if (of_property_read_u32(np, "rockchip,sat-con", &val))
4300                 dev_drv->bcsh.sat_con = 0xffff;
4301         else
4302                 dev_drv->bcsh.sat_con = val;
4303
4304         if (of_property_read_u32(np, "rockchip,hue", &val)) {
4305                 dev_drv->bcsh.sin_hue = 0xffff;
4306                 dev_drv->bcsh.cos_hue = 0xffff;
4307         } else {
4308                 dev_drv->bcsh.sin_hue = val & 0xff;
4309                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4310         }
4311
4312 #if defined(CONFIG_ROCKCHIP_IOMMU)
4313         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4314                 dev_drv->iommu_enabled = 0;
4315         else
4316                 dev_drv->iommu_enabled = val;
4317 #else
4318         dev_drv->iommu_enabled = 0;
4319 #endif
4320         return 0;
4321 }
4322
4323 static int rk3368_lcdc_probe(struct platform_device *pdev)
4324 {
4325         struct lcdc_device *lcdc_dev = NULL;
4326         struct rk_lcdc_driver *dev_drv;
4327         struct device *dev = &pdev->dev;
4328         struct resource *res;
4329         struct device_node *np = pdev->dev.of_node;
4330         int prop;
4331         int ret = 0;
4332
4333         /*if the primary lcdc has not registered ,the extend
4334            lcdc register later */
4335         of_property_read_u32(np, "rockchip,prop", &prop);
4336         if (prop == EXTEND) {
4337                 if (!is_prmry_rk_lcdc_registered())
4338                         return -EPROBE_DEFER;
4339         }
4340         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
4341         if (!lcdc_dev) {
4342                 dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!");
4343                 return -ENOMEM;
4344         }
4345         platform_set_drvdata(pdev, lcdc_dev);
4346         lcdc_dev->dev = dev;
4347         rk3368_lcdc_parse_dt(lcdc_dev);
4348         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4349         lcdc_dev->reg_phy_base = res->start;
4350         lcdc_dev->len = resource_size(res);
4351         lcdc_dev->regs = devm_ioremap_resource(dev, res);
4352         if (IS_ERR(lcdc_dev->regs))
4353                 return PTR_ERR(lcdc_dev->regs);
4354         else
4355                 dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs);
4356
4357         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4358         if (IS_ERR(lcdc_dev->regsbak))
4359                 return PTR_ERR(lcdc_dev->regsbak);
4360         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4361         lcdc_dev->id = 0;
4362         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4363         dev_drv = &lcdc_dev->driver;
4364         dev_drv->dev = dev;
4365         dev_drv->prop = prop;
4366         dev_drv->id = lcdc_dev->id;
4367         dev_drv->ops = &lcdc_drv_ops;
4368         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4369         spin_lock_init(&lcdc_dev->reg_lock);
4370
4371         lcdc_dev->irq = platform_get_irq(pdev, 0);
4372         if (lcdc_dev->irq < 0) {
4373                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4374                         lcdc_dev->id);
4375                 return -ENXIO;
4376         }
4377
4378         ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr,
4379                                IRQF_DISABLED | IRQF_SHARED,
4380                                dev_name(dev), lcdc_dev);
4381         if (ret) {
4382                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4383                         lcdc_dev->irq, ret);
4384                 return ret;
4385         }
4386
4387         if (dev_drv->iommu_enabled) {
4388                 if (lcdc_dev->id == 0) {
4389                         strcpy(dev_drv->mmu_dts_name,
4390                                VOPB_IOMMU_COMPATIBLE_NAME);
4391                 } else {
4392                         strcpy(dev_drv->mmu_dts_name,
4393                                VOPL_IOMMU_COMPATIBLE_NAME);
4394                 }
4395         }
4396
4397         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4398         if (ret < 0) {
4399                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4400                 return ret;
4401         }
4402         lcdc_dev->screen = dev_drv->screen0;
4403         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4404                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4405
4406         return 0;
4407 }
4408
4409 static int rk3368_lcdc_remove(struct platform_device *pdev)
4410 {
4411         return 0;
4412 }
4413
4414 static void rk3368_lcdc_shutdown(struct platform_device *pdev)
4415 {
4416         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
4417
4418         rk3368_lcdc_deint(lcdc_dev);
4419         rk_disp_pwr_disable(&lcdc_dev->driver);
4420 }
4421
4422 #if defined(CONFIG_OF)
4423 static const struct of_device_id rk3368_lcdc_dt_ids[] = {
4424         {.compatible = "rockchip,rk3368-lcdc",},
4425         {}
4426 };
4427 #endif
4428
4429 static struct platform_driver rk3368_lcdc_driver = {
4430         .probe = rk3368_lcdc_probe,
4431         .remove = rk3368_lcdc_remove,
4432         .driver = {
4433                    .name = "rk3368-lcdc",
4434                    .owner = THIS_MODULE,
4435                    .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids),
4436                    },
4437         .suspend = rk3368_lcdc_suspend,
4438         .resume = rk3368_lcdc_resume,
4439         .shutdown = rk3368_lcdc_shutdown,
4440 };
4441
4442 static int __init rk3368_lcdc_module_init(void)
4443 {
4444         return platform_driver_register(&rk3368_lcdc_driver);
4445 }
4446
4447 static void __exit rk3368_lcdc_module_exit(void)
4448 {
4449         platform_driver_unregister(&rk3368_lcdc_driver);
4450 }
4451
4452 fs_initcall(rk3368_lcdc_module_init);
4453 module_exit(rk3368_lcdc_module_exit);