drivers/video/rockchip/lcdc/rk3368_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3368_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *Author:hjc<hjc@rock-chips.com>
   6  *This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk3368_lcdc.h"
  39
  40 #if defined(CONFIG_HAS_EARLYSUSPEND)
  41 #include <linux/earlysuspend.h>
  42 #endif
  43 /*#define CONFIG_RK_FPGA 1*/
  44
  45 static int dbg_thresd;
  46 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  47
  48 #define DBG(level, x...) do {                   \
  49         if (unlikely(dbg_thresd >= level))      \
  50                 pr_info(x);\
  51         } while (0)
  52
  53 static struct rk_lcdc_win lcdc_win[] = {
  54         [0] = {
  55                .name = "win0",
  56                .id = 0,
  57                .support_3d = false,
  58                },
  59         [1] = {
  60                .name = "win1",
  61                .id = 1,
  62                .support_3d = false,
  63                },
  64         [2] = {
  65                .name = "win2",
  66                .id = 2,
  67                .support_3d = false,
  68                },
  69         [3] = {
  70                .name = "win3",
  71                .id = 3,
  72                .support_3d = false,
  73                },
  74         [4] = {
  75                .name = "hwc",
  76                .id = 4,
  77                .support_3d = false,
  78                }
  79 };
  80
  81 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
  82
  83 /*#define WAIT_FOR_SYNC 1*/
  84 u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth)
  85 {
  86         u32 vscalednmult;
  87
  88         if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  89                 vscalednmult = 4;
  90         else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  91                 vscalednmult = 2;
  92         else
  93                 vscalednmult = 1;
  94
  95         return vscalednmult;
  96 }
  97
  98
  99 static int rk3368_set_cabc_lut(struct rk_lcdc_driver *dev_drv, int *cabc_lut)
 100 {
 101         int i;
 102         int __iomem *c;
 103         u32 v;
 104         struct lcdc_device *lcdc_dev =
 105             container_of(dev_drv, struct lcdc_device, driver);
 106
 107         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 108                      v_CABC_LUT_EN(0));
 109         lcdc_cfg_done(lcdc_dev);
 110         mdelay(25);
 111         for (i = 0; i < 256; i++) {
 112                 v = cabc_lut[i];
 113                 c = lcdc_dev->cabc_lut_addr_base + i;
 114                 writel_relaxed(v, c);
 115         }
 116         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 117                      v_CABC_LUT_EN(1));
 118         return 0;
 119 }
 120
 121
 122 static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
 123 {
 124         int i;
 125         int __iomem *c;
 126         u32 v;
 127         struct lcdc_device *lcdc_dev =
 128             container_of(dev_drv, struct lcdc_device, driver);
 129
 130         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 131                      v_DSP_LUT_EN(0));
 132         lcdc_cfg_done(lcdc_dev);
 133         mdelay(25);
 134         for (i = 0; i < 256; i++) {
 135                 v = dsp_lut[i];
 136                 c = lcdc_dev->dsp_lut_addr_base + i;
 137                 writel_relaxed(v, c);
 138         }
 139         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 140                      v_DSP_LUT_EN(1));
 141
 142         return 0;
 143 }
 144
 145 static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 146 {
 147 #ifdef CONFIG_RK_FPGA
 148         lcdc_dev->clk_on = 1;
 149         return 0;
 150 #endif
 151         if (!lcdc_dev->clk_on) {
 152                 clk_prepare_enable(lcdc_dev->hclk);
 153                 clk_prepare_enable(lcdc_dev->dclk);
 154                 clk_prepare_enable(lcdc_dev->aclk);
 155                 clk_prepare_enable(lcdc_dev->pd);
 156                 spin_lock(&lcdc_dev->reg_lock);
 157                 lcdc_dev->clk_on = 1;
 158                 spin_unlock(&lcdc_dev->reg_lock);
 159         }
 160
 161         return 0;
 162 }
 163
 164 static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 165 {
 166 #ifdef CONFIG_RK_FPGA
 167         lcdc_dev->clk_on = 0;
 168         return 0;
 169 #endif
 170         if (lcdc_dev->clk_on) {
 171                 spin_lock(&lcdc_dev->reg_lock);
 172                 lcdc_dev->clk_on = 0;
 173                 spin_unlock(&lcdc_dev->reg_lock);
 174                 mdelay(25);
 175                 clk_disable_unprepare(lcdc_dev->dclk);
 176                 clk_disable_unprepare(lcdc_dev->hclk);
 177                 clk_disable_unprepare(lcdc_dev->aclk);
 178                 clk_disable_unprepare(lcdc_dev->pd);
 179         }
 180
 181         return 0;
 182 }
 183
 184 static int __maybe_unused
 185         rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 186 {
 187         u32 mask, val;
 188
 189         spin_lock(&lcdc_dev->reg_lock);
 190         if (likely(lcdc_dev->clk_on)) {
 191                 mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN |
 192                     m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN |
 193                     m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN |
 194                     m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
 195                     m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
 196                     m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
 197                     m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN;
 198                 val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) |
 199                     v_ADDR_SAME_INTR_EN(0) |
 200                     v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) |
 201                     v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) |
 202                     v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) |
 203                     v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) |
 204                     v_POST_BUF_EMPTY_INTR_EN(0) |
 205                     v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0);
 206                 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
 207
 208                 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR |
 209                     m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
 210                     m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR |
 211                     m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
 212                     m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
 213                     m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
 214                     m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR;
 215                 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
 216                     v_ADDR_SAME_INTR_CLR(1) |
 217                     v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) |
 218                     v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) |
 219                     v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) |
 220                     v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) |
 221                     v_POST_BUF_EMPTY_INTR_CLR(1) |
 222                     v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1);
 223                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
 224                 lcdc_cfg_done(lcdc_dev);
 225                 spin_unlock(&lcdc_dev->reg_lock);
 226         } else {
 227                 spin_unlock(&lcdc_dev->reg_lock);
 228         }
 229         mdelay(1);
 230         return 0;
 231 }
 232
 233 static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
 234 {
 235         struct lcdc_device *lcdc_dev =
 236             container_of(dev_drv, struct lcdc_device, driver);
 237         int *cbase = (int *)lcdc_dev->regs;
 238         int *regsbak = (int *)lcdc_dev->regsbak;
 239         int i, j, val;
 240         char dbg_message[30];
 241         char buf[10];
 242
 243         pr_info("lcd back up reg:\n");
 244         memset(dbg_message, 0, sizeof(dbg_message));
 245         memset(buf, 0, sizeof(buf));
 246         for (i = 0; i <= (0x200 >> 4); i++) {
 247                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 248                 for (j = 0; j < 4; j++) {
 249                         val = sprintf(buf, "%08x  ", *(regsbak + i * 4 + j));
 250                         strcat(dbg_message, buf);
 251                 }
 252                 pr_info("%s\n", dbg_message);
 253                 memset(dbg_message, 0, sizeof(dbg_message));
 254                 memset(buf, 0, sizeof(buf));
 255         }
 256
 257         pr_info("lcdc reg:\n");
 258         for (i = 0; i <= (0x200 >> 4); i++) {
 259                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 260                 for (j = 0; j < 4; j++) {
 261                         sprintf(buf, "%08x  ",
 262                                 readl_relaxed(cbase + i * 4 + j));
 263                         strcat(dbg_message, buf);
 264                 }
 265                 pr_info("%s\n", dbg_message);
 266                 memset(dbg_message, 0, sizeof(dbg_message));
 267                 memset(buf, 0, sizeof(buf));
 268         }
 269
 270         return 0;
 271 }
 272
 273 #define WIN_EN(id)              \
 274 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en)       \
 275 { \
 276         u32 msk, val;                                                   \
 277         spin_lock(&lcdc_dev->reg_lock);                                 \
 278         msk =  m_WIN##id##_EN;                                          \
 279         val  =  v_WIN##id##_EN(en);                                     \
 280         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);              \
 281         lcdc_cfg_done(lcdc_dev);                                        \
 282         val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);            \
 283         while (val !=  (!!en))  {                                       \
 284                 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);    \
 285         }                                                               \
 286         spin_unlock(&lcdc_dev->reg_lock);                               \
 287         return 0;                                                       \
 288 }
 289
 290 WIN_EN(0);
 291 WIN_EN(1);
 292 WIN_EN(2);
 293 WIN_EN(3);
 294 /*enable/disable win directly*/
 295 static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv,
 296                                      int win_id, int en)
 297 {
 298         struct lcdc_device *lcdc_dev =
 299             container_of(drv, struct lcdc_device, driver);
 300         if (win_id == 0)
 301                 win0_enable(lcdc_dev, en);
 302         else if (win_id == 1)
 303                 win1_enable(lcdc_dev, en);
 304         else if (win_id == 2)
 305                 win2_enable(lcdc_dev, en);
 306         else if (win_id == 3)
 307                 win3_enable(lcdc_dev, en);
 308         else
 309                 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
 310         return 0;
 311 }
 312
 313 #define SET_WIN_ADDR(id) \
 314 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
 315 {                                                       \
 316         u32 msk, val;                                   \
 317         spin_lock(&lcdc_dev->reg_lock);                 \
 318         lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr);        \
 319         msk =  m_WIN##id##_EN;                          \
 320         val  =  v_WIN0_EN(1);                           \
 321         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);      \
 322         lcdc_cfg_done(lcdc_dev);                        \
 323         spin_unlock(&lcdc_dev->reg_lock);               \
 324         return 0;                                       \
 325 }
 326
 327 SET_WIN_ADDR(0);
 328 SET_WIN_ADDR(1);
 329 int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
 330                                     int win_id, u32 addr)
 331 {
 332         struct lcdc_device *lcdc_dev =
 333             container_of(dev_drv, struct lcdc_device, driver);
 334         if (win_id == 0)
 335                 set_win0_addr(lcdc_dev, addr);
 336         else
 337                 set_win1_addr(lcdc_dev, addr);
 338
 339         return 0;
 340 }
 341
 342 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 343 {
 344         int reg = 0;
 345         u32 val = 0;
 346         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 347         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 348         u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 349         u32 st_x, st_y;
 350         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 351
 352         spin_lock(&lcdc_dev->reg_lock);
 353         for (reg = 0; reg < SCAN_LINE_NUM; reg += 4) {
 354                 val = lcdc_readl_backup(lcdc_dev, reg);
 355                 switch (reg) {
 356                 case WIN0_ACT_INFO:
 357                         win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1;
 358                         win0->area[0].yact =
 359                             ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
 360                         break;
 361                 case WIN0_DSP_INFO:
 362                         win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1;
 363                         win0->area[0].ysize =
 364                             ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
 365                         break;
 366                 case WIN0_DSP_ST:
 367                         st_x = val & m_WIN0_DSP_XST;
 368                         st_y = (val & m_WIN0_DSP_YST) >> 16;
 369                         win0->area[0].xpos = st_x - h_pw_bp;
 370                         win0->area[0].ypos = st_y - v_pw_bp;
 371                         break;
 372                 case WIN0_CTRL0:
 373                         win0->state = val & m_WIN0_EN;
 374                         win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1;
 375                         win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
 376                         win0->area[0].format = win0->area[0].fmt_cfg;
 377                         break;
 378                 case WIN0_VIR:
 379                         win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE;
 380                         win0->area[0].uv_vir_stride =
 381                             (val & m_WIN0_VIR_STRIDE_UV) >> 16;
 382                         if (win0->area[0].format == ARGB888)
 383                                 win0->area[0].xvir = win0->area[0].y_vir_stride;
 384                         else if (win0->area[0].format == RGB888)
 385                                 win0->area[0].xvir =
 386                                     win0->area[0].y_vir_stride * 4 / 3;
 387                         else if (win0->area[0].format == RGB565)
 388                                 win0->area[0].xvir =
 389                                     2 * win0->area[0].y_vir_stride;
 390                         else    /* YUV */
 391                                 win0->area[0].xvir =
 392                                     4 * win0->area[0].y_vir_stride;
 393                         break;
 394                 case WIN0_YRGB_MST:
 395                         win0->area[0].smem_start = val;
 396                         break;
 397                 case WIN0_CBR_MST:
 398                         win0->area[0].cbr_start = val;
 399                         break;
 400                 default:
 401                         break;
 402                 }
 403         }
 404         spin_unlock(&lcdc_dev->reg_lock);
 405 }
 406
 407 /********do basic init*********/
 408 static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 409 {
 410         u32 mask, val, v;
 411         struct lcdc_device *lcdc_dev =
 412             container_of(dev_drv, struct lcdc_device, driver);
 413         if (lcdc_dev->pre_init)
 414                 return 0;
 415
 416         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 417         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 418         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 419         lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
 420
 421         if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||
 422             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 423                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 424                         lcdc_dev->id);
 425         }
 426
 427         rk_disp_pwr_enable(dev_drv);
 428         rk3368_lcdc_clk_enable(lcdc_dev);
 429
 430         /*backup reg config at uboot */
 431         lcdc_read_reg_defalut_cfg(lcdc_dev);
 432         if (lcdc_dev->pwr18 == 1) {
 433                 v = 0x00200020; /*bit5: 1,1.8v;0,3.3v*/
 434                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 435                                 PMUGRF_SOC_CON0_VOP, v);
 436         } else {
 437                 v = 0x00200000; /*bit5: 1,1.8v;0,3.3v*/
 438                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 439                                 PMUGRF_SOC_CON0_VOP, v);
 440         }
 441 #if 0
 442         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_0, 0x15110903);
 443         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_1, 0x00030911);
 444         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_0, 0x1a150b04);
 445         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_1, 0x00040b15);
 446         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_0, 0x15110903);
 447         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_1, 0x00030911);
 448 #else
 449         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_0, 0x40000000);
 450         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_1, 0x0);
 451         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_0, 0x80000000);
 452         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_1, 0x0);
 453         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_0, 0x40000000);
 454         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_1, 0x0);
 455 #endif
 456         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 457         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 458         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696);
 459         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969);
 460         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 461         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 462
 463         mask = m_AUTO_GATING_EN;
 464         val = v_AUTO_GATING_EN(0);
 465         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 466         mask = m_DITHER_UP_EN;
 467         val = v_DITHER_UP_EN(1);
 468         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
 469         lcdc_cfg_done(lcdc_dev);
 470         /*disable win0 to workaround iommu pagefault */
 471         /*if (dev_drv->iommu_enabled) */
 472         /*      win0_enable(lcdc_dev, 0); */
 473         lcdc_dev->pre_init = true;
 474
 475         return 0;
 476 }
 477
 478 static void rk3368_lcdc_deint(struct lcdc_device *lcdc_dev)
 479 {
 480         u32 mask, val;
 481
 482         if (lcdc_dev->clk_on) {
 483                 rk3368_lcdc_disable_irq(lcdc_dev);
 484                 spin_lock(&lcdc_dev->reg_lock);
 485                 mask = m_WIN0_EN;
 486                 val = v_WIN0_EN(0);
 487                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
 488                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
 489
 490                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
 491                         m_WIN2_MST1_EN |
 492                         m_WIN2_MST2_EN | m_WIN2_MST3_EN;
 493                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
 494                         v_WIN2_MST1_EN(0) |
 495                         v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
 496                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
 497                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
 498                 lcdc_cfg_done(lcdc_dev);
 499                 spin_unlock(&lcdc_dev->reg_lock);
 500                 mdelay(50);
 501         }
 502 }
 503
 504 static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
 505 {
 506         struct lcdc_device *lcdc_dev =
 507             container_of(dev_drv, struct lcdc_device, driver);
 508         struct rk_screen *screen = dev_drv->cur_screen;
 509         u16 x_res = screen->mode.xres;
 510         u16 y_res = screen->mode.yres;
 511         u32 mask, val;
 512         u16 h_total, v_total;
 513         u16 post_hsd_en, post_vsd_en;
 514         u16 post_dsp_hact_st, post_dsp_hact_end;
 515         u16 post_dsp_vact_st, post_dsp_vact_end;
 516         u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
 517         u16 post_h_fac, post_v_fac;
 518
 519         screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200;
 520         screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200;
 521         screen->post_xsize = x_res *
 522             (dev_drv->overscan.left + dev_drv->overscan.right) / 200;
 523         screen->post_ysize = y_res *
 524             (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200;
 525
 526         h_total = screen->mode.hsync_len + screen->mode.left_margin +
 527             x_res + screen->mode.right_margin;
 528         v_total = screen->mode.vsync_len + screen->mode.upper_margin +
 529             y_res + screen->mode.lower_margin;
 530
 531         if (screen->post_dsp_stx + screen->post_xsize > x_res) {
 532                 dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
 533                          screen->post_dsp_stx, screen->post_xsize, x_res);
 534                 screen->post_dsp_stx = x_res - screen->post_xsize;
 535         }
 536         if (screen->x_mirror == 0) {
 537                 post_dsp_hact_st = screen->post_dsp_stx +
 538                     screen->mode.hsync_len + screen->mode.left_margin;
 539                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 540         } else {
 541                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 542                     screen->post_dsp_stx;
 543                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 544         }
 545         if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
 546                 post_hsd_en = 1;
 547                 post_h_fac =
 548                     GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
 549         } else {
 550                 post_hsd_en = 0;
 551                 post_h_fac = 0x1000;
 552         }
 553
 554         if (screen->post_dsp_sty + screen->post_ysize > y_res) {
 555                 dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
 556                          screen->post_dsp_sty, screen->post_ysize, y_res);
 557                 screen->post_dsp_sty = y_res - screen->post_ysize;
 558         }
 559
 560         if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
 561                 post_vsd_en = 1;
 562                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
 563                                                       screen->post_ysize);
 564         } else {
 565                 post_vsd_en = 0;
 566                 post_v_fac = 0x1000;
 567         }
 568
 569         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
 570                 post_dsp_vact_st = screen->post_dsp_sty / 2 +
 571                                         screen->mode.vsync_len +
 572                                         screen->mode.upper_margin;
 573                 post_dsp_vact_end = post_dsp_vact_st +
 574                                         screen->post_ysize / 2;
 575
 576                 post_dsp_vact_st_f1 = screen->mode.vsync_len +
 577                                       screen->mode.upper_margin +
 578                                       y_res/2 +
 579                                       screen->mode.lower_margin +
 580                                       screen->mode.vsync_len +
 581                                       screen->mode.upper_margin +
 582                                       screen->post_dsp_sty / 2 +
 583                                       1;
 584                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
 585                                         screen->post_ysize/2;
 586         } else {
 587                 if (screen->y_mirror == 0) {
 588                         post_dsp_vact_st = screen->post_dsp_sty +
 589                             screen->mode.vsync_len +
 590                             screen->mode.upper_margin;
 591                         post_dsp_vact_end = post_dsp_vact_st +
 592                                 screen->post_ysize;
 593                 } else {
 594                         post_dsp_vact_end = v_total -
 595                                 screen->mode.lower_margin -
 596                             screen->post_dsp_sty;
 597                         post_dsp_vact_st = post_dsp_vact_end -
 598                                 screen->post_ysize;
 599                 }
 600                 post_dsp_vact_st_f1 = 0;
 601                 post_dsp_vact_end_f1 = 0;
 602         }
 603         DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
 604             screen->post_xsize, screen->post_ysize, screen->xpos);
 605         DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 606             screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
 607         mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
 608         val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
 609             v_DSP_HACT_ST_POST(post_dsp_hact_st);
 610         lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
 611
 612         mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
 613         val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
 614             v_DSP_VACT_ST_POST(post_dsp_vact_st);
 615         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
 616
 617         mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
 618         val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
 619             v_POST_VS_FACTOR_YRGB(post_v_fac);
 620         lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
 621
 622         mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
 623         val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
 624             v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
 625         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
 626
 627         mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
 628         val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
 629         lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
 630         return 0;
 631 }
 632
 633 static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 634 {
 635         struct lcdc_device *lcdc_dev =
 636             container_of(dev_drv, struct lcdc_device, driver);
 637         struct rk_lcdc_win *win;
 638         u32 colorkey_r, colorkey_g, colorkey_b;
 639         int i, key_val;
 640
 641         for (i = 0; i < 4; i++) {
 642                 win = dev_drv->win[i];
 643                 key_val = win->color_key_val;
 644                 colorkey_r = (key_val & 0xff) << 2;
 645                 colorkey_g = ((key_val >> 8) & 0xff) << 12;
 646                 colorkey_b = ((key_val >> 16) & 0xff) << 22;
 647                 /*color key dither 565/888->aaa */
 648                 key_val = colorkey_r | colorkey_g | colorkey_b;
 649                 switch (i) {
 650                 case 0:
 651                         lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
 652                         break;
 653                 case 1:
 654                         lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
 655                         break;
 656                 case 2:
 657                         lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
 658                         break;
 659                 case 3:
 660                         lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
 661                         break;
 662                 default:
 663                         pr_info("%s:un support win num:%d\n",
 664                                 __func__, i);
 665                         break;
 666                 }
 667         }
 668         return 0;
 669 }
 670
 671 static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
 672 {
 673         struct lcdc_device *lcdc_dev =
 674             container_of(dev_drv, struct lcdc_device, driver);
 675         struct rk_lcdc_win *win = dev_drv->win[win_id];
 676         struct alpha_config alpha_config;
 677         u32 mask, val;
 678         int ppixel_alpha = 0, global_alpha = 0, i;
 679         u32 src_alpha_ctl, dst_alpha_ctl;
 680
 681         for (i = 0; i < win->area_num; i++) {
 682                 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
 683                                  (win->area[i].format == FBDC_ARGB_888) ||
 684                                  (win->area[i].format == FBDC_ABGR_888) ||
 685                                  (win->area[i].format == ABGR888)) ? 1 : 0;
 686         }
 687         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 688         alpha_config.src_global_alpha_val = win->g_alpha_val;
 689         win->alpha_mode = AB_SRC_OVER;
 690         /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
 691            __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,
 692            global_alpha); */
 693         switch (win->alpha_mode) {
 694         case AB_USER_DEFINE:
 695                 break;
 696         case AB_CLEAR:
 697                 alpha_config.src_factor_mode = AA_ZERO;
 698                 alpha_config.dst_factor_mode = AA_ZERO;
 699                 break;
 700         case AB_SRC:
 701                 alpha_config.src_factor_mode = AA_ONE;
 702                 alpha_config.dst_factor_mode = AA_ZERO;
 703                 break;
 704         case AB_DST:
 705                 alpha_config.src_factor_mode = AA_ZERO;
 706                 alpha_config.dst_factor_mode = AA_ONE;
 707                 break;
 708         case AB_SRC_OVER:
 709                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 710                 if (global_alpha)
 711                         alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 712                 else
 713                         alpha_config.src_factor_mode = AA_ONE;
 714                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 715                 break;
 716         case AB_DST_OVER:
 717                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 718                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 719                 alpha_config.dst_factor_mode = AA_ONE;
 720                 break;
 721         case AB_SRC_IN:
 722                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 723                 alpha_config.src_factor_mode = AA_SRC;
 724                 alpha_config.dst_factor_mode = AA_ZERO;
 725                 break;
 726         case AB_DST_IN:
 727                 alpha_config.src_factor_mode = AA_ZERO;
 728                 alpha_config.dst_factor_mode = AA_SRC;
 729                 break;
 730         case AB_SRC_OUT:
 731                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 732                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 733                 alpha_config.dst_factor_mode = AA_ZERO;
 734                 break;
 735         case AB_DST_OUT:
 736                 alpha_config.src_factor_mode = AA_ZERO;
 737                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 738                 break;
 739         case AB_SRC_ATOP:
 740                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 741                 alpha_config.src_factor_mode = AA_SRC;
 742                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 743                 break;
 744         case AB_DST_ATOP:
 745                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 746                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 747                 alpha_config.dst_factor_mode = AA_SRC;
 748                 break;
 749         case XOR:
 750                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 751                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 752                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 753                 break;
 754         case AB_SRC_OVER_GLOBAL:
 755                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 756                 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
 757                 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 758                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 759                 break;
 760         default:
 761                 pr_err("alpha mode error\n");
 762                 break;
 763         }
 764         if ((ppixel_alpha == 1) && (global_alpha == 1))
 765                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 766         else if (ppixel_alpha == 1)
 767                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 768         else if (global_alpha == 1)
 769                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 770         else
 771                 dev_warn(lcdc_dev->dev, "alpha_en should be 0\n");
 772         alpha_config.src_alpha_mode = AA_STRAIGHT;
 773         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 774
 775         switch (win_id) {
 776         case 0:
 777                 src_alpha_ctl = 0x60;
 778                 dst_alpha_ctl = 0x64;
 779                 break;
 780         case 1:
 781                 src_alpha_ctl = 0xa0;
 782                 dst_alpha_ctl = 0xa4;
 783                 break;
 784         case 2:
 785                 src_alpha_ctl = 0xdc;
 786                 dst_alpha_ctl = 0xec;
 787                 break;
 788         case 3:
 789                 src_alpha_ctl = 0x12c;
 790                 dst_alpha_ctl = 0x13c;
 791                 break;
 792         case 4:
 793                 src_alpha_ctl = 0x160;
 794                 dst_alpha_ctl = 0x164;
 795                 break;
 796         }
 797         mask = m_WIN0_DST_FACTOR_M0;
 798         val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
 799         lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
 800         mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
 801             m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
 802             m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 |
 803             m_WIN0_SRC_GLOBAL_ALPHA;
 804         val = v_WIN0_SRC_ALPHA_EN(1) |
 805             v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
 806             v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
 807             v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
 808             v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
 809             v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
 810             v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 811         lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
 812
 813         return 0;
 814 }
 815
 816 static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num)
 817 {
 818         struct rk_lcdc_win_area area_temp;
 819         int i, j;
 820
 821         for (i = 0; i < area_num; i++) {
 822                 for (j = i + 1; j < area_num; j++) {
 823                         if (win->area[i].dsp_stx >  win->area[j].dsp_stx) {
 824                                 memcpy(&area_temp, &win->area[i],
 825                                        sizeof(struct rk_lcdc_win_area));
 826                                 memcpy(&win->area[i], &win->area[j],
 827                                        sizeof(struct rk_lcdc_win_area));
 828                                 memcpy(&win->area[j], &area_temp,
 829                                        sizeof(struct rk_lcdc_win_area));
 830                         }
 831                 }
 832         }
 833
 834         return 0;
 835 }
 836
 837 static int __maybe_unused
 838         rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num)
 839 {
 840         struct rk_lcdc_win_area area_temp;
 841
 842         switch (area_num) {
 843         case 2:
 844                 area_temp = win->area[0];
 845                 win->area[0] = win->area[1];
 846                 win->area[1] = area_temp;
 847                 break;
 848         case 3:
 849                 area_temp = win->area[0];
 850                 win->area[0] = win->area[2];
 851                 win->area[2] = area_temp;
 852                 break;
 853         case 4:
 854                 area_temp = win->area[0];
 855                 win->area[0] = win->area[3];
 856                 win->area[3] = area_temp;
 857
 858                 area_temp = win->area[1];
 859                 win->area[1] = win->area[2];
 860                 win->area[2] = area_temp;
 861                 break;
 862         default:
 863                 pr_info("un supported area num!\n");
 864                 break;
 865         }
 866         return 0;
 867 }
 868
 869 static int __maybe_unused
 870 rk3368_win_area_check_var(int win_id, int area_num,
 871                           struct rk_lcdc_win_area *area_pre,
 872                           struct rk_lcdc_win_area *area_now)
 873 {
 874         if ((area_pre->xpos > area_now->xpos) ||
 875             ((area_pre->xpos + area_pre->xsize > area_now->xpos) &&
 876              (area_pre->ypos + area_pre->ysize > area_now->ypos))) {
 877                 area_now->state = 0;
 878                 pr_err("win[%d]:\n"
 879                        "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n"
 880                        "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n",
 881                        win_id,
 882                        area_num - 1, area_pre->xpos, area_pre->xsize,
 883                        area_pre->ypos, area_pre->ysize,
 884                        area_num, area_now->xpos, area_now->xsize,
 885                        area_now->ypos, area_now->ysize);
 886                 return -EINVAL;
 887         }
 888         return 0;
 889 }
 890
 891 static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv)
 892 {
 893         struct lcdc_device *lcdc_dev =
 894             container_of(dev_drv, struct lcdc_device, driver);
 895         u32 val, i;
 896
 897         for (i = 0; i < 100; i++) {
 898                 val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0);
 899                 val &= m_DBG_IFBDC_IDLE;
 900                 if (val)
 901                         continue;
 902                 else
 903                         mdelay(10);
 904         };
 905         return val;
 906 }
 907
 908 static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
 909 {
 910         struct lcdc_device *lcdc_dev =
 911             container_of(dev_drv, struct lcdc_device, driver);
 912         struct rk_lcdc_win *win = dev_drv->win[win_id];
 913         u32 mask, val;
 914
 915         mask = m_IFBDC_CTRL_FBDC_EN | m_IFBDC_CTRL_FBDC_COR_EN |
 916             m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE |
 917             m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO;
 918         val = v_IFBDC_CTRL_FBDC_EN(win->area[0].fbdc_en) |
 919             v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) |
 920             v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) |
 921             v_IFBDC_CTRL_FBDC_ROTATION_MODE(win->mirror_en << 1) |
 922             v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) |
 923             v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio);
 924         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
 925
 926         mask = m_IFBDC_TILES_NUM;
 927         val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles);
 928         lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val);
 929
 930         mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT;
 931         val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) |
 932             v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height);
 933         lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val);
 934
 935         mask = m_IFBDC_CMP_INDEX_INIT;
 936         val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init);
 937         lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val);
 938
 939         mask = m_IFBDC_MB_VIR_WIDTH;
 940         val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width);
 941         lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val);
 942
 943         return 0;
 944 }
 945
 946 static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id)
 947 {
 948         struct lcdc_device *lcdc_dev =
 949             container_of(dev_drv, struct lcdc_device, driver);
 950         struct rk_lcdc_win *win = dev_drv->win[win_id];
 951         u8 fbdc_dsp_width_ratio;
 952         u16 fbdc_mb_vir_width, fbdc_mb_vir_height;
 953         u16 fbdc_mb_width, fbdc_mb_height;
 954         u16 fbdc_mb_xst, fbdc_mb_yst, fbdc_num_tiles;
 955         u16 fbdc_cmp_index_init;
 956         u8 mb_w_size, mb_h_size;
 957         struct rk_screen *screen = dev_drv->cur_screen;
 958
 959         if (screen->mode.flag == FB_VMODE_INTERLACED) {
 960                 dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n");
 961                 return 0;
 962         }
 963
 964         switch (win->area[0].fmt_cfg) {
 965         case VOP_FORMAT_ARGB888:
 966                 fbdc_dsp_width_ratio = 0;
 967                 mb_w_size = 16;
 968                 break;
 969         case VOP_FORMAT_RGB888:
 970                 fbdc_dsp_width_ratio = 0;
 971                 mb_w_size = 16;
 972                 break;
 973         case VOP_FORMAT_RGB565:
 974                 fbdc_dsp_width_ratio = 1;
 975                 mb_w_size = 32;
 976                 break;
 977         default:
 978                 dev_err(lcdc_dev->dev,
 979                         "in fbdc mode,unsupport fmt:%d!\n",
 980                         win->area[0].fmt_cfg);
 981                 break;
 982         }
 983         mb_h_size = 4;
 984
 985         /*macro block xvir and yvir */
 986         if ((win->area[0].xvir % mb_w_size == 0) &&
 987             (win->area[0].yvir % mb_h_size == 0)) {
 988                 fbdc_mb_vir_width = win->area[0].xvir / mb_w_size;
 989                 fbdc_mb_vir_height = win->area[0].yvir / mb_h_size;
 990         } else {
 991                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 992                 pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n",
 993                        win->area[0].xvir, win->area[0].yvir,
 994                        mb_w_size, mb_h_size);
 995         }
 996         /*macro block xact and yact */
 997         if ((win->area[0].xact % mb_w_size == 0) &&
 998             (win->area[0].yact % mb_h_size == 0)) {
 999                 fbdc_mb_width = win->area[0].xact / mb_w_size;
1000                 fbdc_mb_height = win->area[0].yact / mb_h_size;
1001         } else {
1002                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
1003                 pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n",
1004                        win->area[0].xact, win->area[0].yact,
1005                        mb_w_size, mb_h_size);
1006         }
1007         /*macro block xoff and yoff */
1008         if ((win->area[0].xoff % mb_w_size == 0) &&
1009             (win->area[0].yoff % mb_h_size == 0)) {
1010                 fbdc_mb_xst = win->area[0].xoff / mb_w_size;
1011                 fbdc_mb_yst = win->area[0].yoff / mb_h_size;
1012         } else {
1013                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
1014                 pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n",
1015                        win->area[0].xoff, win->area[0].yoff,
1016                        mb_w_size, mb_h_size);
1017         }
1018
1019         /*FBDC tiles */
1020         fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height;
1021
1022         /*
1023            switch (fbdc_rotation_mode)  {
1024            case FBDC_ROT_NONE:
1025            fbdc_cmp_index_init =
1026            (fbdc_mb_yst*fbdc_mb_vir_width) +  fbdc_mb_xst;
1027            break;
1028            case FBDC_X_MIRROR:
1029            fbdc_cmp_index_init =
1030            (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+
1031            (fbdc_mb_width-1));
1032            break;
1033            case FBDC_Y_MIRROR:
1034            fbdc_cmp_index_init =
1035            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width)  +
1036            fbdc_mb_xst;
1037            break;
1038            case FBDC_ROT_180:
1039            fbdc_cmp_index_init =
1040            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
1041            (fbdc_mb_xst+(fbdc_mb_width-1));
1042            break;
1043            }
1044          */
1045         if ((win->mirror_en) && ((win_id == 2) || (win_id == 3))) {
1046                 fbdc_cmp_index_init =
1047                     ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) +
1048                     (fbdc_mb_xst + (fbdc_mb_width - 1));
1049         } else {
1050                 fbdc_cmp_index_init =
1051                     (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst;
1052         }
1053         /*fbdc fmt maybe need to change*/
1054         win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio;
1055         win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width;
1056         win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height;
1057         win->area[0].fbdc_mb_width = fbdc_mb_width;
1058         win->area[0].fbdc_mb_height = fbdc_mb_height;
1059         win->area[0].fbdc_mb_xst = fbdc_mb_xst;
1060         win->area[0].fbdc_mb_yst = fbdc_mb_yst;
1061         win->area[0].fbdc_num_tiles = fbdc_num_tiles;
1062         win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init;
1063
1064         return 0;
1065 }
1066
1067 static int rk3368_lcdc_axi_gather_cfg(struct lcdc_device *lcdc_dev,
1068                                             struct rk_lcdc_win *win)
1069 {
1070         u32 mask, val;
1071         u16 yrgb_gather_num = 3;
1072         u16 cbcr_gather_num = 1;
1073
1074         switch (win->area[0].format) {
1075         case ARGB888:
1076         case XBGR888:
1077         case ABGR888:
1078                 yrgb_gather_num = 3;
1079                 break;
1080         case RGB888:
1081         case RGB565:
1082                 yrgb_gather_num = 2;
1083                 break;
1084         case YUV444:
1085         case YUV422:
1086         case YUV420:
1087         case YUV420_NV21:
1088                 yrgb_gather_num = 1;
1089                 cbcr_gather_num = 2;
1090                 break;
1091         default:
1092                 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
1093                         __func__);
1094                 return -EINVAL;
1095         }
1096
1097         if ((win->id == 0) || (win->id == 1)) {
1098                 mask = m_WIN0_YRGB_AXI_GATHER_EN | m_WIN0_CBR_AXI_GATHER_EN |
1099                         m_WIN0_YRGB_AXI_GATHER_NUM | m_WIN0_CBR_AXI_GATHER_NUM;
1100                 val = v_WIN0_YRGB_AXI_GATHER_EN(1) | v_WIN0_CBR_AXI_GATHER_EN(1) |
1101                         v_WIN0_YRGB_AXI_GATHER_NUM(yrgb_gather_num) |
1102                         v_WIN0_CBR_AXI_GATHER_NUM(cbcr_gather_num);
1103                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + (win->id * 0x40), mask, val);
1104         } else if ((win->id == 2) || (win->id == 3)) {
1105                 mask = m_WIN2_AXI_GATHER_EN | m_WIN2_AXI_GATHER_NUM;
1106                 val = v_WIN2_AXI_GATHER_EN(1) |
1107                         v_WIN2_AXI_GATHER_NUM(yrgb_gather_num);
1108                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL1 + ((win->id - 2) * 0x50), mask, val);
1109         } else if (win->id == 4) {
1110                 mask = m_HWC_AXI_GATHER_EN | m_HWC_AXI_GATHER_NUM;
1111                 val = v_HWC_AXI_GATHER_EN(1) |
1112                         v_HWC_AXI_GATHER_NUM(yrgb_gather_num);
1113                 lcdc_msk_reg(lcdc_dev, HWC_CTRL1, mask, val);
1114         }
1115         return 0;
1116 }
1117
1118 static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev,
1119                                  struct rk_lcdc_win *win)
1120 {
1121         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1122         struct rk_screen *screen = dev_drv->cur_screen;
1123
1124         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1125                 switch (win->area[0].fmt_cfg) {
1126                 case VOP_FORMAT_ARGB888:
1127                 case VOP_FORMAT_RGB888:
1128                 case VOP_FORMAT_RGB565:
1129                         if ((screen->mode.xres < 1280) &&
1130                             (screen->mode.yres < 720)) {
1131                                 win->csc_mode = VOP_R2Y_CSC_BT601;
1132                         } else {
1133                                 win->csc_mode = VOP_R2Y_CSC_BT709;
1134                         }
1135                         break;
1136                 default:
1137                         break;
1138                 }
1139         } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
1140                 switch (win->area[0].fmt_cfg) {
1141                 case VOP_FORMAT_YCBCR420:
1142                         if ((win->id == 0) || (win->id == 1))
1143                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
1144                         break;
1145                 default:
1146                         break;
1147                 }
1148         }
1149 }
1150
1151 static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1152 {
1153         struct lcdc_device *lcdc_dev =
1154             container_of(dev_drv, struct lcdc_device, driver);
1155         struct rk_lcdc_win *win = dev_drv->win[win_id];
1156         unsigned int mask, val, off;
1157
1158         off = win_id * 0x40;
1159         /*if(win->win_lb_mode == 5)
1160            win->win_lb_mode = 4;
1161            for rk3288 to fix hw bug? */
1162
1163         if (win->state == 1) {
1164                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1165                 rk3368_lcdc_axi_gather_cfg(lcdc_dev, win);
1166                 if (win->area[0].fbdc_en) {
1167                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1168                 } else {
1169                         mask = m_IFBDC_CTRL_FBDC_EN;
1170                         val = v_IFBDC_CTRL_FBDC_EN(0);
1171                         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1172                 }
1173                 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
1174                     m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR |
1175                     m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE |m_WIN0_UV_SWAP;
1176                 val = v_WIN0_EN(win->state) |
1177                     v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1178                     v_WIN0_FMT_10(win->fmt_10) |
1179                     v_WIN0_LB_MODE(win->win_lb_mode) |
1180                     v_WIN0_RB_SWAP(win->area[0].swap_rb) |
1181                     v_WIN0_X_MIRROR(win->mirror_en) |
1182                     v_WIN0_Y_MIRROR(win->mirror_en) |
1183                     v_WIN0_CSC_MODE(win->csc_mode) |
1184                     v_WIN0_UV_SWAP(win->area[0].swap_uv);
1185                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1186
1187                 mask = m_WIN0_BIC_COE_SEL |
1188                     m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
1189                     m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
1190                     m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
1191                     m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
1192                     m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
1193                     m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
1194                     m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
1195                 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1196                     v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1197                     v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1198                     v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1199                     v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1200                     v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1201                     v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1202                     v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1203                     v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1204                     v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1205                     v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1206                     v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1207                     v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1208                     v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1209                     v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1210                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val);
1211                 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1212                     v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1213                 lcdc_writel(lcdc_dev, WIN0_VIR + off, val);
1214                 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off,
1215                                 win->area[0].y_addr);
1216                    lcdc_writel(lcdc_dev, WIN0_CBR_MST+off,
1217                                 win->area[0].uv_addr); */
1218                 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
1219                     v_WIN0_ACT_HEIGHT(win->area[0].yact);
1220                 lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val);
1221
1222                 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
1223                     v_WIN0_DSP_HEIGHT(win->area[0].ysize);
1224                 lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val);
1225
1226                 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
1227                     v_WIN0_DSP_YST(win->area[0].dsp_sty);
1228                 lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val);
1229
1230                 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1231                     v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1232                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1233
1234                 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1235                     v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1236                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val);
1237                 if (win->alpha_en == 1) {
1238                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1239                 } else {
1240                         mask = m_WIN0_SRC_ALPHA_EN;
1241                         val = v_WIN0_SRC_ALPHA_EN(0);
1242                         lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off,
1243                                      mask, val);
1244                 }
1245
1246                 if (dev_drv->cur_screen->mode.vmode == FB_VMODE_INTERLACED) {
1247                         mask = m_WIN0_YRGB_DEFLICK | m_WIN0_CBR_DEFLICK;
1248                         if (win->area[0].yact == 2 * win->area[0].ysize)
1249                                 val =v_WIN0_YRGB_DEFLICK(0) | v_WIN0_CBR_DEFLICK(0);
1250                         else
1251                                 val =v_WIN0_YRGB_DEFLICK(1) | v_WIN0_CBR_DEFLICK(1);
1252                         lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1253                 }
1254         } else {
1255                 mask = m_WIN0_EN;
1256                 val = v_WIN0_EN(win->state);
1257                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1258         }
1259         return 0;
1260 }
1261
1262 static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1263 {
1264         struct lcdc_device *lcdc_dev =
1265             container_of(dev_drv, struct lcdc_device, driver);
1266         struct rk_lcdc_win *win = dev_drv->win[win_id];
1267         unsigned int mask, val, off;
1268
1269         off = (win_id - 2) * 0x50;
1270         rk3368_lcdc_area_xst(win, win->area_num);
1271
1272         if (win->state == 1) {
1273                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1274                 rk3368_lcdc_axi_gather_cfg(lcdc_dev, win);
1275                 if (win->area[0].fbdc_en) {
1276                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1277                 } else {
1278                         mask = m_IFBDC_CTRL_FBDC_EN;
1279                         val = v_IFBDC_CTRL_FBDC_EN(0);
1280                         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1281                 }
1282
1283                 mask = m_WIN2_EN | m_WIN2_CSC_MODE;
1284                 val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode);
1285                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1286                 /*area 0 */
1287                 if (win->area[0].state == 1) {
1288                         mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 |
1289                             m_WIN2_RB_SWAP0;
1290                         val = v_WIN2_MST0_EN(win->area[0].state) |
1291                             v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1292                             v_WIN2_RB_SWAP0(win->area[0].swap_rb);
1293                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1294
1295                         mask = m_WIN2_VIR_STRIDE0;
1296                         val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1297                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1298
1299                         /*lcdc_writel(lcdc_dev,WIN2_MST0+off,
1300                            win->area[0].y_addr); */
1301                         val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1302                             v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1303                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val);
1304                         val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1305                             v_WIN2_DSP_YST0(win->area[0].dsp_sty);
1306                         lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val);
1307                 } else {
1308                         mask = m_WIN2_MST0_EN;
1309                         val = v_WIN2_MST0_EN(0);
1310                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1311                 }
1312                 /*area 1 */
1313                 if (win->area[1].state == 1) {
1314                         /*rk3368_win_area_check_var(win_id, 1,
1315                                                   &win->area[0], &win->area[1]);
1316                         */
1317
1318                         mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 |
1319                             m_WIN2_RB_SWAP1;
1320                         val = v_WIN2_MST1_EN(win->area[1].state) |
1321                             v_WIN2_DATA_FMT1(win->area[1].fmt_cfg) |
1322                             v_WIN2_RB_SWAP1(win->area[1].swap_rb);
1323                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1324
1325                         mask = m_WIN2_VIR_STRIDE1;
1326                         val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1327                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1328
1329                         /*lcdc_writel(lcdc_dev,WIN2_MST1+off,
1330                            win->area[1].y_addr); */
1331                         val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1332                             v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1333                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val);
1334                         val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1335                             v_WIN2_DSP_YST1(win->area[1].dsp_sty);
1336                         lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val);
1337                 } else {
1338                         mask = m_WIN2_MST1_EN;
1339                         val = v_WIN2_MST1_EN(0);
1340                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1341                 }
1342                 /*area 2 */
1343                 if (win->area[2].state == 1) {
1344                         /*rk3368_win_area_check_var(win_id, 2,
1345                                                   &win->area[1], &win->area[2]);
1346                         */
1347
1348                         mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 |
1349                             m_WIN2_RB_SWAP2;
1350                         val = v_WIN2_MST2_EN(win->area[2].state) |
1351                             v_WIN2_DATA_FMT2(win->area[2].fmt_cfg) |
1352                             v_WIN2_RB_SWAP2(win->area[2].swap_rb);
1353                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1354
1355                         mask = m_WIN2_VIR_STRIDE2;
1356                         val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1357                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1358
1359                         /*lcdc_writel(lcdc_dev,WIN2_MST2+off,
1360                            win->area[2].y_addr); */
1361                         val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1362                             v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1363                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val);
1364                         val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1365                             v_WIN2_DSP_YST2(win->area[2].dsp_sty);
1366                         lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val);
1367                 } else {
1368                         mask = m_WIN2_MST2_EN;
1369                         val = v_WIN2_MST2_EN(0);
1370                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1371                 }
1372                 /*area 3 */
1373                 if (win->area[3].state == 1) {
1374                         /*rk3368_win_area_check_var(win_id, 3,
1375                                                   &win->area[2], &win->area[3]);
1376                         */
1377
1378                         mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 |
1379                             m_WIN2_RB_SWAP3;
1380                         val = v_WIN2_MST3_EN(win->area[3].state) |
1381                             v_WIN2_DATA_FMT3(win->area[3].fmt_cfg) |
1382                             v_WIN2_RB_SWAP3(win->area[3].swap_rb);
1383                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1384
1385                         mask = m_WIN2_VIR_STRIDE3;
1386                         val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1387                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1388
1389                         /*lcdc_writel(lcdc_dev,WIN2_MST3+off,
1390                            win->area[3].y_addr); */
1391                         val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1392                             v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1393                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val);
1394                         val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1395                             v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1396                         lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val);
1397                 } else {
1398                         mask = m_WIN2_MST3_EN;
1399                         val = v_WIN2_MST3_EN(0);
1400                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1401                 }
1402
1403                 if (win->alpha_en == 1) {
1404                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1405                 } else {
1406                         mask = m_WIN2_SRC_ALPHA_EN;
1407                         val = v_WIN2_SRC_ALPHA_EN(0);
1408                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off,
1409                                      mask, val);
1410                 }
1411         } else {
1412                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1413                     m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1414                 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1415                     v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1416                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1417         }
1418         return 0;
1419 }
1420
1421 static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1422 {
1423         struct lcdc_device *lcdc_dev =
1424             container_of(dev_drv, struct lcdc_device, driver);
1425         struct rk_lcdc_win *win = dev_drv->win[win_id];
1426         unsigned int mask, val, hwc_size = 0;
1427
1428         if (win->state == 1) {
1429                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1430                 rk3368_lcdc_axi_gather_cfg(lcdc_dev, win);
1431                 mask = m_HWC_EN | m_HWC_DATA_FMT |
1432                     m_HWC_RB_SWAP | m_WIN0_CSC_MODE;
1433                 val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1434                     v_HWC_RB_SWAP(win->area[0].swap_rb) |
1435                     v_WIN0_CSC_MODE(win->csc_mode);
1436                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1437
1438                 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1439                         hwc_size = 0;
1440                 else if ((win->area[0].xsize == 64) &&
1441                          (win->area[0].ysize == 64))
1442                         hwc_size = 1;
1443                 else if ((win->area[0].xsize == 96) &&
1444                          (win->area[0].ysize == 96))
1445                         hwc_size = 2;
1446                 else if ((win->area[0].xsize == 128) &&
1447                          (win->area[0].ysize == 128))
1448                         hwc_size = 3;
1449                 else
1450                         dev_err(lcdc_dev->dev, "un supported hwc size!\n");
1451
1452                 mask = m_HWC_SIZE;
1453                 val = v_HWC_SIZE(hwc_size);
1454                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1455
1456                 mask = m_HWC_DSP_XST | m_HWC_DSP_YST;
1457                 val = v_HWC_DSP_XST(win->area[0].dsp_stx) |
1458                     v_HWC_DSP_YST(win->area[0].dsp_sty);
1459                 lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val);
1460
1461                 if (win->alpha_en == 1) {
1462                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1463                 } else {
1464                         mask = m_WIN2_SRC_ALPHA_EN;
1465                         val = v_WIN2_SRC_ALPHA_EN(0);
1466                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val);
1467                 }
1468         } else {
1469                 mask = m_HWC_EN;
1470                 val = v_HWC_EN(win->state);
1471                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1472         }
1473         return 0;
1474 }
1475
1476 static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
1477                                          struct rk_lcdc_win *win)
1478 {
1479         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1480         int timeout;
1481         unsigned long flags;
1482
1483         if (likely(lcdc_dev->clk_on)) {
1484                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1485                              v_STANDBY_EN(lcdc_dev->standby));
1486                 if ((win->id == 0) || (win->id == 1))
1487                         rk3368_win_0_1_reg_update(dev_drv, win->id);
1488                 else if ((win->id == 2) || (win->id == 3))
1489                         rk3368_win_2_3_reg_update(dev_drv, win->id);
1490                 else if (win->id == 4)
1491                         rk3368_hwc_reg_update(dev_drv, win->id);
1492                 /*rk3368_lcdc_post_cfg(dev_drv); */
1493                 lcdc_cfg_done(lcdc_dev);
1494         }
1495
1496         /*if (dev_drv->wait_fs) { */
1497         if (0) {
1498                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1499                 init_completion(&dev_drv->frame_done);
1500                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1501                 timeout =
1502                     wait_for_completion_timeout(&dev_drv->frame_done,
1503                                                 msecs_to_jiffies
1504                                                 (dev_drv->cur_screen->ft + 5));
1505                 if (!timeout && (!dev_drv->frame_done.done)) {
1506                         dev_warn(lcdc_dev->dev,
1507                                  "wait for new frame start time out!\n");
1508                         return -ETIMEDOUT;
1509                 }
1510         }
1511         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1512         return 0;
1513 }
1514
1515 static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1516 {
1517         memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x270);
1518         return 0;
1519 }
1520
1521 static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1522 {
1523         u32 mask, val;
1524         struct lcdc_device *lcdc_dev =
1525             container_of(dev_drv, struct lcdc_device, driver);
1526
1527         if (unlikely(!lcdc_dev->clk_on)) {
1528                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
1529                 return 0;
1530         }
1531 #if defined(CONFIG_ROCKCHIP_IOMMU)
1532         if (dev_drv->iommu_enabled) {
1533                 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1534                         if (likely(lcdc_dev->clk_on)) {
1535                                 mask = m_MMU_EN;
1536                                 val = v_MMU_EN(1);
1537                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1538                                 mask = m_AXI_MAX_OUTSTANDING_EN |
1539                                         m_AXI_OUTSTANDING_MAX_NUM;
1540                                 val = v_AXI_OUTSTANDING_MAX_NUM(31) |
1541                                         v_AXI_MAX_OUTSTANDING_EN(1);
1542                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1543                         }
1544                         lcdc_dev->iommu_status = 1;
1545                         rockchip_iovmm_activate(dev_drv->dev);
1546                 }
1547         }
1548 #endif
1549         return 0;
1550 }
1551
1552 static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate)
1553 {
1554         int ret = 0, fps = 0;
1555         struct lcdc_device *lcdc_dev =
1556             container_of(dev_drv, struct lcdc_device, driver);
1557         struct rk_screen *screen = dev_drv->cur_screen;
1558 #ifdef CONFIG_RK_FPGA
1559         return 0;
1560 #endif
1561         if (reset_rate)
1562                 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1563         if (ret)
1564                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1565         lcdc_dev->pixclock =
1566             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1567         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1568
1569         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1570         screen->ft = 1000 / fps;
1571         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1572                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1573         return 0;
1574 }
1575
1576 static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv)
1577 {
1578         struct lcdc_device *lcdc_dev =
1579             container_of(dev_drv, struct lcdc_device, driver);
1580         struct rk_screen *screen = dev_drv->cur_screen;
1581         u16 hsync_len = screen->mode.hsync_len;
1582         u16 left_margin = screen->mode.left_margin;
1583         u16 right_margin = screen->mode.right_margin;
1584         u16 vsync_len = screen->mode.vsync_len;
1585         u16 upper_margin = screen->mode.upper_margin;
1586         u16 lower_margin = screen->mode.lower_margin;
1587         u16 x_res = screen->mode.xres;
1588         u16 y_res = screen->mode.yres;
1589         u32 mask, val;
1590         u16 h_total, v_total;
1591         u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1592
1593         h_total = hsync_len + left_margin + x_res + right_margin;
1594         v_total = vsync_len + upper_margin + y_res + lower_margin;
1595
1596         mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1597         val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1598         lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1599
1600         mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1601         val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1602             v_DSP_HACT_ST(hsync_len + left_margin);
1603         lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1604
1605         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1606                 /* First Field Timing */
1607                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1608                 val = v_DSP_VS_PW(vsync_len) |
1609                     v_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1610                                       lower_margin) + y_res + 1);
1611                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1612
1613                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1614                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1615                     v_DSP_VACT_ST(vsync_len + upper_margin);
1616                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1617
1618                 /* Second Field Timing */
1619                 mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1;
1620                 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1621                 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1622                     lower_margin;
1623                 val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1);
1624                 lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val);
1625
1626                 mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1;
1627                 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1628                     lower_margin + 1;
1629                 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1630                     lower_margin + 1;
1631                 val =
1632                     v_DSP_VACT_END_F1(vact_end_f1) |
1633                     v_DSP_VAC_ST_F1(vact_st_f1);
1634                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val);
1635
1636                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1637                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1638                              v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0));
1639                 mask =
1640                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1641                     m_WIN0_CBR_DEFLICK;
1642                 val =
1643                     v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(0) |
1644                     v_WIN0_CBR_DEFLICK(0);
1645                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1646
1647                 mask =
1648                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1649                     m_WIN1_CBR_DEFLICK;
1650                 val =
1651                     v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(0) |
1652                     v_WIN1_CBR_DEFLICK(0);
1653                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1654
1655                 mask = m_WIN2_INTERLACE_READ;
1656                 val = v_WIN2_INTERLACE_READ(1);
1657                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1658
1659                 mask = m_WIN3_INTERLACE_READ;
1660                 val = v_WIN3_INTERLACE_READ(1);
1661                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1662
1663                 mask = m_HWC_INTERLACE_READ;
1664                 val = v_HWC_INTERLACE_READ(1);
1665                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1666
1667                 mask = m_DSP_LINE_FLAG0_NUM | m_DSP_LINE_FLAG1_NUM;
1668                 val =
1669                     v_DSP_LINE_FLAG0_NUM(vact_end_f1) |
1670                     v_DSP_LINE_FLAG1_NUM(vact_end_f1);
1671                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1672         } else {
1673                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1674                 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1675                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1676
1677                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1678                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1679                     v_DSP_VACT_ST(vsync_len + upper_margin);
1680                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1681
1682                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1683                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1684                              v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0));
1685
1686                 mask =
1687                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1688                     m_WIN0_CBR_DEFLICK;
1689                 val =
1690                     v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) |
1691                     v_WIN0_CBR_DEFLICK(0);
1692                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1693
1694                 mask =
1695                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1696                     m_WIN1_CBR_DEFLICK;
1697                 val =
1698                     v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) |
1699                     v_WIN1_CBR_DEFLICK(0);
1700                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1701
1702                 mask = m_WIN2_INTERLACE_READ;
1703                 val = v_WIN2_INTERLACE_READ(0);
1704                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1705
1706                 mask = m_WIN3_INTERLACE_READ;
1707                 val = v_WIN3_INTERLACE_READ(0);
1708                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1709
1710                 mask = m_HWC_INTERLACE_READ;
1711                 val = v_HWC_INTERLACE_READ(0);
1712                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1713
1714                 mask = m_DSP_LINE_FLAG0_NUM | m_DSP_LINE_FLAG1_NUM;
1715                 val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res) |
1716                         v_DSP_LINE_FLAG1_NUM(vsync_len + upper_margin + y_res);
1717                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1718         }
1719         rk3368_lcdc_post_cfg(dev_drv);
1720         return 0;
1721 }
1722
1723 static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1724 {
1725         struct lcdc_device *lcdc_dev =
1726             container_of(dev_drv, struct lcdc_device, driver);
1727         u32 bcsh_ctrl;
1728
1729         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_OVERLAY_MODE,
1730                      v_OVERLAY_MODE(dev_drv->overlay_mode));
1731         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1732                 if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1733                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1734                                      m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1735                                      v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1736                 else            /* YUV2RGB */
1737                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1738                                      m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1739                                      m_BCSH_R2Y_EN,
1740                                      v_BCSH_Y2R_EN(1) |
1741                                      v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1742                                      v_BCSH_R2Y_EN(0));
1743         } else {                /* overlay_mode=VOP_RGB_DOMAIN */
1744                 /* bypass  --need check,if bcsh close? */
1745                 if (dev_drv->output_color == COLOR_RGB) {
1746                         bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1747                         if (((bcsh_ctrl & m_BCSH_EN) == 1) ||
1748                             (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1749                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1750                                              m_BCSH_R2Y_EN |
1751                                              m_BCSH_Y2R_EN,
1752                                              v_BCSH_R2Y_EN(1) |
1753                                              v_BCSH_Y2R_EN(1));
1754                         else
1755                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1756                                              m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1757                                              v_BCSH_R2Y_EN(0) |
1758                                              v_BCSH_Y2R_EN(0));
1759                 } else          /* RGB2YUV */
1760                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1761                                      m_BCSH_R2Y_EN |
1762                                      m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1763                                      v_BCSH_R2Y_EN(1) |
1764                                      v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1765                                      v_BCSH_Y2R_EN(0));
1766         }
1767 }
1768
1769 static int rk3368_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1770                                   u16 *yact, int *format, u32 *dsp_addr)
1771 {
1772         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1773                                                     struct lcdc_device, driver);
1774         u32 val;
1775
1776         spin_lock(&lcdc_dev->reg_lock);
1777
1778         val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1779         *xact = (val & m_WIN0_ACT_WIDTH) + 1;
1780         *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1;
1781
1782         val = lcdc_readl(lcdc_dev, WIN0_CTRL0);
1783         *format = (val & m_WIN0_DATA_FMT) >> 1;
1784         *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1785
1786         spin_unlock(&lcdc_dev->reg_lock);
1787
1788         return 0;
1789 }
1790
1791 static int rk3368_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1792                               int format, u16 xact, u16 yact, u16 xvir)
1793 {
1794         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1795                                                     struct lcdc_device, driver);
1796         u32 val, mask;
1797         int swap = (format == RGB888) ? 1 : 0;
1798
1799         mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP;
1800         val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap);
1801         lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1802
1803         lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE,
1804                         v_WIN0_VIR_STRIDE(xvir));
1805         lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) |
1806                     v_WIN0_ACT_HEIGHT(yact));
1807
1808         lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1809
1810         lcdc_cfg_done(lcdc_dev);
1811
1812         return 0;
1813 }
1814
1815 static int lcdc_reset(struct rk_lcdc_driver *dev_drv, bool initscreen)
1816 {
1817         struct lcdc_device *lcdc_dev =
1818             container_of(dev_drv, struct lcdc_device, driver);
1819         u32 mask, val;
1820         u32 __maybe_unused v;
1821         /*printk("0407:standby=%d,initscreen=%d,dev_drv->first_frame=%d\n",
1822                 lcdc_dev->standby,initscreen,dev_drv->first_frame);*/
1823         if (!lcdc_dev->standby && initscreen && (dev_drv->first_frame != 1)) {
1824                 mdelay(150);
1825                 mask = m_WIN0_EN;
1826                 val = v_WIN0_EN(0);
1827                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1828                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1829
1830                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1831                         m_WIN2_MST1_EN |
1832                         m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1833                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
1834                         v_WIN2_MST1_EN(0) |
1835                         v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1836                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1837                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1838                 mask = m_HDMI_OUT_EN;
1839                 val = v_HDMI_OUT_EN(0);
1840                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1841                 lcdc_cfg_done(lcdc_dev);
1842                 mdelay(50);
1843                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
1844                 writel_relaxed(0, lcdc_dev->regs + REG_CFG_DONE);
1845                 mdelay(50);
1846 #if 0
1847                 if (dev_drv->iommu_enabled) {
1848                         if (dev_drv->mmu_dev)
1849                                 rockchip_iovmm_deactivate(dev_drv->dev);
1850                 }
1851                 lcdc_cru_writel(lcdc_dev->cru_base, 0x0318,
1852                                 (1 << 4)  | (1 << 5)  | (1 << 6) |
1853                                 (1 << 20) | (1 << 21) | (1 << 22));
1854                 udelay(100);
1855                 v = lcdc_cru_readl(lcdc_dev->cru_base, 0x0318);
1856                 pr_info("cru read = 0x%x\n", v);
1857                 lcdc_cru_writel(lcdc_dev->cru_base, 0x0318,
1858                                 (0 << 4)  | (0 << 5)  | (0 << 6) |
1859                                 (1 << 20) | (1 << 21) | (1 << 22));
1860                 mdelay(100);
1861                 if (dev_drv->iommu_enabled) {
1862                         if (dev_drv->mmu_dev)
1863                                 rockchip_iovmm_activate(dev_drv->dev);
1864                 }
1865                 mdelay(50);
1866                 rk3368_lcdc_reg_restore(lcdc_dev);
1867                 mdelay(50);
1868 #endif
1869         }
1870         return 0;
1871 }
1872
1873 static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1874 {
1875         u16 face = 0;
1876         u16 dclk_ddr = 0;
1877         u32 v = 0;
1878         struct lcdc_device *lcdc_dev =
1879             container_of(dev_drv, struct lcdc_device, driver);
1880         struct rk_screen *screen = dev_drv->cur_screen;
1881         u32 mask, val;
1882
1883         if (unlikely(!lcdc_dev->clk_on)) {
1884                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
1885                 return 0;
1886         }
1887
1888         if (!lcdc_dev->standby && initscreen && (dev_drv->first_frame != 1))
1889                 flush_kthread_worker(&dev_drv->update_regs_worker);
1890
1891         spin_lock(&lcdc_dev->reg_lock);
1892         if (likely(lcdc_dev->clk_on)) {
1893                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1894 #if 0
1895                 if (!lcdc_dev->standby && !initscreen) {
1896                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1897                                      v_STANDBY_EN(1));
1898                         lcdc_cfg_done(lcdc_dev);
1899                         mdelay(50);
1900                 }
1901 #else
1902         lcdc_reset(dev_drv, initscreen);
1903 #endif
1904                 switch (screen->face) {
1905                 case OUT_P565:
1906                         face = OUT_P565;
1907                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1908                             m_DITHER_DOWN_SEL;
1909                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1910                             v_DITHER_DOWN_SEL(1);
1911                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1912                         break;
1913                 case OUT_P666:
1914                         face = OUT_P666;
1915                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1916                             m_DITHER_DOWN_SEL;
1917                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1918                             v_DITHER_DOWN_SEL(1);
1919                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1920                         break;
1921                 case OUT_D888_P565:
1922                         face = OUT_P888;
1923                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1924                             m_DITHER_DOWN_SEL;
1925                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1926                             v_DITHER_DOWN_SEL(1);
1927                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1928                         break;
1929                 case OUT_D888_P666:
1930                         face = OUT_P888;
1931                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1932                             m_DITHER_DOWN_SEL;
1933                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1934                             v_DITHER_DOWN_SEL(1);
1935                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1936                         break;
1937                 case OUT_P888:
1938                         face = OUT_P888;
1939                         mask = m_DITHER_DOWN_EN;
1940                         val = v_DITHER_DOWN_EN(0);
1941                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1942                         break;
1943                 case OUT_YUV_420:
1944                         /*yuv420 output prefer yuv domain overlay */
1945                         face = OUT_YUV_420;
1946                         dclk_ddr = 1;
1947                         mask = m_DITHER_DOWN_EN;
1948                         val = v_DITHER_DOWN_EN(0);
1949                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1950                         break;
1951                 case OUT_S888:
1952                         face = OUT_S888;
1953                         mask = m_DITHER_DOWN_EN;
1954                         val = v_DITHER_DOWN_EN(0);
1955                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1956                         break;
1957                 case OUT_S888DUMY:
1958                         face = OUT_S888DUMY;
1959                         mask = m_DITHER_DOWN_EN;
1960                         val = v_DITHER_DOWN_EN(0);
1961                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1962                         break;
1963                 case OUT_CCIR656:
1964                         if (screen->color_mode == COLOR_RGB)
1965                                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1966                         else
1967                                 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1968                         face = OUT_CCIR656_MODE_0;
1969                         mask = m_DITHER_DOWN_EN;
1970                         val = v_DITHER_DOWN_EN(0);
1971                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1972                         break;
1973                 default:
1974                         dev_err(lcdc_dev->dev, "un supported interface!\n");
1975                         break;
1976                 }
1977                 switch (screen->type) {
1978                 case SCREEN_RGB:
1979                         mask = m_RGB_OUT_EN;
1980                         val = v_RGB_OUT_EN(1);
1981                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1982                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1983                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1984                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1985                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1986                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1987                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1988                         v = 1 << 15 | (1 << (15 + 16));
1989
1990                         break;
1991                 case SCREEN_LVDS:
1992                         mask = m_RGB_OUT_EN;
1993                         val = v_RGB_OUT_EN(1);
1994                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1995                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1996                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1997                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1998                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1999                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
2000                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
2001                         v = 0 << 15 | (1 << (15 + 16));
2002                         break;
2003                 case SCREEN_HDMI:
2004                         /*face = OUT_RGB_AAA;*/
2005                         if (screen->color_mode == COLOR_RGB)
2006                                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
2007                         else
2008                                 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
2009                         mask = m_HDMI_OUT_EN  | m_RGB_OUT_EN;
2010                         val = v_HDMI_OUT_EN(1) | v_RGB_OUT_EN(0);
2011                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2012                         mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
2013                             m_HDMI_DEN_POL | m_HDMI_DCLK_POL;
2014                         val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
2015                             v_HDMI_VSYNC_POL(screen->pin_vsync) |
2016                             v_HDMI_DEN_POL(screen->pin_den) |
2017                             v_HDMI_DCLK_POL(screen->pin_dclk);
2018                         break;
2019                 case SCREEN_MIPI:
2020                         mask = m_MIPI_OUT_EN  | m_RGB_OUT_EN;
2021                         val = v_MIPI_OUT_EN(1) | v_RGB_OUT_EN(0);
2022                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2023                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
2024                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
2025                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
2026                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
2027                             v_MIPI_DEN_POL(screen->pin_den) |
2028                             v_MIPI_DCLK_POL(screen->pin_dclk);
2029                         break;
2030                 case SCREEN_DUAL_MIPI:
2031                         mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN  |
2032                                 m_RGB_OUT_EN;
2033                         val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1) |
2034                                 v_RGB_OUT_EN(0);
2035                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2036                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
2037                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
2038                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
2039                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
2040                             v_MIPI_DEN_POL(screen->pin_den) |
2041                             v_MIPI_DCLK_POL(screen->pin_dclk);
2042                         break;
2043                 case SCREEN_EDP:
2044                         face = OUT_P888;        /*RGB 888 output */
2045
2046                         mask = m_EDP_OUT_EN | m_RGB_OUT_EN;
2047                         val = v_EDP_OUT_EN(1) | v_RGB_OUT_EN(0);
2048                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2049                         /*because edp have to sent aaa fmt */
2050                         mask = m_DITHER_DOWN_EN;
2051                         val = v_DITHER_DOWN_EN(0);
2052
2053                         mask |= m_EDP_HSYNC_POL | m_EDP_VSYNC_POL |
2054                             m_EDP_DEN_POL | m_EDP_DCLK_POL;
2055                         val |= v_EDP_HSYNC_POL(screen->pin_hsync) |
2056                             v_EDP_VSYNC_POL(screen->pin_vsync) |
2057                             v_EDP_DEN_POL(screen->pin_den) |
2058                             v_EDP_DCLK_POL(screen->pin_dclk);
2059                         break;
2060                 }
2061                 /*hsync vsync den dclk polo,dither */
2062                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2063 #ifndef CONFIG_RK_FPGA
2064                 /*writel_relaxed(v, RK_GRF_VIRT + rk3368_GRF_SOC_CON7);
2065                 move to  lvds driver*/
2066                 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
2067 #endif
2068                 mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP |
2069                     m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
2070                     m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
2071                     m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
2072                 val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) |
2073                     v_DSP_BG_SWAP(screen->swap_gb) |
2074                     v_DSP_RB_SWAP(screen->swap_rb) |
2075                     v_DSP_RG_SWAP(screen->swap_rg) |
2076                     v_DSP_DELTA_SWAP(screen->swap_delta) |
2077                     v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
2078                     v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
2079                     v_DSP_X_MIR_EN(screen->x_mirror) |
2080                     v_DSP_Y_MIR_EN(screen->y_mirror);
2081                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
2082                 /*BG color */
2083                 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
2084                 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN)
2085                         val = v_DSP_BG_BLUE(0x80) | v_DSP_BG_GREEN(0x10) |
2086                                 v_DSP_BG_RED(0x80);
2087                 else
2088                         val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) |
2089                                 v_DSP_BG_RED(0);
2090                 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
2091                 dev_drv->output_color = screen->color_mode;
2092                 if (screen->dsp_lut == NULL)
2093                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2094                                      v_DSP_LUT_EN(0));
2095                 else
2096                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2097                                      v_DSP_LUT_EN(1));
2098                 rk3368_lcdc_bcsh_path_sel(dev_drv);
2099                 rk3368_config_timing(dev_drv);
2100         }
2101         spin_unlock(&lcdc_dev->reg_lock);
2102         rk3368_lcdc_set_dclk(dev_drv, 1);
2103         if (screen->type != SCREEN_HDMI &&
2104             screen->type != SCREEN_TVOUT &&
2105             dev_drv->trsm_ops &&
2106             dev_drv->trsm_ops->enable)
2107                 dev_drv->trsm_ops->enable();
2108                 if (screen->init)
2109                         screen->init();
2110         /*if (!lcdc_dev->standby)
2111                 lcdc_msk_reg(lcdc_dev, SYS_CTRL,
2112                         m_STANDBY_EN, v_STANDBY_EN(0));*/
2113         return 0;
2114 }
2115
2116
2117 /*enable layer,open:1,enable;0 disable*/
2118 static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev,
2119                                      unsigned int win_id, bool open)
2120 {
2121         spin_lock(&lcdc_dev->reg_lock);
2122         if (likely(lcdc_dev->clk_on) &&
2123             lcdc_dev->driver.win[win_id]->state != open) {
2124                 if (open) {
2125                         if (!lcdc_dev->atv_layer_cnt) {
2126                                 dev_info(lcdc_dev->dev,
2127                                          "wakeup from standby!\n");
2128                                 lcdc_dev->standby = 0;
2129                         }
2130                         lcdc_dev->atv_layer_cnt |= (1 << win_id);
2131                 } else {
2132                         if (lcdc_dev->atv_layer_cnt & (1 << win_id))
2133                                 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
2134                 }
2135                 lcdc_dev->driver.win[win_id]->state = open;
2136                 if (!open) {
2137                         /*rk3368_lcdc_reg_update(dev_drv);*/
2138                         rk3368_lcdc_layer_update_regs
2139                         (lcdc_dev, lcdc_dev->driver.win[win_id]);
2140                         lcdc_cfg_done(lcdc_dev);
2141                 }
2142                 /*if no layer used,disable lcdc */
2143                 if (!lcdc_dev->atv_layer_cnt) {
2144                         dev_info(lcdc_dev->dev,
2145                                  "no layer is used,go to standby!\n");
2146                         lcdc_dev->standby = 1;
2147                 }
2148         }
2149         spin_unlock(&lcdc_dev->reg_lock);
2150 }
2151
2152 static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
2153 {
2154         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2155                                                     struct lcdc_device, driver);
2156         u32 mask, val;
2157         /*struct rk_screen *screen = dev_drv->cur_screen; */
2158
2159         mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
2160             m_LINE_FLAG1_INTR_CLR;
2161         val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
2162             v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1);
2163         lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
2164
2165         mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN |
2166                 m_BUS_ERROR_INTR_EN | m_LINE_FLAG1_INTR_EN;
2167         val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) |
2168             v_BUS_ERROR_INTR_EN(1) | v_LINE_FLAG1_INTR_EN(0);
2169         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
2170
2171 #ifdef LCDC_IRQ_EMPTY_DEBUG
2172         mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
2173             m_WIN2_EMPTY_INTR_EN |
2174             m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN |
2175             m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN;
2176         val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) |
2177             v_WIN2_EMPTY_INTR_EN(1) |
2178             v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) |
2179             v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1);
2180         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
2181 #endif
2182         return 0;
2183 }
2184
2185 static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
2186                             bool open)
2187 {
2188         struct lcdc_device *lcdc_dev =
2189             container_of(dev_drv, struct lcdc_device, driver);
2190 #if 0/*ndef CONFIG_RK_FPGA*/
2191         int sys_status =
2192             (dev_drv->id == 0) ? SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
2193 #endif
2194         /*enable clk,when first layer open */
2195         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
2196                 /*rockchip_set_system_status(sys_status);*/
2197                 rk3368_lcdc_pre_init(dev_drv);
2198                 rk3368_lcdc_clk_enable(lcdc_dev);
2199                 rk3368_lcdc_enable_irq(dev_drv);
2200 #if defined(CONFIG_ROCKCHIP_IOMMU)
2201                 if (dev_drv->iommu_enabled) {
2202                         if (!dev_drv->mmu_dev) {
2203                                 dev_drv->mmu_dev =
2204                                     rk_fb_get_sysmmu_device_by_compatible
2205                                     (dev_drv->mmu_dts_name);
2206                                 if (dev_drv->mmu_dev) {
2207                                         rk_fb_platform_set_sysmmu
2208                                             (dev_drv->mmu_dev, dev_drv->dev);
2209                                 } else {
2210                                         dev_err(dev_drv->dev,
2211                                                 "fail get rk iommu device\n");
2212                                         return -1;
2213                                 }
2214                         }
2215                         /*if (dev_drv->mmu_dev)
2216                            rockchip_iovmm_activate(dev_drv->dev); */
2217                 }
2218 #endif
2219                 rk3368_lcdc_reg_restore(lcdc_dev);
2220                 /*if (dev_drv->iommu_enabled)
2221                    rk3368_lcdc_mmu_en(dev_drv); */
2222                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
2223                         rk3368_lcdc_set_dclk(dev_drv, 0);
2224                         /*rk3368_lcdc_enable_irq(dev_drv);*/
2225                 } else {
2226                         rk3368_load_screen(dev_drv, 1);
2227                 }
2228                 if (dev_drv->bcsh.enable)
2229                         rk3368_lcdc_set_bcsh(dev_drv, 1);
2230                 spin_lock(&lcdc_dev->reg_lock);
2231                 if (dev_drv->cur_screen->dsp_lut)
2232                         rk3368_lcdc_set_lut(dev_drv,
2233                                             dev_drv->cur_screen->dsp_lut);
2234                 if (dev_drv->cur_screen->cabc_lut)
2235                         rk3368_set_cabc_lut(dev_drv,
2236                                             dev_drv->cur_screen->cabc_lut);
2237                 spin_unlock(&lcdc_dev->reg_lock);
2238         }
2239
2240         if (win_id < ARRAY_SIZE(lcdc_win))
2241                 rk3368_lcdc_layer_enable(lcdc_dev, win_id, open);
2242         else
2243                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
2244
2245
2246         /* when all layer closed,disable clk */
2247         /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
2248            rk3368_lcdc_disable_irq(lcdc_dev);
2249            rk3368_lcdc_reg_update(dev_drv);
2250            #if defined(CONFIG_ROCKCHIP_IOMMU)
2251            if (dev_drv->iommu_enabled) {
2252            if (dev_drv->mmu_dev)
2253            rockchip_iovmm_deactivate(dev_drv->dev);
2254            }
2255            #endif
2256            rk3368_lcdc_clk_disable(lcdc_dev);
2257            #ifndef CONFIG_RK_FPGA
2258            rockchip_clear_system_status(sys_status);
2259            #endif
2260            } */
2261         dev_drv->first_frame = 0;
2262         return 0;
2263 }
2264
2265 static int win_0_1_display(struct lcdc_device *lcdc_dev,
2266                            struct rk_lcdc_win *win)
2267 {
2268         u32 y_addr;
2269         u32 uv_addr;
2270         unsigned int off;
2271
2272         off = win->id * 0x40;
2273         /*win->smem_start + win->y_offset; */
2274         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2275         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
2276         DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
2277             lcdc_dev->id, win->id, y_addr, uv_addr);
2278         DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
2279             win->area[0].y_offset, win->area[0].c_offset);
2280         spin_lock(&lcdc_dev->reg_lock);
2281         if (likely(lcdc_dev->clk_on)) {
2282                 win->area[0].y_addr = y_addr;
2283                 win->area[0].uv_addr = uv_addr;
2284                 lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
2285                 lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
2286                 if (win->area[0].fbdc_en == 1)
2287                         lcdc_writel(lcdc_dev, IFBDC_BASE_ADDR,
2288                                         win->area[0].y_addr);
2289         }
2290         spin_unlock(&lcdc_dev->reg_lock);
2291
2292         return 0;
2293 }
2294
2295 static int win_2_3_display(struct lcdc_device *lcdc_dev,
2296                            struct rk_lcdc_win *win)
2297 {
2298         u32 i, y_addr;
2299         unsigned int off;
2300
2301         off = (win->id - 2) * 0x50;
2302         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2303         DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id);
2304
2305         spin_lock(&lcdc_dev->reg_lock);
2306         if (likely(lcdc_dev->clk_on)) {
2307                 for (i = 0; i < win->area_num; i++) {
2308                         DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2309                             i, win->area[i].y_addr, win->area[i].y_offset);
2310                         win->area[i].y_addr =
2311                             win->area[i].smem_start + win->area[i].y_offset;
2312                         }
2313                 lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr);
2314                 lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr);
2315                 lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr);
2316                 lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr);
2317                 if (win->area[0].fbdc_en == 1)
2318                         lcdc_writel(lcdc_dev, IFBDC_BASE_ADDR,
2319                                         win->area[0].y_addr);
2320         }
2321         spin_unlock(&lcdc_dev->reg_lock);
2322         return 0;
2323 }
2324
2325 static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win)
2326 {
2327         u32 y_addr;
2328
2329         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2330         DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2331             lcdc_dev->id, __func__, y_addr);
2332         spin_lock(&lcdc_dev->reg_lock);
2333         if (likely(lcdc_dev->clk_on)) {
2334                 win->area[0].y_addr = y_addr;
2335                 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
2336         }
2337         spin_unlock(&lcdc_dev->reg_lock);
2338
2339         return 0;
2340 }
2341
2342 static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2343 {
2344         struct lcdc_device *lcdc_dev =
2345             container_of(dev_drv, struct lcdc_device, driver);
2346         struct rk_lcdc_win *win = NULL;
2347         struct rk_screen *screen = dev_drv->cur_screen;
2348
2349 #if defined(WAIT_FOR_SYNC)
2350         int timeout;
2351         unsigned long flags;
2352 #endif
2353         win = dev_drv->win[win_id];
2354         if (!screen) {
2355                 dev_err(dev_drv->dev, "screen is null!\n");
2356                 return -ENOENT;
2357         }
2358         if (unlikely(!lcdc_dev->clk_on)) {
2359                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
2360                 return 0;
2361         }
2362         if (win_id == 0) {
2363                 win_0_1_display(lcdc_dev, win);
2364         } else if (win_id == 1) {
2365                 win_0_1_display(lcdc_dev, win);
2366         } else if (win_id == 2) {
2367                 win_2_3_display(lcdc_dev, win);
2368         } else if (win_id == 3) {
2369                 win_2_3_display(lcdc_dev, win);
2370         } else if (win_id == 4) {
2371                 hwc_display(lcdc_dev, win);
2372         } else {
2373                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2374                 return -EINVAL;
2375         }
2376
2377 #if defined(WAIT_FOR_SYNC)
2378         spin_lock_irqsave(&dev_drv->cpl_lock, flags);
2379         init_completion(&dev_drv->frame_done);
2380         spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
2381         timeout =
2382             wait_for_completion_timeout(&dev_drv->frame_done,
2383                                         msecs_to_jiffies(dev_drv->
2384                                                          cur_screen->ft + 5));
2385         if (!timeout && (!dev_drv->frame_done.done)) {
2386                 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
2387                 return -ETIMEDOUT;
2388         }
2389 #endif
2390         return 0;
2391 }
2392
2393 static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win, struct rk_screen *screen)
2394 {
2395         u16 srcW;
2396         u16 srcH;
2397         u16 dstW;
2398         u16 dstH;
2399         u16 yrgb_srcW;
2400         u16 yrgb_srcH;
2401         u16 yrgb_dstW;
2402         u16 yrgb_dstH;
2403         u32 yrgb_vscalednmult;
2404         u32 yrgb_xscl_factor;
2405         u32 yrgb_yscl_factor;
2406         u8 yrgb_vsd_bil_gt2 = 0;
2407         u8 yrgb_vsd_bil_gt4 = 0;
2408
2409         u16 cbcr_srcW;
2410         u16 cbcr_srcH;
2411         u16 cbcr_dstW;
2412         u16 cbcr_dstH;
2413         u32 cbcr_vscalednmult;
2414         u32 cbcr_xscl_factor;
2415         u32 cbcr_yscl_factor;
2416         u8 cbcr_vsd_bil_gt2 = 0;
2417         u8 cbcr_vsd_bil_gt4 = 0;
2418         u8 yuv_fmt = 0;
2419
2420         srcW = win->area[0].xact;
2421         srcH = win->area[0].yact;
2422         dstW = win->area[0].xsize;
2423         dstH = win->area[0].ysize;
2424
2425         /*yrgb scl mode */
2426         yrgb_srcW = srcW;
2427         yrgb_srcH = srcH;
2428         yrgb_dstW = dstW;
2429         yrgb_dstH = dstH;
2430         if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2431                 pr_err("ERROR: yrgb scale exceed 8,");
2432                 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2433                        yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2434         }
2435         if (yrgb_srcW < yrgb_dstW)
2436                 win->yrgb_hor_scl_mode = SCALE_UP;
2437         else if (yrgb_srcW > yrgb_dstW)
2438                 win->yrgb_hor_scl_mode = SCALE_DOWN;
2439         else
2440                 win->yrgb_hor_scl_mode = SCALE_NONE;
2441
2442         if (yrgb_srcH < yrgb_dstH)
2443                 win->yrgb_ver_scl_mode = SCALE_UP;
2444         else if (yrgb_srcH > yrgb_dstH)
2445                 win->yrgb_ver_scl_mode = SCALE_DOWN;
2446         else
2447                 win->yrgb_ver_scl_mode = SCALE_NONE;
2448
2449         /*cbcr scl mode */
2450         switch (win->area[0].format) {
2451         case YUV422:
2452         case YUV422_A:
2453                 cbcr_srcW = srcW / 2;
2454                 cbcr_dstW = dstW;
2455                 cbcr_srcH = srcH;
2456                 cbcr_dstH = dstH;
2457                 yuv_fmt = 1;
2458                 break;
2459         case YUV420:
2460         case YUV420_A:
2461         case YUV420_NV21:
2462                 cbcr_srcW = srcW / 2;
2463                 cbcr_dstW = dstW;
2464                 cbcr_srcH = srcH / 2;
2465                 cbcr_dstH = dstH;
2466                 yuv_fmt = 1;
2467                 break;
2468         case YUV444:
2469         case YUV444_A:
2470                 cbcr_srcW = srcW;
2471                 cbcr_dstW = dstW;
2472                 cbcr_srcH = srcH;
2473                 cbcr_dstH = dstH;
2474                 yuv_fmt = 1;
2475                 break;
2476         default:
2477                 cbcr_srcW = 0;
2478                 cbcr_dstW = 0;
2479                 cbcr_srcH = 0;
2480                 cbcr_dstH = 0;
2481                 yuv_fmt = 0;
2482                 break;
2483         }
2484         if (yuv_fmt) {
2485                 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2486                     (cbcr_dstH * 8 <= cbcr_srcH)) {
2487                         pr_err("ERROR: cbcr scale exceed 8,");
2488                         pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2489                                cbcr_srcH, cbcr_dstW, cbcr_dstH);
2490                 }
2491         }
2492
2493         if (cbcr_srcW < cbcr_dstW)
2494                 win->cbr_hor_scl_mode = SCALE_UP;
2495         else if (cbcr_srcW > cbcr_dstW)
2496                 win->cbr_hor_scl_mode = SCALE_DOWN;
2497         else
2498                 win->cbr_hor_scl_mode = SCALE_NONE;
2499
2500         if (cbcr_srcH < cbcr_dstH)
2501                 win->cbr_ver_scl_mode = SCALE_UP;
2502         else if (cbcr_srcH > cbcr_dstH)
2503                 win->cbr_ver_scl_mode = SCALE_DOWN;
2504         else
2505                 win->cbr_ver_scl_mode = SCALE_NONE;
2506
2507         /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
2508             "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
2509             "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW,
2510             srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH,
2511             win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW,
2512             cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode,
2513             win->cbr_ver_scl_mode);*/
2514
2515         /*line buffer mode */
2516         if ((win->area[0].format == YUV422) ||
2517             (win->area[0].format == YUV420) ||
2518             (win->area[0].format == YUV420_NV21) ||
2519             (win->area[0].format == YUV422_A) ||
2520             (win->area[0].format == YUV420_A)) {
2521                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2522                         if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2523                             (cbcr_dstW == 0))
2524                                 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2525                                        cbcr_dstW);
2526                         else if (cbcr_dstW > 1280)
2527                                 win->win_lb_mode = LB_YUV_3840X5;
2528                         else
2529                                 win->win_lb_mode = LB_YUV_2560X8;
2530                 } else {        /*SCALE_UP or SCALE_NONE */
2531                         if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2532                             (cbcr_srcW == 0))
2533                                 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2534                                        cbcr_srcW);
2535                         else if (cbcr_srcW > 1280)
2536                                 win->win_lb_mode = LB_YUV_3840X5;
2537                         else
2538                                 win->win_lb_mode = LB_YUV_2560X8;
2539                 }
2540         } else {
2541                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2542                         if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2543                             (yrgb_dstW == 0))
2544                                 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2545                         else if (yrgb_dstW > 2560)
2546                                 win->win_lb_mode = LB_RGB_3840X2;
2547                         else if (yrgb_dstW > 1920)
2548                                 win->win_lb_mode = LB_RGB_2560X4;
2549                         else if (yrgb_dstW > 1280)
2550                                 win->win_lb_mode = LB_RGB_1920X5;
2551                         else
2552                                 win->win_lb_mode = LB_RGB_1280X8;
2553                 } else {        /*SCALE_UP or SCALE_NONE */
2554                         if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2555                             (yrgb_srcW == 0))
2556                                 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2557                         else if (yrgb_srcW > 2560)
2558                                 win->win_lb_mode = LB_RGB_3840X2;
2559                         else if (yrgb_srcW > 1920)
2560                                 win->win_lb_mode = LB_RGB_2560X4;
2561                         else if (yrgb_srcW > 1280)
2562                                 win->win_lb_mode = LB_RGB_1920X5;
2563                         else
2564                                 win->win_lb_mode = LB_RGB_1280X8;
2565                 }
2566         }
2567         DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2568
2569         /*vsd/vsu scale ALGORITHM */
2570         win->yrgb_hsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2571         win->cbr_hsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2572         win->yrgb_vsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2573         win->cbr_vsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2574         switch (win->win_lb_mode) {
2575         case LB_YUV_3840X5:
2576         case LB_YUV_2560X8:
2577         case LB_RGB_1920X5:
2578         case LB_RGB_1280X8:
2579                 win->yrgb_vsu_mode = SCALE_UP_BIC;
2580                 win->cbr_vsu_mode = SCALE_UP_BIC;
2581                 break;
2582         case LB_RGB_3840X2:
2583                 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2584                         pr_err("ERROR : not allow yrgb ver scale\n");
2585                 if (win->cbr_ver_scl_mode != SCALE_NONE)
2586                         pr_err("ERROR : not allow cbcr ver scale\n");
2587                 break;
2588         case LB_RGB_2560X4:
2589                 win->yrgb_vsu_mode = SCALE_UP_BIL;
2590                 win->cbr_vsu_mode = SCALE_UP_BIL;
2591                 break;
2592         default:
2593                 pr_info("%s:un supported win_lb_mode:%d\n",
2594                         __func__, win->win_lb_mode);
2595                 break;
2596         }
2597         if (win->mirror_en == 1) {
2598                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2599         }
2600         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
2601                 /*interlace mode must bill */
2602                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2603                 win->cbr_vsd_mode = SCALE_DOWN_BIL;
2604         }
2605         if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2606             (win->area[0].fbdc_en == 1)) {
2607                 /*in this pattern,use bil mode,not support souble scd,
2608                 use avg mode, support double scd, but aclk should be
2609                 bigger than dclk,aclk>>dclk */
2610                 if (yrgb_srcH >= 2 * yrgb_dstH) {
2611                         pr_err("ERROR : fbdc mode,not support y scale down:");
2612                         pr_err("srcH[%d] > 2 *dstH[%d]\n",
2613                                yrgb_srcH, yrgb_dstH);
2614                 }
2615         }
2616         DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2617             win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2618             win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2619
2620         /*SCALE FACTOR */
2621
2622         /*(1.1)YRGB HOR SCALE FACTOR */
2623         switch (win->yrgb_hor_scl_mode) {
2624         case SCALE_NONE:
2625                 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2626                 break;
2627         case SCALE_UP:
2628                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2629                 break;
2630         case SCALE_DOWN:
2631                 switch (win->yrgb_hsd_mode) {
2632                 case SCALE_DOWN_BIL:
2633                         yrgb_xscl_factor =
2634                             GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2635                         break;
2636                 case SCALE_DOWN_AVG:
2637                         yrgb_xscl_factor =
2638                             GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2639                         break;
2640                 default:
2641                         pr_info(
2642                                 "%s:un supported yrgb_hsd_mode:%d\n", __func__,
2643                                win->yrgb_hsd_mode);
2644                         break;
2645                 }
2646                 break;
2647         default:
2648                 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2649                         __func__, win->yrgb_hor_scl_mode);
2650                 break;
2651         }                       /*win->yrgb_hor_scl_mode */
2652
2653         /*(1.2)YRGB VER SCALE FACTOR */
2654         switch (win->yrgb_ver_scl_mode) {
2655         case SCALE_NONE:
2656                 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2657                 break;
2658         case SCALE_UP:
2659                 switch (win->yrgb_vsu_mode) {
2660                 case SCALE_UP_BIL:
2661                         yrgb_yscl_factor =
2662                             GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2663                         break;
2664                 case SCALE_UP_BIC:
2665                         if (yrgb_srcH < 3) {
2666                                 pr_err("yrgb_srcH should be");
2667                                 pr_err(" greater than 3 !!!\n");
2668                         }
2669                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2670                                                                 yrgb_dstH);
2671                         break;
2672                 default:
2673                         pr_info("%s:un support yrgb_vsu_mode:%d\n",
2674                                 __func__, win->yrgb_vsu_mode);
2675                         break;
2676                 }
2677                 break;
2678         case SCALE_DOWN:
2679                 switch (win->yrgb_vsd_mode) {
2680                 case SCALE_DOWN_BIL:
2681                         yrgb_vscalednmult =
2682                             rk3368_get_hard_ware_vskiplines(yrgb_srcH,
2683                                                             yrgb_dstH);
2684                         yrgb_yscl_factor =
2685                             GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2686                                                            yrgb_vscalednmult);
2687                         if (yrgb_yscl_factor >= 0x2000) {
2688                                 pr_err("yrgb_yscl_factor should be ");
2689                                 pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n",
2690                                        yrgb_yscl_factor);
2691                         }
2692                         if (yrgb_vscalednmult == 4) {
2693                                 yrgb_vsd_bil_gt4 = 1;
2694                                 yrgb_vsd_bil_gt2 = 0;
2695                         } else if (yrgb_vscalednmult == 2) {
2696                                 yrgb_vsd_bil_gt4 = 0;
2697                                 yrgb_vsd_bil_gt2 = 1;
2698                         } else {
2699                                 yrgb_vsd_bil_gt4 = 0;
2700                                 yrgb_vsd_bil_gt2 = 0;
2701                         }
2702                         break;
2703                 case SCALE_DOWN_AVG:
2704                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2705                                                                  yrgb_dstH);
2706                         break;
2707                 default:
2708                         pr_info("%s:un support yrgb_vsd_mode:%d\n",
2709                                 __func__, win->yrgb_vsd_mode);
2710                         break;
2711                 }               /*win->yrgb_vsd_mode */
2712                 break;
2713         default:
2714                 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2715                         __func__, win->yrgb_ver_scl_mode);
2716                 break;
2717         }
2718         win->scale_yrgb_x = yrgb_xscl_factor;
2719         win->scale_yrgb_y = yrgb_yscl_factor;
2720         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2721         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2722         DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2723             yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2724
2725         /*(2.1)CBCR HOR SCALE FACTOR */
2726         switch (win->cbr_hor_scl_mode) {
2727         case SCALE_NONE:
2728                 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2729                 break;
2730         case SCALE_UP:
2731                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2732                 break;
2733         case SCALE_DOWN:
2734                 switch (win->cbr_hsd_mode) {
2735                 case SCALE_DOWN_BIL:
2736                         cbcr_xscl_factor =
2737                             GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2738                         break;
2739                 case SCALE_DOWN_AVG:
2740                         cbcr_xscl_factor =
2741                             GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2742                         break;
2743                 default:
2744                         pr_info("%s:un support cbr_hsd_mode:%d\n",
2745                                 __func__, win->cbr_hsd_mode);
2746                         break;
2747                 }
2748                 break;
2749         default:
2750                 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2751                         __func__, win->cbr_hor_scl_mode);
2752                 break;
2753         }                       /*win->cbr_hor_scl_mode */
2754
2755         /*(2.2)CBCR VER SCALE FACTOR */
2756         switch (win->cbr_ver_scl_mode) {
2757         case SCALE_NONE:
2758                 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2759                 break;
2760         case SCALE_UP:
2761                 switch (win->cbr_vsu_mode) {
2762                 case SCALE_UP_BIL:
2763                         cbcr_yscl_factor =
2764                             GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2765                         break;
2766                 case SCALE_UP_BIC:
2767                         if (cbcr_srcH < 3) {
2768                                 pr_err("cbcr_srcH should be ");
2769                                 pr_err("greater than 3 !!!\n");
2770                         }
2771                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2772                                                                 cbcr_dstH);
2773                         break;
2774                 default:
2775                         pr_info("%s:un support cbr_vsu_mode:%d\n",
2776                                 __func__, win->cbr_vsu_mode);
2777                         break;
2778                 }
2779                 break;
2780         case SCALE_DOWN:
2781                 switch (win->cbr_vsd_mode) {
2782                 case SCALE_DOWN_BIL:
2783                         cbcr_vscalednmult =
2784                             rk3368_get_hard_ware_vskiplines(cbcr_srcH,
2785                                                             cbcr_dstH);
2786                         cbcr_yscl_factor =
2787                             GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2788                                                            cbcr_vscalednmult);
2789                         if (cbcr_yscl_factor >= 0x2000) {
2790                                 pr_err("cbcr_yscl_factor should be less ");
2791                                 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2792                                        cbcr_yscl_factor);
2793                         }
2794
2795                         if (cbcr_vscalednmult == 4) {
2796                                 cbcr_vsd_bil_gt4 = 1;
2797                                 cbcr_vsd_bil_gt2 = 0;
2798                         } else if (cbcr_vscalednmult == 2) {
2799                                 cbcr_vsd_bil_gt4 = 0;
2800                                 cbcr_vsd_bil_gt2 = 1;
2801                         } else {
2802                                 cbcr_vsd_bil_gt4 = 0;
2803                                 cbcr_vsd_bil_gt2 = 0;
2804                         }
2805                         break;
2806                 case SCALE_DOWN_AVG:
2807                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2808                                                                  cbcr_dstH);
2809                         break;
2810                 default:
2811                         pr_info("%s:un support cbr_vsd_mode:%d\n",
2812                                 __func__, win->cbr_vsd_mode);
2813                         break;
2814                 }
2815                 break;
2816         default:
2817                 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2818                         __func__, win->cbr_ver_scl_mode);
2819                 break;
2820         }
2821         win->scale_cbcr_x = cbcr_xscl_factor;
2822         win->scale_cbcr_y = cbcr_yscl_factor;
2823         win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2824         win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2825
2826         DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2827             cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2828         return 0;
2829 }
2830
2831 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2832                      struct rk_lcdc_win_area *area)
2833 {
2834         int pos;
2835
2836         if (screen->x_mirror && mirror_en)
2837                 pr_err("not support both win and global mirror\n");
2838
2839         if ((!mirror_en) && (!screen->x_mirror))
2840                 pos = area->xpos + screen->mode.left_margin +
2841                         screen->mode.hsync_len;
2842         else
2843                 pos = screen->mode.xres - area->xpos -
2844                         area->xsize + screen->mode.left_margin +
2845                         screen->mode.hsync_len;
2846
2847         return pos;
2848 }
2849
2850 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2851                      struct rk_lcdc_win_area *area)
2852 {
2853         int pos;
2854
2855         if (screen->y_mirror && mirror_en)
2856                 pr_err("not support both win and global mirror\n");
2857         if (screen->mode.vmode == FB_VMODE_NONINTERLACED) {
2858                 if ((!mirror_en) && (!screen->y_mirror))
2859                         pos = area->ypos + screen->mode.upper_margin +
2860                                 screen->mode.vsync_len;
2861                 else
2862                         pos = screen->mode.yres - area->ypos -
2863                                 area->ysize + screen->mode.upper_margin +
2864                                 screen->mode.vsync_len;
2865         } else if (screen->mode.vmode == FB_VMODE_INTERLACED) {
2866                 pos = area->ypos / 2 + screen->mode.upper_margin +
2867                         screen->mode.vsync_len;
2868                 area->ysize /= 2;
2869         }
2870
2871         return pos;
2872 }
2873
2874 static int win_0_1_set_par(struct lcdc_device *lcdc_dev,
2875                            struct rk_screen *screen, struct rk_lcdc_win *win)
2876 {
2877         u32 xact, yact, xvir, yvir, xpos, ypos;
2878         u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2879         char fmt[9] = "NULL";
2880
2881         xpos = dsp_x_pos(win->mirror_en, screen, &win->area[0]);
2882         ypos = dsp_y_pos(win->mirror_en, screen, &win->area[0]);
2883
2884         spin_lock(&lcdc_dev->reg_lock);
2885         if (likely(lcdc_dev->clk_on)) {
2886                 rk3368_lcdc_cal_scl_fac(win, screen);   /*fac,lb,gt2,gt4 */
2887                 switch (win->area[0].format) {
2888                 case FBDC_RGB_565:
2889                         fmt_cfg = 2;
2890                         swap_rb = 0;
2891                         win->fmt_10 = 0;
2892                         win->area[0].fbdc_fmt_cfg = 0x05;
2893                         break;
2894                 case FBDC_ARGB_888:
2895                         fmt_cfg = 0;
2896                         swap_rb = 0;
2897                         win->fmt_10 = 0;
2898                         win->area[0].fbdc_fmt_cfg = 0x0c;
2899                         break;
2900                 case FBDC_ABGR_888:
2901                         fmt_cfg = 0;
2902                         swap_rb = 1;
2903                         win->fmt_10 = 0;
2904                         win->area[0].fbdc_fmt_cfg = 0x0c;
2905                         break;
2906                 case FBDC_RGBX_888:
2907                         fmt_cfg = 0;
2908                         swap_rb = 0;
2909                         win->fmt_10 = 0;
2910                         win->area[0].fbdc_fmt_cfg = 0x3a;
2911                         break;
2912                 case ARGB888:
2913                         fmt_cfg = 0;
2914                         swap_rb = 0;
2915                         win->fmt_10 = 0;
2916                         break;
2917                 case XBGR888:
2918                 case ABGR888:
2919                         fmt_cfg = 0;
2920                         swap_rb = 1;
2921                         win->fmt_10 = 0;
2922                         break;
2923                 case RGB888:
2924                         fmt_cfg = 1;
2925                         swap_rb = 0;
2926                         win->fmt_10 = 0;
2927                         break;
2928                 case RGB565:
2929                         fmt_cfg = 2;
2930                         swap_rb = 0;
2931                         win->fmt_10 = 0;
2932                         break;
2933                 case YUV422:
2934                         fmt_cfg = 5;
2935                         swap_rb = 0;
2936                         win->fmt_10 = 0;
2937                         break;
2938                 case YUV420:
2939                         fmt_cfg = 4;
2940                         swap_rb = 0;
2941                         win->fmt_10 = 0;
2942                         break;
2943                 case YUV420_NV21:
2944                         fmt_cfg = 4;
2945                         swap_rb = 0;
2946                         swap_uv = 1;
2947                         win->fmt_10 = 0;
2948                         break;
2949                 case YUV444:
2950                         fmt_cfg = 6;
2951                         swap_rb = 0;
2952                         win->fmt_10 = 0;
2953                         break;
2954                 case YUV422_A:
2955                         fmt_cfg = 5;
2956                         swap_rb = 0;
2957                         win->fmt_10 = 1;
2958                         break;
2959                 case YUV420_A:
2960                         fmt_cfg = 4;
2961                         swap_rb = 0;
2962                         win->fmt_10 = 1;
2963                         break;
2964                 case YUV444_A:
2965                         fmt_cfg = 6;
2966                         swap_rb = 0;
2967                         win->fmt_10 = 1;
2968                         break;
2969                 default:
2970                         dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n",
2971                                 __func__);
2972                         break;
2973                 }
2974                 win->area[0].fmt_cfg = fmt_cfg;
2975                 win->area[0].swap_rb = swap_rb;
2976                 win->area[0].swap_uv = swap_uv;
2977                 win->area[0].dsp_stx = xpos;
2978                 win->area[0].dsp_sty = ypos;
2979                 xact = win->area[0].xact;
2980                 yact = win->area[0].yact;
2981                 xvir = win->area[0].xvir;
2982                 yvir = win->area[0].yvir;
2983         }
2984         if (win->area[0].fbdc_en)
2985                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2986         rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id);
2987         spin_unlock(&lcdc_dev->reg_lock);
2988
2989         DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2990             lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2991             xact, yact, win->area[0].xsize);
2992         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2993             win->area[0].ysize, xvir, yvir, xpos, ypos);
2994
2995         return 0;
2996 }
2997
2998
2999 static int win_2_3_set_par(struct lcdc_device *lcdc_dev,
3000                            struct rk_screen *screen, struct rk_lcdc_win *win)
3001 {
3002         int i;
3003         u8 fmt_cfg, swap_rb;
3004         char fmt[9] = "NULL";
3005
3006         if (win->mirror_en)
3007                 pr_err("win[%d] not support y mirror\n", win->id);
3008         spin_lock(&lcdc_dev->reg_lock);
3009         if (likely(lcdc_dev->clk_on)) {
3010                 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id);
3011                 for (i = 0; i < win->area_num; i++) {
3012                         switch (win->area[i].format) {
3013                         case FBDC_RGB_565:
3014                                 fmt_cfg = 2;
3015                                 swap_rb = 0;
3016                                 win->fmt_10 = 0;
3017                                 win->area[0].fbdc_fmt_cfg = 0x05;
3018                                 break;
3019                         case FBDC_ARGB_888:
3020                                 fmt_cfg = 0;
3021                                 swap_rb = 0;
3022                                 win->fmt_10 = 0;
3023                                 win->area[0].fbdc_fmt_cfg = 0x0c;
3024                                 break;
3025                         case FBDC_RGBX_888:
3026                                 fmt_cfg = 0;
3027                                 swap_rb = 0;
3028                                 win->fmt_10 = 0;
3029                                 win->area[0].fbdc_fmt_cfg = 0x3a;
3030                                 break;
3031                         case ARGB888:
3032                                 fmt_cfg = 0;
3033                                 swap_rb = 0;
3034                                 break;
3035                         case XBGR888:
3036                         case ABGR888:
3037                                 fmt_cfg = 0;
3038                                 swap_rb = 1;
3039                                 break;
3040                         case RGB888:
3041                                 fmt_cfg = 1;
3042                                 swap_rb = 0;
3043                                 break;
3044                         case RGB565:
3045                                 fmt_cfg = 2;
3046                                 swap_rb = 0;
3047                                 break;
3048                         default:
3049                                 dev_err(lcdc_dev->driver.dev,
3050                                         "%s:un supported format!\n", __func__);
3051                                 break;
3052                         }
3053                         win->area[i].fmt_cfg = fmt_cfg;
3054                         win->area[i].swap_rb = swap_rb;
3055                         win->area[i].dsp_stx =
3056                                         dsp_x_pos(win->mirror_en, screen,
3057                                                   &win->area[i]);
3058                         win->area[i].dsp_sty =
3059                                         dsp_y_pos(win->mirror_en, screen,
3060                                                   &win->area[i]);
3061                         if (((win->area[i].xact != win->area[i].xsize) ||
3062                             (win->area[i].yact != win->area[i].ysize)) &&
3063                             (screen->mode.vmode == FB_VMODE_NONINTERLACED)) {
3064                                 pr_err("win[%d]->area[%d],not support scale\n",
3065                                         win->id, i);
3066                                 pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
3067                                         win->area[i].xact,win->area[i].yact,
3068                                         win->area[i].xsize,win->area[i].ysize);
3069                                 win->area[i].xsize = win->area[i].xact;
3070                                 win->area[i].ysize = win->area[i].yact;
3071                         }
3072                         DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
3073                             get_format_string(win->area[i].format, fmt),
3074                             win->area[i].xsize, win->area[i].ysize,
3075                             win->area[i].xpos, win->area[i].ypos);
3076                 }
3077         }
3078         if (win->area[0].fbdc_en)
3079                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
3080         rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id);
3081         spin_unlock(&lcdc_dev->reg_lock);
3082         return 0;
3083 }
3084
3085 static int hwc_set_par(struct lcdc_device *lcdc_dev,
3086                        struct rk_screen *screen, struct rk_lcdc_win *win)
3087 {
3088         u32 xact, yact, xvir, yvir, xpos, ypos;
3089         u8 fmt_cfg = 0, swap_rb;
3090         char fmt[9] = "NULL";
3091
3092         xpos = win->area[0].xpos + screen->mode.left_margin +
3093             screen->mode.hsync_len;
3094         ypos = win->area[0].ypos + screen->mode.upper_margin +
3095             screen->mode.vsync_len;
3096
3097         spin_lock(&lcdc_dev->reg_lock);
3098         if (likely(lcdc_dev->clk_on)) {
3099                 /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */
3100                 switch (win->area[0].format) {
3101                 case ARGB888:
3102                         fmt_cfg = 0;
3103                         swap_rb = 0;
3104                         break;
3105                 case XBGR888:
3106                 case ABGR888:
3107                         fmt_cfg = 0;
3108                         swap_rb = 1;
3109                         break;
3110                 case RGB888:
3111                         fmt_cfg = 1;
3112                         swap_rb = 0;
3113                         break;
3114                 case RGB565:
3115                         fmt_cfg = 2;
3116                         swap_rb = 0;
3117                         break;
3118                 default:
3119                         dev_err(lcdc_dev->driver.dev,
3120                                 "%s:un supported format!\n", __func__);
3121                         break;
3122                 }
3123                 win->area[0].fmt_cfg = fmt_cfg;
3124                 win->area[0].swap_rb = swap_rb;
3125                 win->area[0].dsp_stx = xpos;
3126                 win->area[0].dsp_sty = ypos;
3127                 xact = win->area[0].xact;
3128                 yact = win->area[0].yact;
3129                 xvir = win->area[0].xvir;
3130                 yvir = win->area[0].yvir;
3131         }
3132         rk3368_hwc_reg_update(&lcdc_dev->driver, 4);
3133         spin_unlock(&lcdc_dev->reg_lock);
3134
3135         DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
3136             lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt),
3137             xact, yact, win->area[0].xsize);
3138         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
3139             win->area[0].ysize, xvir, yvir, xpos, ypos);
3140         return 0;
3141 }
3142
3143 static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
3144 {
3145         struct lcdc_device *lcdc_dev =
3146             container_of(dev_drv, struct lcdc_device, driver);
3147         struct rk_lcdc_win *win = NULL;
3148         struct rk_screen *screen = dev_drv->cur_screen;
3149
3150         if (unlikely(!lcdc_dev->clk_on)) {
3151                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
3152                 return 0;
3153         }
3154         win = dev_drv->win[win_id];
3155         switch (win_id) {
3156         case 0:
3157                 win_0_1_set_par(lcdc_dev, screen, win);
3158                 break;
3159         case 1:
3160                 win_0_1_set_par(lcdc_dev, screen, win);
3161                 break;
3162         case 2:
3163                 win_2_3_set_par(lcdc_dev, screen, win);
3164                 break;
3165         case 3:
3166                 win_2_3_set_par(lcdc_dev, screen, win);
3167                 break;
3168         case 4:
3169                 hwc_set_par(lcdc_dev, screen, win);
3170                 break;
3171         default:
3172                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
3173                 break;
3174         }
3175         return 0;
3176 }
3177
3178 static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
3179                              unsigned long arg, int win_id)
3180 {
3181         struct lcdc_device *lcdc_dev =
3182             container_of(dev_drv, struct lcdc_device, driver);
3183         u32 panel_size[2];
3184         void __user *argp = (void __user *)arg;
3185         struct color_key_cfg clr_key_cfg;
3186
3187         switch (cmd) {
3188         case RK_FBIOGET_PANEL_SIZE:
3189                 panel_size[0] = lcdc_dev->screen->mode.xres;
3190                 panel_size[1] = lcdc_dev->screen->mode.yres;
3191                 if (copy_to_user(argp, panel_size, 8))
3192                         return -EFAULT;
3193                 break;
3194         case RK_FBIOPUT_COLOR_KEY_CFG:
3195                 if (copy_from_user(&clr_key_cfg, argp,
3196                                    sizeof(struct color_key_cfg)))
3197                         return -EFAULT;
3198                 rk3368_lcdc_clr_key_cfg(dev_drv);
3199                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
3200                             clr_key_cfg.win0_color_key_cfg);
3201                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
3202                             clr_key_cfg.win1_color_key_cfg);
3203                 break;
3204
3205         default:
3206                 break;
3207         }
3208         return 0;
3209 }
3210
3211 static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
3212 {
3213         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3214                                                     struct lcdc_device, driver);
3215         struct device_node *backlight;
3216         struct property *prop;
3217         u32 brightness_levels[256];
3218         u32 length, max, last;
3219
3220         if (lcdc_dev->backlight)
3221                 return 0;
3222         backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0);
3223         if (backlight) {
3224                 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
3225                 if (!lcdc_dev->backlight)
3226                         dev_info(lcdc_dev->dev, "No find backlight device\n");
3227         } else {
3228                 dev_info(lcdc_dev->dev, "No find backlight device node\n");
3229         }
3230         prop = of_find_property(backlight, "brightness-levels", &length);
3231         if (!prop)
3232                 return -EINVAL;
3233         max = length / sizeof(u32);
3234         last = max - 1;
3235         if (!of_property_read_u32_array(backlight, "brightness-levels", brightness_levels, max)) {
3236                 if (brightness_levels[0] > brightness_levels[last])
3237                         dev_drv->cabc_pwm_pol = 1;/*negative*/
3238                 else
3239                         dev_drv->cabc_pwm_pol = 0;/*positive*/
3240         } else {
3241                 dev_info(lcdc_dev->dev, "Can not read brightness-levels value\n");
3242         }
3243         return 0;
3244 }
3245
3246 static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
3247 {
3248         struct lcdc_device *lcdc_dev =
3249             container_of(dev_drv, struct lcdc_device, driver);
3250         if (dev_drv->suspend_flag)
3251                 return 0;
3252         /* close the backlight */
3253         /*rk3368_lcdc_get_backlight_device(dev_drv);
3254         if (lcdc_dev->backlight) {
3255                 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
3256                 backlight_update_status(lcdc_dev->backlight);
3257         }*/
3258
3259         dev_drv->suspend_flag = 1;
3260         flush_kthread_worker(&dev_drv->update_regs_worker);
3261
3262         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3263                 dev_drv->trsm_ops->disable();
3264
3265         spin_lock(&lcdc_dev->reg_lock);
3266         if (likely(lcdc_dev->clk_on)) {
3267                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3268                              v_DSP_BLANK_EN(1));
3269                 lcdc_msk_reg(lcdc_dev,
3270                              INTR_CLEAR, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR,
3271                              v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1));
3272                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3273                              v_DSP_OUT_ZERO(1));
3274                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
3275                 lcdc_cfg_done(lcdc_dev);
3276
3277                 if (dev_drv->iommu_enabled) {
3278                         if (dev_drv->mmu_dev)
3279                                 rockchip_iovmm_deactivate(dev_drv->dev);
3280                 }
3281
3282                 spin_unlock(&lcdc_dev->reg_lock);
3283         } else {
3284                 spin_unlock(&lcdc_dev->reg_lock);
3285                 return 0;
3286         }
3287         rk3368_lcdc_clk_disable(lcdc_dev);
3288         rk_disp_pwr_disable(dev_drv);
3289         return 0;
3290 }
3291
3292 static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
3293 {
3294         struct lcdc_device *lcdc_dev =
3295             container_of(dev_drv, struct lcdc_device, driver);
3296
3297         if (!dev_drv->suspend_flag)
3298                 return 0;
3299         rk_disp_pwr_enable(dev_drv);
3300
3301         if (1/*lcdc_dev->atv_layer_cnt*/) {
3302                 rk3368_lcdc_clk_enable(lcdc_dev);
3303                 rk3368_lcdc_reg_restore(lcdc_dev);
3304
3305                 spin_lock(&lcdc_dev->reg_lock);
3306                 if (dev_drv->cur_screen->dsp_lut)
3307                         rk3368_lcdc_set_lut(dev_drv,
3308                                             dev_drv->cur_screen->dsp_lut);
3309                 if (dev_drv->cur_screen->cabc_lut)
3310                         rk3368_set_cabc_lut(dev_drv,
3311                                             dev_drv->cur_screen->cabc_lut);
3312
3313                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3314                              v_DSP_OUT_ZERO(0));
3315                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
3316                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3317                              v_DSP_BLANK_EN(0));
3318                 lcdc_cfg_done(lcdc_dev);
3319
3320                 if (dev_drv->iommu_enabled) {
3321                         /* win address maybe effect after next frame start,
3322                          * but mmu maybe effect right now, so we delay 50ms
3323                          */
3324                         mdelay(50);
3325                         if (dev_drv->mmu_dev)
3326                                 rockchip_iovmm_activate(dev_drv->dev);
3327                 }
3328
3329                 spin_unlock(&lcdc_dev->reg_lock);
3330         }
3331         dev_drv->suspend_flag = 0;
3332
3333         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3334                 dev_drv->trsm_ops->enable();
3335         mdelay(100);
3336         return 0;
3337 }
3338
3339 static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv,
3340                              int win_id, int blank_mode)
3341 {
3342         switch (blank_mode) {
3343         case FB_BLANK_UNBLANK:
3344                 rk3368_lcdc_early_resume(dev_drv);
3345                 break;
3346         case FB_BLANK_NORMAL:
3347                 rk3368_lcdc_early_suspend(dev_drv);
3348                 break;
3349         default:
3350                 rk3368_lcdc_early_suspend(dev_drv);
3351                 break;
3352         }
3353
3354         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
3355
3356         return 0;
3357 }
3358
3359 static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv,
3360                                            int win_id, int area_id)
3361 {
3362         struct lcdc_device *lcdc_dev =
3363             container_of(dev_drv, struct lcdc_device, driver);
3364         u32 win_ctrl = 0;
3365         u32 area_status = 0, state = 0;
3366
3367         switch (win_id) {
3368         case 0:
3369                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3370                 area_status = win_ctrl & m_WIN0_EN;
3371                 break;
3372         case 1:
3373                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3374                 area_status = win_ctrl & m_WIN1_EN;
3375                 break;
3376         case 2:
3377                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3378                 if (area_id == 0)
3379                         area_status = win_ctrl & (m_WIN2_MST0_EN | m_WIN2_EN);
3380                 if (area_id == 1)
3381                         area_status = win_ctrl & m_WIN2_MST1_EN;
3382                 if (area_id == 2)
3383                         area_status = win_ctrl & m_WIN2_MST2_EN;
3384                 if (area_id == 3)
3385                         area_status = win_ctrl & m_WIN2_MST3_EN;
3386                 break;
3387         case 3:
3388                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3389                 if (area_id == 0)
3390                         area_status = win_ctrl & (m_WIN3_MST0_EN | m_WIN3_EN);
3391                 if (area_id == 1)
3392                         area_status = win_ctrl & m_WIN3_MST1_EN;
3393                 if (area_id == 2)
3394                         area_status = win_ctrl & m_WIN3_MST2_EN;
3395                 if (area_id == 3)
3396                         area_status = win_ctrl & m_WIN3_MST3_EN;
3397                 break;
3398         case 4:
3399                 win_ctrl = lcdc_readl(lcdc_dev, HWC_CTRL0);
3400                 area_status = win_ctrl & m_HWC_EN;
3401                 break;
3402         default:
3403                 pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n",__func__,win_id,area_id);
3404                 break;
3405         }
3406
3407         state = (area_status > 0) ? 1 : 0;
3408         return state;
3409 }
3410
3411 static int rk3368_lcdc_get_area_num(struct rk_lcdc_driver *dev_drv,
3412                                            unsigned int *area_support)
3413 {
3414         area_support[0] = 1;
3415         area_support[1] = 1;
3416         area_support[2] = 4;
3417         area_support[3] = 4;
3418
3419         return 0;
3420 }
3421
3422 /*overlay will be do at regupdate*/
3423 static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
3424                                bool set)
3425 {
3426         struct lcdc_device *lcdc_dev =
3427             container_of(dev_drv, struct lcdc_device, driver);
3428         struct rk_lcdc_win *win = NULL;
3429         int i, ovl;
3430         unsigned int mask, val;
3431         int z_order_num = 0;
3432         int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3433
3434         if (swap == 0) {
3435                 for (i = 0; i < 4; i++) {
3436                         win = dev_drv->win[i];
3437                         if (win->state == 1)
3438                                 z_order_num++;
3439                 }
3440                 for (i = 0; i < 4; i++) {
3441                         win = dev_drv->win[i];
3442                         if (win->state == 0)
3443                                 win->z_order = z_order_num++;
3444                         switch (win->z_order) {
3445                         case 0:
3446                                 layer0_sel = win->id;
3447                                 break;
3448                         case 1:
3449                                 layer1_sel = win->id;
3450                                 break;
3451                         case 2:
3452                                 layer2_sel = win->id;
3453                                 break;
3454                         case 3:
3455                                 layer3_sel = win->id;
3456                                 break;
3457                         default:
3458                                 break;
3459                         }
3460                 }
3461         } else {
3462                 layer0_sel = swap % 10;
3463                 layer1_sel = swap / 10 % 10;
3464                 layer2_sel = swap / 100 % 10;
3465                 layer3_sel = swap / 1000;
3466         }
3467
3468         spin_lock(&lcdc_dev->reg_lock);
3469         if (lcdc_dev->clk_on) {
3470                 if (set) {
3471                         mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
3472                             m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
3473                         val = v_DSP_LAYER0_SEL(layer0_sel) |
3474                             v_DSP_LAYER1_SEL(layer1_sel) |
3475                             v_DSP_LAYER2_SEL(layer2_sel) |
3476                             v_DSP_LAYER3_SEL(layer3_sel);
3477                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
3478                 } else {
3479                         layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3480                                                    m_DSP_LAYER0_SEL);
3481                         layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3482                                                    m_DSP_LAYER1_SEL);
3483                         layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3484                                                    m_DSP_LAYER2_SEL);
3485                         layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3486                                                    m_DSP_LAYER3_SEL);
3487                         ovl = layer3_sel * 1000 + layer2_sel * 100 +
3488                             layer1_sel * 10 + layer0_sel;
3489                 }
3490         } else {
3491                 ovl = -EPERM;
3492         }
3493         spin_unlock(&lcdc_dev->reg_lock);
3494
3495         return ovl;
3496 }
3497
3498 static char *rk3368_lcdc_format_to_string(int format, char *fmt)
3499 {
3500         if (!fmt)
3501                 return NULL;
3502
3503         switch (format) {
3504         case 0:
3505                 strcpy(fmt, "ARGB888");
3506                 break;
3507         case 1:
3508                 strcpy(fmt, "RGB888");
3509                 break;
3510         case 2:
3511                 strcpy(fmt, "RGB565");
3512                 break;
3513         case 4:
3514                 strcpy(fmt, "YCbCr420");
3515                 break;
3516         case 5:
3517                 strcpy(fmt, "YCbCr422");
3518                 break;
3519         case 6:
3520                 strcpy(fmt, "YCbCr444");
3521                 break;
3522         default:
3523                 strcpy(fmt, "invalid\n");
3524                 break;
3525         }
3526         return fmt;
3527 }
3528 static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
3529                                          char *buf, int win_id)
3530 {
3531         struct lcdc_device *lcdc_dev =
3532             container_of(dev_drv, struct lcdc_device, driver);
3533         struct rk_screen *screen = dev_drv->cur_screen;
3534         u16 hsync_len = screen->mode.hsync_len;
3535         u16 left_margin = screen->mode.left_margin;
3536         u16 vsync_len = screen->mode.vsync_len;
3537         u16 upper_margin = screen->mode.upper_margin;
3538         u32 h_pw_bp = hsync_len + left_margin;
3539         u32 v_pw_bp = vsync_len + upper_margin;
3540         u32 fmt_id;
3541         char format_w0[9] = "NULL";
3542         char format_w1[9] = "NULL";
3543         char format_w2_0[9] = "NULL";
3544         char format_w2_1[9] = "NULL";
3545         char format_w2_2[9] = "NULL";
3546         char format_w2_3[9] = "NULL";
3547         char format_w3_0[9] = "NULL";
3548         char format_w3_1[9] = "NULL";
3549         char format_w3_2[9] = "NULL";
3550         char format_w3_3[9] = "NULL";
3551         char dsp_buf[100];
3552         u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3553         u32 y_factor, uv_factor;
3554         u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3555         u8 w0_state, w1_state, w2_state, w3_state;
3556         u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3557         u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3558
3559         u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3560         u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3561         u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3562         u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3563         u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3564         u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3565
3566         u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3567         u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3568         u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3569         u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3570         u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3571         u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3572         u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3573
3574         u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3575         u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3576         u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3577         u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3578         u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3579         u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3580         u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3581         u32 dclk_freq;
3582         int size = 0;
3583
3584         dclk_freq = screen->mode.pixclock;
3585         /*rk3368_lcdc_reg_dump(dev_drv); */
3586
3587         spin_lock(&lcdc_dev->reg_lock);
3588         if (lcdc_dev->clk_on) {
3589                 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
3590                 layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8;
3591                 layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10;
3592                 layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12;
3593                 layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14;
3594                 /*WIN0 */
3595                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3596                 w0_state = win_ctrl & m_WIN0_EN;
3597                 fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1;
3598                 rk3368_lcdc_format_to_string(fmt_id, format_w0);
3599                 vir_info = lcdc_readl(lcdc_dev, WIN0_VIR);
3600                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
3601                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
3602                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
3603                 y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
3604                 uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR);
3605                 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
3606                 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16;
3607                 w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1;
3608                 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1;
3609                 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1;
3610                 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1;
3611                 if (w0_state) {
3612                         w0_st_x = dsp_st & m_WIN0_DSP_XST;
3613                         w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16;
3614                 }
3615                 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
3616                 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16;
3617                 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
3618                 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16;
3619
3620                 /*WIN1 */
3621                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3622                 w1_state = win_ctrl & m_WIN1_EN;
3623                 fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1;
3624                 rk3368_lcdc_format_to_string(fmt_id, format_w1);
3625                 vir_info = lcdc_readl(lcdc_dev, WIN1_VIR);
3626                 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
3627                 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
3628                 dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
3629                 y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB);
3630                 uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR);
3631                 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
3632                 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16;
3633                 w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1;
3634                 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1;
3635                 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1;
3636                 w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1;
3637                 if (w1_state) {
3638                         w1_st_x = dsp_st & m_WIN1_DSP_XST;
3639                         w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16;
3640                 }
3641                 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
3642                 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16;
3643                 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
3644                 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16;
3645                 /*WIN2 */
3646                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3647                 w2_state = win_ctrl & m_WIN2_EN;
3648                 w2_0_state = (win_ctrl & 0x10) >> 4;
3649                 w2_1_state = (win_ctrl & 0x100) >> 8;
3650                 w2_2_state = (win_ctrl & 0x1000) >> 12;
3651                 w2_3_state = (win_ctrl & 0x10000) >> 16;
3652                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1);
3653                 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3654                 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16;
3655                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3);
3656                 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3657                 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16;
3658
3659                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1;
3660                 rk3368_lcdc_format_to_string(fmt_id, format_w2_0);
3661                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1;
3662                 rk3368_lcdc_format_to_string(fmt_id, format_w2_1);
3663                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1;
3664                 rk3368_lcdc_format_to_string(fmt_id, format_w2_2);
3665                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1;
3666                 rk3368_lcdc_format_to_string(fmt_id, format_w2_3);
3667
3668                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0);
3669                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0);
3670                 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1;
3671                 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1;
3672                 if (w2_0_state) {
3673                         w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3674                         w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16;
3675                 }
3676                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1);
3677                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1);
3678                 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1;
3679                 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1;
3680                 if (w2_1_state) {
3681                         w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3682                         w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16;
3683                 }
3684                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2);
3685                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2);
3686                 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1;
3687                 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1;
3688                 if (w2_2_state) {
3689                         w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3690                         w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16;
3691                 }
3692                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3);
3693                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3);
3694                 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1;
3695                 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1;
3696                 if (w2_3_state) {
3697                         w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3698                         w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16;
3699                 }
3700
3701                 /*WIN3 */
3702                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3703                 w3_state = win_ctrl & m_WIN3_EN;
3704                 w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4;
3705                 w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 8;
3706                 w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 12;
3707                 w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 16;
3708                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1);
3709                 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3710                 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16;
3711                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3);
3712                 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3713                 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16;
3714                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1;
3715                 rk3368_lcdc_format_to_string(fmt_id, format_w3_0);
3716                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1;
3717                 rk3368_lcdc_format_to_string(fmt_id, format_w3_1);
3718                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1;
3719                 rk3368_lcdc_format_to_string(fmt_id, format_w3_2);
3720                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1;
3721                 rk3368_lcdc_format_to_string(fmt_id, format_w3_3);
3722                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0);
3723                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0);
3724                 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1;
3725                 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1;
3726                 if (w3_0_state) {
3727                         w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3728                         w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16;
3729                 }
3730
3731                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1);
3732                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1);
3733                 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1;
3734                 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1;
3735                 if (w3_1_state) {
3736                         w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3737                         w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16;
3738                 }
3739
3740                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2);
3741                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2);
3742                 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1;
3743                 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1;
3744                 if (w3_2_state) {
3745                         w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3746                         w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16;
3747                 }
3748
3749                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3);
3750                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3);
3751                 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1;
3752                 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1;
3753                 if (w3_3_state) {
3754                         w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3755                         w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16;
3756                 }
3757
3758         } else {
3759                 spin_unlock(&lcdc_dev->reg_lock);
3760                 return -EPERM;
3761         }
3762         spin_unlock(&lcdc_dev->reg_lock);
3763         size += snprintf(dsp_buf, 80,
3764                 "z-order:\n  win[%d]\n  win[%d]\n  win[%d]\n  win[%d]\n",
3765                 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3766         strcat(buf, dsp_buf);
3767         memset(dsp_buf, 0, sizeof(dsp_buf));
3768         /*win0*/
3769         size += snprintf(dsp_buf, 80,
3770                  "win0:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3771                  w0_state, format_w0, w0_vir_y, w0_vir_uv);
3772         strcat(buf, dsp_buf);
3773         memset(dsp_buf, 0, sizeof(dsp_buf));
3774
3775         size += snprintf(dsp_buf, 80,
3776                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3777                  w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3778         strcat(buf, dsp_buf);
3779         memset(dsp_buf, 0, sizeof(dsp_buf));
3780
3781         size += snprintf(dsp_buf, 80,
3782                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3783                  w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3784         strcat(buf, dsp_buf);
3785         memset(dsp_buf, 0, sizeof(dsp_buf));
3786
3787         size += snprintf(dsp_buf, 80,
3788                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3789                  w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3790                  lcdc_readl(lcdc_dev, WIN0_CBR_MST));
3791         strcat(buf, dsp_buf);
3792         memset(dsp_buf, 0, sizeof(dsp_buf));
3793
3794         /*win1*/
3795         size += snprintf(dsp_buf, 80,
3796                  "win1:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3797                  w1_state, format_w1, w1_vir_y, w1_vir_uv);
3798         strcat(buf, dsp_buf);
3799         memset(dsp_buf, 0, sizeof(dsp_buf));
3800
3801         size += snprintf(dsp_buf, 80,
3802                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3803                  w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3804         strcat(buf, dsp_buf);
3805         memset(dsp_buf, 0, sizeof(dsp_buf));
3806
3807         size += snprintf(dsp_buf, 80,
3808                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3809                  w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3810         strcat(buf, dsp_buf);
3811         memset(dsp_buf, 0, sizeof(dsp_buf));
3812
3813         size += snprintf(dsp_buf, 80,
3814                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3815                  w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3816                  lcdc_readl(lcdc_dev, WIN1_CBR_MST));
3817         strcat(buf, dsp_buf);
3818         memset(dsp_buf, 0, sizeof(dsp_buf));
3819
3820         /*win2*/
3821         size += snprintf(dsp_buf, 80,
3822                  "win2:\n  state:%d\n",
3823                  w2_state);
3824         strcat(buf, dsp_buf);
3825         memset(dsp_buf, 0, sizeof(dsp_buf));
3826         /*area 0*/
3827         size += snprintf(dsp_buf, 80,
3828                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3829                  w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3830         strcat(buf, dsp_buf);
3831         memset(dsp_buf, 0, sizeof(dsp_buf));
3832         size += snprintf(dsp_buf, 80,
3833                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3834                  w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3835                  lcdc_readl(lcdc_dev, WIN2_MST0));
3836         strcat(buf, dsp_buf);
3837         memset(dsp_buf, 0, sizeof(dsp_buf));
3838
3839         /*area 1*/
3840         size += snprintf(dsp_buf, 80,
3841                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3842                  w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3843         strcat(buf, dsp_buf);
3844         memset(dsp_buf, 0, sizeof(dsp_buf));
3845         size += snprintf(dsp_buf, 80,
3846                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3847                  w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3848                  lcdc_readl(lcdc_dev, WIN2_MST1));
3849         strcat(buf, dsp_buf);
3850         memset(dsp_buf, 0, sizeof(dsp_buf));
3851
3852         /*area 2*/
3853         size += snprintf(dsp_buf, 80,
3854                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3855                  w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3856         strcat(buf, dsp_buf);
3857         memset(dsp_buf, 0, sizeof(dsp_buf));
3858         size += snprintf(dsp_buf, 80,
3859                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3860                  w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3861                  lcdc_readl(lcdc_dev, WIN2_MST2));
3862         strcat(buf, dsp_buf);
3863         memset(dsp_buf, 0, sizeof(dsp_buf));
3864
3865         /*area 3*/
3866         size += snprintf(dsp_buf, 80,
3867                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3868                  w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3869         strcat(buf, dsp_buf);
3870         memset(dsp_buf, 0, sizeof(dsp_buf));
3871         size += snprintf(dsp_buf, 80,
3872                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3873                  w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3874                  lcdc_readl(lcdc_dev, WIN2_MST3));
3875         strcat(buf, dsp_buf);
3876         memset(dsp_buf, 0, sizeof(dsp_buf));
3877
3878         /*win3*/
3879         size += snprintf(dsp_buf, 80,
3880                  "win3:\n  state:%d\n",
3881                  w3_state);
3882         strcat(buf, dsp_buf);
3883         memset(dsp_buf, 0, sizeof(dsp_buf));
3884         /*area 0*/
3885         size += snprintf(dsp_buf, 80,
3886                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3887                  w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
3888         strcat(buf, dsp_buf);
3889         memset(dsp_buf, 0, sizeof(dsp_buf));
3890         size += snprintf(dsp_buf, 80,
3891                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3892                  w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
3893                  lcdc_readl(lcdc_dev, WIN3_MST0));
3894         strcat(buf, dsp_buf);
3895         memset(dsp_buf, 0, sizeof(dsp_buf));
3896
3897         /*area 1*/
3898         size += snprintf(dsp_buf, 80,
3899                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3900                  w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
3901         strcat(buf, dsp_buf);
3902         memset(dsp_buf, 0, sizeof(dsp_buf));
3903         size += snprintf(dsp_buf, 80,
3904                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3905                  w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
3906                  lcdc_readl(lcdc_dev, WIN3_MST1));
3907         strcat(buf, dsp_buf);
3908         memset(dsp_buf, 0, sizeof(dsp_buf));
3909
3910         /*area 2*/
3911         size += snprintf(dsp_buf, 80,
3912                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3913                  w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
3914         strcat(buf, dsp_buf);
3915         memset(dsp_buf, 0, sizeof(dsp_buf));
3916         size += snprintf(dsp_buf, 80,
3917                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3918                  w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
3919                  lcdc_readl(lcdc_dev, WIN3_MST2));
3920         strcat(buf, dsp_buf);
3921         memset(dsp_buf, 0, sizeof(dsp_buf));
3922
3923         /*area 3*/
3924         size += snprintf(dsp_buf, 80,
3925                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3926                  w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
3927         strcat(buf, dsp_buf);
3928         memset(dsp_buf, 0, sizeof(dsp_buf));
3929         size += snprintf(dsp_buf, 80,
3930                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3931                  w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
3932                  lcdc_readl(lcdc_dev, WIN3_MST3));
3933         strcat(buf, dsp_buf);
3934         memset(dsp_buf, 0, sizeof(dsp_buf));
3935
3936         return size;
3937 }
3938
3939 static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3940                                bool set)
3941 {
3942         struct lcdc_device *lcdc_dev =
3943             container_of(dev_drv, struct lcdc_device, driver);
3944         struct rk_screen *screen = dev_drv->cur_screen;
3945         u64 ft = 0;
3946         u32 dotclk;
3947         int ret;
3948         u32 pixclock;
3949         u32 x_total, y_total;
3950
3951         if (set) {
3952                 if (fps == 0) {
3953                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
3954                         return 0;
3955                 }
3956                 ft = div_u64(1000000000000llu, fps);
3957                 x_total =
3958                     screen->mode.upper_margin + screen->mode.lower_margin +
3959                     screen->mode.yres + screen->mode.vsync_len;
3960                 y_total =
3961                     screen->mode.left_margin + screen->mode.right_margin +
3962                     screen->mode.xres + screen->mode.hsync_len;
3963                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3964                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3965                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3966         }
3967
3968         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3969         lcdc_dev->pixclock = pixclock;
3970         dev_drv->pixclock = lcdc_dev->pixclock;
3971         fps = rk_fb_calc_fps(screen, pixclock);
3972         screen->ft = 1000 / fps;        /*one frame time in ms */
3973
3974         if (set)
3975                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3976                          clk_get_rate(lcdc_dev->dclk), fps);
3977
3978         return fps;
3979 }
3980
3981 static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3982 {
3983         mutex_lock(&dev_drv->fb_win_id_mutex);
3984         if (order == FB_DEFAULT_ORDER)
3985                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
3986         dev_drv->fb4_win_id = order / 10000;
3987         dev_drv->fb3_win_id = (order / 1000) % 10;
3988         dev_drv->fb2_win_id = (order / 100) % 10;
3989         dev_drv->fb1_win_id = (order / 10) % 10;
3990         dev_drv->fb0_win_id = order % 10;
3991         mutex_unlock(&dev_drv->fb_win_id_mutex);
3992
3993         return 0;
3994 }
3995
3996 static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3997                                   const char *id)
3998 {
3999         int win_id = 0;
4000
4001         mutex_lock(&dev_drv->fb_win_id_mutex);
4002         if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
4003                 win_id = dev_drv->fb0_win_id;
4004         else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
4005                 win_id = dev_drv->fb1_win_id;
4006         else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
4007                 win_id = dev_drv->fb2_win_id;
4008         else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
4009                 win_id = dev_drv->fb3_win_id;
4010         else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
4011                 win_id = dev_drv->fb4_win_id;
4012         mutex_unlock(&dev_drv->fb_win_id_mutex);
4013
4014         return win_id;
4015 }
4016
4017 static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
4018 {
4019         struct lcdc_device *lcdc_dev =
4020             container_of(dev_drv, struct lcdc_device, driver);
4021         int i;
4022         unsigned int mask, val;
4023         struct rk_lcdc_win *win = NULL;
4024         u32 line_scane_num, dsp_vs_st_f1;
4025
4026         if (lcdc_dev->driver.cur_screen->mode.vmode == FB_VMODE_INTERLACED) {
4027                 dsp_vs_st_f1 = lcdc_readl(lcdc_dev, DSP_VS_ST_END_F1) >> 16;
4028                 for (i = 0; i < 1000; i++) {
4029                         line_scane_num =
4030                                 lcdc_readl(lcdc_dev, SCAN_LINE_NUM) & 0x1fff;
4031                         if (line_scane_num > dsp_vs_st_f1 + 1)
4032                                 udelay(50);
4033                         else
4034                                 break;
4035                 }
4036         }
4037
4038         spin_lock(&lcdc_dev->reg_lock);
4039         rk3368_lcdc_post_cfg(dev_drv);
4040         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
4041                      v_STANDBY_EN(lcdc_dev->standby));
4042         for (i = 0; i < 4; i++) {
4043                 win = dev_drv->win[i];
4044                 if ((win->state == 0) && (win->last_state == 1)) {
4045                         switch (win->id) {
4046                         case 0:
4047                                 /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
4048                                    for rk3288 to fix hw bug? */
4049                                 mask = m_WIN0_EN;
4050                                 val = v_WIN0_EN(0);
4051                                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
4052                                 break;
4053                         case 1:
4054                                 /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
4055                                    for rk3288 to fix hw bug? */
4056                                 mask = m_WIN1_EN;
4057                                 val = v_WIN1_EN(0);
4058                                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
4059                                 break;
4060                         case 2:
4061                                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
4062                                     m_WIN2_MST1_EN |
4063                                     m_WIN2_MST2_EN | m_WIN2_MST3_EN;
4064                                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
4065                                     v_WIN2_MST1_EN(0) |
4066                                     v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
4067                                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
4068                                 break;
4069                         case 3:
4070                                 mask = m_WIN3_EN | m_WIN3_MST0_EN |
4071                                     m_WIN3_MST1_EN |
4072                                     m_WIN3_MST2_EN | m_WIN3_MST3_EN;
4073                                 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |
4074                                     v_WIN3_MST1_EN(0) |
4075                                     v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
4076                                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
4077                                 break;
4078                         case 4:
4079                                 mask = m_HWC_EN;
4080                                 val = v_HWC_EN(0);
4081                                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
4082                                 break;
4083                         default:
4084                                 break;
4085                         }
4086                 }
4087                 win->last_state = win->state;
4088         }
4089         lcdc_cfg_done(lcdc_dev);
4090         spin_unlock(&lcdc_dev->reg_lock);
4091         return 0;
4092 }
4093
4094 static int rk3368_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
4095 {
4096         struct lcdc_device *lcdc_dev =
4097             container_of(dev_drv, struct lcdc_device, driver);
4098         spin_lock(&lcdc_dev->reg_lock);
4099         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
4100                      v_DIRECT_PATH_EN(open));
4101         lcdc_cfg_done(lcdc_dev);
4102         spin_unlock(&lcdc_dev->reg_lock);
4103         return 0;
4104 }
4105
4106 static int rk3368_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
4107 {
4108         struct lcdc_device *lcdc_dev = container_of(dev_drv,
4109                                                     struct lcdc_device, driver);
4110         spin_lock(&lcdc_dev->reg_lock);
4111         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
4112                      v_DIRECT_PATCH_SEL(win_id));
4113         lcdc_cfg_done(lcdc_dev);
4114         spin_unlock(&lcdc_dev->reg_lock);
4115         return 0;
4116 }
4117
4118 static int rk3368_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
4119 {
4120         struct lcdc_device *lcdc_dev =
4121             container_of(dev_drv, struct lcdc_device, driver);
4122         int ovl;
4123
4124         spin_lock(&lcdc_dev->reg_lock);
4125         ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
4126         spin_unlock(&lcdc_dev->reg_lock);
4127         return ovl;
4128 }
4129
4130 static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
4131                                       int enable)
4132 {
4133         struct lcdc_device *lcdc_dev =
4134             container_of(dev_drv, struct lcdc_device, driver);
4135         if (enable)
4136                 enable_irq(lcdc_dev->irq);
4137         else
4138                 disable_irq(lcdc_dev->irq);
4139         return 0;
4140 }
4141
4142 int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
4143 {
4144         struct lcdc_device *lcdc_dev =
4145             container_of(dev_drv, struct lcdc_device, driver);
4146         u32 int_reg;
4147         int ret;
4148
4149         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
4150                 int_reg = lcdc_readl(lcdc_dev, INTR_STATUS);
4151                 if (int_reg & m_LINE_FLAG0_INTR_STS) {
4152                         lcdc_dev->driver.frame_time.last_framedone_t =
4153                             lcdc_dev->driver.frame_time.framedone_t;
4154                         lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4155                         lcdc_msk_reg(lcdc_dev, INTR_CLEAR,
4156                                      m_LINE_FLAG0_INTR_CLR,
4157                                      v_LINE_FLAG0_INTR_CLR(1));
4158                         ret = RK_LF_STATUS_FC;
4159                 } else {
4160                         ret = RK_LF_STATUS_FR;
4161                 }
4162         } else {
4163                 ret = RK_LF_STATUS_NC;
4164         }
4165
4166         return ret;
4167 }
4168
4169 static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
4170                                     unsigned int dsp_addr[][4])
4171 {
4172         struct lcdc_device *lcdc_dev =
4173             container_of(dev_drv, struct lcdc_device, driver);
4174         spin_lock(&lcdc_dev->reg_lock);
4175         if (lcdc_dev->clk_on) {
4176                 dsp_addr[0][0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
4177                 dsp_addr[1][0] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
4178                 dsp_addr[2][0] = lcdc_readl(lcdc_dev, WIN2_MST0);
4179                 dsp_addr[2][1] = lcdc_readl(lcdc_dev, WIN2_MST1);
4180                 dsp_addr[2][2] = lcdc_readl(lcdc_dev, WIN2_MST2);
4181                 dsp_addr[2][3] = lcdc_readl(lcdc_dev, WIN2_MST3);
4182                 dsp_addr[3][0] = lcdc_readl(lcdc_dev, WIN3_MST0);
4183                 dsp_addr[3][1] = lcdc_readl(lcdc_dev, WIN3_MST1);
4184                 dsp_addr[3][2] = lcdc_readl(lcdc_dev, WIN3_MST2);
4185                 dsp_addr[3][3] = lcdc_readl(lcdc_dev, WIN3_MST3);
4186         }
4187         spin_unlock(&lcdc_dev->reg_lock);
4188         return 0;
4189 }
4190 static u32 pwm_period_hpr, pwm_duty_lpr;
4191 static u32 cabc_status = 0;
4192
4193 int rk3368_lcdc_update_pwm(int bl_pwm_period, int bl_pwm_duty)
4194 {
4195         pwm_period_hpr = bl_pwm_period;
4196         pwm_duty_lpr = bl_pwm_duty;
4197         /*pr_info("bl_pwm_period_hpr = 0x%x, bl_pwm_duty_lpr = 0x%x\n",
4198         bl_pwm_period, bl_pwm_duty);*/
4199         return 0;
4200 }
4201
4202 int rk3368_lcdc_cabc_status(void)
4203 {
4204         return cabc_status;
4205 }
4206
4207 static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv,
4208                                     int mode, int calc, int up,
4209                                     int down, int global)
4210 {
4211         struct lcdc_device *lcdc_dev =
4212             container_of(dev_drv, struct lcdc_device, driver);
4213         struct rk_screen *screen = dev_drv->cur_screen;
4214         u32 total_pixel, calc_pixel, stage_up, stage_down;
4215         u32 pixel_num, global_su;
4216         u32 stage_up_rec, stage_down_rec, global_su_rec, gamma_global_su_rec;
4217         u32 mask = 0, val = 0, cabc_en = 0;
4218         int *cabc_lut = NULL;
4219
4220         if (!screen->cabc_lut) {
4221                 pr_err("screen cabc lut not config, so not open cabc\n");
4222                 return 0;
4223         } else {
4224                 cabc_lut = screen->cabc_lut;
4225         }
4226
4227         if (!screen->cabc_gamma_base) {
4228                 pr_err("screen cabc_gamma_base no config, so not open cabc\n");
4229                 return 0;
4230         }
4231         dev_drv->cabc_mode = mode;
4232         cabc_en = (mode > 0) ? 1 : 0;
4233         rk3368_lcdc_get_backlight_device(dev_drv);
4234         if (cabc_en == 0) {
4235                 spin_lock(&lcdc_dev->reg_lock);
4236                 if (lcdc_dev->clk_on) {
4237                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
4238                                      m_CABC_EN, v_CABC_EN(0));
4239                         lcdc_cfg_done(lcdc_dev);
4240                 }
4241                 pr_info("mode = 0, close cabc\n");
4242                 rk_pwm_set(pwm_period_hpr, pwm_duty_lpr);
4243                 cabc_status = 0;
4244                 spin_unlock(&lcdc_dev->reg_lock);
4245                 return 0;
4246         }
4247         if (cabc_status == 0) { /*get from pwm*/
4248                 rk_pwm_get(&pwm_period_hpr, &pwm_duty_lpr);
4249                 pr_info("pwm_period_hpr=0x%x, pwm_duty_lpr=0x%x\n",
4250                         pwm_period_hpr, pwm_duty_lpr);
4251         }
4252
4253         total_pixel = screen->mode.xres * screen->mode.yres;
4254         pixel_num = 1000 - calc;
4255         calc_pixel = (total_pixel * pixel_num) / 1000;
4256         stage_up = up;
4257         stage_down = down;
4258         global_su = global;
4259         pr_info("enable cabc:mode=%d, calc=%d, up=%d, down=%d, global=%d\n",
4260                 mode, calc, stage_up, stage_down, global_su);
4261
4262         stage_up_rec = 256 * 256 / stage_up;
4263         stage_down_rec = 256 * 256 / stage_down;
4264         global_su_rec = (256 * 256 / global_su);
4265         gamma_global_su_rec = cabc_lut[global_su_rec];
4266
4267         spin_lock(&lcdc_dev->reg_lock);
4268         if (lcdc_dev->clk_on) {
4269                 mask = m_CABC_CALC_PIXEL_NUM | m_CABC_EN;
4270                 val = v_CABC_CALC_PIXEL_NUM(calc_pixel) |
4271                         v_CABC_EN(cabc_en);
4272                 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
4273
4274                 mask = m_CABC_TOTAL_PIXEL_NUM | m_CABC_LUT_EN;
4275                 val = v_CABC_TOTAL_PIXEL_NUM(total_pixel) | v_CABC_LUT_EN(1);
4276                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
4277
4278                 mask = m_CABC_STAGE_UP | m_CABC_STAGE_UP_REC |
4279                     m_CABC_GLOBAL_SU_LIMIT_EN | m_CABC_GLOBAL_SU_REC;
4280                 val = v_CABC_STAGE_UP(stage_up) |
4281                     v_CABC_STAGE_UP_REC(stage_up_rec) |
4282                     v_CABC_GLOBAL_SU_LIMIT_EN(1) |
4283                     v_CABC_GLOBAL_SU_REC(gamma_global_su_rec);
4284                 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
4285
4286                 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_DOWN_REC |
4287                     m_CABC_GLOBAL_SU;
4288                 val = v_CABC_STAGE_DOWN(stage_down) |
4289                     v_CABC_STAGE_DOWN_REC(stage_down_rec) |
4290                     v_CABC_GLOBAL_SU(global_su);
4291                 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
4292                 lcdc_cfg_done(lcdc_dev);
4293         }
4294         cabc_status = 1;
4295         spin_unlock(&lcdc_dev->reg_lock);
4296
4297         return 0;
4298 }
4299
4300 /*
4301         a:[-30~0]:
4302             sin_hue = sin(a)*256 +0x100;
4303             cos_hue = cos(a)*256;
4304         a:[0~30]
4305             sin_hue = sin(a)*256;
4306             cos_hue = cos(a)*256;
4307 */
4308 static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
4309                                     bcsh_hue_mode mode)
4310 {
4311         struct lcdc_device *lcdc_dev =
4312             container_of(dev_drv, struct lcdc_device, driver);
4313         u32 val;
4314
4315         spin_lock(&lcdc_dev->reg_lock);
4316         if (lcdc_dev->clk_on) {
4317                 val = lcdc_readl(lcdc_dev, BCSH_H);
4318                 switch (mode) {
4319                 case H_SIN:
4320                         val &= m_BCSH_SIN_HUE;
4321                         break;
4322                 case H_COS:
4323                         val &= m_BCSH_COS_HUE;
4324                         val >>= 16;
4325                         break;
4326                 default:
4327                         break;
4328                 }
4329         }
4330         spin_unlock(&lcdc_dev->reg_lock);
4331
4332         return val;
4333 }
4334
4335 static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
4336                                     int sin_hue, int cos_hue)
4337 {
4338         struct lcdc_device *lcdc_dev =
4339             container_of(dev_drv, struct lcdc_device, driver);
4340         u32 mask, val;
4341
4342         spin_lock(&lcdc_dev->reg_lock);
4343         if (lcdc_dev->clk_on) {
4344                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
4345                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
4346                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
4347                 lcdc_cfg_done(lcdc_dev);
4348         }
4349         spin_unlock(&lcdc_dev->reg_lock);
4350
4351         return 0;
4352 }
4353
4354 static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4355                                     bcsh_bcs_mode mode, int value)
4356 {
4357         struct lcdc_device *lcdc_dev =
4358             container_of(dev_drv, struct lcdc_device, driver);
4359         u32 mask, val;
4360
4361         spin_lock(&lcdc_dev->reg_lock);
4362         if (lcdc_dev->clk_on) {
4363                 switch (mode) {
4364                 case BRIGHTNESS:
4365                         /*from 0 to 255,typical is 128 */
4366                         if (value < 0x80)
4367                                 value += 0x80;
4368                         else if (value >= 0x80)
4369                                 value = value - 0x80;
4370                         mask = m_BCSH_BRIGHTNESS;
4371                         val = v_BCSH_BRIGHTNESS(value);
4372                         break;
4373                 case CONTRAST:
4374                         /*from 0 to 510,typical is 256 */
4375                         mask = m_BCSH_CONTRAST;
4376                         val = v_BCSH_CONTRAST(value);
4377                         break;
4378                 case SAT_CON:
4379                         /*from 0 to 1015,typical is 256 */
4380                         mask = m_BCSH_SAT_CON;
4381                         val = v_BCSH_SAT_CON(value);
4382                         break;
4383                 default:
4384                         break;
4385                 }
4386                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
4387                 lcdc_cfg_done(lcdc_dev);
4388         }
4389         spin_unlock(&lcdc_dev->reg_lock);
4390         return val;
4391 }
4392
4393 static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4394                                     bcsh_bcs_mode mode)
4395 {
4396         struct lcdc_device *lcdc_dev =
4397             container_of(dev_drv, struct lcdc_device, driver);
4398         u32 val;
4399
4400         spin_lock(&lcdc_dev->reg_lock);
4401         if (lcdc_dev->clk_on) {
4402                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
4403                 switch (mode) {
4404                 case BRIGHTNESS:
4405                         val &= m_BCSH_BRIGHTNESS;
4406                         if (val > 0x80)
4407                                 val -= 0x80;
4408                         else
4409                                 val += 0x80;
4410                         break;
4411                 case CONTRAST:
4412                         val &= m_BCSH_CONTRAST;
4413                         val >>= 8;
4414                         break;
4415                 case SAT_CON:
4416                         val &= m_BCSH_SAT_CON;
4417                         val >>= 20;
4418                         break;
4419                 default:
4420                         break;
4421                 }
4422         }
4423         spin_unlock(&lcdc_dev->reg_lock);
4424         return val;
4425 }
4426
4427 static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
4428 {
4429         struct lcdc_device *lcdc_dev =
4430             container_of(dev_drv, struct lcdc_device, driver);
4431         u32 mask, val;
4432
4433         spin_lock(&lcdc_dev->reg_lock);
4434         if (lcdc_dev->clk_on) {
4435                 if (open) {
4436                         lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1);
4437                         lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
4438                         lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
4439                         dev_drv->bcsh.enable = 1;
4440                 } else {
4441                         mask = m_BCSH_EN;
4442                         val = v_BCSH_EN(0);
4443                         lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
4444                         dev_drv->bcsh.enable = 0;
4445                 }
4446                 rk3368_lcdc_bcsh_path_sel(dev_drv);
4447                 lcdc_cfg_done(lcdc_dev);
4448         }
4449         spin_unlock(&lcdc_dev->reg_lock);
4450         return 0;
4451 }
4452
4453 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4454 {
4455         if (!enable || !dev_drv->bcsh.enable) {
4456                 rk3368_lcdc_open_bcsh(dev_drv, false);
4457                 return 0;
4458         }
4459
4460         if (dev_drv->bcsh.brightness <= 255 ||
4461             dev_drv->bcsh.contrast <= 510 ||
4462             dev_drv->bcsh.sat_con <= 1015 ||
4463             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4464                 rk3368_lcdc_open_bcsh(dev_drv, true);
4465                 if (dev_drv->bcsh.brightness <= 255)
4466                         rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4467                                                  dev_drv->bcsh.brightness);
4468                 if (dev_drv->bcsh.contrast <= 510)
4469                         rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
4470                                                  dev_drv->bcsh.contrast);
4471                 if (dev_drv->bcsh.sat_con <= 1015)
4472                         rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
4473                                                  dev_drv->bcsh.sat_con);
4474                 if (dev_drv->bcsh.sin_hue <= 511 &&
4475                     dev_drv->bcsh.cos_hue <= 511)
4476                         rk3368_lcdc_set_bcsh_hue(dev_drv,
4477                                                  dev_drv->bcsh.sin_hue,
4478                                                  dev_drv->bcsh.cos_hue);
4479         }
4480         return 0;
4481 }
4482
4483 static int __maybe_unused
4484 rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4485 {
4486         struct lcdc_device *lcdc_dev =
4487             container_of(dev_drv, struct lcdc_device, driver);
4488
4489         if (enable) {
4490                 spin_lock(&lcdc_dev->reg_lock);
4491                 if (likely(lcdc_dev->clk_on)) {
4492                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4493                                      v_DSP_BLACK_EN(1));
4494                         lcdc_cfg_done(lcdc_dev);
4495                 }
4496                 spin_unlock(&lcdc_dev->reg_lock);
4497         } else {
4498                 spin_lock(&lcdc_dev->reg_lock);
4499                 if (likely(lcdc_dev->clk_on)) {
4500                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4501                                      v_DSP_BLACK_EN(0));
4502
4503                         lcdc_cfg_done(lcdc_dev);
4504                 }
4505                 spin_unlock(&lcdc_dev->reg_lock);
4506         }
4507
4508         return 0;
4509 }
4510
4511
4512 static int rk3368_lcdc_wait_frame_start(struct rk_lcdc_driver *dev_drv,
4513                                          int enable)
4514 {
4515         u32 line_scane_num, vsync_end, vact_end;
4516         u32 interlace_mode;
4517
4518         struct lcdc_device *lcdc_dev =
4519             container_of(dev_drv, struct lcdc_device, driver);
4520
4521         if (unlikely(!lcdc_dev->clk_on)) {
4522                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
4523                 return 0;
4524         }
4525         if (0 == enable) {
4526                 interlace_mode = lcdc_read_bit(lcdc_dev, DSP_CTRL0,
4527                                                m_DSP_INTERLACE);
4528                 if (interlace_mode) {
4529                         vsync_end = lcdc_readl(lcdc_dev, DSP_VS_ST_END_F1) &
4530                                         m_DSP_VS_END_F1;
4531                         vact_end = lcdc_readl(lcdc_dev, DSP_VACT_ST_END_F1) &
4532                                         m_DSP_VACT_END_F1;
4533                 } else {
4534                         vsync_end = lcdc_readl(lcdc_dev, DSP_VTOTAL_VS_END) &
4535                                         m_DSP_VS_PW;
4536                         vact_end = lcdc_readl(lcdc_dev, DSP_VACT_ST_END) &
4537                                         m_DSP_VACT_END;
4538                 }
4539                 while (1) {
4540                         line_scane_num = lcdc_readl(lcdc_dev, SCAN_LINE_NUM) &
4541                                         0x1fff;
4542                         if ((line_scane_num > vsync_end) &&
4543                             (line_scane_num <= vact_end - 100))
4544                                 break;
4545                 }
4546                 return 0;
4547         } else if (1 == enable) {
4548                 line_scane_num = lcdc_readl(lcdc_dev, SCAN_LINE_NUM) & 0x1fff;
4549                 return line_scane_num;
4550         }
4551
4552         return 0;
4553 }
4554
4555 static int rk3368_lcdc_backlight_close(struct rk_lcdc_driver *dev_drv,
4556                                        int enable)
4557 {
4558         struct lcdc_device *lcdc_dev =
4559             container_of(dev_drv, struct lcdc_device, driver);
4560
4561         if (unlikely(!lcdc_dev->clk_on)) {
4562                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
4563                 return 0;
4564         }
4565         rk3368_lcdc_get_backlight_device(dev_drv);
4566
4567         if (enable) {
4568                 /* close the backlight */
4569                 if (lcdc_dev->backlight) {
4570                         lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4571                         backlight_update_status(lcdc_dev->backlight);
4572                 }
4573                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4574                         dev_drv->trsm_ops->disable();
4575         } else {
4576                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4577                         dev_drv->trsm_ops->enable();
4578                 msleep(100);
4579                 /* open the backlight */
4580                 if (lcdc_dev->backlight) {
4581                         lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
4582                         backlight_update_status(lcdc_dev->backlight);
4583                 }
4584         }
4585
4586         return 0;
4587 }
4588
4589 static int rk3368_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv,
4590                                     struct overscan *overscan)
4591 {
4592         struct lcdc_device *lcdc_dev =
4593             container_of(dev_drv, struct lcdc_device, driver);
4594
4595         if (unlikely(!lcdc_dev->clk_on)) {
4596                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
4597                 return 0;
4598         }
4599         /*rk3368_lcdc_post_cfg(dev_drv);*/
4600
4601         return 0;
4602 }
4603
4604 static int rk3368_lcdc_extern_func(struct rk_lcdc_driver *dev_drv,
4605                                         int cmd)
4606 {
4607         struct lcdc_device *lcdc_dev =
4608             container_of(dev_drv, struct lcdc_device, driver);
4609         u32 val;
4610
4611         if (unlikely(!lcdc_dev->clk_on)) {
4612                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
4613                 return 0;
4614         }
4615
4616         switch (cmd) {
4617         case GET_PAGE_FAULT:
4618                 val = lcdc_readl(lcdc_dev, MMU_INT_RAWSTAT);
4619                 if ((val & 0x1) == 1) {
4620                         if ((val & 0x2) == 1)
4621                                 pr_info("val = 0x%x, vop iommu bus error\n", val);
4622                         else
4623                                 return 1;
4624                 }
4625                 break;
4626         case CLR_PAGE_FAULT:
4627                 lcdc_writel(lcdc_dev, MMU_INT_CLEAR, 0x3);
4628                 break;
4629         case UNMASK_PAGE_FAULT:
4630                 lcdc_writel(lcdc_dev, MMU_INT_MASK, 0x2);
4631                 break;
4632         default:
4633                 break;
4634         }
4635
4636         return 0;
4637 }
4638
4639 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4640         .open = rk3368_lcdc_open,
4641         .win_direct_en = rk3368_lcdc_win_direct_en,
4642         .load_screen = rk3368_load_screen,
4643         .get_dspbuf_info = rk3368_get_dspbuf_info,
4644         .post_dspbuf = rk3368_post_dspbuf,
4645         .set_par = rk3368_lcdc_set_par,
4646         .pan_display = rk3368_lcdc_pan_display,
4647         .direct_set_addr = rk3368_lcdc_direct_set_win_addr,
4648         /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/
4649         .blank = rk3368_lcdc_blank,
4650         .ioctl = rk3368_lcdc_ioctl,
4651         .suspend = rk3368_lcdc_early_suspend,
4652         .resume = rk3368_lcdc_early_resume,
4653         .get_win_state = rk3368_lcdc_get_win_state,
4654         .area_support_num = rk3368_lcdc_get_area_num,
4655         .ovl_mgr = rk3368_lcdc_ovl_mgr,
4656         .get_disp_info = rk3368_lcdc_get_disp_info,
4657         .fps_mgr = rk3368_lcdc_fps_mgr,
4658         .fb_get_win_id = rk3368_lcdc_get_win_id,
4659         .fb_win_remap = rk3368_fb_win_remap,
4660         .set_dsp_lut = rk3368_lcdc_set_lut,
4661         .set_cabc_lut = rk3368_set_cabc_lut,
4662         .poll_vblank = rk3368_lcdc_poll_vblank,
4663         .dpi_open = rk3368_lcdc_dpi_open,
4664         .dpi_win_sel = rk3368_lcdc_dpi_win_sel,
4665         .dpi_status = rk3368_lcdc_dpi_status,
4666         .get_dsp_addr = rk3368_lcdc_get_dsp_addr,
4667         .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc,
4668         .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue,
4669         .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs,
4670         .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue,
4671         .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs,
4672         .open_bcsh = rk3368_lcdc_open_bcsh,
4673         .dump_reg = rk3368_lcdc_reg_dump,
4674         .cfg_done = rk3368_lcdc_config_done,
4675         .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu,
4676         /*.dsp_black = rk3368_lcdc_dsp_black,*/
4677         .backlight_close = rk3368_lcdc_backlight_close,
4678         .mmu_en    = rk3368_lcdc_mmu_en,
4679         .set_overscan   = rk3368_lcdc_set_overscan,
4680         .extern_func    = rk3368_lcdc_extern_func,
4681         .wait_frame_start = rk3368_lcdc_wait_frame_start,
4682 };
4683
4684 #ifdef LCDC_IRQ_EMPTY_DEBUG
4685 static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev,
4686                                  unsigned int intr_status)
4687 {
4688         if (intr_status & m_WIN0_EMPTY_INTR_STS) {
4689                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN0_EMPTY_INTR_CLR,
4690                              v_WIN0_EMPTY_INTR_CLR(1));
4691                 dev_warn(lcdc_dev->dev, "win0 empty irq!");
4692         } else if (intr_status & m_WIN1_EMPTY_INTR_STS) {
4693                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN1_EMPTY_INTR_CLR,
4694                              v_WIN1_EMPTY_INTR_CLR(1));
4695                 dev_warn(lcdc_dev->dev, "win1 empty irq!");
4696         } else if (intr_status & m_WIN2_EMPTY_INTR_STS) {
4697                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN2_EMPTY_INTR_CLR,
4698                              v_WIN2_EMPTY_INTR_CLR(1));
4699                 dev_warn(lcdc_dev->dev, "win2 empty irq!");
4700         } else if (intr_status & m_WIN3_EMPTY_INTR_STS) {
4701                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN3_EMPTY_INTR_CLR,
4702                              v_WIN3_EMPTY_INTR_CLR(1));
4703                 dev_warn(lcdc_dev->dev, "win3 empty irq!");
4704         } else if (intr_status & m_HWC_EMPTY_INTR_STS) {
4705                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_HWC_EMPTY_INTR_CLR,
4706                              v_HWC_EMPTY_INTR_CLR(1));
4707                 dev_warn(lcdc_dev->dev, "HWC empty irq!");
4708         } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) {
4709                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_POST_BUF_EMPTY_INTR_CLR,
4710                              v_POST_BUF_EMPTY_INTR_CLR(1));
4711                 dev_warn(lcdc_dev->dev, "post buf empty irq!");
4712         } else if (intr_status & m_PWM_GEN_INTR_STS) {
4713                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_PWM_GEN_INTR_CLR,
4714                              v_PWM_GEN_INTR_CLR(1));
4715                 dev_warn(lcdc_dev->dev, "PWM gen irq!");
4716         }
4717         return 0;
4718 }
4719 #endif
4720
4721 static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id)
4722 {
4723         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
4724         ktime_t timestamp = ktime_get();
4725         u32 intr_status;
4726         u32 scale_global_limit, scale_global_limit_reg;
4727         u32 cabc_pwm_lut_value;
4728         int pwm_plus;
4729         int *cabc_gamma_base = NULL;
4730         u32 line_scane_num, dsp_vs_st_f1;
4731         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
4732
4733         intr_status = lcdc_readl(lcdc_dev, INTR_STATUS);
4734
4735         if (intr_status & m_FS_INTR_STS) {
4736                 timestamp = ktime_get();
4737                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_INTR_CLR,
4738                              v_FS_INTR_CLR(1));
4739                 line_scane_num = lcdc_readl(lcdc_dev, SCAN_LINE_NUM) & 0x1fff;
4740                 dsp_vs_st_f1 = lcdc_readl(lcdc_dev, DSP_VS_ST_END_F1) >> 16;
4741                 /*if(lcdc_dev->driver.wait_fs){ */
4742                 if (0) {
4743                         spin_lock(&(lcdc_dev->driver.cpl_lock));
4744                         complete(&(lcdc_dev->driver.frame_done));
4745                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
4746                 }
4747 #ifdef CONFIG_DRM_ROCKCHIP
4748                 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
4749 #endif
4750                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4751                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
4752                 if ((screen->mode.vmode == FB_VMODE_NONINTERLACED) ||
4753                     (line_scane_num >= dsp_vs_st_f1)) {
4754                         lcdc_dev->driver.vsync_info.timestamp = timestamp;
4755                         wake_up_interruptible_all(
4756                                 &lcdc_dev->driver.vsync_info.wait);
4757                 }
4758         } else if (intr_status & m_LINE_FLAG0_INTR_STS) {
4759                 lcdc_dev->driver.frame_time.last_framedone_t =
4760                         lcdc_dev->driver.frame_time.framedone_t;
4761                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4762                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG0_INTR_CLR,
4763                              v_LINE_FLAG0_INTR_CLR(1));
4764
4765                 if (cabc_status == 1) {
4766                         cabc_gamma_base =
4767                                 lcdc_dev->driver.cur_screen->cabc_gamma_base;
4768                         scale_global_limit  = lcdc_readl(lcdc_dev, CABC_DEBUG2);
4769                         scale_global_limit_reg = scale_global_limit;
4770                         scale_global_limit >>= 16;
4771                         scale_global_limit &= 0xff;
4772
4773                         if (lcdc_dev->driver.cabc_pwm_pol == 1) {/*negative*/
4774                                 pwm_plus = pwm_period_hpr - pwm_duty_lpr;
4775                                 cabc_pwm_lut_value =
4776                                         pwm_period_hpr -
4777                                         ((cabc_gamma_base[scale_global_limit] * pwm_plus) >> 16);
4778                         } else {/*positive*/
4779                                 pwm_plus = pwm_duty_lpr;
4780                                 cabc_pwm_lut_value =
4781                                         cabc_gamma_base[scale_global_limit] *
4782                                         pwm_plus >> 16;
4783                         }
4784                         rk_pwm_set(pwm_period_hpr, cabc_pwm_lut_value);
4785                 }
4786         } else if (intr_status & m_LINE_FLAG1_INTR_STS) {
4787                 /*line flag1 */
4788                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG1_INTR_CLR,
4789                              v_LINE_FLAG1_INTR_CLR(1));
4790         } else if (intr_status & m_FS_NEW_INTR_STS) {
4791                 /*new frame start */
4792                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_NEW_INTR_CLR,
4793                              v_FS_NEW_INTR_CLR(1));
4794         } else if (intr_status & m_BUS_ERROR_INTR_STS) {
4795                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_BUS_ERROR_INTR_CLR,
4796                              v_BUS_ERROR_INTR_CLR(1));
4797                 dev_warn(lcdc_dev->dev, "bus error!");
4798         }
4799
4800         /* for win empty debug */
4801 #ifdef LCDC_IRQ_EMPTY_DEBUG
4802         rk3368_lcdc_parse_irq(lcdc_dev, intr_status);
4803 #endif
4804         return IRQ_HANDLED;
4805 }
4806
4807 #if defined(CONFIG_PM)
4808 static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
4809 {
4810         return 0;
4811 }
4812
4813 static int rk3368_lcdc_resume(struct platform_device *pdev)
4814 {
4815         return 0;
4816 }
4817 #else
4818 #define rk3368_lcdc_suspend NULL
4819 #define rk3368_lcdc_resume  NULL
4820 #endif
4821
4822 static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4823 {
4824         struct device_node *np = lcdc_dev->dev->of_node;
4825         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4826         int val;
4827
4828         if (of_property_read_u32(np, "rockchip,prop", &val))
4829                 lcdc_dev->prop = PRMRY; /*default set it as primary */
4830         else
4831                 lcdc_dev->prop = val;
4832
4833         if (of_property_read_u32(np, "rockchip,mirror", &val))
4834                 dev_drv->rotate_mode = NO_MIRROR;
4835         else
4836                 dev_drv->rotate_mode = val;
4837
4838         if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4839                 dev_drv->cabc_mode = 0; /* default set close cabc */
4840         else
4841                 dev_drv->cabc_mode = val;
4842
4843         if (of_property_read_u32(np, "rockchip,pwr18", &val))
4844                 /*default set it as 3.xv power supply */
4845                 lcdc_dev->pwr18 = false;
4846         else
4847                 lcdc_dev->pwr18 = (val ? true : false);
4848
4849         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4850                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4851         else
4852                 dev_drv->fb_win_map = val;
4853
4854         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4855                 dev_drv->bcsh.enable = false;
4856         else
4857                 dev_drv->bcsh.enable = (val ? true : false);
4858
4859         if (of_property_read_u32(np, "rockchip,brightness", &val))
4860                 dev_drv->bcsh.brightness = 0xffff;
4861         else
4862                 dev_drv->bcsh.brightness = val;
4863
4864         if (of_property_read_u32(np, "rockchip,contrast", &val))
4865                 dev_drv->bcsh.contrast = 0xffff;
4866         else
4867                 dev_drv->bcsh.contrast = val;
4868
4869         if (of_property_read_u32(np, "rockchip,sat-con", &val))
4870                 dev_drv->bcsh.sat_con = 0xffff;
4871         else
4872                 dev_drv->bcsh.sat_con = val;
4873
4874         if (of_property_read_u32(np, "rockchip,hue", &val)) {
4875                 dev_drv->bcsh.sin_hue = 0xffff;
4876                 dev_drv->bcsh.cos_hue = 0xffff;
4877         } else {
4878                 dev_drv->bcsh.sin_hue = val & 0xff;
4879                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4880         }
4881
4882 #if defined(CONFIG_ROCKCHIP_IOMMU)
4883         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4884                 dev_drv->iommu_enabled = 0;
4885         else
4886                 dev_drv->iommu_enabled = val;
4887 #else
4888         dev_drv->iommu_enabled = 0;
4889 #endif
4890         return 0;
4891 }
4892
4893 static int rk3368_lcdc_probe(struct platform_device *pdev)
4894 {
4895         struct lcdc_device *lcdc_dev = NULL;
4896         struct rk_lcdc_driver *dev_drv;
4897         struct device *dev = &pdev->dev;
4898         struct resource *res;
4899         struct device_node *np = pdev->dev.of_node;
4900         int prop;
4901         int ret = 0;
4902
4903         /*if the primary lcdc has not registered ,the extend
4904            lcdc register later */
4905         of_property_read_u32(np, "rockchip,prop", &prop);
4906         if (prop == EXTEND) {
4907                 if (!is_prmry_rk_lcdc_registered())
4908                         return -EPROBE_DEFER;
4909         }
4910         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
4911         if (!lcdc_dev) {
4912                 dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!");
4913                 return -ENOMEM;
4914         }
4915         platform_set_drvdata(pdev, lcdc_dev);
4916         lcdc_dev->dev = dev;
4917         rk3368_lcdc_parse_dt(lcdc_dev);
4918         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4919         lcdc_dev->reg_phy_base = res->start;
4920         lcdc_dev->len = resource_size(res);
4921         lcdc_dev->regs = devm_ioremap_resource(dev, res);
4922         if (IS_ERR(lcdc_dev->regs))
4923                 return PTR_ERR(lcdc_dev->regs);
4924         else
4925                 dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs);
4926
4927         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4928         if (IS_ERR(lcdc_dev->regsbak))
4929                 return PTR_ERR(lcdc_dev->regsbak);
4930         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4931         lcdc_dev->cabc_lut_addr_base = (lcdc_dev->regs + CABC_GAMMA_LUT_ADDR);
4932         lcdc_dev->grf_base =
4933                 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
4934         if (IS_ERR(lcdc_dev->grf_base)) {
4935                 dev_err(&pdev->dev, "can't find lcdc grf property\n");
4936                 return PTR_ERR(lcdc_dev->grf_base);
4937         }
4938         lcdc_dev->pmugrf_base =
4939                 syscon_regmap_lookup_by_phandle(np, "rockchip,pmugrf");
4940         if (IS_ERR(lcdc_dev->pmugrf_base)) {
4941                 dev_err(&pdev->dev, "can't find lcdc pmu grf property\n");
4942                 return PTR_ERR(lcdc_dev->pmugrf_base);
4943         }
4944
4945         lcdc_dev->cru_base =
4946                 syscon_regmap_lookup_by_phandle(np, "rockchip,cru");
4947         if (IS_ERR(lcdc_dev->cru_base)) {
4948                 dev_err(&pdev->dev, "can't find lcdc cru_base property\n");
4949                 return PTR_ERR(lcdc_dev->cru_base);
4950         }
4951
4952         lcdc_dev->id = 0;
4953         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4954         dev_drv = &lcdc_dev->driver;
4955         dev_drv->dev = dev;
4956         dev_drv->prop = prop;
4957         dev_drv->id = lcdc_dev->id;
4958         dev_drv->ops = &lcdc_drv_ops;
4959         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4960         dev_drv->reserved_fb = 1;/*only need reserved 1 buffer*/
4961         spin_lock_init(&lcdc_dev->reg_lock);
4962
4963         lcdc_dev->irq = platform_get_irq(pdev, 0);
4964         if (lcdc_dev->irq < 0) {
4965                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4966                         lcdc_dev->id);
4967                 return -ENXIO;
4968         }
4969
4970         ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr,
4971                                IRQF_DISABLED | IRQF_SHARED,
4972                                dev_name(dev), lcdc_dev);
4973         if (ret) {
4974                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4975                         lcdc_dev->irq, ret);
4976                 return ret;
4977         }
4978
4979         if (dev_drv->iommu_enabled) {
4980                 if (lcdc_dev->id == 0) {
4981                         strcpy(dev_drv->mmu_dts_name,
4982                                VOPB_IOMMU_COMPATIBLE_NAME);
4983                 } else {
4984                         strcpy(dev_drv->mmu_dts_name,
4985                                VOPL_IOMMU_COMPATIBLE_NAME);
4986                 }
4987         }
4988
4989         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4990         if (ret < 0) {
4991                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4992                 return ret;
4993         }
4994         lcdc_dev->screen = dev_drv->screen0;
4995         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4996                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4997
4998         return 0;
4999 }
5000
5001 static int rk3368_lcdc_remove(struct platform_device *pdev)
5002 {
5003         return 0;
5004 }
5005
5006 static void rk3368_lcdc_shutdown(struct platform_device *pdev)
5007 {
5008         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
5009         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
5010 #if 1
5011         dev_drv->suspend_flag = 1;
5012         mdelay(100);
5013         flush_kthread_worker(&dev_drv->update_regs_worker);
5014         kthread_stop(dev_drv->update_regs_thread);
5015         rk3368_lcdc_deint(lcdc_dev);
5016         /*if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
5017                 dev_drv->trsm_ops->disable();*/
5018
5019         rk3368_lcdc_clk_disable(lcdc_dev);
5020         rk_disp_pwr_disable(dev_drv);
5021 #else
5022         rk3368_lcdc_early_suspend(&lcdc_dev->driver);
5023         rk3368_lcdc_deint(lcdc_dev);
5024 #endif
5025
5026 }
5027
5028 #if defined(CONFIG_OF)
5029 static const struct of_device_id rk3368_lcdc_dt_ids[] = {
5030         {.compatible = "rockchip,rk3368-lcdc",},
5031         {}
5032 };
5033 #endif
5034
5035 static struct platform_driver rk3368_lcdc_driver = {
5036         .probe = rk3368_lcdc_probe,
5037         .remove = rk3368_lcdc_remove,
5038         .driver = {
5039                    .name = "rk3368-lcdc",
5040                    .owner = THIS_MODULE,
5041                    .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids),
5042                    },
5043         .suspend = rk3368_lcdc_suspend,
5044         .resume = rk3368_lcdc_resume,
5045         .shutdown = rk3368_lcdc_shutdown,
5046 };
5047
5048 static int __init rk3368_lcdc_module_init(void)
5049 {
5050         return platform_driver_register(&rk3368_lcdc_driver);
5051 }
5052
5053 static void __exit rk3368_lcdc_module_exit(void)
5054 {
5055         platform_driver_unregister(&rk3368_lcdc_driver);
5056 }
5057
5058 fs_initcall(rk3368_lcdc_module_init);
5059 module_exit(rk3368_lcdc_module_exit);