2 * drivers/video/rockchip/lcdc/rk3368_lcdc.c
4 * Copyright (C) 2014 ROCKCHIP, Inc.
5 *Author:hjc<hjc@rock-chips.com>
6 *This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/string.h>
22 #include <linux/slab.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/rockchip-iovmm.h>
30 #include <asm/div64.h>
31 #include <linux/uaccess.h>
32 #include <linux/rockchip/cpu.h>
33 #include <linux/rockchip/iomap.h>
34 #include <linux/rockchip/grf.h>
35 #include <linux/rockchip/common.h>
36 #include <dt-bindings/clock/rk_system_status.h>
38 #include "rk3368_lcdc.h"
40 #if defined(CONFIG_HAS_EARLYSUSPEND)
41 #include <linux/earlysuspend.h>
43 /*#define CONFIG_RK_FPGA 1*/
45 static int dbg_thresd;
46 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
48 #define DBG(level, x...) do { \
49 if (unlikely(dbg_thresd >= level)) \
53 #define EARLY_TIME 500 /*us*/
54 static struct rk_lcdc_win lcdc_win[] = {
58 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_SCALE |
60 .property.max_input_x = 4096,
61 .property.max_input_y = 2304
66 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_SCALE |
68 .property.max_input_x = 4096,
69 .property.max_input_y = 2304
74 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_MULTI_AREA,
75 .property.max_input_x = 4096,
76 .property.max_input_y = 2304
81 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_MULTI_AREA,
82 .property.max_input_x = 4096,
83 .property.max_input_y = 2304
88 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HWC_LAYER,
89 .property.max_input_x = 128,
90 .property.max_input_y = 128
94 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
96 /*#define WAIT_FOR_SYNC 1*/
97 u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth)
101 if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
103 else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
112 static int rk3368_set_cabc_lut(struct rk_lcdc_driver *dev_drv, int *cabc_lut)
117 struct lcdc_device *lcdc_dev =
118 container_of(dev_drv, struct lcdc_device, driver);
120 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
122 lcdc_cfg_done(lcdc_dev);
124 for (i = 0; i < 128; i++) {
126 c = lcdc_dev->cabc_lut_addr_base + i;
127 writel_relaxed(v, c);
129 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
135 static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
140 struct lcdc_device *lcdc_dev =
141 container_of(dev_drv, struct lcdc_device, driver);
143 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
145 lcdc_cfg_done(lcdc_dev);
147 for (i = 0; i < 256; i++) {
149 c = lcdc_dev->dsp_lut_addr_base + i;
150 writel_relaxed(v, c);
152 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
158 static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
160 #ifdef CONFIG_RK_FPGA
161 lcdc_dev->clk_on = 1;
164 if (!lcdc_dev->clk_on) {
165 clk_prepare_enable(lcdc_dev->hclk);
166 clk_prepare_enable(lcdc_dev->dclk);
167 clk_prepare_enable(lcdc_dev->aclk);
169 clk_prepare_enable(lcdc_dev->pd);
170 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
171 pm_runtime_get_sync(lcdc_dev->dev);
173 spin_lock(&lcdc_dev->reg_lock);
174 lcdc_dev->clk_on = 1;
175 spin_unlock(&lcdc_dev->reg_lock);
181 static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
183 #ifdef CONFIG_RK_FPGA
184 lcdc_dev->clk_on = 0;
187 if (lcdc_dev->clk_on) {
188 spin_lock(&lcdc_dev->reg_lock);
189 lcdc_dev->clk_on = 0;
190 spin_unlock(&lcdc_dev->reg_lock);
193 clk_disable_unprepare(lcdc_dev->pd);
194 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
195 pm_runtime_put(lcdc_dev->dev);
197 clk_disable_unprepare(lcdc_dev->dclk);
198 clk_disable_unprepare(lcdc_dev->hclk);
199 clk_disable_unprepare(lcdc_dev->aclk);
205 static int __maybe_unused
206 rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
209 u32 intr_en_reg, intr_clr_reg;
211 if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
212 intr_clr_reg = INTR_CLEAR_RK3366;
213 intr_en_reg = INTR_EN_RK3366;
215 intr_clr_reg = INTR_CLEAR_RK3368;
216 intr_en_reg = INTR_EN_RK3368;
219 spin_lock(&lcdc_dev->reg_lock);
220 if (likely(lcdc_dev->clk_on)) {
221 mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN |
222 m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN |
223 m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN |
224 m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
225 m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
226 m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
227 m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN;
228 val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) |
229 v_ADDR_SAME_INTR_EN(0) |
230 v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) |
231 v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) |
232 v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) |
233 v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) |
234 v_POST_BUF_EMPTY_INTR_EN(0) |
235 v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0);
236 lcdc_msk_reg(lcdc_dev, intr_en_reg, mask, val);
238 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR |
239 m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
240 m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR |
241 m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
242 m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
243 m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
244 m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR;
245 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
246 v_ADDR_SAME_INTR_CLR(1) |
247 v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) |
248 v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) |
249 v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) |
250 v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) |
251 v_POST_BUF_EMPTY_INTR_CLR(1) |
252 v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1);
253 lcdc_msk_reg(lcdc_dev, intr_clr_reg, mask, val);
254 lcdc_cfg_done(lcdc_dev);
255 spin_unlock(&lcdc_dev->reg_lock);
257 spin_unlock(&lcdc_dev->reg_lock);
263 static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
265 struct lcdc_device *lcdc_dev =
266 container_of(dev_drv, struct lcdc_device, driver);
267 int *cbase = (int *)lcdc_dev->regs;
268 int *regsbak = (int *)lcdc_dev->regsbak;
270 char dbg_message[30];
273 pr_info("lcd back up reg:\n");
274 memset(dbg_message, 0, sizeof(dbg_message));
275 memset(buf, 0, sizeof(buf));
276 for (i = 0; i <= (0x200 >> 4); i++) {
277 val = sprintf(dbg_message, "0x%04x: ", i * 16);
278 for (j = 0; j < 4; j++) {
279 val = sprintf(buf, "%08x ", *(regsbak + i * 4 + j));
280 strcat(dbg_message, buf);
282 pr_info("%s\n", dbg_message);
283 memset(dbg_message, 0, sizeof(dbg_message));
284 memset(buf, 0, sizeof(buf));
287 pr_info("lcdc reg:\n");
288 for (i = 0; i <= (0x200 >> 4); i++) {
289 val = sprintf(dbg_message, "0x%04x: ", i * 16);
290 for (j = 0; j < 4; j++) {
291 sprintf(buf, "%08x ",
292 readl_relaxed(cbase + i * 4 + j));
293 strcat(dbg_message, buf);
295 pr_info("%s\n", dbg_message);
296 memset(dbg_message, 0, sizeof(dbg_message));
297 memset(buf, 0, sizeof(buf));
304 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en) \
307 spin_lock(&lcdc_dev->reg_lock); \
308 msk = m_WIN##id##_EN; \
309 val = v_WIN##id##_EN(en); \
310 lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val); \
311 lcdc_cfg_done(lcdc_dev); \
312 spin_unlock(&lcdc_dev->reg_lock); \
320 /*enable/disable win directly*/
321 static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv,
324 struct lcdc_device *lcdc_dev =
325 container_of(drv, struct lcdc_device, driver);
327 win0_enable(lcdc_dev, en);
328 else if (win_id == 1)
329 win1_enable(lcdc_dev, en);
330 else if (win_id == 2)
331 win2_enable(lcdc_dev, en);
332 else if (win_id == 3)
333 win3_enable(lcdc_dev, en);
335 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
339 #define SET_WIN_ADDR(id) \
340 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
343 spin_lock(&lcdc_dev->reg_lock); \
344 lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr); \
345 msk = m_WIN##id##_EN; \
346 val = v_WIN0_EN(1); \
347 lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val); \
348 lcdc_cfg_done(lcdc_dev); \
349 spin_unlock(&lcdc_dev->reg_lock); \
355 int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
356 int win_id, u32 addr)
358 struct lcdc_device *lcdc_dev =
359 container_of(dev_drv, struct lcdc_device, driver);
361 set_win0_addr(lcdc_dev, addr);
363 set_win1_addr(lcdc_dev, addr);
368 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
372 struct rk_screen *screen = lcdc_dev->driver.cur_screen;
373 u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
374 u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
375 u32 st_x = 0, st_y = 0;
376 struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
378 spin_lock(&lcdc_dev->reg_lock);
379 for (reg = 0; reg < SCAN_LINE_NUM; reg += 4) {
380 val = lcdc_readl_backup(lcdc_dev, reg);
383 lcdc_dev->soc_type = val;
386 win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1;
388 ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
391 win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1;
392 win0->area[0].ysize =
393 ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
396 st_x = val & m_WIN0_DSP_XST;
397 st_y = (val & m_WIN0_DSP_YST) >> 16;
398 win0->area[0].xpos = st_x - h_pw_bp;
399 win0->area[0].ypos = st_y - v_pw_bp;
402 win0->state = val & m_WIN0_EN;
403 win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1;
404 win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
405 win0->area[0].format = win0->area[0].fmt_cfg;
408 win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE;
409 win0->area[0].uv_vir_stride =
410 (val & m_WIN0_VIR_STRIDE_UV) >> 16;
411 if (win0->area[0].format == ARGB888)
412 win0->area[0].xvir = win0->area[0].y_vir_stride;
413 else if (win0->area[0].format == RGB888)
415 win0->area[0].y_vir_stride * 4 / 3;
416 else if (win0->area[0].format == RGB565)
418 2 * win0->area[0].y_vir_stride;
421 4 * win0->area[0].y_vir_stride;
424 win0->area[0].smem_start = val;
427 win0->area[0].cbr_start = val;
429 case DSP_VACT_ST_END:
430 if (support_uboot_display()) {
432 (val & 0x1fff) - ((val >> 16) & 0x1fff);
434 st_y - ((val >> 16) & 0x1fff);
437 case DSP_HACT_ST_END:
438 if (support_uboot_display()) {
440 (val & 0x1fff) - ((val >> 16) & 0x1fff);
442 st_x - ((val >> 16) & 0x1fff);
449 spin_unlock(&lcdc_dev->reg_lock);
452 /********do basic init*********/
453 static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
456 struct lcdc_device *lcdc_dev =
457 container_of(dev_drv, struct lcdc_device, driver);
458 if (lcdc_dev->pre_init)
461 lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
462 lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
463 lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
464 if ((IS_ERR(lcdc_dev->aclk)) || (IS_ERR(lcdc_dev->dclk)) ||
465 (IS_ERR(lcdc_dev->hclk))) {
466 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
470 lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
471 if (IS_ERR(lcdc_dev->pd)) {
472 dev_err(lcdc_dev->dev, "failed to get lcdc%d pdclk source\n",
477 if (!support_uboot_display())
478 rk_disp_pwr_enable(dev_drv);
479 rk3368_lcdc_clk_enable(lcdc_dev);
481 /*backup reg config at uboot */
482 lcdc_read_reg_defalut_cfg(lcdc_dev);
483 if (lcdc_dev->soc_type == VOP_FULL_RK3366)
484 lcdc_grf_writel(lcdc_dev->grf_base, RK3366_GRF_IO_VSEL,
485 RK3366_GRF_VOP_IOVOL_SEL(lcdc_dev->pwr18));
487 lcdc_grf_writel(lcdc_dev->pmugrf_base,
489 RK3368_GRF_VOP_IOVOL_SEL(lcdc_dev->pwr18));
491 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_0,0x15110903);
492 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_1,0x00030911);
493 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_0,0x1a150b04);
494 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_1,0x00040b15);
495 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_0,0x15110903);
496 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_1,0x00030911);
498 lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
499 lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
500 lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696);
501 lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969);
502 lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
503 lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
505 mask = m_AUTO_GATING_EN;
506 val = v_AUTO_GATING_EN(0);
507 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
508 mask = m_DITHER_UP_EN;
509 val = v_DITHER_UP_EN(1);
510 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
511 lcdc_cfg_done(lcdc_dev);
512 /*disable win0 to workaround iommu pagefault */
513 /*if (dev_drv->iommu_enabled) */
514 /* win0_enable(lcdc_dev, 0); */
515 lcdc_dev->pre_init = true;
520 static void rk3368_lcdc_deint(struct lcdc_device *lcdc_dev)
524 if (lcdc_dev->clk_on) {
525 rk3368_lcdc_disable_irq(lcdc_dev);
526 spin_lock(&lcdc_dev->reg_lock);
529 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
530 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
532 mask = m_WIN2_EN | m_WIN2_MST0_EN |
534 m_WIN2_MST2_EN | m_WIN2_MST3_EN;
535 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
537 v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
538 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
539 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
540 lcdc_cfg_done(lcdc_dev);
541 spin_unlock(&lcdc_dev->reg_lock);
546 static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
548 struct lcdc_device *lcdc_dev =
549 container_of(dev_drv, struct lcdc_device, driver);
550 struct rk_screen *screen = dev_drv->cur_screen;
551 u16 x_res = screen->mode.xres;
552 u16 y_res = screen->mode.yres;
554 u16 h_total, v_total;
555 u16 post_hsd_en, post_vsd_en;
556 u16 post_dsp_hact_st, post_dsp_hact_end;
557 u16 post_dsp_vact_st, post_dsp_vact_end;
558 u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
559 u16 post_h_fac, post_v_fac;
561 screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200;
562 screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200;
563 screen->post_xsize = x_res *
564 (dev_drv->overscan.left + dev_drv->overscan.right) / 200;
565 screen->post_ysize = y_res *
566 (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200;
568 h_total = screen->mode.hsync_len + screen->mode.left_margin +
569 x_res + screen->mode.right_margin;
570 v_total = screen->mode.vsync_len + screen->mode.upper_margin +
571 y_res + screen->mode.lower_margin;
573 if (screen->post_dsp_stx + screen->post_xsize > x_res) {
574 dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
575 screen->post_dsp_stx, screen->post_xsize, x_res);
576 screen->post_dsp_stx = x_res - screen->post_xsize;
578 if (screen->x_mirror == 0) {
579 post_dsp_hact_st = screen->post_dsp_stx +
580 screen->mode.hsync_len + screen->mode.left_margin;
581 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
583 post_dsp_hact_end = h_total - screen->mode.right_margin -
584 screen->post_dsp_stx;
585 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
587 if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
590 GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
596 if (screen->post_dsp_sty + screen->post_ysize > y_res) {
597 dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
598 screen->post_dsp_sty, screen->post_ysize, y_res);
599 screen->post_dsp_sty = y_res - screen->post_ysize;
602 if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
604 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
611 if (screen->mode.vmode & FB_VMODE_INTERLACED) {
612 post_dsp_vact_st = screen->post_dsp_sty / 2 +
613 screen->mode.vsync_len +
614 screen->mode.upper_margin;
615 post_dsp_vact_end = post_dsp_vact_st +
616 screen->post_ysize / 2;
618 post_dsp_vact_st_f1 = screen->mode.vsync_len +
619 screen->mode.upper_margin +
621 screen->mode.lower_margin +
622 screen->mode.vsync_len +
623 screen->mode.upper_margin +
624 screen->post_dsp_sty / 2 +
626 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
627 screen->post_ysize/2;
629 if (screen->y_mirror == 0) {
630 post_dsp_vact_st = screen->post_dsp_sty +
631 screen->mode.vsync_len +
632 screen->mode.upper_margin;
633 post_dsp_vact_end = post_dsp_vact_st +
636 post_dsp_vact_end = v_total -
637 screen->mode.lower_margin -
638 screen->post_dsp_sty;
639 post_dsp_vact_st = post_dsp_vact_end -
642 post_dsp_vact_st_f1 = 0;
643 post_dsp_vact_end_f1 = 0;
645 DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
646 screen->post_xsize, screen->post_ysize, screen->xpos);
647 DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
648 screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
649 mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
650 val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
651 v_DSP_HACT_ST_POST(post_dsp_hact_st);
652 lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
654 mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
655 val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
656 v_DSP_VACT_ST_POST(post_dsp_vact_st);
657 lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
659 mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
660 val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
661 v_POST_VS_FACTOR_YRGB(post_v_fac);
662 lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
664 mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
665 val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
666 v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
667 lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
669 mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
670 val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
671 lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
675 static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
677 struct lcdc_device *lcdc_dev =
678 container_of(dev_drv, struct lcdc_device, driver);
679 struct rk_lcdc_win *win;
680 u32 colorkey_r, colorkey_g, colorkey_b;
683 for (i = 0; i < 4; i++) {
684 win = dev_drv->win[i];
685 key_val = win->color_key_val;
686 colorkey_r = (key_val & 0xff) << 2;
687 colorkey_g = ((key_val >> 8) & 0xff) << 12;
688 colorkey_b = ((key_val >> 16) & 0xff) << 22;
689 /*color key dither 565/888->aaa */
690 key_val = colorkey_r | colorkey_g | colorkey_b;
693 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
696 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
699 lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
702 lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
705 pr_info("%s:un support win num:%d\n",
713 static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
715 struct lcdc_device *lcdc_dev =
716 container_of(dev_drv, struct lcdc_device, driver);
717 struct rk_lcdc_win *win = dev_drv->win[win_id];
718 struct alpha_config alpha_config;
720 int ppixel_alpha = 0, global_alpha = 0, i;
721 u32 src_alpha_ctl = 0, dst_alpha_ctl = 0;
723 memset(&alpha_config, 0, sizeof(struct alpha_config));
724 for (i = 0; i < win->area_num; i++) {
725 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
726 (win->area[i].format == FBDC_ARGB_888) ||
727 (win->area[i].format == FBDC_ABGR_888) ||
728 (win->area[i].format == ABGR888)) ? 1 : 0;
730 global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
731 alpha_config.src_global_alpha_val = win->g_alpha_val;
732 win->alpha_mode = AB_SRC_OVER;
733 switch (win->alpha_mode) {
737 alpha_config.src_factor_mode = AA_ZERO;
738 alpha_config.dst_factor_mode = AA_ZERO;
741 alpha_config.src_factor_mode = AA_ONE;
742 alpha_config.dst_factor_mode = AA_ZERO;
745 alpha_config.src_factor_mode = AA_ZERO;
746 alpha_config.dst_factor_mode = AA_ONE;
749 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
751 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
753 alpha_config.src_factor_mode = AA_ONE;
754 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
757 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
758 alpha_config.src_factor_mode = AA_SRC_INVERSE;
759 alpha_config.dst_factor_mode = AA_ONE;
762 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
763 alpha_config.src_factor_mode = AA_SRC;
764 alpha_config.dst_factor_mode = AA_ZERO;
767 alpha_config.src_factor_mode = AA_ZERO;
768 alpha_config.dst_factor_mode = AA_SRC;
771 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
772 alpha_config.src_factor_mode = AA_SRC_INVERSE;
773 alpha_config.dst_factor_mode = AA_ZERO;
776 alpha_config.src_factor_mode = AA_ZERO;
777 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
780 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
781 alpha_config.src_factor_mode = AA_SRC;
782 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
785 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
786 alpha_config.src_factor_mode = AA_SRC_INVERSE;
787 alpha_config.dst_factor_mode = AA_SRC;
790 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
791 alpha_config.src_factor_mode = AA_SRC_INVERSE;
792 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
794 case AB_SRC_OVER_GLOBAL:
795 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
796 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
797 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
798 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
801 pr_err("alpha mode error\n");
804 if ((ppixel_alpha == 1) && (global_alpha == 1))
805 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
806 else if (ppixel_alpha == 1)
807 alpha_config.src_global_alpha_mode = AA_PER_PIX;
808 else if (global_alpha == 1)
809 alpha_config.src_global_alpha_mode = AA_GLOBAL;
811 dev_warn(lcdc_dev->dev, "alpha_en should be 0\n");
812 alpha_config.src_alpha_mode = AA_STRAIGHT;
813 alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
817 src_alpha_ctl = 0x60;
818 dst_alpha_ctl = 0x64;
821 src_alpha_ctl = 0xa0;
822 dst_alpha_ctl = 0xa4;
825 src_alpha_ctl = 0xdc;
826 dst_alpha_ctl = 0xec;
829 src_alpha_ctl = 0x12c;
830 dst_alpha_ctl = 0x13c;
833 src_alpha_ctl = 0x160;
834 dst_alpha_ctl = 0x164;
837 mask = m_WIN0_DST_FACTOR_M0;
838 val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
839 lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
840 mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
841 m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
842 m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 |
843 m_WIN0_SRC_GLOBAL_ALPHA;
844 val = v_WIN0_SRC_ALPHA_EN(1) |
845 v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
846 v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
847 v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
848 v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
849 v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
850 v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
851 lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
856 static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num)
858 struct rk_lcdc_win_area area_temp;
861 for (i = 0; i < area_num; i++) {
862 for (j = i + 1; j < area_num; j++) {
863 if (win->area[i].dsp_stx > win->area[j].dsp_stx) {
864 memcpy(&area_temp, &win->area[i],
865 sizeof(struct rk_lcdc_win_area));
866 memcpy(&win->area[i], &win->area[j],
867 sizeof(struct rk_lcdc_win_area));
868 memcpy(&win->area[j], &area_temp,
869 sizeof(struct rk_lcdc_win_area));
877 static int __maybe_unused
878 rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num)
880 struct rk_lcdc_win_area area_temp;
884 area_temp = win->area[0];
885 win->area[0] = win->area[1];
886 win->area[1] = area_temp;
889 area_temp = win->area[0];
890 win->area[0] = win->area[2];
891 win->area[2] = area_temp;
894 area_temp = win->area[0];
895 win->area[0] = win->area[3];
896 win->area[3] = area_temp;
898 area_temp = win->area[1];
899 win->area[1] = win->area[2];
900 win->area[2] = area_temp;
903 pr_info("un supported area num!\n");
909 static int __maybe_unused
910 rk3368_win_area_check_var(int win_id, int area_num,
911 struct rk_lcdc_win_area *area_pre,
912 struct rk_lcdc_win_area *area_now)
914 if ((area_pre->xpos > area_now->xpos) ||
915 ((area_pre->xpos + area_pre->xsize > area_now->xpos) &&
916 (area_pre->ypos + area_pre->ysize > area_now->ypos))) {
919 "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n"
920 "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n",
922 area_num - 1, area_pre->xpos, area_pre->xsize,
923 area_pre->ypos, area_pre->ysize,
924 area_num, area_now->xpos, area_now->xsize,
925 area_now->ypos, area_now->ysize);
931 static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv)
933 struct lcdc_device *lcdc_dev =
934 container_of(dev_drv, struct lcdc_device, driver);
937 for (i = 0; i < 100; i++) {
938 val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0);
939 val &= m_DBG_IFBDC_IDLE;
948 static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
950 struct lcdc_device *lcdc_dev =
951 container_of(dev_drv, struct lcdc_device, driver);
952 struct rk_lcdc_win *win = dev_drv->win[win_id];
955 if (lcdc_dev->soc_type != VOP_FULL_RK3368) {
956 pr_err("soc: 0x%08x not support FBDC\n", lcdc_dev->soc_type);
959 mask = m_IFBDC_CTRL_FBDC_COR_EN |
960 m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE |
961 m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO;
962 val = v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) |
963 v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) |
964 v_IFBDC_CTRL_FBDC_ROTATION_MODE((win->xmirror &&
965 win->ymirror) << 1) |
966 v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) |
967 v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio);
968 lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
970 mask = m_IFBDC_TILES_NUM;
971 val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles);
972 lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val);
974 mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT;
975 val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) |
976 v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height);
977 lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val);
979 mask = m_IFBDC_CMP_INDEX_INIT;
980 val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init);
981 lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val);
983 mask = m_IFBDC_MB_VIR_WIDTH;
984 val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width);
985 lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val);
990 static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id)
992 struct lcdc_device *lcdc_dev =
993 container_of(dev_drv, struct lcdc_device, driver);
994 struct rk_lcdc_win *win = dev_drv->win[win_id];
995 u8 fbdc_dsp_width_ratio = 0;
996 u16 fbdc_mb_vir_width = 0, fbdc_mb_vir_height = 0;
997 u16 fbdc_mb_width = 0, fbdc_mb_height = 0;
998 u16 fbdc_mb_xst = 0, fbdc_mb_yst = 0, fbdc_num_tiles = 0;
999 u16 fbdc_cmp_index_init = 0;
1000 u8 mb_w_size = 0, mb_h_size = 0;
1001 struct rk_screen *screen = dev_drv->cur_screen;
1003 if (screen->mode.flag & FB_VMODE_INTERLACED) {
1004 dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n");
1008 if (lcdc_dev->soc_type != VOP_FULL_RK3368) {
1009 pr_err("soc: 0x%08x not support FBDC\n", lcdc_dev->soc_type);
1012 switch (win->area[0].fmt_cfg) {
1013 case VOP_FORMAT_ARGB888:
1014 fbdc_dsp_width_ratio = 0;
1017 case VOP_FORMAT_RGB888:
1018 fbdc_dsp_width_ratio = 0;
1021 case VOP_FORMAT_RGB565:
1022 fbdc_dsp_width_ratio = 1;
1026 dev_err(lcdc_dev->dev,
1027 "in fbdc mode,unsupport fmt:%d!\n",
1028 win->area[0].fmt_cfg);
1033 /*macro block xvir and yvir */
1034 if ((win->area[0].xvir % mb_w_size == 0) &&
1035 (win->area[0].yvir % mb_h_size == 0)) {
1036 fbdc_mb_vir_width = win->area[0].xvir / mb_w_size;
1037 fbdc_mb_vir_height = win->area[0].yvir / mb_h_size;
1039 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
1040 pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n",
1041 win->area[0].xvir, win->area[0].yvir,
1042 mb_w_size, mb_h_size);
1044 /*macro block xact and yact */
1045 if ((win->area[0].xact % mb_w_size == 0) &&
1046 (win->area[0].yact % mb_h_size == 0)) {
1047 fbdc_mb_width = win->area[0].xact / mb_w_size;
1048 fbdc_mb_height = win->area[0].yact / mb_h_size;
1050 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
1051 pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n",
1052 win->area[0].xact, win->area[0].yact,
1053 mb_w_size, mb_h_size);
1055 /*macro block xoff and yoff */
1056 if ((win->area[0].xoff % mb_w_size == 0) &&
1057 (win->area[0].yoff % mb_h_size == 0)) {
1058 fbdc_mb_xst = win->area[0].xoff / mb_w_size;
1059 fbdc_mb_yst = win->area[0].yoff / mb_h_size;
1061 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
1062 pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n",
1063 win->area[0].xoff, win->area[0].yoff,
1064 mb_w_size, mb_h_size);
1068 fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height;
1071 switch (fbdc_rotation_mode) {
1073 fbdc_cmp_index_init =
1074 (fbdc_mb_yst*fbdc_mb_vir_width) + fbdc_mb_xst;
1077 fbdc_cmp_index_init =
1078 (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+
1082 fbdc_cmp_index_init =
1083 ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
1087 fbdc_cmp_index_init =
1088 ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
1089 (fbdc_mb_xst+(fbdc_mb_width-1));
1093 if (win->xmirror && win->ymirror && ((win_id == 2) || (win_id == 3))) {
1094 fbdc_cmp_index_init =
1095 ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) +
1096 (fbdc_mb_xst + (fbdc_mb_width - 1));
1098 fbdc_cmp_index_init =
1099 (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst;
1101 /*fbdc fmt maybe need to change*/
1102 win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio;
1103 win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width;
1104 win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height;
1105 win->area[0].fbdc_mb_width = fbdc_mb_width;
1106 win->area[0].fbdc_mb_height = fbdc_mb_height;
1107 win->area[0].fbdc_mb_xst = fbdc_mb_xst;
1108 win->area[0].fbdc_mb_yst = fbdc_mb_yst;
1109 win->area[0].fbdc_num_tiles = fbdc_num_tiles;
1110 win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init;
1115 static int rk3368_lcdc_axi_gather_cfg(struct lcdc_device *lcdc_dev,
1116 struct rk_lcdc_win *win)
1119 u16 yrgb_gather_num = 3;
1120 u16 cbcr_gather_num = 1;
1122 switch (win->area[0].format) {
1130 yrgb_gather_num = 3;
1137 yrgb_gather_num = 2;
1143 yrgb_gather_num = 1;
1144 cbcr_gather_num = 2;
1147 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
1152 if ((win->id == 0) || (win->id == 1)) {
1153 mask = m_WIN0_YRGB_AXI_GATHER_EN | m_WIN0_CBR_AXI_GATHER_EN |
1154 m_WIN0_YRGB_AXI_GATHER_NUM | m_WIN0_CBR_AXI_GATHER_NUM;
1155 val = v_WIN0_YRGB_AXI_GATHER_EN(1) |
1156 v_WIN0_CBR_AXI_GATHER_EN(1) |
1157 v_WIN0_YRGB_AXI_GATHER_NUM(yrgb_gather_num) |
1158 v_WIN0_CBR_AXI_GATHER_NUM(cbcr_gather_num);
1159 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + (win->id * 0x40),
1161 } else if ((win->id == 2) || (win->id == 3)) {
1162 mask = m_WIN2_AXI_GATHER_EN | m_WIN2_AXI_GATHER_NUM;
1163 val = v_WIN2_AXI_GATHER_EN(1) |
1164 v_WIN2_AXI_GATHER_NUM(yrgb_gather_num);
1165 lcdc_msk_reg(lcdc_dev, WIN2_CTRL1 + ((win->id - 2) * 0x50),
1167 } else if (win->id == 4) {
1168 mask = m_HWC_AXI_GATHER_EN | m_HWC_AXI_GATHER_NUM;
1169 val = v_HWC_AXI_GATHER_EN(1) |
1170 v_HWC_AXI_GATHER_NUM(yrgb_gather_num);
1171 lcdc_msk_reg(lcdc_dev, HWC_CTRL1, mask, val);
1176 static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev,
1177 struct rk_lcdc_win *win)
1179 struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1180 struct rk_screen *screen = dev_drv->cur_screen;
1182 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1183 switch (win->area[0].fmt_cfg) {
1184 case VOP_FORMAT_ARGB888:
1185 case VOP_FORMAT_RGB888:
1186 case VOP_FORMAT_RGB565:
1187 if ((screen->mode.xres < 1280) &&
1188 (screen->mode.yres < 720)) {
1189 win->csc_mode = VOP_R2Y_CSC_BT601;
1191 win->csc_mode = VOP_R2Y_CSC_BT709;
1197 } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
1198 switch (win->area[0].fmt_cfg) {
1199 case VOP_FORMAT_YCBCR420:
1200 if ((win->id == 0) || (win->id == 1))
1201 win->csc_mode = VOP_Y2R_CSC_MPEG;
1209 static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1211 struct lcdc_device *lcdc_dev =
1212 container_of(dev_drv, struct lcdc_device, driver);
1213 struct rk_lcdc_win *win = dev_drv->win[win_id];
1214 unsigned int mask, val, off;
1216 off = win_id * 0x40;
1217 /*if(win->win_lb_mode == 5)
1218 win->win_lb_mode = 4;
1219 for rk3288 to fix hw bug? */
1221 if (win->state == 1) {
1222 rk3368_lcdc_csc_mode(lcdc_dev, win);
1223 rk3368_lcdc_axi_gather_cfg(lcdc_dev, win);
1224 if (win->area[0].fbdc_en)
1225 rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1226 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
1227 m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR |
1228 m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE | m_WIN0_UV_SWAP;
1229 val = v_WIN0_EN(win->state) |
1230 v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1231 v_WIN0_FMT_10(win->fmt_10) |
1232 v_WIN0_LB_MODE(win->win_lb_mode) |
1233 v_WIN0_RB_SWAP(win->area[0].swap_rb) |
1234 v_WIN0_X_MIRROR(win->xmirror) |
1235 v_WIN0_Y_MIRROR(win->ymirror) |
1236 v_WIN0_CSC_MODE(win->csc_mode) |
1237 v_WIN0_UV_SWAP(win->area[0].swap_uv);
1238 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1240 mask = m_WIN0_BIC_COE_SEL |
1241 m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
1242 m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
1243 m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
1244 m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
1245 m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
1246 m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
1247 m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
1248 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1249 v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1250 v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1251 v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1252 v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1253 v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1254 v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1255 v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1256 v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1257 v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1258 v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1259 v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1260 v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1261 v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1262 v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1263 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val);
1264 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1265 v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1266 lcdc_writel(lcdc_dev, WIN0_VIR + off, val);
1267 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off,
1268 win->area[0].y_addr);
1269 lcdc_writel(lcdc_dev, WIN0_CBR_MST+off,
1270 win->area[0].uv_addr); */
1271 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
1272 v_WIN0_ACT_HEIGHT(win->area[0].yact);
1273 lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val);
1275 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
1276 v_WIN0_DSP_HEIGHT(win->area[0].ysize);
1277 lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val);
1279 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
1280 v_WIN0_DSP_YST(win->area[0].dsp_sty);
1281 lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val);
1283 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1284 v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1285 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1287 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1288 v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1289 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val);
1290 if (win->alpha_en == 1) {
1291 rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1293 mask = m_WIN0_SRC_ALPHA_EN;
1294 val = v_WIN0_SRC_ALPHA_EN(0);
1295 lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off,
1299 if (dev_drv->cur_screen->mode.vmode & FB_VMODE_INTERLACED) {
1300 mask = m_WIN0_YRGB_DEFLICK | m_WIN0_CBR_DEFLICK;
1301 if (win->area[0].yact == 2 * win->area[0].ysize)
1302 val = v_WIN0_YRGB_DEFLICK(0) |
1303 v_WIN0_CBR_DEFLICK(0);
1305 val = v_WIN0_YRGB_DEFLICK(1) |
1306 v_WIN0_CBR_DEFLICK(1);
1307 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1311 val = v_WIN0_EN(win->state);
1312 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1317 static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1319 struct lcdc_device *lcdc_dev =
1320 container_of(dev_drv, struct lcdc_device, driver);
1321 struct rk_lcdc_win *win = dev_drv->win[win_id];
1322 unsigned int mask, val, off;
1324 off = (win_id - 2) * 0x50;
1325 rk3368_lcdc_area_xst(win, win->area_num);
1327 if (win->state == 1) {
1328 rk3368_lcdc_csc_mode(lcdc_dev, win);
1329 rk3368_lcdc_axi_gather_cfg(lcdc_dev, win);
1330 if (win->area[0].fbdc_en)
1331 rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1333 mask = m_WIN2_EN | m_WIN2_CSC_MODE;
1334 val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode);
1335 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1337 if (win->area[0].state == 1) {
1338 mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 |
1340 val = v_WIN2_MST0_EN(win->area[0].state) |
1341 v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1342 v_WIN2_RB_SWAP0(win->area[0].swap_rb);
1343 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1345 mask = m_WIN2_VIR_STRIDE0;
1346 val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1347 lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1349 /*lcdc_writel(lcdc_dev,WIN2_MST0+off,
1350 win->area[0].y_addr); */
1351 val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1352 v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1353 lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val);
1354 val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1355 v_WIN2_DSP_YST0(win->area[0].dsp_sty);
1356 lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val);
1358 mask = m_WIN2_MST0_EN;
1359 val = v_WIN2_MST0_EN(0);
1360 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1363 if (win->area[1].state == 1) {
1364 /*rk3368_win_area_check_var(win_id, 1,
1365 &win->area[0], &win->area[1]);
1368 mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 |
1370 val = v_WIN2_MST1_EN(win->area[1].state) |
1371 v_WIN2_DATA_FMT1(win->area[1].fmt_cfg) |
1372 v_WIN2_RB_SWAP1(win->area[1].swap_rb);
1373 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1375 mask = m_WIN2_VIR_STRIDE1;
1376 val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1377 lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1379 /*lcdc_writel(lcdc_dev,WIN2_MST1+off,
1380 win->area[1].y_addr); */
1381 val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1382 v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1383 lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val);
1384 val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1385 v_WIN2_DSP_YST1(win->area[1].dsp_sty);
1386 lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val);
1388 mask = m_WIN2_MST1_EN;
1389 val = v_WIN2_MST1_EN(0);
1390 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1393 if (win->area[2].state == 1) {
1394 /*rk3368_win_area_check_var(win_id, 2,
1395 &win->area[1], &win->area[2]);
1398 mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 |
1400 val = v_WIN2_MST2_EN(win->area[2].state) |
1401 v_WIN2_DATA_FMT2(win->area[2].fmt_cfg) |
1402 v_WIN2_RB_SWAP2(win->area[2].swap_rb);
1403 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1405 mask = m_WIN2_VIR_STRIDE2;
1406 val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1407 lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1409 /*lcdc_writel(lcdc_dev,WIN2_MST2+off,
1410 win->area[2].y_addr); */
1411 val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1412 v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1413 lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val);
1414 val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1415 v_WIN2_DSP_YST2(win->area[2].dsp_sty);
1416 lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val);
1418 mask = m_WIN2_MST2_EN;
1419 val = v_WIN2_MST2_EN(0);
1420 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1423 if (win->area[3].state == 1) {
1424 /*rk3368_win_area_check_var(win_id, 3,
1425 &win->area[2], &win->area[3]);
1428 mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 |
1430 val = v_WIN2_MST3_EN(win->area[3].state) |
1431 v_WIN2_DATA_FMT3(win->area[3].fmt_cfg) |
1432 v_WIN2_RB_SWAP3(win->area[3].swap_rb);
1433 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1435 mask = m_WIN2_VIR_STRIDE3;
1436 val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1437 lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1439 /*lcdc_writel(lcdc_dev,WIN2_MST3+off,
1440 win->area[3].y_addr); */
1441 val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1442 v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1443 lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val);
1444 val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1445 v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1446 lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val);
1448 mask = m_WIN2_MST3_EN;
1449 val = v_WIN2_MST3_EN(0);
1450 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1453 if (win->alpha_en == 1) {
1454 rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1456 mask = m_WIN2_SRC_ALPHA_EN;
1457 val = v_WIN2_SRC_ALPHA_EN(0);
1458 lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off,
1462 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1463 m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1464 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1465 v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1466 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1471 static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1473 struct lcdc_device *lcdc_dev =
1474 container_of(dev_drv, struct lcdc_device, driver);
1475 struct rk_lcdc_win *win = dev_drv->win[win_id];
1476 unsigned int mask, val, hwc_size = 0;
1478 if (win->state == 1) {
1479 rk3368_lcdc_csc_mode(lcdc_dev, win);
1480 rk3368_lcdc_axi_gather_cfg(lcdc_dev, win);
1481 mask = m_HWC_EN | m_HWC_DATA_FMT |
1482 m_HWC_RB_SWAP | m_WIN0_CSC_MODE;
1483 val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1484 v_HWC_RB_SWAP(win->area[0].swap_rb) |
1485 v_WIN0_CSC_MODE(win->csc_mode);
1486 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1488 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1490 else if ((win->area[0].xsize == 64) &&
1491 (win->area[0].ysize == 64))
1493 else if ((win->area[0].xsize == 96) &&
1494 (win->area[0].ysize == 96))
1496 else if ((win->area[0].xsize == 128) &&
1497 (win->area[0].ysize == 128))
1500 dev_err(lcdc_dev->dev, "un supported hwc size!\n");
1503 val = v_HWC_SIZE(hwc_size);
1504 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1506 mask = m_HWC_DSP_XST | m_HWC_DSP_YST;
1507 val = v_HWC_DSP_XST(win->area[0].dsp_stx) |
1508 v_HWC_DSP_YST(win->area[0].dsp_sty);
1509 lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val);
1511 if (win->alpha_en == 1) {
1512 rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1514 mask = m_WIN2_SRC_ALPHA_EN;
1515 val = v_WIN2_SRC_ALPHA_EN(0);
1516 lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val);
1520 val = v_HWC_EN(win->state);
1521 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1526 static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
1527 struct rk_lcdc_win *win)
1529 struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1531 unsigned long flags;
1533 if (likely(lcdc_dev->clk_on)) {
1534 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1535 v_STANDBY_EN(lcdc_dev->standby));
1536 if ((win->id == 0) || (win->id == 1))
1537 rk3368_win_0_1_reg_update(dev_drv, win->id);
1538 else if ((win->id == 2) || (win->id == 3))
1539 rk3368_win_2_3_reg_update(dev_drv, win->id);
1540 else if (win->id == 4)
1541 rk3368_hwc_reg_update(dev_drv, win->id);
1542 /*rk3368_lcdc_post_cfg(dev_drv); */
1543 lcdc_cfg_done(lcdc_dev);
1546 /*if (dev_drv->wait_fs) { */
1548 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1549 init_completion(&dev_drv->frame_done);
1550 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1552 wait_for_completion_timeout(&dev_drv->frame_done,
1554 (dev_drv->cur_screen->ft + 5));
1555 if (!timeout && (!dev_drv->frame_done.done)) {
1556 dev_warn(lcdc_dev->dev,
1557 "wait for new frame start time out!\n");
1561 DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1565 static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1567 memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x270);
1571 static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1574 struct lcdc_device *lcdc_dev =
1575 container_of(dev_drv, struct lcdc_device, driver);
1577 if (unlikely(!lcdc_dev->clk_on)) {
1578 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
1581 if (dev_drv->iommu_enabled) {
1582 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1583 if (likely(lcdc_dev->clk_on)) {
1586 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1587 mask = m_AXI_MAX_OUTSTANDING_EN |
1588 m_AXI_OUTSTANDING_MAX_NUM;
1589 val = v_AXI_OUTSTANDING_MAX_NUM(31) |
1590 v_AXI_MAX_OUTSTANDING_EN(1);
1591 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1593 lcdc_dev->iommu_status = 1;
1594 rockchip_iovmm_activate(dev_drv->dev);
1600 static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate)
1602 int ret = 0, fps = 0;
1603 struct lcdc_device *lcdc_dev =
1604 container_of(dev_drv, struct lcdc_device, driver);
1605 struct rk_screen *screen = dev_drv->cur_screen;
1606 #ifdef CONFIG_RK_FPGA
1610 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
1612 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1613 lcdc_dev->pixclock =
1614 div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1615 lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1617 fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1618 screen->ft = 1000 / fps;
1619 dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1620 lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1624 static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv)
1626 struct lcdc_device *lcdc_dev =
1627 container_of(dev_drv, struct lcdc_device, driver);
1628 struct rk_screen *screen = dev_drv->cur_screen;
1629 u16 hsync_len = screen->mode.hsync_len;
1630 u16 left_margin = screen->mode.left_margin;
1631 u16 right_margin = screen->mode.right_margin;
1632 u16 vsync_len = screen->mode.vsync_len;
1633 u16 upper_margin = screen->mode.upper_margin;
1634 u16 lower_margin = screen->mode.lower_margin;
1635 u16 x_res = screen->mode.xres;
1636 u16 y_res = screen->mode.yres;
1638 u16 h_total, v_total;
1639 u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1643 if (lcdc_dev->soc_type == VOP_FULL_RK3366)
1644 line_flag_reg = LINE_FLAG_RK3366;
1646 line_flag_reg = LINE_FLAG_RK3368;
1648 h_total = hsync_len + left_margin + x_res + right_margin;
1649 v_total = vsync_len + upper_margin + y_res + lower_margin;
1650 frame_time = 1000 * v_total * h_total / (screen->mode.pixclock / 1000);
1651 mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1652 val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1653 lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1655 mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1656 val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1657 v_DSP_HACT_ST(hsync_len + left_margin);
1658 lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1660 if (screen->mode.vmode & FB_VMODE_INTERLACED) {
1661 /* First Field Timing */
1662 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1663 val = v_DSP_VS_PW(vsync_len) |
1664 v_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1665 lower_margin) + y_res + 1);
1666 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1668 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1669 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1670 v_DSP_VACT_ST(vsync_len + upper_margin);
1671 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1673 /* Second Field Timing */
1674 mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1;
1675 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1676 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1678 val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1);
1679 lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val);
1681 mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1;
1682 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1684 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1687 v_DSP_VACT_END_F1(vact_end_f1) |
1688 v_DSP_VAC_ST_F1(vact_st_f1);
1689 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val);
1691 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1692 m_DSP_INTERLACE | m_DSP_FIELD_POL,
1693 v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0));
1694 if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
1696 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1698 v_SW_CORE_DCLK_SEL(1));
1700 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1702 v_SW_CORE_DCLK_SEL(0));
1705 m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1708 v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(0) |
1709 v_WIN0_CBR_DEFLICK(0);
1710 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1713 m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1716 v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(0) |
1717 v_WIN1_CBR_DEFLICK(0);
1718 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1720 mask = m_WIN2_INTERLACE_READ;
1721 val = v_WIN2_INTERLACE_READ(1);
1722 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1724 mask = m_WIN3_INTERLACE_READ;
1725 val = v_WIN3_INTERLACE_READ(1);
1726 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1728 mask = m_HWC_INTERLACE_READ;
1729 val = v_HWC_INTERLACE_READ(1);
1730 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1732 mask = m_DSP_LINE_FLAG0_NUM | m_DSP_LINE_FLAG1_NUM;
1734 v_DSP_LINE_FLAG0_NUM(vact_end_f1) |
1735 v_DSP_LINE_FLAG1_NUM(vact_end_f1 -
1736 EARLY_TIME * v_total / frame_time);
1737 lcdc_msk_reg(lcdc_dev, line_flag_reg, mask, val);
1739 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1740 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1741 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1743 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1744 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1745 v_DSP_VACT_ST(vsync_len + upper_margin);
1746 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1748 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1749 m_DSP_INTERLACE | m_DSP_FIELD_POL,
1750 v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0));
1751 if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
1752 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1754 v_SW_CORE_DCLK_SEL(0));
1757 m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1760 v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) |
1761 v_WIN0_CBR_DEFLICK(0);
1762 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1765 m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1768 v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) |
1769 v_WIN1_CBR_DEFLICK(0);
1770 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1772 mask = m_WIN2_INTERLACE_READ;
1773 val = v_WIN2_INTERLACE_READ(0);
1774 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1776 mask = m_WIN3_INTERLACE_READ;
1777 val = v_WIN3_INTERLACE_READ(0);
1778 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1780 mask = m_HWC_INTERLACE_READ;
1781 val = v_HWC_INTERLACE_READ(0);
1782 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1784 mask = m_DSP_LINE_FLAG0_NUM | m_DSP_LINE_FLAG1_NUM;
1785 val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res) |
1786 v_DSP_LINE_FLAG1_NUM(vsync_len + upper_margin + y_res -
1787 EARLY_TIME * v_total / frame_time);
1788 lcdc_msk_reg(lcdc_dev, line_flag_reg, mask, val);
1790 rk3368_lcdc_post_cfg(dev_drv);
1794 static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1796 struct lcdc_device *lcdc_dev =
1797 container_of(dev_drv, struct lcdc_device, driver);
1800 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_OVERLAY_MODE,
1801 v_OVERLAY_MODE(dev_drv->overlay_mode));
1802 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1803 if (dev_drv->output_color == COLOR_YCBCR) /* bypass */
1804 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1805 m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1806 v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1808 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1809 m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1812 v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1814 } else { /* overlay_mode=VOP_RGB_DOMAIN */
1815 /* bypass --need check,if bcsh close? */
1816 if (dev_drv->output_color == COLOR_RGB) {
1817 bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1818 if (((bcsh_ctrl & m_BCSH_EN) == 1) ||
1819 (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1820 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1826 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1827 m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1830 } else /* RGB2YUV */
1831 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1833 m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1835 v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1840 static int rk3368_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1841 u16 *yact, int *format, u32 *dsp_addr,
1844 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1845 struct lcdc_device, driver);
1848 spin_lock(&lcdc_dev->reg_lock);
1850 val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1851 *xact = (val & m_WIN0_ACT_WIDTH) + 1;
1852 *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1;
1854 val = lcdc_readl(lcdc_dev, WIN0_CTRL0);
1855 *format = (val & m_WIN0_DATA_FMT) >> 1;
1856 *ymirror = (val & m_WIN0_Y_MIRROR) >> 22;
1857 *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1859 spin_unlock(&lcdc_dev->reg_lock);
1864 static int rk3368_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1865 int format, u16 xact, u16 yact, u16 xvir,
1868 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1869 struct lcdc_device, driver);
1871 struct rk_lcdc_win *win = dev_drv->win[0];
1872 int swap = (format == RGB888) ? 1 : 0;
1874 mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP | m_WIN0_Y_MIRROR;
1875 val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap) |
1876 v_WIN0_Y_MIRROR(ymirror);
1877 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1879 lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE,
1880 v_WIN0_VIR_STRIDE(xvir));
1881 lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) |
1882 v_WIN0_ACT_HEIGHT(yact));
1884 lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1886 lcdc_cfg_done(lcdc_dev);
1887 if (format == RGB888)
1888 win->area[0].format = BGR888;
1890 win->area[0].format = format;
1892 win->ymirror = ymirror;
1894 win->last_state = 1;
1899 static int lcdc_reset(struct rk_lcdc_driver *dev_drv, bool initscreen)
1901 struct lcdc_device *lcdc_dev =
1902 container_of(dev_drv, struct lcdc_device, driver);
1904 u32 __maybe_unused v;
1905 if (!lcdc_dev->standby && initscreen && (dev_drv->first_frame != 1)) {
1909 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1910 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1912 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1914 m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1915 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
1917 v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1918 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1919 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1920 mask = m_HDMI_OUT_EN;
1921 val = v_HDMI_OUT_EN(0);
1922 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1923 lcdc_cfg_done(lcdc_dev);
1925 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
1926 writel_relaxed(0, lcdc_dev->regs + REG_CFG_DONE);
1929 if (dev_drv->iommu_enabled) {
1930 if (dev_drv->mmu_dev)
1931 rockchip_iovmm_deactivate(dev_drv->dev);
1933 lcdc_cru_writel(lcdc_dev->cru_base, 0x0318,
1934 (1 << 4) | (1 << 5) | (1 << 6) |
1935 (1 << 20) | (1 << 21) | (1 << 22));
1937 v = lcdc_cru_readl(lcdc_dev->cru_base, 0x0318);
1938 pr_info("cru read = 0x%x\n", v);
1939 lcdc_cru_writel(lcdc_dev->cru_base, 0x0318,
1940 (0 << 4) | (0 << 5) | (0 << 6) |
1941 (1 << 20) | (1 << 21) | (1 << 22));
1943 if (dev_drv->iommu_enabled) {
1944 if (dev_drv->mmu_dev)
1945 rockchip_iovmm_activate(dev_drv->dev);
1948 rk3368_lcdc_reg_restore(lcdc_dev);
1955 static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1959 struct lcdc_device *lcdc_dev =
1960 container_of(dev_drv, struct lcdc_device, driver);
1961 struct rk_screen *screen = dev_drv->cur_screen;
1962 u32 mask = 0, val = 0;
1964 if (unlikely(!lcdc_dev->clk_on)) {
1965 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
1969 if (!lcdc_dev->standby && initscreen && (dev_drv->first_frame != 1))
1970 flush_kthread_worker(&dev_drv->update_regs_worker);
1972 spin_lock(&lcdc_dev->reg_lock);
1973 if (likely(lcdc_dev->clk_on)) {
1974 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1976 if (!lcdc_dev->standby && !initscreen) {
1977 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1979 lcdc_cfg_done(lcdc_dev);
1983 lcdc_reset(dev_drv, initscreen);
1985 switch (screen->face) {
1988 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1990 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1991 v_DITHER_DOWN_SEL(1);
1992 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1996 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1998 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1999 v_DITHER_DOWN_SEL(1);
2000 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2004 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
2006 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
2007 v_DITHER_DOWN_SEL(1);
2008 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2012 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
2014 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
2015 v_DITHER_DOWN_SEL(1);
2016 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2020 mask = m_DITHER_DOWN_EN;
2021 val = v_DITHER_DOWN_EN(0);
2022 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2025 /*yuv420 output prefer yuv domain overlay */
2028 mask = m_DITHER_DOWN_EN;
2029 val = v_DITHER_DOWN_EN(0);
2030 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2034 mask = m_DITHER_DOWN_EN;
2035 val = v_DITHER_DOWN_EN(0);
2036 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2039 face = OUT_S888DUMY;
2040 mask = m_DITHER_DOWN_EN;
2041 val = v_DITHER_DOWN_EN(0);
2042 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2045 if (screen->color_mode == COLOR_RGB)
2046 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
2048 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
2049 face = OUT_CCIR656_MODE_0;
2050 mask = m_DITHER_DOWN_EN;
2051 val = v_DITHER_DOWN_EN(0);
2052 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2055 dev_err(lcdc_dev->dev, "un supported interface!\n");
2058 switch (screen->type) {
2060 mask = m_RGB_OUT_EN;
2061 val = v_RGB_OUT_EN(1);
2062 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2063 mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
2064 m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
2065 val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
2066 v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
2067 v_RGB_LVDS_DEN_POL(screen->pin_den) |
2068 v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
2069 if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
2070 lcdc_grf_writel(lcdc_dev->grf_base,
2071 RK3366_GRF_SOC_CON5,
2072 RGB_SOURCE_SEL(dev_drv->id));
2073 lcdc_grf_writel(lcdc_dev->grf_base,
2074 RK3366_GRF_SOC_CON0,
2079 mask = m_RGB_OUT_EN;
2080 val = v_RGB_OUT_EN(1);
2081 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2082 mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
2083 m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
2084 val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
2085 v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
2086 v_RGB_LVDS_DEN_POL(screen->pin_den) |
2087 v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
2088 if (lcdc_dev->soc_type == VOP_FULL_RK3366)
2089 lcdc_grf_writel(lcdc_dev->grf_base,
2090 RK3366_GRF_SOC_CON0,
2091 LVDS_SOURCE_SEL(dev_drv->id));
2094 if (screen->color_mode == COLOR_RGB)
2095 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
2097 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
2098 mask = m_HDMI_OUT_EN | m_RGB_OUT_EN;
2099 val = v_HDMI_OUT_EN(1) | v_RGB_OUT_EN(0);
2100 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2101 mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
2102 m_HDMI_DEN_POL | m_HDMI_DCLK_POL;
2103 val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
2104 v_HDMI_VSYNC_POL(screen->pin_vsync) |
2105 v_HDMI_DEN_POL(screen->pin_den) |
2106 v_HDMI_DCLK_POL(screen->pin_dclk);
2107 if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
2108 lcdc_grf_writel(lcdc_dev->grf_base,
2109 RK3366_GRF_SOC_CON0,
2110 HDMI_SOURCE_SEL(dev_drv->id));
2114 mask = m_MIPI_OUT_EN | m_RGB_OUT_EN;
2115 val = v_MIPI_OUT_EN(1) | v_RGB_OUT_EN(0);
2116 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2117 mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
2118 m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
2119 val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
2120 v_MIPI_VSYNC_POL(screen->pin_vsync) |
2121 v_MIPI_DEN_POL(screen->pin_den) |
2122 v_MIPI_DCLK_POL(screen->pin_dclk);
2123 if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
2124 lcdc_grf_writel(lcdc_dev->grf_base,
2125 RK3366_GRF_SOC_CON0,
2126 MIPI_SOURCE_SEL(dev_drv->id));
2129 case SCREEN_DUAL_MIPI:
2130 mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN |
2132 val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1) |
2134 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2135 mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
2136 m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
2137 val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
2138 v_MIPI_VSYNC_POL(screen->pin_vsync) |
2139 v_MIPI_DEN_POL(screen->pin_den) |
2140 v_MIPI_DCLK_POL(screen->pin_dclk);
2143 face = OUT_P888; /*RGB 888 output */
2145 mask = m_EDP_OUT_EN | m_RGB_OUT_EN;
2146 val = v_EDP_OUT_EN(1) | v_RGB_OUT_EN(0);
2147 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2149 mask = m_EDP_HSYNC_POL | m_EDP_VSYNC_POL |
2150 m_EDP_DEN_POL | m_EDP_DCLK_POL;
2151 val = v_EDP_HSYNC_POL(screen->pin_hsync) |
2152 v_EDP_VSYNC_POL(screen->pin_vsync) |
2153 v_EDP_DEN_POL(screen->pin_den) |
2154 v_EDP_DCLK_POL(screen->pin_dclk);
2157 /*hsync vsync den dclk polo,dither */
2158 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2159 mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP |
2160 m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
2161 m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
2162 m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
2163 val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) |
2164 v_DSP_BG_SWAP(screen->swap_gb) |
2165 v_DSP_RB_SWAP(screen->swap_rb) |
2166 v_DSP_RG_SWAP(screen->swap_rg) |
2167 v_DSP_DELTA_SWAP(screen->swap_delta) |
2168 v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
2169 v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
2170 v_DSP_X_MIR_EN(screen->x_mirror) |
2171 v_DSP_Y_MIR_EN(screen->y_mirror);
2172 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
2174 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
2175 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN)
2176 val = v_DSP_BG_BLUE(0x80) | v_DSP_BG_GREEN(0x10) |
2179 val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) |
2181 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
2182 dev_drv->output_color = screen->color_mode;
2183 if (screen->dsp_lut == NULL)
2184 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2187 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2189 rk3368_lcdc_bcsh_path_sel(dev_drv);
2190 rk3368_config_timing(dev_drv);
2191 if (lcdc_dev->soc_type == VOP_FULL_RK3366)
2192 lcdc_cfg_done(lcdc_dev);
2194 spin_unlock(&lcdc_dev->reg_lock);
2195 rk3368_lcdc_set_dclk(dev_drv, 1);
2196 if (screen->type != SCREEN_HDMI &&
2197 screen->type != SCREEN_TVOUT &&
2198 dev_drv->trsm_ops &&
2199 dev_drv->trsm_ops->enable)
2200 dev_drv->trsm_ops->enable();
2203 /*if (!lcdc_dev->standby)
2204 lcdc_msk_reg(lcdc_dev, SYS_CTRL,
2205 m_STANDBY_EN, v_STANDBY_EN(0));*/
2210 /*enable layer,open:1,enable;0 disable*/
2211 static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev,
2212 unsigned int win_id, bool open)
2214 spin_lock(&lcdc_dev->reg_lock);
2215 if (likely(lcdc_dev->clk_on) &&
2216 lcdc_dev->driver.win[win_id]->state != open) {
2218 if (!lcdc_dev->atv_layer_cnt) {
2219 dev_info(lcdc_dev->dev,
2220 "wakeup from standby!\n");
2221 lcdc_dev->standby = 0;
2223 lcdc_dev->atv_layer_cnt |= (1 << win_id);
2225 if (lcdc_dev->atv_layer_cnt & (1 << win_id))
2226 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
2228 lcdc_dev->driver.win[win_id]->state = open;
2230 /*rk3368_lcdc_reg_update(dev_drv);*/
2231 rk3368_lcdc_layer_update_regs
2232 (lcdc_dev, lcdc_dev->driver.win[win_id]);
2233 lcdc_cfg_done(lcdc_dev);
2235 /*if no layer used,disable lcdc */
2236 if (!lcdc_dev->atv_layer_cnt) {
2237 dev_info(lcdc_dev->dev,
2238 "no layer is used,go to standby!\n");
2239 lcdc_dev->standby = 1;
2242 spin_unlock(&lcdc_dev->reg_lock);
2245 static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
2247 struct lcdc_device *lcdc_dev = container_of(dev_drv,
2248 struct lcdc_device, driver);
2250 /*struct rk_screen *screen = dev_drv->cur_screen; */
2251 u32 intr_en_reg, intr_clr_reg;
2253 if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
2254 intr_clr_reg = INTR_CLEAR_RK3366;
2255 intr_en_reg = INTR_EN_RK3366;
2257 intr_clr_reg = INTR_CLEAR_RK3368;
2258 intr_en_reg = INTR_EN_RK3368;
2261 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
2262 m_LINE_FLAG1_INTR_CLR;
2263 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
2264 v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1);
2265 lcdc_msk_reg(lcdc_dev, intr_clr_reg, mask, val);
2267 mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN |
2268 m_BUS_ERROR_INTR_EN | m_LINE_FLAG1_INTR_EN;
2269 val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) |
2270 v_BUS_ERROR_INTR_EN(1) | v_LINE_FLAG1_INTR_EN(0);
2271 lcdc_msk_reg(lcdc_dev, intr_en_reg, mask, val);
2272 #ifdef LCDC_IRQ_EMPTY_DEBUG
2273 mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
2274 m_WIN2_EMPTY_INTR_EN |
2275 m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN |
2276 m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN;
2277 val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) |
2278 v_WIN2_EMPTY_INTR_EN(1) |
2279 v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) |
2280 v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1);
2281 lcdc_msk_reg(lcdc_dev, intr_en_reg, mask, val);
2286 static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
2289 struct lcdc_device *lcdc_dev =
2290 container_of(dev_drv, struct lcdc_device, driver);
2291 /*enable clk,when first layer open */
2292 if ((open) && (!lcdc_dev->atv_layer_cnt)) {
2293 /*rockchip_set_system_status(sys_status);*/
2294 rk3368_lcdc_pre_init(dev_drv);
2295 rk3368_lcdc_clk_enable(lcdc_dev);
2296 rk3368_lcdc_enable_irq(dev_drv);
2297 if (dev_drv->iommu_enabled) {
2298 if (!dev_drv->mmu_dev) {
2300 rk_fb_get_sysmmu_device_by_compatible
2301 (dev_drv->mmu_dts_name);
2302 if (dev_drv->mmu_dev) {
2303 rk_fb_platform_set_sysmmu
2304 (dev_drv->mmu_dev, dev_drv->dev);
2306 dev_err(dev_drv->dev,
2307 "fail get rk iommu device\n");
2311 /*if (dev_drv->mmu_dev)
2312 rockchip_iovmm_activate(dev_drv->dev); */
2314 rk3368_lcdc_reg_restore(lcdc_dev);
2315 /*if (dev_drv->iommu_enabled)
2316 rk3368_lcdc_mmu_en(dev_drv); */
2317 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
2318 rk3368_lcdc_set_dclk(dev_drv, 0);
2319 /*rk3368_lcdc_enable_irq(dev_drv);*/
2321 rk3368_load_screen(dev_drv, 1);
2323 if (dev_drv->bcsh.enable)
2324 rk3368_lcdc_set_bcsh(dev_drv, 1);
2325 spin_lock(&lcdc_dev->reg_lock);
2326 if (dev_drv->cur_screen->dsp_lut)
2327 rk3368_lcdc_set_lut(dev_drv,
2328 dev_drv->cur_screen->dsp_lut);
2329 spin_unlock(&lcdc_dev->reg_lock);
2332 if (win_id < ARRAY_SIZE(lcdc_win))
2333 rk3368_lcdc_layer_enable(lcdc_dev, win_id, open);
2335 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
2338 /* when all layer closed,disable clk */
2339 /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
2340 rk3368_lcdc_disable_irq(lcdc_dev);
2341 rk3368_lcdc_reg_update(dev_drv);
2342 if (dev_drv->iommu_enabled) {
2343 if (dev_drv->mmu_dev)
2344 rockchip_iovmm_deactivate(dev_drv->dev);
2346 rk3368_lcdc_clk_disable(lcdc_dev);
2347 #ifndef CONFIG_RK_FPGA
2348 rockchip_clear_system_status(sys_status);
2351 dev_drv->first_frame = 0;
2355 static int win_0_1_display(struct lcdc_device *lcdc_dev,
2356 struct rk_lcdc_win *win)
2362 off = win->id * 0x40;
2363 /*win->smem_start + win->y_offset; */
2364 y_addr = win->area[0].smem_start + win->area[0].y_offset;
2365 uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
2366 DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
2367 lcdc_dev->id, win->id, y_addr, uv_addr);
2368 DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
2369 win->area[0].y_offset, win->area[0].c_offset);
2370 spin_lock(&lcdc_dev->reg_lock);
2371 if (likely(lcdc_dev->clk_on)) {
2372 win->area[0].y_addr = y_addr;
2373 win->area[0].uv_addr = uv_addr;
2374 lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
2375 lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
2376 if (win->area[0].fbdc_en == 1)
2377 lcdc_writel(lcdc_dev, IFBDC_BASE_ADDR,
2378 win->area[0].y_addr);
2380 spin_unlock(&lcdc_dev->reg_lock);
2385 static int win_2_3_display(struct lcdc_device *lcdc_dev,
2386 struct rk_lcdc_win *win)
2391 off = (win->id - 2) * 0x50;
2392 y_addr = win->area[0].smem_start + win->area[0].y_offset;
2393 DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id);
2395 spin_lock(&lcdc_dev->reg_lock);
2396 if (likely(lcdc_dev->clk_on)) {
2397 for (i = 0; i < win->area_num; i++) {
2398 DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2399 i, win->area[i].y_addr, win->area[i].y_offset);
2400 win->area[i].y_addr =
2401 win->area[i].smem_start + win->area[i].y_offset;
2403 lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr);
2404 lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr);
2405 lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr);
2406 lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr);
2407 if (win->area[0].fbdc_en == 1)
2408 lcdc_writel(lcdc_dev, IFBDC_BASE_ADDR,
2409 win->area[0].y_addr);
2411 spin_unlock(&lcdc_dev->reg_lock);
2415 static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win)
2419 y_addr = win->area[0].smem_start + win->area[0].y_offset;
2420 DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2421 lcdc_dev->id, __func__, y_addr);
2422 spin_lock(&lcdc_dev->reg_lock);
2423 if (likely(lcdc_dev->clk_on)) {
2424 win->area[0].y_addr = y_addr;
2425 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
2427 spin_unlock(&lcdc_dev->reg_lock);
2432 static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2434 struct lcdc_device *lcdc_dev =
2435 container_of(dev_drv, struct lcdc_device, driver);
2436 struct rk_lcdc_win *win = NULL;
2437 struct rk_screen *screen = dev_drv->cur_screen;
2439 #if defined(WAIT_FOR_SYNC)
2441 unsigned long flags;
2443 win = dev_drv->win[win_id];
2445 dev_err(dev_drv->dev, "screen is null!\n");
2448 if (unlikely(!lcdc_dev->clk_on)) {
2449 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
2453 win_0_1_display(lcdc_dev, win);
2454 } else if (win_id == 1) {
2455 win_0_1_display(lcdc_dev, win);
2456 } else if (win_id == 2) {
2457 win_2_3_display(lcdc_dev, win);
2458 } else if (win_id == 3) {
2459 win_2_3_display(lcdc_dev, win);
2460 } else if (win_id == 4) {
2461 hwc_display(lcdc_dev, win);
2463 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2467 #if defined(WAIT_FOR_SYNC)
2468 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
2469 init_completion(&dev_drv->frame_done);
2470 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
2472 wait_for_completion_timeout(&dev_drv->frame_done,
2473 msecs_to_jiffies(dev_drv->
2474 cur_screen->ft + 5));
2475 if (!timeout && (!dev_drv->frame_done.done)) {
2476 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
2483 static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win,
2484 struct rk_screen *screen)
2494 u32 yrgb_vscalednmult = 0;
2495 u32 yrgb_xscl_factor = 0;
2496 u32 yrgb_yscl_factor = 0;
2497 u8 yrgb_vsd_bil_gt2 = 0;
2498 u8 yrgb_vsd_bil_gt4 = 0;
2504 u32 cbcr_vscalednmult = 0;
2505 u32 cbcr_xscl_factor = 0;
2506 u32 cbcr_yscl_factor = 0;
2507 u8 cbcr_vsd_bil_gt2 = 0;
2508 u8 cbcr_vsd_bil_gt4 = 0;
2511 srcW = win->area[0].xact;
2512 if ((screen->mode.vmode & FB_VMODE_INTERLACED) &&
2513 (win->area[0].yact == 2 * win->area[0].ysize)) {
2514 srcH = win->area[0].yact / 2;
2515 yrgb_vsd_bil_gt2 = 1;
2516 cbcr_vsd_bil_gt2 = 1;
2518 srcH = win->area[0].yact;
2520 dstW = win->area[0].xsize;
2521 dstH = win->area[0].ysize;
2528 if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2529 pr_err("ERROR: yrgb scale exceed 8,");
2530 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2531 yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2533 if (yrgb_srcW < yrgb_dstW)
2534 win->yrgb_hor_scl_mode = SCALE_UP;
2535 else if (yrgb_srcW > yrgb_dstW)
2536 win->yrgb_hor_scl_mode = SCALE_DOWN;
2538 win->yrgb_hor_scl_mode = SCALE_NONE;
2540 if (yrgb_srcH < yrgb_dstH)
2541 win->yrgb_ver_scl_mode = SCALE_UP;
2542 else if (yrgb_srcH > yrgb_dstH)
2543 win->yrgb_ver_scl_mode = SCALE_DOWN;
2545 win->yrgb_ver_scl_mode = SCALE_NONE;
2548 switch (win->area[0].format) {
2551 cbcr_srcW = srcW / 2;
2560 cbcr_srcW = srcW / 2;
2562 cbcr_srcH = srcH / 2;
2583 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2584 (cbcr_dstH * 8 <= cbcr_srcH)) {
2585 pr_err("ERROR: cbcr scale exceed 8,");
2586 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2587 cbcr_srcH, cbcr_dstW, cbcr_dstH);
2591 if (cbcr_srcW < cbcr_dstW)
2592 win->cbr_hor_scl_mode = SCALE_UP;
2593 else if (cbcr_srcW > cbcr_dstW)
2594 win->cbr_hor_scl_mode = SCALE_DOWN;
2596 win->cbr_hor_scl_mode = SCALE_NONE;
2598 if (cbcr_srcH < cbcr_dstH)
2599 win->cbr_ver_scl_mode = SCALE_UP;
2600 else if (cbcr_srcH > cbcr_dstH)
2601 win->cbr_ver_scl_mode = SCALE_DOWN;
2603 win->cbr_ver_scl_mode = SCALE_NONE;
2605 /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
2606 "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
2607 "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW,
2608 srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH,
2609 win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW,
2610 cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode,
2611 win->cbr_ver_scl_mode);*/
2613 /*line buffer mode */
2614 if ((win->area[0].format == YUV422) ||
2615 (win->area[0].format == YUV420) ||
2616 (win->area[0].format == YUV420_NV21) ||
2617 (win->area[0].format == YUV422_A) ||
2618 (win->area[0].format == YUV420_A)) {
2619 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2620 if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2622 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2624 else if (cbcr_dstW > 1280)
2625 win->win_lb_mode = LB_YUV_3840X5;
2627 win->win_lb_mode = LB_YUV_2560X8;
2628 } else { /*SCALE_UP or SCALE_NONE */
2629 if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2631 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2633 else if (cbcr_srcW > 1280)
2634 win->win_lb_mode = LB_YUV_3840X5;
2636 win->win_lb_mode = LB_YUV_2560X8;
2639 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2640 if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2642 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2643 else if (yrgb_dstW > 2560)
2644 win->win_lb_mode = LB_RGB_3840X2;
2645 else if (yrgb_dstW > 1920)
2646 win->win_lb_mode = LB_RGB_2560X4;
2647 else if (yrgb_dstW > 1280)
2648 win->win_lb_mode = LB_RGB_1920X5;
2650 win->win_lb_mode = LB_RGB_1280X8;
2651 } else { /*SCALE_UP or SCALE_NONE */
2652 if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2654 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2655 else if (yrgb_srcW > 2560)
2656 win->win_lb_mode = LB_RGB_3840X2;
2657 else if (yrgb_srcW > 1920)
2658 win->win_lb_mode = LB_RGB_2560X4;
2659 else if (yrgb_srcW > 1280)
2660 win->win_lb_mode = LB_RGB_1920X5;
2662 win->win_lb_mode = LB_RGB_1280X8;
2665 DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2667 /*vsd/vsu scale ALGORITHM */
2668 win->yrgb_hsd_mode = SCALE_DOWN_BIL; /*not to specify */
2669 win->cbr_hsd_mode = SCALE_DOWN_BIL; /*not to specify */
2670 win->yrgb_vsd_mode = SCALE_DOWN_BIL; /*not to specify */
2671 win->cbr_vsd_mode = SCALE_DOWN_BIL; /*not to specify */
2672 switch (win->win_lb_mode) {
2677 win->yrgb_vsu_mode = SCALE_UP_BIC;
2678 win->cbr_vsu_mode = SCALE_UP_BIC;
2681 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2682 pr_err("ERROR : not allow yrgb ver scale\n");
2683 if (win->cbr_ver_scl_mode != SCALE_NONE)
2684 pr_err("ERROR : not allow cbcr ver scale\n");
2687 win->yrgb_vsu_mode = SCALE_UP_BIL;
2688 win->cbr_vsu_mode = SCALE_UP_BIL;
2691 pr_info("%s:un supported win_lb_mode:%d\n",
2692 __func__, win->win_lb_mode);
2695 if (win->ymirror == 1)
2696 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2698 if (screen->mode.vmode & FB_VMODE_INTERLACED) {
2699 /*interlace mode must bill */
2700 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2701 win->cbr_vsd_mode = SCALE_DOWN_BIL;
2703 if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2704 (win->area[0].fbdc_en == 1)) {
2705 /*in this pattern,use bil mode,not support souble scd,
2706 use avg mode, support double scd, but aclk should be
2707 bigger than dclk,aclk>>dclk */
2708 if (yrgb_srcH >= 2 * yrgb_dstH) {
2709 pr_err("ERROR : fbdc mode,not support y scale down:");
2710 pr_err("srcH[%d] > 2 *dstH[%d]\n",
2711 yrgb_srcH, yrgb_dstH);
2714 DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2715 win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2716 win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2720 /*(1.1)YRGB HOR SCALE FACTOR */
2721 switch (win->yrgb_hor_scl_mode) {
2723 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2726 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2729 switch (win->yrgb_hsd_mode) {
2730 case SCALE_DOWN_BIL:
2732 GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2734 case SCALE_DOWN_AVG:
2736 GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2740 "%s:un supported yrgb_hsd_mode:%d\n", __func__,
2741 win->yrgb_hsd_mode);
2746 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2747 __func__, win->yrgb_hor_scl_mode);
2749 } /*win->yrgb_hor_scl_mode */
2751 /*(1.2)YRGB VER SCALE FACTOR */
2752 switch (win->yrgb_ver_scl_mode) {
2754 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2757 switch (win->yrgb_vsu_mode) {
2760 GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2763 if (yrgb_srcH < 3) {
2764 pr_err("yrgb_srcH should be");
2765 pr_err(" greater than 3 !!!\n");
2767 yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2771 pr_info("%s:un support yrgb_vsu_mode:%d\n",
2772 __func__, win->yrgb_vsu_mode);
2777 switch (win->yrgb_vsd_mode) {
2778 case SCALE_DOWN_BIL:
2780 rk3368_get_hard_ware_vskiplines(yrgb_srcH,
2783 GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2785 if (yrgb_yscl_factor >= 0x2000) {
2786 pr_err("yrgb_yscl_factor should be ");
2787 pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n",
2790 if (yrgb_vscalednmult == 4) {
2791 yrgb_vsd_bil_gt4 = 1;
2792 yrgb_vsd_bil_gt2 = 0;
2793 } else if (yrgb_vscalednmult == 2) {
2794 yrgb_vsd_bil_gt4 = 0;
2795 yrgb_vsd_bil_gt2 = 1;
2797 yrgb_vsd_bil_gt4 = 0;
2798 yrgb_vsd_bil_gt2 = 0;
2801 case SCALE_DOWN_AVG:
2802 yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2806 pr_info("%s:un support yrgb_vsd_mode:%d\n",
2807 __func__, win->yrgb_vsd_mode);
2809 } /*win->yrgb_vsd_mode */
2812 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2813 __func__, win->yrgb_ver_scl_mode);
2816 win->scale_yrgb_x = yrgb_xscl_factor;
2817 win->scale_yrgb_y = yrgb_yscl_factor;
2818 win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2819 win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2820 DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2821 yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2823 /*(2.1)CBCR HOR SCALE FACTOR */
2824 switch (win->cbr_hor_scl_mode) {
2826 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2829 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2832 switch (win->cbr_hsd_mode) {
2833 case SCALE_DOWN_BIL:
2835 GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2837 case SCALE_DOWN_AVG:
2839 GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2842 pr_info("%s:un support cbr_hsd_mode:%d\n",
2843 __func__, win->cbr_hsd_mode);
2848 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2849 __func__, win->cbr_hor_scl_mode);
2851 } /*win->cbr_hor_scl_mode */
2853 /*(2.2)CBCR VER SCALE FACTOR */
2854 switch (win->cbr_ver_scl_mode) {
2856 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2859 switch (win->cbr_vsu_mode) {
2862 GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2865 if (cbcr_srcH < 3) {
2866 pr_err("cbcr_srcH should be ");
2867 pr_err("greater than 3 !!!\n");
2869 cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2873 pr_info("%s:un support cbr_vsu_mode:%d\n",
2874 __func__, win->cbr_vsu_mode);
2879 switch (win->cbr_vsd_mode) {
2880 case SCALE_DOWN_BIL:
2882 rk3368_get_hard_ware_vskiplines(cbcr_srcH,
2885 GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2887 if (cbcr_yscl_factor >= 0x2000) {
2888 pr_err("cbcr_yscl_factor should be less ");
2889 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2893 if (cbcr_vscalednmult == 4) {
2894 cbcr_vsd_bil_gt4 = 1;
2895 cbcr_vsd_bil_gt2 = 0;
2896 } else if (cbcr_vscalednmult == 2) {
2897 cbcr_vsd_bil_gt4 = 0;
2898 cbcr_vsd_bil_gt2 = 1;
2900 cbcr_vsd_bil_gt4 = 0;
2901 cbcr_vsd_bil_gt2 = 0;
2904 case SCALE_DOWN_AVG:
2905 cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2909 pr_info("%s:un support cbr_vsd_mode:%d\n",
2910 __func__, win->cbr_vsd_mode);
2915 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2916 __func__, win->cbr_ver_scl_mode);
2919 win->scale_cbcr_x = cbcr_xscl_factor;
2920 win->scale_cbcr_y = cbcr_yscl_factor;
2921 win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2922 win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2924 DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2925 cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2929 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2930 struct rk_lcdc_win_area *area)
2934 if (screen->x_mirror && mirror_en)
2935 pr_err("not support both win and global mirror\n");
2937 if ((!mirror_en) && (!screen->x_mirror))
2938 pos = area->xpos + screen->mode.left_margin +
2939 screen->mode.hsync_len;
2941 pos = screen->mode.xres - area->xpos -
2942 area->xsize + screen->mode.left_margin +
2943 screen->mode.hsync_len;
2948 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2949 struct rk_lcdc_win_area *area)
2953 if (screen->y_mirror && mirror_en)
2954 pr_err("not support both win and global mirror\n");
2955 if (!(screen->mode.vmode & FB_VMODE_INTERLACED)) {
2956 if ((!mirror_en) && (!screen->y_mirror))
2957 pos = area->ypos + screen->mode.upper_margin +
2958 screen->mode.vsync_len;
2960 pos = screen->mode.yres - area->ypos -
2961 area->ysize + screen->mode.upper_margin +
2962 screen->mode.vsync_len;
2964 pos = area->ypos / 2 + screen->mode.upper_margin +
2965 screen->mode.vsync_len;
2972 static int win_0_1_set_par(struct lcdc_device *lcdc_dev,
2973 struct rk_screen *screen, struct rk_lcdc_win *win)
2975 u32 xact = 0, yact = 0, xvir = 0, yvir = 0, xpos = 0, ypos = 0;
2976 u8 fmt_cfg = 0, swap_rb = 0, swap_uv = 0;
2977 char fmt[9] = "NULL";
2979 xpos = dsp_x_pos(win->xmirror, screen, &win->area[0]);
2980 ypos = dsp_y_pos(win->ymirror, screen, &win->area[0]);
2982 spin_lock(&lcdc_dev->reg_lock);
2983 if (likely(lcdc_dev->clk_on)) {
2984 rk3368_lcdc_cal_scl_fac(win, screen); /*fac,lb,gt2,gt4 */
2985 switch (win->area[0].format) {
2990 win->area[0].fbdc_fmt_cfg = 0x05;
2996 win->area[0].fbdc_fmt_cfg = 0x0c;
3002 win->area[0].fbdc_fmt_cfg = 0x0c;
3008 win->area[0].fbdc_fmt_cfg = 0x3a;
3073 dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n",
3077 win->area[0].fmt_cfg = fmt_cfg;
3078 win->area[0].swap_rb = swap_rb;
3079 win->area[0].swap_uv = swap_uv;
3080 win->area[0].dsp_stx = xpos;
3081 win->area[0].dsp_sty = ypos;
3082 xact = win->area[0].xact;
3083 yact = win->area[0].yact;
3084 xvir = win->area[0].xvir;
3085 yvir = win->area[0].yvir;
3087 if (win->area[0].fbdc_en)
3088 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
3089 rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id);
3090 spin_unlock(&lcdc_dev->reg_lock);
3092 DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
3093 lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt),
3094 xact, yact, win->area[0].xsize);
3095 DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
3096 win->area[0].ysize, xvir, yvir, xpos, ypos);
3102 static int win_2_3_set_par(struct lcdc_device *lcdc_dev,
3103 struct rk_screen *screen, struct rk_lcdc_win *win)
3106 u8 fmt_cfg = 0, swap_rb = 0;
3107 char fmt[9] = "NULL";
3110 pr_err("win[%d] not support y mirror\n", win->id);
3111 spin_lock(&lcdc_dev->reg_lock);
3112 if (likely(lcdc_dev->clk_on)) {
3113 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id);
3114 for (i = 0; i < win->area_num; i++) {
3115 switch (win->area[i].format) {
3120 win->area[0].fbdc_fmt_cfg = 0x05;
3126 win->area[0].fbdc_fmt_cfg = 0x0c;
3132 win->area[0].fbdc_fmt_cfg = 0x3a;
3152 dev_err(lcdc_dev->driver.dev,
3153 "%s:un supported format!\n", __func__);
3156 win->area[i].fmt_cfg = fmt_cfg;
3157 win->area[i].swap_rb = swap_rb;
3158 win->area[i].dsp_stx =
3159 dsp_x_pos(win->xmirror, screen,
3161 win->area[i].dsp_sty =
3162 dsp_y_pos(win->ymirror, screen,
3164 if (((win->area[i].xact != win->area[i].xsize) ||
3165 (win->area[i].yact != win->area[i].ysize)) &&
3166 !(screen->mode.vmode & FB_VMODE_INTERLACED)) {
3167 pr_err("win[%d]->area[%d],not support scale\n",
3169 pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
3170 win->area[i].xact, win->area[i].yact,
3171 win->area[i].xsize, win->area[i].ysize);
3172 win->area[i].xsize = win->area[i].xact;
3173 win->area[i].ysize = win->area[i].yact;
3175 DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
3176 get_format_string(win->area[i].format, fmt),
3177 win->area[i].xsize, win->area[i].ysize,
3178 win->area[i].xpos, win->area[i].ypos);
3181 if (win->area[0].fbdc_en)
3182 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
3183 rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id);
3184 spin_unlock(&lcdc_dev->reg_lock);
3188 static int hwc_set_par(struct lcdc_device *lcdc_dev,
3189 struct rk_screen *screen, struct rk_lcdc_win *win)
3191 u32 xact = 0, yact = 0, xvir = 0, yvir = 0, xpos = 0, ypos = 0;
3192 u8 fmt_cfg = 0, swap_rb = 0;
3193 char fmt[9] = "NULL";
3195 xpos = win->area[0].xpos + screen->mode.left_margin +
3196 screen->mode.hsync_len;
3197 ypos = win->area[0].ypos + screen->mode.upper_margin +
3198 screen->mode.vsync_len;
3200 spin_lock(&lcdc_dev->reg_lock);
3201 if (likely(lcdc_dev->clk_on)) {
3202 /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */
3203 switch (win->area[0].format) {
3222 dev_err(lcdc_dev->driver.dev,
3223 "%s:un supported format!\n", __func__);
3226 win->area[0].fmt_cfg = fmt_cfg;
3227 win->area[0].swap_rb = swap_rb;
3228 win->area[0].dsp_stx = xpos;
3229 win->area[0].dsp_sty = ypos;
3230 xact = win->area[0].xact;
3231 yact = win->area[0].yact;
3232 xvir = win->area[0].xvir;
3233 yvir = win->area[0].yvir;
3235 rk3368_hwc_reg_update(&lcdc_dev->driver, 4);
3236 spin_unlock(&lcdc_dev->reg_lock);
3238 DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
3239 lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt),
3240 xact, yact, win->area[0].xsize);
3241 DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
3242 win->area[0].ysize, xvir, yvir, xpos, ypos);
3246 static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
3248 struct lcdc_device *lcdc_dev =
3249 container_of(dev_drv, struct lcdc_device, driver);
3250 struct rk_lcdc_win *win = NULL;
3251 struct rk_screen *screen = dev_drv->cur_screen;
3253 if (unlikely(!lcdc_dev->clk_on)) {
3254 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
3257 win = dev_drv->win[win_id];
3260 win_0_1_set_par(lcdc_dev, screen, win);
3263 win_0_1_set_par(lcdc_dev, screen, win);
3266 win_2_3_set_par(lcdc_dev, screen, win);
3269 win_2_3_set_par(lcdc_dev, screen, win);
3272 hwc_set_par(lcdc_dev, screen, win);
3275 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
3281 static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
3282 unsigned long arg, int win_id)
3284 struct lcdc_device *lcdc_dev =
3285 container_of(dev_drv, struct lcdc_device, driver);
3287 void __user *argp = (void __user *)arg;
3288 struct color_key_cfg clr_key_cfg;
3291 case RK_FBIOGET_PANEL_SIZE:
3292 panel_size[0] = lcdc_dev->screen->mode.xres;
3293 panel_size[1] = lcdc_dev->screen->mode.yres;
3294 if (copy_to_user(argp, panel_size, 8))
3297 case RK_FBIOPUT_COLOR_KEY_CFG:
3298 if (copy_from_user(&clr_key_cfg, argp,
3299 sizeof(struct color_key_cfg)))
3301 rk3368_lcdc_clr_key_cfg(dev_drv);
3302 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
3303 clr_key_cfg.win0_color_key_cfg);
3304 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
3305 clr_key_cfg.win1_color_key_cfg);
3314 static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
3316 struct lcdc_device *lcdc_dev = container_of(dev_drv,
3317 struct lcdc_device, driver);
3318 struct device_node *backlight;
3319 struct property *prop;
3320 u32 brightness_levels[256];
3321 u32 length, max, last;
3323 if (lcdc_dev->backlight)
3325 backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0);
3327 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
3328 if (!lcdc_dev->backlight)
3329 dev_info(lcdc_dev->dev, "No find backlight device\n");
3331 dev_info(lcdc_dev->dev, "No find backlight device node\n");
3333 prop = of_find_property(backlight, "brightness-levels", &length);
3336 max = length / sizeof(u32);
3338 if (!of_property_read_u32_array(backlight, "brightness-levels",
3339 brightness_levels, max)) {
3340 if (brightness_levels[0] > brightness_levels[last])
3341 dev_drv->cabc_pwm_pol = 1;/*negative*/
3343 dev_drv->cabc_pwm_pol = 0;/*positive*/
3345 dev_info(lcdc_dev->dev, "Can not read brightness-levels value\n");
3350 static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
3352 struct lcdc_device *lcdc_dev =
3353 container_of(dev_drv, struct lcdc_device, driver);
3356 if (lcdc_dev->soc_type == VOP_FULL_RK3366)
3357 intr_clr_reg = INTR_CLEAR_RK3366;
3359 intr_clr_reg = INTR_CLEAR_RK3368;
3361 if (dev_drv->suspend_flag)
3363 /* close the backlight */
3364 /*rk3368_lcdc_get_backlight_device(dev_drv);
3365 if (lcdc_dev->backlight) {
3366 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
3367 backlight_update_status(lcdc_dev->backlight);
3370 dev_drv->suspend_flag = 1;
3371 flush_kthread_worker(&dev_drv->update_regs_worker);
3373 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3374 dev_drv->trsm_ops->disable();
3376 spin_lock(&lcdc_dev->reg_lock);
3377 if (likely(lcdc_dev->clk_on)) {
3378 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3380 lcdc_msk_reg(lcdc_dev,
3381 intr_clr_reg, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR,
3382 v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1));
3383 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3385 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
3386 lcdc_cfg_done(lcdc_dev);
3388 if (dev_drv->iommu_enabled) {
3389 if (dev_drv->mmu_dev)
3390 rockchip_iovmm_deactivate(dev_drv->dev);
3393 spin_unlock(&lcdc_dev->reg_lock);
3395 spin_unlock(&lcdc_dev->reg_lock);
3398 rk3368_lcdc_clk_disable(lcdc_dev);
3399 rk_disp_pwr_disable(dev_drv);
3403 static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
3405 struct lcdc_device *lcdc_dev =
3406 container_of(dev_drv, struct lcdc_device, driver);
3408 if (!dev_drv->suspend_flag)
3410 rk_disp_pwr_enable(dev_drv);
3412 if (1/*lcdc_dev->atv_layer_cnt*/) {
3413 rk3368_lcdc_clk_enable(lcdc_dev);
3414 rk3368_lcdc_reg_restore(lcdc_dev);
3416 spin_lock(&lcdc_dev->reg_lock);
3417 if (dev_drv->cur_screen->dsp_lut)
3418 rk3368_lcdc_set_lut(dev_drv,
3419 dev_drv->cur_screen->dsp_lut);
3420 if (dev_drv->cur_screen->cabc_lut && dev_drv->cabc_mode)
3421 rk3368_set_cabc_lut(dev_drv,
3422 dev_drv->cur_screen->cabc_lut);
3424 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3426 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
3427 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3429 lcdc_cfg_done(lcdc_dev);
3431 if (dev_drv->iommu_enabled) {
3432 /* win address maybe effect after next frame start,
3433 * but mmu maybe effect right now, so we delay 50ms
3436 if (dev_drv->mmu_dev)
3437 rockchip_iovmm_activate(dev_drv->dev);
3440 spin_unlock(&lcdc_dev->reg_lock);
3442 dev_drv->suspend_flag = 0;
3444 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3445 dev_drv->trsm_ops->enable();
3450 static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv,
3451 int win_id, int blank_mode)
3453 switch (blank_mode) {
3454 case FB_BLANK_UNBLANK:
3455 rk3368_lcdc_early_resume(dev_drv);
3457 case FB_BLANK_NORMAL:
3458 rk3368_lcdc_early_suspend(dev_drv);
3461 rk3368_lcdc_early_suspend(dev_drv);
3465 dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
3470 static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv,
3471 int win_id, int area_id)
3473 struct lcdc_device *lcdc_dev =
3474 container_of(dev_drv, struct lcdc_device, driver);
3476 u32 area_status = 0, state = 0;
3480 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3481 area_status = win_ctrl & m_WIN0_EN;
3484 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3485 area_status = win_ctrl & m_WIN1_EN;
3488 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3490 area_status = win_ctrl & (m_WIN2_MST0_EN | m_WIN2_EN);
3492 area_status = win_ctrl & m_WIN2_MST1_EN;
3494 area_status = win_ctrl & m_WIN2_MST2_EN;
3496 area_status = win_ctrl & m_WIN2_MST3_EN;
3499 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3501 area_status = win_ctrl & (m_WIN3_MST0_EN | m_WIN3_EN);
3503 area_status = win_ctrl & m_WIN3_MST1_EN;
3505 area_status = win_ctrl & m_WIN3_MST2_EN;
3507 area_status = win_ctrl & m_WIN3_MST3_EN;
3510 win_ctrl = lcdc_readl(lcdc_dev, HWC_CTRL0);
3511 area_status = win_ctrl & m_HWC_EN;
3514 pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n",
3515 __func__, win_id, area_id);
3519 state = (area_status > 0) ? 1 : 0;
3523 static int rk3368_lcdc_get_area_num(struct rk_lcdc_driver *dev_drv,
3524 unsigned int *area_support)
3526 area_support[0] = 1;
3527 area_support[1] = 1;
3528 area_support[2] = 4;
3529 area_support[3] = 4;
3534 /*overlay will be do at regupdate*/
3535 static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
3538 struct lcdc_device *lcdc_dev =
3539 container_of(dev_drv, struct lcdc_device, driver);
3540 struct rk_lcdc_win *win = NULL;
3542 unsigned int mask, val;
3543 int z_order_num = 0;
3544 int layer0_sel = 0, layer1_sel = 1, layer2_sel = 2, layer3_sel = 3;
3547 for (i = 0; i < 4; i++) {
3548 win = dev_drv->win[i];
3549 if (win->state == 1)
3552 for (i = 0; i < 4; i++) {
3553 win = dev_drv->win[i];
3554 if (win->state == 0)
3555 win->z_order = z_order_num++;
3556 switch (win->z_order) {
3558 layer0_sel = win->id;
3561 layer1_sel = win->id;
3564 layer2_sel = win->id;
3567 layer3_sel = win->id;
3574 layer0_sel = swap % 10;
3575 layer1_sel = swap / 10 % 10;
3576 layer2_sel = swap / 100 % 10;
3577 layer3_sel = swap / 1000;
3580 spin_lock(&lcdc_dev->reg_lock);
3581 if (lcdc_dev->clk_on) {
3583 mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
3584 m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
3585 val = v_DSP_LAYER0_SEL(layer0_sel) |
3586 v_DSP_LAYER1_SEL(layer1_sel) |
3587 v_DSP_LAYER2_SEL(layer2_sel) |
3588 v_DSP_LAYER3_SEL(layer3_sel);
3589 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
3591 layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3593 layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3595 layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3597 layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3599 ovl = layer3_sel * 1000 + layer2_sel * 100 +
3600 layer1_sel * 10 + layer0_sel;
3605 spin_unlock(&lcdc_dev->reg_lock);
3610 static char *rk3368_lcdc_format_to_string(int format, char *fmt)
3617 strcpy(fmt, "ARGB888");
3620 strcpy(fmt, "RGB888");
3623 strcpy(fmt, "RGB565");
3626 strcpy(fmt, "YCbCr420");
3629 strcpy(fmt, "YCbCr422");
3632 strcpy(fmt, "YCbCr444");
3635 strcpy(fmt, "invalid\n");
3640 static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
3641 char *buf, int win_id)
3643 struct lcdc_device *lcdc_dev =
3644 container_of(dev_drv, struct lcdc_device, driver);
3645 struct rk_screen *screen = dev_drv->cur_screen;
3646 u16 hsync_len = screen->mode.hsync_len;
3647 u16 left_margin = screen->mode.left_margin;
3648 u16 vsync_len = screen->mode.vsync_len;
3649 u16 upper_margin = screen->mode.upper_margin;
3650 u32 h_pw_bp = hsync_len + left_margin;
3651 u32 v_pw_bp = vsync_len + upper_margin;
3653 char format_w0[9] = "NULL";
3654 char format_w1[9] = "NULL";
3655 char format_w2_0[9] = "NULL";
3656 char format_w2_1[9] = "NULL";
3657 char format_w2_2[9] = "NULL";
3658 char format_w2_3[9] = "NULL";
3659 char format_w3_0[9] = "NULL";
3660 char format_w3_1[9] = "NULL";
3661 char format_w3_2[9] = "NULL";
3662 char format_w3_3[9] = "NULL";
3664 u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3665 u32 y_factor, uv_factor;
3666 u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3667 u8 w0_state, w1_state, w2_state, w3_state;
3668 u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3669 u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3671 u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3672 u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3673 u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3674 u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3675 u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3676 u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3678 u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3679 u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3680 u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3681 u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3682 u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3683 u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3684 u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3686 u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3687 u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3688 u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3689 u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3690 u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3691 u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3692 u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3696 dclk_freq = screen->mode.pixclock;
3697 /*rk3368_lcdc_reg_dump(dev_drv); */
3699 spin_lock(&lcdc_dev->reg_lock);
3700 if (lcdc_dev->clk_on) {
3701 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
3702 layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8;
3703 layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10;
3704 layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12;
3705 layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14;
3707 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3708 w0_state = win_ctrl & m_WIN0_EN;
3709 fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1;
3710 rk3368_lcdc_format_to_string(fmt_id, format_w0);
3711 vir_info = lcdc_readl(lcdc_dev, WIN0_VIR);
3712 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
3713 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
3714 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
3715 y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
3716 uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR);
3717 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
3718 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16;
3719 w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1;
3720 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1;
3721 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1;
3722 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1;
3724 w0_st_x = dsp_st & m_WIN0_DSP_XST;
3725 w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16;
3727 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
3728 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16;
3729 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
3730 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16;
3733 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3734 w1_state = win_ctrl & m_WIN1_EN;
3735 fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1;
3736 rk3368_lcdc_format_to_string(fmt_id, format_w1);
3737 vir_info = lcdc_readl(lcdc_dev, WIN1_VIR);
3738 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
3739 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
3740 dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
3741 y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB);
3742 uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR);
3743 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
3744 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16;
3745 w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1;
3746 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1;
3747 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1;
3748 w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1;
3750 w1_st_x = dsp_st & m_WIN1_DSP_XST;
3751 w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16;
3753 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
3754 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16;
3755 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
3756 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16;
3758 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3759 w2_state = win_ctrl & m_WIN2_EN;
3760 w2_0_state = (win_ctrl & 0x10) >> 4;
3761 w2_1_state = (win_ctrl & 0x100) >> 8;
3762 w2_2_state = (win_ctrl & 0x1000) >> 12;
3763 w2_3_state = (win_ctrl & 0x10000) >> 16;
3764 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1);
3765 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3766 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16;
3767 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3);
3768 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3769 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16;
3771 fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1;
3772 rk3368_lcdc_format_to_string(fmt_id, format_w2_0);
3773 fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1;
3774 rk3368_lcdc_format_to_string(fmt_id, format_w2_1);
3775 fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1;
3776 rk3368_lcdc_format_to_string(fmt_id, format_w2_2);
3777 fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1;
3778 rk3368_lcdc_format_to_string(fmt_id, format_w2_3);
3780 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0);
3781 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0);
3782 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1;
3783 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1;
3785 w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3786 w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16;
3788 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1);
3789 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1);
3790 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1;
3791 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1;
3793 w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3794 w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16;
3796 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2);
3797 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2);
3798 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1;
3799 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1;
3801 w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3802 w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16;
3804 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3);
3805 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3);
3806 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1;
3807 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1;
3809 w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3810 w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16;
3814 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3815 w3_state = win_ctrl & m_WIN3_EN;
3816 w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4;
3817 w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 8;
3818 w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 12;
3819 w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 16;
3820 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1);
3821 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3822 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16;
3823 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3);
3824 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3825 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16;
3826 fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1;
3827 rk3368_lcdc_format_to_string(fmt_id, format_w3_0);
3828 fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1;
3829 rk3368_lcdc_format_to_string(fmt_id, format_w3_1);
3830 fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1;
3831 rk3368_lcdc_format_to_string(fmt_id, format_w3_2);
3832 fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1;
3833 rk3368_lcdc_format_to_string(fmt_id, format_w3_3);
3834 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0);
3835 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0);
3836 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1;
3837 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1;
3839 w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3840 w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16;
3843 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1);
3844 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1);
3845 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1;
3846 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1;
3848 w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3849 w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16;
3852 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2);
3853 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2);
3854 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1;
3855 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1;
3857 w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3858 w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16;
3861 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3);
3862 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3);
3863 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1;
3864 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1;
3866 w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3867 w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16;
3871 spin_unlock(&lcdc_dev->reg_lock);
3874 spin_unlock(&lcdc_dev->reg_lock);
3875 size += snprintf(dsp_buf, 80,
3876 "z-order:\n win[%d]\n win[%d]\n win[%d]\n win[%d]\n",
3877 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3878 strcat(buf, dsp_buf);
3879 memset(dsp_buf, 0, sizeof(dsp_buf));
3881 size += snprintf(dsp_buf, 80,
3882 "win0:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,",
3883 w0_state, format_w0, w0_vir_y, w0_vir_uv);
3884 strcat(buf, dsp_buf);
3885 memset(dsp_buf, 0, sizeof(dsp_buf));
3887 size += snprintf(dsp_buf, 80,
3888 " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n",
3889 w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3890 strcat(buf, dsp_buf);
3891 memset(dsp_buf, 0, sizeof(dsp_buf));
3893 size += snprintf(dsp_buf, 80,
3894 " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3895 w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3896 strcat(buf, dsp_buf);
3897 memset(dsp_buf, 0, sizeof(dsp_buf));
3899 size += snprintf(dsp_buf, 80,
3900 "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n",
3901 w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3902 lcdc_readl(lcdc_dev, WIN0_CBR_MST));
3903 strcat(buf, dsp_buf);
3904 memset(dsp_buf, 0, sizeof(dsp_buf));
3907 size += snprintf(dsp_buf, 80,
3908 "win1:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,",
3909 w1_state, format_w1, w1_vir_y, w1_vir_uv);
3910 strcat(buf, dsp_buf);
3911 memset(dsp_buf, 0, sizeof(dsp_buf));
3913 size += snprintf(dsp_buf, 80,
3914 " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n",
3915 w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3916 strcat(buf, dsp_buf);
3917 memset(dsp_buf, 0, sizeof(dsp_buf));
3919 size += snprintf(dsp_buf, 80,
3920 " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3921 w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3922 strcat(buf, dsp_buf);
3923 memset(dsp_buf, 0, sizeof(dsp_buf));
3925 size += snprintf(dsp_buf, 80,
3926 "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n",
3927 w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3928 lcdc_readl(lcdc_dev, WIN1_CBR_MST));
3929 strcat(buf, dsp_buf);
3930 memset(dsp_buf, 0, sizeof(dsp_buf));
3933 size += snprintf(dsp_buf, 80,
3934 "win2:\n state:%d\n",
3936 strcat(buf, dsp_buf);
3937 memset(dsp_buf, 0, sizeof(dsp_buf));
3939 size += snprintf(dsp_buf, 80,
3940 " area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3941 w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3942 strcat(buf, dsp_buf);
3943 memset(dsp_buf, 0, sizeof(dsp_buf));
3944 size += snprintf(dsp_buf, 80,
3945 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3946 w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3947 lcdc_readl(lcdc_dev, WIN2_MST0));
3948 strcat(buf, dsp_buf);
3949 memset(dsp_buf, 0, sizeof(dsp_buf));
3952 size += snprintf(dsp_buf, 80,
3953 " area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3954 w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3955 strcat(buf, dsp_buf);
3956 memset(dsp_buf, 0, sizeof(dsp_buf));
3957 size += snprintf(dsp_buf, 80,
3958 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3959 w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3960 lcdc_readl(lcdc_dev, WIN2_MST1));
3961 strcat(buf, dsp_buf);
3962 memset(dsp_buf, 0, sizeof(dsp_buf));
3965 size += snprintf(dsp_buf, 80,
3966 " area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3967 w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3968 strcat(buf, dsp_buf);
3969 memset(dsp_buf, 0, sizeof(dsp_buf));
3970 size += snprintf(dsp_buf, 80,
3971 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3972 w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3973 lcdc_readl(lcdc_dev, WIN2_MST2));
3974 strcat(buf, dsp_buf);
3975 memset(dsp_buf, 0, sizeof(dsp_buf));
3978 size += snprintf(dsp_buf, 80,
3979 " area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3980 w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3981 strcat(buf, dsp_buf);
3982 memset(dsp_buf, 0, sizeof(dsp_buf));
3983 size += snprintf(dsp_buf, 80,
3984 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3985 w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3986 lcdc_readl(lcdc_dev, WIN2_MST3));
3987 strcat(buf, dsp_buf);
3988 memset(dsp_buf, 0, sizeof(dsp_buf));
3991 size += snprintf(dsp_buf, 80,
3992 "win3:\n state:%d\n",
3994 strcat(buf, dsp_buf);
3995 memset(dsp_buf, 0, sizeof(dsp_buf));
3997 size += snprintf(dsp_buf, 80,
3998 " area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3999 w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
4000 strcat(buf, dsp_buf);
4001 memset(dsp_buf, 0, sizeof(dsp_buf));
4002 size += snprintf(dsp_buf, 80,
4003 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4004 w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
4005 lcdc_readl(lcdc_dev, WIN3_MST0));
4006 strcat(buf, dsp_buf);
4007 memset(dsp_buf, 0, sizeof(dsp_buf));
4010 size += snprintf(dsp_buf, 80,
4011 " area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4012 w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
4013 strcat(buf, dsp_buf);
4014 memset(dsp_buf, 0, sizeof(dsp_buf));
4015 size += snprintf(dsp_buf, 80,
4016 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4017 w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
4018 lcdc_readl(lcdc_dev, WIN3_MST1));
4019 strcat(buf, dsp_buf);
4020 memset(dsp_buf, 0, sizeof(dsp_buf));
4023 size += snprintf(dsp_buf, 80,
4024 " area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4025 w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
4026 strcat(buf, dsp_buf);
4027 memset(dsp_buf, 0, sizeof(dsp_buf));
4028 size += snprintf(dsp_buf, 80,
4029 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4030 w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
4031 lcdc_readl(lcdc_dev, WIN3_MST2));
4032 strcat(buf, dsp_buf);
4033 memset(dsp_buf, 0, sizeof(dsp_buf));
4036 size += snprintf(dsp_buf, 80,
4037 " area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4038 w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
4039 strcat(buf, dsp_buf);
4040 memset(dsp_buf, 0, sizeof(dsp_buf));
4041 size += snprintf(dsp_buf, 80,
4042 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4043 w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
4044 lcdc_readl(lcdc_dev, WIN3_MST3));
4045 strcat(buf, dsp_buf);
4046 memset(dsp_buf, 0, sizeof(dsp_buf));
4051 static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
4054 struct lcdc_device *lcdc_dev =
4055 container_of(dev_drv, struct lcdc_device, driver);
4056 struct rk_screen *screen = dev_drv->cur_screen;
4061 u32 x_total, y_total;
4065 dev_info(dev_drv->dev, "unsupport set fps=0\n");
4068 ft = div_u64(1000000000000llu, fps);
4070 screen->mode.upper_margin + screen->mode.lower_margin +
4071 screen->mode.yres + screen->mode.vsync_len;
4073 screen->mode.left_margin + screen->mode.right_margin +
4074 screen->mode.xres + screen->mode.hsync_len;
4075 dev_drv->pixclock = div_u64(ft, x_total * y_total);
4076 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
4077 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
4080 pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
4081 lcdc_dev->pixclock = pixclock;
4082 dev_drv->pixclock = lcdc_dev->pixclock;
4083 fps = rk_fb_calc_fps(screen, pixclock);
4084 screen->ft = 1000 / fps; /*one frame time in ms */
4087 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
4088 clk_get_rate(lcdc_dev->dclk), fps);
4093 static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
4095 mutex_lock(&dev_drv->fb_win_id_mutex);
4096 if (order == FB_DEFAULT_ORDER)
4097 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
4098 dev_drv->fb4_win_id = order / 10000;
4099 dev_drv->fb3_win_id = (order / 1000) % 10;
4100 dev_drv->fb2_win_id = (order / 100) % 10;
4101 dev_drv->fb1_win_id = (order / 10) % 10;
4102 dev_drv->fb0_win_id = order % 10;
4103 mutex_unlock(&dev_drv->fb_win_id_mutex);
4108 static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
4113 mutex_lock(&dev_drv->fb_win_id_mutex);
4114 if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
4115 win_id = dev_drv->fb0_win_id;
4116 else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
4117 win_id = dev_drv->fb1_win_id;
4118 else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
4119 win_id = dev_drv->fb2_win_id;
4120 else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
4121 win_id = dev_drv->fb3_win_id;
4122 else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
4123 win_id = dev_drv->fb4_win_id;
4124 mutex_unlock(&dev_drv->fb_win_id_mutex);
4129 static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
4131 struct lcdc_device *lcdc_dev =
4132 container_of(dev_drv, struct lcdc_device, driver);
4134 unsigned int mask, val, fbdc_en = 0;
4135 struct rk_lcdc_win *win = NULL;
4136 u32 line_scane_num, dsp_vs_st_f1;
4138 if (lcdc_dev->driver.cur_screen->mode.vmode & FB_VMODE_INTERLACED) {
4139 dsp_vs_st_f1 = lcdc_readl(lcdc_dev, DSP_VS_ST_END_F1) >> 16;
4140 for (i = 0; i < 1000; i++) {
4142 lcdc_readl(lcdc_dev, SCAN_LINE_NUM) & 0x1fff;
4143 if (line_scane_num > dsp_vs_st_f1 + 1)
4150 spin_lock(&lcdc_dev->reg_lock);
4151 rk3368_lcdc_post_cfg(dev_drv);
4152 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
4153 v_STANDBY_EN(lcdc_dev->standby));
4154 for (i = 0; i < 4; i++) {
4155 win = dev_drv->win[i];
4156 fbdc_en |= win->area[0].fbdc_en;
4157 if ((win->state == 0) && (win->last_state == 1)) {
4160 /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
4161 for rk3288 to fix hw bug? */
4164 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
4167 /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
4168 for rk3288 to fix hw bug? */
4171 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
4174 mask = m_WIN2_EN | m_WIN2_MST0_EN |
4176 m_WIN2_MST2_EN | m_WIN2_MST3_EN;
4177 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
4179 v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
4180 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
4183 mask = m_WIN3_EN | m_WIN3_MST0_EN |
4185 m_WIN3_MST2_EN | m_WIN3_MST3_EN;
4186 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |
4188 v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
4189 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
4194 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
4200 win->last_state = win->state;
4202 if (lcdc_dev->soc_type == VOP_FULL_RK3368) {
4203 mask = m_IFBDC_CTRL_FBDC_EN;
4204 val = v_IFBDC_CTRL_FBDC_EN(fbdc_en);
4205 lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
4207 lcdc_cfg_done(lcdc_dev);
4208 spin_unlock(&lcdc_dev->reg_lock);
4212 static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
4215 struct lcdc_device *lcdc_dev =
4216 container_of(dev_drv, struct lcdc_device, driver);
4218 enable_irq(lcdc_dev->irq);
4220 disable_irq(lcdc_dev->irq);
4224 int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
4226 struct lcdc_device *lcdc_dev =
4227 container_of(dev_drv, struct lcdc_device, driver);
4230 u32 intr_status_reg, intr_clear_reg;
4232 if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
4233 intr_status_reg = INTR_STATUS_RK3366;
4234 intr_clear_reg = INTR_CLEAR_RK3366;
4236 intr_status_reg = INTR_STATUS_RK3368;
4237 intr_clear_reg = INTR_CLEAR_RK3368;
4240 if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
4241 int_reg_val = lcdc_readl(lcdc_dev, intr_status_reg);
4242 if (int_reg_val & m_LINE_FLAG0_INTR_STS) {
4243 lcdc_dev->driver.frame_time.last_framedone_t =
4244 lcdc_dev->driver.frame_time.framedone_t;
4245 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4246 lcdc_msk_reg(lcdc_dev, intr_clear_reg,
4247 m_LINE_FLAG0_INTR_CLR,
4248 v_LINE_FLAG0_INTR_CLR(1));
4249 ret = RK_LF_STATUS_FC;
4251 ret = RK_LF_STATUS_FR;
4254 ret = RK_LF_STATUS_NC;
4260 static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
4261 unsigned int dsp_addr[][4])
4263 struct lcdc_device *lcdc_dev =
4264 container_of(dev_drv, struct lcdc_device, driver);
4265 spin_lock(&lcdc_dev->reg_lock);
4266 if (lcdc_dev->clk_on) {
4267 dsp_addr[0][0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
4268 dsp_addr[1][0] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
4269 dsp_addr[2][0] = lcdc_readl(lcdc_dev, WIN2_MST0);
4270 dsp_addr[2][1] = lcdc_readl(lcdc_dev, WIN2_MST1);
4271 dsp_addr[2][2] = lcdc_readl(lcdc_dev, WIN2_MST2);
4272 dsp_addr[2][3] = lcdc_readl(lcdc_dev, WIN2_MST3);
4273 dsp_addr[3][0] = lcdc_readl(lcdc_dev, WIN3_MST0);
4274 dsp_addr[3][1] = lcdc_readl(lcdc_dev, WIN3_MST1);
4275 dsp_addr[3][2] = lcdc_readl(lcdc_dev, WIN3_MST2);
4276 dsp_addr[3][3] = lcdc_readl(lcdc_dev, WIN3_MST3);
4278 spin_unlock(&lcdc_dev->reg_lock);
4282 static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv,
4283 int mode, int calc, int up,
4284 int down, int global)
4286 struct lcdc_device *lcdc_dev =
4287 container_of(dev_drv, struct lcdc_device, driver);
4288 struct rk_screen *screen = dev_drv->cur_screen;
4289 u32 total_pixel, calc_pixel, stage_up, stage_down;
4290 u32 pixel_num, global_dn;
4291 u32 mask = 0, val = 0;
4292 int *cabc_lut = NULL;
4294 if (screen->type == SCREEN_HDMI && screen->type == SCREEN_TVOUT) {
4295 pr_err("screen type is %d, not support cabc\n", screen->type);
4297 } else if (!screen->cabc_lut) {
4298 pr_err("screen cabc lut not config, so not open cabc\n");
4301 cabc_lut = screen->cabc_lut;
4305 spin_lock(&lcdc_dev->reg_lock);
4306 if (lcdc_dev->clk_on) {
4307 lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
4308 m_CABC_EN, v_CABC_EN(0));
4309 lcdc_cfg_done(lcdc_dev);
4311 pr_info("mode = 0, close cabc\n");
4312 dev_drv->cabc_mode = mode;
4313 spin_unlock(&lcdc_dev->reg_lock);
4316 if (dev_drv->cabc_mode == 0)
4317 rk3368_set_cabc_lut(dev_drv, dev_drv->cur_screen->cabc_lut);
4319 total_pixel = screen->mode.xres * screen->mode.yres;
4320 pixel_num = 1000 - calc;
4321 calc_pixel = (total_pixel * pixel_num) / 1000;
4325 pr_info("enable cabc:mode=%d, calc=%d, up=%d, down=%d, global=%d\n",
4326 mode, calc, stage_up, stage_down, global_dn);
4328 spin_lock(&lcdc_dev->reg_lock);
4329 if (lcdc_dev->clk_on) {
4330 mask = m_CABC_EN | m_CABC_HANDLE_EN | m_PWM_CONFIG_MODE |
4331 m_CABC_CALC_PIXEL_NUM;
4332 val = v_CABC_EN(1) | v_CABC_HANDLE_EN(1) |
4333 v_PWM_CONFIG_MODE(STAGE_BY_STAGE) |
4334 v_CABC_CALC_PIXEL_NUM(calc_pixel);
4335 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
4337 mask = m_CABC_LUT_EN | m_CABC_TOTAL_PIXEL_NUM;
4338 val = v_CABC_LUT_EN(1) | v_CABC_TOTAL_PIXEL_NUM(total_pixel);
4339 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
4341 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_UP |
4342 m_CABC_STAGE_MODE | m_MAX_SCALE_CFG_VALUE |
4343 m_MAX_SCALE_CFG_ENABLE;
4344 val = v_CABC_STAGE_DOWN(stage_down) |
4345 v_CABC_STAGE_UP(stage_up) |
4346 v_CABC_STAGE_MODE(0) | v_MAX_SCALE_CFG_VALUE(1) |
4347 v_MAX_SCALE_CFG_ENABLE(0);
4348 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
4350 mask = m_CABC_GLOBAL_DN | m_CABC_GLOBAL_DN_LIMIT_EN;
4351 val = v_CABC_GLOBAL_DN(global_dn) |
4352 v_CABC_GLOBAL_DN_LIMIT_EN(1);
4353 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
4354 lcdc_cfg_done(lcdc_dev);
4355 dev_drv->cabc_mode = mode;
4357 spin_unlock(&lcdc_dev->reg_lock);
4364 sin_hue = sin(a)*256 +0x100;
4365 cos_hue = cos(a)*256;
4367 sin_hue = sin(a)*256;
4368 cos_hue = cos(a)*256;
4370 static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
4373 struct lcdc_device *lcdc_dev =
4374 container_of(dev_drv, struct lcdc_device, driver);
4377 spin_lock(&lcdc_dev->reg_lock);
4378 if (lcdc_dev->clk_on) {
4379 val = lcdc_readl(lcdc_dev, BCSH_H);
4382 val &= m_BCSH_SIN_HUE;
4385 val &= m_BCSH_COS_HUE;
4392 spin_unlock(&lcdc_dev->reg_lock);
4397 static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
4398 int sin_hue, int cos_hue)
4400 struct lcdc_device *lcdc_dev =
4401 container_of(dev_drv, struct lcdc_device, driver);
4404 spin_lock(&lcdc_dev->reg_lock);
4405 if (lcdc_dev->clk_on) {
4406 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
4407 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
4408 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
4409 lcdc_cfg_done(lcdc_dev);
4411 spin_unlock(&lcdc_dev->reg_lock);
4416 static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4417 bcsh_bcs_mode mode, int value)
4419 struct lcdc_device *lcdc_dev =
4420 container_of(dev_drv, struct lcdc_device, driver);
4421 u32 mask = 0, val = 0;
4423 spin_lock(&lcdc_dev->reg_lock);
4424 if (lcdc_dev->clk_on) {
4427 /*user: from 0 to 255,typical is 128,
4428 *vop,6bit: from 0 to 64, typical is 32*/
4432 else if (value >= 0x20)
4433 value = value - 0x20;
4434 mask = m_BCSH_BRIGHTNESS;
4435 val = v_BCSH_BRIGHTNESS(value);
4438 /*user: from 0 to 510,typical is 256
4439 *vop,9bit, from 0 to 511,typical is 256*/
4440 value = 512 - value;
4441 mask = m_BCSH_CONTRAST;
4442 val = v_BCSH_CONTRAST(value);
4445 /*from 0 to 1024,typical is 512
4446 *vop,9bit, from 0 to 512, typical is 256*/
4448 mask = m_BCSH_SAT_CON;
4449 val = v_BCSH_SAT_CON(value);
4454 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
4455 lcdc_cfg_done(lcdc_dev);
4457 spin_unlock(&lcdc_dev->reg_lock);
4461 static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4464 struct lcdc_device *lcdc_dev =
4465 container_of(dev_drv, struct lcdc_device, driver);
4468 spin_lock(&lcdc_dev->reg_lock);
4469 if (lcdc_dev->clk_on) {
4470 val = lcdc_readl(lcdc_dev, BCSH_BCS);
4473 val &= m_BCSH_BRIGHTNESS;
4481 val &= m_BCSH_CONTRAST;
4485 val &= m_BCSH_SAT_CON;
4493 spin_unlock(&lcdc_dev->reg_lock);
4497 static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
4499 struct lcdc_device *lcdc_dev =
4500 container_of(dev_drv, struct lcdc_device, driver);
4503 spin_lock(&lcdc_dev->reg_lock);
4504 if (lcdc_dev->clk_on) {
4506 lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1);
4507 lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
4508 lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
4509 dev_drv->bcsh.enable = 1;
4513 lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
4514 dev_drv->bcsh.enable = 0;
4516 rk3368_lcdc_bcsh_path_sel(dev_drv);
4517 lcdc_cfg_done(lcdc_dev);
4519 spin_unlock(&lcdc_dev->reg_lock);
4523 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4525 if (!enable || !dev_drv->bcsh.enable) {
4526 rk3368_lcdc_open_bcsh(dev_drv, false);
4530 if (dev_drv->bcsh.brightness <= 255 ||
4531 dev_drv->bcsh.contrast <= 510 ||
4532 dev_drv->bcsh.sat_con <= 1015 ||
4533 (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4534 rk3368_lcdc_open_bcsh(dev_drv, true);
4535 if (dev_drv->bcsh.brightness <= 255)
4536 rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4537 dev_drv->bcsh.brightness);
4538 if (dev_drv->bcsh.contrast <= 510)
4539 rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
4540 dev_drv->bcsh.contrast);
4541 if (dev_drv->bcsh.sat_con <= 1015)
4542 rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
4543 dev_drv->bcsh.sat_con);
4544 if (dev_drv->bcsh.sin_hue <= 511 &&
4545 dev_drv->bcsh.cos_hue <= 511)
4546 rk3368_lcdc_set_bcsh_hue(dev_drv,
4547 dev_drv->bcsh.sin_hue,
4548 dev_drv->bcsh.cos_hue);
4553 static int __maybe_unused
4554 rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4556 struct lcdc_device *lcdc_dev =
4557 container_of(dev_drv, struct lcdc_device, driver);
4560 spin_lock(&lcdc_dev->reg_lock);
4561 if (likely(lcdc_dev->clk_on)) {
4562 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4564 lcdc_cfg_done(lcdc_dev);
4566 spin_unlock(&lcdc_dev->reg_lock);
4568 spin_lock(&lcdc_dev->reg_lock);
4569 if (likely(lcdc_dev->clk_on)) {
4570 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4573 lcdc_cfg_done(lcdc_dev);
4575 spin_unlock(&lcdc_dev->reg_lock);
4582 static int rk3368_lcdc_wait_frame_start(struct rk_lcdc_driver *dev_drv,
4585 u32 line_scane_num, vsync_end, vact_end;
4588 struct lcdc_device *lcdc_dev =
4589 container_of(dev_drv, struct lcdc_device, driver);
4591 if (unlikely(!lcdc_dev->clk_on)) {
4592 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
4596 interlace_mode = lcdc_read_bit(lcdc_dev, DSP_CTRL0,
4598 if (interlace_mode) {
4599 vsync_end = lcdc_readl(lcdc_dev, DSP_VS_ST_END_F1) &
4601 vact_end = lcdc_readl(lcdc_dev, DSP_VACT_ST_END_F1) &
4604 vsync_end = lcdc_readl(lcdc_dev, DSP_VTOTAL_VS_END) &
4606 vact_end = lcdc_readl(lcdc_dev, DSP_VACT_ST_END) &
4610 line_scane_num = lcdc_readl(lcdc_dev, SCAN_LINE_NUM) &
4612 if ((line_scane_num > vsync_end) &&
4613 (line_scane_num <= vact_end - 100))
4617 } else if (1 == enable) {
4618 line_scane_num = lcdc_readl(lcdc_dev, SCAN_LINE_NUM) & 0x1fff;
4619 return line_scane_num;
4625 static int rk3368_lcdc_backlight_close(struct rk_lcdc_driver *dev_drv,
4628 struct lcdc_device *lcdc_dev =
4629 container_of(dev_drv, struct lcdc_device, driver);
4631 if (unlikely(!lcdc_dev->clk_on)) {
4632 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
4635 rk3368_lcdc_get_backlight_device(dev_drv);
4638 /* close the backlight */
4639 if (lcdc_dev->backlight) {
4640 lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4641 backlight_update_status(lcdc_dev->backlight);
4643 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4644 dev_drv->trsm_ops->disable();
4646 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4647 dev_drv->trsm_ops->enable();
4649 /* open the backlight */
4650 if (lcdc_dev->backlight) {
4651 lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
4652 backlight_update_status(lcdc_dev->backlight);
4659 static int rk3368_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv,
4660 struct overscan *overscan)
4662 struct lcdc_device *lcdc_dev =
4663 container_of(dev_drv, struct lcdc_device, driver);
4665 if (unlikely(!lcdc_dev->clk_on)) {
4666 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
4669 /*rk3368_lcdc_post_cfg(dev_drv);*/
4674 static int rk3368_lcdc_extern_func(struct rk_lcdc_driver *dev_drv,
4677 struct lcdc_device *lcdc_dev =
4678 container_of(dev_drv, struct lcdc_device, driver);
4681 if (unlikely(!lcdc_dev->clk_on)) {
4682 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
4687 case GET_PAGE_FAULT:
4688 val = lcdc_readl(lcdc_dev, MMU_INT_RAWSTAT);
4689 if ((val & 0x1) == 1) {
4690 if ((val & 0x2) == 1)
4691 pr_info("val=0x%x,vop iommu bus error\n", val);
4696 case CLR_PAGE_FAULT:
4697 lcdc_writel(lcdc_dev, MMU_INT_CLEAR, 0x3);
4699 case UNMASK_PAGE_FAULT:
4700 lcdc_writel(lcdc_dev, MMU_INT_MASK, 0x2);
4709 static int rk3368_lcdc_set_wb(struct rk_lcdc_driver *dev_drv)
4711 struct lcdc_device *lcdc_dev =
4712 container_of(dev_drv, struct lcdc_device, driver);
4713 struct rk_fb_reg_wb_data *wb_data;
4714 u32 src_w, src_h, dst_w, dst_h, fmt_cfg;
4715 u32 xscale_en = 0, x_scale_fac = 0, y_throw = 0;
4716 u32 csc_mode = 0, rgb2yuv = 0, dither_en = 0;
4718 if (unlikely(!lcdc_dev->clk_on)) {
4719 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
4722 wb_data = &dev_drv->wb_data;
4723 if ((wb_data->xsize == 0) || (wb_data->ysize == 0))
4726 src_w = dev_drv->cur_screen->mode.xres;
4727 src_h = dev_drv->cur_screen->mode.yres;
4728 dst_w = wb_data->xsize;
4729 dst_h = wb_data->ysize;
4730 if (!IS_ALIGNED(dst_w, RK3366_WB_ALIGN))
4731 pr_info("dst_w: %d not align 16 pixel\n", dst_w);
4735 else if (src_w < dst_w)
4739 if (wb_data->state && xscale_en)
4740 x_scale_fac = GET_SCALE_FACTOR_BILI_DN(src_w, dst_w);
4741 if ((src_h >= 2 * dst_h) && (dst_h != 0))
4745 switch (wb_data->data_format) {
4761 if (dev_drv->overlay_mode == VOP_RGB_DOMAIN)
4763 if ((src_w < 1280) && (src_h < 720))
4764 csc_mode = VOP_R2Y_CSC_BT601;
4766 csc_mode = VOP_R2Y_CSC_BT709;
4770 pr_info("unsupport fmt: %d\n", wb_data->data_format);
4773 spin_lock(&lcdc_dev->reg_lock);
4774 lcdc_msk_reg(lcdc_dev, WB_CTRL0,
4775 m_WB_EN | m_WB_FMT | m_WB_XPSD_BIL_EN |
4776 m_WB_YTHROW_EN | m_WB_RGB2YUV_EN | m_WB_RGB2YUV_MODE |
4778 v_WB_EN(wb_data->state) | v_WB_FMT(fmt_cfg) |
4779 v_WB_XPSD_BIL_EN(xscale_en) |
4780 v_WB_YTHROW_EN(y_throw) | v_WB_RGB2YUV_EN(rgb2yuv) |
4781 v_WB_RGB2YUV_MODE(csc_mode) | v_WB_DITHER_EN(dither_en));
4782 lcdc_msk_reg(lcdc_dev, WB_CTRL1,
4783 m_WB_WIDTH | m_WB_XPSD_BIL_FACTOR,
4785 v_WB_XPSD_BIL_FACTOR(x_scale_fac));
4786 lcdc_writel(lcdc_dev, WB_YRGB_MST, wb_data->smem_start);
4787 lcdc_writel(lcdc_dev, WB_CBR_MST, wb_data->cbr_start);
4788 spin_unlock(&lcdc_dev->reg_lock);
4793 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4794 .open = rk3368_lcdc_open,
4795 .win_direct_en = rk3368_lcdc_win_direct_en,
4796 .load_screen = rk3368_load_screen,
4797 .get_dspbuf_info = rk3368_get_dspbuf_info,
4798 .post_dspbuf = rk3368_post_dspbuf,
4799 .set_par = rk3368_lcdc_set_par,
4800 .pan_display = rk3368_lcdc_pan_display,
4801 .direct_set_addr = rk3368_lcdc_direct_set_win_addr,
4802 /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/
4803 .blank = rk3368_lcdc_blank,
4804 .ioctl = rk3368_lcdc_ioctl,
4805 .suspend = rk3368_lcdc_early_suspend,
4806 .resume = rk3368_lcdc_early_resume,
4807 .get_win_state = rk3368_lcdc_get_win_state,
4808 .area_support_num = rk3368_lcdc_get_area_num,
4809 .ovl_mgr = rk3368_lcdc_ovl_mgr,
4810 .get_disp_info = rk3368_lcdc_get_disp_info,
4811 .fps_mgr = rk3368_lcdc_fps_mgr,
4812 .fb_get_win_id = rk3368_lcdc_get_win_id,
4813 .fb_win_remap = rk3368_fb_win_remap,
4814 .set_dsp_lut = rk3368_lcdc_set_lut,
4815 .set_cabc_lut = rk3368_set_cabc_lut,
4816 .poll_vblank = rk3368_lcdc_poll_vblank,
4817 .get_dsp_addr = rk3368_lcdc_get_dsp_addr,
4818 .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc,
4819 .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue,
4820 .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs,
4821 .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue,
4822 .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs,
4823 .open_bcsh = rk3368_lcdc_open_bcsh,
4824 .dump_reg = rk3368_lcdc_reg_dump,
4825 .cfg_done = rk3368_lcdc_config_done,
4826 .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu,
4827 /*.dsp_black = rk3368_lcdc_dsp_black,*/
4828 .backlight_close = rk3368_lcdc_backlight_close,
4829 .mmu_en = rk3368_lcdc_mmu_en,
4830 .set_overscan = rk3368_lcdc_set_overscan,
4831 .extern_func = rk3368_lcdc_extern_func,
4832 .wait_frame_start = rk3368_lcdc_wait_frame_start,
4833 .set_wb = rk3368_lcdc_set_wb,
4836 #ifdef LCDC_IRQ_EMPTY_DEBUG
4837 static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev,
4838 unsigned int intr_status)
4842 if (lcdc_dev->soc_type == VOP_FULL_RK3366)
4843 intr_clr_reg = INTR_CLEAR_RK3366;
4845 intr_clr_reg = INTR_CLEAR_RK3368;
4847 if (intr_status & m_WIN0_EMPTY_INTR_STS) {
4848 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_WIN0_EMPTY_INTR_CLR,
4849 v_WIN0_EMPTY_INTR_CLR(1));
4850 dev_warn(lcdc_dev->dev, "win0 empty irq!");
4851 } else if (intr_status & m_WIN1_EMPTY_INTR_STS) {
4852 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_WIN1_EMPTY_INTR_CLR,
4853 v_WIN1_EMPTY_INTR_CLR(1));
4854 dev_warn(lcdc_dev->dev, "win1 empty irq!");
4855 } else if (intr_status & m_WIN2_EMPTY_INTR_STS) {
4856 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_WIN2_EMPTY_INTR_CLR,
4857 v_WIN2_EMPTY_INTR_CLR(1));
4858 dev_warn(lcdc_dev->dev, "win2 empty irq!");
4859 } else if (intr_status & m_WIN3_EMPTY_INTR_STS) {
4860 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_WIN3_EMPTY_INTR_CLR,
4861 v_WIN3_EMPTY_INTR_CLR(1));
4862 dev_warn(lcdc_dev->dev, "win3 empty irq!");
4863 } else if (intr_status & m_HWC_EMPTY_INTR_STS) {
4864 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_HWC_EMPTY_INTR_CLR,
4865 v_HWC_EMPTY_INTR_CLR(1));
4866 dev_warn(lcdc_dev->dev, "HWC empty irq!");
4867 } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) {
4868 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_POST_BUF_EMPTY_INTR_CLR,
4869 v_POST_BUF_EMPTY_INTR_CLR(1));
4870 dev_warn(lcdc_dev->dev, "post buf empty irq!");
4871 } else if (intr_status & m_PWM_GEN_INTR_STS) {
4872 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_PWM_GEN_INTR_CLR,
4873 v_PWM_GEN_INTR_CLR(1));
4874 dev_warn(lcdc_dev->dev, "PWM gen irq!");
4880 static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id)
4882 struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
4883 ktime_t timestamp = ktime_get();
4885 u32 line_scane_num, dsp_vs_st_f1;
4886 struct rk_screen *screen = lcdc_dev->driver.cur_screen;
4887 u32 intr_en_reg, intr_clr_reg, intr_status_reg;
4889 if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
4890 intr_status_reg = INTR_STATUS_RK3366;
4891 intr_clr_reg = INTR_CLEAR_RK3366;
4892 intr_en_reg = INTR_EN_RK3366;
4894 intr_status_reg = INTR_STATUS_RK3368;
4895 intr_clr_reg = INTR_CLEAR_RK3368;
4896 intr_en_reg = INTR_EN_RK3368;
4899 intr_status = lcdc_readl(lcdc_dev, intr_status_reg);
4900 if (intr_status & m_FS_INTR_STS) {
4901 timestamp = ktime_get();
4902 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_FS_INTR_CLR,
4904 line_scane_num = lcdc_readl(lcdc_dev, SCAN_LINE_NUM) & 0x1fff;
4905 dsp_vs_st_f1 = lcdc_readl(lcdc_dev, DSP_VS_ST_END_F1) >> 16;
4906 /*if(lcdc_dev->driver.wait_fs){ */
4908 spin_lock(&(lcdc_dev->driver.cpl_lock));
4909 complete(&(lcdc_dev->driver.frame_done));
4910 spin_unlock(&(lcdc_dev->driver.cpl_lock));
4912 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4913 if ((lcdc_dev->soc_type == VOP_FULL_RK3366) &&
4914 (lcdc_dev->driver.wb_data.state)) {
4915 if (lcdc_read_bit(lcdc_dev, WB_CTRL0, m_WB_EN)) {
4916 lcdc_msk_reg(lcdc_dev, WB_CTRL0,
4917 m_WB_EN, v_WB_EN(0));
4918 lcdc_cfg_done(lcdc_dev);
4919 lcdc_dev->driver.wb_data.state = 0;
4922 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
4923 if (!(screen->mode.vmode & FB_VMODE_INTERLACED) ||
4924 (line_scane_num >= dsp_vs_st_f1)) {
4925 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4926 wake_up_interruptible_all(
4927 &lcdc_dev->driver.vsync_info.wait);
4929 } else if (intr_status & m_LINE_FLAG0_INTR_STS) {
4930 lcdc_dev->driver.frame_time.last_framedone_t =
4931 lcdc_dev->driver.frame_time.framedone_t;
4932 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4933 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_LINE_FLAG0_INTR_CLR,
4934 v_LINE_FLAG0_INTR_CLR(1));
4935 } else if (intr_status & m_LINE_FLAG1_INTR_STS) {
4937 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_LINE_FLAG1_INTR_CLR,
4938 v_LINE_FLAG1_INTR_CLR(1));
4939 } else if (intr_status & m_FS_NEW_INTR_STS) {
4940 /*new frame start */
4941 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_FS_NEW_INTR_CLR,
4942 v_FS_NEW_INTR_CLR(1));
4943 } else if (intr_status & m_BUS_ERROR_INTR_STS) {
4944 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_BUS_ERROR_INTR_CLR,
4945 v_BUS_ERROR_INTR_CLR(1));
4946 dev_warn(lcdc_dev->dev, "bus error!");
4949 /* for win empty debug */
4950 #ifdef LCDC_IRQ_EMPTY_DEBUG
4951 rk3368_lcdc_parse_irq(lcdc_dev, intr_status);
4956 #if defined(CONFIG_PM)
4957 static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
4962 static int rk3368_lcdc_resume(struct platform_device *pdev)
4967 #define rk3368_lcdc_suspend NULL
4968 #define rk3368_lcdc_resume NULL
4971 static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4973 struct device_node *np = lcdc_dev->dev->of_node;
4974 struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4977 if (of_property_read_u32(np, "rockchip,prop", &val))
4978 lcdc_dev->prop = PRMRY; /*default set it as primary */
4980 lcdc_dev->prop = val;
4982 if (of_property_read_u32(np, "rockchip,mirror", &val))
4983 dev_drv->rotate_mode = NO_MIRROR;
4985 dev_drv->rotate_mode = val;
4987 if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4988 dev_drv->cabc_mode = 0; /* default set close cabc */
4990 dev_drv->cabc_mode = val;
4992 if (of_property_read_u32(np, "rockchip,pwr18", &val))
4993 /*default set it as 3.xv power supply */
4994 lcdc_dev->pwr18 = false;
4996 lcdc_dev->pwr18 = (val ? true : false);
4998 if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4999 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
5001 dev_drv->fb_win_map = val;
5003 if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
5004 dev_drv->bcsh.enable = false;
5006 dev_drv->bcsh.enable = (val ? true : false);
5008 if (of_property_read_u32(np, "rockchip,brightness", &val))
5009 dev_drv->bcsh.brightness = 0xffff;
5011 dev_drv->bcsh.brightness = val;
5013 if (of_property_read_u32(np, "rockchip,contrast", &val))
5014 dev_drv->bcsh.contrast = 0xffff;
5016 dev_drv->bcsh.contrast = val;
5018 if (of_property_read_u32(np, "rockchip,sat-con", &val))
5019 dev_drv->bcsh.sat_con = 0xffff;
5021 dev_drv->bcsh.sat_con = val;
5023 if (of_property_read_u32(np, "rockchip,hue", &val)) {
5024 dev_drv->bcsh.sin_hue = 0xffff;
5025 dev_drv->bcsh.cos_hue = 0xffff;
5027 dev_drv->bcsh.sin_hue = val & 0xff;
5028 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
5031 if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
5032 dev_drv->iommu_enabled = 0;
5034 dev_drv->iommu_enabled = val;
5038 static int rk3368_lcdc_probe(struct platform_device *pdev)
5040 struct lcdc_device *lcdc_dev = NULL;
5041 struct rk_lcdc_driver *dev_drv;
5042 struct device *dev = &pdev->dev;
5043 struct resource *res;
5044 struct device_node *np = pdev->dev.of_node;
5048 /*if the primary lcdc has not registered ,the extend
5049 lcdc register later */
5050 of_property_read_u32(np, "rockchip,prop", &prop);
5051 if (prop == EXTEND) {
5052 if (!is_prmry_rk_lcdc_registered())
5053 return -EPROBE_DEFER;
5055 lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
5057 dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!");
5060 platform_set_drvdata(pdev, lcdc_dev);
5061 lcdc_dev->dev = dev;
5062 rk3368_lcdc_parse_dt(lcdc_dev);
5063 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
5064 /* enable power domain */
5065 pm_runtime_enable(dev);
5067 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5068 lcdc_dev->reg_phy_base = res->start;
5069 lcdc_dev->len = resource_size(res);
5071 lcdc_dev->regs = devm_ioremap(&pdev->dev, res->start,
5072 resource_size(res));
5073 if (IS_ERR(lcdc_dev->regs))
5074 return PTR_ERR(lcdc_dev->regs);
5076 dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs);
5078 lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
5079 if (IS_ERR(lcdc_dev->regsbak))
5080 return PTR_ERR(lcdc_dev->regsbak);
5081 lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
5082 lcdc_dev->cabc_lut_addr_base = (lcdc_dev->regs + CABC_GAMMA_LUT_ADDR);
5083 lcdc_dev->grf_base =
5084 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
5085 if (IS_ERR(lcdc_dev->grf_base)) {
5086 dev_err(&pdev->dev, "can't find lcdc grf property\n");
5087 lcdc_dev->grf_base = NULL;
5089 lcdc_dev->pmugrf_base =
5090 syscon_regmap_lookup_by_phandle(np, "rockchip,pmugrf");
5091 if (IS_ERR(lcdc_dev->pmugrf_base)) {
5092 dev_err(&pdev->dev, "can't find lcdc pmu grf property\n");
5093 lcdc_dev->pmugrf_base = NULL;
5096 lcdc_dev->cru_base =
5097 syscon_regmap_lookup_by_phandle(np, "rockchip,cru");
5098 if (IS_ERR(lcdc_dev->cru_base)) {
5099 dev_err(&pdev->dev, "can't find lcdc cru_base property\n");
5100 lcdc_dev->cru_base = NULL;
5104 dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
5105 dev_drv = &lcdc_dev->driver;
5107 dev_drv->prop = prop;
5108 dev_drv->id = lcdc_dev->id;
5109 dev_drv->ops = &lcdc_drv_ops;
5110 dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
5111 dev_drv->reserved_fb = 1;/*only need reserved 1 buffer*/
5112 spin_lock_init(&lcdc_dev->reg_lock);
5114 lcdc_dev->irq = platform_get_irq(pdev, 0);
5115 if (lcdc_dev->irq < 0) {
5116 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
5121 ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr,
5123 dev_name(dev), lcdc_dev);
5125 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
5126 lcdc_dev->irq, ret);
5130 if (dev_drv->iommu_enabled) {
5131 if (lcdc_dev->id == 0) {
5132 strcpy(dev_drv->mmu_dts_name,
5133 VOPB_IOMMU_COMPATIBLE_NAME);
5135 strcpy(dev_drv->mmu_dts_name,
5136 VOPL_IOMMU_COMPATIBLE_NAME);
5140 ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
5142 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
5145 if (lcdc_dev->soc_type == VOP_FULL_RK3366)
5146 dev_drv->property.feature |= SUPPORT_WRITE_BACK;
5147 else if (lcdc_dev->soc_type == VOP_FULL_RK3368)
5148 dev_drv->property.feature |= SUPPORT_IFBDC;
5149 dev_drv->property.feature |= SUPPORT_VOP_IDENTIFY |
5150 SUPPORT_YUV420_OUTPUT;
5151 dev_drv->property.max_output_x = 4096;
5152 dev_drv->property.max_output_y = 2160;
5153 lcdc_dev->screen = dev_drv->screen0;
5154 dev_info(dev, "lcdc%d probe ok, iommu %s\n",
5155 lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
5160 static int rk3368_lcdc_remove(struct platform_device *pdev)
5165 static void rk3368_lcdc_shutdown(struct platform_device *pdev)
5167 struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
5168 struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
5170 dev_drv->suspend_flag = 1;
5172 flush_kthread_worker(&dev_drv->update_regs_worker);
5173 kthread_stop(dev_drv->update_regs_thread);
5174 rk3368_lcdc_deint(lcdc_dev);
5175 /*if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
5176 dev_drv->trsm_ops->disable();*/
5178 rk3368_lcdc_clk_disable(lcdc_dev);
5179 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
5180 pm_runtime_disable(lcdc_dev->dev);
5182 rk_disp_pwr_disable(dev_drv);
5184 rk3368_lcdc_early_suspend(&lcdc_dev->driver);
5185 rk3368_lcdc_deint(lcdc_dev);
5189 #if defined(CONFIG_OF)
5190 static const struct of_device_id rk3368_lcdc_dt_ids[] = {
5191 {.compatible = "rockchip,rk3368-lcdc",},
5192 {.compatible = "rockchip,rk3366-lcdc-big",},
5197 static struct platform_driver rk3368_lcdc_driver = {
5198 .probe = rk3368_lcdc_probe,
5199 .remove = rk3368_lcdc_remove,
5201 .name = "rk3368-lcdc",
5202 .owner = THIS_MODULE,
5203 .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids),
5205 .suspend = rk3368_lcdc_suspend,
5206 .resume = rk3368_lcdc_resume,
5207 .shutdown = rk3368_lcdc_shutdown,
5210 static int __init rk3368_lcdc_module_init(void)
5212 return platform_driver_register(&rk3368_lcdc_driver);
5215 static void __exit rk3368_lcdc_module_exit(void)
5217 platform_driver_unregister(&rk3368_lcdc_driver);
5220 fs_initcall(rk3368_lcdc_module_init);
5221 module_exit(rk3368_lcdc_module_exit);