drivers/video/rockchip/lcdc/rk3368_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3368_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *Author:hjc<hjc@rock-chips.com>
   6  *This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk3368_lcdc.h"
  39
  40 #if defined(CONFIG_HAS_EARLYSUSPEND)
  41 #include <linux/earlysuspend.h>
  42 #endif
  43 /*#define CONFIG_RK_FPGA 1*/
  44
  45 static int dbg_thresd;
  46 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  47
  48 #define DBG(level, x...) do {                   \
  49         if (unlikely(dbg_thresd >= level))      \
  50                 pr_info(x);\
  51         } while (0)
  52
  53 #define EARLY_TIME 500 /*us*/
  54 static struct rk_lcdc_win lcdc_win[] = {
  55         [0] = {
  56                 .name = "win0",
  57                 .id = 0,
  58                 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_SCALE |
  59                                         SUPPORT_YUV,
  60                 .property.max_input_x = 4096,
  61                 .property.max_input_y = 2304
  62                 },
  63         [1] = {
  64                 .name = "win1",
  65                 .id = 1,
  66                 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_SCALE |
  67                                         SUPPORT_YUV,
  68                 .property.max_input_x = 4096,
  69                 .property.max_input_y = 2304
  70                 },
  71         [2] = {
  72                 .name = "win2",
  73                 .id = 2,
  74                 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_MULTI_AREA,
  75                 .property.max_input_x = 4096,
  76                 .property.max_input_y = 2304
  77                 },
  78         [3] = {
  79                 .name = "win3",
  80                 .id = 3,
  81                 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_MULTI_AREA,
  82                 .property.max_input_x = 4096,
  83                 .property.max_input_y = 2304
  84                 },
  85         [4] = {
  86                 .name = "hwc",
  87                 .id = 4,
  88                 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HWC_LAYER,
  89                 .property.max_input_x = 128,
  90                 .property.max_input_y = 128
  91                 },
  92 };
  93
  94 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
  95
  96 /*#define WAIT_FOR_SYNC 1*/
  97 u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth)
  98 {
  99         u32 vscalednmult;
 100
 101         if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
 102                 vscalednmult = 4;
 103         else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
 104                 vscalednmult = 2;
 105         else
 106                 vscalednmult = 1;
 107
 108         return vscalednmult;
 109 }
 110
 111
 112 static int rk3368_set_cabc_lut(struct rk_lcdc_driver *dev_drv, int *cabc_lut)
 113 {
 114         int i;
 115         int __iomem *c;
 116         u32 v;
 117         struct lcdc_device *lcdc_dev =
 118             container_of(dev_drv, struct lcdc_device, driver);
 119
 120         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 121                      v_CABC_LUT_EN(0));
 122         lcdc_cfg_done(lcdc_dev);
 123         mdelay(25);
 124         for (i = 0; i < 128; i++) {
 125                 v = cabc_lut[i];
 126                 c = lcdc_dev->cabc_lut_addr_base + i;
 127                 writel_relaxed(v, c);
 128         }
 129         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 130                      v_CABC_LUT_EN(1));
 131         return 0;
 132 }
 133
 134
 135 static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
 136 {
 137         int i;
 138         int __iomem *c;
 139         u32 v;
 140         struct lcdc_device *lcdc_dev =
 141             container_of(dev_drv, struct lcdc_device, driver);
 142
 143         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 144                      v_DSP_LUT_EN(0));
 145         lcdc_cfg_done(lcdc_dev);
 146         mdelay(25);
 147         for (i = 0; i < 256; i++) {
 148                 v = dsp_lut[i];
 149                 c = lcdc_dev->dsp_lut_addr_base + i;
 150                 writel_relaxed(v, c);
 151         }
 152         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 153                      v_DSP_LUT_EN(1));
 154
 155         return 0;
 156 }
 157
 158 static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 159 {
 160 #ifdef CONFIG_RK_FPGA
 161         lcdc_dev->clk_on = 1;
 162         return 0;
 163 #endif
 164         if (!lcdc_dev->clk_on) {
 165                 clk_prepare_enable(lcdc_dev->hclk);
 166                 clk_prepare_enable(lcdc_dev->dclk);
 167                 clk_prepare_enable(lcdc_dev->aclk);
 168                 if (lcdc_dev->pd)
 169                         clk_prepare_enable(lcdc_dev->pd);
 170 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
 171                 pm_runtime_get_sync(lcdc_dev->dev);
 172 #endif
 173                 spin_lock(&lcdc_dev->reg_lock);
 174                 lcdc_dev->clk_on = 1;
 175                 spin_unlock(&lcdc_dev->reg_lock);
 176         }
 177
 178         return 0;
 179 }
 180
 181 static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 182 {
 183 #ifdef CONFIG_RK_FPGA
 184         lcdc_dev->clk_on = 0;
 185         return 0;
 186 #endif
 187         if (lcdc_dev->clk_on) {
 188                 spin_lock(&lcdc_dev->reg_lock);
 189                 lcdc_dev->clk_on = 0;
 190                 spin_unlock(&lcdc_dev->reg_lock);
 191                 mdelay(25);
 192                 if (lcdc_dev->pd)
 193                         clk_disable_unprepare(lcdc_dev->pd);
 194 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
 195                 pm_runtime_put(lcdc_dev->dev);
 196 #endif
 197                 clk_disable_unprepare(lcdc_dev->dclk);
 198                 clk_disable_unprepare(lcdc_dev->hclk);
 199                 clk_disable_unprepare(lcdc_dev->aclk);
 200         }
 201
 202         return 0;
 203 }
 204
 205 static int __maybe_unused
 206         rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 207 {
 208         u32 mask, val;
 209         u32 intr_en_reg, intr_clr_reg;
 210
 211         if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
 212                 intr_clr_reg = INTR_CLEAR_RK3366;
 213                 intr_en_reg = INTR_EN_RK3366;
 214         } else {
 215                 intr_clr_reg = INTR_CLEAR_RK3368;
 216                 intr_en_reg = INTR_EN_RK3368;
 217         }
 218
 219         spin_lock(&lcdc_dev->reg_lock);
 220         if (likely(lcdc_dev->clk_on)) {
 221                 mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN |
 222                     m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN |
 223                     m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN |
 224                     m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
 225                     m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
 226                     m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
 227                     m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN;
 228                 val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) |
 229                     v_ADDR_SAME_INTR_EN(0) |
 230                     v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) |
 231                     v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) |
 232                     v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) |
 233                     v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) |
 234                     v_POST_BUF_EMPTY_INTR_EN(0) |
 235                     v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0);
 236                 lcdc_msk_reg(lcdc_dev, intr_en_reg, mask, val);
 237
 238                 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR |
 239                     m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
 240                     m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR |
 241                     m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
 242                     m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
 243                     m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
 244                     m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR;
 245                 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
 246                     v_ADDR_SAME_INTR_CLR(1) |
 247                     v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) |
 248                     v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) |
 249                     v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) |
 250                     v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) |
 251                     v_POST_BUF_EMPTY_INTR_CLR(1) |
 252                     v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1);
 253                 lcdc_msk_reg(lcdc_dev, intr_clr_reg, mask, val);
 254                 lcdc_cfg_done(lcdc_dev);
 255                 spin_unlock(&lcdc_dev->reg_lock);
 256         } else {
 257                 spin_unlock(&lcdc_dev->reg_lock);
 258         }
 259         mdelay(1);
 260         return 0;
 261 }
 262
 263 static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
 264 {
 265         struct lcdc_device *lcdc_dev =
 266             container_of(dev_drv, struct lcdc_device, driver);
 267         int *cbase = (int *)lcdc_dev->regs;
 268         int *regsbak = (int *)lcdc_dev->regsbak;
 269         int i, j, val;
 270         char dbg_message[30];
 271         char buf[10];
 272
 273         pr_info("lcd back up reg:\n");
 274         memset(dbg_message, 0, sizeof(dbg_message));
 275         memset(buf, 0, sizeof(buf));
 276         for (i = 0; i <= (0x200 >> 4); i++) {
 277                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 278                 for (j = 0; j < 4; j++) {
 279                         val = sprintf(buf, "%08x  ", *(regsbak + i * 4 + j));
 280                         strcat(dbg_message, buf);
 281                 }
 282                 pr_info("%s\n", dbg_message);
 283                 memset(dbg_message, 0, sizeof(dbg_message));
 284                 memset(buf, 0, sizeof(buf));
 285         }
 286
 287         pr_info("lcdc reg:\n");
 288         for (i = 0; i <= (0x200 >> 4); i++) {
 289                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 290                 for (j = 0; j < 4; j++) {
 291                         sprintf(buf, "%08x  ",
 292                                 readl_relaxed(cbase + i * 4 + j));
 293                         strcat(dbg_message, buf);
 294                 }
 295                 pr_info("%s\n", dbg_message);
 296                 memset(dbg_message, 0, sizeof(dbg_message));
 297                 memset(buf, 0, sizeof(buf));
 298         }
 299
 300         return 0;
 301 }
 302
 303 #define WIN_EN(id)              \
 304 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en)       \
 305 { \
 306         u32 msk, val;                                                   \
 307         spin_lock(&lcdc_dev->reg_lock);                                 \
 308         msk =  m_WIN##id##_EN;                                          \
 309         val  =  v_WIN##id##_EN(en);                                     \
 310         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);              \
 311         lcdc_cfg_done(lcdc_dev);                                        \
 312         spin_unlock(&lcdc_dev->reg_lock);                               \
 313         return 0;                                                       \
 314 }
 315
 316 WIN_EN(0);
 317 WIN_EN(1);
 318 WIN_EN(2);
 319 WIN_EN(3);
 320 /*enable/disable win directly*/
 321 static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv,
 322                                      int win_id, int en)
 323 {
 324         struct lcdc_device *lcdc_dev =
 325             container_of(drv, struct lcdc_device, driver);
 326         if (win_id == 0)
 327                 win0_enable(lcdc_dev, en);
 328         else if (win_id == 1)
 329                 win1_enable(lcdc_dev, en);
 330         else if (win_id == 2)
 331                 win2_enable(lcdc_dev, en);
 332         else if (win_id == 3)
 333                 win3_enable(lcdc_dev, en);
 334         else
 335                 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
 336         return 0;
 337 }
 338
 339 #define SET_WIN_ADDR(id) \
 340 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
 341 {                                                       \
 342         u32 msk, val;                                   \
 343         spin_lock(&lcdc_dev->reg_lock);                 \
 344         lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr);        \
 345         msk =  m_WIN##id##_EN;                          \
 346         val  =  v_WIN0_EN(1);                           \
 347         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);      \
 348         lcdc_cfg_done(lcdc_dev);                        \
 349         spin_unlock(&lcdc_dev->reg_lock);               \
 350         return 0;                                       \
 351 }
 352
 353 SET_WIN_ADDR(0);
 354 SET_WIN_ADDR(1);
 355 int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
 356                                     int win_id, u32 addr)
 357 {
 358         struct lcdc_device *lcdc_dev =
 359             container_of(dev_drv, struct lcdc_device, driver);
 360         if (win_id == 0)
 361                 set_win0_addr(lcdc_dev, addr);
 362         else
 363                 set_win1_addr(lcdc_dev, addr);
 364
 365         return 0;
 366 }
 367
 368 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 369 {
 370         int reg = 0;
 371         u32 val = 0;
 372         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 373         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 374         u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 375         u32 st_x, st_y;
 376         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 377
 378         spin_lock(&lcdc_dev->reg_lock);
 379         for (reg = 0; reg < SCAN_LINE_NUM; reg += 4) {
 380                 val = lcdc_readl_backup(lcdc_dev, reg);
 381                 switch (reg) {
 382                 case VERSION_INFO:
 383                         lcdc_dev->soc_type = val;
 384                         break;
 385                 case WIN0_ACT_INFO:
 386                         win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1;
 387                         win0->area[0].yact =
 388                             ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
 389                         break;
 390                 case WIN0_DSP_INFO:
 391                         win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1;
 392                         win0->area[0].ysize =
 393                             ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
 394                         break;
 395                 case WIN0_DSP_ST:
 396                         st_x = val & m_WIN0_DSP_XST;
 397                         st_y = (val & m_WIN0_DSP_YST) >> 16;
 398                         win0->area[0].xpos = st_x - h_pw_bp;
 399                         win0->area[0].ypos = st_y - v_pw_bp;
 400                         break;
 401                 case WIN0_CTRL0:
 402                         win0->state = val & m_WIN0_EN;
 403                         win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1;
 404                         win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
 405                         win0->area[0].format = win0->area[0].fmt_cfg;
 406                         break;
 407                 case WIN0_VIR:
 408                         win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE;
 409                         win0->area[0].uv_vir_stride =
 410                             (val & m_WIN0_VIR_STRIDE_UV) >> 16;
 411                         if (win0->area[0].format == ARGB888)
 412                                 win0->area[0].xvir = win0->area[0].y_vir_stride;
 413                         else if (win0->area[0].format == RGB888)
 414                                 win0->area[0].xvir =
 415                                     win0->area[0].y_vir_stride * 4 / 3;
 416                         else if (win0->area[0].format == RGB565)
 417                                 win0->area[0].xvir =
 418                                     2 * win0->area[0].y_vir_stride;
 419                         else    /* YUV */
 420                                 win0->area[0].xvir =
 421                                     4 * win0->area[0].y_vir_stride;
 422                         break;
 423                 case WIN0_YRGB_MST:
 424                         win0->area[0].smem_start = val;
 425                         break;
 426                 case WIN0_CBR_MST:
 427                         win0->area[0].cbr_start = val;
 428                         break;
 429                 case DSP_VACT_ST_END:
 430                         if (support_uboot_display()) {
 431                                 screen->mode.yres =
 432                                 (val & 0x1fff) - ((val >> 16) & 0x1fff);
 433                                 win0->area[0].ypos =
 434                                 st_y - ((val >> 16) & 0x1fff);
 435                         }
 436                         break;
 437                 case DSP_HACT_ST_END:
 438                         if (support_uboot_display()) {
 439                                 screen->mode.xres =
 440                                 (val & 0x1fff) - ((val >> 16) & 0x1fff);
 441                                 win0->area[0].xpos =
 442                                 st_x - ((val >> 16) & 0x1fff);
 443                         }
 444                         break;
 445                 default:
 446                         break;
 447                 }
 448         }
 449         spin_unlock(&lcdc_dev->reg_lock);
 450 }
 451
 452 /********do basic init*********/
 453 static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 454 {
 455         u32 mask, val;
 456         struct lcdc_device *lcdc_dev =
 457             container_of(dev_drv, struct lcdc_device, driver);
 458         if (lcdc_dev->pre_init)
 459                 return 0;
 460
 461         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 462         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 463         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 464         if ((IS_ERR(lcdc_dev->aclk)) || (IS_ERR(lcdc_dev->dclk)) ||
 465             (IS_ERR(lcdc_dev->hclk))) {
 466                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 467                         lcdc_dev->id);
 468         }
 469
 470         lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
 471         if (IS_ERR(lcdc_dev->pd)) {
 472                 dev_err(lcdc_dev->dev, "failed to get lcdc%d pdclk source\n",
 473                         lcdc_dev->id);
 474                 lcdc_dev->pd = NULL;
 475         }
 476
 477         if (!support_uboot_display())
 478                 rk_disp_pwr_enable(dev_drv);
 479         rk3368_lcdc_clk_enable(lcdc_dev);
 480
 481         /*backup reg config at uboot */
 482         lcdc_read_reg_defalut_cfg(lcdc_dev);
 483         if (lcdc_dev->soc_type == VOP_FULL_RK3366)
 484                 lcdc_grf_writel(lcdc_dev->grf_base, RK3366_GRF_IO_VSEL,
 485                                 RK3366_GRF_VOP_IOVOL_SEL(lcdc_dev->pwr18));
 486         else
 487                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 488                                 PMUGRF_SOC_CON0_VOP,
 489                                 RK3368_GRF_VOP_IOVOL_SEL(lcdc_dev->pwr18));
 490
 491         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_0,0x15110903);
 492         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_1,0x00030911);
 493         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_0,0x1a150b04);
 494         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_1,0x00040b15);
 495         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_0,0x15110903);
 496         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_1,0x00030911);
 497
 498         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 499         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 500         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696);
 501         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969);
 502         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 503         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 504
 505         mask = m_AUTO_GATING_EN;
 506         val = v_AUTO_GATING_EN(0);
 507         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 508         mask = m_DITHER_UP_EN;
 509         val = v_DITHER_UP_EN(1);
 510         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
 511         lcdc_cfg_done(lcdc_dev);
 512         /*disable win0 to workaround iommu pagefault */
 513         /*if (dev_drv->iommu_enabled) */
 514         /*      win0_enable(lcdc_dev, 0); */
 515         lcdc_dev->pre_init = true;
 516
 517         return 0;
 518 }
 519
 520 static void rk3368_lcdc_deint(struct lcdc_device *lcdc_dev)
 521 {
 522         u32 mask, val;
 523
 524         if (lcdc_dev->clk_on) {
 525                 rk3368_lcdc_disable_irq(lcdc_dev);
 526                 spin_lock(&lcdc_dev->reg_lock);
 527                 mask = m_WIN0_EN;
 528                 val = v_WIN0_EN(0);
 529                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
 530                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
 531
 532                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
 533                         m_WIN2_MST1_EN |
 534                         m_WIN2_MST2_EN | m_WIN2_MST3_EN;
 535                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
 536                         v_WIN2_MST1_EN(0) |
 537                         v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
 538                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
 539                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
 540                 lcdc_cfg_done(lcdc_dev);
 541                 spin_unlock(&lcdc_dev->reg_lock);
 542                 mdelay(50);
 543         }
 544 }
 545
 546 static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
 547 {
 548         struct lcdc_device *lcdc_dev =
 549             container_of(dev_drv, struct lcdc_device, driver);
 550         struct rk_screen *screen = dev_drv->cur_screen;
 551         u16 x_res = screen->mode.xres;
 552         u16 y_res = screen->mode.yres;
 553         u32 mask, val;
 554         u16 h_total, v_total;
 555         u16 post_hsd_en, post_vsd_en;
 556         u16 post_dsp_hact_st, post_dsp_hact_end;
 557         u16 post_dsp_vact_st, post_dsp_vact_end;
 558         u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
 559         u16 post_h_fac, post_v_fac;
 560
 561         screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200;
 562         screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200;
 563         screen->post_xsize = x_res *
 564             (dev_drv->overscan.left + dev_drv->overscan.right) / 200;
 565         screen->post_ysize = y_res *
 566             (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200;
 567
 568         h_total = screen->mode.hsync_len + screen->mode.left_margin +
 569             x_res + screen->mode.right_margin;
 570         v_total = screen->mode.vsync_len + screen->mode.upper_margin +
 571             y_res + screen->mode.lower_margin;
 572
 573         if (screen->post_dsp_stx + screen->post_xsize > x_res) {
 574                 dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
 575                          screen->post_dsp_stx, screen->post_xsize, x_res);
 576                 screen->post_dsp_stx = x_res - screen->post_xsize;
 577         }
 578         if (screen->x_mirror == 0) {
 579                 post_dsp_hact_st = screen->post_dsp_stx +
 580                     screen->mode.hsync_len + screen->mode.left_margin;
 581                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 582         } else {
 583                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 584                     screen->post_dsp_stx;
 585                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 586         }
 587         if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
 588                 post_hsd_en = 1;
 589                 post_h_fac =
 590                     GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
 591         } else {
 592                 post_hsd_en = 0;
 593                 post_h_fac = 0x1000;
 594         }
 595
 596         if (screen->post_dsp_sty + screen->post_ysize > y_res) {
 597                 dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
 598                          screen->post_dsp_sty, screen->post_ysize, y_res);
 599                 screen->post_dsp_sty = y_res - screen->post_ysize;
 600         }
 601
 602         if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
 603                 post_vsd_en = 1;
 604                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
 605                                                       screen->post_ysize);
 606         } else {
 607                 post_vsd_en = 0;
 608                 post_v_fac = 0x1000;
 609         }
 610
 611         if (screen->mode.vmode & FB_VMODE_INTERLACED) {
 612                 post_dsp_vact_st = screen->post_dsp_sty / 2 +
 613                                         screen->mode.vsync_len +
 614                                         screen->mode.upper_margin;
 615                 post_dsp_vact_end = post_dsp_vact_st +
 616                                         screen->post_ysize / 2;
 617
 618                 post_dsp_vact_st_f1 = screen->mode.vsync_len +
 619                                       screen->mode.upper_margin +
 620                                       y_res/2 +
 621                                       screen->mode.lower_margin +
 622                                       screen->mode.vsync_len +
 623                                       screen->mode.upper_margin +
 624                                       screen->post_dsp_sty / 2 +
 625                                       1;
 626                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
 627                                         screen->post_ysize/2;
 628         } else {
 629                 if (screen->y_mirror == 0) {
 630                         post_dsp_vact_st = screen->post_dsp_sty +
 631                             screen->mode.vsync_len +
 632                             screen->mode.upper_margin;
 633                         post_dsp_vact_end = post_dsp_vact_st +
 634                                 screen->post_ysize;
 635                 } else {
 636                         post_dsp_vact_end = v_total -
 637                                 screen->mode.lower_margin -
 638                             screen->post_dsp_sty;
 639                         post_dsp_vact_st = post_dsp_vact_end -
 640                                 screen->post_ysize;
 641                 }
 642                 post_dsp_vact_st_f1 = 0;
 643                 post_dsp_vact_end_f1 = 0;
 644         }
 645         DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
 646             screen->post_xsize, screen->post_ysize, screen->xpos);
 647         DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 648             screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
 649         mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
 650         val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
 651             v_DSP_HACT_ST_POST(post_dsp_hact_st);
 652         lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
 653
 654         mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
 655         val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
 656             v_DSP_VACT_ST_POST(post_dsp_vact_st);
 657         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
 658
 659         mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
 660         val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
 661             v_POST_VS_FACTOR_YRGB(post_v_fac);
 662         lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
 663
 664         mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
 665         val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
 666             v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
 667         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
 668
 669         mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
 670         val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
 671         lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
 672         return 0;
 673 }
 674
 675 static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 676 {
 677         struct lcdc_device *lcdc_dev =
 678             container_of(dev_drv, struct lcdc_device, driver);
 679         struct rk_lcdc_win *win;
 680         u32 colorkey_r, colorkey_g, colorkey_b;
 681         int i, key_val;
 682
 683         for (i = 0; i < 4; i++) {
 684                 win = dev_drv->win[i];
 685                 key_val = win->color_key_val;
 686                 colorkey_r = (key_val & 0xff) << 2;
 687                 colorkey_g = ((key_val >> 8) & 0xff) << 12;
 688                 colorkey_b = ((key_val >> 16) & 0xff) << 22;
 689                 /*color key dither 565/888->aaa */
 690                 key_val = colorkey_r | colorkey_g | colorkey_b;
 691                 switch (i) {
 692                 case 0:
 693                         lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
 694                         break;
 695                 case 1:
 696                         lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
 697                         break;
 698                 case 2:
 699                         lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
 700                         break;
 701                 case 3:
 702                         lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
 703                         break;
 704                 default:
 705                         pr_info("%s:un support win num:%d\n",
 706                                 __func__, i);
 707                         break;
 708                 }
 709         }
 710         return 0;
 711 }
 712
 713 static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
 714 {
 715         struct lcdc_device *lcdc_dev =
 716             container_of(dev_drv, struct lcdc_device, driver);
 717         struct rk_lcdc_win *win = dev_drv->win[win_id];
 718         struct alpha_config alpha_config;
 719         u32 mask, val;
 720         int ppixel_alpha = 0, global_alpha = 0, i;
 721         u32 src_alpha_ctl, dst_alpha_ctl;
 722
 723         for (i = 0; i < win->area_num; i++) {
 724                 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
 725                                  (win->area[i].format == FBDC_ARGB_888) ||
 726                                  (win->area[i].format == FBDC_ABGR_888) ||
 727                                  (win->area[i].format == ABGR888)) ? 1 : 0;
 728         }
 729         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 730         alpha_config.src_global_alpha_val = win->g_alpha_val;
 731         win->alpha_mode = AB_SRC_OVER;
 732         switch (win->alpha_mode) {
 733         case AB_USER_DEFINE:
 734                 break;
 735         case AB_CLEAR:
 736                 alpha_config.src_factor_mode = AA_ZERO;
 737                 alpha_config.dst_factor_mode = AA_ZERO;
 738                 break;
 739         case AB_SRC:
 740                 alpha_config.src_factor_mode = AA_ONE;
 741                 alpha_config.dst_factor_mode = AA_ZERO;
 742                 break;
 743         case AB_DST:
 744                 alpha_config.src_factor_mode = AA_ZERO;
 745                 alpha_config.dst_factor_mode = AA_ONE;
 746                 break;
 747         case AB_SRC_OVER:
 748                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 749                 if (global_alpha)
 750                         alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 751                 else
 752                         alpha_config.src_factor_mode = AA_ONE;
 753                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 754                 break;
 755         case AB_DST_OVER:
 756                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 757                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 758                 alpha_config.dst_factor_mode = AA_ONE;
 759                 break;
 760         case AB_SRC_IN:
 761                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 762                 alpha_config.src_factor_mode = AA_SRC;
 763                 alpha_config.dst_factor_mode = AA_ZERO;
 764                 break;
 765         case AB_DST_IN:
 766                 alpha_config.src_factor_mode = AA_ZERO;
 767                 alpha_config.dst_factor_mode = AA_SRC;
 768                 break;
 769         case AB_SRC_OUT:
 770                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 771                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 772                 alpha_config.dst_factor_mode = AA_ZERO;
 773                 break;
 774         case AB_DST_OUT:
 775                 alpha_config.src_factor_mode = AA_ZERO;
 776                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 777                 break;
 778         case AB_SRC_ATOP:
 779                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 780                 alpha_config.src_factor_mode = AA_SRC;
 781                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 782                 break;
 783         case AB_DST_ATOP:
 784                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 785                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 786                 alpha_config.dst_factor_mode = AA_SRC;
 787                 break;
 788         case XOR:
 789                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 790                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 791                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 792                 break;
 793         case AB_SRC_OVER_GLOBAL:
 794                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 795                 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
 796                 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 797                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 798                 break;
 799         default:
 800                 pr_err("alpha mode error\n");
 801                 break;
 802         }
 803         if ((ppixel_alpha == 1) && (global_alpha == 1))
 804                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 805         else if (ppixel_alpha == 1)
 806                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 807         else if (global_alpha == 1)
 808                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 809         else
 810                 dev_warn(lcdc_dev->dev, "alpha_en should be 0\n");
 811         alpha_config.src_alpha_mode = AA_STRAIGHT;
 812         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 813
 814         switch (win_id) {
 815         case 0:
 816                 src_alpha_ctl = 0x60;
 817                 dst_alpha_ctl = 0x64;
 818                 break;
 819         case 1:
 820                 src_alpha_ctl = 0xa0;
 821                 dst_alpha_ctl = 0xa4;
 822                 break;
 823         case 2:
 824                 src_alpha_ctl = 0xdc;
 825                 dst_alpha_ctl = 0xec;
 826                 break;
 827         case 3:
 828                 src_alpha_ctl = 0x12c;
 829                 dst_alpha_ctl = 0x13c;
 830                 break;
 831         case 4:
 832                 src_alpha_ctl = 0x160;
 833                 dst_alpha_ctl = 0x164;
 834                 break;
 835         }
 836         mask = m_WIN0_DST_FACTOR_M0;
 837         val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
 838         lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
 839         mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
 840             m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
 841             m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 |
 842             m_WIN0_SRC_GLOBAL_ALPHA;
 843         val = v_WIN0_SRC_ALPHA_EN(1) |
 844             v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
 845             v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
 846             v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
 847             v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
 848             v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
 849             v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 850         lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
 851
 852         return 0;
 853 }
 854
 855 static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num)
 856 {
 857         struct rk_lcdc_win_area area_temp;
 858         int i, j;
 859
 860         for (i = 0; i < area_num; i++) {
 861                 for (j = i + 1; j < area_num; j++) {
 862                         if (win->area[i].dsp_stx >  win->area[j].dsp_stx) {
 863                                 memcpy(&area_temp, &win->area[i],
 864                                        sizeof(struct rk_lcdc_win_area));
 865                                 memcpy(&win->area[i], &win->area[j],
 866                                        sizeof(struct rk_lcdc_win_area));
 867                                 memcpy(&win->area[j], &area_temp,
 868                                        sizeof(struct rk_lcdc_win_area));
 869                         }
 870                 }
 871         }
 872
 873         return 0;
 874 }
 875
 876 static int __maybe_unused
 877         rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num)
 878 {
 879         struct rk_lcdc_win_area area_temp;
 880
 881         switch (area_num) {
 882         case 2:
 883                 area_temp = win->area[0];
 884                 win->area[0] = win->area[1];
 885                 win->area[1] = area_temp;
 886                 break;
 887         case 3:
 888                 area_temp = win->area[0];
 889                 win->area[0] = win->area[2];
 890                 win->area[2] = area_temp;
 891                 break;
 892         case 4:
 893                 area_temp = win->area[0];
 894                 win->area[0] = win->area[3];
 895                 win->area[3] = area_temp;
 896
 897                 area_temp = win->area[1];
 898                 win->area[1] = win->area[2];
 899                 win->area[2] = area_temp;
 900                 break;
 901         default:
 902                 pr_info("un supported area num!\n");
 903                 break;
 904         }
 905         return 0;
 906 }
 907
 908 static int __maybe_unused
 909 rk3368_win_area_check_var(int win_id, int area_num,
 910                           struct rk_lcdc_win_area *area_pre,
 911                           struct rk_lcdc_win_area *area_now)
 912 {
 913         if ((area_pre->xpos > area_now->xpos) ||
 914             ((area_pre->xpos + area_pre->xsize > area_now->xpos) &&
 915              (area_pre->ypos + area_pre->ysize > area_now->ypos))) {
 916                 area_now->state = 0;
 917                 pr_err("win[%d]:\n"
 918                        "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n"
 919                        "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n",
 920                        win_id,
 921                        area_num - 1, area_pre->xpos, area_pre->xsize,
 922                        area_pre->ypos, area_pre->ysize,
 923                        area_num, area_now->xpos, area_now->xsize,
 924                        area_now->ypos, area_now->ysize);
 925                 return -EINVAL;
 926         }
 927         return 0;
 928 }
 929
 930 static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv)
 931 {
 932         struct lcdc_device *lcdc_dev =
 933             container_of(dev_drv, struct lcdc_device, driver);
 934         u32 val, i;
 935
 936         for (i = 0; i < 100; i++) {
 937                 val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0);
 938                 val &= m_DBG_IFBDC_IDLE;
 939                 if (val)
 940                         continue;
 941                 else
 942                         mdelay(10);
 943         };
 944         return val;
 945 }
 946
 947 static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
 948 {
 949         struct lcdc_device *lcdc_dev =
 950             container_of(dev_drv, struct lcdc_device, driver);
 951         struct rk_lcdc_win *win = dev_drv->win[win_id];
 952         u32 mask, val;
 953
 954         if (lcdc_dev->soc_type != VOP_FULL_RK3368) {
 955                 pr_err("soc: 0x%08x not support FBDC\n", lcdc_dev->soc_type);
 956                 return 0;
 957         }
 958         mask = m_IFBDC_CTRL_FBDC_COR_EN |
 959             m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE |
 960             m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO;
 961         val = v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) |
 962             v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) |
 963             v_IFBDC_CTRL_FBDC_ROTATION_MODE((win->xmirror &&
 964                                              win->ymirror) << 1) |
 965             v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) |
 966             v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio);
 967         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
 968
 969         mask = m_IFBDC_TILES_NUM;
 970         val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles);
 971         lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val);
 972
 973         mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT;
 974         val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) |
 975             v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height);
 976         lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val);
 977
 978         mask = m_IFBDC_CMP_INDEX_INIT;
 979         val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init);
 980         lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val);
 981
 982         mask = m_IFBDC_MB_VIR_WIDTH;
 983         val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width);
 984         lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val);
 985
 986         return 0;
 987 }
 988
 989 static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id)
 990 {
 991         struct lcdc_device *lcdc_dev =
 992             container_of(dev_drv, struct lcdc_device, driver);
 993         struct rk_lcdc_win *win = dev_drv->win[win_id];
 994         u8 fbdc_dsp_width_ratio;
 995         u16 fbdc_mb_vir_width, fbdc_mb_vir_height;
 996         u16 fbdc_mb_width, fbdc_mb_height;
 997         u16 fbdc_mb_xst, fbdc_mb_yst, fbdc_num_tiles;
 998         u16 fbdc_cmp_index_init;
 999         u8 mb_w_size, mb_h_size;
1000         struct rk_screen *screen = dev_drv->cur_screen;
1001
1002         if (screen->mode.flag & FB_VMODE_INTERLACED) {
1003                 dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n");
1004                 return 0;
1005         }
1006
1007         if (lcdc_dev->soc_type != VOP_FULL_RK3368) {
1008                 pr_err("soc: 0x%08x not support FBDC\n", lcdc_dev->soc_type);
1009                 return 0;
1010         }
1011         switch (win->area[0].fmt_cfg) {
1012         case VOP_FORMAT_ARGB888:
1013                 fbdc_dsp_width_ratio = 0;
1014                 mb_w_size = 16;
1015                 break;
1016         case VOP_FORMAT_RGB888:
1017                 fbdc_dsp_width_ratio = 0;
1018                 mb_w_size = 16;
1019                 break;
1020         case VOP_FORMAT_RGB565:
1021                 fbdc_dsp_width_ratio = 1;
1022                 mb_w_size = 32;
1023                 break;
1024         default:
1025                 dev_err(lcdc_dev->dev,
1026                         "in fbdc mode,unsupport fmt:%d!\n",
1027                         win->area[0].fmt_cfg);
1028                 break;
1029         }
1030         mb_h_size = 4;
1031
1032         /*macro block xvir and yvir */
1033         if ((win->area[0].xvir % mb_w_size == 0) &&
1034             (win->area[0].yvir % mb_h_size == 0)) {
1035                 fbdc_mb_vir_width = win->area[0].xvir / mb_w_size;
1036                 fbdc_mb_vir_height = win->area[0].yvir / mb_h_size;
1037         } else {
1038                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
1039                 pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n",
1040                        win->area[0].xvir, win->area[0].yvir,
1041                        mb_w_size, mb_h_size);
1042         }
1043         /*macro block xact and yact */
1044         if ((win->area[0].xact % mb_w_size == 0) &&
1045             (win->area[0].yact % mb_h_size == 0)) {
1046                 fbdc_mb_width = win->area[0].xact / mb_w_size;
1047                 fbdc_mb_height = win->area[0].yact / mb_h_size;
1048         } else {
1049                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
1050                 pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n",
1051                        win->area[0].xact, win->area[0].yact,
1052                        mb_w_size, mb_h_size);
1053         }
1054         /*macro block xoff and yoff */
1055         if ((win->area[0].xoff % mb_w_size == 0) &&
1056             (win->area[0].yoff % mb_h_size == 0)) {
1057                 fbdc_mb_xst = win->area[0].xoff / mb_w_size;
1058                 fbdc_mb_yst = win->area[0].yoff / mb_h_size;
1059         } else {
1060                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
1061                 pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n",
1062                        win->area[0].xoff, win->area[0].yoff,
1063                        mb_w_size, mb_h_size);
1064         }
1065
1066         /*FBDC tiles */
1067         fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height;
1068
1069         /*
1070            switch (fbdc_rotation_mode)  {
1071            case FBDC_ROT_NONE:
1072            fbdc_cmp_index_init =
1073            (fbdc_mb_yst*fbdc_mb_vir_width) +  fbdc_mb_xst;
1074            break;
1075            case FBDC_X_MIRROR:
1076            fbdc_cmp_index_init =
1077            (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+
1078            (fbdc_mb_width-1));
1079            break;
1080            case FBDC_Y_MIRROR:
1081            fbdc_cmp_index_init =
1082            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width)  +
1083            fbdc_mb_xst;
1084            break;
1085            case FBDC_ROT_180:
1086            fbdc_cmp_index_init =
1087            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
1088            (fbdc_mb_xst+(fbdc_mb_width-1));
1089            break;
1090            }
1091          */
1092         if (win->xmirror && win->ymirror && ((win_id == 2) || (win_id == 3))) {
1093                 fbdc_cmp_index_init =
1094                     ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) +
1095                     (fbdc_mb_xst + (fbdc_mb_width - 1));
1096         } else {
1097                 fbdc_cmp_index_init =
1098                     (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst;
1099         }
1100         /*fbdc fmt maybe need to change*/
1101         win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio;
1102         win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width;
1103         win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height;
1104         win->area[0].fbdc_mb_width = fbdc_mb_width;
1105         win->area[0].fbdc_mb_height = fbdc_mb_height;
1106         win->area[0].fbdc_mb_xst = fbdc_mb_xst;
1107         win->area[0].fbdc_mb_yst = fbdc_mb_yst;
1108         win->area[0].fbdc_num_tiles = fbdc_num_tiles;
1109         win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init;
1110
1111         return 0;
1112 }
1113
1114 static int rk3368_lcdc_axi_gather_cfg(struct lcdc_device *lcdc_dev,
1115                                       struct rk_lcdc_win *win)
1116 {
1117         u32 mask, val;
1118         u16 yrgb_gather_num = 3;
1119         u16 cbcr_gather_num = 1;
1120
1121         switch (win->area[0].format) {
1122         case ARGB888:
1123         case XBGR888:
1124         case XRGB888:
1125         case ABGR888:
1126         case FBDC_ARGB_888:
1127         case FBDC_RGBX_888:
1128         case FBDC_ABGR_888:
1129                 yrgb_gather_num = 3;
1130                 break;
1131         case RGB888:
1132         case RGB565:
1133         case BGR888:
1134         case BGR565:
1135         case FBDC_RGB_565:
1136                 yrgb_gather_num = 2;
1137                 break;
1138         case YUV444:
1139         case YUV422:
1140         case YUV420:
1141         case YUV420_NV21:
1142                 yrgb_gather_num = 1;
1143                 cbcr_gather_num = 2;
1144                 break;
1145         default:
1146                 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
1147                         __func__);
1148                 return -EINVAL;
1149         }
1150
1151         if ((win->id == 0) || (win->id == 1)) {
1152                 mask = m_WIN0_YRGB_AXI_GATHER_EN | m_WIN0_CBR_AXI_GATHER_EN |
1153                         m_WIN0_YRGB_AXI_GATHER_NUM | m_WIN0_CBR_AXI_GATHER_NUM;
1154                 val = v_WIN0_YRGB_AXI_GATHER_EN(1) |
1155                         v_WIN0_CBR_AXI_GATHER_EN(1) |
1156                         v_WIN0_YRGB_AXI_GATHER_NUM(yrgb_gather_num) |
1157                         v_WIN0_CBR_AXI_GATHER_NUM(cbcr_gather_num);
1158                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + (win->id * 0x40),
1159                              mask, val);
1160         } else if ((win->id == 2) || (win->id == 3)) {
1161                 mask = m_WIN2_AXI_GATHER_EN | m_WIN2_AXI_GATHER_NUM;
1162                 val = v_WIN2_AXI_GATHER_EN(1) |
1163                         v_WIN2_AXI_GATHER_NUM(yrgb_gather_num);
1164                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL1 + ((win->id - 2) * 0x50),
1165                              mask, val);
1166         } else if (win->id == 4) {
1167                 mask = m_HWC_AXI_GATHER_EN | m_HWC_AXI_GATHER_NUM;
1168                 val = v_HWC_AXI_GATHER_EN(1) |
1169                         v_HWC_AXI_GATHER_NUM(yrgb_gather_num);
1170                 lcdc_msk_reg(lcdc_dev, HWC_CTRL1, mask, val);
1171         }
1172         return 0;
1173 }
1174
1175 static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev,
1176                                  struct rk_lcdc_win *win)
1177 {
1178         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1179         struct rk_screen *screen = dev_drv->cur_screen;
1180
1181         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1182                 switch (win->area[0].fmt_cfg) {
1183                 case VOP_FORMAT_ARGB888:
1184                 case VOP_FORMAT_RGB888:
1185                 case VOP_FORMAT_RGB565:
1186                         if ((screen->mode.xres < 1280) &&
1187                             (screen->mode.yres < 720)) {
1188                                 win->csc_mode = VOP_R2Y_CSC_BT601;
1189                         } else {
1190                                 win->csc_mode = VOP_R2Y_CSC_BT709;
1191                         }
1192                         break;
1193                 default:
1194                         break;
1195                 }
1196         } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
1197                 switch (win->area[0].fmt_cfg) {
1198                 case VOP_FORMAT_YCBCR420:
1199                         if ((win->id == 0) || (win->id == 1))
1200                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
1201                         break;
1202                 default:
1203                         break;
1204                 }
1205         }
1206 }
1207
1208 static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1209 {
1210         struct lcdc_device *lcdc_dev =
1211             container_of(dev_drv, struct lcdc_device, driver);
1212         struct rk_lcdc_win *win = dev_drv->win[win_id];
1213         unsigned int mask, val, off;
1214
1215         off = win_id * 0x40;
1216         /*if(win->win_lb_mode == 5)
1217            win->win_lb_mode = 4;
1218            for rk3288 to fix hw bug? */
1219
1220         if (win->state == 1) {
1221                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1222                 rk3368_lcdc_axi_gather_cfg(lcdc_dev, win);
1223                 if (win->area[0].fbdc_en)
1224                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1225                 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
1226                         m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR |
1227                         m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE | m_WIN0_UV_SWAP;
1228                 val = v_WIN0_EN(win->state) |
1229                         v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1230                         v_WIN0_FMT_10(win->fmt_10) |
1231                         v_WIN0_LB_MODE(win->win_lb_mode) |
1232                         v_WIN0_RB_SWAP(win->area[0].swap_rb) |
1233                         v_WIN0_X_MIRROR(win->xmirror) |
1234                         v_WIN0_Y_MIRROR(win->ymirror) |
1235                         v_WIN0_CSC_MODE(win->csc_mode) |
1236                         v_WIN0_UV_SWAP(win->area[0].swap_uv);
1237                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1238
1239                 mask = m_WIN0_BIC_COE_SEL |
1240                     m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
1241                     m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
1242                     m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
1243                     m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
1244                     m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
1245                     m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
1246                     m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
1247                 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1248                     v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1249                     v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1250                     v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1251                     v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1252                     v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1253                     v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1254                     v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1255                     v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1256                     v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1257                     v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1258                     v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1259                     v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1260                     v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1261                     v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1262                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val);
1263                 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1264                     v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1265                 lcdc_writel(lcdc_dev, WIN0_VIR + off, val);
1266                 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off,
1267                                 win->area[0].y_addr);
1268                    lcdc_writel(lcdc_dev, WIN0_CBR_MST+off,
1269                                 win->area[0].uv_addr); */
1270                 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
1271                     v_WIN0_ACT_HEIGHT(win->area[0].yact);
1272                 lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val);
1273
1274                 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
1275                     v_WIN0_DSP_HEIGHT(win->area[0].ysize);
1276                 lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val);
1277
1278                 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
1279                     v_WIN0_DSP_YST(win->area[0].dsp_sty);
1280                 lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val);
1281
1282                 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1283                     v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1284                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1285
1286                 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1287                     v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1288                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val);
1289                 if (win->alpha_en == 1) {
1290                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1291                 } else {
1292                         mask = m_WIN0_SRC_ALPHA_EN;
1293                         val = v_WIN0_SRC_ALPHA_EN(0);
1294                         lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off,
1295                                      mask, val);
1296                 }
1297
1298                 if (dev_drv->cur_screen->mode.vmode & FB_VMODE_INTERLACED) {
1299                         mask = m_WIN0_YRGB_DEFLICK | m_WIN0_CBR_DEFLICK;
1300                         if (win->area[0].yact == 2 * win->area[0].ysize)
1301                                 val = v_WIN0_YRGB_DEFLICK(0) |
1302                                         v_WIN0_CBR_DEFLICK(0);
1303                         else
1304                                 val = v_WIN0_YRGB_DEFLICK(1) |
1305                                         v_WIN0_CBR_DEFLICK(1);
1306                         lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1307                 }
1308         } else {
1309                 mask = m_WIN0_EN;
1310                 val = v_WIN0_EN(win->state);
1311                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1312         }
1313         return 0;
1314 }
1315
1316 static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1317 {
1318         struct lcdc_device *lcdc_dev =
1319             container_of(dev_drv, struct lcdc_device, driver);
1320         struct rk_lcdc_win *win = dev_drv->win[win_id];
1321         unsigned int mask, val, off;
1322
1323         off = (win_id - 2) * 0x50;
1324         rk3368_lcdc_area_xst(win, win->area_num);
1325
1326         if (win->state == 1) {
1327                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1328                 rk3368_lcdc_axi_gather_cfg(lcdc_dev, win);
1329                 if (win->area[0].fbdc_en)
1330                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1331
1332                 mask = m_WIN2_EN | m_WIN2_CSC_MODE;
1333                 val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode);
1334                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1335                 /*area 0 */
1336                 if (win->area[0].state == 1) {
1337                         mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 |
1338                             m_WIN2_RB_SWAP0;
1339                         val = v_WIN2_MST0_EN(win->area[0].state) |
1340                             v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1341                             v_WIN2_RB_SWAP0(win->area[0].swap_rb);
1342                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1343
1344                         mask = m_WIN2_VIR_STRIDE0;
1345                         val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1346                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1347
1348                         /*lcdc_writel(lcdc_dev,WIN2_MST0+off,
1349                            win->area[0].y_addr); */
1350                         val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1351                             v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1352                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val);
1353                         val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1354                             v_WIN2_DSP_YST0(win->area[0].dsp_sty);
1355                         lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val);
1356                 } else {
1357                         mask = m_WIN2_MST0_EN;
1358                         val = v_WIN2_MST0_EN(0);
1359                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1360                 }
1361                 /*area 1 */
1362                 if (win->area[1].state == 1) {
1363                         /*rk3368_win_area_check_var(win_id, 1,
1364                                                   &win->area[0], &win->area[1]);
1365                         */
1366
1367                         mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 |
1368                             m_WIN2_RB_SWAP1;
1369                         val = v_WIN2_MST1_EN(win->area[1].state) |
1370                             v_WIN2_DATA_FMT1(win->area[1].fmt_cfg) |
1371                             v_WIN2_RB_SWAP1(win->area[1].swap_rb);
1372                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1373
1374                         mask = m_WIN2_VIR_STRIDE1;
1375                         val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1376                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1377
1378                         /*lcdc_writel(lcdc_dev,WIN2_MST1+off,
1379                            win->area[1].y_addr); */
1380                         val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1381                             v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1382                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val);
1383                         val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1384                             v_WIN2_DSP_YST1(win->area[1].dsp_sty);
1385                         lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val);
1386                 } else {
1387                         mask = m_WIN2_MST1_EN;
1388                         val = v_WIN2_MST1_EN(0);
1389                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1390                 }
1391                 /*area 2 */
1392                 if (win->area[2].state == 1) {
1393                         /*rk3368_win_area_check_var(win_id, 2,
1394                                                   &win->area[1], &win->area[2]);
1395                         */
1396
1397                         mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 |
1398                             m_WIN2_RB_SWAP2;
1399                         val = v_WIN2_MST2_EN(win->area[2].state) |
1400                             v_WIN2_DATA_FMT2(win->area[2].fmt_cfg) |
1401                             v_WIN2_RB_SWAP2(win->area[2].swap_rb);
1402                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1403
1404                         mask = m_WIN2_VIR_STRIDE2;
1405                         val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1406                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1407
1408                         /*lcdc_writel(lcdc_dev,WIN2_MST2+off,
1409                            win->area[2].y_addr); */
1410                         val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1411                             v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1412                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val);
1413                         val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1414                             v_WIN2_DSP_YST2(win->area[2].dsp_sty);
1415                         lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val);
1416                 } else {
1417                         mask = m_WIN2_MST2_EN;
1418                         val = v_WIN2_MST2_EN(0);
1419                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1420                 }
1421                 /*area 3 */
1422                 if (win->area[3].state == 1) {
1423                         /*rk3368_win_area_check_var(win_id, 3,
1424                                                   &win->area[2], &win->area[3]);
1425                         */
1426
1427                         mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 |
1428                             m_WIN2_RB_SWAP3;
1429                         val = v_WIN2_MST3_EN(win->area[3].state) |
1430                             v_WIN2_DATA_FMT3(win->area[3].fmt_cfg) |
1431                             v_WIN2_RB_SWAP3(win->area[3].swap_rb);
1432                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1433
1434                         mask = m_WIN2_VIR_STRIDE3;
1435                         val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1436                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1437
1438                         /*lcdc_writel(lcdc_dev,WIN2_MST3+off,
1439                            win->area[3].y_addr); */
1440                         val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1441                             v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1442                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val);
1443                         val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1444                             v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1445                         lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val);
1446                 } else {
1447                         mask = m_WIN2_MST3_EN;
1448                         val = v_WIN2_MST3_EN(0);
1449                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1450                 }
1451
1452                 if (win->alpha_en == 1) {
1453                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1454                 } else {
1455                         mask = m_WIN2_SRC_ALPHA_EN;
1456                         val = v_WIN2_SRC_ALPHA_EN(0);
1457                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off,
1458                                      mask, val);
1459                 }
1460         } else {
1461                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1462                     m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1463                 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1464                     v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1465                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1466         }
1467         return 0;
1468 }
1469
1470 static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1471 {
1472         struct lcdc_device *lcdc_dev =
1473             container_of(dev_drv, struct lcdc_device, driver);
1474         struct rk_lcdc_win *win = dev_drv->win[win_id];
1475         unsigned int mask, val, hwc_size = 0;
1476
1477         if (win->state == 1) {
1478                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1479                 rk3368_lcdc_axi_gather_cfg(lcdc_dev, win);
1480                 mask = m_HWC_EN | m_HWC_DATA_FMT |
1481                     m_HWC_RB_SWAP | m_WIN0_CSC_MODE;
1482                 val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1483                     v_HWC_RB_SWAP(win->area[0].swap_rb) |
1484                     v_WIN0_CSC_MODE(win->csc_mode);
1485                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1486
1487                 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1488                         hwc_size = 0;
1489                 else if ((win->area[0].xsize == 64) &&
1490                          (win->area[0].ysize == 64))
1491                         hwc_size = 1;
1492                 else if ((win->area[0].xsize == 96) &&
1493                          (win->area[0].ysize == 96))
1494                         hwc_size = 2;
1495                 else if ((win->area[0].xsize == 128) &&
1496                          (win->area[0].ysize == 128))
1497                         hwc_size = 3;
1498                 else
1499                         dev_err(lcdc_dev->dev, "un supported hwc size!\n");
1500
1501                 mask = m_HWC_SIZE;
1502                 val = v_HWC_SIZE(hwc_size);
1503                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1504
1505                 mask = m_HWC_DSP_XST | m_HWC_DSP_YST;
1506                 val = v_HWC_DSP_XST(win->area[0].dsp_stx) |
1507                     v_HWC_DSP_YST(win->area[0].dsp_sty);
1508                 lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val);
1509
1510                 if (win->alpha_en == 1) {
1511                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1512                 } else {
1513                         mask = m_WIN2_SRC_ALPHA_EN;
1514                         val = v_WIN2_SRC_ALPHA_EN(0);
1515                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val);
1516                 }
1517         } else {
1518                 mask = m_HWC_EN;
1519                 val = v_HWC_EN(win->state);
1520                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1521         }
1522         return 0;
1523 }
1524
1525 static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
1526                                          struct rk_lcdc_win *win)
1527 {
1528         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1529         int timeout;
1530         unsigned long flags;
1531
1532         if (likely(lcdc_dev->clk_on)) {
1533                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1534                              v_STANDBY_EN(lcdc_dev->standby));
1535                 if ((win->id == 0) || (win->id == 1))
1536                         rk3368_win_0_1_reg_update(dev_drv, win->id);
1537                 else if ((win->id == 2) || (win->id == 3))
1538                         rk3368_win_2_3_reg_update(dev_drv, win->id);
1539                 else if (win->id == 4)
1540                         rk3368_hwc_reg_update(dev_drv, win->id);
1541                 /*rk3368_lcdc_post_cfg(dev_drv); */
1542                 lcdc_cfg_done(lcdc_dev);
1543         }
1544
1545         /*if (dev_drv->wait_fs) { */
1546         if (0) {
1547                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1548                 init_completion(&dev_drv->frame_done);
1549                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1550                 timeout =
1551                     wait_for_completion_timeout(&dev_drv->frame_done,
1552                                                 msecs_to_jiffies
1553                                                 (dev_drv->cur_screen->ft + 5));
1554                 if (!timeout && (!dev_drv->frame_done.done)) {
1555                         dev_warn(lcdc_dev->dev,
1556                                  "wait for new frame start time out!\n");
1557                         return -ETIMEDOUT;
1558                 }
1559         }
1560         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1561         return 0;
1562 }
1563
1564 static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1565 {
1566         memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x270);
1567         return 0;
1568 }
1569
1570 static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1571 {
1572         u32 mask, val;
1573         struct lcdc_device *lcdc_dev =
1574             container_of(dev_drv, struct lcdc_device, driver);
1575
1576         if (unlikely(!lcdc_dev->clk_on)) {
1577                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
1578                 return 0;
1579         }
1580         if (dev_drv->iommu_enabled) {
1581                 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1582                         if (likely(lcdc_dev->clk_on)) {
1583                                 mask = m_MMU_EN;
1584                                 val = v_MMU_EN(1);
1585                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1586                                 mask = m_AXI_MAX_OUTSTANDING_EN |
1587                                         m_AXI_OUTSTANDING_MAX_NUM;
1588                                 val = v_AXI_OUTSTANDING_MAX_NUM(31) |
1589                                         v_AXI_MAX_OUTSTANDING_EN(1);
1590                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1591                         }
1592                         lcdc_dev->iommu_status = 1;
1593                         rockchip_iovmm_activate(dev_drv->dev);
1594                 }
1595         }
1596         return 0;
1597 }
1598
1599 static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate)
1600 {
1601         int ret = 0, fps = 0;
1602         struct lcdc_device *lcdc_dev =
1603             container_of(dev_drv, struct lcdc_device, driver);
1604         struct rk_screen *screen = dev_drv->cur_screen;
1605 #ifdef CONFIG_RK_FPGA
1606         return 0;
1607 #endif
1608         if (reset_rate)
1609                 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
1610         if (ret)
1611                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1612         lcdc_dev->pixclock =
1613             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1614         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1615
1616         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1617         screen->ft = 1000 / fps;
1618         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1619                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1620         return 0;
1621 }
1622
1623 static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv)
1624 {
1625         struct lcdc_device *lcdc_dev =
1626             container_of(dev_drv, struct lcdc_device, driver);
1627         struct rk_screen *screen = dev_drv->cur_screen;
1628         u16 hsync_len = screen->mode.hsync_len;
1629         u16 left_margin = screen->mode.left_margin;
1630         u16 right_margin = screen->mode.right_margin;
1631         u16 vsync_len = screen->mode.vsync_len;
1632         u16 upper_margin = screen->mode.upper_margin;
1633         u16 lower_margin = screen->mode.lower_margin;
1634         u16 x_res = screen->mode.xres;
1635         u16 y_res = screen->mode.yres;
1636         u32 mask, val;
1637         u16 h_total, v_total;
1638         u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1639         u32 frame_time;
1640         u32 line_flag_reg;
1641
1642         if (lcdc_dev->soc_type == VOP_FULL_RK3366)
1643                 line_flag_reg = LINE_FLAG_RK3366;
1644         else
1645                 line_flag_reg = LINE_FLAG_RK3368;
1646
1647         h_total = hsync_len + left_margin + x_res + right_margin;
1648         v_total = vsync_len + upper_margin + y_res + lower_margin;
1649         frame_time = 1000 * v_total * h_total / (screen->mode.pixclock / 1000);
1650         mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1651         val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1652         lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1653
1654         mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1655         val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1656             v_DSP_HACT_ST(hsync_len + left_margin);
1657         lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1658
1659         if (screen->mode.vmode & FB_VMODE_INTERLACED) {
1660                 /* First Field Timing */
1661                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1662                 val = v_DSP_VS_PW(vsync_len) |
1663                     v_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1664                                       lower_margin) + y_res + 1);
1665                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1666
1667                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1668                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1669                     v_DSP_VACT_ST(vsync_len + upper_margin);
1670                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1671
1672                 /* Second Field Timing */
1673                 mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1;
1674                 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1675                 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1676                     lower_margin;
1677                 val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1);
1678                 lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val);
1679
1680                 mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1;
1681                 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1682                     lower_margin + 1;
1683                 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1684                     lower_margin + 1;
1685                 val =
1686                     v_DSP_VACT_END_F1(vact_end_f1) |
1687                     v_DSP_VAC_ST_F1(vact_st_f1);
1688                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val);
1689
1690                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1691                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1692                              v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0));
1693                 if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
1694                         if (y_res <= 576)
1695                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1696                                              m_SW_CORE_DCLK_SEL,
1697                                              v_SW_CORE_DCLK_SEL(1));
1698                         else
1699                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1700                                              m_SW_CORE_DCLK_SEL,
1701                                              v_SW_CORE_DCLK_SEL(0));
1702                 }
1703                 mask =
1704                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1705                     m_WIN0_CBR_DEFLICK;
1706                 val =
1707                     v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(0) |
1708                     v_WIN0_CBR_DEFLICK(0);
1709                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1710
1711                 mask =
1712                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1713                     m_WIN1_CBR_DEFLICK;
1714                 val =
1715                     v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(0) |
1716                     v_WIN1_CBR_DEFLICK(0);
1717                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1718
1719                 mask = m_WIN2_INTERLACE_READ;
1720                 val = v_WIN2_INTERLACE_READ(1);
1721                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1722
1723                 mask = m_WIN3_INTERLACE_READ;
1724                 val = v_WIN3_INTERLACE_READ(1);
1725                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1726
1727                 mask = m_HWC_INTERLACE_READ;
1728                 val = v_HWC_INTERLACE_READ(1);
1729                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1730
1731                 mask = m_DSP_LINE_FLAG0_NUM | m_DSP_LINE_FLAG1_NUM;
1732                 val =
1733                     v_DSP_LINE_FLAG0_NUM(vact_end_f1) |
1734                     v_DSP_LINE_FLAG1_NUM(vact_end_f1 -
1735                                          EARLY_TIME * v_total / frame_time);
1736                 lcdc_msk_reg(lcdc_dev, line_flag_reg, mask, val);
1737         } else {
1738                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1739                 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1740                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1741
1742                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1743                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1744                     v_DSP_VACT_ST(vsync_len + upper_margin);
1745                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1746
1747                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1748                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1749                              v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0));
1750                 if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
1751                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1752                                      m_SW_CORE_DCLK_SEL,
1753                                      v_SW_CORE_DCLK_SEL(0));
1754                 }
1755                 mask =
1756                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1757                     m_WIN0_CBR_DEFLICK;
1758                 val =
1759                     v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) |
1760                     v_WIN0_CBR_DEFLICK(0);
1761                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1762
1763                 mask =
1764                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1765                     m_WIN1_CBR_DEFLICK;
1766                 val =
1767                     v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) |
1768                     v_WIN1_CBR_DEFLICK(0);
1769                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1770
1771                 mask = m_WIN2_INTERLACE_READ;
1772                 val = v_WIN2_INTERLACE_READ(0);
1773                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1774
1775                 mask = m_WIN3_INTERLACE_READ;
1776                 val = v_WIN3_INTERLACE_READ(0);
1777                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1778
1779                 mask = m_HWC_INTERLACE_READ;
1780                 val = v_HWC_INTERLACE_READ(0);
1781                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1782
1783                 mask = m_DSP_LINE_FLAG0_NUM | m_DSP_LINE_FLAG1_NUM;
1784                 val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res) |
1785                         v_DSP_LINE_FLAG1_NUM(vsync_len + upper_margin + y_res -
1786                                              EARLY_TIME * v_total / frame_time);
1787                 lcdc_msk_reg(lcdc_dev, line_flag_reg, mask, val);
1788         }
1789         rk3368_lcdc_post_cfg(dev_drv);
1790         return 0;
1791 }
1792
1793 static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1794 {
1795         struct lcdc_device *lcdc_dev =
1796             container_of(dev_drv, struct lcdc_device, driver);
1797         u32 bcsh_ctrl;
1798
1799         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_OVERLAY_MODE,
1800                      v_OVERLAY_MODE(dev_drv->overlay_mode));
1801         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1802                 if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1803                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1804                                      m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1805                                      v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1806                 else            /* YUV2RGB */
1807                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1808                                      m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1809                                      m_BCSH_R2Y_EN,
1810                                      v_BCSH_Y2R_EN(1) |
1811                                      v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1812                                      v_BCSH_R2Y_EN(0));
1813         } else {                /* overlay_mode=VOP_RGB_DOMAIN */
1814                 /* bypass  --need check,if bcsh close? */
1815                 if (dev_drv->output_color == COLOR_RGB) {
1816                         bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1817                         if (((bcsh_ctrl & m_BCSH_EN) == 1) ||
1818                             (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1819                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1820                                              m_BCSH_R2Y_EN |
1821                                              m_BCSH_Y2R_EN,
1822                                              v_BCSH_R2Y_EN(1) |
1823                                              v_BCSH_Y2R_EN(1));
1824                         else
1825                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1826                                              m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1827                                              v_BCSH_R2Y_EN(0) |
1828                                              v_BCSH_Y2R_EN(0));
1829                 } else          /* RGB2YUV */
1830                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1831                                      m_BCSH_R2Y_EN |
1832                                      m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1833                                      v_BCSH_R2Y_EN(1) |
1834                                      v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1835                                      v_BCSH_Y2R_EN(0));
1836         }
1837 }
1838
1839 static int rk3368_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1840                                   u16 *yact, int *format, u32 *dsp_addr,
1841                                   int *ymirror)
1842 {
1843         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1844                                                     struct lcdc_device, driver);
1845         u32 val;
1846
1847         spin_lock(&lcdc_dev->reg_lock);
1848
1849         val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1850         *xact = (val & m_WIN0_ACT_WIDTH) + 1;
1851         *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1;
1852
1853         val = lcdc_readl(lcdc_dev, WIN0_CTRL0);
1854         *format = (val & m_WIN0_DATA_FMT) >> 1;
1855         *ymirror = (val & m_WIN0_Y_MIRROR) >> 22;
1856         *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1857
1858         spin_unlock(&lcdc_dev->reg_lock);
1859
1860         return 0;
1861 }
1862
1863 static int rk3368_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1864                               int format, u16 xact, u16 yact, u16 xvir,
1865                               int ymirror)
1866 {
1867         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1868                                                     struct lcdc_device, driver);
1869         u32 val, mask;
1870         struct rk_lcdc_win *win = dev_drv->win[0];
1871         int swap = (format == RGB888) ? 1 : 0;
1872
1873         mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP | m_WIN0_Y_MIRROR;
1874         val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap) |
1875                 v_WIN0_Y_MIRROR(ymirror);
1876         lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1877
1878         lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE,
1879                      v_WIN0_VIR_STRIDE(xvir));
1880         lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) |
1881                     v_WIN0_ACT_HEIGHT(yact));
1882
1883         lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1884
1885         lcdc_cfg_done(lcdc_dev);
1886         if (format == RGB888)
1887                 win->area[0].format = BGR888;
1888         else
1889                 win->area[0].format = format;
1890
1891         win->ymirror = ymirror;
1892         win->state = 1;
1893         win->last_state = 1;
1894
1895         return 0;
1896 }
1897
1898 static int lcdc_reset(struct rk_lcdc_driver *dev_drv, bool initscreen)
1899 {
1900         struct lcdc_device *lcdc_dev =
1901             container_of(dev_drv, struct lcdc_device, driver);
1902         u32 mask, val;
1903         u32 __maybe_unused v;
1904         if (!lcdc_dev->standby && initscreen && (dev_drv->first_frame != 1)) {
1905                 mdelay(150);
1906                 mask = m_WIN0_EN;
1907                 val = v_WIN0_EN(0);
1908                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1909                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1910
1911                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1912                         m_WIN2_MST1_EN |
1913                         m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1914                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
1915                         v_WIN2_MST1_EN(0) |
1916                         v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1917                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1918                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1919                 mask = m_HDMI_OUT_EN;
1920                 val = v_HDMI_OUT_EN(0);
1921                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1922                 lcdc_cfg_done(lcdc_dev);
1923                 mdelay(50);
1924                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
1925                 writel_relaxed(0, lcdc_dev->regs + REG_CFG_DONE);
1926                 mdelay(50);
1927 #ifdef VOP_RESET
1928                 if (dev_drv->iommu_enabled) {
1929                         if (dev_drv->mmu_dev)
1930                                 rockchip_iovmm_deactivate(dev_drv->dev);
1931                 }
1932                 lcdc_cru_writel(lcdc_dev->cru_base, 0x0318,
1933                                 (1 << 4)  | (1 << 5)  | (1 << 6) |
1934                                 (1 << 20) | (1 << 21) | (1 << 22));
1935                 udelay(100);
1936                 v = lcdc_cru_readl(lcdc_dev->cru_base, 0x0318);
1937                 pr_info("cru read = 0x%x\n", v);
1938                 lcdc_cru_writel(lcdc_dev->cru_base, 0x0318,
1939                                 (0 << 4)  | (0 << 5)  | (0 << 6) |
1940                                 (1 << 20) | (1 << 21) | (1 << 22));
1941                 mdelay(100);
1942                 if (dev_drv->iommu_enabled) {
1943                         if (dev_drv->mmu_dev)
1944                                 rockchip_iovmm_activate(dev_drv->dev);
1945                 }
1946                 mdelay(50);
1947                 rk3368_lcdc_reg_restore(lcdc_dev);
1948                 mdelay(50);
1949 #endif
1950         }
1951         return 0;
1952 }
1953
1954 static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1955 {
1956         u16 face = 0;
1957         u16 dclk_ddr = 0;
1958         struct lcdc_device *lcdc_dev =
1959             container_of(dev_drv, struct lcdc_device, driver);
1960         struct rk_screen *screen = dev_drv->cur_screen;
1961         u32 mask, val;
1962
1963         if (unlikely(!lcdc_dev->clk_on)) {
1964                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
1965                 return 0;
1966         }
1967
1968         if (!lcdc_dev->standby && initscreen && (dev_drv->first_frame != 1))
1969                 flush_kthread_worker(&dev_drv->update_regs_worker);
1970
1971         spin_lock(&lcdc_dev->reg_lock);
1972         if (likely(lcdc_dev->clk_on)) {
1973                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1974 #if 0
1975                 if (!lcdc_dev->standby && !initscreen) {
1976                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1977                                      v_STANDBY_EN(1));
1978                         lcdc_cfg_done(lcdc_dev);
1979                         mdelay(50);
1980                 }
1981 #else
1982         lcdc_reset(dev_drv, initscreen);
1983 #endif
1984                 switch (screen->face) {
1985                 case OUT_P565:
1986                         face = OUT_P565;
1987                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1988                             m_DITHER_DOWN_SEL;
1989                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1990                             v_DITHER_DOWN_SEL(1);
1991                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1992                         break;
1993                 case OUT_P666:
1994                         face = OUT_P666;
1995                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1996                             m_DITHER_DOWN_SEL;
1997                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1998                             v_DITHER_DOWN_SEL(1);
1999                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2000                         break;
2001                 case OUT_D888_P565:
2002                         face = OUT_P888;
2003                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
2004                             m_DITHER_DOWN_SEL;
2005                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
2006                             v_DITHER_DOWN_SEL(1);
2007                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2008                         break;
2009                 case OUT_D888_P666:
2010                         face = OUT_P888;
2011                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
2012                             m_DITHER_DOWN_SEL;
2013                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
2014                             v_DITHER_DOWN_SEL(1);
2015                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2016                         break;
2017                 case OUT_P888:
2018                         face = OUT_P888;
2019                         mask = m_DITHER_DOWN_EN;
2020                         val = v_DITHER_DOWN_EN(0);
2021                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2022                         break;
2023                 case OUT_YUV_420:
2024                         /*yuv420 output prefer yuv domain overlay */
2025                         face = OUT_YUV_420;
2026                         dclk_ddr = 1;
2027                         mask = m_DITHER_DOWN_EN;
2028                         val = v_DITHER_DOWN_EN(0);
2029                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2030                         break;
2031                 case OUT_S888:
2032                         face = OUT_S888;
2033                         mask = m_DITHER_DOWN_EN;
2034                         val = v_DITHER_DOWN_EN(0);
2035                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2036                         break;
2037                 case OUT_S888DUMY:
2038                         face = OUT_S888DUMY;
2039                         mask = m_DITHER_DOWN_EN;
2040                         val = v_DITHER_DOWN_EN(0);
2041                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2042                         break;
2043                 case OUT_CCIR656:
2044                         if (screen->color_mode == COLOR_RGB)
2045                                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
2046                         else
2047                                 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
2048                         face = OUT_CCIR656_MODE_0;
2049                         mask = m_DITHER_DOWN_EN;
2050                         val = v_DITHER_DOWN_EN(0);
2051                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2052                         break;
2053                 default:
2054                         dev_err(lcdc_dev->dev, "un supported interface!\n");
2055                         break;
2056                 }
2057                 switch (screen->type) {
2058                 case SCREEN_RGB:
2059                         mask = m_RGB_OUT_EN;
2060                         val = v_RGB_OUT_EN(1);
2061                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2062                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
2063                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
2064                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
2065                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
2066                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
2067                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
2068                         if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
2069                                 lcdc_grf_writel(lcdc_dev->grf_base,
2070                                                 RK3366_GRF_SOC_CON5,
2071                                                 RGB_SOURCE_SEL(dev_drv->id));
2072                                 lcdc_grf_writel(lcdc_dev->grf_base,
2073                                                 RK3366_GRF_SOC_CON0,
2074                                                 RGB_DATA_PLANA);
2075                         }
2076                         break;
2077                 case SCREEN_LVDS:
2078                         mask = m_RGB_OUT_EN;
2079                         val = v_RGB_OUT_EN(1);
2080                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2081                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
2082                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
2083                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
2084                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
2085                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
2086                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
2087                         if (lcdc_dev->soc_type == VOP_FULL_RK3366)
2088                                 lcdc_grf_writel(lcdc_dev->grf_base,
2089                                                 RK3366_GRF_SOC_CON0,
2090                                                 LVDS_SOURCE_SEL(dev_drv->id));
2091                         break;
2092                 case SCREEN_HDMI:
2093                         if (screen->color_mode == COLOR_RGB)
2094                                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
2095                         else
2096                                 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
2097                         mask = m_HDMI_OUT_EN  | m_RGB_OUT_EN;
2098                         val = v_HDMI_OUT_EN(1) | v_RGB_OUT_EN(0);
2099                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2100                         mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
2101                             m_HDMI_DEN_POL | m_HDMI_DCLK_POL;
2102                         val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
2103                             v_HDMI_VSYNC_POL(screen->pin_vsync) |
2104                             v_HDMI_DEN_POL(screen->pin_den) |
2105                             v_HDMI_DCLK_POL(screen->pin_dclk);
2106                         if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
2107                                 lcdc_grf_writel(lcdc_dev->grf_base,
2108                                                 RK3366_GRF_SOC_CON0,
2109                                                 HDMI_SOURCE_SEL(dev_drv->id));
2110                         }
2111                         break;
2112                 case SCREEN_MIPI:
2113                         mask = m_MIPI_OUT_EN  | m_RGB_OUT_EN;
2114                         val = v_MIPI_OUT_EN(1) | v_RGB_OUT_EN(0);
2115                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2116                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
2117                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
2118                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
2119                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
2120                             v_MIPI_DEN_POL(screen->pin_den) |
2121                             v_MIPI_DCLK_POL(screen->pin_dclk);
2122                         if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
2123                                 lcdc_grf_writel(lcdc_dev->grf_base,
2124                                                 RK3366_GRF_SOC_CON0,
2125                                                 MIPI_SOURCE_SEL(dev_drv->id));
2126                         }
2127                         break;
2128                 case SCREEN_DUAL_MIPI:
2129                         mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN  |
2130                                 m_RGB_OUT_EN;
2131                         val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1) |
2132                                 v_RGB_OUT_EN(0);
2133                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2134                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
2135                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
2136                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
2137                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
2138                             v_MIPI_DEN_POL(screen->pin_den) |
2139                             v_MIPI_DCLK_POL(screen->pin_dclk);
2140                         break;
2141                 case SCREEN_EDP:
2142                         face = OUT_P888;        /*RGB 888 output */
2143
2144                         mask = m_EDP_OUT_EN | m_RGB_OUT_EN;
2145                         val = v_EDP_OUT_EN(1) | v_RGB_OUT_EN(0);
2146                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2147
2148                         mask = m_EDP_HSYNC_POL | m_EDP_VSYNC_POL |
2149                             m_EDP_DEN_POL | m_EDP_DCLK_POL;
2150                         val = v_EDP_HSYNC_POL(screen->pin_hsync) |
2151                             v_EDP_VSYNC_POL(screen->pin_vsync) |
2152                             v_EDP_DEN_POL(screen->pin_den) |
2153                             v_EDP_DCLK_POL(screen->pin_dclk);
2154                         break;
2155                 }
2156                 /*hsync vsync den dclk polo,dither */
2157                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2158                 mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP |
2159                     m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
2160                     m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
2161                     m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
2162                 val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) |
2163                     v_DSP_BG_SWAP(screen->swap_gb) |
2164                     v_DSP_RB_SWAP(screen->swap_rb) |
2165                     v_DSP_RG_SWAP(screen->swap_rg) |
2166                     v_DSP_DELTA_SWAP(screen->swap_delta) |
2167                     v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
2168                     v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
2169                     v_DSP_X_MIR_EN(screen->x_mirror) |
2170                     v_DSP_Y_MIR_EN(screen->y_mirror);
2171                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
2172                 /*BG color */
2173                 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
2174                 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN)
2175                         val = v_DSP_BG_BLUE(0x80) | v_DSP_BG_GREEN(0x10) |
2176                                 v_DSP_BG_RED(0x80);
2177                 else
2178                         val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) |
2179                                 v_DSP_BG_RED(0);
2180                 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
2181                 dev_drv->output_color = screen->color_mode;
2182                 if (screen->dsp_lut == NULL)
2183                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2184                                      v_DSP_LUT_EN(0));
2185                 else
2186                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2187                                      v_DSP_LUT_EN(1));
2188                 rk3368_lcdc_bcsh_path_sel(dev_drv);
2189                 rk3368_config_timing(dev_drv);
2190                 if (lcdc_dev->soc_type == VOP_FULL_RK3366)
2191                         lcdc_cfg_done(lcdc_dev);
2192         }
2193         spin_unlock(&lcdc_dev->reg_lock);
2194         rk3368_lcdc_set_dclk(dev_drv, 1);
2195         if (screen->type != SCREEN_HDMI &&
2196             screen->type != SCREEN_TVOUT &&
2197             dev_drv->trsm_ops &&
2198             dev_drv->trsm_ops->enable)
2199                 dev_drv->trsm_ops->enable();
2200                 if (screen->init)
2201                         screen->init();
2202         /*if (!lcdc_dev->standby)
2203                 lcdc_msk_reg(lcdc_dev, SYS_CTRL,
2204                         m_STANDBY_EN, v_STANDBY_EN(0));*/
2205         return 0;
2206 }
2207
2208
2209 /*enable layer,open:1,enable;0 disable*/
2210 static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev,
2211                                      unsigned int win_id, bool open)
2212 {
2213         spin_lock(&lcdc_dev->reg_lock);
2214         if (likely(lcdc_dev->clk_on) &&
2215             lcdc_dev->driver.win[win_id]->state != open) {
2216                 if (open) {
2217                         if (!lcdc_dev->atv_layer_cnt) {
2218                                 dev_info(lcdc_dev->dev,
2219                                          "wakeup from standby!\n");
2220                                 lcdc_dev->standby = 0;
2221                         }
2222                         lcdc_dev->atv_layer_cnt |= (1 << win_id);
2223                 } else {
2224                         if (lcdc_dev->atv_layer_cnt & (1 << win_id))
2225                                 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
2226                 }
2227                 lcdc_dev->driver.win[win_id]->state = open;
2228                 if (!open) {
2229                         /*rk3368_lcdc_reg_update(dev_drv);*/
2230                         rk3368_lcdc_layer_update_regs
2231                         (lcdc_dev, lcdc_dev->driver.win[win_id]);
2232                         lcdc_cfg_done(lcdc_dev);
2233                 }
2234                 /*if no layer used,disable lcdc */
2235                 if (!lcdc_dev->atv_layer_cnt) {
2236                         dev_info(lcdc_dev->dev,
2237                                  "no layer is used,go to standby!\n");
2238                         lcdc_dev->standby = 1;
2239                 }
2240         }
2241         spin_unlock(&lcdc_dev->reg_lock);
2242 }
2243
2244 static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
2245 {
2246         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2247                                                     struct lcdc_device, driver);
2248         u32 mask, val;
2249         /*struct rk_screen *screen = dev_drv->cur_screen; */
2250         u32 intr_en_reg, intr_clr_reg;
2251
2252         if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
2253                 intr_clr_reg = INTR_CLEAR_RK3366;
2254                 intr_en_reg = INTR_EN_RK3366;
2255         } else {
2256                 intr_clr_reg = INTR_CLEAR_RK3368;
2257                 intr_en_reg = INTR_EN_RK3368;
2258         }
2259
2260         mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
2261             m_LINE_FLAG1_INTR_CLR;
2262         val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
2263             v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1);
2264         lcdc_msk_reg(lcdc_dev, intr_clr_reg, mask, val);
2265
2266         mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN |
2267                 m_BUS_ERROR_INTR_EN | m_LINE_FLAG1_INTR_EN;
2268         val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) |
2269             v_BUS_ERROR_INTR_EN(1) | v_LINE_FLAG1_INTR_EN(0);
2270         lcdc_msk_reg(lcdc_dev, intr_en_reg, mask, val);
2271 #ifdef LCDC_IRQ_EMPTY_DEBUG
2272         mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
2273             m_WIN2_EMPTY_INTR_EN |
2274             m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN |
2275             m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN;
2276         val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) |
2277             v_WIN2_EMPTY_INTR_EN(1) |
2278             v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) |
2279             v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1);
2280         lcdc_msk_reg(lcdc_dev, intr_en_reg, mask, val);
2281 #endif
2282         return 0;
2283 }
2284
2285 static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
2286                             bool open)
2287 {
2288         struct lcdc_device *lcdc_dev =
2289             container_of(dev_drv, struct lcdc_device, driver);
2290         /*enable clk,when first layer open */
2291         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
2292                 /*rockchip_set_system_status(sys_status);*/
2293                 rk3368_lcdc_pre_init(dev_drv);
2294                 rk3368_lcdc_clk_enable(lcdc_dev);
2295                 rk3368_lcdc_enable_irq(dev_drv);
2296                 if (dev_drv->iommu_enabled) {
2297                         if (!dev_drv->mmu_dev) {
2298                                 dev_drv->mmu_dev =
2299                                     rk_fb_get_sysmmu_device_by_compatible
2300                                     (dev_drv->mmu_dts_name);
2301                                 if (dev_drv->mmu_dev) {
2302                                         rk_fb_platform_set_sysmmu
2303                                             (dev_drv->mmu_dev, dev_drv->dev);
2304                                 } else {
2305                                         dev_err(dev_drv->dev,
2306                                                 "fail get rk iommu device\n");
2307                                         return -1;
2308                                 }
2309                         }
2310                         /*if (dev_drv->mmu_dev)
2311                            rockchip_iovmm_activate(dev_drv->dev); */
2312                 }
2313                 rk3368_lcdc_reg_restore(lcdc_dev);
2314                 /*if (dev_drv->iommu_enabled)
2315                    rk3368_lcdc_mmu_en(dev_drv); */
2316                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
2317                         rk3368_lcdc_set_dclk(dev_drv, 0);
2318                         /*rk3368_lcdc_enable_irq(dev_drv);*/
2319                 } else {
2320                         rk3368_load_screen(dev_drv, 1);
2321                 }
2322                 if (dev_drv->bcsh.enable)
2323                         rk3368_lcdc_set_bcsh(dev_drv, 1);
2324                 spin_lock(&lcdc_dev->reg_lock);
2325                 if (dev_drv->cur_screen->dsp_lut)
2326                         rk3368_lcdc_set_lut(dev_drv,
2327                                             dev_drv->cur_screen->dsp_lut);
2328                 spin_unlock(&lcdc_dev->reg_lock);
2329         }
2330
2331         if (win_id < ARRAY_SIZE(lcdc_win))
2332                 rk3368_lcdc_layer_enable(lcdc_dev, win_id, open);
2333         else
2334                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
2335
2336
2337         /* when all layer closed,disable clk */
2338         /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
2339            rk3368_lcdc_disable_irq(lcdc_dev);
2340            rk3368_lcdc_reg_update(dev_drv);
2341            if (dev_drv->iommu_enabled) {
2342            if (dev_drv->mmu_dev)
2343            rockchip_iovmm_deactivate(dev_drv->dev);
2344            }
2345            rk3368_lcdc_clk_disable(lcdc_dev);
2346            #ifndef CONFIG_RK_FPGA
2347            rockchip_clear_system_status(sys_status);
2348            #endif
2349            } */
2350         dev_drv->first_frame = 0;
2351         return 0;
2352 }
2353
2354 static int win_0_1_display(struct lcdc_device *lcdc_dev,
2355                            struct rk_lcdc_win *win)
2356 {
2357         u32 y_addr;
2358         u32 uv_addr;
2359         unsigned int off;
2360
2361         off = win->id * 0x40;
2362         /*win->smem_start + win->y_offset; */
2363         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2364         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
2365         DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
2366             lcdc_dev->id, win->id, y_addr, uv_addr);
2367         DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
2368             win->area[0].y_offset, win->area[0].c_offset);
2369         spin_lock(&lcdc_dev->reg_lock);
2370         if (likely(lcdc_dev->clk_on)) {
2371                 win->area[0].y_addr = y_addr;
2372                 win->area[0].uv_addr = uv_addr;
2373                 lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
2374                 lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
2375                 if (win->area[0].fbdc_en == 1)
2376                         lcdc_writel(lcdc_dev, IFBDC_BASE_ADDR,
2377                                     win->area[0].y_addr);
2378         }
2379         spin_unlock(&lcdc_dev->reg_lock);
2380
2381         return 0;
2382 }
2383
2384 static int win_2_3_display(struct lcdc_device *lcdc_dev,
2385                            struct rk_lcdc_win *win)
2386 {
2387         u32 i, y_addr;
2388         unsigned int off;
2389
2390         off = (win->id - 2) * 0x50;
2391         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2392         DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id);
2393
2394         spin_lock(&lcdc_dev->reg_lock);
2395         if (likely(lcdc_dev->clk_on)) {
2396                 for (i = 0; i < win->area_num; i++) {
2397                         DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2398                             i, win->area[i].y_addr, win->area[i].y_offset);
2399                         win->area[i].y_addr =
2400                             win->area[i].smem_start + win->area[i].y_offset;
2401                         }
2402                 lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr);
2403                 lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr);
2404                 lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr);
2405                 lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr);
2406                 if (win->area[0].fbdc_en == 1)
2407                         lcdc_writel(lcdc_dev, IFBDC_BASE_ADDR,
2408                                     win->area[0].y_addr);
2409         }
2410         spin_unlock(&lcdc_dev->reg_lock);
2411         return 0;
2412 }
2413
2414 static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win)
2415 {
2416         u32 y_addr;
2417
2418         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2419         DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2420             lcdc_dev->id, __func__, y_addr);
2421         spin_lock(&lcdc_dev->reg_lock);
2422         if (likely(lcdc_dev->clk_on)) {
2423                 win->area[0].y_addr = y_addr;
2424                 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
2425         }
2426         spin_unlock(&lcdc_dev->reg_lock);
2427
2428         return 0;
2429 }
2430
2431 static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2432 {
2433         struct lcdc_device *lcdc_dev =
2434             container_of(dev_drv, struct lcdc_device, driver);
2435         struct rk_lcdc_win *win = NULL;
2436         struct rk_screen *screen = dev_drv->cur_screen;
2437
2438 #if defined(WAIT_FOR_SYNC)
2439         int timeout;
2440         unsigned long flags;
2441 #endif
2442         win = dev_drv->win[win_id];
2443         if (!screen) {
2444                 dev_err(dev_drv->dev, "screen is null!\n");
2445                 return -ENOENT;
2446         }
2447         if (unlikely(!lcdc_dev->clk_on)) {
2448                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
2449                 return 0;
2450         }
2451         if (win_id == 0) {
2452                 win_0_1_display(lcdc_dev, win);
2453         } else if (win_id == 1) {
2454                 win_0_1_display(lcdc_dev, win);
2455         } else if (win_id == 2) {
2456                 win_2_3_display(lcdc_dev, win);
2457         } else if (win_id == 3) {
2458                 win_2_3_display(lcdc_dev, win);
2459         } else if (win_id == 4) {
2460                 hwc_display(lcdc_dev, win);
2461         } else {
2462                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2463                 return -EINVAL;
2464         }
2465
2466 #if defined(WAIT_FOR_SYNC)
2467         spin_lock_irqsave(&dev_drv->cpl_lock, flags);
2468         init_completion(&dev_drv->frame_done);
2469         spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
2470         timeout =
2471             wait_for_completion_timeout(&dev_drv->frame_done,
2472                                         msecs_to_jiffies(dev_drv->
2473                                                          cur_screen->ft + 5));
2474         if (!timeout && (!dev_drv->frame_done.done)) {
2475                 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
2476                 return -ETIMEDOUT;
2477         }
2478 #endif
2479         return 0;
2480 }
2481
2482 static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win,
2483                                    struct rk_screen *screen)
2484 {
2485         u16 srcW;
2486         u16 srcH;
2487         u16 dstW;
2488         u16 dstH;
2489         u16 yrgb_srcW;
2490         u16 yrgb_srcH;
2491         u16 yrgb_dstW;
2492         u16 yrgb_dstH;
2493         u32 yrgb_vscalednmult;
2494         u32 yrgb_xscl_factor;
2495         u32 yrgb_yscl_factor;
2496         u8 yrgb_vsd_bil_gt2 = 0;
2497         u8 yrgb_vsd_bil_gt4 = 0;
2498
2499         u16 cbcr_srcW;
2500         u16 cbcr_srcH;
2501         u16 cbcr_dstW;
2502         u16 cbcr_dstH;
2503         u32 cbcr_vscalednmult;
2504         u32 cbcr_xscl_factor;
2505         u32 cbcr_yscl_factor;
2506         u8 cbcr_vsd_bil_gt2 = 0;
2507         u8 cbcr_vsd_bil_gt4 = 0;
2508         u8 yuv_fmt = 0;
2509
2510         srcW = win->area[0].xact;
2511         if ((screen->mode.vmode & FB_VMODE_INTERLACED) &&
2512             (win->area[0].yact == 2 * win->area[0].ysize)) {
2513                 srcH = win->area[0].yact / 2;
2514                 yrgb_vsd_bil_gt2 = 1;
2515                 cbcr_vsd_bil_gt2 = 1;
2516         } else {
2517                 srcH = win->area[0].yact;
2518         }
2519         dstW = win->area[0].xsize;
2520         dstH = win->area[0].ysize;
2521
2522         /*yrgb scl mode */
2523         yrgb_srcW = srcW;
2524         yrgb_srcH = srcH;
2525         yrgb_dstW = dstW;
2526         yrgb_dstH = dstH;
2527         if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2528                 pr_err("ERROR: yrgb scale exceed 8,");
2529                 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2530                        yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2531         }
2532         if (yrgb_srcW < yrgb_dstW)
2533                 win->yrgb_hor_scl_mode = SCALE_UP;
2534         else if (yrgb_srcW > yrgb_dstW)
2535                 win->yrgb_hor_scl_mode = SCALE_DOWN;
2536         else
2537                 win->yrgb_hor_scl_mode = SCALE_NONE;
2538
2539         if (yrgb_srcH < yrgb_dstH)
2540                 win->yrgb_ver_scl_mode = SCALE_UP;
2541         else if (yrgb_srcH > yrgb_dstH)
2542                 win->yrgb_ver_scl_mode = SCALE_DOWN;
2543         else
2544                 win->yrgb_ver_scl_mode = SCALE_NONE;
2545
2546         /*cbcr scl mode */
2547         switch (win->area[0].format) {
2548         case YUV422:
2549         case YUV422_A:
2550                 cbcr_srcW = srcW / 2;
2551                 cbcr_dstW = dstW;
2552                 cbcr_srcH = srcH;
2553                 cbcr_dstH = dstH;
2554                 yuv_fmt = 1;
2555                 break;
2556         case YUV420:
2557         case YUV420_A:
2558         case YUV420_NV21:
2559                 cbcr_srcW = srcW / 2;
2560                 cbcr_dstW = dstW;
2561                 cbcr_srcH = srcH / 2;
2562                 cbcr_dstH = dstH;
2563                 yuv_fmt = 1;
2564                 break;
2565         case YUV444:
2566         case YUV444_A:
2567                 cbcr_srcW = srcW;
2568                 cbcr_dstW = dstW;
2569                 cbcr_srcH = srcH;
2570                 cbcr_dstH = dstH;
2571                 yuv_fmt = 1;
2572                 break;
2573         default:
2574                 cbcr_srcW = 0;
2575                 cbcr_dstW = 0;
2576                 cbcr_srcH = 0;
2577                 cbcr_dstH = 0;
2578                 yuv_fmt = 0;
2579                 break;
2580         }
2581         if (yuv_fmt) {
2582                 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2583                     (cbcr_dstH * 8 <= cbcr_srcH)) {
2584                         pr_err("ERROR: cbcr scale exceed 8,");
2585                         pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2586                                cbcr_srcH, cbcr_dstW, cbcr_dstH);
2587                 }
2588         }
2589
2590         if (cbcr_srcW < cbcr_dstW)
2591                 win->cbr_hor_scl_mode = SCALE_UP;
2592         else if (cbcr_srcW > cbcr_dstW)
2593                 win->cbr_hor_scl_mode = SCALE_DOWN;
2594         else
2595                 win->cbr_hor_scl_mode = SCALE_NONE;
2596
2597         if (cbcr_srcH < cbcr_dstH)
2598                 win->cbr_ver_scl_mode = SCALE_UP;
2599         else if (cbcr_srcH > cbcr_dstH)
2600                 win->cbr_ver_scl_mode = SCALE_DOWN;
2601         else
2602                 win->cbr_ver_scl_mode = SCALE_NONE;
2603
2604         /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
2605             "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
2606             "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW,
2607             srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH,
2608             win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW,
2609             cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode,
2610             win->cbr_ver_scl_mode);*/
2611
2612         /*line buffer mode */
2613         if ((win->area[0].format == YUV422) ||
2614             (win->area[0].format == YUV420) ||
2615             (win->area[0].format == YUV420_NV21) ||
2616             (win->area[0].format == YUV422_A) ||
2617             (win->area[0].format == YUV420_A)) {
2618                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2619                         if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2620                             (cbcr_dstW == 0))
2621                                 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2622                                        cbcr_dstW);
2623                         else if (cbcr_dstW > 1280)
2624                                 win->win_lb_mode = LB_YUV_3840X5;
2625                         else
2626                                 win->win_lb_mode = LB_YUV_2560X8;
2627                 } else {        /*SCALE_UP or SCALE_NONE */
2628                         if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2629                             (cbcr_srcW == 0))
2630                                 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2631                                        cbcr_srcW);
2632                         else if (cbcr_srcW > 1280)
2633                                 win->win_lb_mode = LB_YUV_3840X5;
2634                         else
2635                                 win->win_lb_mode = LB_YUV_2560X8;
2636                 }
2637         } else {
2638                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2639                         if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2640                             (yrgb_dstW == 0))
2641                                 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2642                         else if (yrgb_dstW > 2560)
2643                                 win->win_lb_mode = LB_RGB_3840X2;
2644                         else if (yrgb_dstW > 1920)
2645                                 win->win_lb_mode = LB_RGB_2560X4;
2646                         else if (yrgb_dstW > 1280)
2647                                 win->win_lb_mode = LB_RGB_1920X5;
2648                         else
2649                                 win->win_lb_mode = LB_RGB_1280X8;
2650                 } else {        /*SCALE_UP or SCALE_NONE */
2651                         if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2652                             (yrgb_srcW == 0))
2653                                 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2654                         else if (yrgb_srcW > 2560)
2655                                 win->win_lb_mode = LB_RGB_3840X2;
2656                         else if (yrgb_srcW > 1920)
2657                                 win->win_lb_mode = LB_RGB_2560X4;
2658                         else if (yrgb_srcW > 1280)
2659                                 win->win_lb_mode = LB_RGB_1920X5;
2660                         else
2661                                 win->win_lb_mode = LB_RGB_1280X8;
2662                 }
2663         }
2664         DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2665
2666         /*vsd/vsu scale ALGORITHM */
2667         win->yrgb_hsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2668         win->cbr_hsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2669         win->yrgb_vsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2670         win->cbr_vsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2671         switch (win->win_lb_mode) {
2672         case LB_YUV_3840X5:
2673         case LB_YUV_2560X8:
2674         case LB_RGB_1920X5:
2675         case LB_RGB_1280X8:
2676                 win->yrgb_vsu_mode = SCALE_UP_BIC;
2677                 win->cbr_vsu_mode = SCALE_UP_BIC;
2678                 break;
2679         case LB_RGB_3840X2:
2680                 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2681                         pr_err("ERROR : not allow yrgb ver scale\n");
2682                 if (win->cbr_ver_scl_mode != SCALE_NONE)
2683                         pr_err("ERROR : not allow cbcr ver scale\n");
2684                 break;
2685         case LB_RGB_2560X4:
2686                 win->yrgb_vsu_mode = SCALE_UP_BIL;
2687                 win->cbr_vsu_mode = SCALE_UP_BIL;
2688                 break;
2689         default:
2690                 pr_info("%s:un supported win_lb_mode:%d\n",
2691                         __func__, win->win_lb_mode);
2692                 break;
2693         }
2694         if (win->ymirror == 1)
2695                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2696
2697         if (screen->mode.vmode & FB_VMODE_INTERLACED) {
2698                 /*interlace mode must bill */
2699                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2700                 win->cbr_vsd_mode = SCALE_DOWN_BIL;
2701         }
2702         if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2703             (win->area[0].fbdc_en == 1)) {
2704                 /*in this pattern,use bil mode,not support souble scd,
2705                 use avg mode, support double scd, but aclk should be
2706                 bigger than dclk,aclk>>dclk */
2707                 if (yrgb_srcH >= 2 * yrgb_dstH) {
2708                         pr_err("ERROR : fbdc mode,not support y scale down:");
2709                         pr_err("srcH[%d] > 2 *dstH[%d]\n",
2710                                yrgb_srcH, yrgb_dstH);
2711                 }
2712         }
2713         DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2714             win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2715             win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2716
2717         /*SCALE FACTOR */
2718
2719         /*(1.1)YRGB HOR SCALE FACTOR */
2720         switch (win->yrgb_hor_scl_mode) {
2721         case SCALE_NONE:
2722                 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2723                 break;
2724         case SCALE_UP:
2725                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2726                 break;
2727         case SCALE_DOWN:
2728                 switch (win->yrgb_hsd_mode) {
2729                 case SCALE_DOWN_BIL:
2730                         yrgb_xscl_factor =
2731                             GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2732                         break;
2733                 case SCALE_DOWN_AVG:
2734                         yrgb_xscl_factor =
2735                             GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2736                         break;
2737                 default:
2738                         pr_info(
2739                                 "%s:un supported yrgb_hsd_mode:%d\n", __func__,
2740                                win->yrgb_hsd_mode);
2741                         break;
2742                 }
2743                 break;
2744         default:
2745                 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2746                         __func__, win->yrgb_hor_scl_mode);
2747                 break;
2748         }                       /*win->yrgb_hor_scl_mode */
2749
2750         /*(1.2)YRGB VER SCALE FACTOR */
2751         switch (win->yrgb_ver_scl_mode) {
2752         case SCALE_NONE:
2753                 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2754                 break;
2755         case SCALE_UP:
2756                 switch (win->yrgb_vsu_mode) {
2757                 case SCALE_UP_BIL:
2758                         yrgb_yscl_factor =
2759                             GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2760                         break;
2761                 case SCALE_UP_BIC:
2762                         if (yrgb_srcH < 3) {
2763                                 pr_err("yrgb_srcH should be");
2764                                 pr_err(" greater than 3 !!!\n");
2765                         }
2766                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2767                                                                 yrgb_dstH);
2768                         break;
2769                 default:
2770                         pr_info("%s:un support yrgb_vsu_mode:%d\n",
2771                                 __func__, win->yrgb_vsu_mode);
2772                         break;
2773                 }
2774                 break;
2775         case SCALE_DOWN:
2776                 switch (win->yrgb_vsd_mode) {
2777                 case SCALE_DOWN_BIL:
2778                         yrgb_vscalednmult =
2779                             rk3368_get_hard_ware_vskiplines(yrgb_srcH,
2780                                                             yrgb_dstH);
2781                         yrgb_yscl_factor =
2782                             GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2783                                                            yrgb_vscalednmult);
2784                         if (yrgb_yscl_factor >= 0x2000) {
2785                                 pr_err("yrgb_yscl_factor should be ");
2786                                 pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n",
2787                                        yrgb_yscl_factor);
2788                         }
2789                         if (yrgb_vscalednmult == 4) {
2790                                 yrgb_vsd_bil_gt4 = 1;
2791                                 yrgb_vsd_bil_gt2 = 0;
2792                         } else if (yrgb_vscalednmult == 2) {
2793                                 yrgb_vsd_bil_gt4 = 0;
2794                                 yrgb_vsd_bil_gt2 = 1;
2795                         } else {
2796                                 yrgb_vsd_bil_gt4 = 0;
2797                                 yrgb_vsd_bil_gt2 = 0;
2798                         }
2799                         break;
2800                 case SCALE_DOWN_AVG:
2801                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2802                                                                  yrgb_dstH);
2803                         break;
2804                 default:
2805                         pr_info("%s:un support yrgb_vsd_mode:%d\n",
2806                                 __func__, win->yrgb_vsd_mode);
2807                         break;
2808                 }               /*win->yrgb_vsd_mode */
2809                 break;
2810         default:
2811                 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2812                         __func__, win->yrgb_ver_scl_mode);
2813                 break;
2814         }
2815         win->scale_yrgb_x = yrgb_xscl_factor;
2816         win->scale_yrgb_y = yrgb_yscl_factor;
2817         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2818         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2819         DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2820             yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2821
2822         /*(2.1)CBCR HOR SCALE FACTOR */
2823         switch (win->cbr_hor_scl_mode) {
2824         case SCALE_NONE:
2825                 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2826                 break;
2827         case SCALE_UP:
2828                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2829                 break;
2830         case SCALE_DOWN:
2831                 switch (win->cbr_hsd_mode) {
2832                 case SCALE_DOWN_BIL:
2833                         cbcr_xscl_factor =
2834                             GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2835                         break;
2836                 case SCALE_DOWN_AVG:
2837                         cbcr_xscl_factor =
2838                             GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2839                         break;
2840                 default:
2841                         pr_info("%s:un support cbr_hsd_mode:%d\n",
2842                                 __func__, win->cbr_hsd_mode);
2843                         break;
2844                 }
2845                 break;
2846         default:
2847                 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2848                         __func__, win->cbr_hor_scl_mode);
2849                 break;
2850         }                       /*win->cbr_hor_scl_mode */
2851
2852         /*(2.2)CBCR VER SCALE FACTOR */
2853         switch (win->cbr_ver_scl_mode) {
2854         case SCALE_NONE:
2855                 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2856                 break;
2857         case SCALE_UP:
2858                 switch (win->cbr_vsu_mode) {
2859                 case SCALE_UP_BIL:
2860                         cbcr_yscl_factor =
2861                             GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2862                         break;
2863                 case SCALE_UP_BIC:
2864                         if (cbcr_srcH < 3) {
2865                                 pr_err("cbcr_srcH should be ");
2866                                 pr_err("greater than 3 !!!\n");
2867                         }
2868                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2869                                                                 cbcr_dstH);
2870                         break;
2871                 default:
2872                         pr_info("%s:un support cbr_vsu_mode:%d\n",
2873                                 __func__, win->cbr_vsu_mode);
2874                         break;
2875                 }
2876                 break;
2877         case SCALE_DOWN:
2878                 switch (win->cbr_vsd_mode) {
2879                 case SCALE_DOWN_BIL:
2880                         cbcr_vscalednmult =
2881                             rk3368_get_hard_ware_vskiplines(cbcr_srcH,
2882                                                             cbcr_dstH);
2883                         cbcr_yscl_factor =
2884                             GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2885                                                            cbcr_vscalednmult);
2886                         if (cbcr_yscl_factor >= 0x2000) {
2887                                 pr_err("cbcr_yscl_factor should be less ");
2888                                 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2889                                        cbcr_yscl_factor);
2890                         }
2891
2892                         if (cbcr_vscalednmult == 4) {
2893                                 cbcr_vsd_bil_gt4 = 1;
2894                                 cbcr_vsd_bil_gt2 = 0;
2895                         } else if (cbcr_vscalednmult == 2) {
2896                                 cbcr_vsd_bil_gt4 = 0;
2897                                 cbcr_vsd_bil_gt2 = 1;
2898                         } else {
2899                                 cbcr_vsd_bil_gt4 = 0;
2900                                 cbcr_vsd_bil_gt2 = 0;
2901                         }
2902                         break;
2903                 case SCALE_DOWN_AVG:
2904                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2905                                                                  cbcr_dstH);
2906                         break;
2907                 default:
2908                         pr_info("%s:un support cbr_vsd_mode:%d\n",
2909                                 __func__, win->cbr_vsd_mode);
2910                         break;
2911                 }
2912                 break;
2913         default:
2914                 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2915                         __func__, win->cbr_ver_scl_mode);
2916                 break;
2917         }
2918         win->scale_cbcr_x = cbcr_xscl_factor;
2919         win->scale_cbcr_y = cbcr_yscl_factor;
2920         win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2921         win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2922
2923         DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2924             cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2925         return 0;
2926 }
2927
2928 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2929                      struct rk_lcdc_win_area *area)
2930 {
2931         int pos;
2932
2933         if (screen->x_mirror && mirror_en)
2934                 pr_err("not support both win and global mirror\n");
2935
2936         if ((!mirror_en) && (!screen->x_mirror))
2937                 pos = area->xpos + screen->mode.left_margin +
2938                         screen->mode.hsync_len;
2939         else
2940                 pos = screen->mode.xres - area->xpos -
2941                         area->xsize + screen->mode.left_margin +
2942                         screen->mode.hsync_len;
2943
2944         return pos;
2945 }
2946
2947 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2948                      struct rk_lcdc_win_area *area)
2949 {
2950         int pos;
2951
2952         if (screen->y_mirror && mirror_en)
2953                 pr_err("not support both win and global mirror\n");
2954         if (!(screen->mode.vmode & FB_VMODE_INTERLACED)) {
2955                 if ((!mirror_en) && (!screen->y_mirror))
2956                         pos = area->ypos + screen->mode.upper_margin +
2957                                 screen->mode.vsync_len;
2958                 else
2959                         pos = screen->mode.yres - area->ypos -
2960                                 area->ysize + screen->mode.upper_margin +
2961                                 screen->mode.vsync_len;
2962         } else {
2963                 pos = area->ypos / 2 + screen->mode.upper_margin +
2964                         screen->mode.vsync_len;
2965                 area->ysize /= 2;
2966         }
2967
2968         return pos;
2969 }
2970
2971 static int win_0_1_set_par(struct lcdc_device *lcdc_dev,
2972                            struct rk_screen *screen, struct rk_lcdc_win *win)
2973 {
2974         u32 xact, yact, xvir, yvir, xpos, ypos;
2975         u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2976         char fmt[9] = "NULL";
2977
2978         xpos = dsp_x_pos(win->xmirror, screen, &win->area[0]);
2979         ypos = dsp_y_pos(win->ymirror, screen, &win->area[0]);
2980
2981         spin_lock(&lcdc_dev->reg_lock);
2982         if (likely(lcdc_dev->clk_on)) {
2983                 rk3368_lcdc_cal_scl_fac(win, screen);   /*fac,lb,gt2,gt4 */
2984                 switch (win->area[0].format) {
2985                 case FBDC_RGB_565:
2986                         fmt_cfg = 2;
2987                         swap_rb = 0;
2988                         win->fmt_10 = 0;
2989                         win->area[0].fbdc_fmt_cfg = 0x05;
2990                         break;
2991                 case FBDC_ARGB_888:
2992                         fmt_cfg = 0;
2993                         swap_rb = 0;
2994                         win->fmt_10 = 0;
2995                         win->area[0].fbdc_fmt_cfg = 0x0c;
2996                         break;
2997                 case FBDC_ABGR_888:
2998                         fmt_cfg = 0;
2999                         swap_rb = 1;
3000                         win->fmt_10 = 0;
3001                         win->area[0].fbdc_fmt_cfg = 0x0c;
3002                         break;
3003                 case FBDC_RGBX_888:
3004                         fmt_cfg = 0;
3005                         swap_rb = 0;
3006                         win->fmt_10 = 0;
3007                         win->area[0].fbdc_fmt_cfg = 0x3a;
3008                         break;
3009                 case ARGB888:
3010                         fmt_cfg = 0;
3011                         swap_rb = 0;
3012                         win->fmt_10 = 0;
3013                         break;
3014                 case XBGR888:
3015                 case ABGR888:
3016                         fmt_cfg = 0;
3017                         swap_rb = 1;
3018                         win->fmt_10 = 0;
3019                         break;
3020                 case BGR888:
3021                         fmt_cfg = 1;
3022                         swap_rb = 1;
3023                         win->fmt_10 = 0;
3024                         break;
3025                 case RGB888:
3026                         fmt_cfg = 1;
3027                         swap_rb = 0;
3028                         win->fmt_10 = 0;
3029                         break;
3030                 case RGB565:
3031                         fmt_cfg = 2;
3032                         swap_rb = 0;
3033                         win->fmt_10 = 0;
3034                         break;
3035                 case YUV422:
3036                         fmt_cfg = 5;
3037                         swap_rb = 0;
3038                         win->fmt_10 = 0;
3039                         break;
3040                 case YUV420:
3041                         fmt_cfg = 4;
3042                         swap_rb = 0;
3043                         win->fmt_10 = 0;
3044                         break;
3045                 case YUV420_NV21:
3046                         fmt_cfg = 4;
3047                         swap_rb = 0;
3048                         swap_uv = 1;
3049                         win->fmt_10 = 0;
3050                         break;
3051                 case YUV444:
3052                         fmt_cfg = 6;
3053                         swap_rb = 0;
3054                         win->fmt_10 = 0;
3055                         break;
3056                 case YUV422_A:
3057                         fmt_cfg = 5;
3058                         swap_rb = 0;
3059                         win->fmt_10 = 1;
3060                         break;
3061                 case YUV420_A:
3062                         fmt_cfg = 4;
3063                         swap_rb = 0;
3064                         win->fmt_10 = 1;
3065                         break;
3066                 case YUV444_A:
3067                         fmt_cfg = 6;
3068                         swap_rb = 0;
3069                         win->fmt_10 = 1;
3070                         break;
3071                 default:
3072                         dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n",
3073                                 __func__);
3074                         break;
3075                 }
3076                 win->area[0].fmt_cfg = fmt_cfg;
3077                 win->area[0].swap_rb = swap_rb;
3078                 win->area[0].swap_uv = swap_uv;
3079                 win->area[0].dsp_stx = xpos;
3080                 win->area[0].dsp_sty = ypos;
3081                 xact = win->area[0].xact;
3082                 yact = win->area[0].yact;
3083                 xvir = win->area[0].xvir;
3084                 yvir = win->area[0].yvir;
3085         }
3086         if (win->area[0].fbdc_en)
3087                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
3088         rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id);
3089         spin_unlock(&lcdc_dev->reg_lock);
3090
3091         DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
3092             lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt),
3093             xact, yact, win->area[0].xsize);
3094         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
3095             win->area[0].ysize, xvir, yvir, xpos, ypos);
3096
3097         return 0;
3098 }
3099
3100
3101 static int win_2_3_set_par(struct lcdc_device *lcdc_dev,
3102                            struct rk_screen *screen, struct rk_lcdc_win *win)
3103 {
3104         int i;
3105         u8 fmt_cfg, swap_rb;
3106         char fmt[9] = "NULL";
3107
3108         if (win->ymirror)
3109                 pr_err("win[%d] not support y mirror\n", win->id);
3110         spin_lock(&lcdc_dev->reg_lock);
3111         if (likely(lcdc_dev->clk_on)) {
3112                 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id);
3113                 for (i = 0; i < win->area_num; i++) {
3114                         switch (win->area[i].format) {
3115                         case FBDC_RGB_565:
3116                                 fmt_cfg = 2;
3117                                 swap_rb = 0;
3118                                 win->fmt_10 = 0;
3119                                 win->area[0].fbdc_fmt_cfg = 0x05;
3120                                 break;
3121                         case FBDC_ARGB_888:
3122                                 fmt_cfg = 0;
3123                                 swap_rb = 0;
3124                                 win->fmt_10 = 0;
3125                                 win->area[0].fbdc_fmt_cfg = 0x0c;
3126                                 break;
3127                         case FBDC_RGBX_888:
3128                                 fmt_cfg = 0;
3129                                 swap_rb = 0;
3130                                 win->fmt_10 = 0;
3131                                 win->area[0].fbdc_fmt_cfg = 0x3a;
3132                                 break;
3133                         case ARGB888:
3134                                 fmt_cfg = 0;
3135                                 swap_rb = 0;
3136                                 break;
3137                         case XBGR888:
3138                         case ABGR888:
3139                                 fmt_cfg = 0;
3140                                 swap_rb = 1;
3141                                 break;
3142                         case RGB888:
3143                                 fmt_cfg = 1;
3144                                 swap_rb = 0;
3145                                 break;
3146                         case RGB565:
3147                                 fmt_cfg = 2;
3148                                 swap_rb = 0;
3149                                 break;
3150                         default:
3151                                 dev_err(lcdc_dev->driver.dev,
3152                                         "%s:un supported format!\n", __func__);
3153                                 break;
3154                         }
3155                         win->area[i].fmt_cfg = fmt_cfg;
3156                         win->area[i].swap_rb = swap_rb;
3157                         win->area[i].dsp_stx =
3158                                         dsp_x_pos(win->xmirror, screen,
3159                                                   &win->area[i]);
3160                         win->area[i].dsp_sty =
3161                                         dsp_y_pos(win->ymirror, screen,
3162                                                   &win->area[i]);
3163                         if (((win->area[i].xact != win->area[i].xsize) ||
3164                              (win->area[i].yact != win->area[i].ysize)) &&
3165                              !(screen->mode.vmode & FB_VMODE_INTERLACED)) {
3166                                 pr_err("win[%d]->area[%d],not support scale\n",
3167                                        win->id, i);
3168                                 pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
3169                                        win->area[i].xact, win->area[i].yact,
3170                                        win->area[i].xsize, win->area[i].ysize);
3171                                 win->area[i].xsize = win->area[i].xact;
3172                                 win->area[i].ysize = win->area[i].yact;
3173                         }
3174                         DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
3175                             get_format_string(win->area[i].format, fmt),
3176                             win->area[i].xsize, win->area[i].ysize,
3177                             win->area[i].xpos, win->area[i].ypos);
3178                 }
3179         }
3180         if (win->area[0].fbdc_en)
3181                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
3182         rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id);
3183         spin_unlock(&lcdc_dev->reg_lock);
3184         return 0;
3185 }
3186
3187 static int hwc_set_par(struct lcdc_device *lcdc_dev,
3188                        struct rk_screen *screen, struct rk_lcdc_win *win)
3189 {
3190         u32 xact, yact, xvir, yvir, xpos, ypos;
3191         u8 fmt_cfg = 0, swap_rb;
3192         char fmt[9] = "NULL";
3193
3194         xpos = win->area[0].xpos + screen->mode.left_margin +
3195             screen->mode.hsync_len;
3196         ypos = win->area[0].ypos + screen->mode.upper_margin +
3197             screen->mode.vsync_len;
3198
3199         spin_lock(&lcdc_dev->reg_lock);
3200         if (likely(lcdc_dev->clk_on)) {
3201                 /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */
3202                 switch (win->area[0].format) {
3203                 case ARGB888:
3204                         fmt_cfg = 0;
3205                         swap_rb = 0;
3206                         break;
3207                 case XBGR888:
3208                 case ABGR888:
3209                         fmt_cfg = 0;
3210                         swap_rb = 1;
3211                         break;
3212                 case RGB888:
3213                         fmt_cfg = 1;
3214                         swap_rb = 0;
3215                         break;
3216                 case RGB565:
3217                         fmt_cfg = 2;
3218                         swap_rb = 0;
3219                         break;
3220                 default:
3221                         dev_err(lcdc_dev->driver.dev,
3222                                 "%s:un supported format!\n", __func__);
3223                         break;
3224                 }
3225                 win->area[0].fmt_cfg = fmt_cfg;
3226                 win->area[0].swap_rb = swap_rb;
3227                 win->area[0].dsp_stx = xpos;
3228                 win->area[0].dsp_sty = ypos;
3229                 xact = win->area[0].xact;
3230                 yact = win->area[0].yact;
3231                 xvir = win->area[0].xvir;
3232                 yvir = win->area[0].yvir;
3233         }
3234         rk3368_hwc_reg_update(&lcdc_dev->driver, 4);
3235         spin_unlock(&lcdc_dev->reg_lock);
3236
3237         DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
3238             lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt),
3239             xact, yact, win->area[0].xsize);
3240         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
3241             win->area[0].ysize, xvir, yvir, xpos, ypos);
3242         return 0;
3243 }
3244
3245 static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
3246 {
3247         struct lcdc_device *lcdc_dev =
3248             container_of(dev_drv, struct lcdc_device, driver);
3249         struct rk_lcdc_win *win = NULL;
3250         struct rk_screen *screen = dev_drv->cur_screen;
3251
3252         if (unlikely(!lcdc_dev->clk_on)) {
3253                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
3254                 return 0;
3255         }
3256         win = dev_drv->win[win_id];
3257         switch (win_id) {
3258         case 0:
3259                 win_0_1_set_par(lcdc_dev, screen, win);
3260                 break;
3261         case 1:
3262                 win_0_1_set_par(lcdc_dev, screen, win);
3263                 break;
3264         case 2:
3265                 win_2_3_set_par(lcdc_dev, screen, win);
3266                 break;
3267         case 3:
3268                 win_2_3_set_par(lcdc_dev, screen, win);
3269                 break;
3270         case 4:
3271                 hwc_set_par(lcdc_dev, screen, win);
3272                 break;
3273         default:
3274                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
3275                 break;
3276         }
3277         return 0;
3278 }
3279
3280 static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
3281                              unsigned long arg, int win_id)
3282 {
3283         struct lcdc_device *lcdc_dev =
3284             container_of(dev_drv, struct lcdc_device, driver);
3285         u32 panel_size[2];
3286         void __user *argp = (void __user *)arg;
3287         struct color_key_cfg clr_key_cfg;
3288
3289         switch (cmd) {
3290         case RK_FBIOGET_PANEL_SIZE:
3291                 panel_size[0] = lcdc_dev->screen->mode.xres;
3292                 panel_size[1] = lcdc_dev->screen->mode.yres;
3293                 if (copy_to_user(argp, panel_size, 8))
3294                         return -EFAULT;
3295                 break;
3296         case RK_FBIOPUT_COLOR_KEY_CFG:
3297                 if (copy_from_user(&clr_key_cfg, argp,
3298                                    sizeof(struct color_key_cfg)))
3299                         return -EFAULT;
3300                 rk3368_lcdc_clr_key_cfg(dev_drv);
3301                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
3302                             clr_key_cfg.win0_color_key_cfg);
3303                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
3304                             clr_key_cfg.win1_color_key_cfg);
3305                 break;
3306
3307         default:
3308                 break;
3309         }
3310         return 0;
3311 }
3312
3313 static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
3314 {
3315         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3316                                                     struct lcdc_device, driver);
3317         struct device_node *backlight;
3318         struct property *prop;
3319         u32 brightness_levels[256];
3320         u32 length, max, last;
3321
3322         if (lcdc_dev->backlight)
3323                 return 0;
3324         backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0);
3325         if (backlight) {
3326                 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
3327                 if (!lcdc_dev->backlight)
3328                         dev_info(lcdc_dev->dev, "No find backlight device\n");
3329         } else {
3330                 dev_info(lcdc_dev->dev, "No find backlight device node\n");
3331         }
3332         prop = of_find_property(backlight, "brightness-levels", &length);
3333         if (!prop)
3334                 return -EINVAL;
3335         max = length / sizeof(u32);
3336         last = max - 1;
3337         if (!of_property_read_u32_array(backlight, "brightness-levels",
3338                                         brightness_levels, max)) {
3339                 if (brightness_levels[0] > brightness_levels[last])
3340                         dev_drv->cabc_pwm_pol = 1;/*negative*/
3341                 else
3342                         dev_drv->cabc_pwm_pol = 0;/*positive*/
3343         } else {
3344                 dev_info(lcdc_dev->dev, "Can not read brightness-levels value\n");
3345         }
3346         return 0;
3347 }
3348
3349 static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
3350 {
3351         struct lcdc_device *lcdc_dev =
3352             container_of(dev_drv, struct lcdc_device, driver);
3353         u32 intr_clr_reg;
3354
3355         if (lcdc_dev->soc_type == VOP_FULL_RK3366)
3356                 intr_clr_reg = INTR_CLEAR_RK3366;
3357         else
3358                 intr_clr_reg = INTR_CLEAR_RK3368;
3359
3360         if (dev_drv->suspend_flag)
3361                 return 0;
3362         /* close the backlight */
3363         /*rk3368_lcdc_get_backlight_device(dev_drv);
3364         if (lcdc_dev->backlight) {
3365                 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
3366                 backlight_update_status(lcdc_dev->backlight);
3367         }*/
3368
3369         dev_drv->suspend_flag = 1;
3370         flush_kthread_worker(&dev_drv->update_regs_worker);
3371
3372         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3373                 dev_drv->trsm_ops->disable();
3374
3375         spin_lock(&lcdc_dev->reg_lock);
3376         if (likely(lcdc_dev->clk_on)) {
3377                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3378                              v_DSP_BLANK_EN(1));
3379                 lcdc_msk_reg(lcdc_dev,
3380                              intr_clr_reg, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR,
3381                              v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1));
3382                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3383                              v_DSP_OUT_ZERO(1));
3384                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
3385                 lcdc_cfg_done(lcdc_dev);
3386
3387                 if (dev_drv->iommu_enabled) {
3388                         if (dev_drv->mmu_dev)
3389                                 rockchip_iovmm_deactivate(dev_drv->dev);
3390                 }
3391
3392                 spin_unlock(&lcdc_dev->reg_lock);
3393         } else {
3394                 spin_unlock(&lcdc_dev->reg_lock);
3395                 return 0;
3396         }
3397         rk3368_lcdc_clk_disable(lcdc_dev);
3398         rk_disp_pwr_disable(dev_drv);
3399         return 0;
3400 }
3401
3402 static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
3403 {
3404         struct lcdc_device *lcdc_dev =
3405             container_of(dev_drv, struct lcdc_device, driver);
3406
3407         if (!dev_drv->suspend_flag)
3408                 return 0;
3409         rk_disp_pwr_enable(dev_drv);
3410
3411         if (1/*lcdc_dev->atv_layer_cnt*/) {
3412                 rk3368_lcdc_clk_enable(lcdc_dev);
3413                 rk3368_lcdc_reg_restore(lcdc_dev);
3414
3415                 spin_lock(&lcdc_dev->reg_lock);
3416                 if (dev_drv->cur_screen->dsp_lut)
3417                         rk3368_lcdc_set_lut(dev_drv,
3418                                             dev_drv->cur_screen->dsp_lut);
3419                 if (dev_drv->cur_screen->cabc_lut && dev_drv->cabc_mode)
3420                         rk3368_set_cabc_lut(dev_drv,
3421                                             dev_drv->cur_screen->cabc_lut);
3422
3423                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3424                              v_DSP_OUT_ZERO(0));
3425                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
3426                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3427                              v_DSP_BLANK_EN(0));
3428                 lcdc_cfg_done(lcdc_dev);
3429
3430                 if (dev_drv->iommu_enabled) {
3431                         /* win address maybe effect after next frame start,
3432                          * but mmu maybe effect right now, so we delay 50ms
3433                          */
3434                         mdelay(50);
3435                         if (dev_drv->mmu_dev)
3436                                 rockchip_iovmm_activate(dev_drv->dev);
3437                 }
3438
3439                 spin_unlock(&lcdc_dev->reg_lock);
3440         }
3441         dev_drv->suspend_flag = 0;
3442
3443         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3444                 dev_drv->trsm_ops->enable();
3445         mdelay(100);
3446         return 0;
3447 }
3448
3449 static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv,
3450                              int win_id, int blank_mode)
3451 {
3452         switch (blank_mode) {
3453         case FB_BLANK_UNBLANK:
3454                 rk3368_lcdc_early_resume(dev_drv);
3455                 break;
3456         case FB_BLANK_NORMAL:
3457                 rk3368_lcdc_early_suspend(dev_drv);
3458                 break;
3459         default:
3460                 rk3368_lcdc_early_suspend(dev_drv);
3461                 break;
3462         }
3463
3464         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
3465
3466         return 0;
3467 }
3468
3469 static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv,
3470                                      int win_id, int area_id)
3471 {
3472         struct lcdc_device *lcdc_dev =
3473                 container_of(dev_drv, struct lcdc_device, driver);
3474         u32 win_ctrl = 0;
3475         u32 area_status = 0, state = 0;
3476
3477         switch (win_id) {
3478         case 0:
3479                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3480                 area_status = win_ctrl & m_WIN0_EN;
3481                 break;
3482         case 1:
3483                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3484                 area_status = win_ctrl & m_WIN1_EN;
3485                 break;
3486         case 2:
3487                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3488                 if (area_id == 0)
3489                         area_status = win_ctrl & (m_WIN2_MST0_EN | m_WIN2_EN);
3490                 if (area_id == 1)
3491                         area_status = win_ctrl & m_WIN2_MST1_EN;
3492                 if (area_id == 2)
3493                         area_status = win_ctrl & m_WIN2_MST2_EN;
3494                 if (area_id == 3)
3495                         area_status = win_ctrl & m_WIN2_MST3_EN;
3496                 break;
3497         case 3:
3498                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3499                 if (area_id == 0)
3500                         area_status = win_ctrl & (m_WIN3_MST0_EN | m_WIN3_EN);
3501                 if (area_id == 1)
3502                         area_status = win_ctrl & m_WIN3_MST1_EN;
3503                 if (area_id == 2)
3504                         area_status = win_ctrl & m_WIN3_MST2_EN;
3505                 if (area_id == 3)
3506                         area_status = win_ctrl & m_WIN3_MST3_EN;
3507                 break;
3508         case 4:
3509                 win_ctrl = lcdc_readl(lcdc_dev, HWC_CTRL0);
3510                 area_status = win_ctrl & m_HWC_EN;
3511                 break;
3512         default:
3513                 pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n",
3514                        __func__, win_id, area_id);
3515                 break;
3516         }
3517
3518         state = (area_status > 0) ? 1 : 0;
3519         return state;
3520 }
3521
3522 static int rk3368_lcdc_get_area_num(struct rk_lcdc_driver *dev_drv,
3523                                     unsigned int *area_support)
3524 {
3525         area_support[0] = 1;
3526         area_support[1] = 1;
3527         area_support[2] = 4;
3528         area_support[3] = 4;
3529
3530         return 0;
3531 }
3532
3533 /*overlay will be do at regupdate*/
3534 static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
3535                                bool set)
3536 {
3537         struct lcdc_device *lcdc_dev =
3538             container_of(dev_drv, struct lcdc_device, driver);
3539         struct rk_lcdc_win *win = NULL;
3540         int i, ovl;
3541         unsigned int mask, val;
3542         int z_order_num = 0;
3543         int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3544
3545         if (swap == 0) {
3546                 for (i = 0; i < 4; i++) {
3547                         win = dev_drv->win[i];
3548                         if (win->state == 1)
3549                                 z_order_num++;
3550                 }
3551                 for (i = 0; i < 4; i++) {
3552                         win = dev_drv->win[i];
3553                         if (win->state == 0)
3554                                 win->z_order = z_order_num++;
3555                         switch (win->z_order) {
3556                         case 0:
3557                                 layer0_sel = win->id;
3558                                 break;
3559                         case 1:
3560                                 layer1_sel = win->id;
3561                                 break;
3562                         case 2:
3563                                 layer2_sel = win->id;
3564                                 break;
3565                         case 3:
3566                                 layer3_sel = win->id;
3567                                 break;
3568                         default:
3569                                 break;
3570                         }
3571                 }
3572         } else {
3573                 layer0_sel = swap % 10;
3574                 layer1_sel = swap / 10 % 10;
3575                 layer2_sel = swap / 100 % 10;
3576                 layer3_sel = swap / 1000;
3577         }
3578
3579         spin_lock(&lcdc_dev->reg_lock);
3580         if (lcdc_dev->clk_on) {
3581                 if (set) {
3582                         mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
3583                             m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
3584                         val = v_DSP_LAYER0_SEL(layer0_sel) |
3585                             v_DSP_LAYER1_SEL(layer1_sel) |
3586                             v_DSP_LAYER2_SEL(layer2_sel) |
3587                             v_DSP_LAYER3_SEL(layer3_sel);
3588                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
3589                 } else {
3590                         layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3591                                                    m_DSP_LAYER0_SEL);
3592                         layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3593                                                    m_DSP_LAYER1_SEL);
3594                         layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3595                                                    m_DSP_LAYER2_SEL);
3596                         layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3597                                                    m_DSP_LAYER3_SEL);
3598                         ovl = layer3_sel * 1000 + layer2_sel * 100 +
3599                             layer1_sel * 10 + layer0_sel;
3600                 }
3601         } else {
3602                 ovl = -EPERM;
3603         }
3604         spin_unlock(&lcdc_dev->reg_lock);
3605
3606         return ovl;
3607 }
3608
3609 static char *rk3368_lcdc_format_to_string(int format, char *fmt)
3610 {
3611         if (!fmt)
3612                 return NULL;
3613
3614         switch (format) {
3615         case 0:
3616                 strcpy(fmt, "ARGB888");
3617                 break;
3618         case 1:
3619                 strcpy(fmt, "RGB888");
3620                 break;
3621         case 2:
3622                 strcpy(fmt, "RGB565");
3623                 break;
3624         case 4:
3625                 strcpy(fmt, "YCbCr420");
3626                 break;
3627         case 5:
3628                 strcpy(fmt, "YCbCr422");
3629                 break;
3630         case 6:
3631                 strcpy(fmt, "YCbCr444");
3632                 break;
3633         default:
3634                 strcpy(fmt, "invalid\n");
3635                 break;
3636         }
3637         return fmt;
3638 }
3639 static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
3640                                          char *buf, int win_id)
3641 {
3642         struct lcdc_device *lcdc_dev =
3643             container_of(dev_drv, struct lcdc_device, driver);
3644         struct rk_screen *screen = dev_drv->cur_screen;
3645         u16 hsync_len = screen->mode.hsync_len;
3646         u16 left_margin = screen->mode.left_margin;
3647         u16 vsync_len = screen->mode.vsync_len;
3648         u16 upper_margin = screen->mode.upper_margin;
3649         u32 h_pw_bp = hsync_len + left_margin;
3650         u32 v_pw_bp = vsync_len + upper_margin;
3651         u32 fmt_id;
3652         char format_w0[9] = "NULL";
3653         char format_w1[9] = "NULL";
3654         char format_w2_0[9] = "NULL";
3655         char format_w2_1[9] = "NULL";
3656         char format_w2_2[9] = "NULL";
3657         char format_w2_3[9] = "NULL";
3658         char format_w3_0[9] = "NULL";
3659         char format_w3_1[9] = "NULL";
3660         char format_w3_2[9] = "NULL";
3661         char format_w3_3[9] = "NULL";
3662         char dsp_buf[100];
3663         u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3664         u32 y_factor, uv_factor;
3665         u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3666         u8 w0_state, w1_state, w2_state, w3_state;
3667         u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3668         u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3669
3670         u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3671         u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3672         u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3673         u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3674         u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3675         u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3676
3677         u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3678         u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3679         u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3680         u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3681         u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3682         u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3683         u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3684
3685         u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3686         u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3687         u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3688         u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3689         u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3690         u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3691         u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3692         u32 dclk_freq;
3693         int size = 0;
3694
3695         dclk_freq = screen->mode.pixclock;
3696         /*rk3368_lcdc_reg_dump(dev_drv); */
3697
3698         spin_lock(&lcdc_dev->reg_lock);
3699         if (lcdc_dev->clk_on) {
3700                 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
3701                 layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8;
3702                 layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10;
3703                 layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12;
3704                 layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14;
3705                 /*WIN0 */
3706                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3707                 w0_state = win_ctrl & m_WIN0_EN;
3708                 fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1;
3709                 rk3368_lcdc_format_to_string(fmt_id, format_w0);
3710                 vir_info = lcdc_readl(lcdc_dev, WIN0_VIR);
3711                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
3712                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
3713                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
3714                 y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
3715                 uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR);
3716                 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
3717                 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16;
3718                 w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1;
3719                 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1;
3720                 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1;
3721                 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1;
3722                 if (w0_state) {
3723                         w0_st_x = dsp_st & m_WIN0_DSP_XST;
3724                         w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16;
3725                 }
3726                 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
3727                 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16;
3728                 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
3729                 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16;
3730
3731                 /*WIN1 */
3732                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3733                 w1_state = win_ctrl & m_WIN1_EN;
3734                 fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1;
3735                 rk3368_lcdc_format_to_string(fmt_id, format_w1);
3736                 vir_info = lcdc_readl(lcdc_dev, WIN1_VIR);
3737                 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
3738                 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
3739                 dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
3740                 y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB);
3741                 uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR);
3742                 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
3743                 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16;
3744                 w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1;
3745                 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1;
3746                 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1;
3747                 w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1;
3748                 if (w1_state) {
3749                         w1_st_x = dsp_st & m_WIN1_DSP_XST;
3750                         w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16;
3751                 }
3752                 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
3753                 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16;
3754                 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
3755                 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16;
3756                 /*WIN2 */
3757                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3758                 w2_state = win_ctrl & m_WIN2_EN;
3759                 w2_0_state = (win_ctrl & 0x10) >> 4;
3760                 w2_1_state = (win_ctrl & 0x100) >> 8;
3761                 w2_2_state = (win_ctrl & 0x1000) >> 12;
3762                 w2_3_state = (win_ctrl & 0x10000) >> 16;
3763                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1);
3764                 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3765                 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16;
3766                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3);
3767                 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3768                 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16;
3769
3770                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1;
3771                 rk3368_lcdc_format_to_string(fmt_id, format_w2_0);
3772                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1;
3773                 rk3368_lcdc_format_to_string(fmt_id, format_w2_1);
3774                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1;
3775                 rk3368_lcdc_format_to_string(fmt_id, format_w2_2);
3776                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1;
3777                 rk3368_lcdc_format_to_string(fmt_id, format_w2_3);
3778
3779                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0);
3780                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0);
3781                 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1;
3782                 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1;
3783                 if (w2_0_state) {
3784                         w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3785                         w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16;
3786                 }
3787                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1);
3788                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1);
3789                 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1;
3790                 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1;
3791                 if (w2_1_state) {
3792                         w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3793                         w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16;
3794                 }
3795                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2);
3796                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2);
3797                 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1;
3798                 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1;
3799                 if (w2_2_state) {
3800                         w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3801                         w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16;
3802                 }
3803                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3);
3804                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3);
3805                 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1;
3806                 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1;
3807                 if (w2_3_state) {
3808                         w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3809                         w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16;
3810                 }
3811
3812                 /*WIN3 */
3813                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3814                 w3_state = win_ctrl & m_WIN3_EN;
3815                 w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4;
3816                 w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 8;
3817                 w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 12;
3818                 w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 16;
3819                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1);
3820                 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3821                 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16;
3822                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3);
3823                 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3824                 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16;
3825                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1;
3826                 rk3368_lcdc_format_to_string(fmt_id, format_w3_0);
3827                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1;
3828                 rk3368_lcdc_format_to_string(fmt_id, format_w3_1);
3829                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1;
3830                 rk3368_lcdc_format_to_string(fmt_id, format_w3_2);
3831                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1;
3832                 rk3368_lcdc_format_to_string(fmt_id, format_w3_3);
3833                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0);
3834                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0);
3835                 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1;
3836                 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1;
3837                 if (w3_0_state) {
3838                         w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3839                         w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16;
3840                 }
3841
3842                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1);
3843                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1);
3844                 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1;
3845                 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1;
3846                 if (w3_1_state) {
3847                         w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3848                         w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16;
3849                 }
3850
3851                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2);
3852                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2);
3853                 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1;
3854                 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1;
3855                 if (w3_2_state) {
3856                         w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3857                         w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16;
3858                 }
3859
3860                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3);
3861                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3);
3862                 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1;
3863                 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1;
3864                 if (w3_3_state) {
3865                         w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3866                         w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16;
3867                 }
3868
3869         } else {
3870                 spin_unlock(&lcdc_dev->reg_lock);
3871                 return -EPERM;
3872         }
3873         spin_unlock(&lcdc_dev->reg_lock);
3874         size += snprintf(dsp_buf, 80,
3875                 "z-order:\n  win[%d]\n  win[%d]\n  win[%d]\n  win[%d]\n",
3876                 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3877         strcat(buf, dsp_buf);
3878         memset(dsp_buf, 0, sizeof(dsp_buf));
3879         /*win0*/
3880         size += snprintf(dsp_buf, 80,
3881                  "win0:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3882                  w0_state, format_w0, w0_vir_y, w0_vir_uv);
3883         strcat(buf, dsp_buf);
3884         memset(dsp_buf, 0, sizeof(dsp_buf));
3885
3886         size += snprintf(dsp_buf, 80,
3887                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3888                  w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3889         strcat(buf, dsp_buf);
3890         memset(dsp_buf, 0, sizeof(dsp_buf));
3891
3892         size += snprintf(dsp_buf, 80,
3893                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3894                  w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3895         strcat(buf, dsp_buf);
3896         memset(dsp_buf, 0, sizeof(dsp_buf));
3897
3898         size += snprintf(dsp_buf, 80,
3899                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3900                  w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3901                  lcdc_readl(lcdc_dev, WIN0_CBR_MST));
3902         strcat(buf, dsp_buf);
3903         memset(dsp_buf, 0, sizeof(dsp_buf));
3904
3905         /*win1*/
3906         size += snprintf(dsp_buf, 80,
3907                  "win1:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3908                  w1_state, format_w1, w1_vir_y, w1_vir_uv);
3909         strcat(buf, dsp_buf);
3910         memset(dsp_buf, 0, sizeof(dsp_buf));
3911
3912         size += snprintf(dsp_buf, 80,
3913                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3914                  w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3915         strcat(buf, dsp_buf);
3916         memset(dsp_buf, 0, sizeof(dsp_buf));
3917
3918         size += snprintf(dsp_buf, 80,
3919                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3920                  w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3921         strcat(buf, dsp_buf);
3922         memset(dsp_buf, 0, sizeof(dsp_buf));
3923
3924         size += snprintf(dsp_buf, 80,
3925                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3926                  w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3927                  lcdc_readl(lcdc_dev, WIN1_CBR_MST));
3928         strcat(buf, dsp_buf);
3929         memset(dsp_buf, 0, sizeof(dsp_buf));
3930
3931         /*win2*/
3932         size += snprintf(dsp_buf, 80,
3933                  "win2:\n  state:%d\n",
3934                  w2_state);
3935         strcat(buf, dsp_buf);
3936         memset(dsp_buf, 0, sizeof(dsp_buf));
3937         /*area 0*/
3938         size += snprintf(dsp_buf, 80,
3939                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3940                  w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3941         strcat(buf, dsp_buf);
3942         memset(dsp_buf, 0, sizeof(dsp_buf));
3943         size += snprintf(dsp_buf, 80,
3944                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3945                  w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3946                  lcdc_readl(lcdc_dev, WIN2_MST0));
3947         strcat(buf, dsp_buf);
3948         memset(dsp_buf, 0, sizeof(dsp_buf));
3949
3950         /*area 1*/
3951         size += snprintf(dsp_buf, 80,
3952                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3953                  w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3954         strcat(buf, dsp_buf);
3955         memset(dsp_buf, 0, sizeof(dsp_buf));
3956         size += snprintf(dsp_buf, 80,
3957                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3958                  w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3959                  lcdc_readl(lcdc_dev, WIN2_MST1));
3960         strcat(buf, dsp_buf);
3961         memset(dsp_buf, 0, sizeof(dsp_buf));
3962
3963         /*area 2*/
3964         size += snprintf(dsp_buf, 80,
3965                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3966                  w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3967         strcat(buf, dsp_buf);
3968         memset(dsp_buf, 0, sizeof(dsp_buf));
3969         size += snprintf(dsp_buf, 80,
3970                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3971                  w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3972                  lcdc_readl(lcdc_dev, WIN2_MST2));
3973         strcat(buf, dsp_buf);
3974         memset(dsp_buf, 0, sizeof(dsp_buf));
3975
3976         /*area 3*/
3977         size += snprintf(dsp_buf, 80,
3978                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3979                  w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3980         strcat(buf, dsp_buf);
3981         memset(dsp_buf, 0, sizeof(dsp_buf));
3982         size += snprintf(dsp_buf, 80,
3983                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3984                  w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3985                  lcdc_readl(lcdc_dev, WIN2_MST3));
3986         strcat(buf, dsp_buf);
3987         memset(dsp_buf, 0, sizeof(dsp_buf));
3988
3989         /*win3*/
3990         size += snprintf(dsp_buf, 80,
3991                  "win3:\n  state:%d\n",
3992                  w3_state);
3993         strcat(buf, dsp_buf);
3994         memset(dsp_buf, 0, sizeof(dsp_buf));
3995         /*area 0*/
3996         size += snprintf(dsp_buf, 80,
3997                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3998                  w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
3999         strcat(buf, dsp_buf);
4000         memset(dsp_buf, 0, sizeof(dsp_buf));
4001         size += snprintf(dsp_buf, 80,
4002                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4003                  w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
4004                  lcdc_readl(lcdc_dev, WIN3_MST0));
4005         strcat(buf, dsp_buf);
4006         memset(dsp_buf, 0, sizeof(dsp_buf));
4007
4008         /*area 1*/
4009         size += snprintf(dsp_buf, 80,
4010                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4011                  w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
4012         strcat(buf, dsp_buf);
4013         memset(dsp_buf, 0, sizeof(dsp_buf));
4014         size += snprintf(dsp_buf, 80,
4015                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4016                  w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
4017                  lcdc_readl(lcdc_dev, WIN3_MST1));
4018         strcat(buf, dsp_buf);
4019         memset(dsp_buf, 0, sizeof(dsp_buf));
4020
4021         /*area 2*/
4022         size += snprintf(dsp_buf, 80,
4023                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4024                  w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
4025         strcat(buf, dsp_buf);
4026         memset(dsp_buf, 0, sizeof(dsp_buf));
4027         size += snprintf(dsp_buf, 80,
4028                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4029                  w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
4030                  lcdc_readl(lcdc_dev, WIN3_MST2));
4031         strcat(buf, dsp_buf);
4032         memset(dsp_buf, 0, sizeof(dsp_buf));
4033
4034         /*area 3*/
4035         size += snprintf(dsp_buf, 80,
4036                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4037                  w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
4038         strcat(buf, dsp_buf);
4039         memset(dsp_buf, 0, sizeof(dsp_buf));
4040         size += snprintf(dsp_buf, 80,
4041                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4042                  w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
4043                  lcdc_readl(lcdc_dev, WIN3_MST3));
4044         strcat(buf, dsp_buf);
4045         memset(dsp_buf, 0, sizeof(dsp_buf));
4046
4047         return size;
4048 }
4049
4050 static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
4051                                bool set)
4052 {
4053         struct lcdc_device *lcdc_dev =
4054             container_of(dev_drv, struct lcdc_device, driver);
4055         struct rk_screen *screen = dev_drv->cur_screen;
4056         u64 ft = 0;
4057         u32 dotclk;
4058         int ret;
4059         u32 pixclock;
4060         u32 x_total, y_total;
4061
4062         if (set) {
4063                 if (fps == 0) {
4064                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
4065                         return 0;
4066                 }
4067                 ft = div_u64(1000000000000llu, fps);
4068                 x_total =
4069                     screen->mode.upper_margin + screen->mode.lower_margin +
4070                     screen->mode.yres + screen->mode.vsync_len;
4071                 y_total =
4072                     screen->mode.left_margin + screen->mode.right_margin +
4073                     screen->mode.xres + screen->mode.hsync_len;
4074                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
4075                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
4076                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
4077         }
4078
4079         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
4080         lcdc_dev->pixclock = pixclock;
4081         dev_drv->pixclock = lcdc_dev->pixclock;
4082         fps = rk_fb_calc_fps(screen, pixclock);
4083         screen->ft = 1000 / fps;        /*one frame time in ms */
4084
4085         if (set)
4086                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
4087                          clk_get_rate(lcdc_dev->dclk), fps);
4088
4089         return fps;
4090 }
4091
4092 static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
4093 {
4094         mutex_lock(&dev_drv->fb_win_id_mutex);
4095         if (order == FB_DEFAULT_ORDER)
4096                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
4097         dev_drv->fb4_win_id = order / 10000;
4098         dev_drv->fb3_win_id = (order / 1000) % 10;
4099         dev_drv->fb2_win_id = (order / 100) % 10;
4100         dev_drv->fb1_win_id = (order / 10) % 10;
4101         dev_drv->fb0_win_id = order % 10;
4102         mutex_unlock(&dev_drv->fb_win_id_mutex);
4103
4104         return 0;
4105 }
4106
4107 static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
4108                                   const char *id)
4109 {
4110         int win_id = 0;
4111
4112         mutex_lock(&dev_drv->fb_win_id_mutex);
4113         if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
4114                 win_id = dev_drv->fb0_win_id;
4115         else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
4116                 win_id = dev_drv->fb1_win_id;
4117         else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
4118                 win_id = dev_drv->fb2_win_id;
4119         else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
4120                 win_id = dev_drv->fb3_win_id;
4121         else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
4122                 win_id = dev_drv->fb4_win_id;
4123         mutex_unlock(&dev_drv->fb_win_id_mutex);
4124
4125         return win_id;
4126 }
4127
4128 static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
4129 {
4130         struct lcdc_device *lcdc_dev =
4131             container_of(dev_drv, struct lcdc_device, driver);
4132         int i;
4133         unsigned int mask, val, fbdc_en = 0;
4134         struct rk_lcdc_win *win = NULL;
4135         u32 line_scane_num, dsp_vs_st_f1;
4136
4137         if (lcdc_dev->driver.cur_screen->mode.vmode & FB_VMODE_INTERLACED) {
4138                 dsp_vs_st_f1 = lcdc_readl(lcdc_dev, DSP_VS_ST_END_F1) >> 16;
4139                 for (i = 0; i < 1000; i++) {
4140                         line_scane_num =
4141                                 lcdc_readl(lcdc_dev, SCAN_LINE_NUM) & 0x1fff;
4142                         if (line_scane_num > dsp_vs_st_f1 + 1)
4143                                 udelay(50);
4144                         else
4145                                 break;
4146                 }
4147         }
4148
4149         spin_lock(&lcdc_dev->reg_lock);
4150         rk3368_lcdc_post_cfg(dev_drv);
4151         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
4152                      v_STANDBY_EN(lcdc_dev->standby));
4153         for (i = 0; i < 4; i++) {
4154                 win = dev_drv->win[i];
4155                 fbdc_en |= win->area[0].fbdc_en;
4156                 if ((win->state == 0) && (win->last_state == 1)) {
4157                         switch (win->id) {
4158                         case 0:
4159                                 /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
4160                                    for rk3288 to fix hw bug? */
4161                                 mask = m_WIN0_EN;
4162                                 val = v_WIN0_EN(0);
4163                                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
4164                                 break;
4165                         case 1:
4166                                 /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
4167                                    for rk3288 to fix hw bug? */
4168                                 mask = m_WIN1_EN;
4169                                 val = v_WIN1_EN(0);
4170                                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
4171                                 break;
4172                         case 2:
4173                                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
4174                                     m_WIN2_MST1_EN |
4175                                     m_WIN2_MST2_EN | m_WIN2_MST3_EN;
4176                                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
4177                                     v_WIN2_MST1_EN(0) |
4178                                     v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
4179                                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
4180                                 break;
4181                         case 3:
4182                                 mask = m_WIN3_EN | m_WIN3_MST0_EN |
4183                                     m_WIN3_MST1_EN |
4184                                     m_WIN3_MST2_EN | m_WIN3_MST3_EN;
4185                                 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |
4186                                     v_WIN3_MST1_EN(0) |
4187                                     v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
4188                                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
4189                                 break;
4190                         case 4:
4191                                 mask = m_HWC_EN;
4192                                 val = v_HWC_EN(0);
4193                                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
4194                                 break;
4195                         default:
4196                                 break;
4197                         }
4198                 }
4199                 win->last_state = win->state;
4200         }
4201         if (lcdc_dev->soc_type == VOP_FULL_RK3368) {
4202                 mask = m_IFBDC_CTRL_FBDC_EN;
4203                 val = v_IFBDC_CTRL_FBDC_EN(fbdc_en);
4204                 lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
4205         }
4206         lcdc_cfg_done(lcdc_dev);
4207         spin_unlock(&lcdc_dev->reg_lock);
4208         return 0;
4209 }
4210
4211 static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
4212                                       int enable)
4213 {
4214         struct lcdc_device *lcdc_dev =
4215             container_of(dev_drv, struct lcdc_device, driver);
4216         if (enable)
4217                 enable_irq(lcdc_dev->irq);
4218         else
4219                 disable_irq(lcdc_dev->irq);
4220         return 0;
4221 }
4222
4223 int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
4224 {
4225         struct lcdc_device *lcdc_dev =
4226             container_of(dev_drv, struct lcdc_device, driver);
4227         u32 int_reg_val;
4228         int ret;
4229         u32 intr_status_reg, intr_clear_reg;
4230
4231         if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
4232                 intr_status_reg = INTR_STATUS_RK3366;
4233                 intr_clear_reg = INTR_CLEAR_RK3366;
4234         } else {
4235                 intr_status_reg = INTR_STATUS_RK3368;
4236                 intr_clear_reg = INTR_CLEAR_RK3368;
4237         }
4238
4239         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
4240                 int_reg_val = lcdc_readl(lcdc_dev, intr_status_reg);
4241                 if (int_reg_val & m_LINE_FLAG0_INTR_STS) {
4242                         lcdc_dev->driver.frame_time.last_framedone_t =
4243                             lcdc_dev->driver.frame_time.framedone_t;
4244                         lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4245                         lcdc_msk_reg(lcdc_dev, intr_clear_reg,
4246                                      m_LINE_FLAG0_INTR_CLR,
4247                                      v_LINE_FLAG0_INTR_CLR(1));
4248                         ret = RK_LF_STATUS_FC;
4249                 } else {
4250                         ret = RK_LF_STATUS_FR;
4251                 }
4252         } else {
4253                 ret = RK_LF_STATUS_NC;
4254         }
4255
4256         return ret;
4257 }
4258
4259 static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
4260                                     unsigned int dsp_addr[][4])
4261 {
4262         struct lcdc_device *lcdc_dev =
4263             container_of(dev_drv, struct lcdc_device, driver);
4264         spin_lock(&lcdc_dev->reg_lock);
4265         if (lcdc_dev->clk_on) {
4266                 dsp_addr[0][0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
4267                 dsp_addr[1][0] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
4268                 dsp_addr[2][0] = lcdc_readl(lcdc_dev, WIN2_MST0);
4269                 dsp_addr[2][1] = lcdc_readl(lcdc_dev, WIN2_MST1);
4270                 dsp_addr[2][2] = lcdc_readl(lcdc_dev, WIN2_MST2);
4271                 dsp_addr[2][3] = lcdc_readl(lcdc_dev, WIN2_MST3);
4272                 dsp_addr[3][0] = lcdc_readl(lcdc_dev, WIN3_MST0);
4273                 dsp_addr[3][1] = lcdc_readl(lcdc_dev, WIN3_MST1);
4274                 dsp_addr[3][2] = lcdc_readl(lcdc_dev, WIN3_MST2);
4275                 dsp_addr[3][3] = lcdc_readl(lcdc_dev, WIN3_MST3);
4276         }
4277         spin_unlock(&lcdc_dev->reg_lock);
4278         return 0;
4279 }
4280
4281 static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv,
4282                                     int mode, int calc, int up,
4283                                     int down, int global)
4284 {
4285         struct lcdc_device *lcdc_dev =
4286                 container_of(dev_drv, struct lcdc_device, driver);
4287         struct rk_screen *screen = dev_drv->cur_screen;
4288         u32 total_pixel, calc_pixel, stage_up, stage_down;
4289         u32 pixel_num, global_dn;
4290         u32 mask = 0, val = 0;
4291         int *cabc_lut = NULL;
4292
4293         if (screen->type == SCREEN_HDMI && screen->type == SCREEN_TVOUT) {
4294                 pr_err("screen type is %d, not support cabc\n", screen->type);
4295                 return 0;
4296         } else if (!screen->cabc_lut) {
4297                 pr_err("screen cabc lut not config, so not open cabc\n");
4298                 return 0;
4299         } else {
4300                 cabc_lut = screen->cabc_lut;
4301         }
4302
4303         if (mode == 0) {
4304                 spin_lock(&lcdc_dev->reg_lock);
4305                 if (lcdc_dev->clk_on) {
4306                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
4307                                      m_CABC_EN, v_CABC_EN(0));
4308                         lcdc_cfg_done(lcdc_dev);
4309                 }
4310                 pr_info("mode = 0, close cabc\n");
4311                 dev_drv->cabc_mode = mode;
4312                 spin_unlock(&lcdc_dev->reg_lock);
4313                 return 0;
4314         }
4315         if (dev_drv->cabc_mode == 0)
4316                 rk3368_set_cabc_lut(dev_drv, dev_drv->cur_screen->cabc_lut);
4317
4318         total_pixel = screen->mode.xres * screen->mode.yres;
4319         pixel_num = 1000 - calc;
4320         calc_pixel = (total_pixel * pixel_num) / 1000;
4321         stage_up = up;
4322         stage_down = down;
4323         global_dn = global;
4324         pr_info("enable cabc:mode=%d, calc=%d, up=%d, down=%d, global=%d\n",
4325                 mode, calc, stage_up, stage_down, global_dn);
4326
4327         spin_lock(&lcdc_dev->reg_lock);
4328         if (lcdc_dev->clk_on) {
4329                 mask = m_CABC_EN | m_CABC_HANDLE_EN | m_PWM_CONFIG_MODE |
4330                         m_CABC_CALC_PIXEL_NUM;
4331                 val = v_CABC_EN(1) | v_CABC_HANDLE_EN(1) |
4332                         v_PWM_CONFIG_MODE(STAGE_BY_STAGE) |
4333                         v_CABC_CALC_PIXEL_NUM(calc_pixel);
4334                 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
4335
4336                 mask = m_CABC_LUT_EN | m_CABC_TOTAL_PIXEL_NUM;
4337                 val = v_CABC_LUT_EN(1) | v_CABC_TOTAL_PIXEL_NUM(total_pixel);
4338                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
4339
4340                 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_UP |
4341                         m_CABC_STAGE_MODE | m_MAX_SCALE_CFG_VALUE |
4342                         m_MAX_SCALE_CFG_ENABLE;
4343                 val = v_CABC_STAGE_DOWN(stage_down) |
4344                         v_CABC_STAGE_UP(stage_up) |
4345                         v_CABC_STAGE_MODE(0) | v_MAX_SCALE_CFG_VALUE(1) |
4346                         v_MAX_SCALE_CFG_ENABLE(0);
4347                 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
4348
4349                 mask = m_CABC_GLOBAL_DN | m_CABC_GLOBAL_DN_LIMIT_EN;
4350                 val = v_CABC_GLOBAL_DN(global_dn) |
4351                         v_CABC_GLOBAL_DN_LIMIT_EN(1);
4352                 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
4353                 lcdc_cfg_done(lcdc_dev);
4354                 dev_drv->cabc_mode = mode;
4355         }
4356         spin_unlock(&lcdc_dev->reg_lock);
4357
4358         return 0;
4359 }
4360
4361 /*
4362         a:[-30~0]:
4363             sin_hue = sin(a)*256 +0x100;
4364             cos_hue = cos(a)*256;
4365         a:[0~30]
4366             sin_hue = sin(a)*256;
4367             cos_hue = cos(a)*256;
4368 */
4369 static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
4370                                     bcsh_hue_mode mode)
4371 {
4372         struct lcdc_device *lcdc_dev =
4373             container_of(dev_drv, struct lcdc_device, driver);
4374         u32 val;
4375
4376         spin_lock(&lcdc_dev->reg_lock);
4377         if (lcdc_dev->clk_on) {
4378                 val = lcdc_readl(lcdc_dev, BCSH_H);
4379                 switch (mode) {
4380                 case H_SIN:
4381                         val &= m_BCSH_SIN_HUE;
4382                         break;
4383                 case H_COS:
4384                         val &= m_BCSH_COS_HUE;
4385                         val >>= 16;
4386                         break;
4387                 default:
4388                         break;
4389                 }
4390         }
4391         spin_unlock(&lcdc_dev->reg_lock);
4392
4393         return val;
4394 }
4395
4396 static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
4397                                     int sin_hue, int cos_hue)
4398 {
4399         struct lcdc_device *lcdc_dev =
4400             container_of(dev_drv, struct lcdc_device, driver);
4401         u32 mask, val;
4402
4403         spin_lock(&lcdc_dev->reg_lock);
4404         if (lcdc_dev->clk_on) {
4405                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
4406                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
4407                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
4408                 lcdc_cfg_done(lcdc_dev);
4409         }
4410         spin_unlock(&lcdc_dev->reg_lock);
4411
4412         return 0;
4413 }
4414
4415 static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4416                                     bcsh_bcs_mode mode, int value)
4417 {
4418         struct lcdc_device *lcdc_dev =
4419             container_of(dev_drv, struct lcdc_device, driver);
4420         u32 mask, val;
4421
4422         spin_lock(&lcdc_dev->reg_lock);
4423         if (lcdc_dev->clk_on) {
4424                 switch (mode) {
4425                 case BRIGHTNESS:
4426                         /*user: from 0 to 255,typical is 128,
4427                          *vop,6bit: from 0 to 64, typical is 32*/
4428                         value /= 4;
4429                         if (value < 0x20)
4430                                 value += 0x20;
4431                         else if (value >= 0x20)
4432                                 value = value - 0x20;
4433                         mask = m_BCSH_BRIGHTNESS;
4434                         val = v_BCSH_BRIGHTNESS(value);
4435                         break;
4436                 case CONTRAST:
4437                         /*user: from 0 to 510,typical is 256
4438                          *vop,9bit, from 0 to 511,typical is 256*/
4439                         value = 512 - value;
4440                         mask = m_BCSH_CONTRAST;
4441                         val = v_BCSH_CONTRAST(value);
4442                         break;
4443                 case SAT_CON:
4444                         /*from 0 to 1024,typical is 512
4445                          *vop,9bit, from 0 to 512, typical is 256*/
4446                         value /= 2;
4447                         mask = m_BCSH_SAT_CON;
4448                         val = v_BCSH_SAT_CON(value);
4449                         break;
4450                 default:
4451                         break;
4452                 }
4453                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
4454                 lcdc_cfg_done(lcdc_dev);
4455         }
4456         spin_unlock(&lcdc_dev->reg_lock);
4457         return val;
4458 }
4459
4460 static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4461                                     bcsh_bcs_mode mode)
4462 {
4463         struct lcdc_device *lcdc_dev =
4464             container_of(dev_drv, struct lcdc_device, driver);
4465         u32 val;
4466
4467         spin_lock(&lcdc_dev->reg_lock);
4468         if (lcdc_dev->clk_on) {
4469                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
4470                 switch (mode) {
4471                 case BRIGHTNESS:
4472                         val &= m_BCSH_BRIGHTNESS;
4473                         if (val >= 0x20)
4474                                 val -= 0x20;
4475                         else
4476                                 val += 0x20;
4477                         val <<= 2;
4478                         break;
4479                 case CONTRAST:
4480                         val &= m_BCSH_CONTRAST;
4481                         val >>= 8;
4482                         break;
4483                 case SAT_CON:
4484                         val &= m_BCSH_SAT_CON;
4485                         val >>= 20;
4486                         val <<= 1;
4487                         break;
4488                 default:
4489                         break;
4490                 }
4491         }
4492         spin_unlock(&lcdc_dev->reg_lock);
4493         return val;
4494 }
4495
4496 static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
4497 {
4498         struct lcdc_device *lcdc_dev =
4499             container_of(dev_drv, struct lcdc_device, driver);
4500         u32 mask, val;
4501
4502         spin_lock(&lcdc_dev->reg_lock);
4503         if (lcdc_dev->clk_on) {
4504                 if (open) {
4505                         lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1);
4506                         lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
4507                         lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
4508                         dev_drv->bcsh.enable = 1;
4509                 } else {
4510                         mask = m_BCSH_EN;
4511                         val = v_BCSH_EN(0);
4512                         lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
4513                         dev_drv->bcsh.enable = 0;
4514                 }
4515                 rk3368_lcdc_bcsh_path_sel(dev_drv);
4516                 lcdc_cfg_done(lcdc_dev);
4517         }
4518         spin_unlock(&lcdc_dev->reg_lock);
4519         return 0;
4520 }
4521
4522 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4523 {
4524         if (!enable || !dev_drv->bcsh.enable) {
4525                 rk3368_lcdc_open_bcsh(dev_drv, false);
4526                 return 0;
4527         }
4528
4529         if (dev_drv->bcsh.brightness <= 255 ||
4530             dev_drv->bcsh.contrast <= 510 ||
4531             dev_drv->bcsh.sat_con <= 1015 ||
4532             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4533                 rk3368_lcdc_open_bcsh(dev_drv, true);
4534                 if (dev_drv->bcsh.brightness <= 255)
4535                         rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4536                                                  dev_drv->bcsh.brightness);
4537                 if (dev_drv->bcsh.contrast <= 510)
4538                         rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
4539                                                  dev_drv->bcsh.contrast);
4540                 if (dev_drv->bcsh.sat_con <= 1015)
4541                         rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
4542                                                  dev_drv->bcsh.sat_con);
4543                 if (dev_drv->bcsh.sin_hue <= 511 &&
4544                     dev_drv->bcsh.cos_hue <= 511)
4545                         rk3368_lcdc_set_bcsh_hue(dev_drv,
4546                                                  dev_drv->bcsh.sin_hue,
4547                                                  dev_drv->bcsh.cos_hue);
4548         }
4549         return 0;
4550 }
4551
4552 static int __maybe_unused
4553 rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4554 {
4555         struct lcdc_device *lcdc_dev =
4556             container_of(dev_drv, struct lcdc_device, driver);
4557
4558         if (enable) {
4559                 spin_lock(&lcdc_dev->reg_lock);
4560                 if (likely(lcdc_dev->clk_on)) {
4561                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4562                                      v_DSP_BLACK_EN(1));
4563                         lcdc_cfg_done(lcdc_dev);
4564                 }
4565                 spin_unlock(&lcdc_dev->reg_lock);
4566         } else {
4567                 spin_lock(&lcdc_dev->reg_lock);
4568                 if (likely(lcdc_dev->clk_on)) {
4569                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4570                                      v_DSP_BLACK_EN(0));
4571
4572                         lcdc_cfg_done(lcdc_dev);
4573                 }
4574                 spin_unlock(&lcdc_dev->reg_lock);
4575         }
4576
4577         return 0;
4578 }
4579
4580
4581 static int rk3368_lcdc_wait_frame_start(struct rk_lcdc_driver *dev_drv,
4582                                         int enable)
4583 {
4584         u32 line_scane_num, vsync_end, vact_end;
4585         u32 interlace_mode;
4586
4587         struct lcdc_device *lcdc_dev =
4588             container_of(dev_drv, struct lcdc_device, driver);
4589
4590         if (unlikely(!lcdc_dev->clk_on)) {
4591                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
4592                 return 0;
4593         }
4594         if (0 == enable) {
4595                 interlace_mode = lcdc_read_bit(lcdc_dev, DSP_CTRL0,
4596                                                m_DSP_INTERLACE);
4597                 if (interlace_mode) {
4598                         vsync_end = lcdc_readl(lcdc_dev, DSP_VS_ST_END_F1) &
4599                                         m_DSP_VS_END_F1;
4600                         vact_end = lcdc_readl(lcdc_dev, DSP_VACT_ST_END_F1) &
4601                                         m_DSP_VACT_END_F1;
4602                 } else {
4603                         vsync_end = lcdc_readl(lcdc_dev, DSP_VTOTAL_VS_END) &
4604                                         m_DSP_VS_PW;
4605                         vact_end = lcdc_readl(lcdc_dev, DSP_VACT_ST_END) &
4606                                         m_DSP_VACT_END;
4607                 }
4608                 while (1) {
4609                         line_scane_num = lcdc_readl(lcdc_dev, SCAN_LINE_NUM) &
4610                                         0x1fff;
4611                         if ((line_scane_num > vsync_end) &&
4612                             (line_scane_num <= vact_end - 100))
4613                                 break;
4614                 }
4615                 return 0;
4616         } else if (1 == enable) {
4617                 line_scane_num = lcdc_readl(lcdc_dev, SCAN_LINE_NUM) & 0x1fff;
4618                 return line_scane_num;
4619         }
4620
4621         return 0;
4622 }
4623
4624 static int rk3368_lcdc_backlight_close(struct rk_lcdc_driver *dev_drv,
4625                                        int enable)
4626 {
4627         struct lcdc_device *lcdc_dev =
4628             container_of(dev_drv, struct lcdc_device, driver);
4629
4630         if (unlikely(!lcdc_dev->clk_on)) {
4631                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
4632                 return 0;
4633         }
4634         rk3368_lcdc_get_backlight_device(dev_drv);
4635
4636         if (enable) {
4637                 /* close the backlight */
4638                 if (lcdc_dev->backlight) {
4639                         lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4640                         backlight_update_status(lcdc_dev->backlight);
4641                 }
4642                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4643                         dev_drv->trsm_ops->disable();
4644         } else {
4645                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4646                         dev_drv->trsm_ops->enable();
4647                 msleep(100);
4648                 /* open the backlight */
4649                 if (lcdc_dev->backlight) {
4650                         lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
4651                         backlight_update_status(lcdc_dev->backlight);
4652                 }
4653         }
4654
4655         return 0;
4656 }
4657
4658 static int rk3368_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv,
4659                                     struct overscan *overscan)
4660 {
4661         struct lcdc_device *lcdc_dev =
4662             container_of(dev_drv, struct lcdc_device, driver);
4663
4664         if (unlikely(!lcdc_dev->clk_on)) {
4665                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
4666                 return 0;
4667         }
4668         /*rk3368_lcdc_post_cfg(dev_drv);*/
4669
4670         return 0;
4671 }
4672
4673 static int rk3368_lcdc_extern_func(struct rk_lcdc_driver *dev_drv,
4674                                    int cmd)
4675 {
4676         struct lcdc_device *lcdc_dev =
4677             container_of(dev_drv, struct lcdc_device, driver);
4678         u32 val;
4679
4680         if (unlikely(!lcdc_dev->clk_on)) {
4681                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
4682                 return 0;
4683         }
4684
4685         switch (cmd) {
4686         case GET_PAGE_FAULT:
4687                 val = lcdc_readl(lcdc_dev, MMU_INT_RAWSTAT);
4688                 if ((val & 0x1) == 1) {
4689                         if ((val & 0x2) == 1)
4690                                 pr_info("val=0x%x,vop iommu bus error\n", val);
4691                         else
4692                                 return 1;
4693                 }
4694                 break;
4695         case CLR_PAGE_FAULT:
4696                 lcdc_writel(lcdc_dev, MMU_INT_CLEAR, 0x3);
4697                 break;
4698         case UNMASK_PAGE_FAULT:
4699                 lcdc_writel(lcdc_dev, MMU_INT_MASK, 0x2);
4700                 break;
4701         default:
4702                 break;
4703         }
4704
4705         return 0;
4706 }
4707
4708 static int rk3368_lcdc_set_wb(struct rk_lcdc_driver *dev_drv)
4709 {
4710         struct lcdc_device *lcdc_dev =
4711             container_of(dev_drv, struct lcdc_device, driver);
4712         struct rk_fb_reg_wb_data *wb_data;
4713         u32 src_w, src_h, dst_w, dst_h, fmt_cfg;
4714         u32 xscale_en = 0, x_scale_fac = 0, y_throw = 0;
4715         u32 csc_mode = 0, rgb2yuv = 0, dither_en = 0;
4716
4717         if (unlikely(!lcdc_dev->clk_on)) {
4718                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
4719                 return 0;
4720         }
4721         wb_data = &dev_drv->wb_data;
4722         if ((wb_data->xsize == 0) || (wb_data->ysize == 0))
4723                 return 0;
4724
4725         src_w = dev_drv->cur_screen->mode.xres;
4726         src_h = dev_drv->cur_screen->mode.yres;
4727         dst_w = wb_data->xsize;
4728         dst_h = wb_data->ysize;
4729         if (!IS_ALIGNED(dst_w, RK3366_WB_ALIGN))
4730                 pr_info("dst_w: %d not align 16 pixel\n", dst_w);
4731
4732         if (src_w > dst_w)
4733                 xscale_en = 1;
4734         else if (src_w < dst_w)
4735                 dst_w = src_w;
4736         else
4737                 xscale_en = 0;
4738         if (wb_data->state && xscale_en)
4739                 x_scale_fac = GET_SCALE_FACTOR_BILI_DN(src_w, dst_w);
4740         if ((src_h >= 2 * dst_h) && (dst_h != 0))
4741                 y_throw = 1;
4742         else
4743                 y_throw = 0;
4744         switch (wb_data->data_format) {
4745         case XRGB888:
4746         case XBGR888:
4747                 fmt_cfg = 0;
4748                 break;
4749         case RGB888:
4750         case BGR888:
4751                 fmt_cfg = 1;
4752                 break;
4753         case RGB565:
4754         case BGR565:
4755                 fmt_cfg = 2;
4756                 dither_en = 1;
4757                 break;
4758         case YUV420:
4759                 fmt_cfg = 4;
4760                 if (dev_drv->overlay_mode == VOP_RGB_DOMAIN)
4761                         rgb2yuv = 1;
4762                 if ((src_w < 1280) && (src_h < 720))
4763                         csc_mode = VOP_R2Y_CSC_BT601;
4764                 else
4765                         csc_mode = VOP_R2Y_CSC_BT709;
4766                 break;
4767         default:
4768                 fmt_cfg = 0;
4769                 pr_info("unsupport fmt: %d\n", wb_data->data_format);
4770                 break;
4771         }
4772         spin_lock(&lcdc_dev->reg_lock);
4773         lcdc_msk_reg(lcdc_dev, WB_CTRL0,
4774                      m_WB_EN | m_WB_FMT | m_WB_XPSD_BIL_EN |
4775                      m_WB_YTHROW_EN | m_WB_RGB2YUV_EN | m_WB_RGB2YUV_MODE |
4776                      m_WB_DITHER_EN,
4777                      v_WB_EN(wb_data->state) | v_WB_FMT(fmt_cfg) |
4778                      v_WB_XPSD_BIL_EN(xscale_en) |
4779                      v_WB_YTHROW_EN(y_throw) | v_WB_RGB2YUV_EN(rgb2yuv) |
4780                      v_WB_RGB2YUV_MODE(csc_mode) | v_WB_DITHER_EN(dither_en));
4781         lcdc_msk_reg(lcdc_dev, WB_CTRL1,
4782                      m_WB_WIDTH | m_WB_XPSD_BIL_FACTOR,
4783                      v_WB_WIDTH(dst_w) |
4784                      v_WB_XPSD_BIL_FACTOR(x_scale_fac));
4785         lcdc_writel(lcdc_dev, WB_YRGB_MST, wb_data->smem_start);
4786         lcdc_writel(lcdc_dev, WB_CBR_MST, wb_data->cbr_start);
4787         spin_unlock(&lcdc_dev->reg_lock);
4788
4789         return 0;
4790 }
4791
4792 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4793         .open = rk3368_lcdc_open,
4794         .win_direct_en = rk3368_lcdc_win_direct_en,
4795         .load_screen = rk3368_load_screen,
4796         .get_dspbuf_info = rk3368_get_dspbuf_info,
4797         .post_dspbuf = rk3368_post_dspbuf,
4798         .set_par = rk3368_lcdc_set_par,
4799         .pan_display = rk3368_lcdc_pan_display,
4800         .direct_set_addr = rk3368_lcdc_direct_set_win_addr,
4801         /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/
4802         .blank = rk3368_lcdc_blank,
4803         .ioctl = rk3368_lcdc_ioctl,
4804         .suspend = rk3368_lcdc_early_suspend,
4805         .resume = rk3368_lcdc_early_resume,
4806         .get_win_state = rk3368_lcdc_get_win_state,
4807         .area_support_num = rk3368_lcdc_get_area_num,
4808         .ovl_mgr = rk3368_lcdc_ovl_mgr,
4809         .get_disp_info = rk3368_lcdc_get_disp_info,
4810         .fps_mgr = rk3368_lcdc_fps_mgr,
4811         .fb_get_win_id = rk3368_lcdc_get_win_id,
4812         .fb_win_remap = rk3368_fb_win_remap,
4813         .set_dsp_lut = rk3368_lcdc_set_lut,
4814         .set_cabc_lut = rk3368_set_cabc_lut,
4815         .poll_vblank = rk3368_lcdc_poll_vblank,
4816         .get_dsp_addr = rk3368_lcdc_get_dsp_addr,
4817         .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc,
4818         .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue,
4819         .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs,
4820         .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue,
4821         .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs,
4822         .open_bcsh = rk3368_lcdc_open_bcsh,
4823         .dump_reg = rk3368_lcdc_reg_dump,
4824         .cfg_done = rk3368_lcdc_config_done,
4825         .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu,
4826         /*.dsp_black = rk3368_lcdc_dsp_black,*/
4827         .backlight_close = rk3368_lcdc_backlight_close,
4828         .mmu_en    = rk3368_lcdc_mmu_en,
4829         .set_overscan   = rk3368_lcdc_set_overscan,
4830         .extern_func    = rk3368_lcdc_extern_func,
4831         .wait_frame_start = rk3368_lcdc_wait_frame_start,
4832         .set_wb = rk3368_lcdc_set_wb,
4833 };
4834
4835 #ifdef LCDC_IRQ_EMPTY_DEBUG
4836 static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev,
4837                                  unsigned int intr_status)
4838 {
4839         u32 intr_clr_reg;
4840
4841         if (lcdc_dev->soc_type == VOP_FULL_RK3366)
4842                 intr_clr_reg = INTR_CLEAR_RK3366;
4843         else
4844                 intr_clr_reg = INTR_CLEAR_RK3368;
4845
4846         if (intr_status & m_WIN0_EMPTY_INTR_STS) {
4847                 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_WIN0_EMPTY_INTR_CLR,
4848                              v_WIN0_EMPTY_INTR_CLR(1));
4849                 dev_warn(lcdc_dev->dev, "win0 empty irq!");
4850         } else if (intr_status & m_WIN1_EMPTY_INTR_STS) {
4851                 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_WIN1_EMPTY_INTR_CLR,
4852                              v_WIN1_EMPTY_INTR_CLR(1));
4853                 dev_warn(lcdc_dev->dev, "win1 empty irq!");
4854         } else if (intr_status & m_WIN2_EMPTY_INTR_STS) {
4855                 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_WIN2_EMPTY_INTR_CLR,
4856                              v_WIN2_EMPTY_INTR_CLR(1));
4857                 dev_warn(lcdc_dev->dev, "win2 empty irq!");
4858         } else if (intr_status & m_WIN3_EMPTY_INTR_STS) {
4859                 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_WIN3_EMPTY_INTR_CLR,
4860                              v_WIN3_EMPTY_INTR_CLR(1));
4861                 dev_warn(lcdc_dev->dev, "win3 empty irq!");
4862         } else if (intr_status & m_HWC_EMPTY_INTR_STS) {
4863                 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_HWC_EMPTY_INTR_CLR,
4864                              v_HWC_EMPTY_INTR_CLR(1));
4865                 dev_warn(lcdc_dev->dev, "HWC empty irq!");
4866         } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) {
4867                 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_POST_BUF_EMPTY_INTR_CLR,
4868                              v_POST_BUF_EMPTY_INTR_CLR(1));
4869                 dev_warn(lcdc_dev->dev, "post buf empty irq!");
4870         } else if (intr_status & m_PWM_GEN_INTR_STS) {
4871                 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_PWM_GEN_INTR_CLR,
4872                              v_PWM_GEN_INTR_CLR(1));
4873                 dev_warn(lcdc_dev->dev, "PWM gen irq!");
4874         }
4875         return 0;
4876 }
4877 #endif
4878
4879 static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id)
4880 {
4881         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
4882         ktime_t timestamp = ktime_get();
4883         u32 intr_status;
4884         u32 line_scane_num, dsp_vs_st_f1;
4885         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
4886         u32 intr_en_reg, intr_clr_reg, intr_status_reg;
4887
4888         if (lcdc_dev->soc_type == VOP_FULL_RK3366) {
4889                 intr_status_reg = INTR_STATUS_RK3366;
4890                 intr_clr_reg = INTR_CLEAR_RK3366;
4891                 intr_en_reg = INTR_EN_RK3366;
4892         } else {
4893                 intr_status_reg = INTR_STATUS_RK3368;
4894                 intr_clr_reg = INTR_CLEAR_RK3368;
4895                 intr_en_reg = INTR_EN_RK3368;
4896         }
4897
4898         intr_status = lcdc_readl(lcdc_dev, intr_status_reg);
4899         if (intr_status & m_FS_INTR_STS) {
4900                 timestamp = ktime_get();
4901                 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_FS_INTR_CLR,
4902                              v_FS_INTR_CLR(1));
4903                 line_scane_num = lcdc_readl(lcdc_dev, SCAN_LINE_NUM) & 0x1fff;
4904                 dsp_vs_st_f1 = lcdc_readl(lcdc_dev, DSP_VS_ST_END_F1) >> 16;
4905                 /*if(lcdc_dev->driver.wait_fs){ */
4906                 if (0) {
4907                         spin_lock(&(lcdc_dev->driver.cpl_lock));
4908                         complete(&(lcdc_dev->driver.frame_done));
4909                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
4910                 }
4911                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4912                 if ((lcdc_dev->soc_type == VOP_FULL_RK3366) &&
4913                     (lcdc_dev->driver.wb_data.state)) {
4914                         if (lcdc_read_bit(lcdc_dev, WB_CTRL0, m_WB_EN)) {
4915                                 lcdc_msk_reg(lcdc_dev, WB_CTRL0,
4916                                              m_WB_EN, v_WB_EN(0));
4917                                 lcdc_cfg_done(lcdc_dev);
4918                                 lcdc_dev->driver.wb_data.state = 0;
4919                         }
4920                 }
4921                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
4922                 if (!(screen->mode.vmode & FB_VMODE_INTERLACED) ||
4923                     (line_scane_num >= dsp_vs_st_f1)) {
4924                         lcdc_dev->driver.vsync_info.timestamp = timestamp;
4925                         wake_up_interruptible_all(
4926                                 &lcdc_dev->driver.vsync_info.wait);
4927                 }
4928         } else if (intr_status & m_LINE_FLAG0_INTR_STS) {
4929                 lcdc_dev->driver.frame_time.last_framedone_t =
4930                         lcdc_dev->driver.frame_time.framedone_t;
4931                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4932                 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_LINE_FLAG0_INTR_CLR,
4933                              v_LINE_FLAG0_INTR_CLR(1));
4934         } else if (intr_status & m_LINE_FLAG1_INTR_STS) {
4935                 /*line flag1 */
4936                 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_LINE_FLAG1_INTR_CLR,
4937                              v_LINE_FLAG1_INTR_CLR(1));
4938         } else if (intr_status & m_FS_NEW_INTR_STS) {
4939                 /*new frame start */
4940                 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_FS_NEW_INTR_CLR,
4941                              v_FS_NEW_INTR_CLR(1));
4942         } else if (intr_status & m_BUS_ERROR_INTR_STS) {
4943                 lcdc_msk_reg(lcdc_dev, intr_clr_reg, m_BUS_ERROR_INTR_CLR,
4944                              v_BUS_ERROR_INTR_CLR(1));
4945                 dev_warn(lcdc_dev->dev, "bus error!");
4946         }
4947
4948         /* for win empty debug */
4949 #ifdef LCDC_IRQ_EMPTY_DEBUG
4950         rk3368_lcdc_parse_irq(lcdc_dev, intr_status);
4951 #endif
4952         return IRQ_HANDLED;
4953 }
4954
4955 #if defined(CONFIG_PM)
4956 static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
4957 {
4958         return 0;
4959 }
4960
4961 static int rk3368_lcdc_resume(struct platform_device *pdev)
4962 {
4963         return 0;
4964 }
4965 #else
4966 #define rk3368_lcdc_suspend NULL
4967 #define rk3368_lcdc_resume  NULL
4968 #endif
4969
4970 static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4971 {
4972         struct device_node *np = lcdc_dev->dev->of_node;
4973         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4974         int val;
4975
4976         if (of_property_read_u32(np, "rockchip,prop", &val))
4977                 lcdc_dev->prop = PRMRY; /*default set it as primary */
4978         else
4979                 lcdc_dev->prop = val;
4980
4981         if (of_property_read_u32(np, "rockchip,mirror", &val))
4982                 dev_drv->rotate_mode = NO_MIRROR;
4983         else
4984                 dev_drv->rotate_mode = val;
4985
4986         if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4987                 dev_drv->cabc_mode = 0; /* default set close cabc */
4988         else
4989                 dev_drv->cabc_mode = val;
4990
4991         if (of_property_read_u32(np, "rockchip,pwr18", &val))
4992                 /*default set it as 3.xv power supply */
4993                 lcdc_dev->pwr18 = false;
4994         else
4995                 lcdc_dev->pwr18 = (val ? true : false);
4996
4997         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4998                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4999         else
5000                 dev_drv->fb_win_map = val;
5001
5002         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
5003                 dev_drv->bcsh.enable = false;
5004         else
5005                 dev_drv->bcsh.enable = (val ? true : false);
5006
5007         if (of_property_read_u32(np, "rockchip,brightness", &val))
5008                 dev_drv->bcsh.brightness = 0xffff;
5009         else
5010                 dev_drv->bcsh.brightness = val;
5011
5012         if (of_property_read_u32(np, "rockchip,contrast", &val))
5013                 dev_drv->bcsh.contrast = 0xffff;
5014         else
5015                 dev_drv->bcsh.contrast = val;
5016
5017         if (of_property_read_u32(np, "rockchip,sat-con", &val))
5018                 dev_drv->bcsh.sat_con = 0xffff;
5019         else
5020                 dev_drv->bcsh.sat_con = val;
5021
5022         if (of_property_read_u32(np, "rockchip,hue", &val)) {
5023                 dev_drv->bcsh.sin_hue = 0xffff;
5024                 dev_drv->bcsh.cos_hue = 0xffff;
5025         } else {
5026                 dev_drv->bcsh.sin_hue = val & 0xff;
5027                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
5028         }
5029
5030         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
5031                 dev_drv->iommu_enabled = 0;
5032         else
5033                 dev_drv->iommu_enabled = val;
5034         return 0;
5035 }
5036
5037 static int rk3368_lcdc_probe(struct platform_device *pdev)
5038 {
5039         struct lcdc_device *lcdc_dev = NULL;
5040         struct rk_lcdc_driver *dev_drv;
5041         struct device *dev = &pdev->dev;
5042         struct resource *res;
5043         struct device_node *np = pdev->dev.of_node;
5044         int prop;
5045         int ret = 0;
5046
5047         /*if the primary lcdc has not registered ,the extend
5048            lcdc register later */
5049         of_property_read_u32(np, "rockchip,prop", &prop);
5050         if (prop == EXTEND) {
5051                 if (!is_prmry_rk_lcdc_registered())
5052                         return -EPROBE_DEFER;
5053         }
5054         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
5055         if (!lcdc_dev) {
5056                 dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!");
5057                 return -ENOMEM;
5058         }
5059         platform_set_drvdata(pdev, lcdc_dev);
5060         lcdc_dev->dev = dev;
5061         rk3368_lcdc_parse_dt(lcdc_dev);
5062 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
5063         /* enable power domain */
5064         pm_runtime_enable(dev);
5065 #endif
5066         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5067         lcdc_dev->reg_phy_base = res->start;
5068         lcdc_dev->len = resource_size(res);
5069
5070         lcdc_dev->regs = devm_ioremap(&pdev->dev, res->start,
5071                                       resource_size(res));
5072         if (IS_ERR(lcdc_dev->regs))
5073                 return PTR_ERR(lcdc_dev->regs);
5074         else
5075                 dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs);
5076
5077         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
5078         if (IS_ERR(lcdc_dev->regsbak))
5079                 return PTR_ERR(lcdc_dev->regsbak);
5080         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
5081         lcdc_dev->cabc_lut_addr_base = (lcdc_dev->regs + CABC_GAMMA_LUT_ADDR);
5082         lcdc_dev->grf_base =
5083                 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
5084         if (IS_ERR(lcdc_dev->grf_base)) {
5085                 dev_err(&pdev->dev, "can't find lcdc grf property\n");
5086                 lcdc_dev->grf_base = NULL;
5087         }
5088         lcdc_dev->pmugrf_base =
5089                 syscon_regmap_lookup_by_phandle(np, "rockchip,pmugrf");
5090         if (IS_ERR(lcdc_dev->pmugrf_base)) {
5091                 dev_err(&pdev->dev, "can't find lcdc pmu grf property\n");
5092                 lcdc_dev->pmugrf_base = NULL;
5093         }
5094
5095         lcdc_dev->cru_base =
5096                 syscon_regmap_lookup_by_phandle(np, "rockchip,cru");
5097         if (IS_ERR(lcdc_dev->cru_base)) {
5098                 dev_err(&pdev->dev, "can't find lcdc cru_base property\n");
5099                 lcdc_dev->cru_base = NULL;
5100         }
5101
5102         lcdc_dev->id = 0;
5103         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
5104         dev_drv = &lcdc_dev->driver;
5105         dev_drv->dev = dev;
5106         dev_drv->prop = prop;
5107         dev_drv->id = lcdc_dev->id;
5108         dev_drv->ops = &lcdc_drv_ops;
5109         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
5110         dev_drv->reserved_fb = 1;/*only need reserved 1 buffer*/
5111         spin_lock_init(&lcdc_dev->reg_lock);
5112
5113         lcdc_dev->irq = platform_get_irq(pdev, 0);
5114         if (lcdc_dev->irq < 0) {
5115                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
5116                         lcdc_dev->id);
5117                 return -ENXIO;
5118         }
5119
5120         ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr,
5121                                IRQF_SHARED,
5122                                dev_name(dev), lcdc_dev);
5123         if (ret) {
5124                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
5125                         lcdc_dev->irq, ret);
5126                 return ret;
5127         }
5128
5129         if (dev_drv->iommu_enabled) {
5130                 if (lcdc_dev->id == 0) {
5131                         strcpy(dev_drv->mmu_dts_name,
5132                                VOPB_IOMMU_COMPATIBLE_NAME);
5133                 } else {
5134                         strcpy(dev_drv->mmu_dts_name,
5135                                VOPL_IOMMU_COMPATIBLE_NAME);
5136                 }
5137         }
5138
5139         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
5140         if (ret < 0) {
5141                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
5142                 return ret;
5143         }
5144         if (lcdc_dev->soc_type == VOP_FULL_RK3366)
5145                 dev_drv->property.feature |= SUPPORT_WRITE_BACK;
5146         else if (lcdc_dev->soc_type == VOP_FULL_RK3368)
5147                 dev_drv->property.feature |= SUPPORT_IFBDC;
5148         dev_drv->property.feature |= SUPPORT_VOP_IDENTIFY |
5149                                 SUPPORT_YUV420_OUTPUT;
5150         dev_drv->property.max_output_x = 4096;
5151         dev_drv->property.max_output_y = 2160;
5152         lcdc_dev->screen = dev_drv->screen0;
5153         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
5154                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
5155
5156         return 0;
5157 }
5158
5159 static int rk3368_lcdc_remove(struct platform_device *pdev)
5160 {
5161         return 0;
5162 }
5163
5164 static void rk3368_lcdc_shutdown(struct platform_device *pdev)
5165 {
5166         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
5167         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
5168 #if 1
5169         dev_drv->suspend_flag = 1;
5170         mdelay(100);
5171         flush_kthread_worker(&dev_drv->update_regs_worker);
5172         kthread_stop(dev_drv->update_regs_thread);
5173         rk3368_lcdc_deint(lcdc_dev);
5174         /*if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
5175                 dev_drv->trsm_ops->disable();*/
5176
5177         rk3368_lcdc_clk_disable(lcdc_dev);
5178 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
5179         pm_runtime_disable(lcdc_dev->dev);
5180 #endif
5181         rk_disp_pwr_disable(dev_drv);
5182 #else
5183         rk3368_lcdc_early_suspend(&lcdc_dev->driver);
5184         rk3368_lcdc_deint(lcdc_dev);
5185 #endif
5186 }
5187
5188 #if defined(CONFIG_OF)
5189 static const struct of_device_id rk3368_lcdc_dt_ids[] = {
5190         {.compatible = "rockchip,rk3368-lcdc",},
5191         {.compatible = "rockchip,rk3366-lcdc-big",},
5192         {}
5193 };
5194 #endif
5195
5196 static struct platform_driver rk3368_lcdc_driver = {
5197         .probe = rk3368_lcdc_probe,
5198         .remove = rk3368_lcdc_remove,
5199         .driver = {
5200                    .name = "rk3368-lcdc",
5201                    .owner = THIS_MODULE,
5202                    .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids),
5203                    },
5204         .suspend = rk3368_lcdc_suspend,
5205         .resume = rk3368_lcdc_resume,
5206         .shutdown = rk3368_lcdc_shutdown,
5207 };
5208
5209 static int __init rk3368_lcdc_module_init(void)
5210 {
5211         return platform_driver_register(&rk3368_lcdc_driver);
5212 }
5213
5214 static void __exit rk3368_lcdc_module_exit(void)
5215 {
5216         platform_driver_unregister(&rk3368_lcdc_driver);
5217 }
5218
5219 fs_initcall(rk3368_lcdc_module_init);
5220 module_exit(rk3368_lcdc_module_exit);