2 * drivers/video/rockchip/lcdc/rk3368_lcdc.c
4 * Copyright (C) 2014 ROCKCHIP, Inc.
5 *Author:hjc<hjc@rock-chips.com>
6 *This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/string.h>
22 #include <linux/slab.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/rockchip-iovmm.h>
30 #include <asm/div64.h>
31 #include <linux/uaccess.h>
32 #include <linux/rockchip/cpu.h>
33 #include <linux/rockchip/iomap.h>
34 #include <linux/rockchip/grf.h>
35 #include <linux/rockchip/common.h>
36 #include <dt-bindings/clock/rk_system_status.h>
38 #include "rk3368_lcdc.h"
40 #if defined(CONFIG_HAS_EARLYSUSPEND)
41 #include <linux/earlysuspend.h>
43 #define CONFIG_RK_FPGA 1
45 static int dbg_thresd;
46 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
48 #define DBG(level, x...) do { \
49 if (unlikely(dbg_thresd >= level)) \
53 static struct rk_lcdc_win lcdc_win[] = {
81 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
83 /*#define WAIT_FOR_SYNC 1*/
84 u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth)
88 if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
90 else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
98 static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv)
103 struct lcdc_device *lcdc_dev =
104 container_of(dev_drv, struct lcdc_device, driver);
105 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
106 lcdc_cfg_done(lcdc_dev);
108 for (i = 0; i < 256; i++) {
109 v = dev_drv->cur_screen->dsp_lut[i];
110 c = lcdc_dev->dsp_lut_addr_base + (i << 2);
112 g = (v & 0xff00) << 4;
113 r = (v & 0xff0000) << 6;
115 for (j = 0; j < 4; j++) {
116 writel_relaxed(v, c);
117 v += (1 + (1 << 10) + (1 << 20));
121 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
126 static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
128 #ifdef CONFIG_RK_FPGA
129 lcdc_dev->clk_on = 1;
132 if (!lcdc_dev->clk_on) {
133 clk_prepare_enable(lcdc_dev->hclk);
134 clk_prepare_enable(lcdc_dev->dclk);
135 clk_prepare_enable(lcdc_dev->aclk);
136 clk_prepare_enable(lcdc_dev->pd);
137 spin_lock(&lcdc_dev->reg_lock);
138 lcdc_dev->clk_on = 1;
139 spin_unlock(&lcdc_dev->reg_lock);
145 static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
147 #ifdef CONFIG_RK_FPGA
148 lcdc_dev->clk_on = 0;
151 if (lcdc_dev->clk_on) {
152 spin_lock(&lcdc_dev->reg_lock);
153 lcdc_dev->clk_on = 0;
154 spin_unlock(&lcdc_dev->reg_lock);
156 clk_disable_unprepare(lcdc_dev->dclk);
157 clk_disable_unprepare(lcdc_dev->hclk);
158 clk_disable_unprepare(lcdc_dev->aclk);
159 clk_disable_unprepare(lcdc_dev->pd);
165 static int rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
169 spin_lock(&lcdc_dev->reg_lock);
170 if (likely(lcdc_dev->clk_on)) {
171 mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN |
172 m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN |
173 m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN |
174 m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
175 m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
176 m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
177 m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN;
178 val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) |
179 v_ADDR_SAME_INTR_EN(0) |
180 v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) |
181 v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) |
182 v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) |
183 v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) |
184 v_POST_BUF_EMPTY_INTR_EN(0) |
185 v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0);
186 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
188 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR |
189 m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
190 m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR |
191 m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
192 m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
193 m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
194 m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR;
195 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
196 v_ADDR_SAME_INTR_CLR(1) |
197 v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) |
198 v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) |
199 v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) |
200 v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) |
201 v_POST_BUF_EMPTY_INTR_CLR(1) |
202 v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1);
203 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
204 lcdc_cfg_done(lcdc_dev);
205 spin_unlock(&lcdc_dev->reg_lock);
207 spin_unlock(&lcdc_dev->reg_lock);
213 static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
215 struct lcdc_device *lcdc_dev =
216 container_of(dev_drv, struct lcdc_device, driver);
217 int *cbase = (int *)lcdc_dev->regs;
218 int *regsbak = (int *)lcdc_dev->regsbak;
220 char dbg_message[30];
223 pr_info("lcd back up reg:\n");
224 memset(dbg_message, 0, sizeof(dbg_message));
225 memset(buf, 0, sizeof(buf));
226 for (i = 0; i <= (0x200 >> 4); i++) {
227 val = sprintf(dbg_message, "0x%04x: ", i * 16);
228 for (j = 0; j < 4; j++) {
229 val = sprintf(buf, "%08x ", *(regsbak + i * 4 + j));
230 strcat(dbg_message, buf);
232 pr_info("%s\n", dbg_message);
233 memset(dbg_message, 0, sizeof(dbg_message));
234 memset(buf, 0, sizeof(buf));
237 pr_info("lcdc reg:\n");
238 for (i = 0; i <= (0x200 >> 4); i++) {
239 val = sprintf(dbg_message, "0x%04x: ", i * 16);
240 for (j = 0; j < 4; j++) {
241 sprintf(buf, "%08x ",
242 readl_relaxed(cbase + i * 4 + j));
243 strcat(dbg_message, buf);
245 pr_info("%s\n", dbg_message);
246 memset(dbg_message, 0, sizeof(dbg_message));
247 memset(buf, 0, sizeof(buf));
254 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en) \
257 spin_lock(&lcdc_dev->reg_lock); \
258 msk = m_WIN##id##_EN; \
259 val = v_WIN##id##_EN(en); \
260 lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val); \
261 lcdc_cfg_done(lcdc_dev); \
262 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk); \
263 while (val != (!!en)) { \
264 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk); \
266 spin_unlock(&lcdc_dev->reg_lock); \
274 /*enable/disable win directly*/
275 static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv,
278 struct lcdc_device *lcdc_dev =
279 container_of(drv, struct lcdc_device, driver);
281 win0_enable(lcdc_dev, en);
282 else if (win_id == 1)
283 win1_enable(lcdc_dev, en);
284 else if (win_id == 2)
285 win2_enable(lcdc_dev, en);
286 else if (win_id == 3)
287 win3_enable(lcdc_dev, en);
289 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
293 #define SET_WIN_ADDR(id) \
294 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
297 spin_lock(&lcdc_dev->reg_lock); \
298 lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr); \
299 msk = m_WIN##id##_EN; \
300 val = v_WIN0_EN(1); \
301 lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val); \
302 lcdc_cfg_done(lcdc_dev); \
303 spin_unlock(&lcdc_dev->reg_lock); \
309 int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
310 int win_id, u32 addr)
312 struct lcdc_device *lcdc_dev =
313 container_of(dev_drv, struct lcdc_device, driver);
315 set_win0_addr(lcdc_dev, addr);
317 set_win1_addr(lcdc_dev, addr);
322 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
326 struct rk_screen *screen = lcdc_dev->driver.cur_screen;
327 u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
328 u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
330 struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
332 spin_lock(&lcdc_dev->reg_lock);
333 for (reg = 0; reg < FRC_LOWER11_1; reg += 4) {
334 val = lcdc_readl(lcdc_dev, reg);
337 win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1;
339 ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
342 win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1;
343 win0->area[0].ysize =
344 ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
347 st_x = val & m_WIN0_DSP_XST;
348 st_y = (val & m_WIN0_DSP_YST) >> 16;
349 win0->area[0].xpos = st_x - h_pw_bp;
350 win0->area[0].ypos = st_y - v_pw_bp;
353 win0->state = val & m_WIN0_EN;
354 win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1;
355 win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
356 win0->area[0].format = win0->area[0].fmt_cfg;
359 win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE;
360 win0->area[0].uv_vir_stride =
361 (val & m_WIN0_VIR_STRIDE_UV) >> 16;
362 if (win0->area[0].format == ARGB888)
363 win0->area[0].xvir = win0->area[0].y_vir_stride;
364 else if (win0->area[0].format == RGB888)
366 win0->area[0].y_vir_stride * 4 / 3;
367 else if (win0->area[0].format == RGB565)
369 2 * win0->area[0].y_vir_stride;
372 4 * win0->area[0].y_vir_stride;
375 win0->area[0].smem_start = val;
378 win0->area[0].cbr_start = val;
384 spin_unlock(&lcdc_dev->reg_lock);
387 /********do basic init*********/
388 static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
391 struct lcdc_device *lcdc_dev =
392 container_of(dev_drv, struct lcdc_device, driver);
393 if (lcdc_dev->pre_init)
396 lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
397 lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
398 lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
399 lcdc_dev->pll_sclk = devm_clk_get(lcdc_dev->dev, "sclk_pll");
400 lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
402 if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||
403 (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
404 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
408 rk_disp_pwr_enable(dev_drv);
409 rk3368_lcdc_clk_enable(lcdc_dev);
411 /*backup reg config at uboot */
412 lcdc_read_reg_defalut_cfg(lcdc_dev);
413 lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_0, 0x15110903);
414 lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_1, 0x00030911);
415 lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_0, 0x1a150b04);
416 lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_1, 0x00040b15);
417 lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_0, 0x15110903);
418 lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_1, 0x00030911);
420 lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
421 lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
422 lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696);
423 lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969);
424 lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
425 lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
427 mask = m_AUTO_GATING_EN;
428 val = v_AUTO_GATING_EN(0);
429 lcdc_cfg_done(lcdc_dev);
430 /*disable win0 to workaround iommu pagefault */
431 /*if (dev_drv->iommu_enabled) */
432 /* win0_enable(lcdc_dev, 0); */
433 lcdc_dev->pre_init = true;
438 static void rk3368_lcdc_deint(struct lcdc_device *lcdc_dev)
440 rk3368_lcdc_disable_irq(lcdc_dev);
441 spin_lock(&lcdc_dev->reg_lock);
442 if (likely(lcdc_dev->clk_on)) {
443 lcdc_dev->clk_on = 0;
444 lcdc_set_bit(lcdc_dev, SYS_CTRL, m_STANDBY_EN);
445 lcdc_cfg_done(lcdc_dev);
446 spin_unlock(&lcdc_dev->reg_lock);
448 spin_unlock(&lcdc_dev->reg_lock);
453 static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
455 struct lcdc_device *lcdc_dev =
456 container_of(dev_drv, struct lcdc_device, driver);
457 struct rk_screen *screen = dev_drv->cur_screen;
458 u16 x_res = screen->mode.xres;
459 u16 y_res = screen->mode.yres;
461 u16 h_total, v_total;
462 u16 post_hsd_en, post_vsd_en;
463 u16 post_dsp_hact_st, post_dsp_hact_end;
464 u16 post_dsp_vact_st, post_dsp_vact_end;
465 u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
466 u16 post_h_fac, post_v_fac;
468 h_total = screen->mode.hsync_len + screen->mode.left_margin +
469 x_res + screen->mode.right_margin;
470 v_total = screen->mode.vsync_len + screen->mode.upper_margin +
471 y_res + screen->mode.lower_margin;
473 if (screen->post_dsp_stx + screen->post_xsize > x_res) {
474 dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
475 screen->post_dsp_stx, screen->post_xsize, x_res);
476 screen->post_dsp_stx = x_res - screen->post_xsize;
478 if (screen->x_mirror == 0) {
479 post_dsp_hact_st = screen->post_dsp_stx +
480 screen->mode.hsync_len + screen->mode.left_margin;
481 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
483 post_dsp_hact_end = h_total - screen->mode.right_margin -
484 screen->post_dsp_stx;
485 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
487 if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
490 GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
496 if (screen->post_dsp_sty + screen->post_ysize > y_res) {
497 dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
498 screen->post_dsp_sty, screen->post_ysize, y_res);
499 screen->post_dsp_sty = y_res - screen->post_ysize;
502 if (screen->y_mirror == 0) {
503 post_dsp_vact_st = screen->post_dsp_sty +
504 screen->mode.vsync_len + screen->mode.upper_margin;
505 post_dsp_vact_end = post_dsp_vact_st + screen->post_ysize;
507 post_dsp_vact_end = v_total - screen->mode.lower_margin -
508 screen->post_dsp_sty;
509 post_dsp_vact_st = post_dsp_vact_end - screen->post_ysize;
511 if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
513 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
520 if (screen->interlace == 1) {
521 post_dsp_vact_st_f1 = v_total + post_dsp_vact_st;
522 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 + screen->post_ysize;
524 post_dsp_vact_st_f1 = 0;
525 post_dsp_vact_end_f1 = 0;
527 DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
528 screen->post_xsize, screen->post_ysize, screen->xpos);
529 DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
530 screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
531 mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
532 val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
533 v_DSP_HACT_ST_POST(post_dsp_hact_st);
534 lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
536 mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
537 val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
538 v_DSP_VACT_ST_POST(post_dsp_vact_st);
539 lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
541 mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
542 val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
543 v_POST_VS_FACTOR_YRGB(post_v_fac);
544 lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
546 mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
547 val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
548 v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
549 lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
551 mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
552 val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
553 lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
557 static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
559 struct lcdc_device *lcdc_dev =
560 container_of(dev_drv, struct lcdc_device, driver);
561 struct rk_lcdc_win *win;
562 u32 colorkey_r, colorkey_g, colorkey_b;
565 for (i = 0; i < 4; i++) {
566 win = dev_drv->win[i];
567 key_val = win->color_key_val;
568 colorkey_r = (key_val & 0xff) << 2;
569 colorkey_g = ((key_val >> 8) & 0xff) << 12;
570 colorkey_b = ((key_val >> 16) & 0xff) << 22;
571 /*color key dither 565/888->aaa */
572 key_val = colorkey_r | colorkey_g | colorkey_b;
575 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
578 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
581 lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
584 lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
587 pr_info("%s:un support win num:%d\n",
595 static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
597 struct lcdc_device *lcdc_dev =
598 container_of(dev_drv, struct lcdc_device, driver);
599 struct rk_lcdc_win *win = dev_drv->win[win_id];
600 struct alpha_config alpha_config;
602 int ppixel_alpha = 0, global_alpha = 0, i;
603 u32 src_alpha_ctl, dst_alpha_ctl;
605 for (i = 0; i < win->area_num; i++) {
606 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
607 (win->area[i].format == ABGR888)) ? 1 : 0;
609 global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
610 alpha_config.src_global_alpha_val = win->g_alpha_val;
611 win->alpha_mode = AB_SRC_OVER;
612 /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
613 __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,
615 switch (win->alpha_mode) {
619 alpha_config.src_factor_mode = AA_ZERO;
620 alpha_config.dst_factor_mode = AA_ZERO;
623 alpha_config.src_factor_mode = AA_ONE;
624 alpha_config.dst_factor_mode = AA_ZERO;
627 alpha_config.src_factor_mode = AA_ZERO;
628 alpha_config.dst_factor_mode = AA_ONE;
631 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
633 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
635 alpha_config.src_factor_mode = AA_ONE;
636 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
639 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
640 alpha_config.src_factor_mode = AA_SRC_INVERSE;
641 alpha_config.dst_factor_mode = AA_ONE;
644 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
645 alpha_config.src_factor_mode = AA_SRC;
646 alpha_config.dst_factor_mode = AA_ZERO;
649 alpha_config.src_factor_mode = AA_ZERO;
650 alpha_config.dst_factor_mode = AA_SRC;
653 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
654 alpha_config.src_factor_mode = AA_SRC_INVERSE;
655 alpha_config.dst_factor_mode = AA_ZERO;
658 alpha_config.src_factor_mode = AA_ZERO;
659 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
662 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
663 alpha_config.src_factor_mode = AA_SRC;
664 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
667 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
668 alpha_config.src_factor_mode = AA_SRC_INVERSE;
669 alpha_config.dst_factor_mode = AA_SRC;
672 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
673 alpha_config.src_factor_mode = AA_SRC_INVERSE;
674 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
676 case AB_SRC_OVER_GLOBAL:
677 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
678 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
679 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
680 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
683 pr_err("alpha mode error\n");
686 if ((ppixel_alpha == 1) && (global_alpha == 1))
687 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
688 else if (ppixel_alpha == 1)
689 alpha_config.src_global_alpha_mode = AA_PER_PIX;
690 else if (global_alpha == 1)
691 alpha_config.src_global_alpha_mode = AA_GLOBAL;
693 dev_warn(lcdc_dev->dev, "alpha_en should be 0\n");
694 alpha_config.src_alpha_mode = AA_STRAIGHT;
695 alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
699 src_alpha_ctl = 0x60;
700 dst_alpha_ctl = 0x64;
703 src_alpha_ctl = 0xa0;
704 dst_alpha_ctl = 0xa4;
707 src_alpha_ctl = 0xdc;
708 dst_alpha_ctl = 0xec;
711 src_alpha_ctl = 0x12c;
712 dst_alpha_ctl = 0x13c;
715 src_alpha_ctl = 0x160;
716 dst_alpha_ctl = 0x164;
719 mask = m_WIN0_DST_FACTOR_M0;
720 val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
721 lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
722 mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
723 m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
724 m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 |
725 m_WIN0_SRC_GLOBAL_ALPHA;
726 val = v_WIN0_SRC_ALPHA_EN(1) |
727 v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
728 v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
729 v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
730 v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
731 v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
732 v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
733 lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
738 static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num)
740 struct rk_lcdc_win_area area_temp;
743 for (i = 0; i < area_num; i++) {
744 for (j = i + 1; j < area_num; j++) {
745 if (win->area[i].dsp_stx > win->area[j].dsp_stx) {
746 memcpy(&area_temp, &win->area[i],
747 sizeof(struct rk_lcdc_win_area));
748 memcpy(&win->area[i], &win->area[j],
749 sizeof(struct rk_lcdc_win_area));
750 memcpy(&win->area[j], &area_temp,
751 sizeof(struct rk_lcdc_win_area));
759 static int rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num)
761 struct rk_lcdc_win_area area_temp;
765 area_temp = win->area[0];
766 win->area[0] = win->area[1];
767 win->area[1] = area_temp;
770 area_temp = win->area[0];
771 win->area[0] = win->area[2];
772 win->area[2] = area_temp;
775 area_temp = win->area[0];
776 win->area[0] = win->area[3];
777 win->area[3] = area_temp;
779 area_temp = win->area[1];
780 win->area[1] = win->area[2];
781 win->area[2] = area_temp;
784 pr_info("un supported area num!\n");
790 static int rk3368_win_area_check_var(int win_id, int area_num,
791 struct rk_lcdc_win_area *area_pre,
792 struct rk_lcdc_win_area *area_now)
794 if ((area_pre->xpos > area_now->xpos) ||
795 ((area_pre->xpos + area_pre->xsize > area_now->xpos) &&
796 (area_pre->ypos + area_pre->ysize > area_now->ypos))) {
799 "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n"
800 "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n",
802 area_num - 1, area_pre->xpos, area_pre->xsize,
803 area_pre->ypos, area_pre->ysize,
804 area_num, area_now->xpos, area_now->xsize,
805 area_now->ypos, area_now->ysize);
811 static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv)
813 struct lcdc_device *lcdc_dev =
814 container_of(dev_drv, struct lcdc_device, driver);
817 for (i = 0; i < 100; i++) {
818 val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0);
819 val &= m_DBG_IFBDC_IDLE;
828 static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
830 struct lcdc_device *lcdc_dev =
831 container_of(dev_drv, struct lcdc_device, driver);
832 struct rk_lcdc_win *win = dev_drv->win[win_id];
835 mask = m_IFBDC_CTRL_FBDC_EN | m_IFBDC_CTRL_FBDC_COR_EN |
836 m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE |
837 m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO;
838 val = v_IFBDC_CTRL_FBDC_EN(win->area[0].fbdc_en) |
839 v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) |
840 v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) |
841 v_IFBDC_CTRL_FBDC_ROTATION_MODE(win->mirror_en << 1) |
842 v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) |
843 v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio);
844 lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
846 mask = m_IFBDC_TILES_NUM;
847 val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles);
848 lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val);
850 mask = m_IFBDC_BASE_ADDR;
851 val = v_IFBDC_BASE_ADDR(win->area[0].y_addr);
852 lcdc_msk_reg(lcdc_dev, IFBDC_BASE_ADDR, mask, val);
854 mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT;
855 val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) |
856 v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height);
857 lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val);
859 mask = m_IFBDC_CMP_INDEX_INIT;
860 val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init);
861 lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val);
863 mask = m_IFBDC_MB_VIR_WIDTH;
864 val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width);
865 lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val);
870 static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id)
872 struct lcdc_device *lcdc_dev =
873 container_of(dev_drv, struct lcdc_device, driver);
874 struct rk_lcdc_win *win = dev_drv->win[win_id];
875 u8 fbdc_dsp_width_ratio;
876 u16 fbdc_mb_vir_width, fbdc_mb_vir_height;
877 u16 fbdc_mb_width, fbdc_mb_height;
878 u16 fbdc_mb_xst, fbdc_mb_yst, fbdc_num_tiles;
879 u16 fbdc_cmp_index_init;
880 u8 mb_w_size, mb_h_size;
881 struct rk_screen *screen = dev_drv->cur_screen;
883 if (screen->mode.flag == FB_VMODE_INTERLACED) {
884 dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n");
888 switch (win->area[0].fmt_cfg) {
889 case VOP_FORMAT_ARGB888:
890 fbdc_dsp_width_ratio = 0;
893 case VOP_FORMAT_RGB888:
894 fbdc_dsp_width_ratio = 0;
897 case VOP_FORMAT_RGB565:
901 dev_err(lcdc_dev->dev,
902 "in fbdc mode,unsupport fmt:%d!\n",
903 win->area[0].fmt_cfg);
908 /*macro block xvir and yvir */
909 if ((win->area[0].xvir % mb_w_size == 0) &&
910 (win->area[0].yvir % mb_h_size == 0)) {
911 fbdc_mb_vir_width = win->area[0].xvir / mb_w_size;
912 fbdc_mb_vir_height = win->area[0].yvir / mb_h_size;
914 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
915 pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n",
916 win->area[0].xvir, win->area[0].yvir,
917 mb_w_size, mb_h_size);
919 /*macro block xact and yact */
920 if ((win->area[0].xact % mb_w_size == 0) &&
921 (win->area[0].yact % mb_h_size == 0)) {
922 fbdc_mb_width = win->area[0].xact / mb_w_size;
923 fbdc_mb_height = win->area[0].yact / mb_h_size;
925 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
926 pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n",
927 win->area[0].xact, win->area[0].yact,
928 mb_w_size, mb_h_size);
930 /*macro block xoff and yoff */
931 if ((win->area[0].xoff % mb_w_size == 0) &&
932 (win->area[0].yoff % mb_h_size == 0)) {
933 fbdc_mb_xst = win->area[0].xoff / mb_w_size;
934 fbdc_mb_yst = win->area[0].yoff / mb_h_size;
936 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
937 pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n",
938 win->area[0].xoff, win->area[0].yoff,
939 mb_w_size, mb_h_size);
943 fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height;
946 switch (fbdc_rotation_mode) {
948 fbdc_cmp_index_init =
949 (fbdc_mb_yst*fbdc_mb_vir_width) + fbdc_mb_xst;
952 fbdc_cmp_index_init =
953 (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+
957 fbdc_cmp_index_init =
958 ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
962 fbdc_cmp_index_init =
963 ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
964 (fbdc_mb_xst+(fbdc_mb_width-1));
968 if ((win->mirror_en) && ((win_id == 2) || (win_id == 3))) {
969 fbdc_cmp_index_init =
970 ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) +
971 (fbdc_mb_xst + (fbdc_mb_width - 1));
973 fbdc_cmp_index_init =
974 (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst;
976 /*fbdc fmt maybe need to change*/
977 win->area[0].fbdc_fmt_cfg = win->area[0].fbdc_data_format;
978 win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio;
979 win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width;
980 win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height;
981 win->area[0].fbdc_mb_width = fbdc_mb_width;
982 win->area[0].fbdc_mb_height = fbdc_mb_height;
983 win->area[0].fbdc_mb_xst = fbdc_mb_xst;
984 win->area[0].fbdc_mb_yst = fbdc_mb_yst;
985 win->area[0].fbdc_num_tiles = fbdc_num_tiles;
986 win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init;
991 static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev,
992 struct rk_lcdc_win *win)
994 struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
995 struct rk_screen *screen = dev_drv->cur_screen;
997 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
998 switch (win->area[0].fmt_cfg) {
999 case VOP_FORMAT_ARGB888:
1000 case VOP_FORMAT_RGB888:
1001 case VOP_FORMAT_RGB565:
1002 if ((screen->mode.xres < 1280) &&
1003 (screen->mode.yres < 720)) {
1004 win->csc_mode = VOP_R2Y_CSC_BT601;
1006 win->csc_mode = VOP_R2Y_CSC_BT709;
1012 } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
1013 switch (win->area[0].fmt_cfg) {
1014 case VOP_FORMAT_YCBCR420:
1015 if ((win->id == 0) || (win->id == 1))
1016 win->csc_mode = VOP_Y2R_CSC_MPEG;
1024 static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1026 struct lcdc_device *lcdc_dev =
1027 container_of(dev_drv, struct lcdc_device, driver);
1028 struct rk_lcdc_win *win = dev_drv->win[win_id];
1029 unsigned int mask, val, off;
1031 off = win_id * 0x40;
1032 /*if(win->win_lb_mode == 5)
1033 win->win_lb_mode = 4;
1034 for rk3288 to fix hw bug? */
1036 if (win->state == 1) {
1037 rk3368_lcdc_csc_mode(lcdc_dev, win);
1038 if (win->area[0].fbdc_en)
1039 rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1040 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
1041 m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR |
1042 m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE;
1043 val = v_WIN0_EN(win->state) |
1044 v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1045 v_WIN0_FMT_10(win->fmt_10) |
1046 v_WIN0_LB_MODE(win->win_lb_mode) |
1047 v_WIN0_RB_SWAP(win->area[0].swap_rb) |
1048 v_WIN0_X_MIRROR(win->mirror_en) |
1049 v_WIN0_Y_MIRROR(win->mirror_en) |
1050 v_WIN0_CSC_MODE(win->csc_mode);
1051 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1053 mask = m_WIN0_BIC_COE_SEL |
1054 m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
1055 m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
1056 m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
1057 m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
1058 m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
1059 m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
1060 m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
1061 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1062 v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1063 v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1064 v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1065 v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1066 v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1067 v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1068 v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1069 v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1070 v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1071 v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1072 v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1073 v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1074 v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1075 v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1076 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val);
1077 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1078 v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1079 lcdc_writel(lcdc_dev, WIN0_VIR + off, val);
1080 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off,
1081 win->area[0].y_addr);
1082 lcdc_writel(lcdc_dev, WIN0_CBR_MST+off,
1083 win->area[0].uv_addr); */
1084 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
1085 v_WIN0_ACT_HEIGHT(win->area[0].yact);
1086 lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val);
1088 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
1089 v_WIN0_DSP_HEIGHT(win->area[0].ysize);
1090 lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val);
1092 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
1093 v_WIN0_DSP_YST(win->area[0].dsp_sty);
1094 lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val);
1096 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1097 v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1098 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1100 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1101 v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1102 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val);
1103 if (win->alpha_en == 1) {
1104 rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1106 mask = m_WIN0_SRC_ALPHA_EN;
1107 val = v_WIN0_SRC_ALPHA_EN(0);
1108 lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off,
1113 val = v_WIN0_EN(win->state);
1114 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1119 static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1121 struct lcdc_device *lcdc_dev =
1122 container_of(dev_drv, struct lcdc_device, driver);
1123 struct rk_lcdc_win *win = dev_drv->win[win_id];
1124 struct rk_screen *screen = dev_drv->cur_screen;
1125 unsigned int mask, val, off;
1127 off = (win_id - 2) * 0x50;
1128 rk3368_lcdc_area_xst(win, win->area_num);
1129 if (((screen->y_mirror == 1) || (win->mirror_en)) &&
1130 (win->area_num > 1)) {
1131 rk3368_lcdc_area_swap(win, win->area_num);
1134 if (win->state == 1) {
1135 rk3368_lcdc_csc_mode(lcdc_dev, win);
1136 if (win->area[0].fbdc_en)
1137 rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1139 mask = m_WIN2_EN | m_WIN2_CSC_MODE;
1140 val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode);
1141 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1143 if (win->area[0].state == 1) {
1144 mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 |
1146 val = v_WIN2_MST0_EN(win->area[0].state) |
1147 v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1148 v_WIN2_RB_SWAP0(win->area[0].swap_rb);
1149 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1151 mask = m_WIN2_VIR_STRIDE0;
1152 val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1153 lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1155 /*lcdc_writel(lcdc_dev,WIN2_MST0+off,
1156 win->area[0].y_addr); */
1157 val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1158 v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1159 lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val);
1160 val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1161 v_WIN2_DSP_YST0(win->area[0].dsp_sty);
1162 lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val);
1164 mask = m_WIN2_MST0_EN;
1165 val = v_WIN2_MST0_EN(0);
1166 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1169 if (win->area[1].state == 1) {
1170 rk3368_win_area_check_var(win_id, 1,
1171 &win->area[0], &win->area[1]);
1173 mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 |
1175 val = v_WIN2_MST1_EN(win->area[1].state) |
1176 v_WIN2_DATA_FMT0(win->area[1].fmt_cfg) |
1177 v_WIN2_RB_SWAP0(win->area[1].swap_rb);
1178 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1180 mask = m_WIN2_VIR_STRIDE1;
1181 val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1182 lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1184 /*lcdc_writel(lcdc_dev,WIN2_MST1+off,
1185 win->area[1].y_addr); */
1186 val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1187 v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1188 lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val);
1189 val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1190 v_WIN2_DSP_YST1(win->area[1].dsp_sty);
1191 lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val);
1193 mask = m_WIN2_MST1_EN;
1194 val = v_WIN2_MST1_EN(0);
1195 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1198 if (win->area[2].state == 1) {
1199 rk3368_win_area_check_var(win_id, 2,
1200 &win->area[1], &win->area[2]);
1202 mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 |
1204 val = v_WIN2_MST2_EN(win->area[2].state) |
1205 v_WIN2_DATA_FMT0(win->area[2].fmt_cfg) |
1206 v_WIN2_RB_SWAP0(win->area[2].swap_rb);
1207 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1209 mask = m_WIN2_VIR_STRIDE2;
1210 val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1211 lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1213 /*lcdc_writel(lcdc_dev,WIN2_MST2+off,
1214 win->area[2].y_addr); */
1215 val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1216 v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1217 lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val);
1218 val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1219 v_WIN2_DSP_YST2(win->area[2].dsp_sty);
1220 lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val);
1222 mask = m_WIN2_MST2_EN;
1223 val = v_WIN2_MST2_EN(0);
1224 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1227 if (win->area[3].state == 1) {
1228 rk3368_win_area_check_var(win_id, 3,
1229 &win->area[2], &win->area[3]);
1231 mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 |
1233 val = v_WIN2_MST3_EN(win->area[3].state) |
1234 v_WIN2_DATA_FMT0(win->area[3].fmt_cfg) |
1235 v_WIN2_RB_SWAP0(win->area[3].swap_rb);
1236 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1238 mask = m_WIN2_VIR_STRIDE3;
1239 val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1240 lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1242 /*lcdc_writel(lcdc_dev,WIN2_MST3+off,
1243 win->area[3].y_addr); */
1244 val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1245 v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1246 lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val);
1247 val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1248 v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1249 lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val);
1251 mask = m_WIN2_MST3_EN;
1252 val = v_WIN2_MST3_EN(0);
1253 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1256 if (win->alpha_en == 1) {
1257 rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1259 mask = m_WIN2_SRC_ALPHA_EN;
1260 val = v_WIN2_SRC_ALPHA_EN(0);
1261 lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off,
1265 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1266 m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1267 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1268 v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1269 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1274 static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1276 struct lcdc_device *lcdc_dev =
1277 container_of(dev_drv, struct lcdc_device, driver);
1278 struct rk_lcdc_win *win = dev_drv->win[win_id];
1279 unsigned int mask, val, hwc_size = 0;
1281 if (win->state == 1) {
1282 rk3368_lcdc_csc_mode(lcdc_dev, win);
1283 mask = m_HWC_EN | m_HWC_DATA_FMT |
1284 m_HWC_RB_SWAP | m_WIN0_CSC_MODE;
1285 val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1286 v_HWC_RB_SWAP(win->area[0].swap_rb) |
1287 v_WIN0_CSC_MODE(win->csc_mode);
1288 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1290 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1292 else if ((win->area[0].xsize == 64) &&
1293 (win->area[0].ysize == 64))
1295 else if ((win->area[0].xsize == 96) &&
1296 (win->area[0].ysize == 96))
1298 else if ((win->area[0].xsize == 128) &&
1299 (win->area[0].ysize == 128))
1302 dev_err(lcdc_dev->dev, "un supported hwc size!\n");
1305 val = v_HWC_SIZE(hwc_size);
1306 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1308 mask = m_HWC_DSP_XST | m_HWC_DSP_YST;
1309 val = v_HWC_DSP_XST(win->area[0].dsp_stx) |
1310 v_HWC_DSP_YST(win->area[0].dsp_sty);
1311 lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val);
1313 if (win->alpha_en == 1) {
1314 rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1316 mask = m_WIN2_SRC_ALPHA_EN;
1317 val = v_WIN2_SRC_ALPHA_EN(0);
1318 lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val);
1322 val = v_HWC_EN(win->state);
1323 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1328 static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
1329 struct rk_lcdc_win *win)
1331 struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1333 unsigned long flags;
1335 spin_lock(&lcdc_dev->reg_lock);
1336 if (likely(lcdc_dev->clk_on)) {
1337 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1338 v_STANDBY_EN(lcdc_dev->standby));
1339 if ((win->id == 0) || (win->id == 1))
1340 rk3368_win_0_1_reg_update(dev_drv, win->id);
1341 else if ((win->id == 2) || (win->id == 3))
1342 rk3368_win_2_3_reg_update(dev_drv, win->id);
1343 else if (win->id == 4)
1344 rk3368_hwc_reg_update(dev_drv, win->id);
1345 /*rk3368_lcdc_post_cfg(dev_drv); */
1346 lcdc_cfg_done(lcdc_dev);
1348 spin_unlock(&lcdc_dev->reg_lock);
1350 /*if (dev_drv->wait_fs) { */
1352 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1353 init_completion(&dev_drv->frame_done);
1354 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1356 wait_for_completion_timeout(&dev_drv->frame_done,
1358 (dev_drv->cur_screen->ft + 5));
1359 if (!timeout && (!dev_drv->frame_done.done)) {
1360 dev_warn(lcdc_dev->dev,
1361 "wait for new frame start time out!\n");
1365 DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1369 static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1371 if (lcdc_dev->driver.iommu_enabled)
1372 memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x330);
1374 memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x260);
1378 static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1381 struct lcdc_device *lcdc_dev =
1382 container_of(dev_drv, struct lcdc_device, driver);
1383 /*spin_lock(&lcdc_dev->reg_lock); */
1384 if (likely(lcdc_dev->clk_on)) {
1387 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1388 mask = m_AXI_MAX_OUTSTANDING_EN | m_AXI_OUTSTANDING_MAX_NUM;
1389 val = v_AXI_OUTSTANDING_MAX_NUM(31) |
1390 v_AXI_MAX_OUTSTANDING_EN(1);
1391 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1393 /*spin_unlock(&lcdc_dev->reg_lock); */
1394 #if defined(CONFIG_ROCKCHIP_IOMMU)
1395 if (dev_drv->iommu_enabled) {
1396 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1397 lcdc_dev->iommu_status = 1;
1398 rockchip_iovmm_activate(dev_drv->dev);
1399 rk312x_lcdc_mmu_en(dev_drv);
1406 static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
1408 int ret = 0, fps = 0;
1409 struct lcdc_device *lcdc_dev =
1410 container_of(dev_drv, struct lcdc_device, driver);
1411 struct rk_screen *screen = dev_drv->cur_screen;
1412 #ifdef CONFIG_RK_FPGA
1416 ret = clk_set_rate(lcdc_dev->pll_sclk, screen->mode.pixclock);
1418 dev_err(dev_drv->dev, "set lcdc%d pll_sclk failed\n",
1421 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1423 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1424 lcdc_dev->pixclock =
1425 div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1426 lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1428 fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1429 screen->ft = 1000 / fps;
1430 dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1431 lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1435 static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv)
1437 struct lcdc_device *lcdc_dev =
1438 container_of(dev_drv, struct lcdc_device, driver);
1439 struct rk_screen *screen = dev_drv->cur_screen;
1440 u16 hsync_len = screen->mode.hsync_len;
1441 u16 left_margin = screen->mode.left_margin;
1442 u16 right_margin = screen->mode.right_margin;
1443 u16 vsync_len = screen->mode.vsync_len;
1444 u16 upper_margin = screen->mode.upper_margin;
1445 u16 lower_margin = screen->mode.lower_margin;
1446 u16 x_res = screen->mode.xres;
1447 u16 y_res = screen->mode.yres;
1449 u16 h_total, v_total;
1450 u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1452 h_total = hsync_len + left_margin + x_res + right_margin;
1453 v_total = vsync_len + upper_margin + y_res + lower_margin;
1455 screen->post_dsp_stx = x_res * (100 - screen->overscan.left) / 200;
1456 screen->post_dsp_sty = y_res * (100 - screen->overscan.top) / 200;
1457 screen->post_xsize = x_res *
1458 (screen->overscan.left + screen->overscan.right) / 200;
1459 screen->post_ysize = y_res *
1460 (screen->overscan.top + screen->overscan.bottom) / 200;
1462 mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1463 val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1464 lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1466 mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1467 val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1468 v_DSP_HACT_ST(hsync_len + left_margin);
1469 lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1471 if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1472 /* First Field Timing */
1473 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1474 val = v_DSP_VS_PW(vsync_len) |
1475 v_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1476 lower_margin) + y_res + 1);
1477 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1479 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1480 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1481 v_DSP_VACT_ST(vsync_len + upper_margin);
1482 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1484 /* Second Field Timing */
1485 mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1;
1486 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1487 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1489 val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1);
1490 lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val);
1492 mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1;
1493 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1495 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1498 v_DSP_VACT_END_F1(vact_end_f1) |
1499 v_DSP_VAC_ST_F1(vact_st_f1);
1500 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val);
1502 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1503 m_DSP_INTERLACE | m_DSP_FIELD_POL,
1504 v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0));
1506 m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1509 v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(1) |
1510 v_WIN0_CBR_DEFLICK(1);
1511 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1514 m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1517 v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(1) |
1518 v_WIN1_CBR_DEFLICK(1);
1519 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1521 mask = m_WIN2_INTERLACE_READ;
1522 val = v_WIN2_INTERLACE_READ(1);
1523 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1525 mask = m_WIN3_INTERLACE_READ;
1526 val = v_WIN3_INTERLACE_READ(1);
1527 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1529 mask = m_HWC_INTERLACE_READ;
1530 val = v_HWC_INTERLACE_READ(1);
1531 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1533 mask = m_DSP_LINE_FLAG0_NUM;
1535 v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res / 2);
1536 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1538 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1539 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1540 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1542 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1543 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1544 v_DSP_VACT_ST(vsync_len + upper_margin);
1545 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1547 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1548 m_DSP_INTERLACE | m_DSP_FIELD_POL,
1549 v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0));
1552 m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1555 v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) |
1556 v_WIN0_CBR_DEFLICK(0);
1557 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1560 m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1563 v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) |
1564 v_WIN1_CBR_DEFLICK(0);
1565 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1567 mask = m_WIN2_INTERLACE_READ;
1568 val = v_WIN2_INTERLACE_READ(0);
1569 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1571 mask = m_WIN3_INTERLACE_READ;
1572 val = v_WIN3_INTERLACE_READ(0);
1573 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1575 mask = m_HWC_INTERLACE_READ;
1576 val = v_HWC_INTERLACE_READ(0);
1577 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1579 mask = m_DSP_LINE_FLAG0_NUM;
1580 val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res);
1581 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1583 rk3368_lcdc_post_cfg(dev_drv);
1587 static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1589 struct lcdc_device *lcdc_dev =
1590 container_of(dev_drv, struct lcdc_device, driver);
1593 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1594 if (dev_drv->output_color == COLOR_YCBCR) /* bypass */
1595 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1596 m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1597 v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1599 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1600 m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1603 v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1605 } else { /* overlay_mode=VOP_RGB_DOMAIN */
1606 /* bypass --need check,if bcsh close? */
1607 if (dev_drv->output_color == COLOR_RGB) {
1608 bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1609 if ((bcsh_ctrl & m_BCSH_EN) == 1)/*bcsh enabled */
1610 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1616 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1617 m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1620 } else /* RGB2YUV */
1621 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1623 m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1625 v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1630 static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1635 struct lcdc_device *lcdc_dev =
1636 container_of(dev_drv, struct lcdc_device, driver);
1637 struct rk_screen *screen = dev_drv->cur_screen;
1640 spin_lock(&lcdc_dev->reg_lock);
1641 if (likely(lcdc_dev->clk_on)) {
1642 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1643 if (!lcdc_dev->standby && !initscreen) {
1644 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1646 lcdc_cfg_done(lcdc_dev);
1649 switch (screen->face) {
1652 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1654 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1655 v_DITHER_DOWN_SEL(1);
1656 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1660 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1662 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1663 v_DITHER_DOWN_SEL(1);
1664 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1668 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1670 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1671 v_DITHER_DOWN_SEL(1);
1672 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1676 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1678 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1679 v_DITHER_DOWN_SEL(1);
1680 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1684 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1685 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1686 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1689 /*yuv420 output prefer yuv domain overlay */
1692 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1693 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1694 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1697 dev_err(lcdc_dev->dev, "un supported interface!\n");
1700 switch (screen->type) {
1702 mask = m_RGB_OUT_EN;
1703 val = v_RGB_OUT_EN(1);
1704 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1705 mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1706 m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1707 val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1708 v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1709 v_RGB_LVDS_DEN_POL(screen->pin_den) |
1710 v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1711 v = 1 << 15 | (1 << (15 + 16));
1715 mask = m_RGB_OUT_EN;
1716 val = v_RGB_OUT_EN(1);
1717 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1718 mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1719 m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1720 val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1721 v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1722 v_RGB_LVDS_DEN_POL(screen->pin_den) |
1723 v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1724 v = 0 << 15 | (1 << (15 + 16));
1728 mask = m_HDMI_OUT_EN;
1729 val = v_HDMI_OUT_EN(1);
1730 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1731 mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
1732 m_HDMI_DEN_POL | m_HDMI_DCLK_POL;
1733 val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
1734 v_HDMI_VSYNC_POL(screen->pin_vsync) |
1735 v_HDMI_DEN_POL(screen->pin_den) |
1736 v_HDMI_DCLK_POL(screen->pin_dclk);
1739 mask = m_MIPI_OUT_EN;
1740 val = v_MIPI_OUT_EN(1);
1741 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1742 mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1743 m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1744 val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1745 v_MIPI_VSYNC_POL(screen->pin_vsync) |
1746 v_MIPI_DEN_POL(screen->pin_den) |
1747 v_MIPI_DCLK_POL(screen->pin_dclk);
1749 case SCREEN_DUAL_MIPI:
1750 mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN;
1751 val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1);
1752 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1753 mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1754 m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1755 val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1756 v_MIPI_VSYNC_POL(screen->pin_vsync) |
1757 v_MIPI_DEN_POL(screen->pin_den) |
1758 v_MIPI_DCLK_POL(screen->pin_dclk);
1761 face = OUT_RGB_AAA; /*RGB AAA output */
1763 mask = m_EDP_OUT_EN;
1764 val = v_EDP_OUT_EN(1);
1765 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1766 /*because edp have to sent aaa fmt */
1767 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1768 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1770 mask |= m_EDP_HSYNC_POL | m_EDP_VSYNC_POL |
1771 m_EDP_DEN_POL | m_EDP_DCLK_POL;
1772 val |= v_EDP_HSYNC_POL(screen->pin_hsync) |
1773 v_EDP_VSYNC_POL(screen->pin_vsync) |
1774 v_EDP_DEN_POL(screen->pin_den) |
1775 v_EDP_DCLK_POL(screen->pin_dclk);
1778 /*hsync vsync den dclk polo,dither */
1779 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1780 #ifndef CONFIG_RK_FPGA
1781 /*writel_relaxed(v, RK_GRF_VIRT + rk3368_GRF_SOC_CON7);
1782 move to lvds driver*/
1783 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
1785 mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP |
1786 m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1787 m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1788 m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
1789 val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) |
1790 v_DSP_BG_SWAP(screen->swap_gb) |
1791 v_DSP_RB_SWAP(screen->swap_rb) |
1792 v_DSP_RG_SWAP(screen->swap_rg) |
1793 v_DSP_DELTA_SWAP(screen->swap_delta) |
1794 v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1795 v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1796 v_DSP_X_MIR_EN(screen->x_mirror) |
1797 v_DSP_Y_MIR_EN(screen->y_mirror);
1798 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1800 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1801 val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) | v_DSP_BG_RED(0);
1802 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1803 rk3368_lcdc_bcsh_path_sel(dev_drv);
1804 rk3368_config_timing(dev_drv);
1806 spin_unlock(&lcdc_dev->reg_lock);
1807 rk3368_lcdc_set_dclk(dev_drv);
1808 if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1809 dev_drv->trsm_ops->enable)
1810 dev_drv->trsm_ops->enable();
1813 if (!lcdc_dev->standby)
1814 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
1819 /*enable layer,open:1,enable;0 disable*/
1820 static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev,
1821 unsigned int win_id, bool open)
1823 spin_lock(&lcdc_dev->reg_lock);
1824 if (likely(lcdc_dev->clk_on) &&
1825 lcdc_dev->driver.win[win_id]->state != open) {
1827 if (!lcdc_dev->atv_layer_cnt) {
1828 dev_info(lcdc_dev->dev,
1829 "wakeup from standby!\n");
1830 lcdc_dev->standby = 0;
1832 lcdc_dev->atv_layer_cnt |= (1 << win_id);
1834 if (lcdc_dev->atv_layer_cnt & (1 << win_id))
1835 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
1837 lcdc_dev->driver.win[win_id]->state = open;
1839 /*rk3368_lcdc_reg_update(dev_drv);*/
1840 rk3368_lcdc_layer_update_regs
1841 (lcdc_dev, lcdc_dev->driver.win[win_id]);
1842 lcdc_cfg_done(lcdc_dev);
1844 /*if no layer used,disable lcdc */
1845 if (!lcdc_dev->atv_layer_cnt) {
1846 dev_info(lcdc_dev->dev,
1847 "no layer is used,go to standby!\n");
1848 lcdc_dev->standby = 1;
1851 spin_unlock(&lcdc_dev->reg_lock);
1854 static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1856 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1857 struct lcdc_device, driver);
1859 /*struct rk_screen *screen = dev_drv->cur_screen; */
1861 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
1862 m_LINE_FLAG1_INTR_CLR;
1863 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
1864 v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1);
1865 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
1867 mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN | m_BUS_ERROR_INTR_EN;
1868 val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) |
1869 v_BUS_ERROR_INTR_EN(1);
1870 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1872 #ifdef LCDC_IRQ_EMPTY_DEBUG
1873 mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
1874 m_WIN2_EMPTY_INTR_EN |
1875 m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN |
1876 m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN;
1877 val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) |
1878 v_WIN2_EMPTY_INTR_EN(1) |
1879 v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) |
1880 v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1);
1881 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1886 static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1889 struct lcdc_device *lcdc_dev =
1890 container_of(dev_drv, struct lcdc_device, driver);
1891 #ifndef CONFIG_RK_FPGA
1893 (dev_drv->id == 0) ? SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
1895 /*enable clk,when first layer open */
1896 if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1897 #ifndef CONFIG_RK_FPGA
1898 rockchip_set_system_status(sys_status);
1900 rk3368_lcdc_pre_init(dev_drv);
1901 rk3368_lcdc_clk_enable(lcdc_dev);
1902 #if defined(CONFIG_ROCKCHIP_IOMMU)
1903 if (dev_drv->iommu_enabled) {
1904 if (!dev_drv->mmu_dev) {
1906 rk_fb_get_sysmmu_device_by_compatible
1907 (dev_drv->mmu_dts_name);
1908 if (dev_drv->mmu_dev) {
1909 rk_fb_platform_set_sysmmu
1910 (dev_drv->mmu_dev, dev_drv->dev);
1912 dev_err(dev_drv->dev,
1913 "fail get rk iommu device\n");
1917 /*if (dev_drv->mmu_dev)
1918 rockchip_iovmm_activate(dev_drv->dev); */
1921 rk3368_lcdc_reg_restore(lcdc_dev);
1922 /*if (dev_drv->iommu_enabled)
1923 rk3368_lcdc_mmu_en(dev_drv); */
1924 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
1925 /*rk3368_lcdc_set_dclk(dev_drv); */
1926 rk3368_lcdc_enable_irq(dev_drv);
1928 rk3368_load_screen(dev_drv, 1);
1930 if (dev_drv->bcsh.enable)
1931 rk3368_lcdc_set_bcsh(dev_drv, 1);
1932 spin_lock(&lcdc_dev->reg_lock);
1933 if (dev_drv->cur_screen->dsp_lut)
1934 rk3368_lcdc_set_lut(dev_drv);
1935 spin_unlock(&lcdc_dev->reg_lock);
1938 if (win_id < ARRAY_SIZE(lcdc_win))
1939 rk3368_lcdc_layer_enable(lcdc_dev, win_id, open);
1941 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1944 /* when all layer closed,disable clk */
1945 /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1946 rk3368_lcdc_disable_irq(lcdc_dev);
1947 rk3368_lcdc_reg_update(dev_drv);
1948 #if defined(CONFIG_ROCKCHIP_IOMMU)
1949 if (dev_drv->iommu_enabled) {
1950 if (dev_drv->mmu_dev)
1951 rockchip_iovmm_deactivate(dev_drv->dev);
1954 rk3368_lcdc_clk_disable(lcdc_dev);
1955 #ifndef CONFIG_RK_FPGA
1956 rockchip_clear_system_status(sys_status);
1963 static int win_0_1_display(struct lcdc_device *lcdc_dev,
1964 struct rk_lcdc_win *win)
1970 off = win->id * 0x40;
1971 /*win->smem_start + win->y_offset; */
1972 y_addr = win->area[0].smem_start + win->area[0].y_offset;
1973 uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1974 DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
1975 lcdc_dev->id, win->id, y_addr, uv_addr);
1976 DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
1977 win->area[0].y_offset, win->area[0].c_offset);
1978 spin_lock(&lcdc_dev->reg_lock);
1979 if (likely(lcdc_dev->clk_on)) {
1980 win->area[0].y_addr = y_addr;
1981 win->area[0].uv_addr = uv_addr;
1982 lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
1983 lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
1984 /*lcdc_cfg_done(lcdc_dev); */
1986 spin_unlock(&lcdc_dev->reg_lock);
1991 static int win_2_3_display(struct lcdc_device *lcdc_dev,
1992 struct rk_lcdc_win *win)
1997 off = (win->id - 2) * 0x50;
1998 y_addr = win->area[0].smem_start + win->area[0].y_offset;
1999 DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id);
2001 spin_lock(&lcdc_dev->reg_lock);
2002 if (likely(lcdc_dev->clk_on)) {
2003 for (i = 0; i < win->area_num; i++) {
2004 DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2005 i, win->area[i].y_addr, win->area[i].y_offset);
2006 win->area[i].y_addr =
2007 win->area[i].smem_start + win->area[i].y_offset;
2009 lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr);
2010 lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr);
2011 lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr);
2012 lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr);
2014 spin_unlock(&lcdc_dev->reg_lock);
2018 static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win)
2022 y_addr = win->area[0].smem_start + win->area[0].y_offset;
2023 DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2024 lcdc_dev->id, __func__, y_addr);
2025 spin_lock(&lcdc_dev->reg_lock);
2026 if (likely(lcdc_dev->clk_on)) {
2027 win->area[0].y_addr = y_addr;
2028 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
2030 spin_unlock(&lcdc_dev->reg_lock);
2035 static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2037 struct lcdc_device *lcdc_dev =
2038 container_of(dev_drv, struct lcdc_device, driver);
2039 struct rk_lcdc_win *win = NULL;
2040 struct rk_screen *screen = dev_drv->cur_screen;
2042 #if defined(WAIT_FOR_SYNC)
2044 unsigned long flags;
2046 win = dev_drv->win[win_id];
2048 dev_err(dev_drv->dev, "screen is null!\n");
2052 win_0_1_display(lcdc_dev, win);
2053 } else if (win_id == 1) {
2054 win_0_1_display(lcdc_dev, win);
2055 } else if (win_id == 2) {
2056 win_2_3_display(lcdc_dev, win);
2057 } else if (win_id == 3) {
2058 win_2_3_display(lcdc_dev, win);
2059 } else if (win_id == 4) {
2060 hwc_display(lcdc_dev, win);
2062 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2066 /*this is the first frame of the system ,enable frame start interrupt */
2067 if ((dev_drv->first_frame)) {
2068 dev_drv->first_frame = 0;
2069 rk3368_lcdc_enable_irq(dev_drv);
2071 #if defined(WAIT_FOR_SYNC)
2072 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
2073 init_completion(&dev_drv->frame_done);
2074 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
2076 wait_for_completion_timeout(&dev_drv->frame_done,
2077 msecs_to_jiffies(dev_drv->
2078 cur_screen->ft + 5));
2079 if (!timeout && (!dev_drv->frame_done.done)) {
2080 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
2087 static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
2097 u32 yrgb_vscalednmult;
2098 u32 yrgb_xscl_factor;
2099 u32 yrgb_yscl_factor;
2100 u8 yrgb_vsd_bil_gt2 = 0;
2101 u8 yrgb_vsd_bil_gt4 = 0;
2107 u32 cbcr_vscalednmult;
2108 u32 cbcr_xscl_factor;
2109 u32 cbcr_yscl_factor;
2110 u8 cbcr_vsd_bil_gt2 = 0;
2111 u8 cbcr_vsd_bil_gt4 = 0;
2114 srcW = win->area[0].xact;
2115 srcH = win->area[0].yact;
2116 dstW = win->area[0].xsize;
2117 dstH = win->area[0].ysize;
2124 if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2125 pr_err("ERROR: yrgb scale exceed 8,");
2126 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2127 yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2129 if (yrgb_srcW < yrgb_dstW)
2130 win->yrgb_hor_scl_mode = SCALE_UP;
2131 else if (yrgb_srcW > yrgb_dstW)
2132 win->yrgb_hor_scl_mode = SCALE_DOWN;
2134 win->yrgb_hor_scl_mode = SCALE_NONE;
2136 if (yrgb_srcH < yrgb_dstH)
2137 win->yrgb_ver_scl_mode = SCALE_UP;
2138 else if (yrgb_srcH > yrgb_dstH)
2139 win->yrgb_ver_scl_mode = SCALE_DOWN;
2141 win->yrgb_ver_scl_mode = SCALE_NONE;
2144 switch (win->area[0].format) {
2147 cbcr_srcW = srcW / 2;
2155 cbcr_srcW = srcW / 2;
2157 cbcr_srcH = srcH / 2;
2178 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2179 (cbcr_dstH * 8 <= cbcr_srcH)) {
2180 pr_err("ERROR: cbcr scale exceed 8,");
2181 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2182 cbcr_srcH, cbcr_dstW, cbcr_dstH);
2186 if (cbcr_srcW < cbcr_dstW)
2187 win->cbr_hor_scl_mode = SCALE_UP;
2188 else if (cbcr_srcW > cbcr_dstW)
2189 win->cbr_hor_scl_mode = SCALE_DOWN;
2191 win->cbr_hor_scl_mode = SCALE_NONE;
2193 if (cbcr_srcH < cbcr_dstH)
2194 win->cbr_ver_scl_mode = SCALE_UP;
2195 else if (cbcr_srcH > cbcr_dstH)
2196 win->cbr_ver_scl_mode = SCALE_DOWN;
2198 win->cbr_ver_scl_mode = SCALE_NONE;
2200 /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
2201 "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
2202 "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW,
2203 srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH,
2204 win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW,
2205 cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode,
2206 win->cbr_ver_scl_mode);*/
2208 /*line buffer mode */
2209 if ((win->area[0].format == YUV422) ||
2210 (win->area[0].format == YUV420) ||
2211 (win->area[0].format == YUV422_A) ||
2212 (win->area[0].format == YUV420_A)) {
2213 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2214 if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2216 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2218 else if (cbcr_dstW > 1280)
2219 win->win_lb_mode = LB_YUV_3840X5;
2221 win->win_lb_mode = LB_YUV_2560X8;
2222 } else { /*SCALE_UP or SCALE_NONE */
2223 if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2225 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2227 else if (cbcr_srcW > 1280)
2228 win->win_lb_mode = LB_YUV_3840X5;
2230 win->win_lb_mode = LB_YUV_2560X8;
2233 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2234 if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2236 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2237 else if (yrgb_dstW > 2560)
2238 win->win_lb_mode = LB_RGB_3840X2;
2239 else if (yrgb_dstW > 1920)
2240 win->win_lb_mode = LB_RGB_2560X4;
2241 else if (yrgb_dstW > 1280)
2242 win->win_lb_mode = LB_RGB_1920X5;
2244 win->win_lb_mode = LB_RGB_1280X8;
2245 } else { /*SCALE_UP or SCALE_NONE */
2246 if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2248 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2249 else if (yrgb_srcW > 2560)
2250 win->win_lb_mode = LB_RGB_3840X2;
2251 else if (yrgb_srcW > 1920)
2252 win->win_lb_mode = LB_RGB_2560X4;
2253 else if (yrgb_srcW > 1280)
2254 win->win_lb_mode = LB_RGB_1920X5;
2256 win->win_lb_mode = LB_RGB_1280X8;
2259 DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2261 /*vsd/vsu scale ALGORITHM */
2262 win->yrgb_hsd_mode = SCALE_DOWN_BIL; /*not to specify */
2263 win->cbr_hsd_mode = SCALE_DOWN_BIL; /*not to specify */
2264 win->yrgb_vsd_mode = SCALE_DOWN_BIL; /*not to specify */
2265 win->cbr_vsd_mode = SCALE_DOWN_BIL; /*not to specify */
2266 switch (win->win_lb_mode) {
2271 win->yrgb_vsu_mode = SCALE_UP_BIC;
2272 win->cbr_vsu_mode = SCALE_UP_BIC;
2275 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2276 pr_err("ERROR : not allow yrgb ver scale\n");
2277 if (win->cbr_ver_scl_mode != SCALE_NONE)
2278 pr_err("ERROR : not allow cbcr ver scale\n");
2281 win->yrgb_vsu_mode = SCALE_UP_BIL;
2282 win->cbr_vsu_mode = SCALE_UP_BIL;
2285 pr_info("%s:un supported win_lb_mode:%d\n",
2286 __func__, win->win_lb_mode);
2289 if (win->mirror_en == 1) { /*interlace mode must bill */
2290 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2293 if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2294 (win->area[0].fbdc_en == 1)) {
2295 /*in this pattern,use bil mode,not support souble scd,
2296 use avg mode, support double scd, but aclk should be
2297 bigger than dclk,aclk>>dclk */
2298 if (yrgb_srcH >= 2 * yrgb_dstH) {
2299 pr_err("ERROR : fbdc mode,not support y scale down:");
2300 pr_err("srcH[%d] > 2 *dstH[%d]\n",
2301 yrgb_srcH, yrgb_dstH);
2304 DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2305 win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2306 win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2310 /*(1.1)YRGB HOR SCALE FACTOR */
2311 switch (win->yrgb_hor_scl_mode) {
2313 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2316 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2319 switch (win->yrgb_hsd_mode) {
2320 case SCALE_DOWN_BIL:
2322 GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2324 case SCALE_DOWN_AVG:
2326 GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2330 "%s:un supported yrgb_hsd_mode:%d\n", __func__,
2331 win->yrgb_hsd_mode);
2336 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2337 __func__, win->yrgb_hor_scl_mode);
2339 } /*win->yrgb_hor_scl_mode */
2341 /*(1.2)YRGB VER SCALE FACTOR */
2342 switch (win->yrgb_ver_scl_mode) {
2344 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2347 switch (win->yrgb_vsu_mode) {
2350 GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2353 if (yrgb_srcH < 3) {
2354 pr_err("yrgb_srcH should be");
2355 pr_err(" greater than 3 !!!\n");
2357 yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2361 pr_info("%s:un support yrgb_vsu_mode:%d\n",
2362 __func__, win->yrgb_vsu_mode);
2367 switch (win->yrgb_vsd_mode) {
2368 case SCALE_DOWN_BIL:
2370 rk3368_get_hard_ware_vskiplines(yrgb_srcH,
2373 GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2375 if (yrgb_yscl_factor >= 0x2000) {
2376 pr_err("yrgb_yscl_factor should be ");
2377 pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n",
2380 if (yrgb_vscalednmult == 4) {
2381 yrgb_vsd_bil_gt4 = 1;
2382 yrgb_vsd_bil_gt2 = 0;
2383 } else if (yrgb_vscalednmult == 2) {
2384 yrgb_vsd_bil_gt4 = 0;
2385 yrgb_vsd_bil_gt2 = 1;
2387 yrgb_vsd_bil_gt4 = 0;
2388 yrgb_vsd_bil_gt2 = 0;
2391 case SCALE_DOWN_AVG:
2392 yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2396 pr_info("%s:un support yrgb_vsd_mode:%d\n",
2397 __func__, win->yrgb_vsd_mode);
2399 } /*win->yrgb_vsd_mode */
2402 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2403 __func__, win->yrgb_ver_scl_mode);
2406 win->scale_yrgb_x = yrgb_xscl_factor;
2407 win->scale_yrgb_y = yrgb_yscl_factor;
2408 win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2409 win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2410 DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2411 yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2413 /*(2.1)CBCR HOR SCALE FACTOR */
2414 switch (win->cbr_hor_scl_mode) {
2416 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2419 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2422 switch (win->cbr_hsd_mode) {
2423 case SCALE_DOWN_BIL:
2425 GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2427 case SCALE_DOWN_AVG:
2429 GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2432 pr_info("%s:un support cbr_hsd_mode:%d\n",
2433 __func__, win->cbr_hsd_mode);
2438 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2439 __func__, win->cbr_hor_scl_mode);
2441 } /*win->cbr_hor_scl_mode */
2443 /*(2.2)CBCR VER SCALE FACTOR */
2444 switch (win->cbr_ver_scl_mode) {
2446 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2449 switch (win->cbr_vsu_mode) {
2452 GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2455 if (cbcr_srcH < 3) {
2456 pr_err("cbcr_srcH should be ");
2457 pr_err("greater than 3 !!!\n");
2459 cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2463 pr_info("%s:un support cbr_vsu_mode:%d\n",
2464 __func__, win->cbr_vsu_mode);
2469 switch (win->cbr_vsd_mode) {
2470 case SCALE_DOWN_BIL:
2472 rk3368_get_hard_ware_vskiplines(cbcr_srcH,
2475 GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2477 if (cbcr_yscl_factor >= 0x2000) {
2478 pr_err("cbcr_yscl_factor should be less ");
2479 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2483 if (cbcr_vscalednmult == 4) {
2484 cbcr_vsd_bil_gt4 = 1;
2485 cbcr_vsd_bil_gt2 = 0;
2486 } else if (cbcr_vscalednmult == 2) {
2487 cbcr_vsd_bil_gt4 = 0;
2488 cbcr_vsd_bil_gt2 = 1;
2490 cbcr_vsd_bil_gt4 = 0;
2491 cbcr_vsd_bil_gt2 = 0;
2494 case SCALE_DOWN_AVG:
2495 cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2499 pr_info("%s:un support cbr_vsd_mode:%d\n",
2500 __func__, win->cbr_vsd_mode);
2505 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2506 __func__, win->cbr_ver_scl_mode);
2509 win->scale_cbcr_x = cbcr_xscl_factor;
2510 win->scale_cbcr_y = cbcr_yscl_factor;
2511 win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2512 win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2514 DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2515 cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2519 static int win_0_1_set_par(struct lcdc_device *lcdc_dev,
2520 struct rk_screen *screen, struct rk_lcdc_win *win)
2522 u32 xact, yact, xvir, yvir, xpos, ypos;
2523 u8 fmt_cfg = 0, swap_rb;
2524 char fmt[9] = "NULL";
2526 if (!win->mirror_en) {
2527 xpos = win->area[0].xpos + screen->mode.left_margin +
2528 screen->mode.hsync_len;
2529 ypos = win->area[0].ypos + screen->mode.upper_margin +
2530 screen->mode.vsync_len;
2532 xpos = screen->mode.xres - win->area[0].xpos -
2533 win->area[0].xsize +
2534 screen->mode.left_margin + screen->mode.hsync_len;
2535 ypos = screen->mode.yres - win->area[0].ypos -
2536 win->area[0].ysize + screen->mode.upper_margin +
2537 screen->mode.vsync_len;
2539 spin_lock(&lcdc_dev->reg_lock);
2540 if (likely(lcdc_dev->clk_on)) {
2541 rk3368_lcdc_cal_scl_fac(win); /*fac,lb,gt2,gt4 */
2542 switch (win->area[0].format) {
2595 dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n",
2599 win->area[0].fmt_cfg = fmt_cfg;
2600 win->area[0].swap_rb = swap_rb;
2601 win->area[0].dsp_stx = xpos;
2602 win->area[0].dsp_sty = ypos;
2603 xact = win->area[0].xact;
2604 yact = win->area[0].yact;
2605 xvir = win->area[0].xvir;
2606 yvir = win->area[0].yvir;
2608 if (win->area[0].fbdc_en)
2609 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2610 rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id);
2611 spin_unlock(&lcdc_dev->reg_lock);
2613 DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2614 lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2615 xact, yact, win->area[0].xsize);
2616 DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2617 win->area[0].ysize, xvir, yvir, xpos, ypos);
2623 static int win_2_3_set_par(struct lcdc_device *lcdc_dev,
2624 struct rk_screen *screen, struct rk_lcdc_win *win)
2627 u8 fmt_cfg, swap_rb;
2628 char fmt[9] = "NULL";
2630 spin_lock(&lcdc_dev->reg_lock);
2631 if (likely(lcdc_dev->clk_on)) {
2632 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id);
2633 for (i = 0; i < win->area_num; i++) {
2634 switch (win->area[i].format) {
2653 dev_err(lcdc_dev->driver.dev,
2654 "%s:un supported format!\n", __func__);
2657 win->area[i].fmt_cfg = fmt_cfg;
2658 win->area[i].swap_rb = swap_rb;
2659 win->area[i].dsp_stx = win->area[i].xpos +
2660 screen->mode.left_margin + screen->mode.hsync_len;
2661 if (screen->y_mirror == 1) {
2662 win->area[i].dsp_sty = screen->mode.yres -
2664 win->area[i].ysize +
2665 screen->mode.upper_margin +
2666 screen->mode.vsync_len;
2668 win->area[i].dsp_sty = win->area[i].ypos +
2669 screen->mode.upper_margin +
2670 screen->mode.vsync_len;
2673 DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
2674 get_format_string(win->area[i].format, fmt),
2675 win->area[i].xsize, win->area[i].ysize,
2676 win->area[i].xpos, win->area[i].ypos);
2679 if (win->area[0].fbdc_en)
2680 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2681 rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id);
2682 spin_unlock(&lcdc_dev->reg_lock);
2686 static int hwc_set_par(struct lcdc_device *lcdc_dev,
2687 struct rk_screen *screen, struct rk_lcdc_win *win)
2689 u32 xact, yact, xvir, yvir, xpos, ypos;
2690 u8 fmt_cfg = 0, swap_rb;
2691 char fmt[9] = "NULL";
2693 xpos = win->area[0].xpos + screen->mode.left_margin +
2694 screen->mode.hsync_len;
2695 ypos = win->area[0].ypos + screen->mode.upper_margin +
2696 screen->mode.vsync_len;
2698 spin_lock(&lcdc_dev->reg_lock);
2699 if (likely(lcdc_dev->clk_on)) {
2700 /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */
2701 switch (win->area[0].format) {
2720 dev_err(lcdc_dev->driver.dev,
2721 "%s:un supported format!\n", __func__);
2724 win->area[0].fmt_cfg = fmt_cfg;
2725 win->area[0].swap_rb = swap_rb;
2726 win->area[0].dsp_stx = xpos;
2727 win->area[0].dsp_sty = ypos;
2728 xact = win->area[0].xact;
2729 yact = win->area[0].yact;
2730 xvir = win->area[0].xvir;
2731 yvir = win->area[0].yvir;
2733 rk3368_hwc_reg_update(&lcdc_dev->driver, 4);
2734 spin_unlock(&lcdc_dev->reg_lock);
2736 DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2737 lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt),
2738 xact, yact, win->area[0].xsize);
2739 DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2740 win->area[0].ysize, xvir, yvir, xpos, ypos);
2744 static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
2746 struct lcdc_device *lcdc_dev =
2747 container_of(dev_drv, struct lcdc_device, driver);
2748 struct rk_lcdc_win *win = NULL;
2749 struct rk_screen *screen = dev_drv->cur_screen;
2751 win = dev_drv->win[win_id];
2754 win_0_1_set_par(lcdc_dev, screen, win);
2757 win_0_1_set_par(lcdc_dev, screen, win);
2760 win_2_3_set_par(lcdc_dev, screen, win);
2763 win_2_3_set_par(lcdc_dev, screen, win);
2766 hwc_set_par(lcdc_dev, screen, win);
2769 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2775 static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2776 unsigned long arg, int win_id)
2778 struct lcdc_device *lcdc_dev =
2779 container_of(dev_drv, struct lcdc_device, driver);
2781 void __user *argp = (void __user *)arg;
2782 struct color_key_cfg clr_key_cfg;
2785 case RK_FBIOGET_PANEL_SIZE:
2786 panel_size[0] = lcdc_dev->screen->mode.xres;
2787 panel_size[1] = lcdc_dev->screen->mode.yres;
2788 if (copy_to_user(argp, panel_size, 8))
2791 case RK_FBIOPUT_COLOR_KEY_CFG:
2792 if (copy_from_user(&clr_key_cfg, argp,
2793 sizeof(struct color_key_cfg)))
2795 rk3368_lcdc_clr_key_cfg(dev_drv);
2796 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
2797 clr_key_cfg.win0_color_key_cfg);
2798 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
2799 clr_key_cfg.win1_color_key_cfg);
2808 static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
2810 struct lcdc_device *lcdc_dev = container_of(dev_drv,
2811 struct lcdc_device, driver);
2812 /*struct device_node *backlight;*/
2814 if (lcdc_dev->backlight)
2817 backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0);
2819 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
2820 if (!lcdc_dev->backlight)
2821 dev_info(lcdc_dev->dev, "No find backlight device\n");
2823 dev_info(lcdc_dev->dev, "No find backlight device node\n");
2829 static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
2832 struct lcdc_device *lcdc_dev =
2833 container_of(dev_drv, struct lcdc_device, driver);
2834 if (dev_drv->suspend_flag)
2836 /* close the backlight */
2837 /*rk3368_lcdc_get_backlight_device(dev_drv);
2838 if (lcdc_dev->backlight) {
2839 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
2840 backlight_update_status(lcdc_dev->backlight);
2843 dev_drv->suspend_flag = 1;
2844 flush_kthread_worker(&dev_drv->update_regs_worker);
2846 for (reg = MMU_DTE_ADDR; reg <= MMU_AUTO_GATING; reg += 4)
2847 lcdc_readl(lcdc_dev, reg);
2848 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
2849 dev_drv->trsm_ops->disable();
2851 spin_lock(&lcdc_dev->reg_lock);
2852 if (likely(lcdc_dev->clk_on)) {
2853 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2855 lcdc_msk_reg(lcdc_dev,
2856 INTR_CLEAR, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR,
2857 v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1));
2858 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2860 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
2861 lcdc_cfg_done(lcdc_dev);
2863 if (dev_drv->iommu_enabled) {
2864 if (dev_drv->mmu_dev)
2865 rockchip_iovmm_deactivate(dev_drv->dev);
2868 spin_unlock(&lcdc_dev->reg_lock);
2870 spin_unlock(&lcdc_dev->reg_lock);
2873 rk3368_lcdc_clk_disable(lcdc_dev);
2874 rk_disp_pwr_disable(dev_drv);
2878 static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
2880 struct lcdc_device *lcdc_dev =
2881 container_of(dev_drv, struct lcdc_device, driver);
2886 if (!dev_drv->suspend_flag)
2888 rk_disp_pwr_enable(dev_drv);
2889 dev_drv->suspend_flag = 0;
2891 if (1/*lcdc_dev->atv_layer_cnt*/) {
2892 rk3368_lcdc_clk_enable(lcdc_dev);
2893 rk3368_lcdc_reg_restore(lcdc_dev);
2895 spin_lock(&lcdc_dev->reg_lock);
2896 if (dev_drv->cur_screen->dsp_lut) {
2897 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2899 lcdc_cfg_done(lcdc_dev);
2901 for (i = 0; i < 256; i++) {
2902 v = dev_drv->cur_screen->dsp_lut[i];
2903 c = lcdc_dev->dsp_lut_addr_base + (i << 2);
2908 for (j = 0; j < 4; j++) {
2909 writel_relaxed(v, c);
2910 v += (1 + (1 << 10) + (1 << 20));
2914 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2918 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2920 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
2921 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2923 lcdc_cfg_done(lcdc_dev);
2925 if (dev_drv->iommu_enabled) {
2926 if (dev_drv->mmu_dev)
2927 rockchip_iovmm_activate(dev_drv->dev);
2930 spin_unlock(&lcdc_dev->reg_lock);
2933 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2934 dev_drv->trsm_ops->enable();
2939 static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv,
2940 int win_id, int blank_mode)
2942 switch (blank_mode) {
2943 case FB_BLANK_UNBLANK:
2944 rk3368_lcdc_early_resume(dev_drv);
2946 case FB_BLANK_NORMAL:
2947 rk3368_lcdc_early_suspend(dev_drv);
2950 rk3368_lcdc_early_suspend(dev_drv);
2954 dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
2959 static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
2964 /*overlay will be do at regupdate*/
2965 static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
2968 struct lcdc_device *lcdc_dev =
2969 container_of(dev_drv, struct lcdc_device, driver);
2970 struct rk_lcdc_win *win = NULL;
2972 unsigned int mask, val;
2973 int z_order_num = 0;
2974 int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
2977 for (i = 0; i < 4; i++) {
2978 win = dev_drv->win[i];
2979 if (win->state == 1)
2982 for (i = 0; i < 4; i++) {
2983 win = dev_drv->win[i];
2984 if (win->state == 0)
2985 win->z_order = z_order_num++;
2986 switch (win->z_order) {
2988 layer0_sel = win->id;
2991 layer1_sel = win->id;
2994 layer2_sel = win->id;
2997 layer3_sel = win->id;
3004 layer0_sel = swap % 10;
3005 layer1_sel = swap / 10 % 10;
3006 layer2_sel = swap / 100 % 10;
3007 layer3_sel = swap / 1000;
3010 spin_lock(&lcdc_dev->reg_lock);
3011 if (lcdc_dev->clk_on) {
3013 mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
3014 m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
3015 val = v_DSP_LAYER0_SEL(layer0_sel) |
3016 v_DSP_LAYER1_SEL(layer1_sel) |
3017 v_DSP_LAYER2_SEL(layer2_sel) |
3018 v_DSP_LAYER3_SEL(layer3_sel);
3019 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
3021 layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3023 layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3025 layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3027 layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3029 ovl = layer3_sel * 1000 + layer2_sel * 100 +
3030 layer1_sel * 10 + layer0_sel;
3035 spin_unlock(&lcdc_dev->reg_lock);
3040 static char *rk3368_lcdc_format_to_string(int format, char *fmt)
3047 strcpy(fmt, "ARGB888");
3050 strcpy(fmt, "RGB888");
3053 strcpy(fmt, "RGB565");
3056 strcpy(fmt, "YCbCr420");
3059 strcpy(fmt, "YCbCr422");
3062 strcpy(fmt, "YCbCr444");
3065 strcpy(fmt, "invalid\n");
3070 static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
3071 char *buf, int win_id)
3073 struct lcdc_device *lcdc_dev =
3074 container_of(dev_drv, struct lcdc_device, driver);
3075 struct rk_screen *screen = dev_drv->cur_screen;
3076 u16 hsync_len = screen->mode.hsync_len;
3077 u16 left_margin = screen->mode.left_margin;
3078 u16 vsync_len = screen->mode.vsync_len;
3079 u16 upper_margin = screen->mode.upper_margin;
3080 u32 h_pw_bp = hsync_len + left_margin;
3081 u32 v_pw_bp = vsync_len + upper_margin;
3083 char format_w0[9] = "NULL";
3084 char format_w1[9] = "NULL";
3085 char format_w2_0[9] = "NULL";
3086 char format_w2_1[9] = "NULL";
3087 char format_w2_2[9] = "NULL";
3088 char format_w2_3[9] = "NULL";
3089 char format_w3_0[9] = "NULL";
3090 char format_w3_1[9] = "NULL";
3091 char format_w3_2[9] = "NULL";
3092 char format_w3_3[9] = "NULL";
3094 u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3095 u32 y_factor, uv_factor;
3096 u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3097 u8 w0_state, w1_state, w2_state, w3_state;
3098 u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3099 u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3101 u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3102 u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3103 u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3104 u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3105 u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3106 u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3108 u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3109 u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3110 u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3111 u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3112 u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3113 u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3114 u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3116 u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3117 u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3118 u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3119 u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3120 u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3121 u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3122 u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3126 dclk_freq = screen->mode.pixclock;
3127 /*rk3368_lcdc_reg_dump(dev_drv); */
3129 spin_lock(&lcdc_dev->reg_lock);
3130 if (lcdc_dev->clk_on) {
3131 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
3132 layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8;
3133 layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10;
3134 layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12;
3135 layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14;
3137 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3138 w0_state = win_ctrl & m_WIN0_EN;
3139 fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1;
3140 rk3368_lcdc_format_to_string(fmt_id, format_w0);
3141 vir_info = lcdc_readl(lcdc_dev, WIN0_VIR);
3142 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
3143 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
3144 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
3145 y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
3146 uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR);
3147 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
3148 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16;
3149 w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1;
3150 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1;
3151 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1;
3152 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1;
3154 w0_st_x = dsp_st & m_WIN0_DSP_XST;
3155 w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16;
3157 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
3158 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16;
3159 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
3160 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16;
3163 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3164 w1_state = win_ctrl & m_WIN1_EN;
3165 fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1;
3166 rk3368_lcdc_format_to_string(fmt_id, format_w1);
3167 vir_info = lcdc_readl(lcdc_dev, WIN1_VIR);
3168 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
3169 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
3170 dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
3171 y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB);
3172 uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR);
3173 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
3174 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16;
3175 w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1;
3176 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1;
3177 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1;
3178 w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1;
3180 w1_st_x = dsp_st & m_WIN1_DSP_XST;
3181 w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16;
3183 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
3184 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16;
3185 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
3186 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16;
3188 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3189 w2_state = win_ctrl & m_WIN2_EN;
3190 w2_0_state = (win_ctrl & m_WIN2_MST0_EN) >> 4;
3191 w2_1_state = (win_ctrl & m_WIN2_MST1_EN) >> 5;
3192 w2_2_state = (win_ctrl & m_WIN2_MST2_EN) >> 6;
3193 w2_3_state = (win_ctrl & m_WIN2_MST3_EN) >> 7;
3194 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1);
3195 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3196 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16;
3197 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3);
3198 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3199 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16;
3201 fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1;
3202 rk3368_lcdc_format_to_string(fmt_id, format_w2_0);
3203 fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1;
3204 rk3368_lcdc_format_to_string(fmt_id, format_w2_1);
3205 fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1;
3206 rk3368_lcdc_format_to_string(fmt_id, format_w2_2);
3207 fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1;
3208 rk3368_lcdc_format_to_string(fmt_id, format_w2_3);
3210 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0);
3211 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0);
3212 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1;
3213 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1;
3215 w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3216 w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16;
3218 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1);
3219 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1);
3220 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1;
3221 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1;
3223 w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3224 w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16;
3226 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2);
3227 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2);
3228 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1;
3229 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1;
3231 w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3232 w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16;
3234 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3);
3235 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3);
3236 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1;
3237 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1;
3239 w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3240 w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16;
3244 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3245 w3_state = win_ctrl & m_WIN3_EN;
3246 w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4;
3247 w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 5;
3248 w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 6;
3249 w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 7;
3250 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1);
3251 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3252 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16;
3253 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3);
3254 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3255 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16;
3256 fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1;
3257 rk3368_lcdc_format_to_string(fmt_id, format_w3_0);
3258 fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1;
3259 rk3368_lcdc_format_to_string(fmt_id, format_w3_1);
3260 fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1;
3261 rk3368_lcdc_format_to_string(fmt_id, format_w3_2);
3262 fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1;
3263 rk3368_lcdc_format_to_string(fmt_id, format_w3_3);
3264 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0);
3265 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0);
3266 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1;
3267 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1;
3269 w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3270 w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16;
3273 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1);
3274 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1);
3275 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1;
3276 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1;
3278 w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3279 w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16;
3282 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2);
3283 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2);
3284 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1;
3285 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1;
3287 w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3288 w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16;
3291 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3);
3292 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3);
3293 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1;
3294 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1;
3296 w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3297 w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16;
3301 spin_unlock(&lcdc_dev->reg_lock);
3304 spin_unlock(&lcdc_dev->reg_lock);
3305 size += snprintf(dsp_buf, 80,
3306 "z-order:\n win[%d]\n win[%d]\n win[%d]\n win[%d]\n",
3307 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3308 strcat(buf, dsp_buf);
3309 memset(dsp_buf, 0, sizeof(dsp_buf));
3311 size += snprintf(dsp_buf, 80,
3312 "win0:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,",
3313 w0_state, format_w0, w0_vir_y, w0_vir_uv);
3314 strcat(buf, dsp_buf);
3315 memset(dsp_buf, 0, sizeof(dsp_buf));
3317 size += snprintf(dsp_buf, 80,
3318 " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n",
3319 w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3320 strcat(buf, dsp_buf);
3321 memset(dsp_buf, 0, sizeof(dsp_buf));
3323 size += snprintf(dsp_buf, 80,
3324 " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3325 w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3326 strcat(buf, dsp_buf);
3327 memset(dsp_buf, 0, sizeof(dsp_buf));
3329 size += snprintf(dsp_buf, 80,
3330 "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n",
3331 w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3332 lcdc_readl(lcdc_dev, WIN0_CBR_MST));
3333 strcat(buf, dsp_buf);
3334 memset(dsp_buf, 0, sizeof(dsp_buf));
3337 size += snprintf(dsp_buf, 80,
3338 "win1:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,",
3339 w1_state, format_w1, w1_vir_y, w1_vir_uv);
3340 strcat(buf, dsp_buf);
3341 memset(dsp_buf, 0, sizeof(dsp_buf));
3343 size += snprintf(dsp_buf, 80,
3344 " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n",
3345 w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3346 strcat(buf, dsp_buf);
3347 memset(dsp_buf, 0, sizeof(dsp_buf));
3349 size += snprintf(dsp_buf, 80,
3350 " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3351 w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3352 strcat(buf, dsp_buf);
3353 memset(dsp_buf, 0, sizeof(dsp_buf));
3355 size += snprintf(dsp_buf, 80,
3356 "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n",
3357 w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3358 lcdc_readl(lcdc_dev, WIN1_CBR_MST));
3359 strcat(buf, dsp_buf);
3360 memset(dsp_buf, 0, sizeof(dsp_buf));
3363 size += snprintf(dsp_buf, 80,
3364 "win2:\n state:%d\n",
3366 strcat(buf, dsp_buf);
3367 memset(dsp_buf, 0, sizeof(dsp_buf));
3369 size += snprintf(dsp_buf, 80,
3370 " area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3371 w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3372 strcat(buf, dsp_buf);
3373 memset(dsp_buf, 0, sizeof(dsp_buf));
3374 size += snprintf(dsp_buf, 80,
3375 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3376 w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3377 lcdc_readl(lcdc_dev, WIN2_MST0));
3378 strcat(buf, dsp_buf);
3379 memset(dsp_buf, 0, sizeof(dsp_buf));
3382 size += snprintf(dsp_buf, 80,
3383 " area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3384 w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3385 strcat(buf, dsp_buf);
3386 memset(dsp_buf, 0, sizeof(dsp_buf));
3387 size += snprintf(dsp_buf, 80,
3388 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3389 w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3390 lcdc_readl(lcdc_dev, WIN2_MST1));
3391 strcat(buf, dsp_buf);
3392 memset(dsp_buf, 0, sizeof(dsp_buf));
3395 size += snprintf(dsp_buf, 80,
3396 " area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3397 w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3398 strcat(buf, dsp_buf);
3399 memset(dsp_buf, 0, sizeof(dsp_buf));
3400 size += snprintf(dsp_buf, 80,
3401 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3402 w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3403 lcdc_readl(lcdc_dev, WIN2_MST2));
3404 strcat(buf, dsp_buf);
3405 memset(dsp_buf, 0, sizeof(dsp_buf));
3408 size += snprintf(dsp_buf, 80,
3409 " area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3410 w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3411 strcat(buf, dsp_buf);
3412 memset(dsp_buf, 0, sizeof(dsp_buf));
3413 size += snprintf(dsp_buf, 80,
3414 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3415 w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3416 lcdc_readl(lcdc_dev, WIN2_MST3));
3417 strcat(buf, dsp_buf);
3418 memset(dsp_buf, 0, sizeof(dsp_buf));
3421 size += snprintf(dsp_buf, 80,
3422 "win3:\n state:%d\n",
3424 strcat(buf, dsp_buf);
3425 memset(dsp_buf, 0, sizeof(dsp_buf));
3427 size += snprintf(dsp_buf, 80,
3428 " area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3429 w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
3430 strcat(buf, dsp_buf);
3431 memset(dsp_buf, 0, sizeof(dsp_buf));
3432 size += snprintf(dsp_buf, 80,
3433 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3434 w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
3435 lcdc_readl(lcdc_dev, WIN3_MST0));
3436 strcat(buf, dsp_buf);
3437 memset(dsp_buf, 0, sizeof(dsp_buf));
3440 size += snprintf(dsp_buf, 80,
3441 " area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3442 w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
3443 strcat(buf, dsp_buf);
3444 memset(dsp_buf, 0, sizeof(dsp_buf));
3445 size += snprintf(dsp_buf, 80,
3446 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3447 w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
3448 lcdc_readl(lcdc_dev, WIN3_MST1));
3449 strcat(buf, dsp_buf);
3450 memset(dsp_buf, 0, sizeof(dsp_buf));
3453 size += snprintf(dsp_buf, 80,
3454 " area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3455 w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
3456 strcat(buf, dsp_buf);
3457 memset(dsp_buf, 0, sizeof(dsp_buf));
3458 size += snprintf(dsp_buf, 80,
3459 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3460 w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
3461 lcdc_readl(lcdc_dev, WIN3_MST2));
3462 strcat(buf, dsp_buf);
3463 memset(dsp_buf, 0, sizeof(dsp_buf));
3466 size += snprintf(dsp_buf, 80,
3467 " area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3468 w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
3469 strcat(buf, dsp_buf);
3470 memset(dsp_buf, 0, sizeof(dsp_buf));
3471 size += snprintf(dsp_buf, 80,
3472 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3473 w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
3474 lcdc_readl(lcdc_dev, WIN3_MST3));
3475 strcat(buf, dsp_buf);
3476 memset(dsp_buf, 0, sizeof(dsp_buf));
3481 static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3484 struct lcdc_device *lcdc_dev =
3485 container_of(dev_drv, struct lcdc_device, driver);
3486 struct rk_screen *screen = dev_drv->cur_screen;
3491 u32 x_total, y_total;
3495 dev_info(dev_drv->dev, "unsupport set fps=0\n");
3498 ft = div_u64(1000000000000llu, fps);
3500 screen->mode.upper_margin + screen->mode.lower_margin +
3501 screen->mode.yres + screen->mode.vsync_len;
3503 screen->mode.left_margin + screen->mode.right_margin +
3504 screen->mode.xres + screen->mode.hsync_len;
3505 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3506 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3507 ret = clk_set_rate(lcdc_dev->pll_sclk, dotclk); /*set pll */
3509 dev_err(dev_drv->dev,
3510 "set lcdc%d pll_sclk failed\n", lcdc_dev->id);
3512 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3513 /*SET NEW PLL FOR RK3368 */
3516 pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3517 lcdc_dev->pixclock = pixclock;
3518 dev_drv->pixclock = lcdc_dev->pixclock;
3519 fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3520 screen->ft = 1000 / fps; /*one frame time in ms */
3523 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3524 clk_get_rate(lcdc_dev->dclk), fps);
3529 static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3531 mutex_lock(&dev_drv->fb_win_id_mutex);
3532 if (order == FB_DEFAULT_ORDER)
3533 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
3534 dev_drv->fb4_win_id = order / 10000;
3535 dev_drv->fb3_win_id = (order / 1000) % 10;
3536 dev_drv->fb2_win_id = (order / 100) % 10;
3537 dev_drv->fb1_win_id = (order / 10) % 10;
3538 dev_drv->fb0_win_id = order % 10;
3539 mutex_unlock(&dev_drv->fb_win_id_mutex);
3544 static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3549 mutex_lock(&dev_drv->fb_win_id_mutex);
3550 if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
3551 win_id = dev_drv->fb0_win_id;
3552 else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
3553 win_id = dev_drv->fb1_win_id;
3554 else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
3555 win_id = dev_drv->fb2_win_id;
3556 else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
3557 win_id = dev_drv->fb3_win_id;
3558 else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
3559 win_id = dev_drv->fb4_win_id;
3560 mutex_unlock(&dev_drv->fb_win_id_mutex);
3565 static int rk3368_set_dsp_lut(struct rk_lcdc_driver *dev_drv, int *lut)
3572 struct lcdc_device *lcdc_dev =
3573 container_of(dev_drv, struct lcdc_device, driver);
3574 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
3575 lcdc_cfg_done(lcdc_dev);
3577 if (dev_drv->cur_screen->dsp_lut) {
3578 for (i = 0; i < 256; i++) {
3579 dev_drv->cur_screen->dsp_lut[i] = lut[i];
3580 v = dev_drv->cur_screen->dsp_lut[i];
3581 c = lcdc_dev->dsp_lut_addr_base + (i << 2);
3582 b = (v & 0xff) << 2;
3583 g = (v & 0xff00) << 4;
3584 r = (v & 0xff0000) << 6;
3586 for (j = 0; j < 4; j++) {
3587 writel_relaxed(v, c);
3588 v += (1 + (1 << 10) + (1 << 20));
3593 dev_err(dev_drv->dev, "no buffer to backup lut data!\n");
3598 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
3600 lcdc_cfg_done(lcdc_dev);
3601 } while (!lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN));
3605 static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3607 struct lcdc_device *lcdc_dev =
3608 container_of(dev_drv, struct lcdc_device, driver);
3610 unsigned int mask, val;
3611 struct rk_lcdc_win *win = NULL;
3613 spin_lock(&lcdc_dev->reg_lock);
3614 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3615 v_STANDBY_EN(lcdc_dev->standby));
3616 for (i = 0; i < 4; i++) {
3617 win = dev_drv->win[i];
3618 if ((win->state == 0) && (win->last_state == 1)) {
3621 /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
3622 for rk3288 to fix hw bug? */
3625 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
3628 /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
3629 for rk3288 to fix hw bug? */
3632 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
3635 mask = m_WIN2_EN | m_WIN2_MST0_EN |
3637 m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3638 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
3640 v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3641 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
3644 mask = m_WIN3_EN | m_WIN3_MST0_EN |
3646 m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3647 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |
3649 v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3650 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
3655 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
3661 win->last_state = win->state;
3663 lcdc_cfg_done(lcdc_dev);
3664 spin_unlock(&lcdc_dev->reg_lock);
3668 static int rk3368_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3670 struct lcdc_device *lcdc_dev =
3671 container_of(dev_drv, struct lcdc_device, driver);
3672 spin_lock(&lcdc_dev->reg_lock);
3673 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3674 v_DIRECT_PATH_EN(open));
3675 lcdc_cfg_done(lcdc_dev);
3676 spin_unlock(&lcdc_dev->reg_lock);
3680 static int rk3368_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3682 struct lcdc_device *lcdc_dev = container_of(dev_drv,
3683 struct lcdc_device, driver);
3684 spin_lock(&lcdc_dev->reg_lock);
3685 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3686 v_DIRECT_PATCH_SEL(win_id));
3687 lcdc_cfg_done(lcdc_dev);
3688 spin_unlock(&lcdc_dev->reg_lock);
3692 static int rk3368_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3694 struct lcdc_device *lcdc_dev =
3695 container_of(dev_drv, struct lcdc_device, driver);
3698 spin_lock(&lcdc_dev->reg_lock);
3699 ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3700 spin_unlock(&lcdc_dev->reg_lock);
3704 static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
3707 struct lcdc_device *lcdc_dev =
3708 container_of(dev_drv, struct lcdc_device, driver);
3710 enable_irq(lcdc_dev->irq);
3712 disable_irq(lcdc_dev->irq);
3716 int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3718 struct lcdc_device *lcdc_dev =
3719 container_of(dev_drv, struct lcdc_device, driver);
3723 if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
3724 int_reg = lcdc_readl(lcdc_dev, INTR_STATUS);
3725 if (int_reg & m_LINE_FLAG0_INTR_STS) {
3726 lcdc_dev->driver.frame_time.last_framedone_t =
3727 lcdc_dev->driver.frame_time.framedone_t;
3728 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3729 lcdc_msk_reg(lcdc_dev, INTR_CLEAR,
3730 m_LINE_FLAG0_INTR_CLR,
3731 v_LINE_FLAG0_INTR_CLR(1));
3732 ret = RK_LF_STATUS_FC;
3734 ret = RK_LF_STATUS_FR;
3737 ret = RK_LF_STATUS_NC;
3743 static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3744 unsigned int *dsp_addr)
3746 struct lcdc_device *lcdc_dev =
3747 container_of(dev_drv, struct lcdc_device, driver);
3748 spin_lock(&lcdc_dev->reg_lock);
3749 if (lcdc_dev->clk_on) {
3750 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3751 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3752 dsp_addr[2] = lcdc_readl(lcdc_dev, WIN2_MST0);
3753 dsp_addr[3] = lcdc_readl(lcdc_dev, WIN3_MST0);
3755 spin_unlock(&lcdc_dev->reg_lock);
3759 static struct lcdc_cabc_mode cabc_mode[4] = {
3760 /* pixel_num,8 stage_up, stage_down */
3761 {5, 148, 20, 300}, /*mode 1 */
3762 {10, 148, 20, 300}, /*mode 2 */
3763 {15, 148, 20, 300}, /*mode 3 */
3764 {20, 148, 20, 300}, /*mode 4 */
3767 static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode)
3769 struct lcdc_device *lcdc_dev =
3770 container_of(dev_drv, struct lcdc_device, driver);
3771 struct rk_screen *screen = dev_drv->cur_screen;
3772 u32 total_pixel, calc_pixel, stage_up, stage_down;
3773 u32 pixel_num, global_su;
3774 u32 stage_up_rec, stage_down_rec, global_su_rec;
3775 u32 mask = 0, val = 0, cabc_en = 0;
3776 u32 __maybe_unused max_mode_num =
3777 sizeof(cabc_mode) / sizeof(struct lcdc_cabc_mode);
3779 dev_drv->cabc_mode = mode;
3780 #if 0/*ndef CONFIG_RK_FPGA*/
3781 /* iomux connect to vop or pwm */
3783 DBG(3, "close cabc and select rk pwm\n");
3785 writel_relaxed(val, RK_GRF_VIRT + rk3368_GRF_GPIO3C_IOMUX);
3787 } else if (mode > 0 && mode <= max_mode_num) {
3788 DBG(3, "open cabc and select vop pwm\n");
3790 writel_relaxed(val, RK_GRF_VIRT + rk3368_GRF_GPIO3C_IOMUX);
3792 } else if (mode > 0x10 && mode <= (max_mode_num + 0x10)) {
3793 DBG(3, "open cabc and select rk pwm\n");
3795 writel_relaxed(val, RK_GRF_VIRT + rk3368_GRF_GPIO3C_IOMUX);
3798 } else if (mode == 0xff) {
3799 DBG(3, "close cabc and select vop pwm\n");
3801 writel_relaxed(val, RK_GRF_VIRT + rk3368_GRF_GPIO3C_IOMUX);
3804 dev_err(lcdc_dev->dev, "invalid cabc mode value:%d", mode);
3809 spin_lock(&lcdc_dev->reg_lock);
3810 if (lcdc_dev->clk_on) {
3811 lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
3812 m_CABC_EN, v_CABC_EN(0));
3813 lcdc_cfg_done(lcdc_dev);
3815 spin_unlock(&lcdc_dev->reg_lock);
3819 total_pixel = screen->mode.xres * screen->mode.yres;
3820 pixel_num = 1000 - (cabc_mode[mode - 1].pixel_num);
3821 calc_pixel = (total_pixel * pixel_num) / 1000;
3822 stage_up = cabc_mode[mode - 1].stage_up;
3823 stage_down = cabc_mode[mode - 1].stage_down;
3824 global_su = cabc_mode[mode - 1].global_su;
3826 stage_up_rec = 256 * 256 / stage_up;
3827 stage_down_rec = 256 * 256 / stage_down;
3828 global_su_rec = 256 * 256 / global_su;
3830 spin_lock(&lcdc_dev->reg_lock);
3831 if (lcdc_dev->clk_on) {
3832 mask = m_CABC_CALC_PIXEL_NUM;
3833 val = v_CABC_CALC_PIXEL_NUM(calc_pixel);
3834 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3836 mask = m_CABC_TOTAL_PIXEL_NUM;
3837 val = v_CABC_TOTAL_PIXEL_NUM(total_pixel);
3838 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3840 mask = m_CABC_STAGE_UP | m_CABC_STAGE_UP_REC |
3841 m_CABC_GLOBAL_SU_LIMIT_EN | m_CABC_GLOBAL_SU_REC;
3842 val = v_CABC_STAGE_UP(stage_up) |
3843 v_CABC_STAGE_UP_REC(stage_up_rec) |
3844 v_CABC_GLOBAL_SU_LIMIT_EN(1) |
3845 v_CABC_GLOBAL_SU_REC(global_su_rec);
3846 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
3848 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_DOWN_REC |
3850 val = v_CABC_STAGE_DOWN(stage_down) |
3851 v_CABC_STAGE_DOWN_REC(stage_down_rec) |
3852 v_CABC_GLOBAL_SU(global_su);
3853 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
3854 lcdc_cfg_done(lcdc_dev);
3856 spin_unlock(&lcdc_dev->reg_lock);
3863 sin_hue = sin(a)*256 +0x100;
3864 cos_hue = cos(a)*256;
3866 sin_hue = sin(a)*256;
3867 cos_hue = cos(a)*256;
3869 static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3872 struct lcdc_device *lcdc_dev =
3873 container_of(dev_drv, struct lcdc_device, driver);
3876 spin_lock(&lcdc_dev->reg_lock);
3877 if (lcdc_dev->clk_on) {
3878 val = lcdc_readl(lcdc_dev, BCSH_H);
3881 val &= m_BCSH_SIN_HUE;
3884 val &= m_BCSH_COS_HUE;
3891 spin_unlock(&lcdc_dev->reg_lock);
3896 static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3897 int sin_hue, int cos_hue)
3899 struct lcdc_device *lcdc_dev =
3900 container_of(dev_drv, struct lcdc_device, driver);
3903 spin_lock(&lcdc_dev->reg_lock);
3904 if (lcdc_dev->clk_on) {
3905 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
3906 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
3907 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
3908 lcdc_cfg_done(lcdc_dev);
3910 spin_unlock(&lcdc_dev->reg_lock);
3915 static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
3916 bcsh_bcs_mode mode, int value)
3918 struct lcdc_device *lcdc_dev =
3919 container_of(dev_drv, struct lcdc_device, driver);
3922 spin_lock(&lcdc_dev->reg_lock);
3923 if (lcdc_dev->clk_on) {
3926 /*from 0 to 255,typical is 128 */
3929 else if (value >= 0x80)
3930 value = value - 0x80;
3931 mask = m_BCSH_BRIGHTNESS;
3932 val = v_BCSH_BRIGHTNESS(value);
3935 /*from 0 to 510,typical is 256 */
3936 mask = m_BCSH_CONTRAST;
3937 val = v_BCSH_CONTRAST(value);
3940 /*from 0 to 1015,typical is 256 */
3941 mask = m_BCSH_SAT_CON;
3942 val = v_BCSH_SAT_CON(value);
3947 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
3948 lcdc_cfg_done(lcdc_dev);
3950 spin_unlock(&lcdc_dev->reg_lock);
3954 static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
3957 struct lcdc_device *lcdc_dev =
3958 container_of(dev_drv, struct lcdc_device, driver);
3961 spin_lock(&lcdc_dev->reg_lock);
3962 if (lcdc_dev->clk_on) {
3963 val = lcdc_readl(lcdc_dev, BCSH_BCS);
3966 val &= m_BCSH_BRIGHTNESS;
3973 val &= m_BCSH_CONTRAST;
3977 val &= m_BCSH_SAT_CON;
3984 spin_unlock(&lcdc_dev->reg_lock);
3988 static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
3990 struct lcdc_device *lcdc_dev =
3991 container_of(dev_drv, struct lcdc_device, driver);
3994 spin_lock(&lcdc_dev->reg_lock);
3995 if (lcdc_dev->clk_on) {
3996 rk3368_lcdc_bcsh_path_sel(dev_drv);
3998 lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1);
3999 lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
4000 lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
4004 lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
4006 lcdc_cfg_done(lcdc_dev);
4008 spin_unlock(&lcdc_dev->reg_lock);
4012 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4014 if (!enable || !dev_drv->bcsh.enable) {
4015 rk3368_lcdc_open_bcsh(dev_drv, false);
4019 if (dev_drv->bcsh.brightness <= 255 ||
4020 dev_drv->bcsh.contrast <= 510 ||
4021 dev_drv->bcsh.sat_con <= 1015 ||
4022 (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4023 rk3368_lcdc_open_bcsh(dev_drv, true);
4024 if (dev_drv->bcsh.brightness <= 255)
4025 rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4026 dev_drv->bcsh.brightness);
4027 if (dev_drv->bcsh.contrast <= 510)
4028 rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
4029 dev_drv->bcsh.contrast);
4030 if (dev_drv->bcsh.sat_con <= 1015)
4031 rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
4032 dev_drv->bcsh.sat_con);
4033 if (dev_drv->bcsh.sin_hue <= 511 &&
4034 dev_drv->bcsh.cos_hue <= 511)
4035 rk3368_lcdc_set_bcsh_hue(dev_drv,
4036 dev_drv->bcsh.sin_hue,
4037 dev_drv->bcsh.cos_hue);
4042 static int rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4044 struct lcdc_device *lcdc_dev =
4045 container_of(dev_drv, struct lcdc_device, driver);
4047 rk3368_lcdc_get_backlight_device(dev_drv);
4050 /* close the backlight */
4051 if (lcdc_dev->backlight) {
4052 lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4053 backlight_update_status(lcdc_dev->backlight);
4056 spin_lock(&lcdc_dev->reg_lock);
4057 if (likely(lcdc_dev->clk_on)) {
4058 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4060 lcdc_cfg_done(lcdc_dev);
4062 spin_unlock(&lcdc_dev->reg_lock);
4064 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4065 dev_drv->trsm_ops->disable();
4068 spin_lock(&lcdc_dev->reg_lock);
4069 if (likely(lcdc_dev->clk_on)) {
4070 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4073 lcdc_cfg_done(lcdc_dev);
4075 spin_unlock(&lcdc_dev->reg_lock);
4077 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4078 dev_drv->trsm_ops->enable();
4080 /* open the backlight */
4081 if (lcdc_dev->backlight) {
4082 lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
4083 backlight_update_status(lcdc_dev->backlight);
4090 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4091 .open = rk3368_lcdc_open,
4092 .win_direct_en = rk3368_lcdc_win_direct_en,
4093 .load_screen = rk3368_load_screen,
4094 .set_par = rk3368_lcdc_set_par,
4095 .pan_display = rk3368_lcdc_pan_display,
4096 .direct_set_addr = rk3368_lcdc_direct_set_win_addr,
4097 /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/
4098 .blank = rk3368_lcdc_blank,
4099 .ioctl = rk3368_lcdc_ioctl,
4100 .suspend = rk3368_lcdc_early_suspend,
4101 .resume = rk3368_lcdc_early_resume,
4102 .get_win_state = rk3368_lcdc_get_win_state,
4103 .ovl_mgr = rk3368_lcdc_ovl_mgr,
4104 .get_disp_info = rk3368_lcdc_get_disp_info,
4105 .fps_mgr = rk3368_lcdc_fps_mgr,
4106 .fb_get_win_id = rk3368_lcdc_get_win_id,
4107 .fb_win_remap = rk3368_fb_win_remap,
4108 .set_dsp_lut = rk3368_set_dsp_lut,
4109 .poll_vblank = rk3368_lcdc_poll_vblank,
4110 .dpi_open = rk3368_lcdc_dpi_open,
4111 .dpi_win_sel = rk3368_lcdc_dpi_win_sel,
4112 .dpi_status = rk3368_lcdc_dpi_status,
4113 .get_dsp_addr = rk3368_lcdc_get_dsp_addr,
4114 .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc,
4115 .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue,
4116 .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs,
4117 .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue,
4118 .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs,
4119 .open_bcsh = rk3368_lcdc_open_bcsh,
4120 .dump_reg = rk3368_lcdc_reg_dump,
4121 .cfg_done = rk3368_lcdc_config_done,
4122 .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu,
4123 .dsp_black = rk3368_lcdc_dsp_black,
4124 .mmu_en = rk3368_lcdc_mmu_en,
4127 #ifdef LCDC_IRQ_EMPTY_DEBUG
4128 static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev,
4129 unsigned int intr_status)
4131 if (intr_status & m_WIN0_EMPTY_INTR_STS) {
4132 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN0_EMPTY_INTR_CLR,
4133 v_WIN0_EMPTY_INTR_CLR(1));
4134 dev_warn(lcdc_dev->dev, "win0 empty irq!");
4135 } else if (intr_status & m_WIN1_EMPTY_INTR_STS) {
4136 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN1_EMPTY_INTR_CLR,
4137 v_WIN1_EMPTY_INTR_CLR(1));
4138 dev_warn(lcdc_dev->dev, "win1 empty irq!");
4139 } else if (intr_status & m_WIN2_EMPTY_INTR_STS) {
4140 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN2_EMPTY_INTR_CLR,
4141 v_WIN2_EMPTY_INTR_CLR(1));
4142 dev_warn(lcdc_dev->dev, "win2 empty irq!");
4143 } else if (intr_status & m_WIN3_EMPTY_INTR_STS) {
4144 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN3_EMPTY_INTR_CLR,
4145 v_WIN3_EMPTY_INTR_CLR(1));
4146 dev_warn(lcdc_dev->dev, "win3 empty irq!");
4147 } else if (intr_status & m_HWC_EMPTY_INTR_STS) {
4148 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_HWC_EMPTY_INTR_CLR,
4149 v_HWC_EMPTY_INTR_CLR(1));
4150 dev_warn(lcdc_dev->dev, "HWC empty irq!");
4151 } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) {
4152 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_POST_BUF_EMPTY_INTR_CLR,
4153 v_POST_BUF_EMPTY_INTR_CLR(1));
4154 dev_warn(lcdc_dev->dev, "post buf empty irq!");
4155 } else if (intr_status & m_PWM_GEN_INTR_STS) {
4156 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_PWM_GEN_INTR_CLR,
4157 v_PWM_GEN_INTR_CLR(1));
4158 dev_warn(lcdc_dev->dev, "PWM gen irq!");
4164 static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id)
4166 struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
4167 ktime_t timestamp = ktime_get();
4170 intr_status = lcdc_readl(lcdc_dev, INTR_STATUS);
4172 if (intr_status & m_FS_INTR_STS) {
4173 timestamp = ktime_get();
4174 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_INTR_CLR,
4176 /*if(lcdc_dev->driver.wait_fs){ */
4178 spin_lock(&(lcdc_dev->driver.cpl_lock));
4179 complete(&(lcdc_dev->driver.frame_done));
4180 spin_unlock(&(lcdc_dev->driver.cpl_lock));
4182 #ifdef CONFIG_DRM_ROCKCHIP
4183 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
4185 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4186 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
4188 } else if (intr_status & m_LINE_FLAG0_INTR_STS) {
4189 lcdc_dev->driver.frame_time.last_framedone_t =
4190 lcdc_dev->driver.frame_time.framedone_t;
4191 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4192 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG0_INTR_CLR,
4193 v_LINE_FLAG0_INTR_CLR(1));
4194 } else if (intr_status & m_LINE_FLAG1_INTR_STS) {
4196 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG1_INTR_CLR,
4197 v_LINE_FLAG1_INTR_CLR(1));
4198 } else if (intr_status & m_FS_NEW_INTR_STS) {
4199 /*new frame start */
4200 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_NEW_INTR_CLR,
4201 v_FS_NEW_INTR_CLR(1));
4202 } else if (intr_status & m_BUS_ERROR_INTR_STS) {
4203 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_BUS_ERROR_INTR_CLR,
4204 v_BUS_ERROR_INTR_CLR(1));
4205 dev_warn(lcdc_dev->dev, "bus error!");
4208 /* for win empty debug */
4209 #ifdef LCDC_IRQ_EMPTY_DEBUG
4210 rk3368_lcdc_parse_irq(lcdc_dev, intr_status);
4215 #if defined(CONFIG_PM)
4216 static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
4221 static int rk3368_lcdc_resume(struct platform_device *pdev)
4226 #define rk3368_lcdc_suspend NULL
4227 #define rk3368_lcdc_resume NULL
4230 static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4232 struct device_node *np = lcdc_dev->dev->of_node;
4233 struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4236 if (of_property_read_u32(np, "rockchip,prop", &val))
4237 lcdc_dev->prop = PRMRY; /*default set it as primary */
4239 lcdc_dev->prop = val;
4241 if (of_property_read_u32(np, "rockchip,mirror", &val))
4242 dev_drv->rotate_mode = NO_MIRROR;
4244 dev_drv->rotate_mode = val;
4246 if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4247 dev_drv->cabc_mode = 0; /* default set close cabc */
4249 dev_drv->cabc_mode = val;
4251 if (of_property_read_u32(np, "rockchip,pwr18", &val))
4252 /*default set it as 3.xv power supply */
4253 lcdc_dev->pwr18 = false;
4255 lcdc_dev->pwr18 = (val ? true : false);
4257 if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4258 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4260 dev_drv->fb_win_map = val;
4262 if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4263 dev_drv->bcsh.enable = false;
4265 dev_drv->bcsh.enable = (val ? true : false);
4267 if (of_property_read_u32(np, "rockchip,brightness", &val))
4268 dev_drv->bcsh.brightness = 0xffff;
4270 dev_drv->bcsh.brightness = val;
4272 if (of_property_read_u32(np, "rockchip,contrast", &val))
4273 dev_drv->bcsh.contrast = 0xffff;
4275 dev_drv->bcsh.contrast = val;
4277 if (of_property_read_u32(np, "rockchip,sat-con", &val))
4278 dev_drv->bcsh.sat_con = 0xffff;
4280 dev_drv->bcsh.sat_con = val;
4282 if (of_property_read_u32(np, "rockchip,hue", &val)) {
4283 dev_drv->bcsh.sin_hue = 0xffff;
4284 dev_drv->bcsh.cos_hue = 0xffff;
4286 dev_drv->bcsh.sin_hue = val & 0xff;
4287 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4290 #if defined(CONFIG_ROCKCHIP_IOMMU)
4291 if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4292 dev_drv->iommu_enabled = 0;
4294 dev_drv->iommu_enabled = val;
4296 dev_drv->iommu_enabled = 0;
4301 static int rk3368_lcdc_probe(struct platform_device *pdev)
4303 struct lcdc_device *lcdc_dev = NULL;
4304 struct rk_lcdc_driver *dev_drv;
4305 struct device *dev = &pdev->dev;
4306 struct resource *res;
4307 struct device_node *np = pdev->dev.of_node;
4311 /*if the primary lcdc has not registered ,the extend
4312 lcdc register later */
4313 of_property_read_u32(np, "rockchip,prop", &prop);
4314 if (prop == EXTEND) {
4315 if (!is_prmry_rk_lcdc_registered())
4316 return -EPROBE_DEFER;
4318 lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
4320 dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!");
4323 platform_set_drvdata(pdev, lcdc_dev);
4324 lcdc_dev->dev = dev;
4325 rk3368_lcdc_parse_dt(lcdc_dev);
4326 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4327 lcdc_dev->reg_phy_base = res->start;
4328 lcdc_dev->len = resource_size(res);
4329 lcdc_dev->regs = devm_ioremap_resource(dev, res);
4330 if (IS_ERR(lcdc_dev->regs))
4331 return PTR_ERR(lcdc_dev->regs);
4333 dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs);
4335 lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4336 if (IS_ERR(lcdc_dev->regsbak))
4337 return PTR_ERR(lcdc_dev->regsbak);
4338 lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4340 dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4341 dev_drv = &lcdc_dev->driver;
4343 dev_drv->prop = prop;
4344 dev_drv->id = lcdc_dev->id;
4345 dev_drv->ops = &lcdc_drv_ops;
4346 dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4347 spin_lock_init(&lcdc_dev->reg_lock);
4349 lcdc_dev->irq = platform_get_irq(pdev, 0);
4350 if (lcdc_dev->irq < 0) {
4351 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4356 ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr,
4357 IRQF_DISABLED | IRQF_SHARED,
4358 dev_name(dev), lcdc_dev);
4360 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4361 lcdc_dev->irq, ret);
4365 if (dev_drv->iommu_enabled) {
4366 if (lcdc_dev->id == 0) {
4367 strcpy(dev_drv->mmu_dts_name,
4368 VOPB_IOMMU_COMPATIBLE_NAME);
4370 strcpy(dev_drv->mmu_dts_name,
4371 VOPL_IOMMU_COMPATIBLE_NAME);
4375 ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4377 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4380 lcdc_dev->screen = dev_drv->screen0;
4381 dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4382 lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4387 static int rk3368_lcdc_remove(struct platform_device *pdev)
4392 static void rk3368_lcdc_shutdown(struct platform_device *pdev)
4394 struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
4396 rk3368_lcdc_deint(lcdc_dev);
4397 rk_disp_pwr_disable(&lcdc_dev->driver);
4400 #if defined(CONFIG_OF)
4401 static const struct of_device_id rk3368_lcdc_dt_ids[] = {
4402 {.compatible = "rockchip,rk3368-lcdc",},
4407 static struct platform_driver rk3368_lcdc_driver = {
4408 .probe = rk3368_lcdc_probe,
4409 .remove = rk3368_lcdc_remove,
4411 .name = "rk3368-lcdc",
4412 .owner = THIS_MODULE,
4413 .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids),
4415 .suspend = rk3368_lcdc_suspend,
4416 .resume = rk3368_lcdc_resume,
4417 .shutdown = rk3368_lcdc_shutdown,
4420 static int __init rk3368_lcdc_module_init(void)
4422 return platform_driver_register(&rk3368_lcdc_driver);
4425 static void __exit rk3368_lcdc_module_exit(void)
4427 platform_driver_unregister(&rk3368_lcdc_driver);
4430 fs_initcall(rk3368_lcdc_module_init);
4431 module_exit(rk3368_lcdc_module_exit);