drivers/video/rockchip/lcdc/rk3368_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3368_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *Author:hjc<hjc@rock-chips.com>
   6  *This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk3368_lcdc.h"
  39
  40 #if defined(CONFIG_HAS_EARLYSUSPEND)
  41 #include <linux/earlysuspend.h>
  42 #endif
  43 /*#define CONFIG_RK_FPGA 1*/
  44
  45 static int dbg_thresd;
  46 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  47
  48 #define DBG(level, x...) do {                   \
  49         if (unlikely(dbg_thresd >= level))      \
  50                 pr_info(x);\
  51         } while (0)
  52
  53 static struct rk_lcdc_win lcdc_win[] = {
  54         [0] = {
  55                .name = "win0",
  56                .id = 0,
  57                .support_3d = false,
  58                },
  59         [1] = {
  60                .name = "win1",
  61                .id = 1,
  62                .support_3d = false,
  63                },
  64         [2] = {
  65                .name = "win2",
  66                .id = 2,
  67                .support_3d = false,
  68                },
  69         [3] = {
  70                .name = "win3",
  71                .id = 3,
  72                .support_3d = false,
  73                },
  74         [4] = {
  75                .name = "hwc",
  76                .id = 4,
  77                .support_3d = false,
  78                }
  79 };
  80
  81 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
  82
  83 /*#define WAIT_FOR_SYNC 1*/
  84 u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth)
  85 {
  86         u32 vscalednmult;
  87
  88         if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  89                 vscalednmult = 4;
  90         else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  91                 vscalednmult = 2;
  92         else
  93                 vscalednmult = 1;
  94
  95         return vscalednmult;
  96 }
  97
  98
  99 static int rk3368_set_cabc_lut(struct rk_lcdc_driver *dev_drv, int *cabc_lut)
 100 {
 101         int i;
 102         int __iomem *c;
 103         u32 v;
 104         struct lcdc_device *lcdc_dev =
 105             container_of(dev_drv, struct lcdc_device, driver);
 106
 107         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 108                      v_CABC_LUT_EN(0));
 109         lcdc_cfg_done(lcdc_dev);
 110         mdelay(25);
 111         for (i = 0; i < 256; i++) {
 112                 v = cabc_lut[i];
 113                 c = lcdc_dev->cabc_lut_addr_base + i;
 114                 writel_relaxed(v, c);
 115         }
 116         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 117                      v_CABC_LUT_EN(1));
 118         return 0;
 119 }
 120
 121
 122 static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
 123 {
 124         int i;
 125         int __iomem *c;
 126         u32 v;
 127         struct lcdc_device *lcdc_dev =
 128             container_of(dev_drv, struct lcdc_device, driver);
 129
 130         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 131                      v_DSP_LUT_EN(0));
 132         lcdc_cfg_done(lcdc_dev);
 133         mdelay(25);
 134         for (i = 0; i < 256; i++) {
 135                 v = dsp_lut[i];
 136                 c = lcdc_dev->dsp_lut_addr_base + i;
 137                 writel_relaxed(v, c);
 138         }
 139         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 140                      v_DSP_LUT_EN(1));
 141
 142         return 0;
 143 }
 144
 145 static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 146 {
 147 #ifdef CONFIG_RK_FPGA
 148         lcdc_dev->clk_on = 1;
 149         return 0;
 150 #endif
 151         if (!lcdc_dev->clk_on) {
 152                 clk_prepare_enable(lcdc_dev->hclk);
 153                 clk_prepare_enable(lcdc_dev->dclk);
 154                 clk_prepare_enable(lcdc_dev->aclk);
 155                 /*clk_prepare_enable(lcdc_dev->pd);*/
 156                 spin_lock(&lcdc_dev->reg_lock);
 157                 lcdc_dev->clk_on = 1;
 158                 spin_unlock(&lcdc_dev->reg_lock);
 159         }
 160
 161         return 0;
 162 }
 163
 164 static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 165 {
 166 #ifdef CONFIG_RK_FPGA
 167         lcdc_dev->clk_on = 0;
 168         return 0;
 169 #endif
 170         if (lcdc_dev->clk_on) {
 171                 spin_lock(&lcdc_dev->reg_lock);
 172                 lcdc_dev->clk_on = 0;
 173                 spin_unlock(&lcdc_dev->reg_lock);
 174                 mdelay(25);
 175                 clk_disable_unprepare(lcdc_dev->dclk);
 176                 clk_disable_unprepare(lcdc_dev->hclk);
 177                 clk_disable_unprepare(lcdc_dev->aclk);
 178                 /*clk_disable_unprepare(lcdc_dev->pd);*/
 179         }
 180
 181         return 0;
 182 }
 183
 184 static int __maybe_unused
 185         rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 186 {
 187         u32 mask, val;
 188
 189         spin_lock(&lcdc_dev->reg_lock);
 190         if (likely(lcdc_dev->clk_on)) {
 191                 mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN |
 192                     m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN |
 193                     m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN |
 194                     m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
 195                     m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
 196                     m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
 197                     m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN;
 198                 val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) |
 199                     v_ADDR_SAME_INTR_EN(0) |
 200                     v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) |
 201                     v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) |
 202                     v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) |
 203                     v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) |
 204                     v_POST_BUF_EMPTY_INTR_EN(0) |
 205                     v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0);
 206                 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
 207
 208                 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR |
 209                     m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
 210                     m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR |
 211                     m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
 212                     m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
 213                     m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
 214                     m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR;
 215                 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
 216                     v_ADDR_SAME_INTR_CLR(1) |
 217                     v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) |
 218                     v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) |
 219                     v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) |
 220                     v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) |
 221                     v_POST_BUF_EMPTY_INTR_CLR(1) |
 222                     v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1);
 223                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
 224                 lcdc_cfg_done(lcdc_dev);
 225                 spin_unlock(&lcdc_dev->reg_lock);
 226         } else {
 227                 spin_unlock(&lcdc_dev->reg_lock);
 228         }
 229         mdelay(1);
 230         return 0;
 231 }
 232
 233 static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
 234 {
 235         struct lcdc_device *lcdc_dev =
 236             container_of(dev_drv, struct lcdc_device, driver);
 237         int *cbase = (int *)lcdc_dev->regs;
 238         int *regsbak = (int *)lcdc_dev->regsbak;
 239         int i, j, val;
 240         char dbg_message[30];
 241         char buf[10];
 242
 243         pr_info("lcd back up reg:\n");
 244         memset(dbg_message, 0, sizeof(dbg_message));
 245         memset(buf, 0, sizeof(buf));
 246         for (i = 0; i <= (0x200 >> 4); i++) {
 247                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 248                 for (j = 0; j < 4; j++) {
 249                         val = sprintf(buf, "%08x  ", *(regsbak + i * 4 + j));
 250                         strcat(dbg_message, buf);
 251                 }
 252                 pr_info("%s\n", dbg_message);
 253                 memset(dbg_message, 0, sizeof(dbg_message));
 254                 memset(buf, 0, sizeof(buf));
 255         }
 256
 257         pr_info("lcdc reg:\n");
 258         for (i = 0; i <= (0x200 >> 4); i++) {
 259                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 260                 for (j = 0; j < 4; j++) {
 261                         sprintf(buf, "%08x  ",
 262                                 readl_relaxed(cbase + i * 4 + j));
 263                         strcat(dbg_message, buf);
 264                 }
 265                 pr_info("%s\n", dbg_message);
 266                 memset(dbg_message, 0, sizeof(dbg_message));
 267                 memset(buf, 0, sizeof(buf));
 268         }
 269
 270         return 0;
 271 }
 272
 273 #define WIN_EN(id)              \
 274 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en)       \
 275 { \
 276         u32 msk, val;                                                   \
 277         spin_lock(&lcdc_dev->reg_lock);                                 \
 278         msk =  m_WIN##id##_EN;                                          \
 279         val  =  v_WIN##id##_EN(en);                                     \
 280         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);              \
 281         lcdc_cfg_done(lcdc_dev);                                        \
 282         val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);            \
 283         while (val !=  (!!en))  {                                       \
 284                 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);    \
 285         }                                                               \
 286         spin_unlock(&lcdc_dev->reg_lock);                               \
 287         return 0;                                                       \
 288 }
 289
 290 WIN_EN(0);
 291 WIN_EN(1);
 292 WIN_EN(2);
 293 WIN_EN(3);
 294 /*enable/disable win directly*/
 295 static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv,
 296                                      int win_id, int en)
 297 {
 298         struct lcdc_device *lcdc_dev =
 299             container_of(drv, struct lcdc_device, driver);
 300         if (win_id == 0)
 301                 win0_enable(lcdc_dev, en);
 302         else if (win_id == 1)
 303                 win1_enable(lcdc_dev, en);
 304         else if (win_id == 2)
 305                 win2_enable(lcdc_dev, en);
 306         else if (win_id == 3)
 307                 win3_enable(lcdc_dev, en);
 308         else
 309                 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
 310         return 0;
 311 }
 312
 313 #define SET_WIN_ADDR(id) \
 314 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
 315 {                                                       \
 316         u32 msk, val;                                   \
 317         spin_lock(&lcdc_dev->reg_lock);                 \
 318         lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr);        \
 319         msk =  m_WIN##id##_EN;                          \
 320         val  =  v_WIN0_EN(1);                           \
 321         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);      \
 322         lcdc_cfg_done(lcdc_dev);                        \
 323         spin_unlock(&lcdc_dev->reg_lock);               \
 324         return 0;                                       \
 325 }
 326
 327 SET_WIN_ADDR(0);
 328 SET_WIN_ADDR(1);
 329 int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
 330                                     int win_id, u32 addr)
 331 {
 332         struct lcdc_device *lcdc_dev =
 333             container_of(dev_drv, struct lcdc_device, driver);
 334         if (win_id == 0)
 335                 set_win0_addr(lcdc_dev, addr);
 336         else
 337                 set_win1_addr(lcdc_dev, addr);
 338
 339         return 0;
 340 }
 341
 342 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 343 {
 344         int reg = 0;
 345         u32 val = 0;
 346         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 347         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 348         u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 349         u32 st_x, st_y;
 350         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 351
 352         spin_lock(&lcdc_dev->reg_lock);
 353         for (reg = 0; reg < SCAN_LINE_NUM; reg += 4) {
 354                 val = lcdc_readl_backup(lcdc_dev, reg);
 355                 switch (reg) {
 356                 case WIN0_ACT_INFO:
 357                         win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1;
 358                         win0->area[0].yact =
 359                             ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
 360                         break;
 361                 case WIN0_DSP_INFO:
 362                         win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1;
 363                         win0->area[0].ysize =
 364                             ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
 365                         break;
 366                 case WIN0_DSP_ST:
 367                         st_x = val & m_WIN0_DSP_XST;
 368                         st_y = (val & m_WIN0_DSP_YST) >> 16;
 369                         win0->area[0].xpos = st_x - h_pw_bp;
 370                         win0->area[0].ypos = st_y - v_pw_bp;
 371                         break;
 372                 case WIN0_CTRL0:
 373                         win0->state = val & m_WIN0_EN;
 374                         win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1;
 375                         win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
 376                         win0->area[0].format = win0->area[0].fmt_cfg;
 377                         break;
 378                 case WIN0_VIR:
 379                         win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE;
 380                         win0->area[0].uv_vir_stride =
 381                             (val & m_WIN0_VIR_STRIDE_UV) >> 16;
 382                         if (win0->area[0].format == ARGB888)
 383                                 win0->area[0].xvir = win0->area[0].y_vir_stride;
 384                         else if (win0->area[0].format == RGB888)
 385                                 win0->area[0].xvir =
 386                                     win0->area[0].y_vir_stride * 4 / 3;
 387                         else if (win0->area[0].format == RGB565)
 388                                 win0->area[0].xvir =
 389                                     2 * win0->area[0].y_vir_stride;
 390                         else    /* YUV */
 391                                 win0->area[0].xvir =
 392                                     4 * win0->area[0].y_vir_stride;
 393                         break;
 394                 case WIN0_YRGB_MST:
 395                         win0->area[0].smem_start = val;
 396                         break;
 397                 case WIN0_CBR_MST:
 398                         win0->area[0].cbr_start = val;
 399                         break;
 400                 default:
 401                         break;
 402                 }
 403         }
 404         spin_unlock(&lcdc_dev->reg_lock);
 405 }
 406
 407 /********do basic init*********/
 408 static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 409 {
 410         u32 mask, val, v;
 411         struct lcdc_device *lcdc_dev =
 412             container_of(dev_drv, struct lcdc_device, driver);
 413         if (lcdc_dev->pre_init)
 414                 return 0;
 415
 416         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 417         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 418         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 419         /*lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");*/
 420
 421         if (/*IS_ERR(lcdc_dev->pd) || */(IS_ERR(lcdc_dev->aclk)) ||
 422             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 423                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 424                         lcdc_dev->id);
 425         }
 426
 427         rk_disp_pwr_enable(dev_drv);
 428         rk3368_lcdc_clk_enable(lcdc_dev);
 429
 430         /*backup reg config at uboot */
 431         lcdc_read_reg_defalut_cfg(lcdc_dev);
 432         if (lcdc_dev->pwr18 == 1) {
 433                 v = 0x00200020; /*bit5: 1,1.8v;0,3.3v*/
 434                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 435                                 PMUGRF_SOC_CON0_VOP, v);
 436         } else {
 437                 v = 0x00200000; /*bit5: 1,1.8v;0,3.3v*/
 438                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 439                                 PMUGRF_SOC_CON0_VOP, v);
 440         }
 441         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_0, 0x15110903);
 442         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_1, 0x00030911);
 443         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_0, 0x1a150b04);
 444         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_1, 0x00040b15);
 445         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_0, 0x15110903);
 446         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_1, 0x00030911);
 447
 448         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 449         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 450         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696);
 451         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969);
 452         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 453         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 454
 455         mask = m_AUTO_GATING_EN;
 456         val = v_AUTO_GATING_EN(0);
 457         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 458         lcdc_cfg_done(lcdc_dev);
 459         /*disable win0 to workaround iommu pagefault */
 460         /*if (dev_drv->iommu_enabled) */
 461         /*      win0_enable(lcdc_dev, 0); */
 462         lcdc_dev->pre_init = true;
 463
 464         return 0;
 465 }
 466
 467 static void rk3368_lcdc_deint(struct lcdc_device *lcdc_dev)
 468 {
 469 }
 470
 471 static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
 472 {
 473         struct lcdc_device *lcdc_dev =
 474             container_of(dev_drv, struct lcdc_device, driver);
 475         struct rk_screen *screen = dev_drv->cur_screen;
 476         u16 x_res = screen->mode.xres;
 477         u16 y_res = screen->mode.yres;
 478         u32 mask, val;
 479         u16 h_total, v_total;
 480         u16 post_hsd_en, post_vsd_en;
 481         u16 post_dsp_hact_st, post_dsp_hact_end;
 482         u16 post_dsp_vact_st, post_dsp_vact_end;
 483         u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
 484         u16 post_h_fac, post_v_fac;
 485
 486         screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200;
 487         screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200;
 488         screen->post_xsize = x_res *
 489             (dev_drv->overscan.left + dev_drv->overscan.right) / 200;
 490         screen->post_ysize = y_res *
 491             (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200;
 492
 493         h_total = screen->mode.hsync_len + screen->mode.left_margin +
 494             x_res + screen->mode.right_margin;
 495         v_total = screen->mode.vsync_len + screen->mode.upper_margin +
 496             y_res + screen->mode.lower_margin;
 497
 498         if (screen->post_dsp_stx + screen->post_xsize > x_res) {
 499                 dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
 500                          screen->post_dsp_stx, screen->post_xsize, x_res);
 501                 screen->post_dsp_stx = x_res - screen->post_xsize;
 502         }
 503         if (screen->x_mirror == 0) {
 504                 post_dsp_hact_st = screen->post_dsp_stx +
 505                     screen->mode.hsync_len + screen->mode.left_margin;
 506                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 507         } else {
 508                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 509                     screen->post_dsp_stx;
 510                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 511         }
 512         if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
 513                 post_hsd_en = 1;
 514                 post_h_fac =
 515                     GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
 516         } else {
 517                 post_hsd_en = 0;
 518                 post_h_fac = 0x1000;
 519         }
 520
 521         if (screen->post_dsp_sty + screen->post_ysize > y_res) {
 522                 dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
 523                          screen->post_dsp_sty, screen->post_ysize, y_res);
 524                 screen->post_dsp_sty = y_res - screen->post_ysize;
 525         }
 526
 527         if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
 528                 post_vsd_en = 1;
 529                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
 530                                                       screen->post_ysize);
 531         } else {
 532                 post_vsd_en = 0;
 533                 post_v_fac = 0x1000;
 534         }
 535
 536         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
 537                 post_dsp_vact_st = screen->post_dsp_sty / 2 +
 538                                         screen->mode.vsync_len +
 539                                         screen->mode.upper_margin;
 540                 post_dsp_vact_end = post_dsp_vact_st +
 541                                         screen->post_ysize / 2;
 542
 543                 post_dsp_vact_st_f1 = screen->mode.vsync_len +
 544                                       screen->mode.upper_margin +
 545                                       y_res/2 +
 546                                       screen->mode.lower_margin +
 547                                       screen->mode.vsync_len +
 548                                       screen->mode.upper_margin +
 549                                       screen->post_dsp_sty / 2 +
 550                                       1;
 551                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
 552                                         screen->post_ysize/2;
 553         } else {
 554                 if (screen->y_mirror == 0) {
 555                         post_dsp_vact_st = screen->post_dsp_sty +
 556                             screen->mode.vsync_len +
 557                             screen->mode.upper_margin;
 558                         post_dsp_vact_end = post_dsp_vact_st +
 559                                 screen->post_ysize;
 560                 } else {
 561                         post_dsp_vact_end = v_total -
 562                                 screen->mode.lower_margin -
 563                             screen->post_dsp_sty;
 564                         post_dsp_vact_st = post_dsp_vact_end -
 565                                 screen->post_ysize;
 566                 }
 567                 post_dsp_vact_st_f1 = 0;
 568                 post_dsp_vact_end_f1 = 0;
 569         }
 570         DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
 571             screen->post_xsize, screen->post_ysize, screen->xpos);
 572         DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 573             screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
 574         mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
 575         val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
 576             v_DSP_HACT_ST_POST(post_dsp_hact_st);
 577         lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
 578
 579         mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
 580         val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
 581             v_DSP_VACT_ST_POST(post_dsp_vact_st);
 582         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
 583
 584         mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
 585         val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
 586             v_POST_VS_FACTOR_YRGB(post_v_fac);
 587         lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
 588
 589         mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
 590         val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
 591             v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
 592         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
 593
 594         mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
 595         val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
 596         lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
 597         return 0;
 598 }
 599
 600 static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 601 {
 602         struct lcdc_device *lcdc_dev =
 603             container_of(dev_drv, struct lcdc_device, driver);
 604         struct rk_lcdc_win *win;
 605         u32 colorkey_r, colorkey_g, colorkey_b;
 606         int i, key_val;
 607
 608         for (i = 0; i < 4; i++) {
 609                 win = dev_drv->win[i];
 610                 key_val = win->color_key_val;
 611                 colorkey_r = (key_val & 0xff) << 2;
 612                 colorkey_g = ((key_val >> 8) & 0xff) << 12;
 613                 colorkey_b = ((key_val >> 16) & 0xff) << 22;
 614                 /*color key dither 565/888->aaa */
 615                 key_val = colorkey_r | colorkey_g | colorkey_b;
 616                 switch (i) {
 617                 case 0:
 618                         lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
 619                         break;
 620                 case 1:
 621                         lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
 622                         break;
 623                 case 2:
 624                         lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
 625                         break;
 626                 case 3:
 627                         lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
 628                         break;
 629                 default:
 630                         pr_info("%s:un support win num:%d\n",
 631                                 __func__, i);
 632                         break;
 633                 }
 634         }
 635         return 0;
 636 }
 637
 638 static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
 639 {
 640         struct lcdc_device *lcdc_dev =
 641             container_of(dev_drv, struct lcdc_device, driver);
 642         struct rk_lcdc_win *win = dev_drv->win[win_id];
 643         struct alpha_config alpha_config;
 644         u32 mask, val;
 645         int ppixel_alpha = 0, global_alpha = 0, i;
 646         u32 src_alpha_ctl, dst_alpha_ctl;
 647
 648         for (i = 0; i < win->area_num; i++) {
 649                 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
 650                                  (win->area[i].format == FBDC_ARGB_888) ||
 651                                  (win->area[i].format == ABGR888)) ? 1 : 0;
 652         }
 653         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 654         alpha_config.src_global_alpha_val = win->g_alpha_val;
 655         win->alpha_mode = AB_SRC_OVER;
 656         /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
 657            __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,
 658            global_alpha); */
 659         switch (win->alpha_mode) {
 660         case AB_USER_DEFINE:
 661                 break;
 662         case AB_CLEAR:
 663                 alpha_config.src_factor_mode = AA_ZERO;
 664                 alpha_config.dst_factor_mode = AA_ZERO;
 665                 break;
 666         case AB_SRC:
 667                 alpha_config.src_factor_mode = AA_ONE;
 668                 alpha_config.dst_factor_mode = AA_ZERO;
 669                 break;
 670         case AB_DST:
 671                 alpha_config.src_factor_mode = AA_ZERO;
 672                 alpha_config.dst_factor_mode = AA_ONE;
 673                 break;
 674         case AB_SRC_OVER:
 675                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 676                 if (global_alpha)
 677                         alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 678                 else
 679                         alpha_config.src_factor_mode = AA_ONE;
 680                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 681                 break;
 682         case AB_DST_OVER:
 683                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 684                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 685                 alpha_config.dst_factor_mode = AA_ONE;
 686                 break;
 687         case AB_SRC_IN:
 688                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 689                 alpha_config.src_factor_mode = AA_SRC;
 690                 alpha_config.dst_factor_mode = AA_ZERO;
 691                 break;
 692         case AB_DST_IN:
 693                 alpha_config.src_factor_mode = AA_ZERO;
 694                 alpha_config.dst_factor_mode = AA_SRC;
 695                 break;
 696         case AB_SRC_OUT:
 697                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 698                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 699                 alpha_config.dst_factor_mode = AA_ZERO;
 700                 break;
 701         case AB_DST_OUT:
 702                 alpha_config.src_factor_mode = AA_ZERO;
 703                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 704                 break;
 705         case AB_SRC_ATOP:
 706                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 707                 alpha_config.src_factor_mode = AA_SRC;
 708                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 709                 break;
 710         case AB_DST_ATOP:
 711                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 712                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 713                 alpha_config.dst_factor_mode = AA_SRC;
 714                 break;
 715         case XOR:
 716                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 717                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 718                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 719                 break;
 720         case AB_SRC_OVER_GLOBAL:
 721                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 722                 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
 723                 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 724                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 725                 break;
 726         default:
 727                 pr_err("alpha mode error\n");
 728                 break;
 729         }
 730         if ((ppixel_alpha == 1) && (global_alpha == 1))
 731                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 732         else if (ppixel_alpha == 1)
 733                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 734         else if (global_alpha == 1)
 735                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 736         else
 737                 dev_warn(lcdc_dev->dev, "alpha_en should be 0\n");
 738         alpha_config.src_alpha_mode = AA_STRAIGHT;
 739         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 740
 741         switch (win_id) {
 742         case 0:
 743                 src_alpha_ctl = 0x60;
 744                 dst_alpha_ctl = 0x64;
 745                 break;
 746         case 1:
 747                 src_alpha_ctl = 0xa0;
 748                 dst_alpha_ctl = 0xa4;
 749                 break;
 750         case 2:
 751                 src_alpha_ctl = 0xdc;
 752                 dst_alpha_ctl = 0xec;
 753                 break;
 754         case 3:
 755                 src_alpha_ctl = 0x12c;
 756                 dst_alpha_ctl = 0x13c;
 757                 break;
 758         case 4:
 759                 src_alpha_ctl = 0x160;
 760                 dst_alpha_ctl = 0x164;
 761                 break;
 762         }
 763         mask = m_WIN0_DST_FACTOR_M0;
 764         val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
 765         lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
 766         mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
 767             m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
 768             m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 |
 769             m_WIN0_SRC_GLOBAL_ALPHA;
 770         val = v_WIN0_SRC_ALPHA_EN(1) |
 771             v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
 772             v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
 773             v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
 774             v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
 775             v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
 776             v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 777         lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
 778
 779         return 0;
 780 }
 781
 782 static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num)
 783 {
 784         struct rk_lcdc_win_area area_temp;
 785         int i, j;
 786
 787         for (i = 0; i < area_num; i++) {
 788                 for (j = i + 1; j < area_num; j++) {
 789                         if (win->area[i].dsp_stx >  win->area[j].dsp_stx) {
 790                                 memcpy(&area_temp, &win->area[i],
 791                                        sizeof(struct rk_lcdc_win_area));
 792                                 memcpy(&win->area[i], &win->area[j],
 793                                        sizeof(struct rk_lcdc_win_area));
 794                                 memcpy(&win->area[j], &area_temp,
 795                                        sizeof(struct rk_lcdc_win_area));
 796                         }
 797                 }
 798         }
 799
 800         return 0;
 801 }
 802
 803 static int __maybe_unused
 804         rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num)
 805 {
 806         struct rk_lcdc_win_area area_temp;
 807
 808         switch (area_num) {
 809         case 2:
 810                 area_temp = win->area[0];
 811                 win->area[0] = win->area[1];
 812                 win->area[1] = area_temp;
 813                 break;
 814         case 3:
 815                 area_temp = win->area[0];
 816                 win->area[0] = win->area[2];
 817                 win->area[2] = area_temp;
 818                 break;
 819         case 4:
 820                 area_temp = win->area[0];
 821                 win->area[0] = win->area[3];
 822                 win->area[3] = area_temp;
 823
 824                 area_temp = win->area[1];
 825                 win->area[1] = win->area[2];
 826                 win->area[2] = area_temp;
 827                 break;
 828         default:
 829                 pr_info("un supported area num!\n");
 830                 break;
 831         }
 832         return 0;
 833 }
 834
 835 static int __maybe_unused
 836 rk3368_win_area_check_var(int win_id, int area_num,
 837                           struct rk_lcdc_win_area *area_pre,
 838                           struct rk_lcdc_win_area *area_now)
 839 {
 840         if ((area_pre->xpos > area_now->xpos) ||
 841             ((area_pre->xpos + area_pre->xsize > area_now->xpos) &&
 842              (area_pre->ypos + area_pre->ysize > area_now->ypos))) {
 843                 area_now->state = 0;
 844                 pr_err("win[%d]:\n"
 845                        "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n"
 846                        "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n",
 847                        win_id,
 848                        area_num - 1, area_pre->xpos, area_pre->xsize,
 849                        area_pre->ypos, area_pre->ysize,
 850                        area_num, area_now->xpos, area_now->xsize,
 851                        area_now->ypos, area_now->ysize);
 852                 return -EINVAL;
 853         }
 854         return 0;
 855 }
 856
 857 static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv)
 858 {
 859         struct lcdc_device *lcdc_dev =
 860             container_of(dev_drv, struct lcdc_device, driver);
 861         u32 val, i;
 862
 863         for (i = 0; i < 100; i++) {
 864                 val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0);
 865                 val &= m_DBG_IFBDC_IDLE;
 866                 if (val)
 867                         continue;
 868                 else
 869                         mdelay(10);
 870         };
 871         return val;
 872 }
 873
 874 static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
 875 {
 876         struct lcdc_device *lcdc_dev =
 877             container_of(dev_drv, struct lcdc_device, driver);
 878         struct rk_lcdc_win *win = dev_drv->win[win_id];
 879         u32 mask, val;
 880
 881         mask = m_IFBDC_CTRL_FBDC_EN | m_IFBDC_CTRL_FBDC_COR_EN |
 882             m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE |
 883             m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO;
 884         val = v_IFBDC_CTRL_FBDC_EN(win->area[0].fbdc_en) |
 885             v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) |
 886             v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) |
 887             v_IFBDC_CTRL_FBDC_ROTATION_MODE(win->mirror_en << 1) |
 888             v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) |
 889             v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio);
 890         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
 891
 892         mask = m_IFBDC_TILES_NUM;
 893         val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles);
 894         lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val);
 895
 896         mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT;
 897         val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) |
 898             v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height);
 899         lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val);
 900
 901         mask = m_IFBDC_CMP_INDEX_INIT;
 902         val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init);
 903         lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val);
 904
 905         mask = m_IFBDC_MB_VIR_WIDTH;
 906         val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width);
 907         lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val);
 908
 909         return 0;
 910 }
 911
 912 static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id)
 913 {
 914         struct lcdc_device *lcdc_dev =
 915             container_of(dev_drv, struct lcdc_device, driver);
 916         struct rk_lcdc_win *win = dev_drv->win[win_id];
 917         u8 fbdc_dsp_width_ratio;
 918         u16 fbdc_mb_vir_width, fbdc_mb_vir_height;
 919         u16 fbdc_mb_width, fbdc_mb_height;
 920         u16 fbdc_mb_xst, fbdc_mb_yst, fbdc_num_tiles;
 921         u16 fbdc_cmp_index_init;
 922         u8 mb_w_size, mb_h_size;
 923         struct rk_screen *screen = dev_drv->cur_screen;
 924
 925         if (screen->mode.flag == FB_VMODE_INTERLACED) {
 926                 dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n");
 927                 return 0;
 928         }
 929
 930         switch (win->area[0].fmt_cfg) {
 931         case VOP_FORMAT_ARGB888:
 932                 fbdc_dsp_width_ratio = 0;
 933                 mb_w_size = 16;
 934                 break;
 935         case VOP_FORMAT_RGB888:
 936                 fbdc_dsp_width_ratio = 0;
 937                 mb_w_size = 16;
 938                 break;
 939         case VOP_FORMAT_RGB565:
 940                 fbdc_dsp_width_ratio = 1;
 941                 mb_w_size = 32;
 942                 break;
 943         default:
 944                 dev_err(lcdc_dev->dev,
 945                         "in fbdc mode,unsupport fmt:%d!\n",
 946                         win->area[0].fmt_cfg);
 947                 break;
 948         }
 949         mb_h_size = 4;
 950
 951         /*macro block xvir and yvir */
 952         if ((win->area[0].xvir % mb_w_size == 0) &&
 953             (win->area[0].yvir % mb_h_size == 0)) {
 954                 fbdc_mb_vir_width = win->area[0].xvir / mb_w_size;
 955                 fbdc_mb_vir_height = win->area[0].yvir / mb_h_size;
 956         } else {
 957                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 958                 pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n",
 959                        win->area[0].xvir, win->area[0].yvir,
 960                        mb_w_size, mb_h_size);
 961         }
 962         /*macro block xact and yact */
 963         if ((win->area[0].xact % mb_w_size == 0) &&
 964             (win->area[0].yact % mb_h_size == 0)) {
 965                 fbdc_mb_width = win->area[0].xact / mb_w_size;
 966                 fbdc_mb_height = win->area[0].yact / mb_h_size;
 967         } else {
 968                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 969                 pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n",
 970                        win->area[0].xact, win->area[0].yact,
 971                        mb_w_size, mb_h_size);
 972         }
 973         /*macro block xoff and yoff */
 974         if ((win->area[0].xoff % mb_w_size == 0) &&
 975             (win->area[0].yoff % mb_h_size == 0)) {
 976                 fbdc_mb_xst = win->area[0].xoff / mb_w_size;
 977                 fbdc_mb_yst = win->area[0].yoff / mb_h_size;
 978         } else {
 979                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 980                 pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n",
 981                        win->area[0].xoff, win->area[0].yoff,
 982                        mb_w_size, mb_h_size);
 983         }
 984
 985         /*FBDC tiles */
 986         fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height;
 987
 988         /*
 989            switch (fbdc_rotation_mode)  {
 990            case FBDC_ROT_NONE:
 991            fbdc_cmp_index_init =
 992            (fbdc_mb_yst*fbdc_mb_vir_width) +  fbdc_mb_xst;
 993            break;
 994            case FBDC_X_MIRROR:
 995            fbdc_cmp_index_init =
 996            (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+
 997            (fbdc_mb_width-1));
 998            break;
 999            case FBDC_Y_MIRROR:
1000            fbdc_cmp_index_init =
1001            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width)  +
1002            fbdc_mb_xst;
1003            break;
1004            case FBDC_ROT_180:
1005            fbdc_cmp_index_init =
1006            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
1007            (fbdc_mb_xst+(fbdc_mb_width-1));
1008            break;
1009            }
1010          */
1011         if ((win->mirror_en) && ((win_id == 2) || (win_id == 3))) {
1012                 fbdc_cmp_index_init =
1013                     ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) +
1014                     (fbdc_mb_xst + (fbdc_mb_width - 1));
1015         } else {
1016                 fbdc_cmp_index_init =
1017                     (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst;
1018         }
1019         /*fbdc fmt maybe need to change*/
1020         win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio;
1021         win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width;
1022         win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height;
1023         win->area[0].fbdc_mb_width = fbdc_mb_width;
1024         win->area[0].fbdc_mb_height = fbdc_mb_height;
1025         win->area[0].fbdc_mb_xst = fbdc_mb_xst;
1026         win->area[0].fbdc_mb_yst = fbdc_mb_yst;
1027         win->area[0].fbdc_num_tiles = fbdc_num_tiles;
1028         win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init;
1029
1030         return 0;
1031 }
1032
1033 static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev,
1034                                  struct rk_lcdc_win *win)
1035 {
1036         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1037         struct rk_screen *screen = dev_drv->cur_screen;
1038
1039         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1040                 switch (win->area[0].fmt_cfg) {
1041                 case VOP_FORMAT_ARGB888:
1042                 case VOP_FORMAT_RGB888:
1043                 case VOP_FORMAT_RGB565:
1044                         if ((screen->mode.xres < 1280) &&
1045                             (screen->mode.yres < 720)) {
1046                                 win->csc_mode = VOP_R2Y_CSC_BT601;
1047                         } else {
1048                                 win->csc_mode = VOP_R2Y_CSC_BT709;
1049                         }
1050                         break;
1051                 default:
1052                         break;
1053                 }
1054         } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
1055                 switch (win->area[0].fmt_cfg) {
1056                 case VOP_FORMAT_YCBCR420:
1057                         if ((win->id == 0) || (win->id == 1))
1058                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
1059                         break;
1060                 default:
1061                         break;
1062                 }
1063         }
1064 }
1065
1066 static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1067 {
1068         struct lcdc_device *lcdc_dev =
1069             container_of(dev_drv, struct lcdc_device, driver);
1070         struct rk_lcdc_win *win = dev_drv->win[win_id];
1071         unsigned int mask, val, off;
1072
1073         off = win_id * 0x40;
1074         /*if(win->win_lb_mode == 5)
1075            win->win_lb_mode = 4;
1076            for rk3288 to fix hw bug? */
1077
1078         if (win->state == 1) {
1079                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1080                 if (win->area[0].fbdc_en) {
1081                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1082                 } else {
1083                         mask = m_IFBDC_CTRL_FBDC_EN;
1084                         val = v_IFBDC_CTRL_FBDC_EN(0);
1085                         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1086                 }
1087                 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
1088                     m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR |
1089                     m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE |m_WIN0_UV_SWAP;
1090                 val = v_WIN0_EN(win->state) |
1091                     v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1092                     v_WIN0_FMT_10(win->fmt_10) |
1093                     v_WIN0_LB_MODE(win->win_lb_mode) |
1094                     v_WIN0_RB_SWAP(win->area[0].swap_rb) |
1095                     v_WIN0_X_MIRROR(win->mirror_en) |
1096                     v_WIN0_Y_MIRROR(win->mirror_en) |
1097                     v_WIN0_CSC_MODE(win->csc_mode) |
1098                     v_WIN0_UV_SWAP(win->area[0].swap_uv);
1099                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1100
1101                 mask = m_WIN0_BIC_COE_SEL |
1102                     m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
1103                     m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
1104                     m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
1105                     m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
1106                     m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
1107                     m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
1108                     m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
1109                 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1110                     v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1111                     v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1112                     v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1113                     v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1114                     v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1115                     v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1116                     v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1117                     v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1118                     v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1119                     v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1120                     v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1121                     v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1122                     v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1123                     v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1124                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val);
1125                 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1126                     v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1127                 lcdc_writel(lcdc_dev, WIN0_VIR + off, val);
1128                 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off,
1129                                 win->area[0].y_addr);
1130                    lcdc_writel(lcdc_dev, WIN0_CBR_MST+off,
1131                                 win->area[0].uv_addr); */
1132                 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
1133                     v_WIN0_ACT_HEIGHT(win->area[0].yact);
1134                 lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val);
1135
1136                 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
1137                     v_WIN0_DSP_HEIGHT(win->area[0].ysize);
1138                 lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val);
1139
1140                 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
1141                     v_WIN0_DSP_YST(win->area[0].dsp_sty);
1142                 lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val);
1143
1144                 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1145                     v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1146                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1147
1148                 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1149                     v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1150                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val);
1151                 if (win->alpha_en == 1) {
1152                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1153                 } else {
1154                         mask = m_WIN0_SRC_ALPHA_EN;
1155                         val = v_WIN0_SRC_ALPHA_EN(0);
1156                         lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off,
1157                                      mask, val);
1158                 }
1159         } else {
1160                 mask = m_WIN0_EN;
1161                 val = v_WIN0_EN(win->state);
1162                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1163         }
1164         return 0;
1165 }
1166
1167 static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1168 {
1169         struct lcdc_device *lcdc_dev =
1170             container_of(dev_drv, struct lcdc_device, driver);
1171         struct rk_lcdc_win *win = dev_drv->win[win_id];
1172         unsigned int mask, val, off;
1173
1174         off = (win_id - 2) * 0x50;
1175         rk3368_lcdc_area_xst(win, win->area_num);
1176
1177         if (win->state == 1) {
1178                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1179                 if (win->area[0].fbdc_en) {
1180                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1181                 } else {
1182                         mask = m_IFBDC_CTRL_FBDC_EN;
1183                         val = v_IFBDC_CTRL_FBDC_EN(0);
1184                         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1185                 }
1186
1187                 mask = m_WIN2_EN | m_WIN2_CSC_MODE;
1188                 val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode);
1189                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1190                 /*area 0 */
1191                 if (win->area[0].state == 1) {
1192                         mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 |
1193                             m_WIN2_RB_SWAP0;
1194                         val = v_WIN2_MST0_EN(win->area[0].state) |
1195                             v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1196                             v_WIN2_RB_SWAP0(win->area[0].swap_rb);
1197                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1198
1199                         mask = m_WIN2_VIR_STRIDE0;
1200                         val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1201                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1202
1203                         /*lcdc_writel(lcdc_dev,WIN2_MST0+off,
1204                            win->area[0].y_addr); */
1205                         val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1206                             v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1207                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val);
1208                         val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1209                             v_WIN2_DSP_YST0(win->area[0].dsp_sty);
1210                         lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val);
1211                 } else {
1212                         mask = m_WIN2_MST0_EN;
1213                         val = v_WIN2_MST0_EN(0);
1214                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1215                 }
1216                 /*area 1 */
1217                 if (win->area[1].state == 1) {
1218                         /*rk3368_win_area_check_var(win_id, 1,
1219                                                   &win->area[0], &win->area[1]);
1220                         */
1221
1222                         mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 |
1223                             m_WIN2_RB_SWAP1;
1224                         val = v_WIN2_MST1_EN(win->area[1].state) |
1225                             v_WIN2_DATA_FMT1(win->area[1].fmt_cfg) |
1226                             v_WIN2_RB_SWAP1(win->area[1].swap_rb);
1227                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1228
1229                         mask = m_WIN2_VIR_STRIDE1;
1230                         val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1231                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1232
1233                         /*lcdc_writel(lcdc_dev,WIN2_MST1+off,
1234                            win->area[1].y_addr); */
1235                         val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1236                             v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1237                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val);
1238                         val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1239                             v_WIN2_DSP_YST1(win->area[1].dsp_sty);
1240                         lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val);
1241                 } else {
1242                         mask = m_WIN2_MST1_EN;
1243                         val = v_WIN2_MST1_EN(0);
1244                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1245                 }
1246                 /*area 2 */
1247                 if (win->area[2].state == 1) {
1248                         /*rk3368_win_area_check_var(win_id, 2,
1249                                                   &win->area[1], &win->area[2]);
1250                         */
1251
1252                         mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 |
1253                             m_WIN2_RB_SWAP2;
1254                         val = v_WIN2_MST2_EN(win->area[2].state) |
1255                             v_WIN2_DATA_FMT2(win->area[2].fmt_cfg) |
1256                             v_WIN2_RB_SWAP2(win->area[2].swap_rb);
1257                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1258
1259                         mask = m_WIN2_VIR_STRIDE2;
1260                         val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1261                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1262
1263                         /*lcdc_writel(lcdc_dev,WIN2_MST2+off,
1264                            win->area[2].y_addr); */
1265                         val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1266                             v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1267                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val);
1268                         val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1269                             v_WIN2_DSP_YST2(win->area[2].dsp_sty);
1270                         lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val);
1271                 } else {
1272                         mask = m_WIN2_MST2_EN;
1273                         val = v_WIN2_MST2_EN(0);
1274                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1275                 }
1276                 /*area 3 */
1277                 if (win->area[3].state == 1) {
1278                         /*rk3368_win_area_check_var(win_id, 3,
1279                                                   &win->area[2], &win->area[3]);
1280                         */
1281
1282                         mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 |
1283                             m_WIN2_RB_SWAP3;
1284                         val = v_WIN2_MST3_EN(win->area[3].state) |
1285                             v_WIN2_DATA_FMT3(win->area[3].fmt_cfg) |
1286                             v_WIN2_RB_SWAP3(win->area[3].swap_rb);
1287                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1288
1289                         mask = m_WIN2_VIR_STRIDE3;
1290                         val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1291                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1292
1293                         /*lcdc_writel(lcdc_dev,WIN2_MST3+off,
1294                            win->area[3].y_addr); */
1295                         val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1296                             v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1297                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val);
1298                         val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1299                             v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1300                         lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val);
1301                 } else {
1302                         mask = m_WIN2_MST3_EN;
1303                         val = v_WIN2_MST3_EN(0);
1304                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1305                 }
1306
1307                 if (win->alpha_en == 1) {
1308                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1309                 } else {
1310                         mask = m_WIN2_SRC_ALPHA_EN;
1311                         val = v_WIN2_SRC_ALPHA_EN(0);
1312                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off,
1313                                      mask, val);
1314                 }
1315         } else {
1316                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1317                     m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1318                 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1319                     v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1320                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1321         }
1322         return 0;
1323 }
1324
1325 static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1326 {
1327         struct lcdc_device *lcdc_dev =
1328             container_of(dev_drv, struct lcdc_device, driver);
1329         struct rk_lcdc_win *win = dev_drv->win[win_id];
1330         unsigned int mask, val, hwc_size = 0;
1331
1332         if (win->state == 1) {
1333                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1334                 mask = m_HWC_EN | m_HWC_DATA_FMT |
1335                     m_HWC_RB_SWAP | m_WIN0_CSC_MODE;
1336                 val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1337                     v_HWC_RB_SWAP(win->area[0].swap_rb) |
1338                     v_WIN0_CSC_MODE(win->csc_mode);
1339                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1340
1341                 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1342                         hwc_size = 0;
1343                 else if ((win->area[0].xsize == 64) &&
1344                          (win->area[0].ysize == 64))
1345                         hwc_size = 1;
1346                 else if ((win->area[0].xsize == 96) &&
1347                          (win->area[0].ysize == 96))
1348                         hwc_size = 2;
1349                 else if ((win->area[0].xsize == 128) &&
1350                          (win->area[0].ysize == 128))
1351                         hwc_size = 3;
1352                 else
1353                         dev_err(lcdc_dev->dev, "un supported hwc size!\n");
1354
1355                 mask = m_HWC_SIZE;
1356                 val = v_HWC_SIZE(hwc_size);
1357                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1358
1359                 mask = m_HWC_DSP_XST | m_HWC_DSP_YST;
1360                 val = v_HWC_DSP_XST(win->area[0].dsp_stx) |
1361                     v_HWC_DSP_YST(win->area[0].dsp_sty);
1362                 lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val);
1363
1364                 if (win->alpha_en == 1) {
1365                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1366                 } else {
1367                         mask = m_WIN2_SRC_ALPHA_EN;
1368                         val = v_WIN2_SRC_ALPHA_EN(0);
1369                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val);
1370                 }
1371         } else {
1372                 mask = m_HWC_EN;
1373                 val = v_HWC_EN(win->state);
1374                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1375         }
1376         return 0;
1377 }
1378
1379 static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
1380                                          struct rk_lcdc_win *win)
1381 {
1382         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1383         int timeout;
1384         unsigned long flags;
1385
1386         spin_lock(&lcdc_dev->reg_lock);
1387         if (likely(lcdc_dev->clk_on)) {
1388                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1389                              v_STANDBY_EN(lcdc_dev->standby));
1390                 if ((win->id == 0) || (win->id == 1))
1391                         rk3368_win_0_1_reg_update(dev_drv, win->id);
1392                 else if ((win->id == 2) || (win->id == 3))
1393                         rk3368_win_2_3_reg_update(dev_drv, win->id);
1394                 else if (win->id == 4)
1395                         rk3368_hwc_reg_update(dev_drv, win->id);
1396                 /*rk3368_lcdc_post_cfg(dev_drv); */
1397                 lcdc_cfg_done(lcdc_dev);
1398         }
1399         spin_unlock(&lcdc_dev->reg_lock);
1400
1401         /*if (dev_drv->wait_fs) { */
1402         if (0) {
1403                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1404                 init_completion(&dev_drv->frame_done);
1405                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1406                 timeout =
1407                     wait_for_completion_timeout(&dev_drv->frame_done,
1408                                                 msecs_to_jiffies
1409                                                 (dev_drv->cur_screen->ft + 5));
1410                 if (!timeout && (!dev_drv->frame_done.done)) {
1411                         dev_warn(lcdc_dev->dev,
1412                                  "wait for new frame start time out!\n");
1413                         return -ETIMEDOUT;
1414                 }
1415         }
1416         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1417         return 0;
1418 }
1419
1420 static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1421 {
1422         memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x270);
1423         return 0;
1424 }
1425
1426 static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1427 {
1428         u32 mask, val;
1429         struct lcdc_device *lcdc_dev =
1430             container_of(dev_drv, struct lcdc_device, driver);
1431
1432 #if defined(CONFIG_ROCKCHIP_IOMMU)
1433         if (dev_drv->iommu_enabled) {
1434                 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1435                         if (likely(lcdc_dev->clk_on)) {
1436                                 mask = m_MMU_EN;
1437                                 val = v_MMU_EN(1);
1438                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1439                                 mask = m_AXI_MAX_OUTSTANDING_EN |
1440                                         m_AXI_OUTSTANDING_MAX_NUM;
1441                                 val = v_AXI_OUTSTANDING_MAX_NUM(31) |
1442                                         v_AXI_MAX_OUTSTANDING_EN(1);
1443                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1444                         }
1445                         lcdc_dev->iommu_status = 1;
1446                         rockchip_iovmm_activate(dev_drv->dev);
1447                 }
1448         }
1449 #endif
1450         return 0;
1451 }
1452
1453 static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate)
1454 {
1455         int ret = 0, fps = 0;
1456         struct lcdc_device *lcdc_dev =
1457             container_of(dev_drv, struct lcdc_device, driver);
1458         struct rk_screen *screen = dev_drv->cur_screen;
1459 #ifdef CONFIG_RK_FPGA
1460         return 0;
1461 #endif
1462         if (reset_rate)
1463                 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1464         if (ret)
1465                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1466         lcdc_dev->pixclock =
1467             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1468         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1469
1470         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1471         screen->ft = 1000 / fps;
1472         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1473                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1474         return 0;
1475 }
1476
1477 static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv)
1478 {
1479         struct lcdc_device *lcdc_dev =
1480             container_of(dev_drv, struct lcdc_device, driver);
1481         struct rk_screen *screen = dev_drv->cur_screen;
1482         u16 hsync_len = screen->mode.hsync_len;
1483         u16 left_margin = screen->mode.left_margin;
1484         u16 right_margin = screen->mode.right_margin;
1485         u16 vsync_len = screen->mode.vsync_len;
1486         u16 upper_margin = screen->mode.upper_margin;
1487         u16 lower_margin = screen->mode.lower_margin;
1488         u16 x_res = screen->mode.xres;
1489         u16 y_res = screen->mode.yres;
1490         u32 mask, val;
1491         u16 h_total, v_total;
1492         u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1493
1494         h_total = hsync_len + left_margin + x_res + right_margin;
1495         v_total = vsync_len + upper_margin + y_res + lower_margin;
1496
1497         mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1498         val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1499         lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1500
1501         mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1502         val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1503             v_DSP_HACT_ST(hsync_len + left_margin);
1504         lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1505
1506         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1507                 /* First Field Timing */
1508                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1509                 val = v_DSP_VS_PW(vsync_len) |
1510                     v_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1511                                       lower_margin) + y_res + 1);
1512                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1513
1514                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1515                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1516                     v_DSP_VACT_ST(vsync_len + upper_margin);
1517                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1518
1519                 /* Second Field Timing */
1520                 mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1;
1521                 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1522                 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1523                     lower_margin;
1524                 val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1);
1525                 lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val);
1526
1527                 mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1;
1528                 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1529                     lower_margin + 1;
1530                 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1531                     lower_margin + 1;
1532                 val =
1533                     v_DSP_VACT_END_F1(vact_end_f1) |
1534                     v_DSP_VAC_ST_F1(vact_st_f1);
1535                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val);
1536
1537                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1538                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1539                              v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0));
1540                 mask =
1541                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1542                     m_WIN0_CBR_DEFLICK;
1543                 val =
1544                     v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(1) |
1545                     v_WIN0_CBR_DEFLICK(1);
1546                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1547
1548                 mask =
1549                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1550                     m_WIN1_CBR_DEFLICK;
1551                 val =
1552                     v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(1) |
1553                     v_WIN1_CBR_DEFLICK(1);
1554                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1555
1556                 mask = m_WIN2_INTERLACE_READ;
1557                 val = v_WIN2_INTERLACE_READ(1);
1558                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1559
1560                 mask = m_WIN3_INTERLACE_READ;
1561                 val = v_WIN3_INTERLACE_READ(1);
1562                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1563
1564                 mask = m_HWC_INTERLACE_READ;
1565                 val = v_HWC_INTERLACE_READ(1);
1566                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1567
1568                 mask = m_DSP_LINE_FLAG0_NUM | m_DSP_LINE_FLAG1_NUM;
1569                 val =
1570                     v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res / 2) |
1571                     v_DSP_LINE_FLAG1_NUM(vsync_len + upper_margin + y_res / 2);
1572                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1573         } else {
1574                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1575                 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1576                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1577
1578                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1579                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1580                     v_DSP_VACT_ST(vsync_len + upper_margin);
1581                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1582
1583                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1584                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1585                              v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0));
1586
1587                 mask =
1588                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1589                     m_WIN0_CBR_DEFLICK;
1590                 val =
1591                     v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) |
1592                     v_WIN0_CBR_DEFLICK(0);
1593                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1594
1595                 mask =
1596                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1597                     m_WIN1_CBR_DEFLICK;
1598                 val =
1599                     v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) |
1600                     v_WIN1_CBR_DEFLICK(0);
1601                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1602
1603                 mask = m_WIN2_INTERLACE_READ;
1604                 val = v_WIN2_INTERLACE_READ(0);
1605                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1606
1607                 mask = m_WIN3_INTERLACE_READ;
1608                 val = v_WIN3_INTERLACE_READ(0);
1609                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1610
1611                 mask = m_HWC_INTERLACE_READ;
1612                 val = v_HWC_INTERLACE_READ(0);
1613                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1614
1615                 mask = m_DSP_LINE_FLAG0_NUM | m_DSP_LINE_FLAG1_NUM;
1616                 val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res) |
1617                         v_DSP_LINE_FLAG1_NUM(vsync_len + upper_margin + y_res);
1618                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1619         }
1620         rk3368_lcdc_post_cfg(dev_drv);
1621         return 0;
1622 }
1623
1624 static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1625 {
1626         struct lcdc_device *lcdc_dev =
1627             container_of(dev_drv, struct lcdc_device, driver);
1628         u32 bcsh_ctrl;
1629
1630         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_OVERLAY_MODE,
1631                      v_OVERLAY_MODE(dev_drv->overlay_mode));
1632         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1633                 if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1634                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1635                                      m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1636                                      v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1637                 else            /* YUV2RGB */
1638                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1639                                      m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1640                                      m_BCSH_R2Y_EN,
1641                                      v_BCSH_Y2R_EN(1) |
1642                                      v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1643                                      v_BCSH_R2Y_EN(0));
1644         } else {                /* overlay_mode=VOP_RGB_DOMAIN */
1645                 /* bypass  --need check,if bcsh close? */
1646                 if (dev_drv->output_color == COLOR_RGB) {
1647                         bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1648                         if (((bcsh_ctrl & m_BCSH_EN) == 1) ||
1649                             (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1650                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1651                                              m_BCSH_R2Y_EN |
1652                                              m_BCSH_Y2R_EN,
1653                                              v_BCSH_R2Y_EN(1) |
1654                                              v_BCSH_Y2R_EN(1));
1655                         else
1656                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1657                                              m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1658                                              v_BCSH_R2Y_EN(0) |
1659                                              v_BCSH_Y2R_EN(0));
1660                 } else          /* RGB2YUV */
1661                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1662                                      m_BCSH_R2Y_EN |
1663                                      m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1664                                      v_BCSH_R2Y_EN(1) |
1665                                      v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1666                                      v_BCSH_Y2R_EN(0));
1667         }
1668 }
1669
1670 static int rk3368_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1671                                   u16 *yact, int *format, u32 *dsp_addr)
1672 {
1673         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1674                                                     struct lcdc_device, driver);
1675         u32 val;
1676
1677         spin_lock(&lcdc_dev->reg_lock);
1678
1679         val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1680         *xact = (val & m_WIN0_ACT_WIDTH) + 1;
1681         *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1;
1682
1683         val = lcdc_readl(lcdc_dev, WIN0_CTRL0);
1684         *format = (val & m_WIN0_DATA_FMT) >> 1;
1685         *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1686
1687         spin_unlock(&lcdc_dev->reg_lock);
1688
1689         return 0;
1690 }
1691
1692 static int rk3368_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1693                               int format, u16 xact, u16 yact, u16 xvir)
1694 {
1695         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1696                                                     struct lcdc_device, driver);
1697         u32 val, mask;
1698         int swap = (format == RGB888) ? 1 : 0;
1699
1700         mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP;
1701         val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap);
1702         lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1703
1704         lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE,
1705                         v_WIN0_VIR_STRIDE(xvir));
1706         lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) |
1707                     v_WIN0_ACT_HEIGHT(yact));
1708
1709         lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1710
1711         lcdc_cfg_done(lcdc_dev);
1712
1713         return 0;
1714 }
1715
1716
1717 static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1718 {
1719         u16 face = 0;
1720         u16 dclk_ddr = 0;
1721         u32 v = 0;
1722         struct lcdc_device *lcdc_dev =
1723             container_of(dev_drv, struct lcdc_device, driver);
1724         struct rk_screen *screen = dev_drv->cur_screen;
1725         u32 mask, val;
1726
1727         spin_lock(&lcdc_dev->reg_lock);
1728         if (likely(lcdc_dev->clk_on)) {
1729                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1730                 if (!lcdc_dev->standby && !initscreen) {
1731                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1732                                      v_STANDBY_EN(1));
1733                         lcdc_cfg_done(lcdc_dev);
1734                         mdelay(50);
1735                 }
1736                 switch (screen->face) {
1737                 case OUT_P565:
1738                         face = OUT_P565;
1739                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1740                             m_DITHER_DOWN_SEL;
1741                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1742                             v_DITHER_DOWN_SEL(1);
1743                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1744                         break;
1745                 case OUT_P666:
1746                         face = OUT_P666;
1747                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1748                             m_DITHER_DOWN_SEL;
1749                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1750                             v_DITHER_DOWN_SEL(1);
1751                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1752                         break;
1753                 case OUT_D888_P565:
1754                         face = OUT_P888;
1755                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1756                             m_DITHER_DOWN_SEL;
1757                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1758                             v_DITHER_DOWN_SEL(1);
1759                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1760                         break;
1761                 case OUT_D888_P666:
1762                         face = OUT_P888;
1763                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1764                             m_DITHER_DOWN_SEL;
1765                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1766                             v_DITHER_DOWN_SEL(1);
1767                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1768                         break;
1769                 case OUT_P888:
1770                         face = OUT_P888;
1771                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1772                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1773                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1774                         break;
1775                 case OUT_YUV_420:
1776                         /*yuv420 output prefer yuv domain overlay */
1777                         face = OUT_YUV_420;
1778                         dclk_ddr = 1;
1779                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1780                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1781                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1782                         break;
1783                 default:
1784                         dev_err(lcdc_dev->dev, "un supported interface!\n");
1785                         break;
1786                 }
1787                 switch (screen->type) {
1788                 case SCREEN_RGB:
1789                         mask = m_RGB_OUT_EN;
1790                         val = v_RGB_OUT_EN(1);
1791                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1792                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1793                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1794                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1795                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1796                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1797                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1798                         v = 1 << 15 | (1 << (15 + 16));
1799
1800                         break;
1801                 case SCREEN_LVDS:
1802                         mask = m_RGB_OUT_EN;
1803                         val = v_RGB_OUT_EN(1);
1804                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1805                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1806                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1807                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1808                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1809                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1810                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1811                         v = 0 << 15 | (1 << (15 + 16));
1812                         break;
1813                 case SCREEN_HDMI:
1814                         /*face = OUT_RGB_AAA;*/
1815                         if (screen->color_mode == COLOR_RGB)
1816                                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1817                         else
1818                                 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1819                         mask = m_HDMI_OUT_EN  | m_RGB_OUT_EN;
1820                         val = v_HDMI_OUT_EN(1) | v_RGB_OUT_EN(0);
1821                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1822                         mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
1823                             m_HDMI_DEN_POL | m_HDMI_DCLK_POL;
1824                         val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
1825                             v_HDMI_VSYNC_POL(screen->pin_vsync) |
1826                             v_HDMI_DEN_POL(screen->pin_den) |
1827                             v_HDMI_DCLK_POL(screen->pin_dclk);
1828                         break;
1829                 case SCREEN_MIPI:
1830                         mask = m_MIPI_OUT_EN  | m_RGB_OUT_EN;
1831                         val = v_MIPI_OUT_EN(1) | v_RGB_OUT_EN(0);
1832                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1833                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1834                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1835                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1836                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1837                             v_MIPI_DEN_POL(screen->pin_den) |
1838                             v_MIPI_DCLK_POL(screen->pin_dclk);
1839                         break;
1840                 case SCREEN_DUAL_MIPI:
1841                         mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN  |
1842                                 m_RGB_OUT_EN;
1843                         val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1) |
1844                                 v_RGB_OUT_EN(0);
1845                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1846                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1847                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1848                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1849                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1850                             v_MIPI_DEN_POL(screen->pin_den) |
1851                             v_MIPI_DCLK_POL(screen->pin_dclk);
1852                         break;
1853                 case SCREEN_EDP:
1854                         face = OUT_P888;        /*RGB 888 output */
1855
1856                         mask = m_EDP_OUT_EN | m_RGB_OUT_EN;
1857                         val = v_EDP_OUT_EN(1) | v_RGB_OUT_EN(0);
1858                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1859                         /*because edp have to sent aaa fmt */
1860                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1861                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1862
1863                         mask |= m_EDP_HSYNC_POL | m_EDP_VSYNC_POL |
1864                             m_EDP_DEN_POL | m_EDP_DCLK_POL;
1865                         val |= v_EDP_HSYNC_POL(screen->pin_hsync) |
1866                             v_EDP_VSYNC_POL(screen->pin_vsync) |
1867                             v_EDP_DEN_POL(screen->pin_den) |
1868                             v_EDP_DCLK_POL(screen->pin_dclk);
1869                         break;
1870                 }
1871                 /*hsync vsync den dclk polo,dither */
1872                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1873 #ifndef CONFIG_RK_FPGA
1874                 /*writel_relaxed(v, RK_GRF_VIRT + rk3368_GRF_SOC_CON7);
1875                 move to  lvds driver*/
1876                 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
1877 #endif
1878                 mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP |
1879                     m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1880                     m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1881                     m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
1882                 val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) |
1883                     v_DSP_BG_SWAP(screen->swap_gb) |
1884                     v_DSP_RB_SWAP(screen->swap_rb) |
1885                     v_DSP_RG_SWAP(screen->swap_rg) |
1886                     v_DSP_DELTA_SWAP(screen->swap_delta) |
1887                     v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1888                     v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1889                     v_DSP_X_MIR_EN(screen->x_mirror) |
1890                     v_DSP_Y_MIR_EN(screen->y_mirror);
1891                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1892                 /*BG color */
1893                 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1894                 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN)
1895                         val = v_DSP_BG_BLUE(0x80) | v_DSP_BG_GREEN(0x10) |
1896                                 v_DSP_BG_RED(0x80);
1897                 else
1898                         val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) |
1899                                 v_DSP_BG_RED(0);
1900                 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1901                 dev_drv->output_color = screen->color_mode;
1902                 if (screen->dsp_lut == NULL)
1903                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
1904                                      v_DSP_LUT_EN(0));
1905                 else
1906                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
1907                                      v_DSP_LUT_EN(1));
1908                 if (screen->cabc_lut == NULL) {
1909                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0, m_CABC_EN,
1910                                      v_CABC_EN(0));
1911                 } else {
1912                         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
1913                                      v_CABC_LUT_EN(1));
1914                 }
1915                 rk3368_lcdc_bcsh_path_sel(dev_drv);
1916                 rk3368_config_timing(dev_drv);
1917         }
1918         spin_unlock(&lcdc_dev->reg_lock);
1919         rk3368_lcdc_set_dclk(dev_drv, 1);
1920         if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1921             dev_drv->trsm_ops->enable)
1922                 dev_drv->trsm_ops->enable();
1923         if (screen->init)
1924                 screen->init();
1925         if (!lcdc_dev->standby)
1926                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
1927         return 0;
1928 }
1929
1930
1931 /*enable layer,open:1,enable;0 disable*/
1932 static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev,
1933                                      unsigned int win_id, bool open)
1934 {
1935         spin_lock(&lcdc_dev->reg_lock);
1936         if (likely(lcdc_dev->clk_on) &&
1937             lcdc_dev->driver.win[win_id]->state != open) {
1938                 if (open) {
1939                         if (!lcdc_dev->atv_layer_cnt) {
1940                                 dev_info(lcdc_dev->dev,
1941                                          "wakeup from standby!\n");
1942                                 lcdc_dev->standby = 0;
1943                         }
1944                         lcdc_dev->atv_layer_cnt |= (1 << win_id);
1945                 } else {
1946                         if (lcdc_dev->atv_layer_cnt & (1 << win_id))
1947                                 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
1948                 }
1949                 lcdc_dev->driver.win[win_id]->state = open;
1950                 if (!open) {
1951                         /*rk3368_lcdc_reg_update(dev_drv);*/
1952                         rk3368_lcdc_layer_update_regs
1953                         (lcdc_dev, lcdc_dev->driver.win[win_id]);
1954                         lcdc_cfg_done(lcdc_dev);
1955                 }
1956                 /*if no layer used,disable lcdc */
1957                 if (!lcdc_dev->atv_layer_cnt) {
1958                         dev_info(lcdc_dev->dev,
1959                                  "no layer is used,go to standby!\n");
1960                         lcdc_dev->standby = 1;
1961                 }
1962         }
1963         spin_unlock(&lcdc_dev->reg_lock);
1964 }
1965
1966 static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1967 {
1968         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1969                                                     struct lcdc_device, driver);
1970         u32 mask, val;
1971         /*struct rk_screen *screen = dev_drv->cur_screen; */
1972
1973         mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
1974             m_LINE_FLAG1_INTR_CLR;
1975         val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
1976             v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1);
1977         lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
1978
1979         mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN |
1980                 m_BUS_ERROR_INTR_EN | m_LINE_FLAG1_INTR_EN;
1981         val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) |
1982             v_BUS_ERROR_INTR_EN(1) | v_LINE_FLAG1_INTR_EN(0);
1983         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1984
1985 #ifdef LCDC_IRQ_EMPTY_DEBUG
1986         mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
1987             m_WIN2_EMPTY_INTR_EN |
1988             m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN |
1989             m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN;
1990         val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) |
1991             v_WIN2_EMPTY_INTR_EN(1) |
1992             v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) |
1993             v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1);
1994         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1995 #endif
1996         return 0;
1997 }
1998
1999 static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
2000                             bool open)
2001 {
2002         struct lcdc_device *lcdc_dev =
2003             container_of(dev_drv, struct lcdc_device, driver);
2004 #if 0/*ndef CONFIG_RK_FPGA*/
2005         int sys_status =
2006             (dev_drv->id == 0) ? SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
2007 #endif
2008         /*enable clk,when first layer open */
2009         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
2010                 /*rockchip_set_system_status(sys_status);*/
2011                 rk3368_lcdc_pre_init(dev_drv);
2012                 rk3368_lcdc_clk_enable(lcdc_dev);
2013 #if defined(CONFIG_ROCKCHIP_IOMMU)
2014                 if (dev_drv->iommu_enabled) {
2015                         if (!dev_drv->mmu_dev) {
2016                                 dev_drv->mmu_dev =
2017                                     rk_fb_get_sysmmu_device_by_compatible
2018                                     (dev_drv->mmu_dts_name);
2019                                 if (dev_drv->mmu_dev) {
2020                                         rk_fb_platform_set_sysmmu
2021                                             (dev_drv->mmu_dev, dev_drv->dev);
2022                                 } else {
2023                                         dev_err(dev_drv->dev,
2024                                                 "fail get rk iommu device\n");
2025                                         return -1;
2026                                 }
2027                         }
2028                         /*if (dev_drv->mmu_dev)
2029                            rockchip_iovmm_activate(dev_drv->dev); */
2030                 }
2031 #endif
2032                 rk3368_lcdc_reg_restore(lcdc_dev);
2033                 /*if (dev_drv->iommu_enabled)
2034                    rk3368_lcdc_mmu_en(dev_drv); */
2035                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
2036                         rk3368_lcdc_set_dclk(dev_drv, 0);
2037                         rk3368_lcdc_enable_irq(dev_drv);
2038                 } else {
2039                         rk3368_load_screen(dev_drv, 1);
2040                 }
2041                 if (dev_drv->bcsh.enable)
2042                         rk3368_lcdc_set_bcsh(dev_drv, 1);
2043                 spin_lock(&lcdc_dev->reg_lock);
2044                 if (dev_drv->cur_screen->dsp_lut)
2045                         rk3368_lcdc_set_lut(dev_drv,
2046                                             dev_drv->cur_screen->dsp_lut);
2047                 if (dev_drv->cur_screen->cabc_lut)
2048                         rk3368_set_cabc_lut(dev_drv,
2049                                             dev_drv->cur_screen->cabc_lut);
2050                 spin_unlock(&lcdc_dev->reg_lock);
2051         }
2052
2053         if (win_id < ARRAY_SIZE(lcdc_win))
2054                 rk3368_lcdc_layer_enable(lcdc_dev, win_id, open);
2055         else
2056                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
2057
2058
2059         /* when all layer closed,disable clk */
2060         /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
2061            rk3368_lcdc_disable_irq(lcdc_dev);
2062            rk3368_lcdc_reg_update(dev_drv);
2063            #if defined(CONFIG_ROCKCHIP_IOMMU)
2064            if (dev_drv->iommu_enabled) {
2065            if (dev_drv->mmu_dev)
2066            rockchip_iovmm_deactivate(dev_drv->dev);
2067            }
2068            #endif
2069            rk3368_lcdc_clk_disable(lcdc_dev);
2070            #ifndef CONFIG_RK_FPGA
2071            rockchip_clear_system_status(sys_status);
2072            #endif
2073            } */
2074
2075         return 0;
2076 }
2077
2078 static int win_0_1_display(struct lcdc_device *lcdc_dev,
2079                            struct rk_lcdc_win *win)
2080 {
2081         u32 y_addr;
2082         u32 uv_addr;
2083         unsigned int off;
2084
2085         off = win->id * 0x40;
2086         /*win->smem_start + win->y_offset; */
2087         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2088         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
2089         DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
2090             lcdc_dev->id, win->id, y_addr, uv_addr);
2091         DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
2092             win->area[0].y_offset, win->area[0].c_offset);
2093         spin_lock(&lcdc_dev->reg_lock);
2094         if (likely(lcdc_dev->clk_on)) {
2095                 win->area[0].y_addr = y_addr;
2096                 win->area[0].uv_addr = uv_addr;
2097                 lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
2098                 lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
2099                 if (win->area[0].fbdc_en == 1)
2100                         lcdc_writel(lcdc_dev, IFBDC_BASE_ADDR,
2101                                         win->area[0].y_addr);
2102         }
2103         spin_unlock(&lcdc_dev->reg_lock);
2104
2105         return 0;
2106 }
2107
2108 static int win_2_3_display(struct lcdc_device *lcdc_dev,
2109                            struct rk_lcdc_win *win)
2110 {
2111         u32 i, y_addr;
2112         unsigned int off;
2113
2114         off = (win->id - 2) * 0x50;
2115         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2116         DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id);
2117
2118         spin_lock(&lcdc_dev->reg_lock);
2119         if (likely(lcdc_dev->clk_on)) {
2120                 for (i = 0; i < win->area_num; i++) {
2121                         DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2122                             i, win->area[i].y_addr, win->area[i].y_offset);
2123                         win->area[i].y_addr =
2124                             win->area[i].smem_start + win->area[i].y_offset;
2125                         }
2126                 lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr);
2127                 lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr);
2128                 lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr);
2129                 lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr);
2130                 if (win->area[0].fbdc_en == 1)
2131                         lcdc_writel(lcdc_dev, IFBDC_BASE_ADDR,
2132                                         win->area[0].y_addr);
2133         }
2134         spin_unlock(&lcdc_dev->reg_lock);
2135         return 0;
2136 }
2137
2138 static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win)
2139 {
2140         u32 y_addr;
2141
2142         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2143         DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2144             lcdc_dev->id, __func__, y_addr);
2145         spin_lock(&lcdc_dev->reg_lock);
2146         if (likely(lcdc_dev->clk_on)) {
2147                 win->area[0].y_addr = y_addr;
2148                 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
2149         }
2150         spin_unlock(&lcdc_dev->reg_lock);
2151
2152         return 0;
2153 }
2154
2155 static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2156 {
2157         struct lcdc_device *lcdc_dev =
2158             container_of(dev_drv, struct lcdc_device, driver);
2159         struct rk_lcdc_win *win = NULL;
2160         struct rk_screen *screen = dev_drv->cur_screen;
2161
2162 #if defined(WAIT_FOR_SYNC)
2163         int timeout;
2164         unsigned long flags;
2165 #endif
2166         win = dev_drv->win[win_id];
2167         if (!screen) {
2168                 dev_err(dev_drv->dev, "screen is null!\n");
2169                 return -ENOENT;
2170         }
2171         if (win_id == 0) {
2172                 win_0_1_display(lcdc_dev, win);
2173         } else if (win_id == 1) {
2174                 win_0_1_display(lcdc_dev, win);
2175         } else if (win_id == 2) {
2176                 win_2_3_display(lcdc_dev, win);
2177         } else if (win_id == 3) {
2178                 win_2_3_display(lcdc_dev, win);
2179         } else if (win_id == 4) {
2180                 hwc_display(lcdc_dev, win);
2181         } else {
2182                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2183                 return -EINVAL;
2184         }
2185
2186         /*this is the first frame of the system ,enable frame start interrupt */
2187         if ((dev_drv->first_frame)) {
2188                 dev_drv->first_frame = 0;
2189                 rk3368_lcdc_enable_irq(dev_drv);
2190         }
2191 #if defined(WAIT_FOR_SYNC)
2192         spin_lock_irqsave(&dev_drv->cpl_lock, flags);
2193         init_completion(&dev_drv->frame_done);
2194         spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
2195         timeout =
2196             wait_for_completion_timeout(&dev_drv->frame_done,
2197                                         msecs_to_jiffies(dev_drv->
2198                                                          cur_screen->ft + 5));
2199         if (!timeout && (!dev_drv->frame_done.done)) {
2200                 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
2201                 return -ETIMEDOUT;
2202         }
2203 #endif
2204         return 0;
2205 }
2206
2207 static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
2208 {
2209         u16 srcW;
2210         u16 srcH;
2211         u16 dstW;
2212         u16 dstH;
2213         u16 yrgb_srcW;
2214         u16 yrgb_srcH;
2215         u16 yrgb_dstW;
2216         u16 yrgb_dstH;
2217         u32 yrgb_vscalednmult;
2218         u32 yrgb_xscl_factor;
2219         u32 yrgb_yscl_factor;
2220         u8 yrgb_vsd_bil_gt2 = 0;
2221         u8 yrgb_vsd_bil_gt4 = 0;
2222
2223         u16 cbcr_srcW;
2224         u16 cbcr_srcH;
2225         u16 cbcr_dstW;
2226         u16 cbcr_dstH;
2227         u32 cbcr_vscalednmult;
2228         u32 cbcr_xscl_factor;
2229         u32 cbcr_yscl_factor;
2230         u8 cbcr_vsd_bil_gt2 = 0;
2231         u8 cbcr_vsd_bil_gt4 = 0;
2232         u8 yuv_fmt = 0;
2233
2234         srcW = win->area[0].xact;
2235         srcH = win->area[0].yact;
2236         dstW = win->area[0].xsize;
2237         dstH = win->area[0].ysize;
2238
2239         /*yrgb scl mode */
2240         yrgb_srcW = srcW;
2241         yrgb_srcH = srcH;
2242         yrgb_dstW = dstW;
2243         yrgb_dstH = dstH;
2244         if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2245                 pr_err("ERROR: yrgb scale exceed 8,");
2246                 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2247                        yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2248         }
2249         if (yrgb_srcW < yrgb_dstW)
2250                 win->yrgb_hor_scl_mode = SCALE_UP;
2251         else if (yrgb_srcW > yrgb_dstW)
2252                 win->yrgb_hor_scl_mode = SCALE_DOWN;
2253         else
2254                 win->yrgb_hor_scl_mode = SCALE_NONE;
2255
2256         if (yrgb_srcH < yrgb_dstH)
2257                 win->yrgb_ver_scl_mode = SCALE_UP;
2258         else if (yrgb_srcH > yrgb_dstH)
2259                 win->yrgb_ver_scl_mode = SCALE_DOWN;
2260         else
2261                 win->yrgb_ver_scl_mode = SCALE_NONE;
2262
2263         /*cbcr scl mode */
2264         switch (win->area[0].format) {
2265         case YUV422:
2266         case YUV422_A:
2267                 cbcr_srcW = srcW / 2;
2268                 cbcr_dstW = dstW;
2269                 cbcr_srcH = srcH;
2270                 cbcr_dstH = dstH;
2271                 yuv_fmt = 1;
2272                 break;
2273         case YUV420:
2274         case YUV420_A:
2275                 cbcr_srcW = srcW / 2;
2276                 cbcr_dstW = dstW;
2277                 cbcr_srcH = srcH / 2;
2278                 cbcr_dstH = dstH;
2279                 yuv_fmt = 1;
2280                 break;
2281         case YUV444:
2282         case YUV444_A:
2283                 cbcr_srcW = srcW;
2284                 cbcr_dstW = dstW;
2285                 cbcr_srcH = srcH;
2286                 cbcr_dstH = dstH;
2287                 yuv_fmt = 1;
2288                 break;
2289         default:
2290                 cbcr_srcW = 0;
2291                 cbcr_dstW = 0;
2292                 cbcr_srcH = 0;
2293                 cbcr_dstH = 0;
2294                 yuv_fmt = 0;
2295                 break;
2296         }
2297         if (yuv_fmt) {
2298                 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2299                     (cbcr_dstH * 8 <= cbcr_srcH)) {
2300                         pr_err("ERROR: cbcr scale exceed 8,");
2301                         pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2302                                cbcr_srcH, cbcr_dstW, cbcr_dstH);
2303                 }
2304         }
2305
2306         if (cbcr_srcW < cbcr_dstW)
2307                 win->cbr_hor_scl_mode = SCALE_UP;
2308         else if (cbcr_srcW > cbcr_dstW)
2309                 win->cbr_hor_scl_mode = SCALE_DOWN;
2310         else
2311                 win->cbr_hor_scl_mode = SCALE_NONE;
2312
2313         if (cbcr_srcH < cbcr_dstH)
2314                 win->cbr_ver_scl_mode = SCALE_UP;
2315         else if (cbcr_srcH > cbcr_dstH)
2316                 win->cbr_ver_scl_mode = SCALE_DOWN;
2317         else
2318                 win->cbr_ver_scl_mode = SCALE_NONE;
2319
2320         /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
2321             "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
2322             "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW,
2323             srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH,
2324             win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW,
2325             cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode,
2326             win->cbr_ver_scl_mode);*/
2327
2328         /*line buffer mode */
2329         if ((win->area[0].format == YUV422) ||
2330             (win->area[0].format == YUV420) ||
2331             (win->area[0].format == YUV422_A) ||
2332             (win->area[0].format == YUV420_A)) {
2333                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2334                         if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2335                             (cbcr_dstW == 0))
2336                                 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2337                                        cbcr_dstW);
2338                         else if (cbcr_dstW > 1280)
2339                                 win->win_lb_mode = LB_YUV_3840X5;
2340                         else
2341                                 win->win_lb_mode = LB_YUV_2560X8;
2342                 } else {        /*SCALE_UP or SCALE_NONE */
2343                         if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2344                             (cbcr_srcW == 0))
2345                                 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2346                                        cbcr_srcW);
2347                         else if (cbcr_srcW > 1280)
2348                                 win->win_lb_mode = LB_YUV_3840X5;
2349                         else
2350                                 win->win_lb_mode = LB_YUV_2560X8;
2351                 }
2352         } else {
2353                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2354                         if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2355                             (yrgb_dstW == 0))
2356                                 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2357                         else if (yrgb_dstW > 2560)
2358                                 win->win_lb_mode = LB_RGB_3840X2;
2359                         else if (yrgb_dstW > 1920)
2360                                 win->win_lb_mode = LB_RGB_2560X4;
2361                         else if (yrgb_dstW > 1280)
2362                                 win->win_lb_mode = LB_RGB_1920X5;
2363                         else
2364                                 win->win_lb_mode = LB_RGB_1280X8;
2365                 } else {        /*SCALE_UP or SCALE_NONE */
2366                         if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2367                             (yrgb_srcW == 0))
2368                                 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2369                         else if (yrgb_srcW > 2560)
2370                                 win->win_lb_mode = LB_RGB_3840X2;
2371                         else if (yrgb_srcW > 1920)
2372                                 win->win_lb_mode = LB_RGB_2560X4;
2373                         else if (yrgb_srcW > 1280)
2374                                 win->win_lb_mode = LB_RGB_1920X5;
2375                         else
2376                                 win->win_lb_mode = LB_RGB_1280X8;
2377                 }
2378         }
2379         DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2380
2381         /*vsd/vsu scale ALGORITHM */
2382         win->yrgb_hsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2383         win->cbr_hsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2384         win->yrgb_vsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2385         win->cbr_vsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2386         switch (win->win_lb_mode) {
2387         case LB_YUV_3840X5:
2388         case LB_YUV_2560X8:
2389         case LB_RGB_1920X5:
2390         case LB_RGB_1280X8:
2391                 win->yrgb_vsu_mode = SCALE_UP_BIC;
2392                 win->cbr_vsu_mode = SCALE_UP_BIC;
2393                 break;
2394         case LB_RGB_3840X2:
2395                 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2396                         pr_err("ERROR : not allow yrgb ver scale\n");
2397                 if (win->cbr_ver_scl_mode != SCALE_NONE)
2398                         pr_err("ERROR : not allow cbcr ver scale\n");
2399                 break;
2400         case LB_RGB_2560X4:
2401                 win->yrgb_vsu_mode = SCALE_UP_BIL;
2402                 win->cbr_vsu_mode = SCALE_UP_BIL;
2403                 break;
2404         default:
2405                 pr_info("%s:un supported win_lb_mode:%d\n",
2406                         __func__, win->win_lb_mode);
2407                 break;
2408         }
2409         if (win->mirror_en == 1) {      /*interlace mode must bill */
2410                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2411         }
2412
2413         if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2414             (win->area[0].fbdc_en == 1)) {
2415                 /*in this pattern,use bil mode,not support souble scd,
2416                 use avg mode, support double scd, but aclk should be
2417                 bigger than dclk,aclk>>dclk */
2418                 if (yrgb_srcH >= 2 * yrgb_dstH) {
2419                         pr_err("ERROR : fbdc mode,not support y scale down:");
2420                         pr_err("srcH[%d] > 2 *dstH[%d]\n",
2421                                yrgb_srcH, yrgb_dstH);
2422                 }
2423         }
2424         DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2425             win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2426             win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2427
2428         /*SCALE FACTOR */
2429
2430         /*(1.1)YRGB HOR SCALE FACTOR */
2431         switch (win->yrgb_hor_scl_mode) {
2432         case SCALE_NONE:
2433                 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2434                 break;
2435         case SCALE_UP:
2436                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2437                 break;
2438         case SCALE_DOWN:
2439                 switch (win->yrgb_hsd_mode) {
2440                 case SCALE_DOWN_BIL:
2441                         yrgb_xscl_factor =
2442                             GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2443                         break;
2444                 case SCALE_DOWN_AVG:
2445                         yrgb_xscl_factor =
2446                             GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2447                         break;
2448                 default:
2449                         pr_info(
2450                                 "%s:un supported yrgb_hsd_mode:%d\n", __func__,
2451                                win->yrgb_hsd_mode);
2452                         break;
2453                 }
2454                 break;
2455         default:
2456                 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2457                         __func__, win->yrgb_hor_scl_mode);
2458                 break;
2459         }                       /*win->yrgb_hor_scl_mode */
2460
2461         /*(1.2)YRGB VER SCALE FACTOR */
2462         switch (win->yrgb_ver_scl_mode) {
2463         case SCALE_NONE:
2464                 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2465                 break;
2466         case SCALE_UP:
2467                 switch (win->yrgb_vsu_mode) {
2468                 case SCALE_UP_BIL:
2469                         yrgb_yscl_factor =
2470                             GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2471                         break;
2472                 case SCALE_UP_BIC:
2473                         if (yrgb_srcH < 3) {
2474                                 pr_err("yrgb_srcH should be");
2475                                 pr_err(" greater than 3 !!!\n");
2476                         }
2477                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2478                                                                 yrgb_dstH);
2479                         break;
2480                 default:
2481                         pr_info("%s:un support yrgb_vsu_mode:%d\n",
2482                                 __func__, win->yrgb_vsu_mode);
2483                         break;
2484                 }
2485                 break;
2486         case SCALE_DOWN:
2487                 switch (win->yrgb_vsd_mode) {
2488                 case SCALE_DOWN_BIL:
2489                         yrgb_vscalednmult =
2490                             rk3368_get_hard_ware_vskiplines(yrgb_srcH,
2491                                                             yrgb_dstH);
2492                         yrgb_yscl_factor =
2493                             GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2494                                                            yrgb_vscalednmult);
2495                         if (yrgb_yscl_factor >= 0x2000) {
2496                                 pr_err("yrgb_yscl_factor should be ");
2497                                 pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n",
2498                                        yrgb_yscl_factor);
2499                         }
2500                         if (yrgb_vscalednmult == 4) {
2501                                 yrgb_vsd_bil_gt4 = 1;
2502                                 yrgb_vsd_bil_gt2 = 0;
2503                         } else if (yrgb_vscalednmult == 2) {
2504                                 yrgb_vsd_bil_gt4 = 0;
2505                                 yrgb_vsd_bil_gt2 = 1;
2506                         } else {
2507                                 yrgb_vsd_bil_gt4 = 0;
2508                                 yrgb_vsd_bil_gt2 = 0;
2509                         }
2510                         break;
2511                 case SCALE_DOWN_AVG:
2512                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2513                                                                  yrgb_dstH);
2514                         break;
2515                 default:
2516                         pr_info("%s:un support yrgb_vsd_mode:%d\n",
2517                                 __func__, win->yrgb_vsd_mode);
2518                         break;
2519                 }               /*win->yrgb_vsd_mode */
2520                 break;
2521         default:
2522                 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2523                         __func__, win->yrgb_ver_scl_mode);
2524                 break;
2525         }
2526         win->scale_yrgb_x = yrgb_xscl_factor;
2527         win->scale_yrgb_y = yrgb_yscl_factor;
2528         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2529         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2530         DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2531             yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2532
2533         /*(2.1)CBCR HOR SCALE FACTOR */
2534         switch (win->cbr_hor_scl_mode) {
2535         case SCALE_NONE:
2536                 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2537                 break;
2538         case SCALE_UP:
2539                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2540                 break;
2541         case SCALE_DOWN:
2542                 switch (win->cbr_hsd_mode) {
2543                 case SCALE_DOWN_BIL:
2544                         cbcr_xscl_factor =
2545                             GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2546                         break;
2547                 case SCALE_DOWN_AVG:
2548                         cbcr_xscl_factor =
2549                             GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2550                         break;
2551                 default:
2552                         pr_info("%s:un support cbr_hsd_mode:%d\n",
2553                                 __func__, win->cbr_hsd_mode);
2554                         break;
2555                 }
2556                 break;
2557         default:
2558                 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2559                         __func__, win->cbr_hor_scl_mode);
2560                 break;
2561         }                       /*win->cbr_hor_scl_mode */
2562
2563         /*(2.2)CBCR VER SCALE FACTOR */
2564         switch (win->cbr_ver_scl_mode) {
2565         case SCALE_NONE:
2566                 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2567                 break;
2568         case SCALE_UP:
2569                 switch (win->cbr_vsu_mode) {
2570                 case SCALE_UP_BIL:
2571                         cbcr_yscl_factor =
2572                             GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2573                         break;
2574                 case SCALE_UP_BIC:
2575                         if (cbcr_srcH < 3) {
2576                                 pr_err("cbcr_srcH should be ");
2577                                 pr_err("greater than 3 !!!\n");
2578                         }
2579                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2580                                                                 cbcr_dstH);
2581                         break;
2582                 default:
2583                         pr_info("%s:un support cbr_vsu_mode:%d\n",
2584                                 __func__, win->cbr_vsu_mode);
2585                         break;
2586                 }
2587                 break;
2588         case SCALE_DOWN:
2589                 switch (win->cbr_vsd_mode) {
2590                 case SCALE_DOWN_BIL:
2591                         cbcr_vscalednmult =
2592                             rk3368_get_hard_ware_vskiplines(cbcr_srcH,
2593                                                             cbcr_dstH);
2594                         cbcr_yscl_factor =
2595                             GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2596                                                            cbcr_vscalednmult);
2597                         if (cbcr_yscl_factor >= 0x2000) {
2598                                 pr_err("cbcr_yscl_factor should be less ");
2599                                 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2600                                        cbcr_yscl_factor);
2601                         }
2602
2603                         if (cbcr_vscalednmult == 4) {
2604                                 cbcr_vsd_bil_gt4 = 1;
2605                                 cbcr_vsd_bil_gt2 = 0;
2606                         } else if (cbcr_vscalednmult == 2) {
2607                                 cbcr_vsd_bil_gt4 = 0;
2608                                 cbcr_vsd_bil_gt2 = 1;
2609                         } else {
2610                                 cbcr_vsd_bil_gt4 = 0;
2611                                 cbcr_vsd_bil_gt2 = 0;
2612                         }
2613                         break;
2614                 case SCALE_DOWN_AVG:
2615                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2616                                                                  cbcr_dstH);
2617                         break;
2618                 default:
2619                         pr_info("%s:un support cbr_vsd_mode:%d\n",
2620                                 __func__, win->cbr_vsd_mode);
2621                         break;
2622                 }
2623                 break;
2624         default:
2625                 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2626                         __func__, win->cbr_ver_scl_mode);
2627                 break;
2628         }
2629         win->scale_cbcr_x = cbcr_xscl_factor;
2630         win->scale_cbcr_y = cbcr_yscl_factor;
2631         win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2632         win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2633
2634         DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2635             cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2636         return 0;
2637 }
2638
2639 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2640                      struct rk_lcdc_win_area *area)
2641 {
2642         int pos;
2643
2644         if (screen->x_mirror && mirror_en)
2645                 pr_err("not support both win and global mirror\n");
2646
2647         if ((!mirror_en) && (!screen->x_mirror))
2648                 pos = area->xpos + screen->mode.left_margin +
2649                         screen->mode.hsync_len;
2650         else
2651                 pos = screen->mode.xres - area->xpos -
2652                         area->xsize + screen->mode.left_margin +
2653                         screen->mode.hsync_len;
2654
2655         return pos;
2656 }
2657
2658 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2659                      struct rk_lcdc_win_area *area)
2660 {
2661         int pos;
2662
2663         if (screen->y_mirror && mirror_en)
2664                 pr_err("not support both win and global mirror\n");
2665         if (screen->mode.vmode == FB_VMODE_NONINTERLACED) {
2666                 if ((!mirror_en) && (!screen->y_mirror))
2667                         pos = area->ypos + screen->mode.upper_margin +
2668                                 screen->mode.vsync_len;
2669                 else
2670                         pos = screen->mode.yres - area->ypos -
2671                                 area->ysize + screen->mode.upper_margin +
2672                                 screen->mode.vsync_len;
2673         } else if (screen->mode.vmode == FB_VMODE_INTERLACED) {
2674                 pos = area->ypos / 2 + screen->mode.upper_margin +
2675                         screen->mode.vsync_len;
2676                 area->ysize /= 2;
2677         }
2678
2679         return pos;
2680 }
2681
2682 static int win_0_1_set_par(struct lcdc_device *lcdc_dev,
2683                            struct rk_screen *screen, struct rk_lcdc_win *win)
2684 {
2685         u32 xact, yact, xvir, yvir, xpos, ypos;
2686         u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2687         char fmt[9] = "NULL";
2688
2689         xpos = dsp_x_pos(win->mirror_en, screen, &win->area[0]);
2690         ypos = dsp_y_pos(win->mirror_en, screen, &win->area[0]);
2691
2692         spin_lock(&lcdc_dev->reg_lock);
2693         if (likely(lcdc_dev->clk_on)) {
2694                 rk3368_lcdc_cal_scl_fac(win);   /*fac,lb,gt2,gt4 */
2695                 switch (win->area[0].format) {
2696                 case FBDC_RGB_565:
2697                         fmt_cfg = 2;
2698                         swap_rb = 0;
2699                         win->fmt_10 = 0;
2700                         win->area[0].fbdc_fmt_cfg = 0x05;
2701                         break;
2702                 case FBDC_ARGB_888:
2703                         fmt_cfg = 0;
2704                         swap_rb = 0;
2705                         win->fmt_10 = 0;
2706                         win->area[0].fbdc_fmt_cfg = 0x0c;
2707                         break;
2708                 case FBDC_ABGR_888:
2709                         fmt_cfg = 0;
2710                         swap_rb = 1;
2711                         win->fmt_10 = 0;
2712                         win->area[0].fbdc_fmt_cfg = 0x0c;
2713                         break;
2714                 case FBDC_RGBX_888:
2715                         fmt_cfg = 0;
2716                         swap_rb = 0;
2717                         win->fmt_10 = 0;
2718                         win->area[0].fbdc_fmt_cfg = 0x3a;
2719                         break;
2720                 case ARGB888:
2721                         fmt_cfg = 0;
2722                         swap_rb = 0;
2723                         win->fmt_10 = 0;
2724                         break;
2725                 case XBGR888:
2726                 case ABGR888:
2727                         fmt_cfg = 0;
2728                         swap_rb = 1;
2729                         win->fmt_10 = 0;
2730                         break;
2731                 case RGB888:
2732                         fmt_cfg = 1;
2733                         swap_rb = 0;
2734                         win->fmt_10 = 0;
2735                         break;
2736                 case RGB565:
2737                         fmt_cfg = 2;
2738                         swap_rb = 0;
2739                         win->fmt_10 = 0;
2740                         break;
2741                 case YUV422:
2742                         fmt_cfg = 5;
2743                         swap_rb = 0;
2744                         win->fmt_10 = 0;
2745                         break;
2746                 case YUV420:
2747                         fmt_cfg = 4;
2748                         swap_rb = 0;
2749                         win->fmt_10 = 0;
2750                         break;
2751                 case YUV420_NV21:
2752                         fmt_cfg = 4;
2753                         swap_rb = 0;
2754                         swap_uv = 1;
2755                         win->fmt_10 = 0;
2756                         break;
2757                 case YUV444:
2758                         fmt_cfg = 6;
2759                         swap_rb = 0;
2760                         win->fmt_10 = 0;
2761                         break;
2762                 case YUV422_A:
2763                         fmt_cfg = 5;
2764                         swap_rb = 0;
2765                         win->fmt_10 = 1;
2766                         break;
2767                 case YUV420_A:
2768                         fmt_cfg = 4;
2769                         swap_rb = 0;
2770                         win->fmt_10 = 1;
2771                         break;
2772                 case YUV444_A:
2773                         fmt_cfg = 6;
2774                         swap_rb = 0;
2775                         win->fmt_10 = 1;
2776                         break;
2777                 default:
2778                         dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n",
2779                                 __func__);
2780                         break;
2781                 }
2782                 win->area[0].fmt_cfg = fmt_cfg;
2783                 win->area[0].swap_rb = swap_rb;
2784                 win->area[0].swap_uv = swap_uv;
2785                 win->area[0].dsp_stx = xpos;
2786                 win->area[0].dsp_sty = ypos;
2787                 xact = win->area[0].xact;
2788                 yact = win->area[0].yact;
2789                 xvir = win->area[0].xvir;
2790                 yvir = win->area[0].yvir;
2791         }
2792         if (win->area[0].fbdc_en)
2793                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2794         rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id);
2795         spin_unlock(&lcdc_dev->reg_lock);
2796
2797         DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2798             lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2799             xact, yact, win->area[0].xsize);
2800         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2801             win->area[0].ysize, xvir, yvir, xpos, ypos);
2802
2803         return 0;
2804 }
2805
2806
2807 static int win_2_3_set_par(struct lcdc_device *lcdc_dev,
2808                            struct rk_screen *screen, struct rk_lcdc_win *win)
2809 {
2810         int i;
2811         u8 fmt_cfg, swap_rb;
2812         char fmt[9] = "NULL";
2813
2814         if (win->mirror_en)
2815                 pr_err("win[%d] not support y mirror\n", win->id);
2816         spin_lock(&lcdc_dev->reg_lock);
2817         if (likely(lcdc_dev->clk_on)) {
2818                 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id);
2819                 for (i = 0; i < win->area_num; i++) {
2820                         switch (win->area[i].format) {
2821                         case FBDC_RGB_565:
2822                                 fmt_cfg = 2;
2823                                 swap_rb = 0;
2824                                 win->fmt_10 = 0;
2825                                 win->area[0].fbdc_fmt_cfg = 0x05;
2826                                 break;
2827                         case FBDC_ARGB_888:
2828                                 fmt_cfg = 0;
2829                                 swap_rb = 0;
2830                                 win->fmt_10 = 0;
2831                                 win->area[0].fbdc_fmt_cfg = 0x0c;
2832                                 break;
2833                         case FBDC_RGBX_888:
2834                                 fmt_cfg = 0;
2835                                 swap_rb = 0;
2836                                 win->fmt_10 = 0;
2837                                 win->area[0].fbdc_fmt_cfg = 0x3a;
2838                                 break;
2839                         case ARGB888:
2840                                 fmt_cfg = 0;
2841                                 swap_rb = 0;
2842                                 break;
2843                         case XBGR888:
2844                         case ABGR888:
2845                                 fmt_cfg = 0;
2846                                 swap_rb = 1;
2847                                 break;
2848                         case RGB888:
2849                                 fmt_cfg = 1;
2850                                 swap_rb = 0;
2851                                 break;
2852                         case RGB565:
2853                                 fmt_cfg = 2;
2854                                 swap_rb = 0;
2855                                 break;
2856                         default:
2857                                 dev_err(lcdc_dev->driver.dev,
2858                                         "%s:un supported format!\n", __func__);
2859                                 break;
2860                         }
2861                         win->area[i].fmt_cfg = fmt_cfg;
2862                         win->area[i].swap_rb = swap_rb;
2863                         win->area[i].dsp_stx =
2864                                         dsp_x_pos(win->mirror_en, screen,
2865                                                   &win->area[i]);
2866                         win->area[i].dsp_sty =
2867                                         dsp_y_pos(win->mirror_en, screen,
2868                                                   &win->area[i]);
2869                         if ((win->area[i].xact != win->area[i].xsize) ||
2870                             (win->area[i].yact != win->area[i].ysize)) {
2871                                 pr_err("win[%d]->area[%d],not support scale\n",
2872                                         win->id, i);
2873                                 pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
2874                                         win->area[i].xact,win->area[i].yact,
2875                                         win->area[i].xsize,win->area[i].ysize);
2876                                 win->area[i].xsize = win->area[i].xact;
2877                                 win->area[i].ysize = win->area[i].yact;
2878                         }
2879                         DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
2880                             get_format_string(win->area[i].format, fmt),
2881                             win->area[i].xsize, win->area[i].ysize,
2882                             win->area[i].xpos, win->area[i].ypos);
2883                 }
2884         }
2885         if (win->area[0].fbdc_en)
2886                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2887         rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id);
2888         spin_unlock(&lcdc_dev->reg_lock);
2889         return 0;
2890 }
2891
2892 static int hwc_set_par(struct lcdc_device *lcdc_dev,
2893                        struct rk_screen *screen, struct rk_lcdc_win *win)
2894 {
2895         u32 xact, yact, xvir, yvir, xpos, ypos;
2896         u8 fmt_cfg = 0, swap_rb;
2897         char fmt[9] = "NULL";
2898
2899         xpos = win->area[0].xpos + screen->mode.left_margin +
2900             screen->mode.hsync_len;
2901         ypos = win->area[0].ypos + screen->mode.upper_margin +
2902             screen->mode.vsync_len;
2903
2904         spin_lock(&lcdc_dev->reg_lock);
2905         if (likely(lcdc_dev->clk_on)) {
2906                 /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */
2907                 switch (win->area[0].format) {
2908                 case ARGB888:
2909                         fmt_cfg = 0;
2910                         swap_rb = 0;
2911                         break;
2912                 case XBGR888:
2913                 case ABGR888:
2914                         fmt_cfg = 0;
2915                         swap_rb = 1;
2916                         break;
2917                 case RGB888:
2918                         fmt_cfg = 1;
2919                         swap_rb = 0;
2920                         break;
2921                 case RGB565:
2922                         fmt_cfg = 2;
2923                         swap_rb = 0;
2924                         break;
2925                 default:
2926                         dev_err(lcdc_dev->driver.dev,
2927                                 "%s:un supported format!\n", __func__);
2928                         break;
2929                 }
2930                 win->area[0].fmt_cfg = fmt_cfg;
2931                 win->area[0].swap_rb = swap_rb;
2932                 win->area[0].dsp_stx = xpos;
2933                 win->area[0].dsp_sty = ypos;
2934                 xact = win->area[0].xact;
2935                 yact = win->area[0].yact;
2936                 xvir = win->area[0].xvir;
2937                 yvir = win->area[0].yvir;
2938         }
2939         rk3368_hwc_reg_update(&lcdc_dev->driver, 4);
2940         spin_unlock(&lcdc_dev->reg_lock);
2941
2942         DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2943             lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt),
2944             xact, yact, win->area[0].xsize);
2945         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2946             win->area[0].ysize, xvir, yvir, xpos, ypos);
2947         return 0;
2948 }
2949
2950 static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
2951 {
2952         struct lcdc_device *lcdc_dev =
2953             container_of(dev_drv, struct lcdc_device, driver);
2954         struct rk_lcdc_win *win = NULL;
2955         struct rk_screen *screen = dev_drv->cur_screen;
2956
2957         win = dev_drv->win[win_id];
2958         switch (win_id) {
2959         case 0:
2960                 win_0_1_set_par(lcdc_dev, screen, win);
2961                 break;
2962         case 1:
2963                 win_0_1_set_par(lcdc_dev, screen, win);
2964                 break;
2965         case 2:
2966                 win_2_3_set_par(lcdc_dev, screen, win);
2967                 break;
2968         case 3:
2969                 win_2_3_set_par(lcdc_dev, screen, win);
2970                 break;
2971         case 4:
2972                 hwc_set_par(lcdc_dev, screen, win);
2973                 break;
2974         default:
2975                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2976                 break;
2977         }
2978         return 0;
2979 }
2980
2981 static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2982                              unsigned long arg, int win_id)
2983 {
2984         struct lcdc_device *lcdc_dev =
2985             container_of(dev_drv, struct lcdc_device, driver);
2986         u32 panel_size[2];
2987         void __user *argp = (void __user *)arg;
2988         struct color_key_cfg clr_key_cfg;
2989
2990         switch (cmd) {
2991         case RK_FBIOGET_PANEL_SIZE:
2992                 panel_size[0] = lcdc_dev->screen->mode.xres;
2993                 panel_size[1] = lcdc_dev->screen->mode.yres;
2994                 if (copy_to_user(argp, panel_size, 8))
2995                         return -EFAULT;
2996                 break;
2997         case RK_FBIOPUT_COLOR_KEY_CFG:
2998                 if (copy_from_user(&clr_key_cfg, argp,
2999                                    sizeof(struct color_key_cfg)))
3000                         return -EFAULT;
3001                 rk3368_lcdc_clr_key_cfg(dev_drv);
3002                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
3003                             clr_key_cfg.win0_color_key_cfg);
3004                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
3005                             clr_key_cfg.win1_color_key_cfg);
3006                 break;
3007
3008         default:
3009                 break;
3010         }
3011         return 0;
3012 }
3013
3014 static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
3015 {
3016         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3017                                                     struct lcdc_device, driver);
3018         /*struct device_node *backlight;*/
3019
3020         if (lcdc_dev->backlight)
3021                 return 0;
3022 #if 0
3023         backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0);
3024         if (backlight) {
3025                 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
3026                 if (!lcdc_dev->backlight)
3027                         dev_info(lcdc_dev->dev, "No find backlight device\n");
3028         } else {
3029                 dev_info(lcdc_dev->dev, "No find backlight device node\n");
3030         }
3031 #endif
3032         return 0;
3033 }
3034
3035 static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
3036 {
3037         struct lcdc_device *lcdc_dev =
3038             container_of(dev_drv, struct lcdc_device, driver);
3039         if (dev_drv->suspend_flag)
3040                 return 0;
3041         /* close the backlight */
3042         /*rk3368_lcdc_get_backlight_device(dev_drv);
3043         if (lcdc_dev->backlight) {
3044                 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
3045                 backlight_update_status(lcdc_dev->backlight);
3046         }*/
3047
3048         dev_drv->suspend_flag = 1;
3049         flush_kthread_worker(&dev_drv->update_regs_worker);
3050
3051         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3052                 dev_drv->trsm_ops->disable();
3053
3054         spin_lock(&lcdc_dev->reg_lock);
3055         if (likely(lcdc_dev->clk_on)) {
3056                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3057                              v_DSP_BLANK_EN(1));
3058                 lcdc_msk_reg(lcdc_dev,
3059                              INTR_CLEAR, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR,
3060                              v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1));
3061                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3062                              v_DSP_OUT_ZERO(1));
3063                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
3064                 lcdc_cfg_done(lcdc_dev);
3065
3066                 if (dev_drv->iommu_enabled) {
3067                         if (dev_drv->mmu_dev)
3068                                 rockchip_iovmm_deactivate(dev_drv->dev);
3069                 }
3070
3071                 spin_unlock(&lcdc_dev->reg_lock);
3072         } else {
3073                 spin_unlock(&lcdc_dev->reg_lock);
3074                 return 0;
3075         }
3076         rk3368_lcdc_clk_disable(lcdc_dev);
3077         rk_disp_pwr_disable(dev_drv);
3078         return 0;
3079 }
3080
3081 static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
3082 {
3083         struct lcdc_device *lcdc_dev =
3084             container_of(dev_drv, struct lcdc_device, driver);
3085
3086         if (!dev_drv->suspend_flag)
3087                 return 0;
3088         rk_disp_pwr_enable(dev_drv);
3089         dev_drv->suspend_flag = 0;
3090
3091         if (1/*lcdc_dev->atv_layer_cnt*/) {
3092                 rk3368_lcdc_clk_enable(lcdc_dev);
3093                 rk3368_lcdc_reg_restore(lcdc_dev);
3094
3095                 spin_lock(&lcdc_dev->reg_lock);
3096                 if (dev_drv->cur_screen->dsp_lut)
3097                         rk3368_lcdc_set_lut(dev_drv,
3098                                             dev_drv->cur_screen->dsp_lut);
3099                 if (dev_drv->cur_screen->cabc_lut)
3100                         rk3368_set_cabc_lut(dev_drv,
3101                                             dev_drv->cur_screen->cabc_lut);
3102
3103                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3104                              v_DSP_OUT_ZERO(0));
3105                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
3106                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3107                              v_DSP_BLANK_EN(0));
3108                 lcdc_cfg_done(lcdc_dev);
3109
3110                 if (dev_drv->iommu_enabled) {
3111                         if (dev_drv->mmu_dev)
3112                                 rockchip_iovmm_activate(dev_drv->dev);
3113                 }
3114
3115                 spin_unlock(&lcdc_dev->reg_lock);
3116         }
3117
3118         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3119                 dev_drv->trsm_ops->enable();
3120         return 0;
3121 }
3122
3123 static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv,
3124                              int win_id, int blank_mode)
3125 {
3126         switch (blank_mode) {
3127         case FB_BLANK_UNBLANK:
3128                 rk3368_lcdc_early_resume(dev_drv);
3129                 break;
3130         case FB_BLANK_NORMAL:
3131                 rk3368_lcdc_early_suspend(dev_drv);
3132                 break;
3133         default:
3134                 rk3368_lcdc_early_suspend(dev_drv);
3135                 break;
3136         }
3137
3138         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
3139
3140         return 0;
3141 }
3142
3143 static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
3144 {
3145         struct lcdc_device *lcdc_dev =
3146             container_of(dev_drv, struct lcdc_device, driver);
3147         int win_status = 0;
3148         if (win_id == 0)
3149                 win_status = lcdc_read_bit(lcdc_dev, WIN0_CTRL0, m_WIN0_EN);
3150         else if (win_id == 1)
3151                 win_status = lcdc_read_bit(lcdc_dev, WIN1_CTRL0, m_WIN1_EN);
3152         else if (win_id == 2)
3153                 win_status = lcdc_read_bit(lcdc_dev, WIN2_CTRL0, m_WIN2_EN);
3154         else if (win_id == 3)
3155                 win_status = lcdc_read_bit(lcdc_dev, WIN3_CTRL0, m_WIN3_EN);
3156         else if (win_id == 4)
3157                 win_status = lcdc_read_bit(lcdc_dev, HWC_CTRL0, m_HWC_EN);
3158         else
3159                 pr_err("!!!%s,win_id :%d,unsupport!!!\n",__func__,win_id);
3160
3161         return win_status;
3162 }
3163
3164 /*overlay will be do at regupdate*/
3165 static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
3166                                bool set)
3167 {
3168         struct lcdc_device *lcdc_dev =
3169             container_of(dev_drv, struct lcdc_device, driver);
3170         struct rk_lcdc_win *win = NULL;
3171         int i, ovl;
3172         unsigned int mask, val;
3173         int z_order_num = 0;
3174         int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3175
3176         if (swap == 0) {
3177                 for (i = 0; i < 4; i++) {
3178                         win = dev_drv->win[i];
3179                         if (win->state == 1)
3180                                 z_order_num++;
3181                 }
3182                 for (i = 0; i < 4; i++) {
3183                         win = dev_drv->win[i];
3184                         if (win->state == 0)
3185                                 win->z_order = z_order_num++;
3186                         switch (win->z_order) {
3187                         case 0:
3188                                 layer0_sel = win->id;
3189                                 break;
3190                         case 1:
3191                                 layer1_sel = win->id;
3192                                 break;
3193                         case 2:
3194                                 layer2_sel = win->id;
3195                                 break;
3196                         case 3:
3197                                 layer3_sel = win->id;
3198                                 break;
3199                         default:
3200                                 break;
3201                         }
3202                 }
3203         } else {
3204                 layer0_sel = swap % 10;
3205                 layer1_sel = swap / 10 % 10;
3206                 layer2_sel = swap / 100 % 10;
3207                 layer3_sel = swap / 1000;
3208         }
3209
3210         spin_lock(&lcdc_dev->reg_lock);
3211         if (lcdc_dev->clk_on) {
3212                 if (set) {
3213                         mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
3214                             m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
3215                         val = v_DSP_LAYER0_SEL(layer0_sel) |
3216                             v_DSP_LAYER1_SEL(layer1_sel) |
3217                             v_DSP_LAYER2_SEL(layer2_sel) |
3218                             v_DSP_LAYER3_SEL(layer3_sel);
3219                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
3220                 } else {
3221                         layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3222                                                    m_DSP_LAYER0_SEL);
3223                         layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3224                                                    m_DSP_LAYER1_SEL);
3225                         layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3226                                                    m_DSP_LAYER2_SEL);
3227                         layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3228                                                    m_DSP_LAYER3_SEL);
3229                         ovl = layer3_sel * 1000 + layer2_sel * 100 +
3230                             layer1_sel * 10 + layer0_sel;
3231                 }
3232         } else {
3233                 ovl = -EPERM;
3234         }
3235         spin_unlock(&lcdc_dev->reg_lock);
3236
3237         return ovl;
3238 }
3239
3240 static char *rk3368_lcdc_format_to_string(int format, char *fmt)
3241 {
3242         if (!fmt)
3243                 return NULL;
3244
3245         switch (format) {
3246         case 0:
3247                 strcpy(fmt, "ARGB888");
3248                 break;
3249         case 1:
3250                 strcpy(fmt, "RGB888");
3251                 break;
3252         case 2:
3253                 strcpy(fmt, "RGB565");
3254                 break;
3255         case 4:
3256                 strcpy(fmt, "YCbCr420");
3257                 break;
3258         case 5:
3259                 strcpy(fmt, "YCbCr422");
3260                 break;
3261         case 6:
3262                 strcpy(fmt, "YCbCr444");
3263                 break;
3264         default:
3265                 strcpy(fmt, "invalid\n");
3266                 break;
3267         }
3268         return fmt;
3269 }
3270 static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
3271                                          char *buf, int win_id)
3272 {
3273         struct lcdc_device *lcdc_dev =
3274             container_of(dev_drv, struct lcdc_device, driver);
3275         struct rk_screen *screen = dev_drv->cur_screen;
3276         u16 hsync_len = screen->mode.hsync_len;
3277         u16 left_margin = screen->mode.left_margin;
3278         u16 vsync_len = screen->mode.vsync_len;
3279         u16 upper_margin = screen->mode.upper_margin;
3280         u32 h_pw_bp = hsync_len + left_margin;
3281         u32 v_pw_bp = vsync_len + upper_margin;
3282         u32 fmt_id;
3283         char format_w0[9] = "NULL";
3284         char format_w1[9] = "NULL";
3285         char format_w2_0[9] = "NULL";
3286         char format_w2_1[9] = "NULL";
3287         char format_w2_2[9] = "NULL";
3288         char format_w2_3[9] = "NULL";
3289         char format_w3_0[9] = "NULL";
3290         char format_w3_1[9] = "NULL";
3291         char format_w3_2[9] = "NULL";
3292         char format_w3_3[9] = "NULL";
3293         char dsp_buf[100];
3294         u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3295         u32 y_factor, uv_factor;
3296         u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3297         u8 w0_state, w1_state, w2_state, w3_state;
3298         u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3299         u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3300
3301         u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3302         u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3303         u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3304         u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3305         u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3306         u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3307
3308         u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3309         u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3310         u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3311         u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3312         u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3313         u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3314         u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3315
3316         u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3317         u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3318         u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3319         u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3320         u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3321         u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3322         u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3323         u32 dclk_freq;
3324         int size = 0;
3325
3326         dclk_freq = screen->mode.pixclock;
3327         /*rk3368_lcdc_reg_dump(dev_drv); */
3328
3329         spin_lock(&lcdc_dev->reg_lock);
3330         if (lcdc_dev->clk_on) {
3331                 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
3332                 layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8;
3333                 layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10;
3334                 layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12;
3335                 layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14;
3336                 /*WIN0 */
3337                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3338                 w0_state = win_ctrl & m_WIN0_EN;
3339                 fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1;
3340                 rk3368_lcdc_format_to_string(fmt_id, format_w0);
3341                 vir_info = lcdc_readl(lcdc_dev, WIN0_VIR);
3342                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
3343                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
3344                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
3345                 y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
3346                 uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR);
3347                 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
3348                 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16;
3349                 w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1;
3350                 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1;
3351                 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1;
3352                 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1;
3353                 if (w0_state) {
3354                         w0_st_x = dsp_st & m_WIN0_DSP_XST;
3355                         w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16;
3356                 }
3357                 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
3358                 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16;
3359                 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
3360                 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16;
3361
3362                 /*WIN1 */
3363                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3364                 w1_state = win_ctrl & m_WIN1_EN;
3365                 fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1;
3366                 rk3368_lcdc_format_to_string(fmt_id, format_w1);
3367                 vir_info = lcdc_readl(lcdc_dev, WIN1_VIR);
3368                 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
3369                 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
3370                 dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
3371                 y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB);
3372                 uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR);
3373                 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
3374                 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16;
3375                 w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1;
3376                 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1;
3377                 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1;
3378                 w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1;
3379                 if (w1_state) {
3380                         w1_st_x = dsp_st & m_WIN1_DSP_XST;
3381                         w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16;
3382                 }
3383                 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
3384                 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16;
3385                 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
3386                 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16;
3387                 /*WIN2 */
3388                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3389                 w2_state = win_ctrl & m_WIN2_EN;
3390                 w2_0_state = (win_ctrl & 0x10) >> 4;
3391                 w2_1_state = (win_ctrl & 0x100) >> 8;
3392                 w2_2_state = (win_ctrl & 0x1000) >> 12;
3393                 w2_3_state = (win_ctrl & 0x10000) >> 16;
3394                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1);
3395                 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3396                 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16;
3397                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3);
3398                 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3399                 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16;
3400
3401                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1;
3402                 rk3368_lcdc_format_to_string(fmt_id, format_w2_0);
3403                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1;
3404                 rk3368_lcdc_format_to_string(fmt_id, format_w2_1);
3405                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1;
3406                 rk3368_lcdc_format_to_string(fmt_id, format_w2_2);
3407                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1;
3408                 rk3368_lcdc_format_to_string(fmt_id, format_w2_3);
3409
3410                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0);
3411                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0);
3412                 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1;
3413                 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1;
3414                 if (w2_0_state) {
3415                         w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3416                         w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16;
3417                 }
3418                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1);
3419                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1);
3420                 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1;
3421                 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1;
3422                 if (w2_1_state) {
3423                         w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3424                         w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16;
3425                 }
3426                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2);
3427                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2);
3428                 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1;
3429                 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1;
3430                 if (w2_2_state) {
3431                         w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3432                         w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16;
3433                 }
3434                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3);
3435                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3);
3436                 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1;
3437                 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1;
3438                 if (w2_3_state) {
3439                         w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3440                         w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16;
3441                 }
3442
3443                 /*WIN3 */
3444                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3445                 w3_state = win_ctrl & m_WIN3_EN;
3446                 w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4;
3447                 w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 8;
3448                 w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 12;
3449                 w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 16;
3450                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1);
3451                 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3452                 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16;
3453                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3);
3454                 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3455                 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16;
3456                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1;
3457                 rk3368_lcdc_format_to_string(fmt_id, format_w3_0);
3458                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1;
3459                 rk3368_lcdc_format_to_string(fmt_id, format_w3_1);
3460                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1;
3461                 rk3368_lcdc_format_to_string(fmt_id, format_w3_2);
3462                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1;
3463                 rk3368_lcdc_format_to_string(fmt_id, format_w3_3);
3464                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0);
3465                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0);
3466                 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1;
3467                 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1;
3468                 if (w3_0_state) {
3469                         w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3470                         w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16;
3471                 }
3472
3473                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1);
3474                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1);
3475                 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1;
3476                 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1;
3477                 if (w3_1_state) {
3478                         w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3479                         w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16;
3480                 }
3481
3482                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2);
3483                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2);
3484                 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1;
3485                 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1;
3486                 if (w3_2_state) {
3487                         w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3488                         w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16;
3489                 }
3490
3491                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3);
3492                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3);
3493                 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1;
3494                 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1;
3495                 if (w3_3_state) {
3496                         w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3497                         w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16;
3498                 }
3499
3500         } else {
3501                 spin_unlock(&lcdc_dev->reg_lock);
3502                 return -EPERM;
3503         }
3504         spin_unlock(&lcdc_dev->reg_lock);
3505         size += snprintf(dsp_buf, 80,
3506                 "z-order:\n  win[%d]\n  win[%d]\n  win[%d]\n  win[%d]\n",
3507                 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3508         strcat(buf, dsp_buf);
3509         memset(dsp_buf, 0, sizeof(dsp_buf));
3510         /*win0*/
3511         size += snprintf(dsp_buf, 80,
3512                  "win0:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3513                  w0_state, format_w0, w0_vir_y, w0_vir_uv);
3514         strcat(buf, dsp_buf);
3515         memset(dsp_buf, 0, sizeof(dsp_buf));
3516
3517         size += snprintf(dsp_buf, 80,
3518                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3519                  w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3520         strcat(buf, dsp_buf);
3521         memset(dsp_buf, 0, sizeof(dsp_buf));
3522
3523         size += snprintf(dsp_buf, 80,
3524                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3525                  w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3526         strcat(buf, dsp_buf);
3527         memset(dsp_buf, 0, sizeof(dsp_buf));
3528
3529         size += snprintf(dsp_buf, 80,
3530                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3531                  w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3532                  lcdc_readl(lcdc_dev, WIN0_CBR_MST));
3533         strcat(buf, dsp_buf);
3534         memset(dsp_buf, 0, sizeof(dsp_buf));
3535
3536         /*win1*/
3537         size += snprintf(dsp_buf, 80,
3538                  "win1:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3539                  w1_state, format_w1, w1_vir_y, w1_vir_uv);
3540         strcat(buf, dsp_buf);
3541         memset(dsp_buf, 0, sizeof(dsp_buf));
3542
3543         size += snprintf(dsp_buf, 80,
3544                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3545                  w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3546         strcat(buf, dsp_buf);
3547         memset(dsp_buf, 0, sizeof(dsp_buf));
3548
3549         size += snprintf(dsp_buf, 80,
3550                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3551                  w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3552         strcat(buf, dsp_buf);
3553         memset(dsp_buf, 0, sizeof(dsp_buf));
3554
3555         size += snprintf(dsp_buf, 80,
3556                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3557                  w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3558                  lcdc_readl(lcdc_dev, WIN1_CBR_MST));
3559         strcat(buf, dsp_buf);
3560         memset(dsp_buf, 0, sizeof(dsp_buf));
3561
3562         /*win2*/
3563         size += snprintf(dsp_buf, 80,
3564                  "win2:\n  state:%d\n",
3565                  w2_state);
3566         strcat(buf, dsp_buf);
3567         memset(dsp_buf, 0, sizeof(dsp_buf));
3568         /*area 0*/
3569         size += snprintf(dsp_buf, 80,
3570                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3571                  w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3572         strcat(buf, dsp_buf);
3573         memset(dsp_buf, 0, sizeof(dsp_buf));
3574         size += snprintf(dsp_buf, 80,
3575                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3576                  w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3577                  lcdc_readl(lcdc_dev, WIN2_MST0));
3578         strcat(buf, dsp_buf);
3579         memset(dsp_buf, 0, sizeof(dsp_buf));
3580
3581         /*area 1*/
3582         size += snprintf(dsp_buf, 80,
3583                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3584                  w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3585         strcat(buf, dsp_buf);
3586         memset(dsp_buf, 0, sizeof(dsp_buf));
3587         size += snprintf(dsp_buf, 80,
3588                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3589                  w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3590                  lcdc_readl(lcdc_dev, WIN2_MST1));
3591         strcat(buf, dsp_buf);
3592         memset(dsp_buf, 0, sizeof(dsp_buf));
3593
3594         /*area 2*/
3595         size += snprintf(dsp_buf, 80,
3596                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3597                  w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3598         strcat(buf, dsp_buf);
3599         memset(dsp_buf, 0, sizeof(dsp_buf));
3600         size += snprintf(dsp_buf, 80,
3601                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3602                  w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3603                  lcdc_readl(lcdc_dev, WIN2_MST2));
3604         strcat(buf, dsp_buf);
3605         memset(dsp_buf, 0, sizeof(dsp_buf));
3606
3607         /*area 3*/
3608         size += snprintf(dsp_buf, 80,
3609                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3610                  w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3611         strcat(buf, dsp_buf);
3612         memset(dsp_buf, 0, sizeof(dsp_buf));
3613         size += snprintf(dsp_buf, 80,
3614                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3615                  w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3616                  lcdc_readl(lcdc_dev, WIN2_MST3));
3617         strcat(buf, dsp_buf);
3618         memset(dsp_buf, 0, sizeof(dsp_buf));
3619
3620         /*win3*/
3621         size += snprintf(dsp_buf, 80,
3622                  "win3:\n  state:%d\n",
3623                  w3_state);
3624         strcat(buf, dsp_buf);
3625         memset(dsp_buf, 0, sizeof(dsp_buf));
3626         /*area 0*/
3627         size += snprintf(dsp_buf, 80,
3628                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3629                  w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
3630         strcat(buf, dsp_buf);
3631         memset(dsp_buf, 0, sizeof(dsp_buf));
3632         size += snprintf(dsp_buf, 80,
3633                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3634                  w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
3635                  lcdc_readl(lcdc_dev, WIN3_MST0));
3636         strcat(buf, dsp_buf);
3637         memset(dsp_buf, 0, sizeof(dsp_buf));
3638
3639         /*area 1*/
3640         size += snprintf(dsp_buf, 80,
3641                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3642                  w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
3643         strcat(buf, dsp_buf);
3644         memset(dsp_buf, 0, sizeof(dsp_buf));
3645         size += snprintf(dsp_buf, 80,
3646                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3647                  w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
3648                  lcdc_readl(lcdc_dev, WIN3_MST1));
3649         strcat(buf, dsp_buf);
3650         memset(dsp_buf, 0, sizeof(dsp_buf));
3651
3652         /*area 2*/
3653         size += snprintf(dsp_buf, 80,
3654                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3655                  w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
3656         strcat(buf, dsp_buf);
3657         memset(dsp_buf, 0, sizeof(dsp_buf));
3658         size += snprintf(dsp_buf, 80,
3659                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3660                  w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
3661                  lcdc_readl(lcdc_dev, WIN3_MST2));
3662         strcat(buf, dsp_buf);
3663         memset(dsp_buf, 0, sizeof(dsp_buf));
3664
3665         /*area 3*/
3666         size += snprintf(dsp_buf, 80,
3667                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3668                  w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
3669         strcat(buf, dsp_buf);
3670         memset(dsp_buf, 0, sizeof(dsp_buf));
3671         size += snprintf(dsp_buf, 80,
3672                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3673                  w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
3674                  lcdc_readl(lcdc_dev, WIN3_MST3));
3675         strcat(buf, dsp_buf);
3676         memset(dsp_buf, 0, sizeof(dsp_buf));
3677
3678         return size;
3679 }
3680
3681 static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3682                                bool set)
3683 {
3684         struct lcdc_device *lcdc_dev =
3685             container_of(dev_drv, struct lcdc_device, driver);
3686         struct rk_screen *screen = dev_drv->cur_screen;
3687         u64 ft = 0;
3688         u32 dotclk;
3689         int ret;
3690         u32 pixclock;
3691         u32 x_total, y_total;
3692
3693         if (set) {
3694                 if (fps == 0) {
3695                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
3696                         return 0;
3697                 }
3698                 ft = div_u64(1000000000000llu, fps);
3699                 x_total =
3700                     screen->mode.upper_margin + screen->mode.lower_margin +
3701                     screen->mode.yres + screen->mode.vsync_len;
3702                 y_total =
3703                     screen->mode.left_margin + screen->mode.right_margin +
3704                     screen->mode.xres + screen->mode.hsync_len;
3705                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3706                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3707                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3708         }
3709
3710         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3711         lcdc_dev->pixclock = pixclock;
3712         dev_drv->pixclock = lcdc_dev->pixclock;
3713         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3714         screen->ft = 1000 / fps;        /*one frame time in ms */
3715
3716         if (set)
3717                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3718                          clk_get_rate(lcdc_dev->dclk), fps);
3719
3720         return fps;
3721 }
3722
3723 static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3724 {
3725         mutex_lock(&dev_drv->fb_win_id_mutex);
3726         if (order == FB_DEFAULT_ORDER)
3727                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
3728         dev_drv->fb4_win_id = order / 10000;
3729         dev_drv->fb3_win_id = (order / 1000) % 10;
3730         dev_drv->fb2_win_id = (order / 100) % 10;
3731         dev_drv->fb1_win_id = (order / 10) % 10;
3732         dev_drv->fb0_win_id = order % 10;
3733         mutex_unlock(&dev_drv->fb_win_id_mutex);
3734
3735         return 0;
3736 }
3737
3738 static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3739                                   const char *id)
3740 {
3741         int win_id = 0;
3742
3743         mutex_lock(&dev_drv->fb_win_id_mutex);
3744         if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
3745                 win_id = dev_drv->fb0_win_id;
3746         else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
3747                 win_id = dev_drv->fb1_win_id;
3748         else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
3749                 win_id = dev_drv->fb2_win_id;
3750         else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
3751                 win_id = dev_drv->fb3_win_id;
3752         else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
3753                 win_id = dev_drv->fb4_win_id;
3754         mutex_unlock(&dev_drv->fb_win_id_mutex);
3755
3756         return win_id;
3757 }
3758
3759 static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3760 {
3761         struct lcdc_device *lcdc_dev =
3762             container_of(dev_drv, struct lcdc_device, driver);
3763         int i;
3764         unsigned int mask, val;
3765         struct rk_lcdc_win *win = NULL;
3766
3767         spin_lock(&lcdc_dev->reg_lock);
3768         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3769                      v_STANDBY_EN(lcdc_dev->standby));
3770         for (i = 0; i < 4; i++) {
3771                 win = dev_drv->win[i];
3772                 if ((win->state == 0) && (win->last_state == 1)) {
3773                         switch (win->id) {
3774                         case 0:
3775                                 /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
3776                                    for rk3288 to fix hw bug? */
3777                                 mask = m_WIN0_EN;
3778                                 val = v_WIN0_EN(0);
3779                                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
3780                                 break;
3781                         case 1:
3782                                 /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
3783                                    for rk3288 to fix hw bug? */
3784                                 mask = m_WIN1_EN;
3785                                 val = v_WIN1_EN(0);
3786                                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
3787                                 break;
3788                         case 2:
3789                                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
3790                                     m_WIN2_MST1_EN |
3791                                     m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3792                                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
3793                                     v_WIN2_MST1_EN(0) |
3794                                     v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3795                                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
3796                                 break;
3797                         case 3:
3798                                 mask = m_WIN3_EN | m_WIN3_MST0_EN |
3799                                     m_WIN3_MST1_EN |
3800                                     m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3801                                 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |
3802                                     v_WIN3_MST1_EN(0) |
3803                                     v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3804                                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
3805                                 break;
3806                         case 4:
3807                                 mask = m_HWC_EN;
3808                                 val = v_HWC_EN(0);
3809                                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
3810                                 break;
3811                         default:
3812                                 break;
3813                         }
3814                 }
3815                 win->last_state = win->state;
3816         }
3817         lcdc_cfg_done(lcdc_dev);
3818         spin_unlock(&lcdc_dev->reg_lock);
3819         return 0;
3820 }
3821
3822 static int rk3368_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3823 {
3824         struct lcdc_device *lcdc_dev =
3825             container_of(dev_drv, struct lcdc_device, driver);
3826         spin_lock(&lcdc_dev->reg_lock);
3827         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3828                      v_DIRECT_PATH_EN(open));
3829         lcdc_cfg_done(lcdc_dev);
3830         spin_unlock(&lcdc_dev->reg_lock);
3831         return 0;
3832 }
3833
3834 static int rk3368_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3835 {
3836         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3837                                                     struct lcdc_device, driver);
3838         spin_lock(&lcdc_dev->reg_lock);
3839         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3840                      v_DIRECT_PATCH_SEL(win_id));
3841         lcdc_cfg_done(lcdc_dev);
3842         spin_unlock(&lcdc_dev->reg_lock);
3843         return 0;
3844 }
3845
3846 static int rk3368_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3847 {
3848         struct lcdc_device *lcdc_dev =
3849             container_of(dev_drv, struct lcdc_device, driver);
3850         int ovl;
3851
3852         spin_lock(&lcdc_dev->reg_lock);
3853         ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3854         spin_unlock(&lcdc_dev->reg_lock);
3855         return ovl;
3856 }
3857
3858 static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
3859                                       int enable)
3860 {
3861         struct lcdc_device *lcdc_dev =
3862             container_of(dev_drv, struct lcdc_device, driver);
3863         if (enable)
3864                 enable_irq(lcdc_dev->irq);
3865         else
3866                 disable_irq(lcdc_dev->irq);
3867         return 0;
3868 }
3869
3870 int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3871 {
3872         struct lcdc_device *lcdc_dev =
3873             container_of(dev_drv, struct lcdc_device, driver);
3874         u32 int_reg;
3875         int ret;
3876
3877         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
3878                 int_reg = lcdc_readl(lcdc_dev, INTR_STATUS);
3879                 if (int_reg & m_LINE_FLAG0_INTR_STS) {
3880                         lcdc_dev->driver.frame_time.last_framedone_t =
3881                             lcdc_dev->driver.frame_time.framedone_t;
3882                         lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3883                         lcdc_msk_reg(lcdc_dev, INTR_CLEAR,
3884                                      m_LINE_FLAG0_INTR_CLR,
3885                                      v_LINE_FLAG0_INTR_CLR(1));
3886                         ret = RK_LF_STATUS_FC;
3887                 } else {
3888                         ret = RK_LF_STATUS_FR;
3889                 }
3890         } else {
3891                 ret = RK_LF_STATUS_NC;
3892         }
3893
3894         return ret;
3895 }
3896
3897 static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3898                                     unsigned int *dsp_addr)
3899 {
3900         struct lcdc_device *lcdc_dev =
3901             container_of(dev_drv, struct lcdc_device, driver);
3902         spin_lock(&lcdc_dev->reg_lock);
3903         if (lcdc_dev->clk_on) {
3904                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3905                 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3906                 dsp_addr[2] = lcdc_readl(lcdc_dev, WIN2_MST0);
3907                 dsp_addr[3] = lcdc_readl(lcdc_dev, WIN3_MST0);
3908         }
3909         spin_unlock(&lcdc_dev->reg_lock);
3910         return 0;
3911 }
3912
3913 static struct lcdc_cabc_mode cabc_mode[4] = {
3914       /* calc,     up,     down,   global_limit   */
3915         {5,    256,  256,   256},  /*mode 1   0*/
3916         {5,    258,  253,   277},  /*mode 2   15%*/
3917         {5,    259,  252,   330},  /*mode 3   40%*/
3918         {5,    267,  244,   400},  /*mode 4   60%*/
3919 };
3920
3921 static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode)
3922 {
3923         struct lcdc_device *lcdc_dev =
3924             container_of(dev_drv, struct lcdc_device, driver);
3925         struct rk_screen *screen = dev_drv->cur_screen;
3926         u32 total_pixel, calc_pixel, stage_up, stage_down;
3927         u32 pixel_num, global_su;
3928         u32 stage_up_rec, stage_down_rec, global_su_rec, gamma_global_su_rec;
3929         u32 mask = 0, val = 0, cabc_en = 0;
3930         int *cabc_lut = NULL;
3931
3932         if (!screen->cabc_lut) {
3933                 pr_err("screen cabc lut not config, so not open cabc\n");
3934                 return 0;
3935         } else {
3936                 cabc_lut = screen->cabc_lut;
3937         }
3938
3939         dev_drv->cabc_mode = mode;
3940         cabc_en = (mode > 0) ? 1 : 0;
3941
3942         if (cabc_en == 0) {
3943                 spin_lock(&lcdc_dev->reg_lock);
3944                 if (lcdc_dev->clk_on) {
3945                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
3946                                      m_CABC_EN, v_CABC_EN(0));
3947                         lcdc_cfg_done(lcdc_dev);
3948                 }
3949                 spin_unlock(&lcdc_dev->reg_lock);
3950                 return 0;
3951         }
3952
3953         total_pixel = screen->mode.xres * screen->mode.yres;
3954         pixel_num = 1000 - (cabc_mode[mode - 1].pixel_num);
3955         calc_pixel = (total_pixel * pixel_num) / 1000;
3956         stage_up = cabc_mode[mode - 1].stage_up;
3957         stage_down = cabc_mode[mode - 1].stage_down;
3958         global_su = cabc_mode[mode - 1].global_su;
3959
3960         stage_up_rec = 256 * 256 / stage_up;
3961         stage_down_rec = 256 * 256 / stage_down;
3962         global_su_rec = (256 * 256 / global_su) - 1;
3963         gamma_global_su_rec = cabc_lut[global_su_rec];
3964
3965         spin_lock(&lcdc_dev->reg_lock);
3966         if (lcdc_dev->clk_on) {
3967                 mask = m_CABC_CALC_PIXEL_NUM | m_CABC_EN;
3968                 val = v_CABC_CALC_PIXEL_NUM(calc_pixel) |
3969                         v_CABC_EN(cabc_en);
3970                 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3971
3972                 mask = m_CABC_TOTAL_PIXEL_NUM | m_CABC_LUT_EN;
3973                 val = v_CABC_TOTAL_PIXEL_NUM(total_pixel) | v_CABC_LUT_EN(1);
3974                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3975
3976                 mask = m_CABC_STAGE_UP | m_CABC_STAGE_UP_REC |
3977                     m_CABC_GLOBAL_SU_LIMIT_EN | m_CABC_GLOBAL_SU_REC;
3978                 val = v_CABC_STAGE_UP(stage_up) |
3979                     v_CABC_STAGE_UP_REC(stage_up_rec) |
3980                     v_CABC_GLOBAL_SU_LIMIT_EN(1) |
3981                     v_CABC_GLOBAL_SU_REC(gamma_global_su_rec);
3982                 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
3983
3984                 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_DOWN_REC |
3985                     m_CABC_GLOBAL_SU;
3986                 val = v_CABC_STAGE_DOWN(stage_down) |
3987                     v_CABC_STAGE_DOWN_REC(stage_down_rec) |
3988                     v_CABC_GLOBAL_SU(global_su);
3989                 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
3990                 lcdc_cfg_done(lcdc_dev);
3991         }
3992         spin_unlock(&lcdc_dev->reg_lock);
3993
3994         return 0;
3995 }
3996
3997 /*
3998         a:[-30~0]:
3999             sin_hue = sin(a)*256 +0x100;
4000             cos_hue = cos(a)*256;
4001         a:[0~30]
4002             sin_hue = sin(a)*256;
4003             cos_hue = cos(a)*256;
4004 */
4005 static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
4006                                     bcsh_hue_mode mode)
4007 {
4008         struct lcdc_device *lcdc_dev =
4009             container_of(dev_drv, struct lcdc_device, driver);
4010         u32 val;
4011
4012         spin_lock(&lcdc_dev->reg_lock);
4013         if (lcdc_dev->clk_on) {
4014                 val = lcdc_readl(lcdc_dev, BCSH_H);
4015                 switch (mode) {
4016                 case H_SIN:
4017                         val &= m_BCSH_SIN_HUE;
4018                         break;
4019                 case H_COS:
4020                         val &= m_BCSH_COS_HUE;
4021                         val >>= 16;
4022                         break;
4023                 default:
4024                         break;
4025                 }
4026         }
4027         spin_unlock(&lcdc_dev->reg_lock);
4028
4029         return val;
4030 }
4031
4032 static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
4033                                     int sin_hue, int cos_hue)
4034 {
4035         struct lcdc_device *lcdc_dev =
4036             container_of(dev_drv, struct lcdc_device, driver);
4037         u32 mask, val;
4038
4039         spin_lock(&lcdc_dev->reg_lock);
4040         if (lcdc_dev->clk_on) {
4041                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
4042                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
4043                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
4044                 lcdc_cfg_done(lcdc_dev);
4045         }
4046         spin_unlock(&lcdc_dev->reg_lock);
4047
4048         return 0;
4049 }
4050
4051 static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4052                                     bcsh_bcs_mode mode, int value)
4053 {
4054         struct lcdc_device *lcdc_dev =
4055             container_of(dev_drv, struct lcdc_device, driver);
4056         u32 mask, val;
4057
4058         spin_lock(&lcdc_dev->reg_lock);
4059         if (lcdc_dev->clk_on) {
4060                 switch (mode) {
4061                 case BRIGHTNESS:
4062                         /*from 0 to 255,typical is 128 */
4063                         if (value < 0x80)
4064                                 value += 0x80;
4065                         else if (value >= 0x80)
4066                                 value = value - 0x80;
4067                         mask = m_BCSH_BRIGHTNESS;
4068                         val = v_BCSH_BRIGHTNESS(value);
4069                         break;
4070                 case CONTRAST:
4071                         /*from 0 to 510,typical is 256 */
4072                         mask = m_BCSH_CONTRAST;
4073                         val = v_BCSH_CONTRAST(value);
4074                         break;
4075                 case SAT_CON:
4076                         /*from 0 to 1015,typical is 256 */
4077                         mask = m_BCSH_SAT_CON;
4078                         val = v_BCSH_SAT_CON(value);
4079                         break;
4080                 default:
4081                         break;
4082                 }
4083                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
4084                 lcdc_cfg_done(lcdc_dev);
4085         }
4086         spin_unlock(&lcdc_dev->reg_lock);
4087         return val;
4088 }
4089
4090 static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4091                                     bcsh_bcs_mode mode)
4092 {
4093         struct lcdc_device *lcdc_dev =
4094             container_of(dev_drv, struct lcdc_device, driver);
4095         u32 val;
4096
4097         spin_lock(&lcdc_dev->reg_lock);
4098         if (lcdc_dev->clk_on) {
4099                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
4100                 switch (mode) {
4101                 case BRIGHTNESS:
4102                         val &= m_BCSH_BRIGHTNESS;
4103                         if (val > 0x80)
4104                                 val -= 0x80;
4105                         else
4106                                 val += 0x80;
4107                         break;
4108                 case CONTRAST:
4109                         val &= m_BCSH_CONTRAST;
4110                         val >>= 8;
4111                         break;
4112                 case SAT_CON:
4113                         val &= m_BCSH_SAT_CON;
4114                         val >>= 20;
4115                         break;
4116                 default:
4117                         break;
4118                 }
4119         }
4120         spin_unlock(&lcdc_dev->reg_lock);
4121         return val;
4122 }
4123
4124 static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
4125 {
4126         struct lcdc_device *lcdc_dev =
4127             container_of(dev_drv, struct lcdc_device, driver);
4128         u32 mask, val;
4129
4130         spin_lock(&lcdc_dev->reg_lock);
4131         if (lcdc_dev->clk_on) {
4132                 if (open) {
4133                         lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1);
4134                         lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
4135                         lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
4136                         dev_drv->bcsh.enable = 1;
4137                 } else {
4138                         mask = m_BCSH_EN;
4139                         val = v_BCSH_EN(0);
4140                         lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
4141                         dev_drv->bcsh.enable = 0;
4142                 }
4143                 rk3368_lcdc_bcsh_path_sel(dev_drv);
4144                 lcdc_cfg_done(lcdc_dev);
4145         }
4146         spin_unlock(&lcdc_dev->reg_lock);
4147         return 0;
4148 }
4149
4150 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4151 {
4152         if (!enable || !dev_drv->bcsh.enable) {
4153                 rk3368_lcdc_open_bcsh(dev_drv, false);
4154                 return 0;
4155         }
4156
4157         if (dev_drv->bcsh.brightness <= 255 ||
4158             dev_drv->bcsh.contrast <= 510 ||
4159             dev_drv->bcsh.sat_con <= 1015 ||
4160             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4161                 rk3368_lcdc_open_bcsh(dev_drv, true);
4162                 if (dev_drv->bcsh.brightness <= 255)
4163                         rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4164                                                  dev_drv->bcsh.brightness);
4165                 if (dev_drv->bcsh.contrast <= 510)
4166                         rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
4167                                                  dev_drv->bcsh.contrast);
4168                 if (dev_drv->bcsh.sat_con <= 1015)
4169                         rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
4170                                                  dev_drv->bcsh.sat_con);
4171                 if (dev_drv->bcsh.sin_hue <= 511 &&
4172                     dev_drv->bcsh.cos_hue <= 511)
4173                         rk3368_lcdc_set_bcsh_hue(dev_drv,
4174                                                  dev_drv->bcsh.sin_hue,
4175                                                  dev_drv->bcsh.cos_hue);
4176         }
4177         return 0;
4178 }
4179
4180 static int rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4181 {
4182         struct lcdc_device *lcdc_dev =
4183             container_of(dev_drv, struct lcdc_device, driver);
4184
4185         if (enable) {
4186                 spin_lock(&lcdc_dev->reg_lock);
4187                 if (likely(lcdc_dev->clk_on)) {
4188                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4189                                      v_DSP_BLACK_EN(1));
4190                         lcdc_cfg_done(lcdc_dev);
4191                 }
4192                 spin_unlock(&lcdc_dev->reg_lock);
4193         } else {
4194                 spin_lock(&lcdc_dev->reg_lock);
4195                 if (likely(lcdc_dev->clk_on)) {
4196                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4197                                      v_DSP_BLACK_EN(0));
4198
4199                         lcdc_cfg_done(lcdc_dev);
4200                 }
4201                 spin_unlock(&lcdc_dev->reg_lock);
4202         }
4203
4204         return 0;
4205 }
4206
4207
4208 static int rk3368_lcdc_backlight_close(struct rk_lcdc_driver *dev_drv,
4209                                        int enable)
4210 {
4211         struct lcdc_device *lcdc_dev =
4212             container_of(dev_drv, struct lcdc_device, driver);
4213
4214         rk3368_lcdc_get_backlight_device(dev_drv);
4215
4216         if (enable) {
4217                 /* close the backlight */
4218                 if (lcdc_dev->backlight) {
4219                         lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4220                         backlight_update_status(lcdc_dev->backlight);
4221                 }
4222                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4223                         dev_drv->trsm_ops->disable();
4224         } else {
4225                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4226                         dev_drv->trsm_ops->enable();
4227                 msleep(100);
4228                 /* open the backlight */
4229                 if (lcdc_dev->backlight) {
4230                         lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
4231                         backlight_update_status(lcdc_dev->backlight);
4232                 }
4233         }
4234
4235         return 0;
4236 }
4237
4238 static int rk3368_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv,
4239                                     struct overscan *overscan)
4240 {
4241         rk3368_lcdc_post_cfg(dev_drv);
4242
4243         return 0;
4244 }
4245
4246 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4247         .open = rk3368_lcdc_open,
4248         .win_direct_en = rk3368_lcdc_win_direct_en,
4249         .load_screen = rk3368_load_screen,
4250         .get_dspbuf_info = rk3368_get_dspbuf_info,
4251         .post_dspbuf = rk3368_post_dspbuf,
4252         .set_par = rk3368_lcdc_set_par,
4253         .pan_display = rk3368_lcdc_pan_display,
4254         .direct_set_addr = rk3368_lcdc_direct_set_win_addr,
4255         /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/
4256         .blank = rk3368_lcdc_blank,
4257         .ioctl = rk3368_lcdc_ioctl,
4258         .suspend = rk3368_lcdc_early_suspend,
4259         .resume = rk3368_lcdc_early_resume,
4260         .get_win_state = rk3368_lcdc_get_win_state,
4261         .ovl_mgr = rk3368_lcdc_ovl_mgr,
4262         .get_disp_info = rk3368_lcdc_get_disp_info,
4263         .fps_mgr = rk3368_lcdc_fps_mgr,
4264         .fb_get_win_id = rk3368_lcdc_get_win_id,
4265         .fb_win_remap = rk3368_fb_win_remap,
4266         .set_dsp_lut = rk3368_lcdc_set_lut,
4267         .set_cabc_lut = rk3368_set_cabc_lut,
4268         .poll_vblank = rk3368_lcdc_poll_vblank,
4269         .dpi_open = rk3368_lcdc_dpi_open,
4270         .dpi_win_sel = rk3368_lcdc_dpi_win_sel,
4271         .dpi_status = rk3368_lcdc_dpi_status,
4272         .get_dsp_addr = rk3368_lcdc_get_dsp_addr,
4273         .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc,
4274         .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue,
4275         .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs,
4276         .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue,
4277         .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs,
4278         .open_bcsh = rk3368_lcdc_open_bcsh,
4279         .dump_reg = rk3368_lcdc_reg_dump,
4280         .cfg_done = rk3368_lcdc_config_done,
4281         .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu,
4282         .dsp_black = rk3368_lcdc_dsp_black,
4283         .backlight_close = rk3368_lcdc_backlight_close,
4284         .mmu_en    = rk3368_lcdc_mmu_en,
4285         .set_overscan   = rk3368_lcdc_set_overscan,
4286 };
4287
4288 #ifdef LCDC_IRQ_EMPTY_DEBUG
4289 static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev,
4290                                  unsigned int intr_status)
4291 {
4292         if (intr_status & m_WIN0_EMPTY_INTR_STS) {
4293                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN0_EMPTY_INTR_CLR,
4294                              v_WIN0_EMPTY_INTR_CLR(1));
4295                 dev_warn(lcdc_dev->dev, "win0 empty irq!");
4296         } else if (intr_status & m_WIN1_EMPTY_INTR_STS) {
4297                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN1_EMPTY_INTR_CLR,
4298                              v_WIN1_EMPTY_INTR_CLR(1));
4299                 dev_warn(lcdc_dev->dev, "win1 empty irq!");
4300         } else if (intr_status & m_WIN2_EMPTY_INTR_STS) {
4301                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN2_EMPTY_INTR_CLR,
4302                              v_WIN2_EMPTY_INTR_CLR(1));
4303                 dev_warn(lcdc_dev->dev, "win2 empty irq!");
4304         } else if (intr_status & m_WIN3_EMPTY_INTR_STS) {
4305                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN3_EMPTY_INTR_CLR,
4306                              v_WIN3_EMPTY_INTR_CLR(1));
4307                 dev_warn(lcdc_dev->dev, "win3 empty irq!");
4308         } else if (intr_status & m_HWC_EMPTY_INTR_STS) {
4309                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_HWC_EMPTY_INTR_CLR,
4310                              v_HWC_EMPTY_INTR_CLR(1));
4311                 dev_warn(lcdc_dev->dev, "HWC empty irq!");
4312         } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) {
4313                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_POST_BUF_EMPTY_INTR_CLR,
4314                              v_POST_BUF_EMPTY_INTR_CLR(1));
4315                 dev_warn(lcdc_dev->dev, "post buf empty irq!");
4316         } else if (intr_status & m_PWM_GEN_INTR_STS) {
4317                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_PWM_GEN_INTR_CLR,
4318                              v_PWM_GEN_INTR_CLR(1));
4319                 dev_warn(lcdc_dev->dev, "PWM gen irq!");
4320         }
4321         return 0;
4322 }
4323 #endif
4324
4325 static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id)
4326 {
4327         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
4328         ktime_t timestamp = ktime_get();
4329         u32 intr_status;
4330
4331         intr_status = lcdc_readl(lcdc_dev, INTR_STATUS);
4332
4333         if (intr_status & m_FS_INTR_STS) {
4334                 timestamp = ktime_get();
4335                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_INTR_CLR,
4336                              v_FS_INTR_CLR(1));
4337                 /*if(lcdc_dev->driver.wait_fs){ */
4338                 if (0) {
4339                         spin_lock(&(lcdc_dev->driver.cpl_lock));
4340                         complete(&(lcdc_dev->driver.frame_done));
4341                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
4342                 }
4343 #ifdef CONFIG_DRM_ROCKCHIP
4344                 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
4345 #endif
4346                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4347                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
4348
4349         } else if (intr_status & m_LINE_FLAG0_INTR_STS) {
4350                 lcdc_dev->driver.frame_time.last_framedone_t =
4351                     lcdc_dev->driver.frame_time.framedone_t;
4352                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4353                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG0_INTR_CLR,
4354                              v_LINE_FLAG0_INTR_CLR(1));
4355         } else if (intr_status & m_LINE_FLAG1_INTR_STS) {
4356                 /*line flag1 */
4357                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG1_INTR_CLR,
4358                              v_LINE_FLAG1_INTR_CLR(1));
4359         } else if (intr_status & m_FS_NEW_INTR_STS) {
4360                 /*new frame start */
4361                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_NEW_INTR_CLR,
4362                              v_FS_NEW_INTR_CLR(1));
4363         } else if (intr_status & m_BUS_ERROR_INTR_STS) {
4364                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_BUS_ERROR_INTR_CLR,
4365                              v_BUS_ERROR_INTR_CLR(1));
4366                 dev_warn(lcdc_dev->dev, "bus error!");
4367         }
4368
4369         /* for win empty debug */
4370 #ifdef LCDC_IRQ_EMPTY_DEBUG
4371         rk3368_lcdc_parse_irq(lcdc_dev, intr_status);
4372 #endif
4373         return IRQ_HANDLED;
4374 }
4375
4376 #if defined(CONFIG_PM)
4377 static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
4378 {
4379         return 0;
4380 }
4381
4382 static int rk3368_lcdc_resume(struct platform_device *pdev)
4383 {
4384         return 0;
4385 }
4386 #else
4387 #define rk3368_lcdc_suspend NULL
4388 #define rk3368_lcdc_resume  NULL
4389 #endif
4390
4391 static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4392 {
4393         struct device_node *np = lcdc_dev->dev->of_node;
4394         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4395         int val;
4396
4397         if (of_property_read_u32(np, "rockchip,prop", &val))
4398                 lcdc_dev->prop = PRMRY; /*default set it as primary */
4399         else
4400                 lcdc_dev->prop = val;
4401
4402         if (of_property_read_u32(np, "rockchip,mirror", &val))
4403                 dev_drv->rotate_mode = NO_MIRROR;
4404         else
4405                 dev_drv->rotate_mode = val;
4406
4407         if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4408                 dev_drv->cabc_mode = 0; /* default set close cabc */
4409         else
4410                 dev_drv->cabc_mode = val;
4411
4412         if (of_property_read_u32(np, "rockchip,pwr18", &val))
4413                 /*default set it as 3.xv power supply */
4414                 lcdc_dev->pwr18 = false;
4415         else
4416                 lcdc_dev->pwr18 = (val ? true : false);
4417
4418         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4419                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4420         else
4421                 dev_drv->fb_win_map = val;
4422
4423         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4424                 dev_drv->bcsh.enable = false;
4425         else
4426                 dev_drv->bcsh.enable = (val ? true : false);
4427
4428         if (of_property_read_u32(np, "rockchip,brightness", &val))
4429                 dev_drv->bcsh.brightness = 0xffff;
4430         else
4431                 dev_drv->bcsh.brightness = val;
4432
4433         if (of_property_read_u32(np, "rockchip,contrast", &val))
4434                 dev_drv->bcsh.contrast = 0xffff;
4435         else
4436                 dev_drv->bcsh.contrast = val;
4437
4438         if (of_property_read_u32(np, "rockchip,sat-con", &val))
4439                 dev_drv->bcsh.sat_con = 0xffff;
4440         else
4441                 dev_drv->bcsh.sat_con = val;
4442
4443         if (of_property_read_u32(np, "rockchip,hue", &val)) {
4444                 dev_drv->bcsh.sin_hue = 0xffff;
4445                 dev_drv->bcsh.cos_hue = 0xffff;
4446         } else {
4447                 dev_drv->bcsh.sin_hue = val & 0xff;
4448                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4449         }
4450
4451 #if defined(CONFIG_ROCKCHIP_IOMMU)
4452         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4453                 dev_drv->iommu_enabled = 0;
4454         else
4455                 dev_drv->iommu_enabled = val;
4456 #else
4457         dev_drv->iommu_enabled = 0;
4458 #endif
4459         return 0;
4460 }
4461
4462 static int rk3368_lcdc_probe(struct platform_device *pdev)
4463 {
4464         struct lcdc_device *lcdc_dev = NULL;
4465         struct rk_lcdc_driver *dev_drv;
4466         struct device *dev = &pdev->dev;
4467         struct resource *res;
4468         struct device_node *np = pdev->dev.of_node;
4469         int prop;
4470         int ret = 0;
4471
4472         /*if the primary lcdc has not registered ,the extend
4473            lcdc register later */
4474         of_property_read_u32(np, "rockchip,prop", &prop);
4475         if (prop == EXTEND) {
4476                 if (!is_prmry_rk_lcdc_registered())
4477                         return -EPROBE_DEFER;
4478         }
4479         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
4480         if (!lcdc_dev) {
4481                 dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!");
4482                 return -ENOMEM;
4483         }
4484         platform_set_drvdata(pdev, lcdc_dev);
4485         lcdc_dev->dev = dev;
4486         rk3368_lcdc_parse_dt(lcdc_dev);
4487         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4488         lcdc_dev->reg_phy_base = res->start;
4489         lcdc_dev->len = resource_size(res);
4490         lcdc_dev->regs = devm_ioremap_resource(dev, res);
4491         if (IS_ERR(lcdc_dev->regs))
4492                 return PTR_ERR(lcdc_dev->regs);
4493         else
4494                 dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs);
4495
4496         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4497         if (IS_ERR(lcdc_dev->regsbak))
4498                 return PTR_ERR(lcdc_dev->regsbak);
4499         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4500         lcdc_dev->cabc_lut_addr_base = (lcdc_dev->regs + CABC_GAMMA_LUT_ADDR);
4501         lcdc_dev->grf_base =
4502                 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
4503         if (IS_ERR(lcdc_dev->grf_base)) {
4504                 dev_err(&pdev->dev, "can't find lcdc grf property\n");
4505                 return PTR_ERR(lcdc_dev->grf_base);
4506         }
4507         lcdc_dev->pmugrf_base =
4508                 syscon_regmap_lookup_by_phandle(np, "rockchip,pmugrf");
4509         if (IS_ERR(lcdc_dev->pmugrf_base)) {
4510                 dev_err(&pdev->dev, "can't find lcdc pmu grf property\n");
4511                 return PTR_ERR(lcdc_dev->pmugrf_base);
4512         }
4513         lcdc_dev->id = 0;
4514         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4515         dev_drv = &lcdc_dev->driver;
4516         dev_drv->dev = dev;
4517         dev_drv->prop = prop;
4518         dev_drv->id = lcdc_dev->id;
4519         dev_drv->ops = &lcdc_drv_ops;
4520         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4521         spin_lock_init(&lcdc_dev->reg_lock);
4522
4523         lcdc_dev->irq = platform_get_irq(pdev, 0);
4524         if (lcdc_dev->irq < 0) {
4525                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4526                         lcdc_dev->id);
4527                 return -ENXIO;
4528         }
4529
4530         ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr,
4531                                IRQF_DISABLED | IRQF_SHARED,
4532                                dev_name(dev), lcdc_dev);
4533         if (ret) {
4534                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4535                         lcdc_dev->irq, ret);
4536                 return ret;
4537         }
4538
4539         if (dev_drv->iommu_enabled) {
4540                 if (lcdc_dev->id == 0) {
4541                         strcpy(dev_drv->mmu_dts_name,
4542                                VOPB_IOMMU_COMPATIBLE_NAME);
4543                 } else {
4544                         strcpy(dev_drv->mmu_dts_name,
4545                                VOPL_IOMMU_COMPATIBLE_NAME);
4546                 }
4547         }
4548
4549         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4550         if (ret < 0) {
4551                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4552                 return ret;
4553         }
4554         lcdc_dev->screen = dev_drv->screen0;
4555         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4556                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4557
4558         return 0;
4559 }
4560
4561 static int rk3368_lcdc_remove(struct platform_device *pdev)
4562 {
4563         return 0;
4564 }
4565
4566 static void rk3368_lcdc_shutdown(struct platform_device *pdev)
4567 {
4568         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
4569
4570         rk3368_lcdc_early_suspend(&lcdc_dev->driver);
4571         rk3368_lcdc_deint(lcdc_dev);
4572 }
4573
4574 #if defined(CONFIG_OF)
4575 static const struct of_device_id rk3368_lcdc_dt_ids[] = {
4576         {.compatible = "rockchip,rk3368-lcdc",},
4577         {}
4578 };
4579 #endif
4580
4581 static struct platform_driver rk3368_lcdc_driver = {
4582         .probe = rk3368_lcdc_probe,
4583         .remove = rk3368_lcdc_remove,
4584         .driver = {
4585                    .name = "rk3368-lcdc",
4586                    .owner = THIS_MODULE,
4587                    .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids),
4588                    },
4589         .suspend = rk3368_lcdc_suspend,
4590         .resume = rk3368_lcdc_resume,
4591         .shutdown = rk3368_lcdc_shutdown,
4592 };
4593
4594 static int __init rk3368_lcdc_module_init(void)
4595 {
4596         return platform_driver_register(&rk3368_lcdc_driver);
4597 }
4598
4599 static void __exit rk3368_lcdc_module_exit(void)
4600 {
4601         platform_driver_unregister(&rk3368_lcdc_driver);
4602 }
4603
4604 fs_initcall(rk3368_lcdc_module_init);
4605 module_exit(rk3368_lcdc_module_exit);