2 * drivers/video/rockchip/lcdc/rk3288_lcdc.c
4 * Copyright (C) 2014 ROCKCHIP, Inc.
5 *Author:hjc<hjc@rock-chips.com>
6 *This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/string.h>
22 #include <linux/slab.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/rockchip-iovmm.h>
30 #include <asm/div64.h>
31 #include <asm/uaccess.h>
32 #include <linux/rockchip/cpu.h>
33 #include <linux/rockchip/iomap.h>
34 #include <linux/rockchip/grf.h>
35 #include <linux/rockchip/common.h>
36 #include <dt-bindings/clock/rk_system_status.h>
38 #include "rk3288_lcdc.h"
40 #if defined(CONFIG_HAS_EARLYSUSPEND)
41 #include <linux/earlysuspend.h>
44 static int dbg_thresd;
45 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
47 #define DBG(level, x...) do { \
48 if (unlikely(dbg_thresd >= level)) \
49 printk(KERN_INFO x); } while (0)
51 static int rk3288_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv,
54 struct fb_info *rk_get_fb(int fb_id);
55 /*#define WAIT_FOR_SYNC 1*/
57 static int rk3288_lcdc_get_id(u32 phy_base)
59 if (cpu_is_rk3288()) {
60 if (phy_base == 0xff930000)/*vop big*/
62 else if (phy_base == 0xff940000)/*vop lit*/
67 pr_err("un supported platform \n");
72 static int rk3288_lcdc_set_lut(struct rk_lcdc_driver *dev_drv)
77 struct lcdc_device *lcdc_dev = container_of(dev_drv,
78 struct lcdc_device,driver);
79 if (dev_drv->cur_screen->dsp_lut)
80 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
82 if ((dev_drv->cur_screen->cabc_lut) &&
83 (dev_drv->version == VOP_FULL_RK3288_V1_1))
84 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
86 lcdc_cfg_done(lcdc_dev);
88 if (dev_drv->cur_screen->dsp_lut) {
89 for (i = 0; i < 256; i++) {
90 v = dev_drv->cur_screen->dsp_lut[i];
91 c = lcdc_dev->dsp_lut_addr_base + (i << 2);
93 g = (v & 0xff00) << 4;
94 r = (v & 0xff0000) << 6;
96 for (j = 0; j < 4; j++) {
98 v += (1 + (1 << 10) + (1 << 20));
102 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
105 if ((dev_drv->cur_screen->cabc_lut) &&
106 (dev_drv->version == VOP_FULL_RK3288_V1_1)) {
107 for (i = 0; i < 128; i++) {
108 v = dev_drv->cur_screen->cabc_lut[i];
109 lcdc_writel(lcdc_dev, i * 4 + CABC_LUT_ADDR, v);
111 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
119 static int rk3288_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
121 #ifdef CONFIG_RK_FPGA
122 lcdc_dev->clk_on = 1;
125 if (!lcdc_dev->clk_on) {
126 clk_prepare_enable(lcdc_dev->hclk);
127 clk_prepare_enable(lcdc_dev->dclk);
128 clk_prepare_enable(lcdc_dev->aclk);
129 clk_prepare_enable(lcdc_dev->pd);
130 spin_lock(&lcdc_dev->reg_lock);
131 lcdc_dev->clk_on = 1;
132 spin_unlock(&lcdc_dev->reg_lock);
138 static int rk3288_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
140 #ifdef CONFIG_RK_FPGA
141 lcdc_dev->clk_on = 0;
144 if (lcdc_dev->clk_on) {
145 spin_lock(&lcdc_dev->reg_lock);
146 lcdc_dev->clk_on = 0;
147 spin_unlock(&lcdc_dev->reg_lock);
149 clk_disable_unprepare(lcdc_dev->dclk);
150 clk_disable_unprepare(lcdc_dev->hclk);
151 clk_disable_unprepare(lcdc_dev->aclk);
152 clk_disable_unprepare(lcdc_dev->pd);
158 static int rk3288_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
161 spin_lock(&lcdc_dev->reg_lock);
162 if (likely(lcdc_dev->clk_on)) {
163 mask = m_DSP_HOLD_VALID_INTR_EN | m_FS_INTR_EN |
164 m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_EN;
165 val = v_DSP_HOLD_VALID_INTR_EN(0) | v_FS_INTR_EN(0) |
166 v_LINE_FLAG_INTR_EN(0) | v_BUS_ERROR_INTR_EN(0);
167 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
169 mask = m_DSP_HOLD_VALID_INTR_CLR | m_FS_INTR_CLR |
170 m_LINE_FLAG_INTR_CLR | m_LINE_FLAG_INTR_CLR;
171 val = v_DSP_HOLD_VALID_INTR_CLR(0) | v_FS_INTR_CLR(0) |
172 v_LINE_FLAG_INTR_CLR(0) | v_BUS_ERROR_INTR_CLR(0);
173 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
175 mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
176 m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
177 m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
178 m_POST_BUF_EMPTY_INTR_EN;
179 val = v_WIN0_EMPTY_INTR_EN(0) | v_WIN1_EMPTY_INTR_EN(0) |
180 v_WIN2_EMPTY_INTR_EN(0) | v_WIN3_EMPTY_INTR_EN(0) |
181 v_HWC_EMPTY_INTR_EN(0) | v_POST_BUF_EMPTY_INTR_EN(0) |
182 v_PWM_GEN_INTR_EN(0);
183 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
185 mask = m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
186 m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
187 m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
188 m_POST_BUF_EMPTY_INTR_CLR;
189 val = v_WIN0_EMPTY_INTR_CLR(0) | v_WIN1_EMPTY_INTR_CLR(0) |
190 v_WIN2_EMPTY_INTR_CLR(0) | v_WIN3_EMPTY_INTR_CLR(0) |
191 v_HWC_EMPTY_INTR_CLR(0) | v_POST_BUF_EMPTY_INTR_CLR(0) |
192 v_PWM_GEN_INTR_CLR(0);
193 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
194 lcdc_cfg_done(lcdc_dev);
195 spin_unlock(&lcdc_dev->reg_lock);
197 spin_unlock(&lcdc_dev->reg_lock);
202 static int rk3288_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
204 struct lcdc_device *lcdc_dev = container_of(dev_drv,
207 int *cbase = (int *)lcdc_dev->regs;
208 int *regsbak = (int *)lcdc_dev->regsbak;
211 printk("back up reg:\n");
212 for (i = 0; i <= (0x200 >> 4); i++) {
213 printk("0x%04x: ",i*16);
214 for (j = 0; j < 4; j++)
215 printk("%08x ", *(regsbak + i * 4 + j));
219 printk("lcdc reg:\n");
220 for (i = 0; i <= (0x200 >> 4); i++) {
221 printk("0x%04x: ",i*16);
222 for (j = 0; j < 4; j++)
223 printk("%08x ", readl_relaxed(cbase + i * 4 + j));
231 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en) \
234 spin_lock(&lcdc_dev->reg_lock); \
235 msk = m_WIN##id##_EN; \
236 val = v_WIN##id##_EN(en); \
237 lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val); \
238 lcdc_cfg_done(lcdc_dev); \
239 /*val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk); \
240 while (val != (!!en)) { \
241 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk); \
243 spin_unlock(&lcdc_dev->reg_lock); \
251 /*enable/disable win directly*/
252 static int rk3288_lcdc_win_direct_en
253 (struct rk_lcdc_driver *drv, int win_id , int en)
255 struct lcdc_device *lcdc_dev = container_of(drv,
256 struct lcdc_device, driver);
258 win0_enable(lcdc_dev, en);
259 else if (win_id == 1)
260 win1_enable(lcdc_dev, en);
261 else if (win_id == 2)
262 win2_enable(lcdc_dev, en);
263 else if (win_id == 3)
264 win3_enable(lcdc_dev, en);
266 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
271 #define SET_WIN_ADDR(id) \
272 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
275 spin_lock(&lcdc_dev->reg_lock); \
276 lcdc_writel(lcdc_dev,WIN##id##_YRGB_MST,addr); \
277 msk = m_WIN##id##_EN; \
278 val = v_WIN0_EN(1); \
279 lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk,val); \
280 lcdc_cfg_done(lcdc_dev); \
281 spin_unlock(&lcdc_dev->reg_lock); \
287 int rk3288_lcdc_direct_set_win_addr
288 (struct rk_lcdc_driver *dev_drv, int win_id, u32 addr)
290 struct lcdc_device *lcdc_dev = container_of(dev_drv,
291 struct lcdc_device, driver);
293 set_win0_addr(lcdc_dev, addr);
295 set_win1_addr(lcdc_dev, addr);
300 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
304 struct rk_screen *screen = lcdc_dev->driver.cur_screen;
305 u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
306 u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
308 struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
310 spin_lock(&lcdc_dev->reg_lock);
311 memcpy(lcdc_dev->regsbak, lcdc_dev->regs, FRC_LOWER11_1);
312 for (reg = 0; reg < FRC_LOWER11_1; reg += 4) {
313 val = lcdc_readl(lcdc_dev, reg);
316 lcdc_dev->driver.version = val;
320 (val & m_WIN0_ACT_WIDTH) + 1;
322 ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
325 win0->area[0].xsize =
326 (val & m_WIN0_DSP_WIDTH) + 1;
327 win0->area[0].ysize =
328 ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
331 st_x = val & m_WIN0_DSP_XST;
332 st_y = (val & m_WIN0_DSP_YST) >> 16;
333 win0->area[0].xpos = st_x - h_pw_bp;
334 win0->area[0].ypos = st_y - v_pw_bp;
337 win0->state = val & m_WIN0_EN;
338 win0->area[0].fmt_cfg =
339 (val & m_WIN0_DATA_FMT) >> 1;
340 win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
341 win0->area[0].format = win0->area[0].fmt_cfg;
344 win0->area[0].y_vir_stride =
345 val & m_WIN0_VIR_STRIDE;
346 win0->area[0].uv_vir_stride =
347 (val & m_WIN0_VIR_STRIDE_UV) >> 16;
348 if (win0->area[0].format == ARGB888)
350 win0->area[0].y_vir_stride;
351 else if (win0->area[0].format == RGB888)
353 win0->area[0].y_vir_stride * 4 / 3;
354 else if (win0->area[0].format == RGB565)
356 2 * win0->area[0].y_vir_stride;
359 4 * win0->area[0].y_vir_stride;
362 win0->area[0].smem_start = val;
365 win0->area[0].cbr_start = val;
367 case DSP_VACT_ST_END:
368 if (support_uboot_display()) {
370 (val & 0x1fff) - ((val >> 16) & 0x1fff);
372 st_y - ((val >> 16) & 0x1fff);
375 case DSP_HACT_ST_END:
376 if (support_uboot_display()) {
378 (val & 0x1fff) - ((val >> 16) & 0x1fff);
380 st_x - ((val >> 16) & 0x1fff);
387 spin_unlock(&lcdc_dev->reg_lock);
391 /********do basic init*********/
392 static int rk3288_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
396 struct lcdc_device *lcdc_dev = container_of(dev_drv,
400 if (lcdc_dev->pre_init)
403 lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
404 lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
405 lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
406 lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
408 if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||
409 (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
410 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
413 if (!support_uboot_display())
414 rk_disp_pwr_enable(dev_drv);
415 rk3288_lcdc_clk_enable(lcdc_dev);
417 /*backup reg config at uboot*/
418 lcdc_read_reg_defalut_cfg(lcdc_dev);
420 #ifndef CONFIG_RK_FPGA
421 if (lcdc_dev->pwr18 == true) {
422 v = 0x00010001; /*bit14: 1,1.8v;0,3.3v*/
423 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL);
426 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL);
429 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_0,0x15110903);
430 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_1,0x00030911);
431 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_0,0x1a150b04);
432 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_1,0x00040b15);
433 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_0,0x15110903);
434 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_1,0x00030911);
436 lcdc_writel(lcdc_dev,FRC_LOWER01_0,0x12844821);
437 lcdc_writel(lcdc_dev,FRC_LOWER01_1,0x21488412);
438 lcdc_writel(lcdc_dev,FRC_LOWER10_0,0xa55a9696);
439 lcdc_writel(lcdc_dev,FRC_LOWER10_1,0x5aa56969);
440 lcdc_writel(lcdc_dev,FRC_LOWER11_0,0xdeb77deb);
441 lcdc_writel(lcdc_dev,FRC_LOWER11_1,0xed7bb7de);
443 mask = m_AUTO_GATING_EN;
444 val = v_AUTO_GATING_EN(0);
445 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask,val);
446 lcdc_cfg_done(lcdc_dev);
447 /*disable win0 to workaround iommu pagefault */
448 /*if (dev_drv->iommu_enabled) */
449 /* win0_enable(lcdc_dev, 0); */
450 lcdc_dev->pre_init = true;
456 static void rk3288_lcdc_deint(struct lcdc_device *lcdc_dev)
460 rk3288_lcdc_disable_irq(lcdc_dev);
461 spin_lock(&lcdc_dev->reg_lock);
462 if (likely(lcdc_dev->clk_on)) {
463 lcdc_dev->clk_on = 0;
464 lcdc_set_bit(lcdc_dev, SYS_CTRL, m_STANDBY_EN);
465 lcdc_cfg_done(lcdc_dev);
466 spin_unlock(&lcdc_dev->reg_lock);
468 spin_unlock(&lcdc_dev->reg_lock);
472 static int rk3288_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
474 struct lcdc_device *lcdc_dev =
475 container_of(dev_drv, struct lcdc_device, driver);
476 struct rk_screen *screen = dev_drv->cur_screen;
477 u16 x_res = screen->mode.xres;
478 u16 y_res = screen->mode.yres;
481 u16 post_hsd_en,post_vsd_en;
482 u16 post_dsp_hact_st,post_dsp_hact_end;
483 u16 post_dsp_vact_st,post_dsp_vact_end;
484 u16 post_dsp_vact_st_f1,post_dsp_vact_end_f1;
485 u16 post_h_fac,post_v_fac;
487 screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200;
488 screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200;
489 screen->post_xsize = x_res *
490 (dev_drv->overscan.left + dev_drv->overscan.right) / 200;
491 screen->post_ysize = y_res *
492 (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200;
493 h_total = screen->mode.hsync_len+screen->mode.left_margin +
494 x_res + screen->mode.right_margin;
495 v_total = screen->mode.vsync_len+screen->mode.upper_margin +
496 y_res + screen->mode.lower_margin;
498 if(screen->post_dsp_stx + screen->post_xsize > x_res){
499 dev_warn(lcdc_dev->dev, "post:stx[%d] + xsize[%d] > x_res[%d]\n",
500 screen->post_dsp_stx,screen->post_xsize,x_res);
501 screen->post_dsp_stx = x_res - screen->post_xsize;
503 if(screen->x_mirror == 0){
504 post_dsp_hact_st=screen->post_dsp_stx +
505 screen->mode.hsync_len+screen->mode.left_margin;
506 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
508 post_dsp_hact_end = h_total - screen->mode.right_margin -
509 screen->post_dsp_stx;
510 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
512 if((screen->post_xsize < x_res)&&(screen->post_xsize != 0)){
515 GET_SCALE_FACTOR_BILI_DN(x_res , screen->post_xsize);
522 if(screen->post_dsp_sty + screen->post_ysize > y_res){
523 dev_warn(lcdc_dev->dev, "post:sty[%d] + ysize[%d] > y_res[%d]\n",
524 screen->post_dsp_sty,screen->post_ysize,y_res);
525 screen->post_dsp_sty = y_res - screen->post_ysize;
528 if(screen->y_mirror == 0){
529 post_dsp_vact_st = screen->post_dsp_sty +
530 screen->mode.vsync_len+screen->mode.upper_margin;
531 post_dsp_vact_end = post_dsp_vact_st + screen->post_ysize;
533 post_dsp_vact_end = v_total - screen->mode.lower_margin -
534 - screen->post_dsp_sty;
535 post_dsp_vact_st = post_dsp_vact_end - screen->post_ysize;
537 if((screen->post_ysize < y_res)&&(screen->post_ysize != 0)){
539 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res, screen->post_ysize);
545 if(screen->interlace == 1){
546 post_dsp_vact_st_f1 = v_total + post_dsp_vact_st;
547 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 + screen->post_ysize;
549 post_dsp_vact_st_f1 = 0;
550 post_dsp_vact_end_f1 = 0;
552 DBG(1,"post:xsize=%d,ysize=%d,xpos=%d,ypos=%d,"
553 "hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
554 screen->post_xsize,screen->post_ysize,screen->xpos,screen->ypos,
555 post_hsd_en,post_h_fac,post_vsd_en,post_v_fac);
556 mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
557 val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
558 v_DSP_HACT_ST_POST(post_dsp_hact_st);
559 lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
561 mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
562 val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
563 v_DSP_VACT_ST_POST(post_dsp_vact_st);
564 lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
566 mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
567 val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
568 v_POST_VS_FACTOR_YRGB(post_v_fac);
569 lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
571 mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
572 val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
573 v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
574 lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
576 mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
577 val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
578 lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
582 static int rk3288_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
584 struct lcdc_device *lcdc_dev = container_of(dev_drv,
588 struct rk_lcdc_win *win;
589 u32 colorkey_r,colorkey_g,colorkey_b;
592 win = dev_drv->win[i];
593 key_val = win->color_key_val;
594 colorkey_r = (key_val & 0xff)<<2;
595 colorkey_g = ((key_val>>8)&0xff)<<12;
596 colorkey_b = ((key_val>>16)&0xff)<<22;
597 /*color key dither 565/888->aaa*/
598 key_val = colorkey_r | colorkey_g | colorkey_b;
601 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
604 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
607 lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
610 lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
613 printk(KERN_WARNING "%s:un support win num:%d\n",
621 static int rk3288_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv,int win_id)
623 struct lcdc_device *lcdc_dev =
624 container_of(dev_drv, struct lcdc_device, driver);
625 struct rk_lcdc_win *win = dev_drv->win[win_id];
626 struct alpha_config alpha_config;
629 int ppixel_alpha,global_alpha;
630 u32 src_alpha_ctl,dst_alpha_ctl;
631 ppixel_alpha = ((win->area[0].format == ARGB888) ||
632 (win->area[0].format == ABGR888)) ? 1 : 0;
633 global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
634 alpha_config.src_global_alpha_val = win->g_alpha_val;
635 win->alpha_mode = AB_SRC_OVER;
636 /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
637 __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,global_alpha);*/
638 switch(win->alpha_mode){
642 alpha_config.src_factor_mode=AA_ZERO;
643 alpha_config.dst_factor_mode=AA_ZERO;
646 alpha_config.src_factor_mode=AA_ONE;
647 alpha_config.dst_factor_mode=AA_ZERO;
650 alpha_config.src_factor_mode=AA_ZERO;
651 alpha_config.dst_factor_mode=AA_ONE;
654 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
656 alpha_config.src_factor_mode=AA_SRC_GLOBAL;
658 alpha_config.src_factor_mode=AA_ONE;
659 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
662 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
663 alpha_config.src_factor_mode=AA_SRC_INVERSE;
664 alpha_config.dst_factor_mode=AA_ONE;
667 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
668 alpha_config.src_factor_mode=AA_SRC;
669 alpha_config.dst_factor_mode=AA_ZERO;
672 alpha_config.src_factor_mode=AA_ZERO;
673 alpha_config.dst_factor_mode=AA_SRC;
676 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
677 alpha_config.src_factor_mode=AA_SRC_INVERSE;
678 alpha_config.dst_factor_mode=AA_ZERO;
681 alpha_config.src_factor_mode=AA_ZERO;
682 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
685 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
686 alpha_config.src_factor_mode=AA_SRC;
687 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
690 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
691 alpha_config.src_factor_mode=AA_SRC_INVERSE;
692 alpha_config.dst_factor_mode=AA_SRC;
695 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
696 alpha_config.src_factor_mode=AA_SRC_INVERSE;
697 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
699 case AB_SRC_OVER_GLOBAL:
700 alpha_config.src_global_alpha_mode=AA_PER_PIX_GLOBAL;
701 alpha_config.src_color_mode=AA_SRC_NO_PRE_MUL;
702 alpha_config.src_factor_mode=AA_SRC_GLOBAL;
703 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
706 pr_err("alpha mode error\n");
709 if((ppixel_alpha == 1)&&(global_alpha == 1)){
710 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
711 }else if(ppixel_alpha == 1){
712 alpha_config.src_global_alpha_mode = AA_PER_PIX;
713 }else if(global_alpha == 1){
714 alpha_config.src_global_alpha_mode = AA_GLOBAL;
716 dev_warn(lcdc_dev->dev,"alpha_en should be 0\n");
718 alpha_config.src_alpha_mode = AA_STRAIGHT;
719 alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
723 src_alpha_ctl = 0x60;
724 dst_alpha_ctl = 0x64;
727 src_alpha_ctl = 0xa0;
728 dst_alpha_ctl = 0xa4;
731 src_alpha_ctl = 0xdc;
732 dst_alpha_ctl = 0xec;
735 src_alpha_ctl = 0x12c;
736 dst_alpha_ctl = 0x13c;
739 mask = m_WIN0_DST_FACTOR_M0;
740 val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
741 lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
742 mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
743 m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
744 m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0|
745 m_WIN0_SRC_GLOBAL_ALPHA;
746 val = v_WIN0_SRC_ALPHA_EN(1) |
747 v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
748 v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
749 v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
750 v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
751 v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
752 v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
753 lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
757 static int rk3288_lcdc_area_swap(struct rk_lcdc_win *win,int area_num)
759 struct rk_lcdc_win_area area_temp;
762 area_temp = win->area[0];
763 win->area[0] = win->area[1];
764 win->area[1] = area_temp;
767 area_temp = win->area[0];
768 win->area[0] = win->area[2];
769 win->area[2] = area_temp;
772 area_temp = win->area[0];
773 win->area[0] = win->area[3];
774 win->area[3] = area_temp;
776 area_temp = win->area[1];
777 win->area[1] = win->area[2];
778 win->area[2] = area_temp;
781 printk(KERN_WARNING "un supported area num!\n");
787 static int rk3288_win_area_check_var(int win_id,int area_num,struct rk_lcdc_win_area *area_pre,
788 struct rk_lcdc_win_area *area_now)
790 if((area_pre->ypos >= area_now->ypos) ||
791 (area_pre->ypos+area_pre->ysize > area_now->ypos)){
794 "area_pre[%d]:ypos[%d],ysize[%d]\n"
795 "area_now[%d]:ypos[%d],ysize[%d]\n",
797 area_num-1,area_pre->ypos,area_pre->ysize,
798 area_num, area_now->ypos,area_now->ysize);
804 static int rk3288_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv,int win_id)
806 struct lcdc_device *lcdc_dev =
807 container_of(dev_drv, struct lcdc_device, driver);
808 struct rk_lcdc_win *win = dev_drv->win[win_id];
809 unsigned int mask, val, off;
811 if((win->win_lb_mode == 5) &&
812 (dev_drv->version == VOP_FULL_RK3288_V1_0))
813 win->win_lb_mode = 4;
816 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
817 m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_UV_SWAP;
818 val = v_WIN0_EN(win->state) |
819 v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
820 v_WIN0_FMT_10(win->fmt_10) |
821 v_WIN0_LB_MODE(win->win_lb_mode) |
822 v_WIN0_RB_SWAP(win->area[0].swap_rb) |
823 v_WIN0_UV_SWAP(win->area[0].swap_uv);
824 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val);
826 mask = m_WIN0_BIC_COE_SEL |
827 m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
828 m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
829 m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
830 m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
831 m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
832 m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
833 m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
834 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
835 v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
836 v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
837 v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
838 v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
839 v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
840 v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
841 v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
842 v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
843 v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
844 v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
845 v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
846 v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
847 v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
848 v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
849 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1+off, mask,val);
851 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
852 v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
853 lcdc_writel(lcdc_dev, WIN0_VIR+off, val);
854 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off, win->area[0].y_addr);
855 lcdc_writel(lcdc_dev, WIN0_CBR_MST+off, win->area[0].uv_addr);*/
856 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
857 v_WIN0_ACT_HEIGHT(win->area[0].yact);
858 lcdc_writel(lcdc_dev, WIN0_ACT_INFO+off, val);
860 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
861 v_WIN0_DSP_HEIGHT(win->area[0].ysize);
862 lcdc_writel(lcdc_dev, WIN0_DSP_INFO+off, val);
864 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
865 v_WIN0_DSP_YST(win->area[0].dsp_sty);
866 lcdc_writel(lcdc_dev, WIN0_DSP_ST+off, val);
868 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
869 v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
870 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB+off, val);
872 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
873 v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
874 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR+off, val);
875 if(win->alpha_en == 1)
876 rk3288_lcdc_alpha_cfg(dev_drv,win_id);
878 mask = m_WIN0_SRC_ALPHA_EN;
879 val = v_WIN0_SRC_ALPHA_EN(0);
880 lcdc_msk_reg(lcdc_dev,WIN0_SRC_ALPHA_CTRL+off,mask,val);
885 val = v_WIN0_EN(win->state);
886 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val);
891 static int rk3288_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv,int win_id)
893 struct lcdc_device *lcdc_dev =
894 container_of(dev_drv, struct lcdc_device, driver);
895 struct rk_lcdc_win *win = dev_drv->win[win_id];
896 struct rk_screen *screen = dev_drv->cur_screen;
897 unsigned int mask, val, off;
898 struct fb_info *fb0 = rk_get_fb(0);
900 off = (win_id-2) * 0x50;
901 if((screen->y_mirror == 1)&&(win->area_num > 1)){
902 rk3288_lcdc_area_swap(win,win->area_num);
906 mask = m_WIN2_EN | m_WIN2_DATA_FMT | m_WIN2_RB_SWAP;
908 v_WIN2_DATA_FMT(win->area[0].fmt_cfg) |
909 v_WIN2_RB_SWAP(win->area[0].swap_rb);
910 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
912 if(win->area[0].state == 1){
913 mask = m_WIN2_MST0_EN;
914 val = v_WIN2_MST0_EN(win->area[0].state);
915 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
917 mask = m_WIN2_VIR_STRIDE0;
918 val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
919 lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val);
921 /*lcdc_writel(lcdc_dev,WIN2_MST0+off,win->area[0].y_addr);*/
922 val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
923 v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
924 lcdc_writel(lcdc_dev,WIN2_DSP_INFO0+off,val);
925 val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
926 v_WIN2_DSP_YST0(win->area[0].dsp_sty);
927 lcdc_writel(lcdc_dev,WIN2_DSP_ST0+off,val);
929 mask = m_WIN2_MST0_EN;
930 val = v_WIN2_MST0_EN(0);
931 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
932 lcdc_writel(lcdc_dev, WIN2_MST0 + off,
933 fb0->fix.smem_start);
936 if(win->area[1].state == 1){
937 rk3288_win_area_check_var(win_id,1,&win->area[0],&win->area[1]);
939 mask = m_WIN2_MST1_EN;
940 val = v_WIN2_MST1_EN(win->area[1].state);
941 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
943 mask = m_WIN2_VIR_STRIDE1;
944 val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
945 lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val);
947 /*lcdc_writel(lcdc_dev,WIN2_MST1+off,win->area[1].y_addr);*/
948 val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
949 v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
950 lcdc_writel(lcdc_dev,WIN2_DSP_INFO1+off,val);
951 val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
952 v_WIN2_DSP_YST1(win->area[1].dsp_sty);
953 lcdc_writel(lcdc_dev,WIN2_DSP_ST1+off,val);
955 mask = m_WIN2_MST1_EN;
956 val = v_WIN2_MST1_EN(0);
957 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
958 lcdc_writel(lcdc_dev, WIN2_MST1 + off,
959 fb0->fix.smem_start);
962 if(win->area[2].state == 1){
963 rk3288_win_area_check_var(win_id,2,&win->area[1],&win->area[2]);
965 mask = m_WIN2_MST2_EN;
966 val = v_WIN2_MST2_EN(win->area[2].state);
967 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
969 mask = m_WIN2_VIR_STRIDE2;
970 val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
971 lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val);
973 /*lcdc_writel(lcdc_dev,WIN2_MST2+off,win->area[2].y_addr);*/
974 val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
975 v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
976 lcdc_writel(lcdc_dev,WIN2_DSP_INFO2+off,val);
977 val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
978 v_WIN2_DSP_YST2(win->area[2].dsp_sty);
979 lcdc_writel(lcdc_dev,WIN2_DSP_ST2+off,val);
981 mask = m_WIN2_MST2_EN;
982 val = v_WIN2_MST2_EN(0);
983 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
984 lcdc_writel(lcdc_dev, WIN2_MST2 + off,
985 fb0->fix.smem_start);
988 if(win->area[3].state == 1){
989 rk3288_win_area_check_var(win_id,3,&win->area[2],&win->area[3]);
991 mask = m_WIN2_MST3_EN;
992 val = v_WIN2_MST3_EN(win->area[3].state);
993 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
995 mask = m_WIN2_VIR_STRIDE3;
996 val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
997 lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val);
999 /*lcdc_writel(lcdc_dev,WIN2_MST3+off,win->area[3].y_addr);*/
1000 val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1001 v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1002 lcdc_writel(lcdc_dev,WIN2_DSP_INFO3+off,val);
1003 val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1004 v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1005 lcdc_writel(lcdc_dev,WIN2_DSP_ST3+off,val);
1007 mask = m_WIN2_MST3_EN;
1008 val = v_WIN2_MST3_EN(0);
1009 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
1010 lcdc_writel(lcdc_dev, WIN2_MST3 + off,
1011 fb0->fix.smem_start);
1014 if(win->alpha_en == 1)
1015 rk3288_lcdc_alpha_cfg(dev_drv,win_id);
1017 mask = m_WIN2_SRC_ALPHA_EN;
1018 val = v_WIN2_SRC_ALPHA_EN(0);
1019 lcdc_msk_reg(lcdc_dev,WIN2_SRC_ALPHA_CTRL+off,mask,val);
1022 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1023 m_WIN2_MST0_EN | m_WIN2_MST2_EN |
1025 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1026 v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) |
1028 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0+off, mask,val);
1033 static int rk3288_lcdc_reg_update(struct rk_lcdc_driver *dev_drv)
1035 struct lcdc_device *lcdc_dev =
1036 container_of(dev_drv, struct lcdc_device, driver);
1038 unsigned long flags;
1040 spin_lock(&lcdc_dev->reg_lock);
1041 if(likely(lcdc_dev->clk_on))
1043 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1044 v_STANDBY_EN(lcdc_dev->standby));
1045 rk3288_win_0_1_reg_update(dev_drv,0);
1046 rk3288_win_0_1_reg_update(dev_drv,1);
1047 rk3288_win_2_3_reg_update(dev_drv,2);
1048 rk3288_win_2_3_reg_update(dev_drv,3);
1049 /*rk3288_lcdc_post_cfg(dev_drv);*/
1050 lcdc_cfg_done(lcdc_dev);
1052 spin_unlock(&lcdc_dev->reg_lock);
1054 /*if (dev_drv->wait_fs) {*/
1056 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1057 init_completion(&dev_drv->frame_done);
1058 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1059 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
1061 (dev_drv->cur_screen->ft +
1063 if (!timeout && (!dev_drv->frame_done.done)) {
1064 dev_warn(lcdc_dev->dev, "wait for new frame start time out!\n");
1068 DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1073 static int rk3288_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1075 memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0x1fc);
1078 static int rk3288_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1081 struct lcdc_device *lcdc_dev =
1082 container_of(dev_drv, struct lcdc_device, driver);
1084 if (unlikely(!lcdc_dev->clk_on)) {
1085 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
1088 if (dev_drv->iommu_enabled) {
1089 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1091 if (likely(lcdc_dev->clk_on)) {
1092 spin_lock(&lcdc_dev->reg_lock);
1095 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1096 mask = m_AXI_MAX_OUTSTANDING_EN | m_AXI_OUTSTANDING_MAX_NUM;
1097 val = v_AXI_OUTSTANDING_MAX_NUM(31) | v_AXI_MAX_OUTSTANDING_EN(1);
1098 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1099 spin_unlock(&lcdc_dev->reg_lock);
1101 lcdc_dev->iommu_status = 1;
1102 rockchip_iovmm_activate(dev_drv->dev);
1108 static int rk3288_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate)
1110 #ifdef CONFIG_RK_FPGA
1114 struct lcdc_device *lcdc_dev =
1115 container_of(dev_drv, struct lcdc_device, driver);
1116 struct rk_screen *screen = dev_drv->cur_screen;
1119 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1121 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1122 lcdc_dev->pixclock =
1123 div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1124 lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1126 fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1127 screen->ft = 1000 / fps;
1128 dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1129 lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1134 static void rk3288_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1136 struct lcdc_device *lcdc_dev =
1137 container_of(dev_drv, struct lcdc_device, driver);
1140 if (dev_drv->output_color == COLOR_RGB) {
1141 bcsh_color_bar = lcdc_readl(lcdc_dev, BCSH_COLOR_BAR);
1142 if (((bcsh_color_bar & m_BCSH_EN) == 1) ||
1143 (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1144 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1145 m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1146 v_BCSH_R2Y_EN(1) | v_BCSH_Y2R_EN(1));
1148 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1149 m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1150 v_BCSH_R2Y_EN(0) | v_BCSH_Y2R_EN(0));
1151 } else { /* RGB2YUV */
1152 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1153 m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1154 v_BCSH_R2Y_EN(1) | v_BCSH_Y2R_EN(0));
1158 static int rk3288_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1159 u16 *yact, int *format, u32 *dsp_addr,
1162 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1163 struct lcdc_device, driver);
1166 spin_lock(&lcdc_dev->reg_lock);
1168 val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1169 *xact = (val & m_WIN0_ACT_WIDTH) + 1;
1170 *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1;
1172 val = lcdc_readl(lcdc_dev, WIN0_CTRL0);
1173 *format = (val & m_WIN0_DATA_FMT) >> 1;
1174 *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1176 spin_unlock(&lcdc_dev->reg_lock);
1181 static int rk3288_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1182 int format, u16 xact, u16 yact, u16 xvir,
1185 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1186 struct lcdc_device, driver);
1188 struct rk_lcdc_win *win = dev_drv->win[0];
1189 int swap = (format == RGB888) ? 1 : 0;
1191 mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP;
1192 val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap);
1193 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1195 lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE,
1196 v_WIN0_VIR_STRIDE(xvir));
1197 lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) |
1198 v_WIN0_ACT_HEIGHT(yact));
1200 lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1202 lcdc_cfg_done(lcdc_dev);
1204 win->last_state = 1;
1209 static int rk3288_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1214 struct lcdc_device *lcdc_dev =
1215 container_of(dev_drv, struct lcdc_device, driver);
1216 struct rk_screen *screen = dev_drv->cur_screen;
1217 u16 hsync_len = screen->mode.hsync_len;
1218 u16 left_margin = screen->mode.left_margin;
1219 u16 right_margin = screen->mode.right_margin;
1220 u16 vsync_len = screen->mode.vsync_len;
1221 u16 upper_margin = screen->mode.upper_margin;
1222 u16 lower_margin = screen->mode.lower_margin;
1223 u16 x_res = screen->mode.xres;
1224 u16 y_res = screen->mode.yres;
1226 u16 h_total,v_total;
1228 int hdmi_dclk_out_en = 0;
1230 if (unlikely(!lcdc_dev->clk_on)) {
1231 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
1235 h_total = hsync_len + left_margin + x_res + right_margin;
1236 v_total = vsync_len + upper_margin + y_res + lower_margin;
1238 screen->post_dsp_stx = x_res * (100 - screen->overscan.left) / 200;
1239 screen->post_dsp_sty = y_res * (100 - screen->overscan.top) / 200;
1240 screen->post_xsize = x_res * (screen->overscan.left + screen->overscan.right) / 200;
1241 screen->post_ysize = y_res * (screen->overscan.top + screen->overscan.bottom) / 200;
1243 spin_lock(&lcdc_dev->reg_lock);
1244 if (likely(lcdc_dev->clk_on)) {
1245 switch (screen->face) {
1248 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1249 m_DITHER_DOWN_SEL | m_DITHER_UP_EN |
1250 m_PRE_DITHER_DOWN_EN;
1251 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1252 v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) |
1253 v_PRE_DITHER_DOWN_EN(1);
1254 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1258 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1259 m_DITHER_DOWN_SEL | m_DITHER_UP_EN |
1260 m_PRE_DITHER_DOWN_EN;
1261 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1262 v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) |
1263 v_PRE_DITHER_DOWN_EN(1);
1264 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1268 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1269 m_DITHER_DOWN_SEL | m_DITHER_UP_EN |
1270 m_PRE_DITHER_DOWN_EN;
1271 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1272 v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) |
1273 v_PRE_DITHER_DOWN_EN(1);
1274 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1278 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1279 m_DITHER_DOWN_SEL | m_DITHER_UP_EN |
1280 m_PRE_DITHER_DOWN_EN;
1281 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1282 v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) |
1283 v_PRE_DITHER_DOWN_EN(1);
1284 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1288 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN |
1289 m_PRE_DITHER_DOWN_EN;
1290 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) |
1291 v_PRE_DITHER_DOWN_EN(1);
1292 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1295 hdmi_dclk_out_en = 1;
1298 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN |
1299 m_PRE_DITHER_DOWN_EN;
1300 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) |
1301 v_PRE_DITHER_DOWN_EN(1);
1302 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1304 case OUT_YUV_420_10BIT:
1305 hdmi_dclk_out_en = 1;
1308 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN |
1309 m_PRE_DITHER_DOWN_EN;
1310 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) |
1311 v_PRE_DITHER_DOWN_EN(0);
1312 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1316 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN |
1317 m_PRE_DITHER_DOWN_EN;
1318 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) |
1319 v_PRE_DITHER_DOWN_EN(0);
1320 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1323 dev_err(lcdc_dev->dev,"un supported interface!\n");
1326 switch(screen->type){
1329 case SCREEN_DUAL_LVDS:
1330 case SCREEN_LVDS_10BIT:
1331 case SCREEN_DUAL_LVDS_10BIT:
1332 mask = m_RGB_OUT_EN;
1333 val = v_RGB_OUT_EN(1);
1335 v |= (lcdc_dev->id << 3);
1338 if ((screen->face == OUT_P888) ||
1339 (screen->face == OUT_P101010))
1340 face = OUT_P101010;/*RGB 101010 output*/
1341 mask = m_HDMI_OUT_EN;
1342 val = v_HDMI_OUT_EN(1);
1345 mask = m_MIPI_OUT_EN;
1346 val = v_MIPI_OUT_EN(1);
1348 case SCREEN_DUAL_MIPI:
1349 mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN;
1350 val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1);
1353 face = OUT_P101010; /*RGB 101010 output*/
1354 mask = m_EDP_OUT_EN;
1355 val = v_EDP_OUT_EN(1);
1358 if (dev_drv->version == VOP_FULL_RK3288_V1_1) {
1359 mask |= m_HDMI_DCLK_OUT_EN;
1360 val |= v_HDMI_DCLK_OUT_EN(hdmi_dclk_out_en);
1362 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1363 #ifndef CONFIG_RK_FPGA
1364 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
1366 mask = m_DSP_OUT_MODE | m_DSP_HSYNC_POL | m_DSP_VSYNC_POL |
1367 m_DSP_DEN_POL | m_DSP_DCLK_POL | m_DSP_BG_SWAP |
1368 m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1369 m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1370 m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN |
1372 val = v_DSP_OUT_MODE(face) | v_DSP_HSYNC_POL(screen->pin_hsync) |
1373 v_DSP_VSYNC_POL(screen->pin_vsync) |
1374 v_DSP_DEN_POL(screen->pin_den) | v_DSP_DCLK_POL(screen->pin_dclk) |
1375 v_DSP_BG_SWAP(screen->swap_gb) | v_DSP_RB_SWAP(screen->swap_rb) |
1376 v_DSP_RG_SWAP(screen->swap_rg) |
1377 v_DSP_DELTA_SWAP(screen->swap_delta) |
1378 v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1379 v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1380 v_DSP_X_MIR_EN(screen->x_mirror) |
1381 v_DSP_Y_MIR_EN(screen->y_mirror) |
1382 v_DSP_DCLK_DDR(dclk_ddr);
1383 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1385 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1386 val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) | v_DSP_BG_RED(0);
1387 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1389 mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1390 val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1391 lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1393 mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1394 val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1395 v_DSP_HACT_ST(hsync_len + left_margin);
1396 lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1398 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1399 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1400 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1402 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1403 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1404 v_DSP_VACT_ST(vsync_len + upper_margin);
1405 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1407 rk3288_lcdc_post_cfg(dev_drv);
1408 mask = m_DSP_LINE_FLAG_NUM;
1409 val = v_DSP_LINE_FLAG_NUM(vsync_len + upper_margin + y_res);
1410 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
1411 dev_drv->output_color = screen->color_mode;
1412 if (dev_drv->version == VOP_FULL_RK3288_V1_1) {
1413 rk3288_lcdc_bcsh_path_sel(dev_drv);
1415 if (dev_drv->output_color != COLOR_RGB) {
1416 pr_err("vop ver:%x,unsupport output color:%d\n",
1417 dev_drv->version, dev_drv->output_color);
1422 spin_unlock(&lcdc_dev->reg_lock);
1423 rk3288_lcdc_set_dclk(dev_drv, 1);
1424 if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1425 dev_drv->trsm_ops->enable)
1426 dev_drv->trsm_ops->enable();
1433 /*enable layer,open:1,enable;0 disable*/
1434 static int win0_open(struct lcdc_device *lcdc_dev, bool open)
1436 spin_lock(&lcdc_dev->reg_lock);
1437 if (likely(lcdc_dev->clk_on)) {
1439 if (!lcdc_dev->atv_layer_cnt) {
1440 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1441 lcdc_dev->standby = 0;
1443 lcdc_dev->atv_layer_cnt++;
1444 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1445 lcdc_dev->atv_layer_cnt--;
1447 lcdc_dev->driver.win[0]->state = open;
1448 if (!lcdc_dev->atv_layer_cnt) {
1449 dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1450 lcdc_dev->standby = 1;
1453 spin_unlock(&lcdc_dev->reg_lock);
1458 static int win1_open(struct lcdc_device *lcdc_dev, bool open)
1460 spin_lock(&lcdc_dev->reg_lock);
1461 if (likely(lcdc_dev->clk_on)) {
1463 if (!lcdc_dev->atv_layer_cnt) {
1464 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1465 lcdc_dev->standby = 0;
1467 lcdc_dev->atv_layer_cnt++;
1468 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1469 lcdc_dev->atv_layer_cnt--;
1471 lcdc_dev->driver.win[1]->state = open;
1473 /*if no layer used,disable lcdc*/
1474 if (!lcdc_dev->atv_layer_cnt) {
1475 dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1476 lcdc_dev->standby = 1;
1479 spin_unlock(&lcdc_dev->reg_lock);
1484 static int win2_open(struct lcdc_device *lcdc_dev, bool open)
1486 spin_lock(&lcdc_dev->reg_lock);
1487 if (likely(lcdc_dev->clk_on)) {
1489 if (!lcdc_dev->atv_layer_cnt) {
1490 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1491 lcdc_dev->standby = 0;
1493 lcdc_dev->atv_layer_cnt++;
1494 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1495 lcdc_dev->atv_layer_cnt--;
1497 lcdc_dev->driver.win[2]->state = open;
1499 /*if no layer used,disable lcdc*/
1500 if (!lcdc_dev->atv_layer_cnt) {
1501 dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1502 lcdc_dev->standby = 1;
1505 spin_unlock(&lcdc_dev->reg_lock);
1510 static int win3_open(struct lcdc_device *lcdc_dev, bool open)
1512 spin_lock(&lcdc_dev->reg_lock);
1513 if (likely(lcdc_dev->clk_on)) {
1515 if (!lcdc_dev->atv_layer_cnt) {
1516 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1517 lcdc_dev->standby = 0;
1519 lcdc_dev->atv_layer_cnt++;
1520 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1521 lcdc_dev->atv_layer_cnt--;
1523 lcdc_dev->driver.win[3]->state = open;
1525 /*if no layer used,disable lcdc*/
1526 if (!lcdc_dev->atv_layer_cnt) {
1527 dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1528 lcdc_dev->standby = 1;
1531 spin_unlock(&lcdc_dev->reg_lock);
1535 static int rk3288_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1537 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1538 struct lcdc_device, driver);
1541 mask = m_FS_INTR_CLR | m_FS_INTR_EN | m_LINE_FLAG_INTR_CLR |
1542 m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_CLR |
1543 m_BUS_ERROR_INTR_EN;
1544 val = v_FS_INTR_CLR(1) | v_FS_INTR_EN(1) | v_LINE_FLAG_INTR_CLR(1) |
1545 v_LINE_FLAG_INTR_EN(1) | v_BUS_ERROR_INTR_CLR(1) | v_BUS_ERROR_INTR_EN(0);
1546 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
1547 #ifdef LCDC_IRQ_EMPTY_DEBUG
1548 mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN | m_WIN2_EMPTY_INTR_EN |
1549 m_WIN3_EMPTY_INTR_EN |m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
1551 val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) | v_WIN2_EMPTY_INTR_EN(1) |
1552 v_WIN3_EMPTY_INTR_EN(1)| v_HWC_EMPTY_INTR_EN(1) | v_POST_BUF_EMPTY_INTR_EN(1) |
1553 v_PWM_GEN_INTR_EN(1);
1554 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
1559 static int rk3288_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1562 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1563 struct lcdc_device, driver);
1564 int sys_status = (dev_drv->id == 0) ?
1565 SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
1567 /*enable clk,when first layer open */
1568 if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1569 rockchip_set_system_status(sys_status);
1570 rk3288_lcdc_pre_init(dev_drv);
1571 rk3288_lcdc_clk_enable(lcdc_dev);
1572 rk3288_lcdc_enable_irq(dev_drv);
1573 if (dev_drv->iommu_enabled) {
1574 if (!dev_drv->mmu_dev) {
1576 rk_fb_get_sysmmu_device_by_compatible(dev_drv->mmu_dts_name);
1577 if (dev_drv->mmu_dev) {
1578 rk_fb_platform_set_sysmmu(dev_drv->mmu_dev,
1581 dev_err(dev_drv->dev,
1582 "failed to get rockchip iommu device\n");
1587 rk3288_lcdc_reg_restore(lcdc_dev);
1588 /*if (dev_drv->iommu_enabled)
1589 rk3368_lcdc_mmu_en(dev_drv); */
1590 if ((support_uboot_display()&&(lcdc_dev->prop == PRMRY))) {
1591 rk3288_lcdc_set_dclk(dev_drv, 0);
1592 /* rk3288_lcdc_enable_irq(dev_drv); */
1594 rk3288_load_screen(dev_drv, 1);
1596 if (dev_drv->bcsh.enable)
1597 rk3288_lcdc_set_bcsh(dev_drv, 1);
1598 spin_lock(&lcdc_dev->reg_lock);
1599 rk3288_lcdc_set_lut(dev_drv);
1600 spin_unlock(&lcdc_dev->reg_lock);
1604 win0_open(lcdc_dev, open);
1605 else if (win_id == 1)
1606 win1_open(lcdc_dev, open);
1607 else if (win_id == 2)
1608 win2_open(lcdc_dev, open);
1609 else if (win_id == 3)
1610 win3_open(lcdc_dev, open);
1612 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1614 /* when all layer closed,disable clk */
1615 if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1616 rk3288_lcdc_disable_irq(lcdc_dev);
1617 rk3288_lcdc_reg_update(dev_drv);
1618 if (dev_drv->iommu_enabled) {
1619 if (dev_drv->mmu_dev) {
1620 rockchip_iovmm_deactivate(dev_drv->dev);
1621 lcdc_dev->iommu_status = 0;
1624 rk3288_lcdc_clk_disable(lcdc_dev);
1625 rockchip_clear_system_status(sys_status);
1631 static int win0_display(struct lcdc_device *lcdc_dev,
1632 struct rk_lcdc_win *win)
1636 y_addr = win->area[0].smem_start+win->area[0].y_offset;/*win->smem_start + win->y_offset;*/
1637 uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1638 DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n",
1639 lcdc_dev->id, __func__, y_addr, uv_addr,win->area[0].y_offset);
1640 spin_lock(&lcdc_dev->reg_lock);
1641 if (likely(lcdc_dev->clk_on)) {
1642 win->area[0].y_addr = y_addr;
1643 win->area[0].uv_addr = uv_addr;
1644 lcdc_writel(lcdc_dev, WIN0_YRGB_MST, win->area[0].y_addr);
1645 lcdc_writel(lcdc_dev, WIN0_CBR_MST, win->area[0].uv_addr);
1646 /*lcdc_cfg_done(lcdc_dev);*/
1648 spin_unlock(&lcdc_dev->reg_lock);
1654 static int win1_display(struct lcdc_device *lcdc_dev,
1655 struct rk_lcdc_win *win)
1659 y_addr = win->area[0].smem_start + win->area[0].y_offset;
1660 uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1661 DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",
1662 lcdc_dev->id, __func__, y_addr, uv_addr);
1664 spin_lock(&lcdc_dev->reg_lock);
1665 if (likely(lcdc_dev->clk_on)) {
1666 win->area[0].y_addr = y_addr;
1667 win->area[0].uv_addr = uv_addr;
1668 lcdc_writel(lcdc_dev, WIN1_YRGB_MST, win->area[0].y_addr);
1669 lcdc_writel(lcdc_dev, WIN1_CBR_MST, win->area[0].uv_addr);
1671 spin_unlock(&lcdc_dev->reg_lock);
1677 static int win2_display(struct lcdc_device *lcdc_dev,
1678 struct rk_lcdc_win *win)
1681 y_addr = win->area[0].smem_start + win->area[0].y_offset;
1682 DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n",
1683 lcdc_dev->id, __func__, y_addr);
1685 spin_lock(&lcdc_dev->reg_lock);
1686 if (likely(lcdc_dev->clk_on)){
1687 for(i=0;i<win->area_num;i++)
1688 win->area[i].y_addr =
1689 win->area[i].smem_start + win->area[i].y_offset;
1690 if (win->area[0].state)
1691 lcdc_writel(lcdc_dev, WIN2_MST0,
1692 win->area[0].y_addr);
1693 if (win->area[1].state)
1694 lcdc_writel(lcdc_dev, WIN2_MST1,
1695 win->area[1].y_addr);
1696 if (win->area[2].state)
1697 lcdc_writel(lcdc_dev, WIN2_MST2,
1698 win->area[2].y_addr);
1699 if (win->area[3].state)
1700 lcdc_writel(lcdc_dev, WIN2_MST3,
1701 win->area[3].y_addr);
1703 spin_unlock(&lcdc_dev->reg_lock);
1707 static int win3_display(struct lcdc_device *lcdc_dev,
1708 struct rk_lcdc_win *win)
1711 y_addr = win->area[0].smem_start + win->area[0].y_offset;
1712 DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n",
1713 lcdc_dev->id, __func__, y_addr);
1715 spin_lock(&lcdc_dev->reg_lock);
1716 if (likely(lcdc_dev->clk_on)){
1717 for(i=0;i<win->area_num;i++)
1718 win->area[i].y_addr =
1719 win->area[i].smem_start + win->area[i].y_offset;
1720 if (win->area[0].state)
1721 lcdc_writel(lcdc_dev, WIN3_MST0,
1722 win->area[0].y_addr);
1723 if (win->area[1].state)
1724 lcdc_writel(lcdc_dev, WIN3_MST1,
1725 win->area[1].y_addr);
1726 if (win->area[2].state)
1727 lcdc_writel(lcdc_dev, WIN3_MST2,
1728 win->area[2].y_addr);
1729 if (win->area[3].state)
1730 lcdc_writel(lcdc_dev, WIN3_MST3,
1731 win->area[3].y_addr);
1733 spin_unlock(&lcdc_dev->reg_lock);
1737 static int rk3288_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
1739 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1740 struct lcdc_device, driver);
1741 struct rk_lcdc_win *win = NULL;
1742 struct rk_screen *screen = dev_drv->cur_screen;
1744 #if defined(WAIT_FOR_SYNC)
1746 unsigned long flags;
1748 win = dev_drv->win[win_id];
1750 dev_err(dev_drv->dev, "screen is null!\n");
1754 win0_display(lcdc_dev, win);
1755 }else if(win_id == 1){
1756 win1_display(lcdc_dev, win);
1757 }else if(win_id == 2){
1758 win2_display(lcdc_dev, win);
1759 }else if(win_id == 3){
1760 win3_display(lcdc_dev, win);
1762 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1766 /*this is the first frame of the system ,enable frame start interrupt */
1767 if ((dev_drv->first_frame)) {
1768 dev_drv->first_frame = 0;
1769 rk3288_lcdc_enable_irq(dev_drv);
1771 #if defined(WAIT_FOR_SYNC)
1772 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1773 init_completion(&dev_drv->frame_done);
1774 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1775 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
1776 msecs_to_jiffies(dev_drv->
1779 if (!timeout && (!dev_drv->frame_done.done)) {
1780 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
1787 static int rk3288_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
1797 u32 yrgb_vScaleDnMult;
1798 u32 yrgb_xscl_factor;
1799 u32 yrgb_yscl_factor;
1800 u8 yrgb_vsd_bil_gt2=0;
1801 u8 yrgb_vsd_bil_gt4=0;
1807 u32 cbcr_vScaleDnMult;
1808 u32 cbcr_xscl_factor;
1809 u32 cbcr_yscl_factor;
1810 u8 cbcr_vsd_bil_gt2=0;
1811 u8 cbcr_vsd_bil_gt4=0;
1815 srcW = win->area[0].xact;
1816 srcH = win->area[0].yact;
1817 dstW = win->area[0].xsize;
1818 dstH = win->area[0].ysize;
1825 if ((yrgb_dstW*8 <= yrgb_srcW) || (yrgb_dstH*8 <= yrgb_srcH)) {
1826 pr_err("ERROR: yrgb scale exceed 8,"
1827 "srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
1828 yrgb_srcW,yrgb_srcH,yrgb_dstW,yrgb_dstH);
1830 if(yrgb_srcW < yrgb_dstW){
1831 win->yrgb_hor_scl_mode = SCALE_UP;
1832 }else if(yrgb_srcW > yrgb_dstW){
1833 win->yrgb_hor_scl_mode = SCALE_DOWN;
1835 win->yrgb_hor_scl_mode = SCALE_NONE;
1838 if(yrgb_srcH < yrgb_dstH){
1839 win->yrgb_ver_scl_mode = SCALE_UP;
1840 }else if (yrgb_srcH > yrgb_dstH){
1841 win->yrgb_ver_scl_mode = SCALE_DOWN;
1843 win->yrgb_ver_scl_mode = SCALE_NONE;
1847 switch (win->area[0].format) {
1881 if ((cbcr_dstW*8 <= cbcr_srcW) || (cbcr_dstH*8 <= cbcr_srcH)) {
1882 pr_err("ERROR: cbcr scale exceed 8,"
1883 "srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
1884 cbcr_srcW,cbcr_srcH,cbcr_dstW,cbcr_dstH);
1888 if(cbcr_srcW < cbcr_dstW){
1889 win->cbr_hor_scl_mode = SCALE_UP;
1890 }else if(cbcr_srcW > cbcr_dstW){
1891 win->cbr_hor_scl_mode = SCALE_DOWN;
1893 win->cbr_hor_scl_mode = SCALE_NONE;
1896 if(cbcr_srcH < cbcr_dstH){
1897 win->cbr_ver_scl_mode = SCALE_UP;
1898 }else if(cbcr_srcH > cbcr_dstH){
1899 win->cbr_ver_scl_mode = SCALE_DOWN;
1901 win->cbr_ver_scl_mode = SCALE_NONE;
1903 DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
1904 "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
1905 "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
1906 ,srcW,srcH,dstW,dstH,yrgb_srcW,yrgb_srcH,yrgb_dstW,
1907 yrgb_dstH,win->yrgb_hor_scl_mode,win->yrgb_ver_scl_mode,
1908 cbcr_srcW,cbcr_srcH,cbcr_dstW,cbcr_dstH,
1909 win->cbr_hor_scl_mode,win->cbr_ver_scl_mode);
1911 /*line buffer mode*/
1912 if ((win->area[0].format == YUV422) ||
1913 (win->area[0].format == YUV420) ||
1914 (win->area[0].format == YUV422_A) ||
1915 (win->area[0].format == YUV420_A)) {
1916 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
1917 if ((cbcr_dstW > 3840) || (cbcr_dstW == 0)) {
1918 pr_err("ERROR cbcr_dstW = %d\n",cbcr_dstW);
1919 } else if (cbcr_dstW > 2560) {
1920 win->win_lb_mode = LB_RGB_3840X2;
1921 } else if (cbcr_dstW > 1920) {
1922 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
1923 if(yrgb_dstW > 3840){
1924 pr_err("ERROR yrgb_dst_width exceeds 3840\n");
1925 }else if(yrgb_dstW > 2560){
1926 win->win_lb_mode = LB_RGB_3840X2;
1927 }else if(yrgb_dstW > 1920){
1928 win->win_lb_mode = LB_RGB_2560X4;
1930 pr_err("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n");
1933 } else if (cbcr_dstW > 1280) {
1934 win->win_lb_mode = LB_YUV_3840X5;
1936 win->win_lb_mode = LB_YUV_2560X8;
1938 } else { /*SCALE_UP or SCALE_NONE*/
1939 if ((cbcr_srcW > 3840) || (cbcr_srcW == 0)) {
1940 pr_err("ERROR cbcr_srcW = %d\n",cbcr_srcW);
1941 }else if(cbcr_srcW > 2560){
1942 win->win_lb_mode = LB_RGB_3840X2;
1943 }else if(cbcr_srcW > 1920){
1944 if(win->yrgb_hor_scl_mode == SCALE_DOWN){
1945 if(yrgb_dstW > 3840){
1946 pr_err("ERROR yrgb_dst_width exceeds 3840\n");
1947 }else if(yrgb_dstW > 2560){
1948 win->win_lb_mode = LB_RGB_3840X2;
1949 }else if(yrgb_dstW > 1920){
1950 win->win_lb_mode = LB_RGB_2560X4;
1952 pr_err("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n");
1955 }else if(cbcr_srcW > 1280){
1956 win->win_lb_mode = LB_YUV_3840X5;
1958 win->win_lb_mode = LB_YUV_2560X8;
1962 if(win->yrgb_hor_scl_mode == SCALE_DOWN){
1963 if ((yrgb_dstW > 3840) || (yrgb_dstW == 0)) {
1964 pr_err("ERROR yrgb_dstW = %d\n",yrgb_dstW);
1965 }else if(yrgb_dstW > 2560){
1966 win->win_lb_mode = LB_RGB_3840X2;
1967 }else if(yrgb_dstW > 1920){
1968 win->win_lb_mode = LB_RGB_2560X4;
1969 }else if(yrgb_dstW > 1280){
1970 win->win_lb_mode = LB_RGB_1920X5;
1972 win->win_lb_mode = LB_RGB_1280X8;
1974 }else{ /*SCALE_UP or SCALE_NONE*/
1975 if ((yrgb_srcW > 3840) || (yrgb_srcW == 0)) {
1976 pr_err("ERROR yrgb_srcW = %d\n",yrgb_srcW);
1977 }else if(yrgb_srcW > 2560){
1978 win->win_lb_mode = LB_RGB_3840X2;
1979 }else if(yrgb_srcW > 1920){
1980 win->win_lb_mode = LB_RGB_2560X4;
1981 }else if(yrgb_srcW > 1280){
1982 win->win_lb_mode = LB_RGB_1920X5;
1984 win->win_lb_mode = LB_RGB_1280X8;
1988 DBG(1,"win->win_lb_mode = %d;\n",win->win_lb_mode);
1990 /*vsd/vsu scale ALGORITHM*/
1991 win->yrgb_hsd_mode = SCALE_DOWN_BIL;/*not to specify*/
1992 win->cbr_hsd_mode = SCALE_DOWN_BIL;/*not to specify*/
1993 win->yrgb_vsd_mode = SCALE_DOWN_BIL;/*not to specify*/
1994 win->cbr_vsd_mode = SCALE_DOWN_BIL;/*not to specify*/
1995 switch(win->win_lb_mode){
2000 win->yrgb_vsu_mode = SCALE_UP_BIC;
2001 win->cbr_vsu_mode = SCALE_UP_BIC;
2004 if(win->yrgb_ver_scl_mode != SCALE_NONE) {
2005 pr_err("ERROR : not allow yrgb ver scale\n");
2007 if(win->cbr_ver_scl_mode != SCALE_NONE) {
2008 pr_err("ERROR : not allow cbcr ver scale\n");
2012 win->yrgb_vsu_mode = SCALE_UP_BIL;
2013 win->cbr_vsu_mode = SCALE_UP_BIL;
2016 printk(KERN_WARNING "%s:un supported win_lb_mode:%d\n",
2017 __func__,win->win_lb_mode);
2020 DBG(1,"yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2021 win->yrgb_hsd_mode,win->yrgb_vsd_mode,win->yrgb_vsu_mode,
2022 win->cbr_hsd_mode,win->cbr_vsd_mode,win->cbr_vsu_mode);
2026 /*(1.1)YRGB HOR SCALE FACTOR*/
2027 switch(win->yrgb_hor_scl_mode){
2029 yrgb_xscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2032 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2035 switch(win->yrgb_hsd_mode)
2037 case SCALE_DOWN_BIL:
2038 yrgb_xscl_factor = GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2040 case SCALE_DOWN_AVG:
2041 yrgb_xscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2044 printk(KERN_WARNING "%s:un supported yrgb_hsd_mode:%d\n",
2045 __func__,win->yrgb_hsd_mode);
2050 printk(KERN_WARNING "%s:un supported yrgb_hor_scl_mode:%d\n",
2051 __func__,win->yrgb_hor_scl_mode);
2053 } /*win->yrgb_hor_scl_mode*/
2055 /*(1.2)YRGB VER SCALE FACTOR*/
2056 switch(win->yrgb_ver_scl_mode)
2059 yrgb_yscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2062 switch(win->yrgb_vsu_mode)
2065 yrgb_yscl_factor = GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2069 pr_err("yrgb_srcH should be greater than 3 !!!\n");
2071 yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH, yrgb_dstH);
2074 printk(KERN_WARNING "%s:un supported yrgb_vsu_mode:%d\n",
2075 __func__,win->yrgb_vsu_mode);
2080 switch(win->yrgb_vsd_mode)
2082 case SCALE_DOWN_BIL:
2083 yrgb_vScaleDnMult = getHardWareVSkipLines(yrgb_srcH, yrgb_dstH);
2084 yrgb_yscl_factor = GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH, yrgb_vScaleDnMult);
2085 if(yrgb_vScaleDnMult == 4){
2086 yrgb_vsd_bil_gt4 = 1;
2087 yrgb_vsd_bil_gt2 = 0;
2088 }else if(yrgb_vScaleDnMult == 2){
2089 yrgb_vsd_bil_gt4 = 0;
2090 yrgb_vsd_bil_gt2 = 1;
2092 yrgb_vsd_bil_gt4 = 0;
2093 yrgb_vsd_bil_gt2 = 0;
2096 case SCALE_DOWN_AVG:
2097 yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH, yrgb_dstH);
2100 printk(KERN_WARNING "%s:un supported yrgb_vsd_mode:%d\n",
2101 __func__,win->yrgb_vsd_mode);
2103 } /*win->yrgb_vsd_mode*/
2106 printk(KERN_WARNING "%s:un supported yrgb_ver_scl_mode:%d\n",
2107 __func__,win->yrgb_ver_scl_mode);
2110 win->scale_yrgb_x = yrgb_xscl_factor;
2111 win->scale_yrgb_y = yrgb_yscl_factor;
2112 win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2113 win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2114 DBG(1,"yrgb:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",yrgb_xscl_factor,
2115 yrgb_yscl_factor,yrgb_vsd_bil_gt4,yrgb_vsd_bil_gt2);
2117 /*(2.1)CBCR HOR SCALE FACTOR*/
2118 switch(win->cbr_hor_scl_mode)
2121 cbcr_xscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2124 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2127 switch(win->cbr_hsd_mode)
2129 case SCALE_DOWN_BIL:
2130 cbcr_xscl_factor = GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2132 case SCALE_DOWN_AVG:
2133 cbcr_xscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2136 printk(KERN_WARNING "%s:un supported cbr_hsd_mode:%d\n",
2137 __func__,win->cbr_hsd_mode);
2142 printk(KERN_WARNING "%s:un supported cbr_hor_scl_mode:%d\n",
2143 __func__,win->cbr_hor_scl_mode);
2145 } /*win->cbr_hor_scl_mode*/
2147 /*(2.2)CBCR VER SCALE FACTOR*/
2148 switch(win->cbr_ver_scl_mode)
2151 cbcr_yscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2154 switch(win->cbr_vsu_mode)
2157 cbcr_yscl_factor = GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2161 pr_err("cbcr_srcH should be greater than 3 !!!\n");
2163 cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH, cbcr_dstH);
2166 printk(KERN_WARNING "%s:un supported cbr_vsu_mode:%d\n",
2167 __func__,win->cbr_vsu_mode);
2172 switch(win->cbr_vsd_mode)
2174 case SCALE_DOWN_BIL:
2175 cbcr_vScaleDnMult = getHardWareVSkipLines(cbcr_srcH, cbcr_dstH);
2176 cbcr_yscl_factor = GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH, cbcr_vScaleDnMult);
2177 if(cbcr_vScaleDnMult == 4){
2178 cbcr_vsd_bil_gt4 = 1;
2179 cbcr_vsd_bil_gt2 = 0;
2180 }else if(cbcr_vScaleDnMult == 2){
2181 cbcr_vsd_bil_gt4 = 0;
2182 cbcr_vsd_bil_gt2 = 1;
2184 cbcr_vsd_bil_gt4 = 0;
2185 cbcr_vsd_bil_gt2 = 0;
2188 case SCALE_DOWN_AVG:
2189 cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH, cbcr_dstH);
2192 printk(KERN_WARNING "%s:un supported cbr_vsd_mode:%d\n",
2193 __func__,win->cbr_vsd_mode);
2198 printk(KERN_WARNING "%s:un supported cbr_ver_scl_mode:%d\n",
2199 __func__,win->cbr_ver_scl_mode);
2202 win->scale_cbcr_x = cbcr_xscl_factor;
2203 win->scale_cbcr_y = cbcr_yscl_factor;
2204 win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2205 win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2207 DBG(1,"cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",cbcr_xscl_factor,
2208 cbcr_yscl_factor,cbcr_vsd_bil_gt4,cbcr_vsd_bil_gt2);
2214 static int win0_set_par(struct lcdc_device *lcdc_dev,
2215 struct rk_screen *screen, struct rk_lcdc_win *win)
2217 u32 xact,yact,xvir, yvir,xpos, ypos;
2218 u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2219 char fmt[9] = "NULL";
2221 xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len;
2222 ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len;
2224 spin_lock(&lcdc_dev->reg_lock);
2225 if(likely(lcdc_dev->clk_on)){
2226 rk3288_lcdc_cal_scl_fac(win);/*fac,lb,gt2,gt4*/
2227 switch (win->area[0].format) {
2285 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
2289 win->area[0].fmt_cfg = fmt_cfg;
2290 win->area[0].swap_rb = swap_rb;
2291 win->area[0].dsp_stx = xpos;
2292 win->area[0].dsp_sty = ypos;
2293 win->area[0].swap_uv = swap_uv;
2294 xact = win->area[0].xact;
2295 yact = win->area[0].yact;
2296 xvir = win->area[0].xvir;
2297 yvir = win->area[0].yvir;
2299 rk3288_win_0_1_reg_update(&lcdc_dev->driver,0);
2300 spin_unlock(&lcdc_dev->reg_lock);
2302 DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
2303 ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id,
2304 __func__, get_format_string(win->area[0].format, fmt), xact,
2305 yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos);
2310 static int win1_set_par(struct lcdc_device *lcdc_dev,
2311 struct rk_screen *screen, struct rk_lcdc_win *win)
2313 u32 xact, yact, xvir, yvir, xpos, ypos;
2314 u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2315 char fmt[9] = "NULL";
2317 xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len;
2318 ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len;
2320 spin_lock(&lcdc_dev->reg_lock);
2321 if (likely(lcdc_dev->clk_on)) {
2322 rk3288_lcdc_cal_scl_fac(win);/*fac,lb,gt2,gt4*/
2323 switch (win->area[0].format) {
2382 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
2386 win->area[0].fmt_cfg = fmt_cfg;
2387 win->area[0].swap_rb = swap_rb;
2388 win->area[0].dsp_stx = xpos;
2389 win->area[0].dsp_sty = ypos;
2390 win->area[0].swap_uv = swap_uv;
2391 xact = win->area[0].xact;
2392 yact = win->area[0].yact;
2393 xvir = win->area[0].xvir;
2394 yvir = win->area[0].yvir;
2396 rk3288_win_0_1_reg_update(&lcdc_dev->driver,1);
2397 spin_unlock(&lcdc_dev->reg_lock);
2399 DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
2400 ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id,
2401 __func__, get_format_string(win->area[0].format, fmt), xact,
2402 yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos);
2407 static int win2_set_par(struct lcdc_device *lcdc_dev,
2408 struct rk_screen *screen, struct rk_lcdc_win *win)
2411 u8 fmt_cfg, swap_rb;
2413 spin_lock(&lcdc_dev->reg_lock);
2414 if (likely(lcdc_dev->clk_on)) {
2415 for (i = 0; i < win->area_num; i++) {
2416 switch (win->area[i].format) {
2435 dev_err(lcdc_dev->driver.dev,
2436 "%s:un supported format!\n",
2440 win->area[i].fmt_cfg = fmt_cfg;
2441 win->area[i].swap_rb = swap_rb;
2442 win->area[i].dsp_stx = win->area[i].xpos +
2443 screen->mode.left_margin +
2444 screen->mode.hsync_len;
2445 if (screen->y_mirror == 1) {
2446 win->area[i].dsp_sty = screen->mode.yres -
2448 win->area[i].ysize +
2449 screen->mode.upper_margin +
2450 screen->mode.vsync_len;
2452 win->area[i].dsp_sty = win->area[i].ypos +
2453 screen->mode.upper_margin +
2454 screen->mode.vsync_len;
2456 if ((win->area[i].xact != win->area[i].xsize) ||
2457 (win->area[i].yact != win->area[i].ysize)) {
2458 pr_err("win[%d]->area[%d],not support scale\n",
2460 pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
2461 win->area[i].xact,win->area[i].yact,
2462 win->area[i].xsize,win->area[i].ysize);
2463 win->area[i].xsize = win->area[i].xact;
2464 win->area[i].ysize = win->area[i].yact;
2468 rk3288_win_2_3_reg_update(&lcdc_dev->driver,2);
2469 spin_unlock(&lcdc_dev->reg_lock);
2473 static int win3_set_par(struct lcdc_device *lcdc_dev,
2474 struct rk_screen *screen, struct rk_lcdc_win *win)
2478 u8 fmt_cfg, swap_rb;
2480 spin_lock(&lcdc_dev->reg_lock);
2481 if (likely(lcdc_dev->clk_on)) {
2482 for (i = 0; i < win->area_num; i++) {
2483 switch (win->area[i].format) {
2502 dev_err(lcdc_dev->driver.dev,
2503 "%s:un supported format!\n",
2507 win->area[i].fmt_cfg = fmt_cfg;
2508 win->area[i].swap_rb = swap_rb;
2509 win->area[i].dsp_stx = win->area[i].xpos +
2510 screen->mode.left_margin +
2511 screen->mode.hsync_len;
2512 if (screen->y_mirror == 1) {
2513 win->area[i].dsp_sty = screen->mode.yres -
2515 win->area[i].ysize +
2516 screen->mode.upper_margin +
2517 screen->mode.vsync_len;
2519 win->area[i].dsp_sty = win->area[i].ypos +
2520 screen->mode.upper_margin +
2521 screen->mode.vsync_len;
2523 if ((win->area[i].xact != win->area[i].xsize) ||
2524 (win->area[i].yact != win->area[i].ysize)) {
2525 pr_err("win[%d]->area[%d],not support scale\n",
2527 pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
2528 win->area[i].xact, win->area[i].yact,
2529 win->area[i].xsize, win->area[i].ysize);
2530 win->area[i].xsize = win->area[i].xact;
2531 win->area[i].ysize = win->area[i].yact;
2535 rk3288_win_2_3_reg_update(&lcdc_dev->driver,3);
2536 spin_unlock(&lcdc_dev->reg_lock);
2540 static int rk3288_lcdc_set_par(struct rk_lcdc_driver *dev_drv,int win_id)
2542 struct lcdc_device *lcdc_dev =
2543 container_of(dev_drv, struct lcdc_device, driver);
2544 struct rk_lcdc_win *win = NULL;
2545 struct rk_screen *screen = dev_drv->cur_screen;
2546 win = dev_drv->win[win_id];
2551 win0_set_par(lcdc_dev, screen, win);
2554 win1_set_par(lcdc_dev, screen, win);
2557 win2_set_par(lcdc_dev, screen, win);
2560 win3_set_par(lcdc_dev, screen, win);
2563 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2569 static int rk3288_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2570 unsigned long arg, int win_id)
2572 struct lcdc_device *lcdc_dev = container_of(dev_drv,
2577 void __user *argp = (void __user *)arg;
2578 struct color_key_cfg clr_key_cfg;
2581 case RK_FBIOGET_PANEL_SIZE:
2582 panel_size[0] = lcdc_dev->screen->mode.xres;
2583 panel_size[1] = lcdc_dev->screen->mode.yres;
2584 if (copy_to_user(argp, panel_size, 8))
2587 case RK_FBIOPUT_COLOR_KEY_CFG:
2588 if (copy_from_user(&clr_key_cfg, argp,
2589 sizeof(struct color_key_cfg)))
2591 rk3288_lcdc_clr_key_cfg(dev_drv);
2592 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
2593 clr_key_cfg.win0_color_key_cfg);
2594 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
2595 clr_key_cfg.win1_color_key_cfg);
2604 static int rk3288_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
2607 struct lcdc_device *lcdc_dev =
2608 container_of(dev_drv, struct lcdc_device, driver);
2609 if (dev_drv->suspend_flag)
2612 dev_drv->suspend_flag = 1;
2613 flush_kthread_worker(&dev_drv->update_regs_worker);
2615 for (reg = MMU_DTE_ADDR; reg <= MMU_AUTO_GATING; reg +=4)
2616 lcdc_readl(lcdc_dev, reg);
2617 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
2618 dev_drv->trsm_ops->disable();
2620 spin_lock(&lcdc_dev->reg_lock);
2621 if (likely(lcdc_dev->clk_on)) {
2622 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2624 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_FS_INTR_CLR | m_LINE_FLAG_INTR_CLR,
2625 v_FS_INTR_CLR(1) | v_LINE_FLAG_INTR_CLR(1));
2626 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2628 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
2630 lcdc_cfg_done(lcdc_dev);
2632 if (dev_drv->iommu_enabled) {
2633 if (dev_drv->mmu_dev)
2634 rockchip_iovmm_deactivate(dev_drv->dev);
2637 spin_unlock(&lcdc_dev->reg_lock);
2639 spin_unlock(&lcdc_dev->reg_lock);
2642 rk3288_lcdc_clk_disable(lcdc_dev);
2643 rk_disp_pwr_disable(dev_drv);
2647 static int rk3288_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
2649 struct lcdc_device *lcdc_dev =
2650 container_of(dev_drv, struct lcdc_device, driver);
2652 if (!dev_drv->suspend_flag)
2654 rk_disp_pwr_enable(dev_drv);
2655 dev_drv->suspend_flag = 0;
2657 if (lcdc_dev->atv_layer_cnt) {
2658 rk3288_lcdc_clk_enable(lcdc_dev);
2659 rk3288_lcdc_reg_restore(lcdc_dev);
2661 spin_lock(&lcdc_dev->reg_lock);
2662 rk3288_lcdc_set_lut(dev_drv);
2664 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2666 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
2668 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2670 lcdc_cfg_done(lcdc_dev);
2672 if (dev_drv->iommu_enabled) {
2673 if (dev_drv->mmu_dev)
2674 rockchip_iovmm_activate(dev_drv->dev);
2677 spin_unlock(&lcdc_dev->reg_lock);
2680 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2681 dev_drv->trsm_ops->enable();
2686 static int rk3288_lcdc_blank(struct rk_lcdc_driver *dev_drv,
2687 int win_id, int blank_mode)
2689 switch (blank_mode) {
2690 case FB_BLANK_UNBLANK:
2691 rk3288_lcdc_early_resume(dev_drv);
2693 case FB_BLANK_NORMAL:
2694 rk3288_lcdc_early_suspend(dev_drv);
2697 rk3288_lcdc_early_suspend(dev_drv);
2701 dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
2706 static int rk3288_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv,
2707 int win_id, int area_id)
2709 struct lcdc_device *lcdc_dev =
2710 container_of(dev_drv, struct lcdc_device, driver);
2712 u32 area_status = 0;
2716 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
2717 area_status = win_ctrl & m_WIN0_EN;
2720 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
2721 area_status = win_ctrl & m_WIN1_EN;
2724 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
2726 area_status = win_ctrl & m_WIN2_MST0_EN;
2728 area_status = win_ctrl & m_WIN2_MST1_EN;
2730 area_status = win_ctrl & m_WIN2_MST2_EN;
2732 area_status = win_ctrl & m_WIN2_MST3_EN;
2735 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
2737 area_status = win_ctrl & m_WIN3_MST0_EN;
2739 area_status = win_ctrl & m_WIN3_MST1_EN;
2741 area_status = win_ctrl & m_WIN3_MST2_EN;
2743 area_status = win_ctrl & m_WIN3_MST3_EN;
2746 win_ctrl = lcdc_readl(lcdc_dev, HWC_CTRL0);
2747 area_status = win_ctrl & m_HWC_EN;
2750 pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n",__func__,win_id,area_id);
2756 static int rk3288_lcdc_get_area_num(struct rk_lcdc_driver *dev_drv,
2757 unsigned int *area_support)
2759 area_support[0] = 1;
2760 area_support[1] = 1;
2761 area_support[2] = 4;
2762 area_support[3] = 4;
2767 /*overlay will be do at regupdate*/
2768 static int rk3288_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
2771 struct lcdc_device *lcdc_dev =
2772 container_of(dev_drv, struct lcdc_device, driver);
2773 struct rk_lcdc_win *win = NULL;
2775 unsigned int mask, val;
2777 int layer0_sel,layer1_sel,layer2_sel,layer3_sel;
2780 win = dev_drv->win[i];
2781 if(win->state == 1){
2786 win = dev_drv->win[i];
2788 win->z_order = z_order_num++;
2789 switch(win->z_order){
2791 layer0_sel = win->id;
2794 layer1_sel = win->id;
2797 layer2_sel = win->id;
2800 layer3_sel = win->id;
2807 layer0_sel = swap %10;;
2808 layer1_sel = swap /10 % 10;
2809 layer2_sel = swap / 100 %10;
2810 layer3_sel = swap / 1000;
2813 spin_lock(&lcdc_dev->reg_lock);
2814 if(lcdc_dev->clk_on){
2816 mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
2817 m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
2818 val = v_DSP_LAYER0_SEL(layer0_sel) |
2819 v_DSP_LAYER1_SEL(layer1_sel) |
2820 v_DSP_LAYER2_SEL(layer2_sel) |
2821 v_DSP_LAYER3_SEL(layer3_sel);
2822 lcdc_msk_reg(lcdc_dev,DSP_CTRL1,mask,val);
2824 layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER0_SEL);
2825 layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER1_SEL);
2826 layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER2_SEL);
2827 layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER3_SEL);
2828 ovl = layer3_sel*1000 + layer2_sel*100 + layer1_sel *10 + layer0_sel;
2833 spin_unlock(&lcdc_dev->reg_lock);
2838 static ssize_t rk3288_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
2839 char *buf, int win_id)
2841 struct lcdc_device *lcdc_dev = container_of(dev_drv,
2845 struct rk_screen *screen = dev_drv->cur_screen;
2846 u16 hsync_len = screen->mode.hsync_len;
2847 u16 left_margin = screen->mode.left_margin;
2848 u16 vsync_len = screen->mode.vsync_len;
2849 u16 upper_margin = screen->mode.upper_margin;
2850 u32 h_pw_bp = hsync_len + left_margin;
2851 u32 v_pw_bp = vsync_len + upper_margin;
2853 char format_w0[9] = "NULL";
2854 char format_w1[9] = "NULL";
2855 char format_w2[9] = "NULL";
2856 char format_w3[9] = "NULL";
2857 u32 win_ctrl,zorder,vir_info,act_info,dsp_info,dsp_st,y_factor,uv_factor;
2858 u8 layer0_sel,layer1_sel,layer2_sel,layer3_sel;
2859 u8 w0_state,w1_state,w2_state,w3_state;
2860 u8 w2_0_state,w2_1_state,w2_2_state,w2_3_state;
2861 u8 w3_0_state,w3_1_state,w3_2_state,w3_3_state;
2863 u32 w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y,w0_dsp_x,w0_dsp_y,w0_st_x=h_pw_bp,w0_st_y=v_pw_bp;
2864 u32 w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y,w1_dsp_x,w1_dsp_y,w1_st_x=h_pw_bp,w1_st_y=v_pw_bp;
2865 u32 w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac,w0_uv_v_fac;
2866 u32 w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac,w1_uv_v_fac;
2868 u32 w2_0_vir_y,w2_1_vir_y,w2_2_vir_y,w2_3_vir_y;
2869 u32 w2_0_dsp_x,w2_1_dsp_x,w2_2_dsp_x,w2_3_dsp_x;
2870 u32 w2_0_dsp_y,w2_1_dsp_y,w2_2_dsp_y,w2_3_dsp_y;
2871 u32 w2_0_st_x=h_pw_bp,w2_1_st_x=h_pw_bp,w2_2_st_x=h_pw_bp,w2_3_st_x=h_pw_bp;
2872 u32 w2_0_st_y=v_pw_bp,w2_1_st_y=v_pw_bp,w2_2_st_y=v_pw_bp,w2_3_st_y=v_pw_bp;
2874 u32 w3_0_vir_y,w3_1_vir_y,w3_2_vir_y,w3_3_vir_y;
2875 u32 w3_0_dsp_x,w3_1_dsp_x,w3_2_dsp_x,w3_3_dsp_x;
2876 u32 w3_0_dsp_y,w3_1_dsp_y,w3_2_dsp_y,w3_3_dsp_y;
2877 u32 w3_0_st_x=h_pw_bp,w3_1_st_x=h_pw_bp,w3_2_st_x=h_pw_bp,w3_3_st_x=h_pw_bp;
2878 u32 w3_0_st_y=v_pw_bp,w3_1_st_y=v_pw_bp,w3_2_st_y=v_pw_bp,w3_3_st_y=v_pw_bp;
2881 dclk_freq = screen->mode.pixclock;
2882 /*rk3288_lcdc_reg_dump(dev_drv);*/
2884 spin_lock(&lcdc_dev->reg_lock);
2885 if (lcdc_dev->clk_on) {
2886 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
2887 layer0_sel = (zorder & m_DSP_LAYER0_SEL)>>8;
2888 layer1_sel = (zorder & m_DSP_LAYER1_SEL)>>10;
2889 layer2_sel = (zorder & m_DSP_LAYER2_SEL)>>12;
2890 layer3_sel = (zorder & m_DSP_LAYER3_SEL)>>14;
2892 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
2893 w0_state = win_ctrl & m_WIN0_EN;
2894 fmt_id = (win_ctrl & m_WIN0_DATA_FMT)>>1;
2897 strcpy(format_w0, "ARGB888");
2900 strcpy(format_w0, "RGB888");
2903 strcpy(format_w0, "RGB565");
2906 strcpy(format_w0, "YCbCr420");
2909 strcpy(format_w0, "YCbCr422");
2912 strcpy(format_w0, "YCbCr444");
2915 strcpy(format_w0, "invalid\n");
2918 vir_info = lcdc_readl(lcdc_dev,WIN0_VIR);
2919 act_info = lcdc_readl(lcdc_dev,WIN0_ACT_INFO);
2920 dsp_info = lcdc_readl(lcdc_dev,WIN0_DSP_INFO);
2921 dsp_st = lcdc_readl(lcdc_dev,WIN0_DSP_ST);
2922 y_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_YRGB);
2923 uv_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_CBR);
2924 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
2925 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV)>>16;
2926 w0_act_x = (act_info & m_WIN0_ACT_WIDTH)+1;
2927 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT)>>16)+1;
2928 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH)+1;
2929 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT)>>16)+1;
2931 w0_st_x = dsp_st & m_WIN0_DSP_XST;
2932 w0_st_y = (dsp_st & m_WIN0_DSP_YST)>>16;
2934 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
2935 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB)>>16;
2936 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
2937 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR)>>16;
2940 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
2941 w1_state = win_ctrl & m_WIN1_EN;
2942 fmt_id = (win_ctrl & m_WIN1_DATA_FMT)>>1;
2945 strcpy(format_w1, "ARGB888");
2948 strcpy(format_w1, "RGB888");
2951 strcpy(format_w1, "RGB565");
2954 strcpy(format_w1, "YCbCr420");
2957 strcpy(format_w1, "YCbCr422");
2960 strcpy(format_w1, "YCbCr444");
2963 strcpy(format_w1, "invalid\n");
2966 vir_info = lcdc_readl(lcdc_dev,WIN1_VIR);
2967 act_info = lcdc_readl(lcdc_dev,WIN1_ACT_INFO);
2968 dsp_info = lcdc_readl(lcdc_dev,WIN1_DSP_INFO);
2969 dsp_st = lcdc_readl(lcdc_dev,WIN1_DSP_ST);
2970 y_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_YRGB);
2971 uv_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_CBR);
2972 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
2973 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV)>>16;
2974 w1_act_x = (act_info & m_WIN1_ACT_WIDTH)+1;
2975 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT)>>16)+1;
2976 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH)+1;
2977 w1_dsp_y =((dsp_info & m_WIN1_DSP_HEIGHT)>>16)+1;
2979 w1_st_x = dsp_st & m_WIN1_DSP_XST;
2980 w1_st_y = (dsp_st & m_WIN1_DSP_YST)>>16;
2982 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
2983 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB)>>16;
2984 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
2985 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR)>>16;
2987 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
2988 w2_state = win_ctrl & m_WIN2_EN;
2989 w2_0_state = (win_ctrl & m_WIN2_MST0_EN)>>4;
2990 w2_1_state = (win_ctrl & m_WIN2_MST1_EN)>>5;
2991 w2_2_state = (win_ctrl & m_WIN2_MST2_EN)>>6;
2992 w2_3_state = (win_ctrl & m_WIN2_MST3_EN)>>7;
2993 vir_info = lcdc_readl(lcdc_dev,WIN2_VIR0_1);
2994 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
2995 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1)>>16;
2996 vir_info = lcdc_readl(lcdc_dev,WIN2_VIR2_3);
2997 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
2998 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3)>>16;
2999 fmt_id = (win_ctrl & m_WIN2_DATA_FMT)>>1;
3002 strcpy(format_w2, "ARGB888");
3005 strcpy(format_w2, "RGB888");
3008 strcpy(format_w2, "RGB565");
3011 strcpy(format_w2,"8bpp");
3014 strcpy(format_w2,"4bpp");
3017 strcpy(format_w2,"2bpp");
3020 strcpy(format_w2,"1bpp");
3023 strcpy(format_w2, "invalid\n");
3026 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO0);
3027 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST0);
3028 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0)+1;
3029 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0)>>16)+1;
3031 w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3032 w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0)>>16;
3034 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO1);
3035 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST1);
3036 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1)+1;
3037 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1)>>16)+1;
3039 w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3040 w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1)>>16;
3042 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO2);
3043 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST2);
3044 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2)+1;
3045 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2)>>16)+1;
3047 w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3048 w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2)>>16;
3050 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO3);
3051 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST3);
3052 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3)+1;
3053 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3)>>16)+1;
3055 w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3056 w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3)>>16;
3060 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3061 w3_state = win_ctrl & m_WIN3_EN;
3062 w3_0_state = (win_ctrl & m_WIN3_MST0_EN)>>4;
3063 w3_1_state = (win_ctrl & m_WIN3_MST1_EN)>>5;
3064 w3_2_state = (win_ctrl & m_WIN3_MST2_EN)>>6;
3065 w3_3_state = (win_ctrl & m_WIN3_MST3_EN)>>7;
3066 vir_info = lcdc_readl(lcdc_dev,WIN3_VIR0_1);
3067 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3068 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1)>>16;
3069 vir_info = lcdc_readl(lcdc_dev,WIN3_VIR2_3);
3070 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3071 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3)>>16;
3072 fmt_id = (win_ctrl & m_WIN3_DATA_FMT)>>1;
3075 strcpy(format_w3, "ARGB888");
3078 strcpy(format_w3, "RGB888");
3081 strcpy(format_w3, "RGB565");
3084 strcpy(format_w3,"8bpp");
3087 strcpy(format_w3,"4bpp");
3090 strcpy(format_w3,"2bpp");
3093 strcpy(format_w3,"1bpp");
3096 strcpy(format_w3, "invalid");
3099 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO0);
3100 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST0);
3101 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0)+1;
3102 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0)>>16)+1;
3104 w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3105 w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0)>>16;
3108 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO1);
3109 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST1);
3110 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1)+1;
3111 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1)>>16)+1;
3113 w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3114 w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1)>>16;
3117 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO2);
3118 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST2);
3119 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2)+1;
3120 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2)>>16)+1;
3122 w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3123 w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2)>>16;
3126 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO3);
3127 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST3);
3128 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3)+1;
3129 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3)>>16)+1;
3131 w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3132 w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3)>>16;
3136 spin_unlock(&lcdc_dev->reg_lock);
3139 spin_unlock(&lcdc_dev->reg_lock);
3140 return snprintf(buf, PAGE_SIZE,
3142 " layer3_sel_win[%d]\n"
3143 " layer2_sel_win[%d]\n"
3144 " layer1_sel_win[%d]\n"
3145 " layer0_sel_win[%d]\n"
3250 layer3_sel,layer2_sel,layer1_sel,layer0_sel,
3251 w0_state,format_w0,w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y,
3252 w0_dsp_x,w0_dsp_y,w0_st_x-h_pw_bp,w0_st_y-v_pw_bp,w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac,
3253 w0_uv_v_fac,lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3254 lcdc_readl(lcdc_dev, WIN0_CBR_MST),
3256 w1_state,format_w1,w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y,
3257 w1_dsp_x,w1_dsp_y,w1_st_x-h_pw_bp,w1_st_y-v_pw_bp,w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac,
3258 w1_uv_v_fac,lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3259 lcdc_readl(lcdc_dev, WIN1_CBR_MST),
3262 w2_0_state,w2_0_vir_y,w2_0_dsp_x,w2_0_dsp_y,
3263 w2_0_st_x-h_pw_bp,w2_0_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST0),
3265 w2_1_state,w2_1_vir_y,w2_1_dsp_x,w2_1_dsp_y,
3266 w2_1_st_x-h_pw_bp,w2_1_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST1),
3268 w2_2_state,w2_2_vir_y,w2_2_dsp_x,w2_2_dsp_y,
3269 w2_2_st_x-h_pw_bp,w2_2_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST2),
3271 w2_3_state,w2_3_vir_y,w2_3_dsp_x,w2_3_dsp_y,
3272 w2_3_st_x-h_pw_bp,w2_3_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST3),
3275 w3_0_state,w3_0_vir_y,w3_0_dsp_x,w3_0_dsp_y,
3276 w3_0_st_x-h_pw_bp,w3_0_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST0),
3278 w3_1_state,w3_1_vir_y,w3_1_dsp_x,w3_1_dsp_y,
3279 w3_1_st_x-h_pw_bp,w3_1_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST1),
3281 w3_2_state,w3_2_vir_y,w3_2_dsp_x,w3_2_dsp_y,
3282 w3_2_st_x-h_pw_bp,w3_2_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST2),
3284 w3_3_state,w3_3_vir_y,w3_3_dsp_x,w3_3_dsp_y,
3285 w3_3_st_x-h_pw_bp,w3_3_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST3)
3290 static int rk3288_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3293 struct lcdc_device *lcdc_dev =
3294 container_of(dev_drv, struct lcdc_device, driver);
3295 struct rk_screen *screen = dev_drv->cur_screen;
3300 u32 x_total, y_total;
3303 dev_info(dev_drv->dev, "unsupport set fps=0\n");
3306 ft = div_u64(1000000000000llu, fps);
3308 screen->mode.upper_margin + screen->mode.lower_margin +
3309 screen->mode.yres + screen->mode.vsync_len;
3311 screen->mode.left_margin + screen->mode.right_margin +
3312 screen->mode.xres + screen->mode.hsync_len;
3313 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3314 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3315 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3318 pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3319 dev_drv->pixclock = lcdc_dev->pixclock = pixclock;
3320 fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3321 screen->ft = 1000 / fps; /*one frame time in ms */
3324 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3325 clk_get_rate(lcdc_dev->dclk), fps);
3330 static int rk3288_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3332 mutex_lock(&dev_drv->fb_win_id_mutex);
3333 if (order == FB_DEFAULT_ORDER)
3334 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3;
3335 dev_drv->fb3_win_id = order / 1000;
3336 dev_drv->fb2_win_id = (order / 100) % 10;
3337 dev_drv->fb1_win_id = (order / 10) % 10;
3338 dev_drv->fb0_win_id = order % 10;
3339 mutex_unlock(&dev_drv->fb_win_id_mutex);
3344 static int rk3288_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3348 mutex_lock(&dev_drv->fb_win_id_mutex);
3349 if (!strcmp(id, "fb0") || !strcmp(id, "fb4"))
3350 win_id = dev_drv->fb0_win_id;
3351 else if (!strcmp(id, "fb1") || !strcmp(id, "fb5"))
3352 win_id = dev_drv->fb1_win_id;
3353 else if (!strcmp(id, "fb2") || !strcmp(id, "fb6"))
3354 win_id = dev_drv->fb2_win_id;
3355 else if (!strcmp(id, "fb3") || !strcmp(id, "fb7"))
3356 win_id = dev_drv->fb3_win_id;
3357 mutex_unlock(&dev_drv->fb_win_id_mutex);
3362 static int rk3288_set_dsp_lut(struct rk_lcdc_driver *dev_drv, int *lut)
3369 struct lcdc_device *lcdc_dev =
3370 container_of(dev_drv, struct lcdc_device, driver);
3371 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
3372 lcdc_cfg_done(lcdc_dev);
3374 if (dev_drv->cur_screen->dsp_lut) {
3375 for (i = 0; i < 256; i++) {
3376 v = dev_drv->cur_screen->dsp_lut[i] = lut[i];
3377 c = lcdc_dev->dsp_lut_addr_base + (i << 2);
3378 b = (v & 0xff) << 2;
3379 g = (v & 0xff00) << 4;
3380 r = (v & 0xff0000) << 6;
3382 for (j = 0; j < 4; j++) {
3383 writel_relaxed(v, c);
3384 v += (1 + (1 << 10) + (1 << 20)) ;
3389 dev_err(dev_drv->dev, "no buffer to backup lut data!\n");
3394 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
3395 lcdc_cfg_done(lcdc_dev);
3396 }while(!lcdc_read_bit(lcdc_dev,DSP_CTRL1,m_DSP_LUT_EN));
3400 static int rk3288_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3402 struct lcdc_device *lcdc_dev =
3403 container_of(dev_drv, struct lcdc_device, driver);
3405 unsigned int mask, val;
3406 struct rk_lcdc_win *win = NULL;
3407 struct fb_info *fb0 = rk_get_fb(0);
3409 spin_lock(&lcdc_dev->reg_lock);
3410 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3411 v_STANDBY_EN(lcdc_dev->standby));
3413 win = dev_drv->win[i];
3414 if ((win->state == 0)&&(win->last_state == 1)) {
3417 if (dev_drv->version == VOP_FULL_RK3288_V1_0)
3418 lcdc_writel(lcdc_dev, WIN0_CTRL1, 0x0);
3421 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask,val);
3424 if (dev_drv->version == VOP_FULL_RK3288_V1_0)
3425 lcdc_writel(lcdc_dev, WIN1_CTRL1, 0x0);
3428 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask,val);
3431 mask = m_WIN2_EN | m_WIN2_MST0_EN | m_WIN2_MST1_EN |
3432 m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3433 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) | v_WIN2_MST1_EN(0) |
3434 v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3435 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask,val);
3436 lcdc_writel(lcdc_dev,WIN2_DSP_INFO0,0);
3437 lcdc_writel(lcdc_dev,WIN2_DSP_INFO1,0);
3438 lcdc_writel(lcdc_dev,WIN2_DSP_INFO2,0);
3439 lcdc_writel(lcdc_dev,WIN2_DSP_INFO3,0);
3440 lcdc_writel(lcdc_dev,WIN2_MST0, fb0->fix.smem_start);
3441 lcdc_writel(lcdc_dev,WIN2_MST1, fb0->fix.smem_start);
3442 lcdc_writel(lcdc_dev,WIN2_MST2, fb0->fix.smem_start);
3443 lcdc_writel(lcdc_dev,WIN2_MST3, fb0->fix.smem_start);
3446 mask = m_WIN3_EN | m_WIN3_MST0_EN | m_WIN3_MST1_EN |
3447 m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3448 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) | v_WIN3_MST1_EN(0) |
3449 v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3450 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask,val);
3451 lcdc_writel(lcdc_dev,WIN3_DSP_INFO0,0);
3452 lcdc_writel(lcdc_dev,WIN3_DSP_INFO1,0);
3453 lcdc_writel(lcdc_dev,WIN3_DSP_INFO2,0);
3454 lcdc_writel(lcdc_dev,WIN3_DSP_INFO3,0);
3455 lcdc_writel(lcdc_dev,WIN3_MST0, fb0->fix.smem_start);
3456 lcdc_writel(lcdc_dev,WIN3_MST1, fb0->fix.smem_start);
3457 lcdc_writel(lcdc_dev,WIN3_MST2, fb0->fix.smem_start);
3458 lcdc_writel(lcdc_dev,WIN3_MST3, fb0->fix.smem_start);
3464 win->last_state = win->state;
3466 lcdc_cfg_done(lcdc_dev);
3467 spin_unlock(&lcdc_dev->reg_lock);
3472 static int rk3288_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3474 struct lcdc_device *lcdc_dev =
3475 container_of(dev_drv, struct lcdc_device, driver);
3476 spin_lock(&lcdc_dev->reg_lock);
3477 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3478 v_DIRECT_PATH_EN(open));
3479 lcdc_cfg_done(lcdc_dev);
3480 spin_unlock(&lcdc_dev->reg_lock);
3484 static int rk3288_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3486 struct lcdc_device *lcdc_dev = container_of(dev_drv,
3487 struct lcdc_device, driver);
3488 spin_lock(&lcdc_dev->reg_lock);
3489 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3490 v_DIRECT_PATCH_SEL(win_id));
3491 lcdc_cfg_done(lcdc_dev);
3492 spin_unlock(&lcdc_dev->reg_lock);
3497 static int rk3288_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3499 struct lcdc_device *lcdc_dev =
3500 container_of(dev_drv, struct lcdc_device, driver);
3502 spin_lock(&lcdc_dev->reg_lock);
3503 ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3504 spin_unlock(&lcdc_dev->reg_lock);
3507 static int rk3288_lcdc_set_irq_to_cpu(struct rk_lcdc_driver * dev_drv,int enable)
3509 struct lcdc_device *lcdc_dev =
3510 container_of(dev_drv,struct lcdc_device,driver);
3512 enable_irq(lcdc_dev->irq);
3514 disable_irq(lcdc_dev->irq);
3518 int rk3288_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3520 struct lcdc_device *lcdc_dev =
3521 container_of(dev_drv, struct lcdc_device, driver);
3525 if (lcdc_dev->clk_on &&(!dev_drv->suspend_flag)){
3526 int_reg = lcdc_readl(lcdc_dev, INTR_CTRL0);
3527 if (int_reg & m_LINE_FLAG_INTR_STS) {
3528 lcdc_dev->driver.frame_time.last_framedone_t =
3529 lcdc_dev->driver.frame_time.framedone_t;
3530 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3531 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR,
3532 v_LINE_FLAG_INTR_CLR(1));
3533 ret = RK_LF_STATUS_FC;
3535 ret = RK_LF_STATUS_FR;
3537 ret = RK_LF_STATUS_NC;
3543 static int rk3288_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3544 unsigned int dsp_addr[][4])
3546 struct lcdc_device *lcdc_dev =
3547 container_of(dev_drv, struct lcdc_device, driver);
3548 spin_lock(&lcdc_dev->reg_lock);
3549 if (lcdc_dev->clk_on) {
3550 dsp_addr[0][0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3551 dsp_addr[1][0] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3552 dsp_addr[2][0] = lcdc_readl(lcdc_dev, WIN2_MST0);
3553 dsp_addr[2][1] = lcdc_readl(lcdc_dev, WIN2_MST1);
3554 dsp_addr[2][2] = lcdc_readl(lcdc_dev, WIN2_MST2);
3555 dsp_addr[2][3] = lcdc_readl(lcdc_dev, WIN2_MST3);
3556 dsp_addr[3][0] = lcdc_readl(lcdc_dev, WIN3_MST0);
3557 dsp_addr[3][1] = lcdc_readl(lcdc_dev, WIN3_MST1);
3558 dsp_addr[3][2] = lcdc_readl(lcdc_dev, WIN3_MST2);
3559 dsp_addr[3][3] = lcdc_readl(lcdc_dev, WIN3_MST3);
3561 spin_unlock(&lcdc_dev->reg_lock);
3565 static int rk3288_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv,
3566 int mode, int calc, int up,
3567 int down, int global)
3569 struct lcdc_device *lcdc_dev =
3570 container_of(dev_drv, struct lcdc_device, driver);
3571 struct rk_screen *screen = dev_drv->cur_screen;
3572 u32 total_pixel, calc_pixel, stage_up, stage_down;
3573 u32 pixel_num, global_dn;
3574 u32 mask = 0, val = 0;
3576 if (dev_drv->version != VOP_FULL_RK3288_V1_1) {
3577 pr_err("vop version:%x, not supoort cabc\n", dev_drv->version);
3580 if (!screen->cabc_lut) {
3581 pr_err("screen cabc lut not config, so not open cabc\n");
3584 dev_drv->cabc_mode = mode;
3585 if (!dev_drv->cabc_mode) {
3586 spin_lock(&lcdc_dev->reg_lock);
3587 if (lcdc_dev->clk_on) {
3588 lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
3589 m_CABC_HANDLE_EN | m_CABC_EN,
3590 v_CABC_EN(0) | v_CABC_HANDLE_EN(0));
3591 lcdc_cfg_done(lcdc_dev);
3593 pr_info("mode = 0, close cabc\n");
3594 spin_unlock(&lcdc_dev->reg_lock);
3598 total_pixel = screen->mode.xres * screen->mode.yres;
3599 pixel_num = 1000 - calc;
3600 calc_pixel = (total_pixel * pixel_num) / 1000;
3604 pr_info("enable cabc:mode=%d, calc=%d, up=%d, down=%d, global=%d\n",
3605 mode, calc, stage_up, stage_down, global_dn);
3607 spin_lock(&lcdc_dev->reg_lock);
3608 if (lcdc_dev->clk_on) {
3609 mask = m_CABC_EN | m_CABC_HANDLE_EN | m_PWM_CONFIG_MODE |
3610 m_CABC_CALC_PIXEL_NUM;
3611 val = v_CABC_EN(1) | v_CABC_HANDLE_EN(1) |
3612 v_PWM_CONFIG_MODE(STAGE_BY_STAGE) |
3613 v_CABC_CALC_PIXEL_NUM(calc_pixel);
3614 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3616 mask = m_CABC_LUT_EN | m_CABC_TOTAL_PIXEL_NUM;
3617 val = v_CABC_LUT_EN(1) | v_CABC_TOTAL_PIXEL_NUM(total_pixel);
3618 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3620 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_UP |
3621 m_CABC_STAGE_MODE | m_MAX_SCALE_CFG_VALUE |
3622 m_MAX_SCALE_CFG_ENABLE;
3623 val = v_CABC_STAGE_DOWN(stage_down) |
3624 v_CABC_STAGE_UP(stage_up) |
3625 v_CABC_STAGE_MODE(0) | v_MAX_SCALE_CFG_VALUE(1) |
3626 v_MAX_SCALE_CFG_ENABLE(0);
3627 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
3629 mask = m_CABC_GLOBAL_DN | m_CABC_GLOBAL_DN_LIMIT_EN;
3630 val = v_CABC_GLOBAL_DN(global_dn) |
3631 v_CABC_GLOBAL_DN_LIMIT_EN(1);
3632 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
3633 lcdc_cfg_done(lcdc_dev);
3635 spin_unlock(&lcdc_dev->reg_lock);
3642 sin_hue = sin(a)*256 +0x100;
3643 cos_hue = cos(a)*256;
3645 sin_hue = sin(a)*256;
3646 cos_hue = cos(a)*256;
3648 static int rk3288_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode)
3651 struct lcdc_device *lcdc_dev =
3652 container_of(dev_drv, struct lcdc_device, driver);
3655 spin_lock(&lcdc_dev->reg_lock);
3656 if (lcdc_dev->clk_on) {
3657 val = lcdc_readl(lcdc_dev, BCSH_H);
3660 val &= m_BCSH_SIN_HUE;
3663 val &= m_BCSH_COS_HUE;
3670 spin_unlock(&lcdc_dev->reg_lock);
3676 static int rk3288_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue)
3679 struct lcdc_device *lcdc_dev =
3680 container_of(dev_drv, struct lcdc_device, driver);
3683 spin_lock(&lcdc_dev->reg_lock);
3684 if (lcdc_dev->clk_on) {
3685 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
3686 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
3687 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
3688 lcdc_cfg_done(lcdc_dev);
3690 spin_unlock(&lcdc_dev->reg_lock);
3695 static int rk3288_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value)
3697 struct lcdc_device *lcdc_dev =
3698 container_of(dev_drv, struct lcdc_device, driver);
3701 spin_lock(&lcdc_dev->reg_lock);
3702 if(lcdc_dev->clk_on) {
3705 /*from 0 to 255,typical is 128*/
3708 else if (value >= 0x80)
3709 value = value - 0x80;
3710 mask = m_BCSH_BRIGHTNESS;
3711 val = v_BCSH_BRIGHTNESS(value);
3714 /*from 0 to 510,typical is 256*/
3715 mask = m_BCSH_CONTRAST;
3716 val = v_BCSH_CONTRAST(value);
3719 /*from 0 to 1015,typical is 256*/
3720 mask = m_BCSH_SAT_CON;
3721 val = v_BCSH_SAT_CON(value);
3726 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
3727 lcdc_cfg_done(lcdc_dev);
3729 spin_unlock(&lcdc_dev->reg_lock);
3733 static int rk3288_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode)
3735 struct lcdc_device *lcdc_dev =
3736 container_of(dev_drv, struct lcdc_device, driver);
3739 spin_lock(&lcdc_dev->reg_lock);
3740 if(lcdc_dev->clk_on) {
3741 val = lcdc_readl(lcdc_dev, BCSH_BCS);
3744 val &= m_BCSH_BRIGHTNESS;
3751 val &= m_BCSH_CONTRAST;
3755 val &= m_BCSH_SAT_CON;
3762 spin_unlock(&lcdc_dev->reg_lock);
3767 static int rk3288_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
3769 struct lcdc_device *lcdc_dev =
3770 container_of(dev_drv, struct lcdc_device, driver);
3773 spin_lock(&lcdc_dev->reg_lock);
3774 if (lcdc_dev->clk_on) {
3776 lcdc_writel(lcdc_dev,BCSH_COLOR_BAR,0x1);
3777 lcdc_writel(lcdc_dev,BCSH_BCS,0xd0010000);
3778 lcdc_writel(lcdc_dev,BCSH_H,0x01000000);
3779 dev_drv->bcsh.enable = 1;
3783 lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
3784 dev_drv->bcsh.enable = 0;
3786 if (dev_drv->version == VOP_FULL_RK3288_V1_1)
3787 rk3288_lcdc_bcsh_path_sel(dev_drv);
3788 lcdc_cfg_done(lcdc_dev);
3790 spin_unlock(&lcdc_dev->reg_lock);
3794 static int rk3288_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv,
3797 if (!enable || !dev_drv->bcsh.enable) {
3798 rk3288_lcdc_open_bcsh(dev_drv, false);
3802 if (dev_drv->bcsh.brightness <= 255 ||
3803 dev_drv->bcsh.contrast <= 510 ||
3804 dev_drv->bcsh.sat_con <= 1015 ||
3805 (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
3806 rk3288_lcdc_open_bcsh(dev_drv, true);
3807 if (dev_drv->bcsh.brightness <= 255)
3808 rk3288_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
3809 dev_drv->bcsh.brightness);
3810 if (dev_drv->bcsh.contrast <= 510)
3811 rk3288_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
3812 dev_drv->bcsh.contrast);
3813 if (dev_drv->bcsh.sat_con <= 1015)
3814 rk3288_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
3815 dev_drv->bcsh.sat_con);
3816 if (dev_drv->bcsh.sin_hue <= 511 &&
3817 dev_drv->bcsh.cos_hue <= 511)
3818 rk3288_lcdc_set_bcsh_hue(dev_drv,
3819 dev_drv->bcsh.sin_hue,
3820 dev_drv->bcsh.cos_hue);
3825 static int rk3288_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv,
3826 struct overscan *overscan)
3828 struct lcdc_device *lcdc_dev =
3829 container_of(dev_drv, struct lcdc_device, driver);
3831 if (unlikely(!lcdc_dev->clk_on)) {
3832 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
3835 rk3288_lcdc_post_cfg(dev_drv);
3840 static struct rk_lcdc_win lcdc_win[] = {
3844 .support_3d = false,
3849 .support_3d = false,
3854 .support_3d = false,
3859 .support_3d = false,
3863 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
3864 .open = rk3288_lcdc_open,
3865 .win_direct_en = rk3288_lcdc_win_direct_en,
3866 .load_screen = rk3288_load_screen,
3867 .get_dspbuf_info = rk3288_get_dspbuf_info,
3868 .post_dspbuf = rk3288_post_dspbuf,
3869 .set_par = rk3288_lcdc_set_par,
3870 .pan_display = rk3288_lcdc_pan_display,
3871 .direct_set_addr = rk3288_lcdc_direct_set_win_addr,
3872 .lcdc_reg_update = rk3288_lcdc_reg_update,
3873 .blank = rk3288_lcdc_blank,
3874 .ioctl = rk3288_lcdc_ioctl,
3875 .suspend = rk3288_lcdc_early_suspend,
3876 .resume = rk3288_lcdc_early_resume,
3877 .get_win_state = rk3288_lcdc_get_win_state,
3878 .area_support_num = rk3288_lcdc_get_area_num,
3879 .ovl_mgr = rk3288_lcdc_ovl_mgr,
3880 .get_disp_info = rk3288_lcdc_get_disp_info,
3881 .fps_mgr = rk3288_lcdc_fps_mgr,
3882 .fb_get_win_id = rk3288_lcdc_get_win_id,
3883 .fb_win_remap = rk3288_fb_win_remap,
3884 .set_dsp_lut = rk3288_set_dsp_lut,
3885 .poll_vblank = rk3288_lcdc_poll_vblank,
3886 .dpi_open = rk3288_lcdc_dpi_open,
3887 .dpi_win_sel = rk3288_lcdc_dpi_win_sel,
3888 .dpi_status = rk3288_lcdc_dpi_status,
3889 .get_dsp_addr = rk3288_lcdc_get_dsp_addr,
3890 .set_dsp_cabc = rk3288_lcdc_set_dsp_cabc,
3891 .set_dsp_bcsh_hue = rk3288_lcdc_set_bcsh_hue,
3892 .set_dsp_bcsh_bcs = rk3288_lcdc_set_bcsh_bcs,
3893 .get_dsp_bcsh_hue = rk3288_lcdc_get_bcsh_hue,
3894 .get_dsp_bcsh_bcs = rk3288_lcdc_get_bcsh_bcs,
3895 .open_bcsh = rk3288_lcdc_open_bcsh,
3896 .dump_reg = rk3288_lcdc_reg_dump,
3897 .cfg_done = rk3288_lcdc_config_done,
3898 .set_irq_to_cpu = rk3288_lcdc_set_irq_to_cpu,
3899 .mmu_en = rk3288_lcdc_mmu_en,
3900 .set_overscan = rk3288_lcdc_set_overscan,
3904 #ifdef LCDC_IRQ_DEBUG
3905 static int rk3288_lcdc_parse_irq(struct lcdc_device *lcdc_dev,unsigned int reg_val)
3907 if (reg_val & m_WIN0_EMPTY_INTR_STS) {
3908 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN0_EMPTY_INTR_CLR,
3909 v_WIN0_EMPTY_INTR_CLR(1));
3910 dev_warn(lcdc_dev->dev,"win0 empty irq!");
3911 }else if (reg_val & m_WIN1_EMPTY_INTR_STS) {
3912 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN1_EMPTY_INTR_CLR,
3913 v_WIN1_EMPTY_INTR_CLR(1));
3914 dev_warn(lcdc_dev->dev,"win1 empty irq!");
3915 }else if (reg_val & m_WIN2_EMPTY_INTR_STS) {
3916 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN2_EMPTY_INTR_CLR,
3917 v_WIN2_EMPTY_INTR_CLR(1));
3918 dev_warn(lcdc_dev->dev,"win2 empty irq!");
3919 }else if (reg_val & m_WIN3_EMPTY_INTR_STS) {
3920 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN3_EMPTY_INTR_CLR,
3921 v_WIN3_EMPTY_INTR_CLR(1));
3922 dev_warn(lcdc_dev->dev,"win3 empty irq!");
3923 }else if (reg_val & m_HWC_EMPTY_INTR_STS) {
3924 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_HWC_EMPTY_INTR_CLR,
3925 v_HWC_EMPTY_INTR_CLR(1));
3926 dev_warn(lcdc_dev->dev,"HWC empty irq!");
3927 }else if (reg_val & m_POST_BUF_EMPTY_INTR_STS) {
3928 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_POST_BUF_EMPTY_INTR_CLR,
3929 v_POST_BUF_EMPTY_INTR_CLR(1));
3930 dev_warn(lcdc_dev->dev,"post buf empty irq!");
3931 }else if (reg_val & m_PWM_GEN_INTR_STS) {
3932 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_PWM_GEN_INTR_CLR,
3933 v_PWM_GEN_INTR_CLR(1));
3934 dev_warn(lcdc_dev->dev,"PWM gen irq!");
3941 static irqreturn_t rk3288_lcdc_isr(int irq, void *dev_id)
3943 struct lcdc_device *lcdc_dev =
3944 (struct lcdc_device *)dev_id;
3945 ktime_t timestamp = ktime_get();
3948 intr0_reg = lcdc_readl(lcdc_dev, INTR_CTRL0);
3950 if(intr0_reg & m_FS_INTR_STS){
3951 timestamp = ktime_get();
3952 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_FS_INTR_CLR,
3954 /*if(lcdc_dev->driver.wait_fs){ */
3956 spin_lock(&(lcdc_dev->driver.cpl_lock));
3957 complete(&(lcdc_dev->driver.frame_done));
3958 spin_unlock(&(lcdc_dev->driver.cpl_lock));
3960 lcdc_dev->driver.vsync_info.timestamp = timestamp;
3961 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
3963 }else if(intr0_reg & m_LINE_FLAG_INTR_STS){
3964 lcdc_dev->driver.frame_time.last_framedone_t =
3965 lcdc_dev->driver.frame_time.framedone_t;
3966 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3967 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR,
3968 v_LINE_FLAG_INTR_CLR(1));
3969 }else if(intr0_reg & m_BUS_ERROR_INTR_STS){
3970 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_BUS_ERROR_INTR_CLR,
3971 v_BUS_ERROR_INTR_CLR(1));
3972 dev_warn(lcdc_dev->dev,"buf_error_int!");
3975 /* for win empty debug */
3976 #ifdef LCDC_IRQ_EMPTY_DEBUG
3977 intr1_reg = lcdc_readl(lcdc_dev, INTR_CTRL1);
3978 if (intr1_reg != 0) {
3979 rk3288_lcdc_parse_irq(lcdc_dev,intr1_reg);
3985 #if defined(CONFIG_PM)
3986 static int rk3288_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
3991 static int rk3288_lcdc_resume(struct platform_device *pdev)
3996 #define rk3288_lcdc_suspend NULL
3997 #define rk3288_lcdc_resume NULL
4000 static int rk3288_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4002 struct device_node *np = lcdc_dev->dev->of_node;
4003 struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4006 if (of_property_read_u32(np, "rockchip,prop", &val))
4007 lcdc_dev->prop = PRMRY; /*default set it as primary */
4009 lcdc_dev->prop = val;
4011 if (of_property_read_u32(np, "rockchip,mirror", &val))
4012 dev_drv->rotate_mode = NO_MIRROR;
4014 dev_drv->rotate_mode = val;
4016 if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4017 dev_drv->cabc_mode = 0; /* default set close cabc */
4019 dev_drv->cabc_mode = val;
4021 if (of_property_read_u32(np, "rockchip,pwr18", &val))
4022 lcdc_dev->pwr18 = false; /*default set it as 3.xv power supply */
4024 lcdc_dev->pwr18 = (val ? true : false);
4026 if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4027 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4029 dev_drv->fb_win_map = val;
4031 if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4032 dev_drv->bcsh.enable = false;
4034 dev_drv->bcsh.enable = (val ? true : false);
4036 if (of_property_read_u32(np, "rockchip,brightness", &val))
4037 dev_drv->bcsh.brightness = 0xffff;
4039 dev_drv->bcsh.brightness = val;
4041 if (of_property_read_u32(np, "rockchip,contrast", &val))
4042 dev_drv->bcsh.contrast = 0xffff;
4044 dev_drv->bcsh.contrast = val;
4046 if (of_property_read_u32(np, "rockchip,sat-con", &val))
4047 dev_drv->bcsh.sat_con = 0xffff;
4049 dev_drv->bcsh.sat_con = val;
4051 if (of_property_read_u32(np, "rockchip,hue", &val)) {
4052 dev_drv->bcsh.sin_hue = 0xffff;
4053 dev_drv->bcsh.cos_hue = 0xffff;
4055 dev_drv->bcsh.sin_hue = val & 0xff;
4056 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4059 if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4060 dev_drv->iommu_enabled = 0;
4062 dev_drv->iommu_enabled = val;
4066 static int rk3288_lcdc_probe(struct platform_device *pdev)
4068 struct lcdc_device *lcdc_dev = NULL;
4069 struct rk_lcdc_driver *dev_drv;
4070 struct device *dev = &pdev->dev;
4071 struct resource *res;
4072 struct device_node *np = pdev->dev.of_node;
4076 /*if the primary lcdc has not registered ,the extend
4077 lcdc register later */
4078 of_property_read_u32(np, "rockchip,prop", &prop);
4079 if (prop == EXTEND) {
4080 if (!is_prmry_rk_lcdc_registered())
4081 return -EPROBE_DEFER;
4083 lcdc_dev = devm_kzalloc(dev,
4084 sizeof(struct lcdc_device), GFP_KERNEL);
4086 dev_err(&pdev->dev, "rk3288 lcdc device kmalloc fail!");
4089 platform_set_drvdata(pdev, lcdc_dev);
4090 lcdc_dev->dev = dev;
4091 rk3288_lcdc_parse_dt(lcdc_dev);
4092 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4093 lcdc_dev->reg_phy_base = res->start;
4094 lcdc_dev->len = resource_size(res);
4095 lcdc_dev->regs = devm_ioremap_resource(dev, res);
4096 if (IS_ERR(lcdc_dev->regs))
4097 return PTR_ERR(lcdc_dev->regs);
4099 lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4100 if (IS_ERR(lcdc_dev->regsbak))
4101 return PTR_ERR(lcdc_dev->regsbak);
4102 lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4103 lcdc_dev->id = rk3288_lcdc_get_id(lcdc_dev->reg_phy_base);
4104 if (lcdc_dev->id < 0) {
4105 dev_err(&pdev->dev, "no such lcdc device!\n");
4108 dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4109 dev_drv = &lcdc_dev->driver;
4111 dev_drv->prop = prop;
4112 dev_drv->id = lcdc_dev->id;
4113 dev_drv->ops = &lcdc_drv_ops;
4114 dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4115 spin_lock_init(&lcdc_dev->reg_lock);
4117 lcdc_dev->irq = platform_get_irq(pdev, 0);
4118 if (lcdc_dev->irq < 0) {
4119 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4124 ret = devm_request_irq(dev, lcdc_dev->irq, rk3288_lcdc_isr,
4125 IRQF_DISABLED | IRQF_SHARED, dev_name(dev), lcdc_dev);
4127 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4128 lcdc_dev->irq, ret);
4132 if (dev_drv->iommu_enabled) {
4133 if(lcdc_dev->id == 0){
4134 strcpy(dev_drv->mmu_dts_name, VOPB_IOMMU_COMPATIBLE_NAME);
4136 strcpy(dev_drv->mmu_dts_name, VOPL_IOMMU_COMPATIBLE_NAME);
4140 ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4142 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4145 lcdc_dev->screen = dev_drv->screen0;
4146 dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4147 lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4152 static int rk3288_lcdc_remove(struct platform_device *pdev)
4158 static void rk3288_lcdc_shutdown(struct platform_device *pdev)
4160 struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
4162 rk3288_lcdc_deint(lcdc_dev);
4163 rk_disp_pwr_disable(&lcdc_dev->driver);
4166 #if defined(CONFIG_OF)
4167 static const struct of_device_id rk3288_lcdc_dt_ids[] = {
4168 {.compatible = "rockchip,rk3288-lcdc",},
4173 static struct platform_driver rk3288_lcdc_driver = {
4174 .probe = rk3288_lcdc_probe,
4175 .remove = rk3288_lcdc_remove,
4177 .name = "rk3288-lcdc",
4178 .owner = THIS_MODULE,
4179 .of_match_table = of_match_ptr(rk3288_lcdc_dt_ids),
4181 .suspend = rk3288_lcdc_suspend,
4182 .resume = rk3288_lcdc_resume,
4183 .shutdown = rk3288_lcdc_shutdown,
4186 static int __init rk3288_lcdc_module_init(void)
4188 return platform_driver_register(&rk3288_lcdc_driver);
4191 static void __exit rk3288_lcdc_module_exit(void)
4193 platform_driver_unregister(&rk3288_lcdc_driver);
4196 fs_initcall(rk3288_lcdc_module_init);
4197 module_exit(rk3288_lcdc_module_exit);