drivers/video/rockchip/lcdc/rk3288_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3288_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *Author:hjc<hjc@rock-chips.com>
   6  *This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <asm/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk3288_lcdc.h"
  39
  40 #if defined(CONFIG_HAS_EARLYSUSPEND)
  41 #include <linux/earlysuspend.h>
  42 #endif
  43
  44 static int dbg_thresd;
  45 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  46
  47 #define DBG(level, x...) do {                   \
  48         if (unlikely(dbg_thresd >= level))      \
  49                 printk(KERN_INFO x); } while (0)
  50
  51 static int rk3288_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv,
  52                                      bool enable);
  53
  54 /*#define WAIT_FOR_SYNC 1*/
  55
  56 static int rk3288_lcdc_get_id(u32 phy_base)
  57 {
  58         if (cpu_is_rk3288()) {
  59                 if (phy_base == 0xff930000)/*vop big*/
  60                         return 0;
  61                 else if (phy_base == 0xff940000)/*vop lit*/
  62                         return 1;
  63                 else
  64                         return -EINVAL;
  65         } else {
  66                 pr_err("un supported platform \n");
  67                 return -EINVAL;
  68         }
  69 }
  70
  71 static int rk3288_lcdc_set_lut(struct rk_lcdc_driver *dev_drv)
  72 {
  73         int i,j;
  74         int __iomem *c;
  75         u32 v,r,g,b;
  76         struct lcdc_device *lcdc_dev = container_of(dev_drv,
  77                                         struct lcdc_device,driver);
  78         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
  79         lcdc_cfg_done(lcdc_dev);
  80         mdelay(25);
  81         for (i = 0; i < 256; i++) {
  82                 v = dev_drv->cur_screen->dsp_lut[i];
  83                 c = lcdc_dev->dsp_lut_addr_base + (i << 2);
  84                 b = (v & 0xff) << 2;
  85                 g = (v & 0xff00) << 4;
  86                 r = (v & 0xff0000) << 6;
  87                 v = r + g + b;
  88                 for (j = 0; j < 4; j++) {
  89                         writel_relaxed(v, c);
  90                         v += (1 + (1 << 10) + (1 << 20)) ;
  91                         c++;
  92                 }
  93         }
  94         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
  95
  96         return 0;
  97
  98 }
  99
 100 static int rk3288_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 101 {
 102 #ifdef CONFIG_RK_FPGA
 103         lcdc_dev->clk_on = 1;
 104         return 0;
 105 #endif
 106         if (!lcdc_dev->clk_on) {
 107                 clk_prepare_enable(lcdc_dev->hclk);
 108                 clk_prepare_enable(lcdc_dev->dclk);
 109                 clk_prepare_enable(lcdc_dev->aclk);
 110                 clk_prepare_enable(lcdc_dev->pd);
 111                 spin_lock(&lcdc_dev->reg_lock);
 112                 lcdc_dev->clk_on = 1;
 113                 spin_unlock(&lcdc_dev->reg_lock);
 114         }
 115
 116         return 0;
 117 }
 118
 119 static int rk3288_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 120 {
 121 #ifdef CONFIG_RK_FPGA
 122         lcdc_dev->clk_on = 0;
 123         return 0;
 124 #endif
 125         if (lcdc_dev->clk_on) {
 126                 spin_lock(&lcdc_dev->reg_lock);
 127                 lcdc_dev->clk_on = 0;
 128                 spin_unlock(&lcdc_dev->reg_lock);
 129                 mdelay(25);
 130                 clk_disable_unprepare(lcdc_dev->dclk);
 131                 clk_disable_unprepare(lcdc_dev->hclk);
 132                 clk_disable_unprepare(lcdc_dev->aclk);
 133                 clk_disable_unprepare(lcdc_dev->pd);
 134         }
 135
 136         return 0;
 137 }
 138
 139 static int rk3288_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 140 {
 141         u32 mask, val;
 142         spin_lock(&lcdc_dev->reg_lock);
 143         if (likely(lcdc_dev->clk_on)) {
 144                 mask = m_DSP_HOLD_VALID_INTR_EN | m_FS_INTR_EN |
 145                         m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_EN;
 146                 val = v_DSP_HOLD_VALID_INTR_EN(0) | v_FS_INTR_EN(0) |
 147                         v_LINE_FLAG_INTR_EN(0) | v_BUS_ERROR_INTR_EN(0);
 148                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
 149
 150                 mask = m_DSP_HOLD_VALID_INTR_CLR | m_FS_INTR_CLR |
 151                         m_LINE_FLAG_INTR_CLR | m_LINE_FLAG_INTR_CLR;
 152                 val = v_DSP_HOLD_VALID_INTR_CLR(0) | v_FS_INTR_CLR(0) |
 153                         v_LINE_FLAG_INTR_CLR(0) | v_BUS_ERROR_INTR_CLR(0);
 154                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
 155
 156                 mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
 157                         m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
 158                         m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
 159                         m_POST_BUF_EMPTY_INTR_EN;
 160                 val = v_WIN0_EMPTY_INTR_EN(0) | v_WIN1_EMPTY_INTR_EN(0) |
 161                         v_WIN2_EMPTY_INTR_EN(0) | v_WIN3_EMPTY_INTR_EN(0) |
 162                         v_HWC_EMPTY_INTR_EN(0) | v_POST_BUF_EMPTY_INTR_EN(0) |
 163                         v_PWM_GEN_INTR_EN(0);
 164                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
 165
 166                 mask = m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
 167                         m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
 168                         m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
 169                         m_POST_BUF_EMPTY_INTR_CLR;
 170                 val = v_WIN0_EMPTY_INTR_CLR(0) | v_WIN1_EMPTY_INTR_CLR(0) |
 171                         v_WIN2_EMPTY_INTR_CLR(0) | v_WIN3_EMPTY_INTR_CLR(0) |
 172                         v_HWC_EMPTY_INTR_CLR(0) | v_POST_BUF_EMPTY_INTR_CLR(0) |
 173                         v_PWM_GEN_INTR_CLR(0);
 174                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
 175                 lcdc_cfg_done(lcdc_dev);
 176                 spin_unlock(&lcdc_dev->reg_lock);
 177         } else {
 178                 spin_unlock(&lcdc_dev->reg_lock);
 179         }
 180         mdelay(1);
 181         return 0;
 182 }
 183 static int rk3288_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
 184 {
 185         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 186                                                 struct lcdc_device,
 187                                                 driver);
 188         int *cbase = (int *)lcdc_dev->regs;
 189         int *regsbak = (int *)lcdc_dev->regsbak;
 190         int i, j;
 191
 192         printk("back up reg:\n");
 193         for (i = 0; i <= (0x200 >> 4); i++) {
 194                 printk("0x%04x: ",i*16);
 195                 for (j = 0; j < 4; j++)
 196                         printk("%08x  ", *(regsbak + i * 4 + j));
 197                 printk("\n");
 198         }
 199
 200         printk("lcdc reg:\n");
 201         for (i = 0; i <= (0x200 >> 4); i++) {
 202                 printk("0x%04x: ",i*16);
 203                 for (j = 0; j < 4; j++)
 204                         printk("%08x  ", readl_relaxed(cbase + i * 4 + j));
 205                 printk("\n");
 206         }
 207         return 0;
 208
 209 }
 210
 211 #define WIN_EN(id)              \
 212 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en)       \
 213 { \
 214         u32 msk, val;                                                   \
 215         spin_lock(&lcdc_dev->reg_lock);                                 \
 216         msk =  m_WIN##id##_EN;                                          \
 217         val  =  v_WIN##id##_EN(en);                                     \
 218         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);              \
 219         lcdc_cfg_done(lcdc_dev);                                        \
 220         val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);            \
 221         while (val !=  (!!en))  {                                       \
 222                 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);    \
 223         }                                                               \
 224         spin_unlock(&lcdc_dev->reg_lock);                               \
 225         return 0;                                                       \
 226 }
 227
 228 WIN_EN(0);
 229 WIN_EN(1);
 230 WIN_EN(2);
 231 WIN_EN(3);
 232 /*enable/disable win directly*/
 233 static int rk3288_lcdc_win_direct_en
 234                 (struct rk_lcdc_driver *drv, int win_id , int en)
 235 {
 236         struct lcdc_device *lcdc_dev = container_of(drv,
 237                                         struct lcdc_device, driver);
 238         if (win_id == 0)
 239                 win0_enable(lcdc_dev, en);
 240         else if (win_id == 1)
 241                 win1_enable(lcdc_dev, en);
 242         else if (win_id == 2)
 243                 win2_enable(lcdc_dev, en);
 244         else if (win_id == 3)
 245                 win3_enable(lcdc_dev, en);
 246         else
 247                 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
 248         return 0;
 249
 250 }
 251
 252 #define SET_WIN_ADDR(id) \
 253 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
 254 {                                                       \
 255         u32 msk, val;                                   \
 256         spin_lock(&lcdc_dev->reg_lock);                 \
 257         lcdc_writel(lcdc_dev,WIN##id##_YRGB_MST,addr);  \
 258         msk =  m_WIN##id##_EN;                          \
 259         val  =  v_WIN0_EN(1);                           \
 260         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk,val);       \
 261         lcdc_cfg_done(lcdc_dev);                        \
 262         spin_unlock(&lcdc_dev->reg_lock);               \
 263         return 0;                                       \
 264 }
 265
 266 SET_WIN_ADDR(0);
 267 SET_WIN_ADDR(1);
 268 int rk3288_lcdc_direct_set_win_addr
 269                 (struct rk_lcdc_driver *dev_drv, int win_id, u32 addr)
 270 {
 271         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 272                                 struct lcdc_device, driver);
 273         if (win_id == 0)
 274                 set_win0_addr(lcdc_dev, addr);
 275         else
 276                 set_win1_addr(lcdc_dev, addr);
 277
 278         return 0;
 279 }
 280
 281 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 282 {
 283         int reg = 0;
 284         u32 val = 0;
 285         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 286         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 287         u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 288         u32 st_x, st_y;
 289         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 290
 291         spin_lock(&lcdc_dev->reg_lock);
 292         for (reg = 0; reg < FRC_LOWER11_1; reg += 4) {
 293                 val = lcdc_readl(lcdc_dev, reg);
 294                 switch (reg) {
 295                         case WIN0_ACT_INFO:
 296                                 win0->area[0].xact =
 297                                         (val & m_WIN0_ACT_WIDTH) + 1;
 298                                 win0->area[0].yact =
 299                                         ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
 300                                 break;
 301                         case WIN0_DSP_INFO:
 302                                 win0->area[0].xsize =
 303                                         (val & m_WIN0_DSP_WIDTH) + 1;
 304                                 win0->area[0].ysize =
 305                                         ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
 306                                 break;
 307                         case WIN0_DSP_ST:
 308                                 st_x = val & m_WIN0_DSP_XST;
 309                                 st_y = (val & m_WIN0_DSP_YST) >> 16;
 310                                 win0->area[0].xpos = st_x - h_pw_bp;
 311                                 win0->area[0].ypos = st_y - v_pw_bp;
 312                                 break;
 313                         case WIN0_CTRL0:
 314                                 win0->state = val & m_WIN0_EN;
 315                                 win0->area[0].fmt_cfg =
 316                                         (val & m_WIN0_DATA_FMT) >> 1;
 317                                 win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
 318                                 win0->area[0].format = win0->area[0].fmt_cfg;
 319                                 break;
 320                         case WIN0_VIR:
 321                                 win0->area[0].y_vir_stride =
 322                                         val & m_WIN0_VIR_STRIDE;
 323                                 win0->area[0].uv_vir_stride =
 324                                         (val & m_WIN0_VIR_STRIDE_UV) >> 16;
 325                                 if (win0->area[0].format == ARGB888)
 326                                         win0->area[0].xvir =
 327                                                 win0->area[0].y_vir_stride;
 328                                 else if (win0->area[0].format == RGB888)
 329                                         win0->area[0].xvir =
 330                                                 win0->area[0].y_vir_stride * 4 / 3;
 331                                 else if (win0->area[0].format == RGB565)
 332                                         win0->area[0].xvir =
 333                                                 2 * win0->area[0].y_vir_stride;
 334                                 else /* YUV */
 335                                         win0->area[0].xvir =
 336                                                 4 * win0->area[0].y_vir_stride;
 337                                 break;
 338                         case WIN0_YRGB_MST:
 339                                 win0->area[0].smem_start = val;
 340                                 break;
 341                         case WIN0_CBR_MST:
 342                                 win0->area[0].cbr_start = val;
 343                                 break;
 344                         default:
 345                                 break;
 346                 }
 347         }
 348         spin_unlock(&lcdc_dev->reg_lock);
 349
 350 }
 351
 352 /********do basic init*********/
 353 static int rk3288_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 354 {
 355         int v;
 356         u32 mask,val;
 357         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 358                                                            struct
 359                                                            lcdc_device,
 360                                                    driver);
 361         if (lcdc_dev->pre_init)
 362                 return 0;
 363
 364         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 365         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 366         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 367         lcdc_dev->pd   = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
 368
 369         if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||
 370             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 371                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 372                         lcdc_dev->id);
 373         }
 374
 375         rk_disp_pwr_enable(dev_drv);
 376         rk3288_lcdc_clk_enable(lcdc_dev);
 377
 378         /*backup reg config at uboot*/
 379         lcdc_read_reg_defalut_cfg(lcdc_dev);
 380         v = 0;
 381 #ifndef CONFIG_RK_FPGA
 382         if (lcdc_dev->pwr18 == true) {
 383                 v = 0x00010001; /*bit14: 1,1.8v;0,3.3v*/
 384                 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL);
 385         } else {
 386                 v = 0x00010000;
 387                 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL);
 388         }
 389 #endif
 390         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_0,0x15110903);
 391         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_1,0x00030911);
 392         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_0,0x1a150b04);
 393         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_1,0x00040b15);
 394         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_0,0x15110903);
 395         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_1,0x00030911);
 396
 397         lcdc_writel(lcdc_dev,FRC_LOWER01_0,0x12844821);
 398         lcdc_writel(lcdc_dev,FRC_LOWER01_1,0x21488412);
 399         lcdc_writel(lcdc_dev,FRC_LOWER10_0,0xa55a9696);
 400         lcdc_writel(lcdc_dev,FRC_LOWER10_1,0x5aa56969);
 401         lcdc_writel(lcdc_dev,FRC_LOWER11_0,0xdeb77deb);
 402         lcdc_writel(lcdc_dev,FRC_LOWER11_1,0xed7bb7de);
 403
 404         mask =  m_AUTO_GATING_EN;
 405         val  =  v_AUTO_GATING_EN(0);
 406         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask,val);
 407         lcdc_cfg_done(lcdc_dev);
 408         if (dev_drv->iommu_enabled) /*disable win0 to workaround iommu pagefault*/
 409                 win0_enable(lcdc_dev, 0);
 410         lcdc_dev->pre_init = true;
 411
 412
 413         return 0;
 414 }
 415
 416 static void rk3288_lcdc_deint(struct lcdc_device *lcdc_dev)
 417 {
 418
 419
 420         rk3288_lcdc_disable_irq(lcdc_dev);
 421         spin_lock(&lcdc_dev->reg_lock);
 422         if (likely(lcdc_dev->clk_on)) {
 423                 lcdc_dev->clk_on = 0;
 424                 lcdc_set_bit(lcdc_dev, SYS_CTRL, m_STANDBY_EN);
 425                 lcdc_cfg_done(lcdc_dev);
 426                 spin_unlock(&lcdc_dev->reg_lock);
 427         } else {
 428                 spin_unlock(&lcdc_dev->reg_lock);
 429         }
 430         mdelay(1);
 431 }
 432 static int rk3288_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
 433 {
 434         struct lcdc_device *lcdc_dev =
 435             container_of(dev_drv, struct lcdc_device, driver);
 436         struct rk_screen *screen = dev_drv->cur_screen;
 437         u16 x_res = screen->mode.xres;
 438         u16 y_res = screen->mode.yres;
 439         u32 mask, val;
 440         u16 h_total,v_total;
 441         u16 post_hsd_en,post_vsd_en;
 442         u16 post_dsp_hact_st,post_dsp_hact_end;
 443         u16 post_dsp_vact_st,post_dsp_vact_end;
 444         u16 post_dsp_vact_st_f1,post_dsp_vact_end_f1;
 445         u16 post_h_fac,post_v_fac;
 446
 447         h_total = screen->mode.hsync_len+screen->mode.left_margin +
 448                   x_res + screen->mode.right_margin;
 449         v_total = screen->mode.vsync_len+screen->mode.upper_margin +
 450                   y_res + screen->mode.lower_margin;
 451
 452         if(screen->post_dsp_stx + screen->post_xsize > x_res){
 453                 dev_warn(lcdc_dev->dev, "post:stx[%d] + xsize[%d] > x_res[%d]\n",
 454                         screen->post_dsp_stx,screen->post_xsize,x_res);
 455                 screen->post_dsp_stx = x_res - screen->post_xsize;
 456         }
 457         if(screen->x_mirror == 0){
 458                 post_dsp_hact_st=screen->post_dsp_stx +
 459                         screen->mode.hsync_len+screen->mode.left_margin;
 460                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 461         }else{
 462                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 463                                         screen->post_dsp_stx;
 464                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 465         }
 466         if((screen->post_xsize < x_res)&&(screen->post_xsize != 0)){
 467                 post_hsd_en = 1;
 468                 post_h_fac =
 469                         GET_SCALE_FACTOR_BILI_DN(x_res , screen->post_xsize);
 470         }else{
 471                 post_hsd_en = 0;
 472                 post_h_fac = 0x1000;
 473         }
 474
 475
 476         if(screen->post_dsp_sty + screen->post_ysize > y_res){
 477                 dev_warn(lcdc_dev->dev, "post:sty[%d] + ysize[%d] > y_res[%d]\n",
 478                         screen->post_dsp_sty,screen->post_ysize,y_res);
 479                 screen->post_dsp_sty = y_res - screen->post_ysize;
 480         }
 481
 482         if(screen->y_mirror == 0){
 483                 post_dsp_vact_st = screen->post_dsp_sty +
 484                         screen->mode.vsync_len+screen->mode.upper_margin;
 485                 post_dsp_vact_end = post_dsp_vact_st + screen->post_ysize;
 486         }else{
 487                 post_dsp_vact_end = v_total - screen->mode.lower_margin -
 488                                         - screen->post_dsp_sty;
 489                 post_dsp_vact_st = post_dsp_vact_end - screen->post_ysize;
 490         }
 491         if((screen->post_ysize < y_res)&&(screen->post_ysize != 0)){
 492                 post_vsd_en = 1;
 493                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res, screen->post_ysize);
 494         }else{
 495                 post_vsd_en = 0;
 496                 post_v_fac = 0x1000;
 497         }
 498
 499         if(screen->interlace == 1){
 500                 post_dsp_vact_st_f1  = v_total + post_dsp_vact_st;
 501                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 + screen->post_ysize;
 502         }else{
 503                 post_dsp_vact_st_f1  = 0;
 504                 post_dsp_vact_end_f1 = 0;
 505         }
 506         DBG(1,"post:xsize=%d,ysize=%d,xpos=%d,ypos=%d,"
 507               "hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 508                 screen->post_xsize,screen->post_ysize,screen->xpos,screen->ypos,
 509                 post_hsd_en,post_h_fac,post_vsd_en,post_v_fac);
 510         mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
 511         val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
 512               v_DSP_HACT_ST_POST(post_dsp_hact_st);
 513         lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
 514
 515         mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
 516         val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
 517               v_DSP_VACT_ST_POST(post_dsp_vact_st);
 518         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
 519
 520         mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
 521         val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
 522                 v_POST_VS_FACTOR_YRGB(post_v_fac);
 523         lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
 524
 525         mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
 526         val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
 527                 v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
 528         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
 529
 530         mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
 531         val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
 532         lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
 533         return 0;
 534 }
 535
 536 static int rk3288_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 537 {
 538         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 539                                                            struct
 540                                                            lcdc_device,
 541                                                            driver);
 542         struct rk_lcdc_win *win;
 543         u32  colorkey_r,colorkey_g,colorkey_b;
 544         int i,key_val;
 545         for(i=0;i<4;i++){
 546                 win = dev_drv->win[i];
 547                 key_val = win->color_key_val;
 548                 colorkey_r = (key_val & 0xff)<<2;
 549                 colorkey_g = ((key_val>>8)&0xff)<<12;
 550                 colorkey_b = ((key_val>>16)&0xff)<<22;
 551                 /*color key dither 565/888->aaa*/
 552                 key_val = colorkey_r | colorkey_g | colorkey_b;
 553                 switch(i){
 554                 case 0:
 555                         lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
 556                         break;
 557                 case 1:
 558                         lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
 559                         break;
 560                 case 2:
 561                         lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
 562                         break;
 563                 case 3:
 564                         lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
 565                         break;
 566                 default:
 567                         printk(KERN_WARNING "%s:un support win num:%d\n",
 568                                 __func__,i);
 569                         break;
 570                 }
 571         }
 572         return 0;
 573 }
 574
 575 static int rk3288_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv,int win_id)
 576 {
 577         struct lcdc_device *lcdc_dev =
 578                 container_of(dev_drv, struct lcdc_device, driver);
 579         struct rk_lcdc_win *win = dev_drv->win[win_id];
 580         struct alpha_config alpha_config;
 581
 582         u32 mask, val;
 583         int ppixel_alpha,global_alpha;
 584         u32 src_alpha_ctl,dst_alpha_ctl;
 585         ppixel_alpha = ((win->area[0].format == ARGB888) ||
 586                         (win->area[0].format == ABGR888)) ? 1 : 0;
 587         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 588         alpha_config.src_global_alpha_val = win->g_alpha_val;
 589         win->alpha_mode = AB_SRC_OVER;
 590         /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
 591                 __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,global_alpha);*/
 592         switch(win->alpha_mode){
 593         case AB_USER_DEFINE:
 594                 break;
 595         case AB_CLEAR:
 596                 alpha_config.src_factor_mode=AA_ZERO;
 597                 alpha_config.dst_factor_mode=AA_ZERO;
 598                 break;
 599         case AB_SRC:
 600                 alpha_config.src_factor_mode=AA_ONE;
 601                 alpha_config.dst_factor_mode=AA_ZERO;
 602                 break;
 603         case AB_DST:
 604                 alpha_config.src_factor_mode=AA_ZERO;
 605                 alpha_config.dst_factor_mode=AA_ONE;
 606                 break;
 607         case AB_SRC_OVER:
 608                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 609                 if(global_alpha)
 610                         alpha_config.src_factor_mode=AA_SRC_GLOBAL;
 611                 else
 612                         alpha_config.src_factor_mode=AA_ONE;
 613                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 614                 break;
 615         case AB_DST_OVER:
 616                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 617                 alpha_config.src_factor_mode=AA_SRC_INVERSE;
 618                 alpha_config.dst_factor_mode=AA_ONE;
 619                 break;
 620         case AB_SRC_IN:
 621                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 622                 alpha_config.src_factor_mode=AA_SRC;
 623                 alpha_config.dst_factor_mode=AA_ZERO;
 624                 break;
 625         case AB_DST_IN:
 626                 alpha_config.src_factor_mode=AA_ZERO;
 627                 alpha_config.dst_factor_mode=AA_SRC;
 628                 break;
 629         case AB_SRC_OUT:
 630                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 631                 alpha_config.src_factor_mode=AA_SRC_INVERSE;
 632                 alpha_config.dst_factor_mode=AA_ZERO;
 633                 break;
 634         case AB_DST_OUT:
 635                 alpha_config.src_factor_mode=AA_ZERO;
 636                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 637                 break;
 638         case AB_SRC_ATOP:
 639                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 640                 alpha_config.src_factor_mode=AA_SRC;
 641                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 642                 break;
 643         case AB_DST_ATOP:
 644                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 645                 alpha_config.src_factor_mode=AA_SRC_INVERSE;
 646                 alpha_config.dst_factor_mode=AA_SRC;
 647                 break;
 648         case XOR:
 649                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 650                 alpha_config.src_factor_mode=AA_SRC_INVERSE;
 651                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 652                 break;
 653         case AB_SRC_OVER_GLOBAL:
 654                 alpha_config.src_global_alpha_mode=AA_PER_PIX_GLOBAL;
 655                 alpha_config.src_color_mode=AA_SRC_NO_PRE_MUL;
 656                 alpha_config.src_factor_mode=AA_SRC_GLOBAL;
 657                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 658                 break;
 659         default:
 660                 pr_err("alpha mode error\n");
 661                 break;
 662         }
 663         if((ppixel_alpha == 1)&&(global_alpha == 1)){
 664                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 665         }else if(ppixel_alpha == 1){
 666                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 667         }else if(global_alpha == 1){
 668                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 669         }else{
 670                 dev_warn(lcdc_dev->dev,"alpha_en should be 0\n");
 671         }
 672         alpha_config.src_alpha_mode = AA_STRAIGHT;
 673         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 674
 675         switch(win_id){
 676         case 0:
 677                 src_alpha_ctl = 0x60;
 678                 dst_alpha_ctl = 0x64;
 679                 break;
 680         case 1:
 681                 src_alpha_ctl = 0xa0;
 682                 dst_alpha_ctl = 0xa4;
 683                 break;
 684         case 2:
 685                 src_alpha_ctl = 0xdc;
 686                 dst_alpha_ctl = 0xec;
 687                 break;
 688         case 3:
 689                 src_alpha_ctl = 0x12c;
 690                 dst_alpha_ctl = 0x13c;
 691                 break;
 692         }
 693         mask = m_WIN0_DST_FACTOR_M0;
 694         val  = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
 695         lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
 696         mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
 697                 m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
 698                 m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0|
 699                 m_WIN0_SRC_GLOBAL_ALPHA;
 700         val = v_WIN0_SRC_ALPHA_EN(1) |
 701                 v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
 702                 v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
 703                 v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
 704                 v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
 705                 v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
 706                 v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 707         lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
 708
 709         return 0;
 710 }
 711 static int rk3288_lcdc_area_swap(struct rk_lcdc_win *win,int area_num)
 712 {
 713         struct rk_lcdc_win_area area_temp;
 714         switch(area_num){
 715         case 2:
 716                 area_temp = win->area[0];
 717                 win->area[0] = win->area[1];
 718                 win->area[1] = area_temp;
 719                 break;
 720         case 3:
 721                 area_temp = win->area[0];
 722                 win->area[0] = win->area[2];
 723                 win->area[2] = area_temp;
 724                 break;
 725         case 4:
 726                 area_temp = win->area[0];
 727                 win->area[0] = win->area[3];
 728                 win->area[3] = area_temp;
 729
 730                 area_temp = win->area[1];
 731                 win->area[1] = win->area[2];
 732                 win->area[2] = area_temp;
 733                 break;
 734         default:
 735                 printk(KERN_WARNING "un supported area num!\n");
 736                 break;
 737         }
 738         return 0;
 739 }
 740
 741 static int rk3288_win_area_check_var(int win_id,int area_num,struct rk_lcdc_win_area *area_pre,
 742                         struct rk_lcdc_win_area *area_now)
 743 {
 744         if((area_pre->ypos >= area_now->ypos) ||
 745                 (area_pre->ypos+area_pre->ysize > area_now->ypos)){
 746                 area_now->state = 0;
 747                 pr_err("win[%d]:\n"
 748                         "area_pre[%d]:ypos[%d],ysize[%d]\n"
 749                         "area_now[%d]:ypos[%d],ysize[%d]\n",
 750                         win_id,
 751                         area_num-1,area_pre->ypos,area_pre->ysize,
 752                         area_num,  area_now->ypos,area_now->ysize);
 753                 return -EINVAL;
 754         }
 755         return 0;
 756 }
 757
 758 static int rk3288_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv,int win_id)
 759 {
 760         struct lcdc_device *lcdc_dev =
 761             container_of(dev_drv, struct lcdc_device, driver);
 762         struct rk_lcdc_win *win = dev_drv->win[win_id];
 763         unsigned int mask, val, off;
 764         off = win_id * 0x40;
 765         if(win->win_lb_mode == 5)
 766                 win->win_lb_mode = 4;
 767
 768         if(win->state == 1){
 769                 mask =  m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
 770                         m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_UV_SWAP;
 771                 val  =  v_WIN0_EN(win->state) |
 772                         v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
 773                         v_WIN0_FMT_10(win->fmt_10) |
 774                         v_WIN0_LB_MODE(win->win_lb_mode) |
 775                         v_WIN0_RB_SWAP(win->area[0].swap_rb) |
 776                         v_WIN0_UV_SWAP(win->area[0].swap_uv);
 777                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val);
 778
 779                 mask =  m_WIN0_BIC_COE_SEL |
 780                         m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
 781                         m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
 782                         m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
 783                         m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
 784                         m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
 785                         m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
 786                         m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
 787                 val =   v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
 788                         v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
 789                         v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
 790                         v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
 791                         v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
 792                         v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
 793                         v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
 794                         v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
 795                         v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
 796                         v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
 797                         v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
 798                         v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
 799                         v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
 800                         v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
 801                         v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
 802                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1+off, mask,val);
 803
 804                 val =   v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
 805                         v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
 806                 lcdc_writel(lcdc_dev, WIN0_VIR+off, val);
 807                 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off, win->area[0].y_addr);
 808                 lcdc_writel(lcdc_dev, WIN0_CBR_MST+off, win->area[0].uv_addr);*/
 809                 val =   v_WIN0_ACT_WIDTH(win->area[0].xact) |
 810                         v_WIN0_ACT_HEIGHT(win->area[0].yact);
 811                 lcdc_writel(lcdc_dev, WIN0_ACT_INFO+off, val);
 812
 813                 val =   v_WIN0_DSP_WIDTH(win->area[0].xsize) |
 814                         v_WIN0_DSP_HEIGHT(win->area[0].ysize);
 815                 lcdc_writel(lcdc_dev, WIN0_DSP_INFO+off, val);
 816
 817                 val =   v_WIN0_DSP_XST(win->area[0].dsp_stx) |
 818                         v_WIN0_DSP_YST(win->area[0].dsp_sty);
 819                 lcdc_writel(lcdc_dev, WIN0_DSP_ST+off, val);
 820
 821                 val =   v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
 822                         v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
 823                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB+off, val);
 824
 825                 val =   v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
 826                         v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
 827                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR+off, val);
 828                 if(win->alpha_en == 1)
 829                         rk3288_lcdc_alpha_cfg(dev_drv,win_id);
 830                 else{
 831                         mask = m_WIN0_SRC_ALPHA_EN;
 832                         val = v_WIN0_SRC_ALPHA_EN(0);
 833                         lcdc_msk_reg(lcdc_dev,WIN0_SRC_ALPHA_CTRL+off,mask,val);
 834                 }
 835                 /*offset*/
 836         }else{
 837                 mask = m_WIN0_EN;
 838                 val = v_WIN0_EN(win->state);
 839                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val);
 840         }
 841         return 0;
 842 }
 843
 844 static int rk3288_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv,int win_id)
 845 {
 846         struct lcdc_device *lcdc_dev =
 847             container_of(dev_drv, struct lcdc_device, driver);
 848         struct rk_lcdc_win *win = dev_drv->win[win_id];
 849         struct rk_screen *screen = dev_drv->cur_screen;
 850         unsigned int mask, val, off;
 851         off = (win_id-2) * 0x50;
 852         if((screen->y_mirror == 1)&&(win->area_num > 1)){
 853                 rk3288_lcdc_area_swap(win,win->area_num);
 854         }
 855
 856         if(win->state == 1){
 857                 mask =  m_WIN2_EN | m_WIN2_DATA_FMT | m_WIN2_RB_SWAP;
 858                 val  =  v_WIN2_EN(1) |
 859                         v_WIN2_DATA_FMT(win->area[0].fmt_cfg) |
 860                         v_WIN2_RB_SWAP(win->area[0].swap_rb);
 861                 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 862                 /*area 0*/
 863                 if(win->area[0].state == 1){
 864                         mask = m_WIN2_MST0_EN;
 865                         val  = v_WIN2_MST0_EN(win->area[0].state);
 866                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 867
 868                         mask = m_WIN2_VIR_STRIDE0;
 869                         val  = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
 870                         lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val);
 871
 872                         /*lcdc_writel(lcdc_dev,WIN2_MST0+off,win->area[0].y_addr);*/
 873                         val  =  v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
 874                                 v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
 875                         lcdc_writel(lcdc_dev,WIN2_DSP_INFO0+off,val);
 876                         val  =  v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
 877                                 v_WIN2_DSP_YST0(win->area[0].dsp_sty);
 878                         lcdc_writel(lcdc_dev,WIN2_DSP_ST0+off,val);
 879                 }else{
 880                         mask = m_WIN2_MST0_EN;
 881                         val  = v_WIN2_MST0_EN(0);
 882                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 883                 }
 884                 /*area 1*/
 885                 if(win->area[1].state == 1){
 886                         rk3288_win_area_check_var(win_id,1,&win->area[0],&win->area[1]);
 887
 888                         mask = m_WIN2_MST1_EN;
 889                         val  = v_WIN2_MST1_EN(win->area[1].state);
 890                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 891
 892                         mask = m_WIN2_VIR_STRIDE1;
 893                         val  = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
 894                         lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val);
 895
 896                         /*lcdc_writel(lcdc_dev,WIN2_MST1+off,win->area[1].y_addr);*/
 897                         val  =  v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
 898                                 v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
 899                         lcdc_writel(lcdc_dev,WIN2_DSP_INFO1+off,val);
 900                         val  =  v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
 901                                 v_WIN2_DSP_YST1(win->area[1].dsp_sty);
 902                         lcdc_writel(lcdc_dev,WIN2_DSP_ST1+off,val);
 903                 }else{
 904                         mask = m_WIN2_MST1_EN;
 905                         val  = v_WIN2_MST1_EN(0);
 906                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 907                 }
 908                 /*area 2*/
 909                 if(win->area[2].state == 1){
 910                         rk3288_win_area_check_var(win_id,2,&win->area[1],&win->area[2]);
 911
 912                         mask = m_WIN2_MST2_EN;
 913                         val  = v_WIN2_MST2_EN(win->area[2].state);
 914                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 915
 916                         mask = m_WIN2_VIR_STRIDE2;
 917                         val  = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
 918                         lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val);
 919
 920                         /*lcdc_writel(lcdc_dev,WIN2_MST2+off,win->area[2].y_addr);*/
 921                         val  =  v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
 922                                 v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
 923                         lcdc_writel(lcdc_dev,WIN2_DSP_INFO2+off,val);
 924                         val  =  v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
 925                                 v_WIN2_DSP_YST2(win->area[2].dsp_sty);
 926                         lcdc_writel(lcdc_dev,WIN2_DSP_ST2+off,val);
 927                 }else{
 928                         mask = m_WIN2_MST2_EN;
 929                         val  = v_WIN2_MST2_EN(0);
 930                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 931                 }
 932                 /*area 3*/
 933                 if(win->area[3].state == 1){
 934                         rk3288_win_area_check_var(win_id,3,&win->area[2],&win->area[3]);
 935
 936                         mask = m_WIN2_MST3_EN;
 937                         val  = v_WIN2_MST3_EN(win->area[3].state);
 938                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 939
 940                         mask = m_WIN2_VIR_STRIDE3;
 941                         val  = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
 942                         lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val);
 943
 944                         /*lcdc_writel(lcdc_dev,WIN2_MST3+off,win->area[3].y_addr);*/
 945                         val  =  v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
 946                                 v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
 947                         lcdc_writel(lcdc_dev,WIN2_DSP_INFO3+off,val);
 948                         val  =  v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
 949                                 v_WIN2_DSP_YST3(win->area[3].dsp_sty);
 950                         lcdc_writel(lcdc_dev,WIN2_DSP_ST3+off,val);
 951                 }else{
 952                         mask = m_WIN2_MST3_EN;
 953                         val  = v_WIN2_MST3_EN(0);
 954                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 955                 }
 956
 957                 if(win->alpha_en == 1)
 958                         rk3288_lcdc_alpha_cfg(dev_drv,win_id);
 959                 else{
 960                         mask = m_WIN2_SRC_ALPHA_EN;
 961                         val = v_WIN2_SRC_ALPHA_EN(0);
 962                         lcdc_msk_reg(lcdc_dev,WIN2_SRC_ALPHA_CTRL+off,mask,val);
 963                 }
 964         }else{
 965                 mask =  m_WIN2_EN | m_WIN2_MST0_EN |
 966                         m_WIN2_MST0_EN | m_WIN2_MST2_EN |
 967                         m_WIN2_MST3_EN;
 968                 val  =  v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
 969                         v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) |
 970                         v_WIN2_MST3_EN(0);
 971                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0+off, mask,val);
 972         }
 973         return 0;
 974 }
 975
 976 static int rk3288_lcdc_reg_update(struct rk_lcdc_driver *dev_drv)
 977 {
 978         struct lcdc_device *lcdc_dev =
 979             container_of(dev_drv, struct lcdc_device, driver);
 980         int timeout;
 981         unsigned long flags;
 982
 983         spin_lock(&lcdc_dev->reg_lock);
 984         if(likely(lcdc_dev->clk_on))
 985         {
 986                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
 987                              v_STANDBY_EN(lcdc_dev->standby));
 988                 rk3288_win_0_1_reg_update(dev_drv,0);
 989                 rk3288_win_0_1_reg_update(dev_drv,1);
 990                 rk3288_win_2_3_reg_update(dev_drv,2);
 991                 rk3288_win_2_3_reg_update(dev_drv,3);
 992                 /*rk3288_lcdc_post_cfg(dev_drv);*/
 993                 lcdc_cfg_done(lcdc_dev);
 994         }
 995         spin_unlock(&lcdc_dev->reg_lock);
 996
 997         /*if (dev_drv->wait_fs) {*/
 998         if (0){
 999                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1000                 init_completion(&dev_drv->frame_done);
1001                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1002                 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
1003                                                       msecs_to_jiffies
1004                                                       (dev_drv->cur_screen->ft +
1005                                                        5));
1006                 if (!timeout && (!dev_drv->frame_done.done)) {
1007                         dev_warn(lcdc_dev->dev, "wait for new frame start time out!\n");
1008                         return -ETIMEDOUT;
1009                 }
1010         }
1011         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1012         return 0;
1013
1014 }
1015
1016 static int rk3288_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1017 {
1018         if (lcdc_dev->driver.iommu_enabled)
1019                 memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0x330);
1020         else
1021                 memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0x1fc);
1022         return 0;
1023 }
1024 static int rk3288_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1025 {
1026         u32 mask,val;
1027         struct lcdc_device *lcdc_dev =
1028             container_of(dev_drv, struct lcdc_device, driver);
1029         spin_lock(&lcdc_dev->reg_lock);
1030         if (likely(lcdc_dev->clk_on)) {
1031                 mask = m_MMU_EN;
1032                 val = v_MMU_EN(1);
1033                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1034                 mask = m_AXI_MAX_OUTSTANDING_EN | m_AXI_OUTSTANDING_MAX_NUM;
1035                 val = v_AXI_OUTSTANDING_MAX_NUM(31) | v_AXI_MAX_OUTSTANDING_EN(1);
1036                 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1037         }
1038         spin_unlock(&lcdc_dev->reg_lock);
1039         return 0;
1040 }
1041
1042 static int rk3288_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
1043 {
1044 #ifdef CONFIG_RK_FPGA
1045         return 0;
1046 #endif
1047         int ret,fps;
1048         struct lcdc_device *lcdc_dev =
1049             container_of(dev_drv, struct lcdc_device, driver);
1050         struct rk_screen *screen = dev_drv->cur_screen;
1051
1052         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
1053         if (ret)
1054                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1055         lcdc_dev->pixclock =
1056                  div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1057         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1058
1059         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1060         screen->ft = 1000 / fps;
1061         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1062                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1063         return 0;
1064
1065 }
1066
1067 static int rk3288_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1068                                   u16 *yact, int *format, u32 *dsp_addr)
1069 {
1070         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1071                                                     struct lcdc_device, driver);
1072         u32 val;
1073
1074         spin_lock(&lcdc_dev->reg_lock);
1075
1076         val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1077         *xact = (val & m_WIN0_ACT_WIDTH) + 1;
1078         *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1;
1079
1080         val = lcdc_readl(lcdc_dev, WIN0_CTRL0);
1081         *format = (val & m_WIN0_DATA_FMT) >> 1;
1082         *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1083
1084         spin_unlock(&lcdc_dev->reg_lock);
1085
1086         return 0;
1087 }
1088
1089 static int rk3288_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1090                               int format, u16 xact, u16 yact, u16 xvir)
1091 {
1092         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1093                                                     struct lcdc_device, driver);
1094         u32 val, mask;
1095         int swap = (format == RGB888) ? 1 : 0;
1096
1097         mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP;
1098         val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap);
1099         lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1100
1101         lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE,
1102                         v_WIN0_VIR_STRIDE(xvir));
1103         lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) |
1104                     v_WIN0_ACT_HEIGHT(yact));
1105
1106         lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1107
1108         lcdc_cfg_done(lcdc_dev);
1109
1110         return 0;
1111 }
1112
1113 static int rk3288_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1114 {
1115         u16 face = 0;
1116         u32 v=0;
1117         struct lcdc_device *lcdc_dev =
1118             container_of(dev_drv, struct lcdc_device, driver);
1119         struct rk_screen *screen = dev_drv->cur_screen;
1120         u16 hsync_len = screen->mode.hsync_len;
1121         u16 left_margin = screen->mode.left_margin;
1122         u16 right_margin = screen->mode.right_margin;
1123         u16 vsync_len = screen->mode.vsync_len;
1124         u16 upper_margin = screen->mode.upper_margin;
1125         u16 lower_margin = screen->mode.lower_margin;
1126         u16 x_res = screen->mode.xres;
1127         u16 y_res = screen->mode.yres;
1128         u32 mask, val;
1129         u16 h_total,v_total;
1130
1131         h_total = hsync_len + left_margin  + x_res + right_margin;
1132         v_total = vsync_len + upper_margin + y_res + lower_margin;
1133
1134         screen->post_dsp_stx = x_res * (100 - screen->overscan.left) / 200;
1135         screen->post_dsp_sty = y_res * (100 - screen->overscan.top) / 200;
1136         screen->post_xsize = x_res * (screen->overscan.left + screen->overscan.right) / 200;
1137         screen->post_ysize = y_res * (screen->overscan.top + screen->overscan.bottom) / 200;
1138
1139         spin_lock(&lcdc_dev->reg_lock);
1140         if (likely(lcdc_dev->clk_on)) {
1141                 switch (screen->face) {
1142                 case OUT_P565:
1143                         face = OUT_P565;
1144                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1145                             m_DITHER_DOWN_SEL;
1146                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1147                             v_DITHER_DOWN_SEL(1);
1148                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1149                         break;
1150                 case OUT_P666:
1151                         face = OUT_P666;
1152                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1153                             m_DITHER_DOWN_SEL;
1154                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1155                             v_DITHER_DOWN_SEL(1);
1156                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1157                         break;
1158                 case OUT_D888_P565:
1159                         face = OUT_P888;
1160                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1161                             m_DITHER_DOWN_SEL;
1162                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1163                             v_DITHER_DOWN_SEL(1);
1164                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1165                         break;
1166                 case OUT_D888_P666:
1167                         face = OUT_P888;
1168                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1169                             m_DITHER_DOWN_SEL;
1170                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1171                             v_DITHER_DOWN_SEL(1);
1172                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1173                         break;
1174                 case OUT_P888:
1175                         face = OUT_P888;
1176                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1177                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1178                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1179                         break;
1180                 default:
1181                         dev_err(lcdc_dev->dev,"un supported interface!\n");
1182                         break;
1183                 }
1184                 switch(screen->type){
1185                 case SCREEN_RGB:
1186                 case SCREEN_LVDS:
1187                 case SCREEN_DUAL_LVDS:
1188                         mask = m_RGB_OUT_EN;
1189                         val = v_RGB_OUT_EN(1);
1190                         v = 1 << (3+16);
1191                         v |= (lcdc_dev->id << 3);
1192                         break;
1193                 case SCREEN_HDMI:
1194                         face = OUT_RGB_AAA;
1195                         mask = m_HDMI_OUT_EN;
1196                         val = v_HDMI_OUT_EN(1);
1197                         break;
1198                 case SCREEN_MIPI:
1199                         mask = m_MIPI_OUT_EN;
1200                         val = v_MIPI_OUT_EN(1);
1201                         break;
1202                 case SCREEN_DUAL_MIPI:
1203                         mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN;
1204                         val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1);
1205                         break;
1206                 case SCREEN_EDP:
1207                         face = OUT_RGB_AAA;  /*RGB AAA output*/
1208                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1209                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1210                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1211                         mask = m_EDP_OUT_EN;
1212                         val = v_EDP_OUT_EN(1);
1213                         break;
1214                 }
1215                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1216 #ifndef CONFIG_RK_FPGA
1217                 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
1218 #endif
1219                 mask = m_DSP_OUT_MODE | m_DSP_HSYNC_POL | m_DSP_VSYNC_POL |
1220                        m_DSP_DEN_POL | m_DSP_DCLK_POL | m_DSP_BG_SWAP |
1221                        m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1222                        m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1223                        m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
1224                 val = v_DSP_OUT_MODE(face) | v_DSP_HSYNC_POL(screen->pin_hsync) |
1225                       v_DSP_VSYNC_POL(screen->pin_vsync) |
1226                       v_DSP_DEN_POL(screen->pin_den) | v_DSP_DCLK_POL(screen->pin_dclk) |
1227                       v_DSP_BG_SWAP(screen->swap_gb) | v_DSP_RB_SWAP(screen->swap_rb) |
1228                       v_DSP_RG_SWAP(screen->swap_rg) |
1229                       v_DSP_DELTA_SWAP(screen->swap_delta) |
1230                       v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1231                       v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1232                       v_DSP_X_MIR_EN(screen->x_mirror) | v_DSP_Y_MIR_EN(screen->y_mirror);
1233                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1234
1235                 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1236                 val  = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) | v_DSP_BG_RED(0);
1237                 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1238
1239                 mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1240                 val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1241                 lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1242
1243                 mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1244                 val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1245                     v_DSP_HACT_ST(hsync_len + left_margin);
1246                 lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1247
1248                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1249                 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1250                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1251
1252                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1253                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1254                     v_DSP_VACT_ST(vsync_len + upper_margin);
1255                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1256
1257                 rk3288_lcdc_post_cfg(dev_drv);
1258         }
1259         spin_unlock(&lcdc_dev->reg_lock);
1260         rk3288_lcdc_set_dclk(dev_drv);
1261         if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1262             dev_drv->trsm_ops->enable)
1263                 dev_drv->trsm_ops->enable();
1264         if (screen->init)
1265                 screen->init();
1266
1267         return 0;
1268 }
1269
1270 /*enable layer,open:1,enable;0 disable*/
1271 static int win0_open(struct lcdc_device *lcdc_dev, bool open)
1272 {
1273         spin_lock(&lcdc_dev->reg_lock);
1274         if (likely(lcdc_dev->clk_on)) {
1275                 if (open) {
1276                         if (!lcdc_dev->atv_layer_cnt) {
1277                                 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1278                                 lcdc_dev->standby = 0;
1279                         }
1280                         lcdc_dev->atv_layer_cnt++;
1281                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1282                         lcdc_dev->atv_layer_cnt--;
1283                 }
1284                 lcdc_dev->driver.win[0]->state = open;
1285                 if (!lcdc_dev->atv_layer_cnt) {
1286                         dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1287                         lcdc_dev->standby = 1;
1288                 }
1289         }
1290         spin_unlock(&lcdc_dev->reg_lock);
1291
1292         return 0;
1293 }
1294
1295 static int win1_open(struct lcdc_device *lcdc_dev, bool open)
1296 {
1297         spin_lock(&lcdc_dev->reg_lock);
1298         if (likely(lcdc_dev->clk_on)) {
1299                 if (open) {
1300                         if (!lcdc_dev->atv_layer_cnt) {
1301                                 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1302                                 lcdc_dev->standby = 0;
1303                         }
1304                         lcdc_dev->atv_layer_cnt++;
1305                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1306                         lcdc_dev->atv_layer_cnt--;
1307                 }
1308                 lcdc_dev->driver.win[1]->state = open;
1309
1310                 /*if no layer used,disable lcdc*/
1311                 if (!lcdc_dev->atv_layer_cnt) {
1312                         dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1313                         lcdc_dev->standby = 1;
1314                 }
1315         }
1316         spin_unlock(&lcdc_dev->reg_lock);
1317
1318         return 0;
1319 }
1320
1321 static int win2_open(struct lcdc_device *lcdc_dev, bool open)
1322 {
1323         spin_lock(&lcdc_dev->reg_lock);
1324         if (likely(lcdc_dev->clk_on)) {
1325                 if (open) {
1326                         if (!lcdc_dev->atv_layer_cnt) {
1327                                 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1328                                 lcdc_dev->standby = 0;
1329                         }
1330                         lcdc_dev->atv_layer_cnt++;
1331                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1332                         lcdc_dev->atv_layer_cnt--;
1333                 }
1334                 lcdc_dev->driver.win[2]->state = open;
1335
1336                 /*if no layer used,disable lcdc*/
1337                 if (!lcdc_dev->atv_layer_cnt) {
1338                         dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1339                         lcdc_dev->standby = 1;
1340                 }
1341         }
1342         spin_unlock(&lcdc_dev->reg_lock);
1343
1344         return 0;
1345 }
1346
1347 static int win3_open(struct lcdc_device *lcdc_dev, bool open)
1348 {
1349         spin_lock(&lcdc_dev->reg_lock);
1350         if (likely(lcdc_dev->clk_on)) {
1351                 if (open) {
1352                         if (!lcdc_dev->atv_layer_cnt) {
1353                                 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1354                                 lcdc_dev->standby = 0;
1355                         }
1356                         lcdc_dev->atv_layer_cnt++;
1357                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1358                         lcdc_dev->atv_layer_cnt--;
1359                 }
1360                 lcdc_dev->driver.win[3]->state = open;
1361
1362                 /*if no layer used,disable lcdc*/
1363                 if (!lcdc_dev->atv_layer_cnt) {
1364                         dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1365                         lcdc_dev->standby = 1;
1366                 }
1367         }
1368         spin_unlock(&lcdc_dev->reg_lock);
1369
1370         return 0;
1371 }
1372 static int rk3288_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1373 {
1374         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1375                                         struct lcdc_device, driver);
1376         u32 mask,val;
1377         struct rk_screen *screen = dev_drv->cur_screen;
1378
1379         mask = m_FS_INTR_CLR | m_FS_INTR_EN | m_LINE_FLAG_INTR_CLR |
1380                             m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_CLR |
1381                             m_BUS_ERROR_INTR_EN | m_DSP_LINE_FLAG_NUM;
1382         val = v_FS_INTR_CLR(1) | v_FS_INTR_EN(1) | v_LINE_FLAG_INTR_CLR(1) |
1383             v_LINE_FLAG_INTR_EN(1) | v_BUS_ERROR_INTR_CLR(1) | v_BUS_ERROR_INTR_EN(0) |
1384             v_DSP_LINE_FLAG_NUM(screen->mode.vsync_len + screen->mode.upper_margin +
1385             screen->mode.yres);
1386         lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
1387 #ifdef LCDC_IRQ_EMPTY_DEBUG
1388                  mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN | m_WIN2_EMPTY_INTR_EN |
1389                          m_WIN3_EMPTY_INTR_EN |m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
1390                          m_PWM_GEN_INTR_EN;
1391                  val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) | v_WIN2_EMPTY_INTR_EN(1) |
1392                          v_WIN3_EMPTY_INTR_EN(1)| v_HWC_EMPTY_INTR_EN(1) | v_POST_BUF_EMPTY_INTR_EN(1) |
1393                          v_PWM_GEN_INTR_EN(1);
1394                  lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
1395 #endif
1396         return 0;
1397 }
1398
1399 static int rk3288_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1400                             bool open)
1401 {
1402         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1403                                         struct lcdc_device, driver);
1404         int sys_status = (dev_drv->id == 0) ?
1405                         SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
1406
1407         /*enable clk,when first layer open */
1408         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1409                 rockchip_set_system_status(sys_status);
1410                 rk3288_lcdc_pre_init(dev_drv);
1411                 rk3288_lcdc_clk_enable(lcdc_dev);
1412                 rk3288_lcdc_enable_irq(dev_drv);
1413 #if defined(CONFIG_ROCKCHIP_IOMMU)
1414                 if (dev_drv->iommu_enabled) {
1415                         if (!dev_drv->mmu_dev) {
1416                                 dev_drv->mmu_dev =
1417                                         rk_fb_get_sysmmu_device_by_compatible(dev_drv->mmu_dts_name);
1418                                 if (dev_drv->mmu_dev) {
1419                                         rk_fb_platform_set_sysmmu(dev_drv->mmu_dev,
1420                                                                   dev_drv->dev);
1421                                 } else {
1422                                         dev_err(dev_drv->dev,
1423                                                 "failed to get rockchip iommu device\n");
1424                                         return -1;
1425                                 }
1426                         }
1427                         if (dev_drv->mmu_dev)
1428                                 rockchip_iovmm_activate(dev_drv->dev);
1429                 }
1430 #endif
1431                 rk3288_lcdc_reg_restore(lcdc_dev);
1432                 if (dev_drv->iommu_enabled)
1433                         rk3288_lcdc_mmu_en(dev_drv);
1434                 if ((support_uboot_display()&&(lcdc_dev->prop == PRMRY))) {
1435                         rk3288_lcdc_set_dclk(dev_drv);
1436                         rk3288_lcdc_enable_irq(dev_drv);
1437                 } else {
1438                         rk3288_load_screen(dev_drv, 1);
1439                 }
1440                 if (dev_drv->bcsh.enable)
1441                         rk3288_lcdc_set_bcsh(dev_drv, 1);
1442                 spin_lock(&lcdc_dev->reg_lock);
1443                 if (dev_drv->cur_screen->dsp_lut)
1444                         rk3288_lcdc_set_lut(dev_drv);
1445                 spin_unlock(&lcdc_dev->reg_lock);
1446         }
1447
1448         if (win_id == 0)
1449                 win0_open(lcdc_dev, open);
1450         else if (win_id == 1)
1451                 win1_open(lcdc_dev, open);
1452         else if (win_id == 2)
1453                 win2_open(lcdc_dev, open);
1454         else if (win_id == 3)
1455                 win3_open(lcdc_dev, open);
1456         else
1457                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1458
1459         /* when all layer closed,disable clk */
1460         if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1461                 rk3288_lcdc_disable_irq(lcdc_dev);
1462                 rk3288_lcdc_reg_update(dev_drv);
1463 #if defined(CONFIG_ROCKCHIP_IOMMU)
1464                 if (dev_drv->iommu_enabled) {
1465                         if (dev_drv->mmu_dev)
1466                                 rockchip_iovmm_deactivate(dev_drv->dev);
1467                 }
1468 #endif
1469                 rk3288_lcdc_clk_disable(lcdc_dev);
1470                 rockchip_clear_system_status(sys_status);
1471         }
1472
1473         return 0;
1474 }
1475
1476 static int win0_display(struct lcdc_device *lcdc_dev,
1477                         struct rk_lcdc_win *win)
1478 {
1479         u32 y_addr;
1480         u32 uv_addr;
1481         y_addr = win->area[0].smem_start+win->area[0].y_offset;/*win->smem_start + win->y_offset;*/
1482         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1483         DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n",
1484             lcdc_dev->id, __func__, y_addr, uv_addr,win->area[0].y_offset);
1485         spin_lock(&lcdc_dev->reg_lock);
1486         if (likely(lcdc_dev->clk_on)) {
1487                 win->area[0].y_addr = y_addr;
1488                 win->area[0].uv_addr = uv_addr;
1489                 lcdc_writel(lcdc_dev, WIN0_YRGB_MST, win->area[0].y_addr);
1490                 lcdc_writel(lcdc_dev, WIN0_CBR_MST, win->area[0].uv_addr);
1491                 /*lcdc_cfg_done(lcdc_dev);*/
1492         }
1493         spin_unlock(&lcdc_dev->reg_lock);
1494
1495         return 0;
1496
1497 }
1498
1499 static int win1_display(struct lcdc_device *lcdc_dev,
1500                         struct rk_lcdc_win *win)
1501 {
1502         u32 y_addr;
1503         u32 uv_addr;
1504         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1505         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1506         DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",
1507             lcdc_dev->id, __func__, y_addr, uv_addr);
1508
1509         spin_lock(&lcdc_dev->reg_lock);
1510         if (likely(lcdc_dev->clk_on)) {
1511                 win->area[0].y_addr = y_addr;
1512                 win->area[0].uv_addr = uv_addr;
1513                 lcdc_writel(lcdc_dev, WIN1_YRGB_MST, win->area[0].y_addr);
1514                 lcdc_writel(lcdc_dev, WIN1_CBR_MST, win->area[0].uv_addr);
1515         }
1516         spin_unlock(&lcdc_dev->reg_lock);
1517
1518
1519         return 0;
1520 }
1521
1522 static int win2_display(struct lcdc_device *lcdc_dev,
1523                         struct rk_lcdc_win *win)
1524 {
1525         u32 i,y_addr;
1526         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1527         DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n",
1528             lcdc_dev->id, __func__, y_addr);
1529
1530         spin_lock(&lcdc_dev->reg_lock);
1531         if (likely(lcdc_dev->clk_on)){
1532                 for(i=0;i<win->area_num;i++)
1533                         win->area[i].y_addr =
1534                                 win->area[i].smem_start + win->area[i].y_offset;
1535                         lcdc_writel(lcdc_dev,WIN2_MST0,win->area[0].y_addr);
1536                         lcdc_writel(lcdc_dev,WIN2_MST1,win->area[1].y_addr);
1537                         lcdc_writel(lcdc_dev,WIN2_MST2,win->area[2].y_addr);
1538                         lcdc_writel(lcdc_dev,WIN2_MST3,win->area[3].y_addr);
1539         }
1540         spin_unlock(&lcdc_dev->reg_lock);
1541         return 0;
1542 }
1543
1544 static int win3_display(struct lcdc_device *lcdc_dev,
1545                         struct rk_lcdc_win *win)
1546 {
1547         u32 i,y_addr;
1548         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1549         DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n",
1550             lcdc_dev->id, __func__, y_addr);
1551
1552         spin_lock(&lcdc_dev->reg_lock);
1553         if (likely(lcdc_dev->clk_on)){
1554                 for(i=0;i<win->area_num;i++)
1555                         win->area[i].y_addr =
1556                                 win->area[i].smem_start + win->area[i].y_offset;
1557                         lcdc_writel(lcdc_dev,WIN3_MST0,win->area[0].y_addr);
1558                         lcdc_writel(lcdc_dev,WIN3_MST1,win->area[1].y_addr);
1559                         lcdc_writel(lcdc_dev,WIN3_MST2,win->area[2].y_addr);
1560                         lcdc_writel(lcdc_dev,WIN3_MST3,win->area[3].y_addr);
1561                 }
1562         spin_unlock(&lcdc_dev->reg_lock);
1563         return 0;
1564 }
1565
1566 static int rk3288_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
1567 {
1568         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1569                                 struct lcdc_device, driver);
1570         struct rk_lcdc_win *win = NULL;
1571         struct rk_screen *screen = dev_drv->cur_screen;
1572
1573 #if defined(WAIT_FOR_SYNC)
1574         int timeout;
1575         unsigned long flags;
1576 #endif
1577         win = dev_drv->win[win_id];
1578         if (!screen) {
1579                 dev_err(dev_drv->dev, "screen is null!\n");
1580                 return -ENOENT;
1581         }
1582         if(win_id == 0){
1583                 win0_display(lcdc_dev, win);
1584         }else if(win_id == 1){
1585                 win1_display(lcdc_dev, win);
1586         }else if(win_id == 2){
1587                 win2_display(lcdc_dev, win);
1588         }else if(win_id == 3){
1589                 win3_display(lcdc_dev, win);
1590         }else{
1591                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1592                 return -EINVAL;
1593         }
1594
1595         /*this is the first frame of the system ,enable frame start interrupt */
1596         if ((dev_drv->first_frame)) {
1597                 dev_drv->first_frame = 0;
1598                 rk3288_lcdc_enable_irq(dev_drv);
1599         }
1600 #if defined(WAIT_FOR_SYNC)
1601         spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1602         init_completion(&dev_drv->frame_done);
1603         spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1604         timeout = wait_for_completion_timeout(&dev_drv->frame_done,
1605                                               msecs_to_jiffies(dev_drv->
1606                                                                cur_screen->ft +
1607                                                                5));
1608         if (!timeout && (!dev_drv->frame_done.done)) {
1609                 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
1610                 return -ETIMEDOUT;
1611         }
1612 #endif
1613         return 0;
1614 }
1615
1616 static int rk3288_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
1617 {
1618         u16 srcW;
1619         u16 srcH;
1620         u16 dstW;
1621         u16 dstH;
1622         u16 yrgb_srcW;
1623         u16 yrgb_srcH;
1624         u16 yrgb_dstW;
1625         u16 yrgb_dstH;
1626         u32 yrgb_vScaleDnMult;
1627         u32 yrgb_xscl_factor;
1628         u32 yrgb_yscl_factor;
1629         u8  yrgb_vsd_bil_gt2=0;
1630         u8  yrgb_vsd_bil_gt4=0;
1631
1632         u16 cbcr_srcW;
1633         u16 cbcr_srcH;
1634         u16 cbcr_dstW;
1635         u16 cbcr_dstH;
1636         u32 cbcr_vScaleDnMult;
1637         u32 cbcr_xscl_factor;
1638         u32 cbcr_yscl_factor;
1639         u8  cbcr_vsd_bil_gt2=0;
1640         u8  cbcr_vsd_bil_gt4=0;
1641         u8  yuv_fmt=0;
1642
1643
1644         srcW = win->area[0].xact;
1645         srcH = win->area[0].yact;
1646         dstW = win->area[0].xsize;
1647         dstH = win->area[0].ysize;
1648
1649         /*yrgb scl mode*/
1650         yrgb_srcW = srcW;
1651         yrgb_srcH = srcH;
1652         yrgb_dstW = dstW;
1653         yrgb_dstH = dstH;
1654         if ((yrgb_dstW*8 <= yrgb_srcW) || (yrgb_dstH*8 <= yrgb_srcH)) {
1655                 pr_err("ERROR: yrgb scale exceed 8,"
1656                        "srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
1657                        yrgb_srcW,yrgb_srcH,yrgb_dstW,yrgb_dstH);
1658         }
1659         if(yrgb_srcW < yrgb_dstW){
1660                 win->yrgb_hor_scl_mode = SCALE_UP;
1661         }else if(yrgb_srcW > yrgb_dstW){
1662                 win->yrgb_hor_scl_mode = SCALE_DOWN;
1663         }else{
1664                 win->yrgb_hor_scl_mode = SCALE_NONE;
1665         }
1666
1667         if(yrgb_srcH < yrgb_dstH){
1668                 win->yrgb_ver_scl_mode = SCALE_UP;
1669         }else if (yrgb_srcH  > yrgb_dstH){
1670                 win->yrgb_ver_scl_mode = SCALE_DOWN;
1671         }else{
1672                 win->yrgb_ver_scl_mode = SCALE_NONE;
1673         }
1674
1675         /*cbcr scl mode*/
1676         switch (win->area[0].format) {
1677         case YUV422:
1678         case YUV422_A:
1679                 cbcr_srcW = srcW/2;
1680                 cbcr_dstW = dstW;
1681                 cbcr_srcH = srcH;
1682                 cbcr_dstH = dstH;
1683                 yuv_fmt = 1;
1684                 break;
1685         case YUV420:
1686         case YUV420_A:
1687                 cbcr_srcW = srcW/2;
1688                 cbcr_dstW = dstW;
1689                 cbcr_srcH = srcH/2;
1690                 cbcr_dstH = dstH;
1691                 yuv_fmt = 1;
1692                 break;
1693         case YUV444:
1694         case YUV444_A:
1695                 cbcr_srcW = srcW;
1696                 cbcr_dstW = dstW;
1697                 cbcr_srcH = srcH;
1698                 cbcr_dstH = dstH;
1699                 yuv_fmt = 1;
1700                 break;
1701         default:
1702                 cbcr_srcW = 0;
1703                 cbcr_dstW = 0;
1704                 cbcr_srcH = 0;
1705                 cbcr_dstH = 0;
1706                 yuv_fmt = 0;
1707                 break;
1708         }
1709         if (yuv_fmt) {
1710                 if ((cbcr_dstW*8 <= cbcr_srcW) || (cbcr_dstH*8 <= cbcr_srcH)) {
1711                         pr_err("ERROR: cbcr scale exceed 8,"
1712                        "srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
1713                        cbcr_srcW,cbcr_srcH,cbcr_dstW,cbcr_dstH);
1714                 }
1715         }
1716
1717         if(cbcr_srcW < cbcr_dstW){
1718                 win->cbr_hor_scl_mode = SCALE_UP;
1719         }else if(cbcr_srcW > cbcr_dstW){
1720                 win->cbr_hor_scl_mode = SCALE_DOWN;
1721         }else{
1722                 win->cbr_hor_scl_mode = SCALE_NONE;
1723         }
1724
1725         if(cbcr_srcH < cbcr_dstH){
1726                 win->cbr_ver_scl_mode = SCALE_UP;
1727         }else if(cbcr_srcH > cbcr_dstH){
1728                 win->cbr_ver_scl_mode = SCALE_DOWN;
1729         }else{
1730                 win->cbr_ver_scl_mode = SCALE_NONE;
1731         }
1732         DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
1733                "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
1734                "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
1735                 ,srcW,srcH,dstW,dstH,yrgb_srcW,yrgb_srcH,yrgb_dstW,
1736                 yrgb_dstH,win->yrgb_hor_scl_mode,win->yrgb_ver_scl_mode,
1737                 cbcr_srcW,cbcr_srcH,cbcr_dstW,cbcr_dstH,
1738                 win->cbr_hor_scl_mode,win->cbr_ver_scl_mode);
1739
1740     /*line buffer mode*/
1741         if ((win->area[0].format == YUV422) ||
1742             (win->area[0].format == YUV420) ||
1743             (win->area[0].format == YUV422_A) ||
1744             (win->area[0].format == YUV420_A)) {
1745                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
1746                         if ((cbcr_dstW > 3840) || (cbcr_dstW == 0)) {
1747                                 pr_err("ERROR cbcr_dstW = %d\n",cbcr_dstW);
1748                         } else if (cbcr_dstW > 2560) {
1749                                 win->win_lb_mode = LB_RGB_3840X2;
1750                         } else if (cbcr_dstW > 1920) {
1751                                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
1752                                         if(yrgb_dstW > 3840){
1753                                                 pr_err("ERROR yrgb_dst_width exceeds 3840\n");
1754                                         }else if(yrgb_dstW > 2560){
1755                                                 win->win_lb_mode = LB_RGB_3840X2;
1756                                         }else if(yrgb_dstW > 1920){
1757                                                 win->win_lb_mode = LB_RGB_2560X4;
1758                                         }else{
1759                                                 pr_err("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n");
1760                                         }
1761                                 }
1762                         } else if (cbcr_dstW > 1280) {
1763                                 win->win_lb_mode = LB_YUV_3840X5;
1764                         } else {
1765                                 win->win_lb_mode = LB_YUV_2560X8;
1766                         }
1767                 } else { /*SCALE_UP or SCALE_NONE*/
1768                         if ((cbcr_srcW > 3840) || (cbcr_srcW == 0)) {
1769                                 pr_err("ERROR cbcr_srcW = %d\n",cbcr_srcW);
1770                         }else if(cbcr_srcW > 2560){
1771                                 win->win_lb_mode = LB_RGB_3840X2;
1772                         }else if(cbcr_srcW > 1920){
1773                                 if(win->yrgb_hor_scl_mode == SCALE_DOWN){
1774                                         if(yrgb_dstW > 3840){
1775                                                 pr_err("ERROR yrgb_dst_width exceeds 3840\n");
1776                                         }else if(yrgb_dstW > 2560){
1777                                                 win->win_lb_mode = LB_RGB_3840X2;
1778                                         }else if(yrgb_dstW > 1920){
1779                                                 win->win_lb_mode = LB_RGB_2560X4;
1780                                         }else{
1781                                                 pr_err("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n");
1782                                         }
1783                                 }
1784                         }else if(cbcr_srcW > 1280){
1785                                  win->win_lb_mode = LB_YUV_3840X5;
1786                         }else{
1787                                 win->win_lb_mode = LB_YUV_2560X8;
1788                         }
1789                 }
1790         }else {
1791                 if(win->yrgb_hor_scl_mode == SCALE_DOWN){
1792                         if ((yrgb_dstW > 3840) || (yrgb_dstW == 0)) {
1793                                 pr_err("ERROR yrgb_dstW = %d\n",yrgb_dstW);
1794                         }else if(yrgb_dstW > 2560){
1795                                 win->win_lb_mode = LB_RGB_3840X2;
1796                         }else if(yrgb_dstW > 1920){
1797                                 win->win_lb_mode = LB_RGB_2560X4;
1798                         }else if(yrgb_dstW > 1280){
1799                                 win->win_lb_mode = LB_RGB_1920X5;
1800                         }else{
1801                                 win->win_lb_mode = LB_RGB_1280X8;
1802                         }
1803                 }else{ /*SCALE_UP or SCALE_NONE*/
1804                         if ((yrgb_srcW > 3840) || (yrgb_srcW == 0)) {
1805                                 pr_err("ERROR yrgb_srcW = %d\n",yrgb_srcW);
1806                         }else if(yrgb_srcW > 2560){
1807                                 win->win_lb_mode = LB_RGB_3840X2;
1808                         }else if(yrgb_srcW > 1920){
1809                                 win->win_lb_mode = LB_RGB_2560X4;
1810                         }else if(yrgb_srcW > 1280){
1811                                 win->win_lb_mode = LB_RGB_1920X5;
1812                         }else{
1813                                 win->win_lb_mode = LB_RGB_1280X8;
1814                         }
1815                 }
1816         }
1817         DBG(1,"win->win_lb_mode = %d;\n",win->win_lb_mode);
1818
1819         /*vsd/vsu scale ALGORITHM*/
1820         win->yrgb_hsd_mode = SCALE_DOWN_BIL;/*not to specify*/
1821         win->cbr_hsd_mode  = SCALE_DOWN_BIL;/*not to specify*/
1822         win->yrgb_vsd_mode = SCALE_DOWN_BIL;/*not to specify*/
1823         win->cbr_vsd_mode  = SCALE_DOWN_BIL;/*not to specify*/
1824         switch(win->win_lb_mode){
1825             case LB_YUV_3840X5:
1826             case LB_YUV_2560X8:
1827             case LB_RGB_1920X5:
1828             case LB_RGB_1280X8:
1829                 win->yrgb_vsu_mode = SCALE_UP_BIC;
1830                 win->cbr_vsu_mode  = SCALE_UP_BIC;
1831                 break;
1832             case LB_RGB_3840X2:
1833                 if(win->yrgb_ver_scl_mode != SCALE_NONE) {
1834                     pr_err("ERROR : not allow yrgb ver scale\n");
1835                 }
1836                 if(win->cbr_ver_scl_mode != SCALE_NONE) {
1837                     pr_err("ERROR : not allow cbcr ver scale\n");
1838                 }
1839                 break;
1840             case LB_RGB_2560X4:
1841                 win->yrgb_vsu_mode = SCALE_UP_BIL;
1842                 win->cbr_vsu_mode  = SCALE_UP_BIL;
1843                 break;
1844             default:
1845                 printk(KERN_WARNING "%s:un supported win_lb_mode:%d\n",
1846                         __func__,win->win_lb_mode);
1847                 break;
1848         }
1849         DBG(1,"yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
1850                win->yrgb_hsd_mode,win->yrgb_vsd_mode,win->yrgb_vsu_mode,
1851                win->cbr_hsd_mode,win->cbr_vsd_mode,win->cbr_vsu_mode);
1852
1853         /*SCALE FACTOR*/
1854
1855         /*(1.1)YRGB HOR SCALE FACTOR*/
1856         switch(win->yrgb_hor_scl_mode){
1857         case SCALE_NONE:
1858                 yrgb_xscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
1859                 break;
1860         case SCALE_UP  :
1861                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
1862                 break;
1863         case SCALE_DOWN:
1864                 switch(win->yrgb_hsd_mode)
1865                 {
1866                 case SCALE_DOWN_BIL:
1867                         yrgb_xscl_factor = GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
1868                         break;
1869                 case SCALE_DOWN_AVG:
1870                         yrgb_xscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
1871                         break;
1872                 default :
1873                         printk(KERN_WARNING "%s:un supported yrgb_hsd_mode:%d\n",
1874                                 __func__,win->yrgb_hsd_mode);
1875                         break;
1876                 }
1877                 break;
1878         default :
1879                 printk(KERN_WARNING "%s:un supported yrgb_hor_scl_mode:%d\n",
1880                                 __func__,win->yrgb_hor_scl_mode);
1881             break;
1882         } /*win->yrgb_hor_scl_mode*/
1883
1884         /*(1.2)YRGB VER SCALE FACTOR*/
1885         switch(win->yrgb_ver_scl_mode)
1886         {
1887         case SCALE_NONE:
1888                 yrgb_yscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
1889                  break;
1890         case SCALE_UP  :
1891                 switch(win->yrgb_vsu_mode)
1892                 {
1893                 case SCALE_UP_BIL:
1894                         yrgb_yscl_factor = GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
1895                         break;
1896                 case SCALE_UP_BIC:
1897                         if(yrgb_srcH < 3){
1898                                 pr_err("yrgb_srcH should be greater than 3 !!!\n");
1899                         }
1900                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH, yrgb_dstH);
1901                         break;
1902                 default :
1903                         printk(KERN_WARNING "%s:un supported yrgb_vsu_mode:%d\n",
1904                                 __func__,win->yrgb_vsu_mode);
1905                         break;
1906             }
1907             break;
1908         case SCALE_DOWN:
1909                 switch(win->yrgb_vsd_mode)
1910                 {
1911                 case SCALE_DOWN_BIL:
1912                         yrgb_vScaleDnMult = getHardWareVSkipLines(yrgb_srcH, yrgb_dstH);
1913                         yrgb_yscl_factor  = GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH, yrgb_vScaleDnMult);
1914                         if(yrgb_vScaleDnMult == 4){
1915                                 yrgb_vsd_bil_gt4 = 1;
1916                                 yrgb_vsd_bil_gt2 = 0;
1917                         }else if(yrgb_vScaleDnMult == 2){
1918                                 yrgb_vsd_bil_gt4 = 0;
1919                                 yrgb_vsd_bil_gt2 = 1;
1920                         }else{
1921                                 yrgb_vsd_bil_gt4 = 0;
1922                                 yrgb_vsd_bil_gt2 = 0;
1923                         }
1924                         break;
1925                 case SCALE_DOWN_AVG:
1926                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH, yrgb_dstH);
1927                         break;
1928                 default:
1929                         printk(KERN_WARNING "%s:un supported yrgb_vsd_mode:%d\n",
1930                                 __func__,win->yrgb_vsd_mode);
1931                         break;
1932                 } /*win->yrgb_vsd_mode*/
1933                 break;
1934         default :
1935                 printk(KERN_WARNING "%s:un supported yrgb_ver_scl_mode:%d\n",
1936                         __func__,win->yrgb_ver_scl_mode);
1937                 break;
1938         }
1939         win->scale_yrgb_x = yrgb_xscl_factor;
1940         win->scale_yrgb_y = yrgb_yscl_factor;
1941         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
1942         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
1943         DBG(1,"yrgb:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",yrgb_xscl_factor,
1944                 yrgb_yscl_factor,yrgb_vsd_bil_gt4,yrgb_vsd_bil_gt2);
1945
1946         /*(2.1)CBCR HOR SCALE FACTOR*/
1947         switch(win->cbr_hor_scl_mode)
1948         {
1949         case SCALE_NONE:
1950                 cbcr_xscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
1951                 break;
1952         case SCALE_UP  :
1953                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
1954                 break;
1955         case SCALE_DOWN:
1956                 switch(win->cbr_hsd_mode)
1957                 {
1958                 case SCALE_DOWN_BIL:
1959                         cbcr_xscl_factor = GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
1960                         break;
1961                 case SCALE_DOWN_AVG:
1962                         cbcr_xscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
1963                         break;
1964                 default :
1965                         printk(KERN_WARNING "%s:un supported cbr_hsd_mode:%d\n",
1966                                 __func__,win->cbr_hsd_mode);
1967                         break;
1968                 }
1969                 break;
1970         default :
1971                 printk(KERN_WARNING "%s:un supported cbr_hor_scl_mode:%d\n",
1972                         __func__,win->cbr_hor_scl_mode);
1973                 break;
1974         } /*win->cbr_hor_scl_mode*/
1975
1976         /*(2.2)CBCR VER SCALE FACTOR*/
1977         switch(win->cbr_ver_scl_mode)
1978         {
1979         case SCALE_NONE:
1980                 cbcr_yscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
1981                 break;
1982         case SCALE_UP  :
1983                 switch(win->cbr_vsu_mode)
1984                 {
1985                 case SCALE_UP_BIL:
1986                         cbcr_yscl_factor = GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
1987                         break;
1988                 case SCALE_UP_BIC:
1989                         if(cbcr_srcH < 3) {
1990                                 pr_err("cbcr_srcH should be greater than 3 !!!\n");
1991                         }
1992                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH, cbcr_dstH);
1993                         break;
1994                 default :
1995                         printk(KERN_WARNING "%s:un supported cbr_vsu_mode:%d\n",
1996                                 __func__,win->cbr_vsu_mode);
1997                         break;
1998                 }
1999                 break;
2000         case SCALE_DOWN:
2001                 switch(win->cbr_vsd_mode)
2002                 {
2003                 case SCALE_DOWN_BIL:
2004                         cbcr_vScaleDnMult = getHardWareVSkipLines(cbcr_srcH, cbcr_dstH);
2005                         cbcr_yscl_factor  = GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH, cbcr_vScaleDnMult);
2006                         if(cbcr_vScaleDnMult == 4){
2007                                 cbcr_vsd_bil_gt4 = 1;
2008                                 cbcr_vsd_bil_gt2 = 0;
2009                         }else if(cbcr_vScaleDnMult == 2){
2010                                 cbcr_vsd_bil_gt4 = 0;
2011                                 cbcr_vsd_bil_gt2 = 1;
2012                         }else{
2013                                 cbcr_vsd_bil_gt4 = 0;
2014                                 cbcr_vsd_bil_gt2 = 0;
2015                         }
2016                         break;
2017                 case SCALE_DOWN_AVG:
2018                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH, cbcr_dstH);
2019                         break;
2020                 default :
2021                         printk(KERN_WARNING "%s:un supported cbr_vsd_mode:%d\n",
2022                                 __func__,win->cbr_vsd_mode);
2023                     break;
2024                 }
2025                 break;
2026         default :
2027                 printk(KERN_WARNING "%s:un supported cbr_ver_scl_mode:%d\n",
2028                         __func__,win->cbr_ver_scl_mode);
2029                 break;
2030         }
2031         win->scale_cbcr_x = cbcr_xscl_factor;
2032         win->scale_cbcr_y = cbcr_yscl_factor;
2033         win->vsd_cbr_gt4  = cbcr_vsd_bil_gt4;
2034         win->vsd_cbr_gt2  = cbcr_vsd_bil_gt2;
2035
2036         DBG(1,"cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",cbcr_xscl_factor,
2037                 cbcr_yscl_factor,cbcr_vsd_bil_gt4,cbcr_vsd_bil_gt2);
2038         return 0;
2039 }
2040
2041
2042
2043 static int win0_set_par(struct lcdc_device *lcdc_dev,
2044                         struct rk_screen *screen, struct rk_lcdc_win *win)
2045 {
2046         u32 xact,yact,xvir, yvir,xpos, ypos;
2047         u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2048         char fmt[9] = "NULL";
2049
2050         xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len;
2051         ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len;
2052
2053         spin_lock(&lcdc_dev->reg_lock);
2054         if(likely(lcdc_dev->clk_on)){
2055                 rk3288_lcdc_cal_scl_fac(win);/*fac,lb,gt2,gt4*/
2056                 switch (win->area[0].format) {
2057                 case ARGB888:
2058                         fmt_cfg = 0;
2059                         swap_rb = 0;
2060                         win->fmt_10 = 0;
2061                         break;
2062                 case XBGR888:
2063                 case ABGR888:
2064                         fmt_cfg = 0;
2065                         swap_rb = 1;
2066                         win->fmt_10 = 0;
2067                         break;
2068                 case RGB888:
2069                         fmt_cfg = 1;
2070                         swap_rb = 0;
2071                         win->fmt_10 = 0;
2072                         break;
2073                 case RGB565:
2074                         fmt_cfg = 2;
2075                         swap_rb = 0;
2076                         win->fmt_10 = 0;
2077                         break;
2078                 case YUV422:
2079                         fmt_cfg = 5;
2080                         swap_rb = 0;
2081                         win->fmt_10 = 0;
2082                         break;
2083                 case YUV420:
2084                         fmt_cfg = 4;
2085                         swap_rb = 0;
2086                         win->fmt_10 = 0;
2087                         break;
2088                 case YUV420_NV21:
2089                         fmt_cfg = 4;
2090                         swap_rb = 0;
2091                         swap_uv = 1;
2092                         win->fmt_10 = 0;
2093                         break;
2094                 case YUV444:
2095                         fmt_cfg = 6;
2096                         swap_rb = 0;
2097                         win->fmt_10 = 0;
2098                 case YUV422_A:
2099                         fmt_cfg = 5;
2100                         swap_rb = 0;
2101                         win->fmt_10 = 1;
2102                         break;
2103                 case YUV420_A:
2104                         fmt_cfg = 4;
2105                         swap_rb = 0;
2106                         win->fmt_10 = 1;
2107                         break;
2108                 case YUV444_A:
2109                         fmt_cfg = 6;
2110                         swap_rb = 0;
2111                         win->fmt_10 = 1;
2112                         break;
2113                 default:
2114                         dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
2115                                 __func__);
2116                         break;
2117                 }
2118                 win->area[0].fmt_cfg = fmt_cfg;
2119                 win->area[0].swap_rb = swap_rb;
2120                 win->area[0].dsp_stx = xpos;
2121                 win->area[0].dsp_sty = ypos;
2122                 win->area[0].swap_uv = swap_uv;
2123                 xact = win->area[0].xact;
2124                 yact = win->area[0].yact;
2125                 xvir = win->area[0].xvir;
2126                 yvir = win->area[0].yvir;
2127         }
2128         rk3288_win_0_1_reg_update(&lcdc_dev->driver,0);
2129         spin_unlock(&lcdc_dev->reg_lock);
2130
2131         DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
2132                 ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id,
2133                 __func__, get_format_string(win->area[0].format, fmt), xact,
2134                 yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos);
2135         return 0;
2136
2137 }
2138
2139 static int win1_set_par(struct lcdc_device *lcdc_dev,
2140                         struct rk_screen *screen, struct rk_lcdc_win *win)
2141 {
2142         u32 xact, yact, xvir, yvir, xpos, ypos;
2143         u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2144         char fmt[9] = "NULL";
2145
2146         xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len;
2147         ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len;
2148
2149         spin_lock(&lcdc_dev->reg_lock);
2150         if (likely(lcdc_dev->clk_on)) {
2151                 rk3288_lcdc_cal_scl_fac(win);/*fac,lb,gt2,gt4*/
2152                 switch (win->area[0].format) {
2153                 case ARGB888:
2154                         fmt_cfg = 0;
2155                         swap_rb = 0;
2156                         win->fmt_10 = 0;
2157                         break;
2158                 case XBGR888:
2159                 case ABGR888:
2160                         fmt_cfg = 0;
2161                         swap_rb = 1;
2162                         win->fmt_10 = 0;
2163                         break;
2164                 case RGB888:
2165                         fmt_cfg = 1;
2166                         swap_rb = 0;
2167                         win->fmt_10 = 0;
2168                         break;
2169                 case RGB565:
2170                         fmt_cfg = 2;
2171                         swap_rb = 0;
2172                         win->fmt_10 = 0;
2173                         break;
2174                 case YUV422:
2175                         fmt_cfg = 5;
2176                         swap_rb = 0;
2177                         win->fmt_10 = 0;
2178                         break;
2179                 case YUV420:
2180                         fmt_cfg = 4;
2181                         swap_rb = 0;
2182                         win->fmt_10 = 0;
2183                         break;
2184                 case YUV420_NV21:
2185                         fmt_cfg = 4;
2186                         swap_rb = 0;
2187                         swap_uv = 1;
2188                         win->fmt_10 = 0;
2189                         break;
2190                 case YUV444:
2191                         fmt_cfg = 6;
2192                         swap_rb = 0;
2193                         win->fmt_10 = 0;
2194                         break;
2195                 case YUV422_A:
2196                         fmt_cfg = 5;
2197                         swap_rb = 0;
2198                         win->fmt_10 = 1;
2199                         break;
2200                 case YUV420_A:
2201                         fmt_cfg = 4;
2202                         swap_rb = 0;
2203                         win->fmt_10 = 1;
2204                         break;
2205                 case YUV444_A:
2206                         fmt_cfg = 6;
2207                         swap_rb = 0;
2208                         win->fmt_10 = 1;
2209                         break;
2210                 default:
2211                         dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
2212                                 __func__);
2213                         break;
2214                 }
2215                 win->area[0].fmt_cfg = fmt_cfg;
2216                 win->area[0].swap_rb = swap_rb;
2217                 win->area[0].dsp_stx = xpos;
2218                 win->area[0].dsp_sty = ypos;
2219                 win->area[0].swap_uv = swap_uv;
2220                 xact = win->area[0].xact;
2221                 yact = win->area[0].yact;
2222                 xvir = win->area[0].xvir;
2223                 yvir = win->area[0].yvir;
2224         }
2225         rk3288_win_0_1_reg_update(&lcdc_dev->driver,1);
2226         spin_unlock(&lcdc_dev->reg_lock);
2227
2228         DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
2229                 ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id,
2230                 __func__, get_format_string(win->area[0].format, fmt), xact,
2231                 yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos);
2232         return 0;
2233
2234 }
2235
2236 static int win2_set_par(struct lcdc_device *lcdc_dev,
2237                         struct rk_screen *screen, struct rk_lcdc_win *win)
2238 {
2239         int i;
2240         u8 fmt_cfg, swap_rb;
2241
2242         spin_lock(&lcdc_dev->reg_lock);
2243         if (likely(lcdc_dev->clk_on)) {
2244                 for (i = 0; i < win->area_num; i++) {
2245                         switch (win->area[i].format) {
2246                         case ARGB888:
2247                                 fmt_cfg = 0;
2248                                 swap_rb = 0;
2249                                 break;
2250                         case XBGR888:
2251                         case ABGR888:
2252                                 fmt_cfg = 0;
2253                                 swap_rb = 1;
2254                                 break;
2255                         case RGB888:
2256                                 fmt_cfg = 1;
2257                                 swap_rb = 0;
2258                                 break;
2259                         case RGB565:
2260                                 fmt_cfg = 2;
2261                                 swap_rb = 0;
2262                                 break;
2263                         default:
2264                                 dev_err(lcdc_dev->driver.dev,
2265                                         "%s:un supported format!\n",
2266                                         __func__);
2267                                 break;
2268                         }
2269                         win->area[i].fmt_cfg = fmt_cfg;
2270                         win->area[i].swap_rb = swap_rb;
2271                         win->area[i].dsp_stx = win->area[i].xpos +
2272                                 screen->mode.left_margin +
2273                                 screen->mode.hsync_len;
2274                         if (screen->y_mirror == 1) {
2275                                 win->area[i].dsp_sty = screen->mode.yres -
2276                                         win->area[i].ypos -
2277                                         win->area[i].ysize +
2278                                         screen->mode.upper_margin +
2279                                         screen->mode.vsync_len;
2280                         } else {
2281                                 win->area[i].dsp_sty = win->area[i].ypos +
2282                                         screen->mode.upper_margin +
2283                                         screen->mode.vsync_len;
2284                         }
2285                 }
2286         }
2287         rk3288_win_2_3_reg_update(&lcdc_dev->driver,2);
2288         spin_unlock(&lcdc_dev->reg_lock);
2289         return 0;
2290 }
2291
2292 static int win3_set_par(struct lcdc_device *lcdc_dev,
2293                         struct rk_screen *screen, struct rk_lcdc_win *win)
2294
2295 {
2296         int i;
2297         u8 fmt_cfg, swap_rb;
2298
2299         spin_lock(&lcdc_dev->reg_lock);
2300         if (likely(lcdc_dev->clk_on)) {
2301                 for (i = 0; i < win->area_num; i++) {
2302                         switch (win->area[i].format) {
2303                         case ARGB888:
2304                                 fmt_cfg = 0;
2305                                 swap_rb = 0;
2306                                 break;
2307                         case XBGR888:
2308                         case ABGR888:
2309                                 fmt_cfg = 0;
2310                                 swap_rb = 1;
2311                                 break;
2312                         case RGB888:
2313                                 fmt_cfg = 1;
2314                                 swap_rb = 0;
2315                                 break;
2316                         case RGB565:
2317                                 fmt_cfg = 2;
2318                                 swap_rb = 0;
2319                                 break;
2320                         default:
2321                                 dev_err(lcdc_dev->driver.dev,
2322                                         "%s:un supported format!\n",
2323                                         __func__);
2324                                 break;
2325                         }
2326                         win->area[i].fmt_cfg = fmt_cfg;
2327                         win->area[i].swap_rb = swap_rb;
2328                         win->area[i].dsp_stx = win->area[i].xpos +
2329                                 screen->mode.left_margin +
2330                                 screen->mode.hsync_len;
2331                         if (screen->y_mirror == 1) {
2332                                 win->area[i].dsp_sty = screen->mode.yres -
2333                                         win->area[i].ypos -
2334                                         win->area[i].ysize +
2335                                         screen->mode.upper_margin +
2336                                         screen->mode.vsync_len;
2337                         } else {
2338                                 win->area[i].dsp_sty = win->area[i].ypos +
2339                                         screen->mode.upper_margin +
2340                                         screen->mode.vsync_len;
2341                         }
2342                 }
2343         }
2344         rk3288_win_2_3_reg_update(&lcdc_dev->driver,3);
2345         spin_unlock(&lcdc_dev->reg_lock);
2346         return 0;
2347 }
2348
2349 static int rk3288_lcdc_set_par(struct rk_lcdc_driver *dev_drv,int win_id)
2350 {
2351         struct lcdc_device *lcdc_dev =
2352             container_of(dev_drv, struct lcdc_device, driver);
2353         struct rk_lcdc_win *win = NULL;
2354         struct rk_screen *screen = dev_drv->cur_screen;
2355         win = dev_drv->win[win_id];
2356
2357         switch(win_id)
2358         {
2359         case 0:
2360                 win0_set_par(lcdc_dev, screen, win);
2361                 break;
2362         case 1:
2363                 win1_set_par(lcdc_dev, screen, win);
2364                 break;
2365         case 2:
2366                 win2_set_par(lcdc_dev, screen, win);
2367                 break;
2368         case 3:
2369                 win3_set_par(lcdc_dev, screen, win);
2370                 break;
2371         default:
2372                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2373                 break;
2374         }
2375         return 0;
2376 }
2377
2378 static int rk3288_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2379                              unsigned long arg, int win_id)
2380 {
2381         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2382                                                            struct
2383                                                            lcdc_device,
2384                                                            driver);
2385         u32 panel_size[2];
2386         void __user *argp = (void __user *)arg;
2387         struct color_key_cfg clr_key_cfg;
2388
2389         switch (cmd) {
2390         case RK_FBIOGET_PANEL_SIZE:
2391                 panel_size[0] = lcdc_dev->screen->mode.xres;
2392                 panel_size[1] = lcdc_dev->screen->mode.yres;
2393                 if (copy_to_user(argp, panel_size, 8))
2394                         return -EFAULT;
2395                 break;
2396         case RK_FBIOPUT_COLOR_KEY_CFG:
2397                 if (copy_from_user(&clr_key_cfg, argp,
2398                                    sizeof(struct color_key_cfg)))
2399                         return -EFAULT;
2400                 rk3288_lcdc_clr_key_cfg(dev_drv);
2401                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
2402                             clr_key_cfg.win0_color_key_cfg);
2403                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
2404                             clr_key_cfg.win1_color_key_cfg);
2405                 break;
2406
2407         default:
2408                 break;
2409         }
2410         return 0;
2411 }
2412
2413 static int rk3288_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
2414 {
2415         u32 reg;
2416         struct lcdc_device *lcdc_dev =
2417             container_of(dev_drv, struct lcdc_device, driver);
2418         if (dev_drv->suspend_flag)
2419                 return 0;
2420
2421         dev_drv->suspend_flag = 1;
2422         flush_kthread_worker(&dev_drv->update_regs_worker);
2423
2424         for (reg = MMU_DTE_ADDR; reg <= MMU_AUTO_GATING; reg +=4)
2425                         lcdc_readl(lcdc_dev, reg);
2426         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
2427                 dev_drv->trsm_ops->disable();
2428
2429         spin_lock(&lcdc_dev->reg_lock);
2430         if (likely(lcdc_dev->clk_on)) {
2431                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2432                                         v_DSP_BLANK_EN(1));
2433                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_FS_INTR_CLR | m_LINE_FLAG_INTR_CLR,
2434                                         v_FS_INTR_CLR(1) | v_LINE_FLAG_INTR_CLR(1));
2435                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2436                                         v_DSP_OUT_ZERO(1));
2437                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
2438                                         v_STANDBY_EN(1));
2439                 lcdc_cfg_done(lcdc_dev);
2440
2441                 if (dev_drv->iommu_enabled) {
2442                         if (dev_drv->mmu_dev)
2443                                 rockchip_iovmm_deactivate(dev_drv->dev);
2444                 }
2445
2446                 spin_unlock(&lcdc_dev->reg_lock);
2447         } else {
2448                 spin_unlock(&lcdc_dev->reg_lock);
2449                 return 0;
2450         }
2451         rk3288_lcdc_clk_disable(lcdc_dev);
2452         rk_disp_pwr_disable(dev_drv);
2453         return 0;
2454 }
2455
2456 static int rk3288_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
2457 {
2458         struct lcdc_device *lcdc_dev =
2459             container_of(dev_drv, struct lcdc_device, driver);
2460         int i, j;
2461         int __iomem *c;
2462         int v, r, g, b;
2463
2464         if (!dev_drv->suspend_flag)
2465                 return 0;
2466         rk_disp_pwr_enable(dev_drv);
2467         dev_drv->suspend_flag = 0;
2468
2469         if (lcdc_dev->atv_layer_cnt) {
2470                 rk3288_lcdc_clk_enable(lcdc_dev);
2471                 rk3288_lcdc_reg_restore(lcdc_dev);
2472
2473                 spin_lock(&lcdc_dev->reg_lock);
2474                 if (dev_drv->cur_screen->dsp_lut) {
2475                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2476                                      v_DSP_LUT_EN(0));
2477                         lcdc_cfg_done(lcdc_dev);
2478                         mdelay(25);
2479                         for (i = 0; i < 256; i++) {
2480                                 v = dev_drv->cur_screen->dsp_lut[i];
2481                                 c = lcdc_dev->dsp_lut_addr_base + (i << 2);
2482                                 b = (v & 0xff) << 2;
2483                                 g = (v & 0xff00) << 4;
2484                                 r = (v & 0xff0000) << 6;
2485                                 v = r + g + b;
2486                                 for (j = 0; j < 4; j++) {
2487                                         writel_relaxed(v, c);
2488                                         v += (1 + (1 << 10) + (1 << 20)) ;
2489                                         c++;
2490                                 }
2491                         }
2492                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2493                                      v_DSP_LUT_EN(1));
2494                 }
2495
2496                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2497                              v_DSP_OUT_ZERO(0));
2498                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
2499                              v_STANDBY_EN(0));
2500                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2501                                         v_DSP_BLANK_EN(0));
2502                 lcdc_cfg_done(lcdc_dev);
2503
2504                 if (dev_drv->iommu_enabled) {
2505                         if (dev_drv->mmu_dev)
2506                                 rockchip_iovmm_activate(dev_drv->dev);
2507                 }
2508
2509                 spin_unlock(&lcdc_dev->reg_lock);
2510         }
2511
2512         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2513                 dev_drv->trsm_ops->enable();
2514
2515         return 0;
2516 }
2517
2518 static int rk3288_lcdc_blank(struct rk_lcdc_driver *dev_drv,
2519                              int win_id, int blank_mode)
2520 {
2521         switch (blank_mode) {
2522         case FB_BLANK_UNBLANK:
2523                 rk3288_lcdc_early_resume(dev_drv);
2524                 break;
2525         case FB_BLANK_NORMAL:
2526                 rk3288_lcdc_early_suspend(dev_drv);
2527                 break;
2528         default:
2529                 rk3288_lcdc_early_suspend(dev_drv);
2530                 break;
2531         }
2532
2533         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
2534
2535         return 0;
2536 }
2537
2538 static int rk3288_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
2539 {
2540         struct lcdc_device *lcdc_dev =
2541                 container_of(dev_drv, struct lcdc_device, driver);
2542         int win_status = 0;
2543         if (win_id == 0)
2544                 win_status = lcdc_read_bit(lcdc_dev, WIN0_CTRL0, m_WIN0_EN);
2545         else if (win_id == 1)
2546                 win_status = lcdc_read_bit(lcdc_dev, WIN1_CTRL0, m_WIN1_EN);
2547         else if (win_id == 2)
2548                 win_status = lcdc_read_bit(lcdc_dev, WIN2_CTRL0, m_WIN2_EN);
2549         else if (win_id == 3)
2550                 win_status = lcdc_read_bit(lcdc_dev, WIN3_CTRL0, m_WIN3_EN);
2551         else if (win_id == 4)
2552                 win_status = lcdc_read_bit(lcdc_dev, HWC_CTRL0, m_HWC_EN);
2553         else
2554                 pr_err("!!!%s,win_id :%d,unsupport!!!\n",__func__,win_id);
2555
2556         return win_status;
2557 }
2558
2559 /*overlay will be do at regupdate*/
2560 static int rk3288_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
2561                                bool set)
2562 {
2563         struct lcdc_device *lcdc_dev =
2564             container_of(dev_drv, struct lcdc_device, driver);
2565         struct rk_lcdc_win *win = NULL;
2566         int i,ovl;
2567         unsigned int mask, val;
2568         int z_order_num=0;
2569         int layer0_sel,layer1_sel,layer2_sel,layer3_sel;
2570         if(swap == 0){
2571                 for(i=0;i<4;i++){
2572                         win = dev_drv->win[i];
2573                         if(win->state == 1){
2574                                 z_order_num++;
2575                         }
2576                 }
2577                 for(i=0;i<4;i++){
2578                         win = dev_drv->win[i];
2579                         if(win->state == 0)
2580                                 win->z_order = z_order_num++;
2581                         switch(win->z_order){
2582                         case 0:
2583                                 layer0_sel = win->id;
2584                                 break;
2585                         case 1:
2586                                 layer1_sel = win->id;
2587                                 break;
2588                         case 2:
2589                                 layer2_sel = win->id;
2590                                 break;
2591                         case 3:
2592                                 layer3_sel = win->id;
2593                                 break;
2594                         default:
2595                                 break;
2596                         }
2597                 }
2598         }else{
2599                 layer0_sel = swap %10;;
2600                 layer1_sel = swap /10 % 10;
2601                 layer2_sel = swap / 100 %10;
2602                 layer3_sel = swap / 1000;
2603         }
2604
2605         spin_lock(&lcdc_dev->reg_lock);
2606         if(lcdc_dev->clk_on){
2607                 if(set){
2608                         mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
2609                                 m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
2610                         val  = v_DSP_LAYER0_SEL(layer0_sel) |
2611                                 v_DSP_LAYER1_SEL(layer1_sel) |
2612                                 v_DSP_LAYER2_SEL(layer2_sel) |
2613                                 v_DSP_LAYER3_SEL(layer3_sel);
2614                         lcdc_msk_reg(lcdc_dev,DSP_CTRL1,mask,val);
2615                 }else{
2616                         layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER0_SEL);
2617                         layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER1_SEL);
2618                         layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER2_SEL);
2619                         layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER3_SEL);
2620                         ovl = layer3_sel*1000 + layer2_sel*100 + layer1_sel *10 + layer0_sel;
2621                 }
2622         }else{
2623                 ovl = -EPERM;
2624         }
2625         spin_unlock(&lcdc_dev->reg_lock);
2626
2627         return ovl;
2628 }
2629
2630 static ssize_t rk3288_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
2631                                          char *buf, int win_id)
2632 {
2633         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2634                                                            struct
2635                                                            lcdc_device,
2636                                                            driver);
2637         struct rk_screen *screen = dev_drv->cur_screen;
2638         u16 hsync_len = screen->mode.hsync_len;
2639         u16 left_margin = screen->mode.left_margin;
2640         u16 vsync_len = screen->mode.vsync_len;
2641         u16 upper_margin = screen->mode.upper_margin;
2642         u32 h_pw_bp = hsync_len + left_margin;
2643         u32 v_pw_bp = vsync_len + upper_margin;
2644         u32 fmt_id;
2645         char format_w0[9] = "NULL";
2646         char format_w1[9] = "NULL";
2647         char format_w2[9] = "NULL";
2648         char format_w3[9] = "NULL";
2649         u32 win_ctrl,zorder,vir_info,act_info,dsp_info,dsp_st,y_factor,uv_factor;
2650         u8 layer0_sel,layer1_sel,layer2_sel,layer3_sel;
2651         u8 w0_state,w1_state,w2_state,w3_state;
2652         u8 w2_0_state,w2_1_state,w2_2_state,w2_3_state;
2653         u8 w3_0_state,w3_1_state,w3_2_state,w3_3_state;
2654
2655         u32 w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y,w0_dsp_x,w0_dsp_y,w0_st_x=h_pw_bp,w0_st_y=v_pw_bp;
2656         u32 w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y,w1_dsp_x,w1_dsp_y,w1_st_x=h_pw_bp,w1_st_y=v_pw_bp;
2657         u32 w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac,w0_uv_v_fac;
2658         u32 w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac,w1_uv_v_fac;
2659
2660         u32 w2_0_vir_y,w2_1_vir_y,w2_2_vir_y,w2_3_vir_y;
2661         u32 w2_0_dsp_x,w2_1_dsp_x,w2_2_dsp_x,w2_3_dsp_x;
2662         u32 w2_0_dsp_y,w2_1_dsp_y,w2_2_dsp_y,w2_3_dsp_y;
2663         u32 w2_0_st_x=h_pw_bp,w2_1_st_x=h_pw_bp,w2_2_st_x=h_pw_bp,w2_3_st_x=h_pw_bp;
2664         u32 w2_0_st_y=v_pw_bp,w2_1_st_y=v_pw_bp,w2_2_st_y=v_pw_bp,w2_3_st_y=v_pw_bp;
2665
2666         u32 w3_0_vir_y,w3_1_vir_y,w3_2_vir_y,w3_3_vir_y;
2667         u32 w3_0_dsp_x,w3_1_dsp_x,w3_2_dsp_x,w3_3_dsp_x;
2668         u32 w3_0_dsp_y,w3_1_dsp_y,w3_2_dsp_y,w3_3_dsp_y;
2669         u32 w3_0_st_x=h_pw_bp,w3_1_st_x=h_pw_bp,w3_2_st_x=h_pw_bp,w3_3_st_x=h_pw_bp;
2670         u32 w3_0_st_y=v_pw_bp,w3_1_st_y=v_pw_bp,w3_2_st_y=v_pw_bp,w3_3_st_y=v_pw_bp;
2671         u32 dclk_freq;
2672
2673         dclk_freq = screen->mode.pixclock;
2674         /*rk3288_lcdc_reg_dump(dev_drv);*/
2675
2676         spin_lock(&lcdc_dev->reg_lock);
2677         if (lcdc_dev->clk_on) {
2678                 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
2679                 layer0_sel = (zorder & m_DSP_LAYER0_SEL)>>8;
2680                 layer1_sel = (zorder & m_DSP_LAYER1_SEL)>>10;
2681                 layer2_sel = (zorder & m_DSP_LAYER2_SEL)>>12;
2682                 layer3_sel = (zorder & m_DSP_LAYER3_SEL)>>14;
2683                 /*WIN0*/
2684                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
2685                 w0_state = win_ctrl & m_WIN0_EN;
2686                 fmt_id = (win_ctrl & m_WIN0_DATA_FMT)>>1;
2687                 switch (fmt_id) {
2688                 case 0:
2689                         strcpy(format_w0, "ARGB888");
2690                         break;
2691                 case 1:
2692                         strcpy(format_w0, "RGB888");
2693                         break;
2694                 case 2:
2695                         strcpy(format_w0, "RGB565");
2696                         break;
2697                 case 4:
2698                         strcpy(format_w0, "YCbCr420");
2699                         break;
2700                 case 5:
2701                         strcpy(format_w0, "YCbCr422");
2702                         break;
2703                 case 6:
2704                         strcpy(format_w0, "YCbCr444");
2705                         break;
2706                 default:
2707                         strcpy(format_w0, "invalid\n");
2708                         break;
2709                 }
2710                 vir_info = lcdc_readl(lcdc_dev,WIN0_VIR);
2711                 act_info = lcdc_readl(lcdc_dev,WIN0_ACT_INFO);
2712                 dsp_info = lcdc_readl(lcdc_dev,WIN0_DSP_INFO);
2713                 dsp_st = lcdc_readl(lcdc_dev,WIN0_DSP_ST);
2714                 y_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_YRGB);
2715                 uv_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_CBR);
2716                 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
2717                 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV)>>16;
2718                 w0_act_x = (act_info & m_WIN0_ACT_WIDTH)+1;
2719                 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT)>>16)+1;
2720                 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH)+1;
2721                 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT)>>16)+1;
2722                 if (w0_state) {
2723                         w0_st_x = dsp_st & m_WIN0_DSP_XST;
2724                         w0_st_y = (dsp_st & m_WIN0_DSP_YST)>>16;
2725                 }
2726                 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
2727                 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB)>>16;
2728                 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
2729                 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR)>>16;
2730
2731                 /*WIN1*/
2732                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
2733                 w1_state = win_ctrl & m_WIN1_EN;
2734                 fmt_id = (win_ctrl & m_WIN1_DATA_FMT)>>1;
2735                 switch (fmt_id) {
2736                 case 0:
2737                         strcpy(format_w1, "ARGB888");
2738                         break;
2739                 case 1:
2740                         strcpy(format_w1, "RGB888");
2741                         break;
2742                 case 2:
2743                         strcpy(format_w1, "RGB565");
2744                         break;
2745                 case 4:
2746                         strcpy(format_w1, "YCbCr420");
2747                         break;
2748                 case 5:
2749                         strcpy(format_w1, "YCbCr422");
2750                         break;
2751                 case 6:
2752                         strcpy(format_w1, "YCbCr444");
2753                         break;
2754                 default:
2755                         strcpy(format_w1, "invalid\n");
2756                         break;
2757                 }
2758                 vir_info = lcdc_readl(lcdc_dev,WIN1_VIR);
2759                 act_info = lcdc_readl(lcdc_dev,WIN1_ACT_INFO);
2760                 dsp_info = lcdc_readl(lcdc_dev,WIN1_DSP_INFO);
2761                 dsp_st = lcdc_readl(lcdc_dev,WIN1_DSP_ST);
2762                 y_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_YRGB);
2763                 uv_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_CBR);
2764                 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
2765                 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV)>>16;
2766                 w1_act_x = (act_info & m_WIN1_ACT_WIDTH)+1;
2767                 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT)>>16)+1;
2768                 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH)+1;
2769                 w1_dsp_y =((dsp_info & m_WIN1_DSP_HEIGHT)>>16)+1;
2770                 if (w1_state) {
2771                         w1_st_x = dsp_st & m_WIN1_DSP_XST;
2772                         w1_st_y = (dsp_st & m_WIN1_DSP_YST)>>16;
2773                 }
2774                 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
2775                 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB)>>16;
2776                 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
2777                 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR)>>16;
2778                 /*WIN2*/
2779                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
2780                 w2_state = win_ctrl & m_WIN2_EN;
2781                 w2_0_state = (win_ctrl & m_WIN2_MST0_EN)>>4;
2782                 w2_1_state = (win_ctrl & m_WIN2_MST1_EN)>>5;
2783                 w2_2_state = (win_ctrl & m_WIN2_MST2_EN)>>6;
2784                 w2_3_state = (win_ctrl & m_WIN2_MST3_EN)>>7;
2785                 vir_info = lcdc_readl(lcdc_dev,WIN2_VIR0_1);
2786                 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
2787                 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1)>>16;
2788                 vir_info = lcdc_readl(lcdc_dev,WIN2_VIR2_3);
2789                 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
2790                 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3)>>16;
2791                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT)>>1;
2792                 switch (fmt_id) {
2793                 case 0:
2794                         strcpy(format_w2, "ARGB888");
2795                         break;
2796                 case 1:
2797                         strcpy(format_w2, "RGB888");
2798                         break;
2799                 case 2:
2800                         strcpy(format_w2, "RGB565");
2801                         break;
2802                 case 4:
2803                         strcpy(format_w2,"8bpp");
2804                         break;
2805                 case 5:
2806                         strcpy(format_w2,"4bpp");
2807                         break;
2808                 case 6:
2809                         strcpy(format_w2,"2bpp");
2810                         break;
2811                 case 7:
2812                         strcpy(format_w2,"1bpp");
2813                         break;
2814                 default:
2815                         strcpy(format_w2, "invalid\n");
2816                         break;
2817                 }
2818                 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO0);
2819                 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST0);
2820                 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0)+1;
2821                 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0)>>16)+1;
2822                 if (w2_0_state) {
2823                         w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
2824                         w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0)>>16;
2825                 }
2826                 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO1);
2827                 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST1);
2828                 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1)+1;
2829                 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1)>>16)+1;
2830                 if (w2_1_state) {
2831                         w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
2832                         w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1)>>16;
2833                 }
2834                 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO2);
2835                 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST2);
2836                 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2)+1;
2837                 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2)>>16)+1;
2838                 if (w2_2_state) {
2839                         w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
2840                         w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2)>>16;
2841                 }
2842                 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO3);
2843                 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST3);
2844                 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3)+1;
2845                 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3)>>16)+1;
2846                 if (w2_3_state) {
2847                         w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
2848                         w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3)>>16;
2849                 }
2850
2851                 /*WIN3*/
2852                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
2853                 w3_state = win_ctrl & m_WIN3_EN;
2854                 w3_0_state = (win_ctrl & m_WIN3_MST0_EN)>>4;
2855                 w3_1_state = (win_ctrl & m_WIN3_MST1_EN)>>5;
2856                 w3_2_state = (win_ctrl & m_WIN3_MST2_EN)>>6;
2857                 w3_3_state = (win_ctrl & m_WIN3_MST3_EN)>>7;
2858                 vir_info = lcdc_readl(lcdc_dev,WIN3_VIR0_1);
2859                 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
2860                 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1)>>16;
2861                 vir_info = lcdc_readl(lcdc_dev,WIN3_VIR2_3);
2862                 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
2863                 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3)>>16;
2864                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT)>>1;
2865                 switch (fmt_id) {
2866                 case 0:
2867                         strcpy(format_w3, "ARGB888");
2868                         break;
2869                 case 1:
2870                         strcpy(format_w3, "RGB888");
2871                         break;
2872                 case 2:
2873                         strcpy(format_w3, "RGB565");
2874                         break;
2875                 case 4:
2876                         strcpy(format_w3,"8bpp");
2877                         break;
2878                 case 5:
2879                         strcpy(format_w3,"4bpp");
2880                         break;
2881                 case 6:
2882                         strcpy(format_w3,"2bpp");
2883                         break;
2884                 case 7:
2885                         strcpy(format_w3,"1bpp");
2886                         break;
2887                 default:
2888                         strcpy(format_w3, "invalid");
2889                         break;
2890                 }
2891                 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO0);
2892                 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST0);
2893                 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0)+1;
2894                 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0)>>16)+1;
2895                 if (w3_0_state) {
2896                         w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
2897                         w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0)>>16;
2898                 }
2899
2900                 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO1);
2901                 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST1);
2902                 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1)+1;
2903                 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1)>>16)+1;
2904                 if (w3_1_state) {
2905                         w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
2906                         w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1)>>16;
2907                 }
2908
2909                 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO2);
2910                 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST2);
2911                 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2)+1;
2912                 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2)>>16)+1;
2913                 if (w3_2_state) {
2914                         w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
2915                         w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2)>>16;
2916                 }
2917
2918                 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO3);
2919                 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST3);
2920                 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3)+1;
2921                 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3)>>16)+1;
2922                 if (w3_3_state) {
2923                         w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
2924                         w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3)>>16;
2925                 }
2926
2927         } else {
2928                 spin_unlock(&lcdc_dev->reg_lock);
2929                 return -EPERM;
2930         }
2931         spin_unlock(&lcdc_dev->reg_lock);
2932         return snprintf(buf, PAGE_SIZE,
2933                         "z-order:\n"
2934                         "  layer3_sel_win[%d]\n"
2935                         "  layer2_sel_win[%d]\n"
2936                         "  layer1_sel_win[%d]\n"
2937                         "  layer0_sel_win[%d]\n"
2938                         "win0:\n"
2939                         "  state:%d, "
2940                         "  fmt:%s, "
2941                         "  y_vir:%d, "
2942                         "  uv_vir:%d\n"
2943                         "  xact:%4d, "
2944                         "  yact:%4d, "
2945                         "  dsp_x:%4d, "
2946                         "  dsp_y:%4d, "
2947                         "  x_st:%4d, "
2948                         "  y_st:%4d\n"
2949                         "  y_h_fac:%8d, "
2950                         "  y_v_fac:%8d, "
2951                         "  uv_h_fac:%8d, "
2952                         "  uv_v_fac:%8d\n"
2953                         "  y_addr: 0x%08x, "
2954                         "  uv_addr:0x%08x\n"
2955                         "win1:\n"
2956                         "  state:%d, "
2957                         "  fmt:%s, "
2958                         "  y_vir:%d, "
2959                         "  uv_vir:%d\n"
2960                         "  xact:%4d, "
2961                         "  yact:%4d, "
2962                         "  dsp_x:%4d, "
2963                         "  dsp_y:%4d, "
2964                         "  x_st:%4d, "
2965                         "  y_st:%4d\n"
2966                         "  y_h_fac:%8d, "
2967                         "  y_v_fac:%8d, "
2968                         "  uv_h_fac:%8d, "
2969                         "  uv_v_fac:%8d\n"
2970                         "  y_addr: 0x%08x, "
2971                         "  uv_addr:0x%08x\n"
2972                         "win2:\n"
2973                         "  state:%d\n"
2974                         "  fmt:%s\n"
2975                         "  area0:"
2976                         "  state:%d,"
2977                         "  y_vir:%4d,"
2978                         "  dsp_x:%4d,"
2979                         "  dsp_y:%4d,"
2980                         "  x_st:%4d,"
2981                         "  y_st:%4d,"
2982                         "  addr:0x%08x\n"
2983                         "  area1:"
2984                         "  state:%d,"
2985                         "  y_vir:%4d,"
2986                         "  dsp_x:%4d,"
2987                         "  dsp_y:%4d,"
2988                         "  x_st:%4d,"
2989                         "  y_st:%4d,"
2990                         "  addr:0x%08x\n"
2991                         "  area2:"
2992                         "  state:%d,"
2993                         "  y_vir:%4d,"
2994                         "  dsp_x:%4d,"
2995                         "  dsp_y:%4d,"
2996                         "  x_st:%4d,"
2997                         "  y_st:%4d,"
2998                         "  addr:0x%08x\n"
2999                         "  area3:"
3000                         "  state:%d,"
3001                         "  y_vir:%4d,"
3002                         "  dsp_x:%4d,"
3003                         "  dsp_y:%4d,"
3004                         "  x_st:%4d,"
3005                         "  y_st:%4d,"
3006                         "  addr:0x%08x\n"
3007                         "win3:\n"
3008                         "  state:%d\n"
3009                         "  fmt:%s\n"
3010                         "  area0:"
3011                         "  state:%d,"
3012                         "  y_vir:%4d,"
3013                         "  dsp_x:%4d,"
3014                         "  dsp_y:%4d,"
3015                         "  x_st:%4d,"
3016                         "  y_st:%4d,"
3017                         "  addr:0x%08x\n"
3018                         "  area1:"
3019                         "  state:%d,"
3020                         "  y_vir:%4d,"
3021                         "  dsp_x:%4d,"
3022                         "  dsp_y:%4d,"
3023                         "  x_st:%4d,"
3024                         "  y_st:%4d "
3025                         "  addr:0x%08x\n"
3026                         "  area2:"
3027                         "  state:%d,"
3028                         "  y_vir:%4d,"
3029                         "  dsp_x:%4d,"
3030                         "  dsp_y:%4d,"
3031                         "  x_st:%4d,"
3032                         "  y_st:%4d,"
3033                         "  addr:0x%08x\n"
3034                         "  area3:"
3035                         "  state:%d,"
3036                         "  y_vir:%4d,"
3037                         "  dsp_x:%4d,"
3038                         "  dsp_y:%4d,"
3039                         "  x_st:%4d,"
3040                         "  y_st:%4d,"
3041                         "  addr:0x%08x\n",
3042                         layer3_sel,layer2_sel,layer1_sel,layer0_sel,
3043                         w0_state,format_w0,w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y,
3044                         w0_dsp_x,w0_dsp_y,w0_st_x-h_pw_bp,w0_st_y-v_pw_bp,w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac,
3045                         w0_uv_v_fac,lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3046                         lcdc_readl(lcdc_dev, WIN0_CBR_MST),
3047
3048                         w1_state,format_w1,w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y,
3049                         w1_dsp_x,w1_dsp_y,w1_st_x-h_pw_bp,w1_st_y-v_pw_bp,w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac,
3050                         w1_uv_v_fac,lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3051                         lcdc_readl(lcdc_dev, WIN1_CBR_MST),
3052
3053                         w2_state,format_w2,
3054                         w2_0_state,w2_0_vir_y,w2_0_dsp_x,w2_0_dsp_y,
3055                         w2_0_st_x-h_pw_bp,w2_0_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST0),
3056
3057                         w2_1_state,w2_1_vir_y,w2_1_dsp_x,w2_1_dsp_y,
3058                         w2_1_st_x-h_pw_bp,w2_1_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST1),
3059
3060                         w2_2_state,w2_2_vir_y,w2_2_dsp_x,w2_2_dsp_y,
3061                         w2_2_st_x-h_pw_bp,w2_2_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST2),
3062
3063                         w2_3_state,w2_3_vir_y,w2_3_dsp_x,w2_3_dsp_y,
3064                         w2_3_st_x-h_pw_bp,w2_3_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST3),
3065
3066                         w3_state,format_w3,
3067                         w3_0_state,w3_0_vir_y,w3_0_dsp_x,w3_0_dsp_y,
3068                         w3_0_st_x-h_pw_bp,w3_0_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST0),
3069
3070                         w3_1_state,w3_1_vir_y,w3_1_dsp_x,w3_1_dsp_y,
3071                         w3_1_st_x-h_pw_bp,w3_1_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST1),
3072
3073                         w3_2_state,w3_2_vir_y,w3_2_dsp_x,w3_2_dsp_y,
3074                         w3_2_st_x-h_pw_bp,w3_2_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST2),
3075
3076                         w3_3_state,w3_3_vir_y,w3_3_dsp_x,w3_3_dsp_y,
3077                         w3_3_st_x-h_pw_bp,w3_3_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST3)
3078         );
3079
3080 }
3081
3082 static int rk3288_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3083                                bool set)
3084 {
3085         struct lcdc_device *lcdc_dev =
3086             container_of(dev_drv, struct lcdc_device, driver);
3087         struct rk_screen *screen = dev_drv->cur_screen;
3088         u64 ft = 0;
3089         u32 dotclk;
3090         int ret;
3091         u32 pixclock;
3092         u32 x_total, y_total;
3093         if (set) {
3094                 if (fps == 0) {
3095                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
3096                         return 0;
3097                 }
3098                 ft = div_u64(1000000000000llu, fps);
3099                 x_total =
3100                     screen->mode.upper_margin + screen->mode.lower_margin +
3101                     screen->mode.yres + screen->mode.vsync_len;
3102                 y_total =
3103                     screen->mode.left_margin + screen->mode.right_margin +
3104                     screen->mode.xres + screen->mode.hsync_len;
3105                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3106                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3107                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3108         }
3109
3110         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3111         dev_drv->pixclock = lcdc_dev->pixclock = pixclock;
3112         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3113         screen->ft = 1000 / fps;        /*one frame time in ms */
3114
3115         if (set)
3116                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3117                          clk_get_rate(lcdc_dev->dclk), fps);
3118
3119         return fps;
3120 }
3121
3122 static int rk3288_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3123 {
3124         mutex_lock(&dev_drv->fb_win_id_mutex);
3125         if (order == FB_DEFAULT_ORDER)
3126                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3;
3127         dev_drv->fb3_win_id = order / 1000;
3128         dev_drv->fb2_win_id = (order / 100) % 10;
3129         dev_drv->fb1_win_id = (order / 10) % 10;
3130         dev_drv->fb0_win_id = order % 10;
3131         mutex_unlock(&dev_drv->fb_win_id_mutex);
3132
3133         return 0;
3134 }
3135
3136 static int rk3288_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3137                                   const char *id)
3138 {
3139         int win_id = 0;
3140         mutex_lock(&dev_drv->fb_win_id_mutex);
3141         if (!strcmp(id, "fb0") || !strcmp(id, "fb4"))
3142                 win_id = dev_drv->fb0_win_id;
3143         else if (!strcmp(id, "fb1") || !strcmp(id, "fb5"))
3144                 win_id = dev_drv->fb1_win_id;
3145         else if (!strcmp(id, "fb2") || !strcmp(id, "fb6"))
3146                 win_id = dev_drv->fb2_win_id;
3147         else if (!strcmp(id, "fb3") || !strcmp(id, "fb7"))
3148                 win_id = dev_drv->fb3_win_id;
3149         mutex_unlock(&dev_drv->fb_win_id_mutex);
3150
3151         return win_id;
3152 }
3153
3154 static int rk3288_set_dsp_lut(struct rk_lcdc_driver *dev_drv, int *lut)
3155 {
3156         int i,j;
3157         int __iomem *c;
3158         int v, r, g, b;
3159         int ret = 0;
3160
3161         struct lcdc_device *lcdc_dev =
3162             container_of(dev_drv, struct lcdc_device, driver);
3163         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
3164         lcdc_cfg_done(lcdc_dev);
3165         mdelay(25);
3166         if (dev_drv->cur_screen->dsp_lut) {
3167                 for (i = 0; i < 256; i++) {
3168                         v = dev_drv->cur_screen->dsp_lut[i] = lut[i];
3169                         c = lcdc_dev->dsp_lut_addr_base + (i << 2);
3170                         b = (v & 0xff) << 2;
3171                         g = (v & 0xff00) << 4;
3172                         r = (v & 0xff0000) << 6;
3173                         v = r + g + b;
3174                         for (j = 0; j < 4; j++) {
3175                                 writel_relaxed(v, c);
3176                                 v += (1 + (1 << 10) + (1 << 20)) ;
3177                                 c++;
3178                         }
3179                 }
3180         } else {
3181                 dev_err(dev_drv->dev, "no buffer to backup lut data!\n");
3182                 ret = -1;
3183         }
3184
3185         do{
3186                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
3187                 lcdc_cfg_done(lcdc_dev);
3188         }while(!lcdc_read_bit(lcdc_dev,DSP_CTRL1,m_DSP_LUT_EN));
3189         return ret;
3190 }
3191
3192 static int rk3288_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3193 {
3194         struct lcdc_device *lcdc_dev =
3195             container_of(dev_drv, struct lcdc_device, driver);
3196         int i;
3197         unsigned int mask, val;
3198         struct rk_lcdc_win *win = NULL;
3199         spin_lock(&lcdc_dev->reg_lock);
3200         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3201                              v_STANDBY_EN(lcdc_dev->standby));
3202         for (i=0;i<4;i++) {
3203                 win = dev_drv->win[i];
3204                 if ((win->state == 0)&&(win->last_state == 1)) {
3205                         switch (win->id) {
3206                         case 0:
3207                                 lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
3208                                 mask =  m_WIN0_EN;
3209                                 val  =  v_WIN0_EN(0);
3210                                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask,val);
3211                                 break;
3212                         case 1:
3213                                 lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
3214                                 mask =  m_WIN1_EN;
3215                                 val  =  v_WIN1_EN(0);
3216                                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask,val);
3217                                 break;
3218                         case 2:
3219                                 mask =  m_WIN2_EN | m_WIN2_MST0_EN | m_WIN2_MST1_EN |
3220                                         m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3221                                 val  =  v_WIN2_EN(0) | v_WIN2_MST0_EN(0) | v_WIN2_MST1_EN(0) |
3222                                         v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3223                                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask,val);
3224                                 break;
3225                         case 3:
3226                                 mask =  m_WIN3_EN | m_WIN3_MST0_EN | m_WIN3_MST1_EN |
3227                                         m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3228                                 val  =  v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |  v_WIN3_MST1_EN(0) |
3229                                         v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3230                                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask,val);
3231                                 break;
3232                         default:
3233                                 break;
3234                         }
3235                 }
3236                 win->last_state = win->state;
3237         }
3238         lcdc_cfg_done(lcdc_dev);
3239         spin_unlock(&lcdc_dev->reg_lock);
3240         return 0;
3241 }
3242
3243
3244 static int rk3288_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3245 {
3246         struct lcdc_device *lcdc_dev =
3247             container_of(dev_drv, struct lcdc_device, driver);
3248         spin_lock(&lcdc_dev->reg_lock);
3249         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3250                      v_DIRECT_PATH_EN(open));
3251         lcdc_cfg_done(lcdc_dev);
3252         spin_unlock(&lcdc_dev->reg_lock);
3253         return 0;
3254 }
3255
3256 static int rk3288_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3257 {
3258         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3259                                         struct lcdc_device, driver);
3260         spin_lock(&lcdc_dev->reg_lock);
3261         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3262                      v_DIRECT_PATCH_SEL(win_id));
3263         lcdc_cfg_done(lcdc_dev);
3264         spin_unlock(&lcdc_dev->reg_lock);
3265         return 0;
3266
3267 }
3268
3269 static int rk3288_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3270 {
3271         struct lcdc_device *lcdc_dev =
3272             container_of(dev_drv, struct lcdc_device, driver);
3273         int ovl;
3274         spin_lock(&lcdc_dev->reg_lock);
3275         ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3276         spin_unlock(&lcdc_dev->reg_lock);
3277         return ovl;
3278 }
3279 static int rk3288_lcdc_set_irq_to_cpu(struct rk_lcdc_driver * dev_drv,int enable)
3280 {
3281        struct lcdc_device *lcdc_dev =
3282                                 container_of(dev_drv,struct lcdc_device,driver);
3283        if (enable)
3284                enable_irq(lcdc_dev->irq);
3285        else
3286                disable_irq(lcdc_dev->irq);
3287        return 0;
3288 }
3289
3290 int rk3288_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3291 {
3292         struct lcdc_device *lcdc_dev =
3293             container_of(dev_drv, struct lcdc_device, driver);
3294         u32 int_reg;
3295         int ret;
3296
3297         if (lcdc_dev->clk_on &&(!dev_drv->suspend_flag)){
3298                 int_reg = lcdc_readl(lcdc_dev, INTR_CTRL0);
3299                 if (int_reg & m_LINE_FLAG_INTR_STS) {
3300                         lcdc_dev->driver.frame_time.last_framedone_t =
3301                                         lcdc_dev->driver.frame_time.framedone_t;
3302                         lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3303                         lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR,
3304                                      v_LINE_FLAG_INTR_CLR(1));
3305                         ret = RK_LF_STATUS_FC;
3306                 } else
3307                         ret = RK_LF_STATUS_FR;
3308         } else {
3309                 ret = RK_LF_STATUS_NC;
3310         }
3311
3312         return ret;
3313 }
3314 static int rk3288_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,unsigned int *dsp_addr)
3315 {
3316         struct lcdc_device *lcdc_dev =
3317             container_of(dev_drv, struct lcdc_device, driver);
3318         spin_lock(&lcdc_dev->reg_lock);
3319         if(lcdc_dev->clk_on){
3320                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3321                 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3322                 dsp_addr[2] = lcdc_readl(lcdc_dev, WIN2_MST0);
3323                 dsp_addr[3] = lcdc_readl(lcdc_dev, WIN3_MST0);
3324         }
3325         spin_unlock(&lcdc_dev->reg_lock);
3326         return 0;
3327 }
3328
3329 static struct lcdc_cabc_mode cabc_mode[4] = {
3330 /* pixel_num, stage_up, stage_down */
3331         {5,     128,    0},     /*mode 1*/
3332         {10,    128,    0},     /*mode 2*/
3333         {15,    128,    0},     /*mode 3*/
3334         {20,    128,    0},     /*mode 4*/
3335 };
3336
3337 static int rk3288_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode)
3338 {
3339         struct lcdc_device *lcdc_dev =
3340             container_of(dev_drv, struct lcdc_device, driver);
3341         struct rk_screen *screen = dev_drv->cur_screen;
3342         u32 total_pixel, calc_pixel, stage_up, stage_down, pixel_num;
3343         u32 mask = 0, val = 0, cabc_en = 0;
3344         u32 max_mode_num = sizeof(cabc_mode) / sizeof(struct lcdc_cabc_mode);
3345
3346         dev_drv->cabc_mode = mode;
3347
3348         /* iomux connect to vop or pwm */
3349         if (mode == 0) {
3350                 DBG(3, "close cabc and select rk pwm\n");
3351                 val = 0x30001;
3352                 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_GPIO7A_IOMUX);
3353                 cabc_en = 0;
3354         } else if (mode > 0 && mode <= max_mode_num) {
3355                 DBG(3, "open cabc and select vop pwm\n");
3356                 val = (dev_drv->id == 0) ? 0x30002 : 0x30003;
3357                 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_GPIO7A_IOMUX);
3358                 cabc_en = 1;
3359         } else if (mode > 0x10 && mode <= (max_mode_num + 0x10)) {
3360                 DBG(3, "open cabc and select rk pwm\n");
3361                 val = 0x30001;
3362                 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_GPIO7A_IOMUX);
3363                 cabc_en = 1;
3364                 mode -= 0x10;
3365         } else if (mode == 0xff) {
3366                 DBG(3, "close cabc and select vop pwm\n");
3367                 val = (dev_drv->id == 0) ? 0x30002 : 0x30003;
3368                 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_GPIO7A_IOMUX);
3369                 cabc_en = 0;
3370         } else {
3371                 dev_err(lcdc_dev->dev, "invalid cabc mode value:%d", mode);
3372                 return 0;
3373         }
3374
3375         if (cabc_en == 0) {
3376                 spin_lock(&lcdc_dev->reg_lock);
3377                 if(lcdc_dev->clk_on) {
3378                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0, m_CABC_EN, v_CABC_EN(0));
3379                         lcdc_cfg_done(lcdc_dev);
3380                 }
3381                 spin_unlock(&lcdc_dev->reg_lock);
3382                 return 0;
3383         }
3384
3385         total_pixel = screen->mode.xres * screen->mode.yres;
3386         pixel_num = 1000 - (cabc_mode[mode - 1].pixel_num);
3387         calc_pixel = (total_pixel * pixel_num) / 1000;
3388         stage_up = cabc_mode[mode - 1].stage_up;
3389         stage_down = cabc_mode[mode - 1].stage_down;
3390
3391         spin_lock(&lcdc_dev->reg_lock);
3392         if(lcdc_dev->clk_on) {
3393                 mask = m_CABC_TOTAL_NUM | m_CABC_STAGE_DOWN;
3394                 val = v_CABC_TOTAL_NUM(total_pixel) | v_CABC_STAGE_DOWN(stage_down);
3395                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3396
3397                 mask = m_CABC_EN | m_CABC_CALC_PIXEL_NUM |
3398                         m_CABC_STAGE_UP;
3399                 val = v_CABC_EN(1) | v_CABC_CALC_PIXEL_NUM(calc_pixel) |
3400                         v_CABC_STAGE_UP(stage_up);
3401                 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3402                 lcdc_cfg_done(lcdc_dev);
3403         }
3404         spin_unlock(&lcdc_dev->reg_lock);
3405
3406         return 0;
3407 }
3408 /*
3409         a:[-30~0]:
3410             sin_hue = sin(a)*256 +0x100;
3411             cos_hue = cos(a)*256;
3412         a:[0~30]
3413             sin_hue = sin(a)*256;
3414             cos_hue = cos(a)*256;
3415 */
3416 static int rk3288_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode)
3417 {
3418
3419         struct lcdc_device *lcdc_dev =
3420             container_of(dev_drv, struct lcdc_device, driver);
3421         u32 val;
3422
3423         spin_lock(&lcdc_dev->reg_lock);
3424         if (lcdc_dev->clk_on) {
3425                 val = lcdc_readl(lcdc_dev, BCSH_H);
3426                 switch(mode){
3427                 case H_SIN:
3428                         val &= m_BCSH_SIN_HUE;
3429                         break;
3430                 case H_COS:
3431                         val &= m_BCSH_COS_HUE;
3432                         val >>= 16;
3433                         break;
3434                 default:
3435                         break;
3436                 }
3437         }
3438         spin_unlock(&lcdc_dev->reg_lock);
3439
3440         return val;
3441 }
3442
3443
3444 static int rk3288_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue)
3445 {
3446
3447         struct lcdc_device *lcdc_dev =
3448             container_of(dev_drv, struct lcdc_device, driver);
3449         u32 mask, val;
3450
3451         spin_lock(&lcdc_dev->reg_lock);
3452         if (lcdc_dev->clk_on) {
3453                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
3454                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
3455                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
3456                 lcdc_cfg_done(lcdc_dev);
3457         }
3458         spin_unlock(&lcdc_dev->reg_lock);
3459
3460         return 0;
3461 }
3462
3463 static int rk3288_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value)
3464 {
3465         struct lcdc_device *lcdc_dev =
3466             container_of(dev_drv, struct lcdc_device, driver);
3467         u32 mask, val;
3468
3469         spin_lock(&lcdc_dev->reg_lock);
3470         if(lcdc_dev->clk_on) {
3471                 switch (mode) {
3472                 case BRIGHTNESS:
3473                 /*from 0 to 255,typical is 128*/
3474                         if (value < 0x80)
3475                                 value += 0x80;
3476                         else if (value >= 0x80)
3477                                 value = value - 0x80;
3478                         mask =  m_BCSH_BRIGHTNESS;
3479                         val = v_BCSH_BRIGHTNESS(value);
3480                         break;
3481                 case CONTRAST:
3482                 /*from 0 to 510,typical is 256*/
3483                         mask =  m_BCSH_CONTRAST;
3484                         val =  v_BCSH_CONTRAST(value);
3485                         break;
3486                 case SAT_CON:
3487                 /*from 0 to 1015,typical is 256*/
3488                         mask = m_BCSH_SAT_CON;
3489                         val = v_BCSH_SAT_CON(value);
3490                         break;
3491                 default:
3492                         break;
3493                 }
3494                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
3495                 lcdc_cfg_done(lcdc_dev);
3496         }
3497         spin_unlock(&lcdc_dev->reg_lock);
3498         return val;
3499 }
3500
3501 static int rk3288_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode)
3502 {
3503         struct lcdc_device *lcdc_dev =
3504             container_of(dev_drv, struct lcdc_device, driver);
3505         u32 val;
3506
3507         spin_lock(&lcdc_dev->reg_lock);
3508         if(lcdc_dev->clk_on) {
3509                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
3510                 switch (mode) {
3511                 case BRIGHTNESS:
3512                         val &= m_BCSH_BRIGHTNESS;
3513                         if(val > 0x80)
3514                                 val -= 0x80;
3515                         else
3516                                 val += 0x80;
3517                         break;
3518                 case CONTRAST:
3519                         val &= m_BCSH_CONTRAST;
3520                         val >>= 8;
3521                         break;
3522                 case SAT_CON:
3523                         val &= m_BCSH_SAT_CON;
3524                         val >>= 20;
3525                         break;
3526                 default:
3527                         break;
3528                 }
3529         }
3530         spin_unlock(&lcdc_dev->reg_lock);
3531         return val;
3532 }
3533
3534
3535 static int rk3288_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
3536 {
3537         struct lcdc_device *lcdc_dev =
3538             container_of(dev_drv, struct lcdc_device, driver);
3539         u32 mask, val;
3540
3541         spin_lock(&lcdc_dev->reg_lock);
3542         if (lcdc_dev->clk_on) {
3543                 if (open) {
3544                         lcdc_writel(lcdc_dev,BCSH_COLOR_BAR,0x1);
3545                         lcdc_writel(lcdc_dev,BCSH_BCS,0xd0010000);
3546                         lcdc_writel(lcdc_dev,BCSH_H,0x01000000);
3547                 } else {
3548                         mask = m_BCSH_EN;
3549                         val = v_BCSH_EN(0);
3550                         lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
3551                 }
3552                 lcdc_cfg_done(lcdc_dev);
3553         }
3554         spin_unlock(&lcdc_dev->reg_lock);
3555         return 0;
3556 }
3557
3558 static int rk3288_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv,
3559                                      bool enable)
3560 {
3561         if (!enable || !dev_drv->bcsh.enable) {
3562                 rk3288_lcdc_open_bcsh(dev_drv, false);
3563                 return 0;
3564         }
3565
3566         if (dev_drv->bcsh.brightness <= 255 ||
3567             dev_drv->bcsh.contrast <= 510 ||
3568             dev_drv->bcsh.sat_con <= 1015 ||
3569             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
3570                 rk3288_lcdc_open_bcsh(dev_drv, true);
3571                 if (dev_drv->bcsh.brightness <= 255)
3572                         rk3288_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
3573                                                  dev_drv->bcsh.brightness);
3574                 if (dev_drv->bcsh.contrast <= 510)
3575                         rk3288_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
3576                                                  dev_drv->bcsh.contrast);
3577                 if (dev_drv->bcsh.sat_con <= 1015)
3578                         rk3288_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
3579                                                  dev_drv->bcsh.sat_con);
3580                 if (dev_drv->bcsh.sin_hue <= 511 &&
3581                     dev_drv->bcsh.cos_hue <= 511)
3582                         rk3288_lcdc_set_bcsh_hue(dev_drv,
3583                                                  dev_drv->bcsh.sin_hue,
3584                                                  dev_drv->bcsh.cos_hue);
3585         }
3586         return 0;
3587 }
3588
3589 static struct rk_lcdc_win lcdc_win[] = {
3590         [0] = {
3591                .name = "win0",
3592                .id = 0,
3593                .support_3d = false,
3594                },
3595         [1] = {
3596                .name = "win1",
3597                .id = 1,
3598                .support_3d = false,
3599                },
3600         [2] = {
3601                .name = "win2",
3602                .id = 2,
3603                .support_3d = false,
3604                },
3605         [3] = {
3606                .name = "win3",
3607                .id = 3,
3608                .support_3d = false,
3609                },
3610 };
3611
3612 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
3613         .open                   = rk3288_lcdc_open,
3614         .win_direct_en          = rk3288_lcdc_win_direct_en,
3615         .load_screen            = rk3288_load_screen,
3616         .get_dspbuf_info        = rk3288_get_dspbuf_info,
3617         .post_dspbuf            = rk3288_post_dspbuf,
3618         .set_par                = rk3288_lcdc_set_par,
3619         .pan_display            = rk3288_lcdc_pan_display,
3620         .direct_set_addr        = rk3288_lcdc_direct_set_win_addr,
3621         .lcdc_reg_update        = rk3288_lcdc_reg_update,
3622         .blank                  = rk3288_lcdc_blank,
3623         .ioctl                  = rk3288_lcdc_ioctl,
3624         .suspend                = rk3288_lcdc_early_suspend,
3625         .resume                 = rk3288_lcdc_early_resume,
3626         .get_win_state          = rk3288_lcdc_get_win_state,
3627         .ovl_mgr                = rk3288_lcdc_ovl_mgr,
3628         .get_disp_info          = rk3288_lcdc_get_disp_info,
3629         .fps_mgr                = rk3288_lcdc_fps_mgr,
3630         .fb_get_win_id          = rk3288_lcdc_get_win_id,
3631         .fb_win_remap           = rk3288_fb_win_remap,
3632         .set_dsp_lut            = rk3288_set_dsp_lut,
3633         .poll_vblank            = rk3288_lcdc_poll_vblank,
3634         .dpi_open               = rk3288_lcdc_dpi_open,
3635         .dpi_win_sel            = rk3288_lcdc_dpi_win_sel,
3636         .dpi_status             = rk3288_lcdc_dpi_status,
3637         .get_dsp_addr           = rk3288_lcdc_get_dsp_addr,
3638         .set_dsp_cabc           = rk3288_lcdc_set_dsp_cabc,
3639         .set_dsp_bcsh_hue       = rk3288_lcdc_set_bcsh_hue,
3640         .set_dsp_bcsh_bcs       = rk3288_lcdc_set_bcsh_bcs,
3641         .get_dsp_bcsh_hue       = rk3288_lcdc_get_bcsh_hue,
3642         .get_dsp_bcsh_bcs       = rk3288_lcdc_get_bcsh_bcs,
3643         .open_bcsh              = rk3288_lcdc_open_bcsh,
3644         .dump_reg               = rk3288_lcdc_reg_dump,
3645         .cfg_done               = rk3288_lcdc_config_done,
3646         .set_irq_to_cpu         = rk3288_lcdc_set_irq_to_cpu,
3647 };
3648
3649 #ifdef LCDC_IRQ_DEBUG
3650 static int rk3288_lcdc_parse_irq(struct lcdc_device *lcdc_dev,unsigned int reg_val)
3651 {
3652         if (reg_val & m_WIN0_EMPTY_INTR_STS) {
3653                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN0_EMPTY_INTR_CLR,
3654                              v_WIN0_EMPTY_INTR_CLR(1));
3655                 dev_warn(lcdc_dev->dev,"win0 empty irq!");
3656         }else if (reg_val & m_WIN1_EMPTY_INTR_STS) {
3657                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN1_EMPTY_INTR_CLR,
3658                              v_WIN1_EMPTY_INTR_CLR(1));
3659                 dev_warn(lcdc_dev->dev,"win1 empty irq!");
3660         }else if (reg_val & m_WIN2_EMPTY_INTR_STS) {
3661                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN2_EMPTY_INTR_CLR,
3662                              v_WIN2_EMPTY_INTR_CLR(1));
3663                 dev_warn(lcdc_dev->dev,"win2 empty irq!");
3664         }else if (reg_val & m_WIN3_EMPTY_INTR_STS) {
3665                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN3_EMPTY_INTR_CLR,
3666                              v_WIN3_EMPTY_INTR_CLR(1));
3667                 dev_warn(lcdc_dev->dev,"win3 empty irq!");
3668         }else if (reg_val & m_HWC_EMPTY_INTR_STS) {
3669                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_HWC_EMPTY_INTR_CLR,
3670                              v_HWC_EMPTY_INTR_CLR(1));
3671                 dev_warn(lcdc_dev->dev,"HWC empty irq!");
3672         }else if (reg_val & m_POST_BUF_EMPTY_INTR_STS) {
3673                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_POST_BUF_EMPTY_INTR_CLR,
3674                              v_POST_BUF_EMPTY_INTR_CLR(1));
3675                 dev_warn(lcdc_dev->dev,"post buf empty irq!");
3676         }else if (reg_val & m_PWM_GEN_INTR_STS) {
3677                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_PWM_GEN_INTR_CLR,
3678                              v_PWM_GEN_INTR_CLR(1));
3679                 dev_warn(lcdc_dev->dev,"PWM gen irq!");
3680         }
3681
3682         return 0;
3683 }
3684 #endif
3685
3686 static irqreturn_t rk3288_lcdc_isr(int irq, void *dev_id)
3687 {
3688         struct lcdc_device *lcdc_dev =
3689             (struct lcdc_device *)dev_id;
3690         ktime_t timestamp = ktime_get();
3691         u32 intr0_reg;
3692
3693         intr0_reg = lcdc_readl(lcdc_dev, INTR_CTRL0);
3694
3695         if(intr0_reg & m_FS_INTR_STS){
3696                 timestamp = ktime_get();
3697                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_FS_INTR_CLR,
3698                              v_FS_INTR_CLR(1));
3699                 /*if(lcdc_dev->driver.wait_fs){ */
3700                 if (0) {
3701                         spin_lock(&(lcdc_dev->driver.cpl_lock));
3702                         complete(&(lcdc_dev->driver.frame_done));
3703                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
3704                 }
3705 #ifdef CONFIG_DRM_ROCKCHIP
3706                 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
3707 #endif
3708                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
3709                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
3710
3711         }else if(intr0_reg & m_LINE_FLAG_INTR_STS){
3712                 lcdc_dev->driver.frame_time.last_framedone_t =
3713                                 lcdc_dev->driver.frame_time.framedone_t;
3714                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3715                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR,
3716                              v_LINE_FLAG_INTR_CLR(1));
3717         }else if(intr0_reg & m_BUS_ERROR_INTR_STS){
3718                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_BUS_ERROR_INTR_CLR,
3719                              v_BUS_ERROR_INTR_CLR(1));
3720                 dev_warn(lcdc_dev->dev,"buf_error_int!");
3721         }
3722
3723         /* for win empty debug */
3724 #ifdef LCDC_IRQ_EMPTY_DEBUG
3725         intr1_reg = lcdc_readl(lcdc_dev, INTR_CTRL1);
3726         if (intr1_reg != 0) {
3727                 rk3288_lcdc_parse_irq(lcdc_dev,intr1_reg);
3728         }
3729 #endif
3730         return IRQ_HANDLED;
3731 }
3732
3733 #if defined(CONFIG_PM)
3734 static int rk3288_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
3735 {
3736         return 0;
3737 }
3738
3739 static int rk3288_lcdc_resume(struct platform_device *pdev)
3740 {
3741         return 0;
3742 }
3743 #else
3744 #define rk3288_lcdc_suspend NULL
3745 #define rk3288_lcdc_resume  NULL
3746 #endif
3747
3748 static int rk3288_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
3749 {
3750         struct device_node *np = lcdc_dev->dev->of_node;
3751         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
3752         int val;
3753
3754         if (of_property_read_u32(np, "rockchip,prop", &val))
3755                 lcdc_dev->prop = PRMRY; /*default set it as primary */
3756         else
3757                 lcdc_dev->prop = val;
3758
3759         if (of_property_read_u32(np, "rockchip,mirror", &val))
3760                 dev_drv->rotate_mode = NO_MIRROR;
3761         else
3762                 dev_drv->rotate_mode = val;
3763
3764         if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
3765                 dev_drv->cabc_mode = 0; /* default set close cabc */
3766         else
3767                 dev_drv->cabc_mode = val;
3768
3769         if (of_property_read_u32(np, "rockchip,pwr18", &val))
3770                 lcdc_dev->pwr18 = false;        /*default set it as 3.xv power supply */
3771         else
3772                 lcdc_dev->pwr18 = (val ? true : false);
3773
3774         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
3775                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
3776         else
3777                 dev_drv->fb_win_map = val;
3778
3779         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
3780                 dev_drv->bcsh.enable = false;
3781         else
3782                 dev_drv->bcsh.enable = (val ? true : false);
3783
3784         if (of_property_read_u32(np, "rockchip,brightness", &val))
3785                 dev_drv->bcsh.brightness = 0xffff;
3786         else
3787                 dev_drv->bcsh.brightness = val;
3788
3789         if (of_property_read_u32(np, "rockchip,contrast", &val))
3790                 dev_drv->bcsh.contrast = 0xffff;
3791         else
3792                 dev_drv->bcsh.contrast = val;
3793
3794         if (of_property_read_u32(np, "rockchip,sat-con", &val))
3795                 dev_drv->bcsh.sat_con = 0xffff;
3796         else
3797                 dev_drv->bcsh.sat_con = val;
3798
3799         if (of_property_read_u32(np, "rockchip,hue", &val)) {
3800                 dev_drv->bcsh.sin_hue = 0xffff;
3801                 dev_drv->bcsh.cos_hue = 0xffff;
3802         } else {
3803                 dev_drv->bcsh.sin_hue = val & 0xff;
3804                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
3805         }
3806
3807 #if defined(CONFIG_ROCKCHIP_IOMMU)
3808         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
3809                 dev_drv->iommu_enabled = 0;
3810         else
3811                 dev_drv->iommu_enabled = val;
3812 #else
3813         dev_drv->iommu_enabled = 0;
3814 #endif
3815         return 0;
3816 }
3817
3818 static int rk3288_lcdc_probe(struct platform_device *pdev)
3819 {
3820         struct lcdc_device *lcdc_dev = NULL;
3821         struct rk_lcdc_driver *dev_drv;
3822         struct device *dev = &pdev->dev;
3823         struct resource *res;
3824         struct device_node *np = pdev->dev.of_node;
3825         int prop;
3826         int ret = 0;
3827
3828         /*if the primary lcdc has not registered ,the extend
3829            lcdc register later */
3830         of_property_read_u32(np, "rockchip,prop", &prop);
3831         if (prop == EXTEND) {
3832                 if (!is_prmry_rk_lcdc_registered())
3833                         return -EPROBE_DEFER;
3834         }
3835         lcdc_dev = devm_kzalloc(dev,
3836                                 sizeof(struct lcdc_device), GFP_KERNEL);
3837         if (!lcdc_dev) {
3838                 dev_err(&pdev->dev, "rk3288 lcdc device kmalloc fail!");
3839                 return -ENOMEM;
3840         }
3841         platform_set_drvdata(pdev, lcdc_dev);
3842         lcdc_dev->dev = dev;
3843         rk3288_lcdc_parse_dt(lcdc_dev);
3844         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3845         lcdc_dev->reg_phy_base = res->start;
3846         lcdc_dev->len = resource_size(res);
3847         lcdc_dev->regs = devm_ioremap_resource(dev, res);
3848         if (IS_ERR(lcdc_dev->regs))
3849                 return PTR_ERR(lcdc_dev->regs);
3850
3851         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
3852         if (IS_ERR(lcdc_dev->regsbak))
3853                 return PTR_ERR(lcdc_dev->regsbak);
3854         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
3855         lcdc_dev->id = rk3288_lcdc_get_id(lcdc_dev->reg_phy_base);
3856         if (lcdc_dev->id < 0) {
3857                 dev_err(&pdev->dev, "no such lcdc device!\n");
3858                 return -ENXIO;
3859         }
3860         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
3861         dev_drv = &lcdc_dev->driver;
3862         dev_drv->dev = dev;
3863         dev_drv->prop = prop;
3864         dev_drv->id = lcdc_dev->id;
3865         dev_drv->ops = &lcdc_drv_ops;
3866         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
3867         spin_lock_init(&lcdc_dev->reg_lock);
3868
3869         lcdc_dev->irq = platform_get_irq(pdev, 0);
3870         if (lcdc_dev->irq < 0) {
3871                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
3872                         lcdc_dev->id);
3873                 return -ENXIO;
3874         }
3875
3876         ret = devm_request_irq(dev, lcdc_dev->irq, rk3288_lcdc_isr,
3877                                IRQF_DISABLED | IRQF_SHARED, dev_name(dev), lcdc_dev);
3878         if (ret) {
3879                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
3880                         lcdc_dev->irq, ret);
3881                 return ret;
3882         }
3883
3884         if (dev_drv->iommu_enabled) {
3885                 if(lcdc_dev->id == 0){
3886                         strcpy(dev_drv->mmu_dts_name, VOPB_IOMMU_COMPATIBLE_NAME);
3887                 }else{
3888                         strcpy(dev_drv->mmu_dts_name, VOPL_IOMMU_COMPATIBLE_NAME);
3889                 }
3890         }
3891
3892         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
3893         if (ret < 0) {
3894                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
3895                 return ret;
3896         }
3897         lcdc_dev->screen = dev_drv->screen0;
3898         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
3899                 lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
3900
3901         return 0;
3902 }
3903
3904 static int rk3288_lcdc_remove(struct platform_device *pdev)
3905 {
3906
3907         return 0;
3908 }
3909
3910 static void rk3288_lcdc_shutdown(struct platform_device *pdev)
3911 {
3912         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
3913
3914         rk3288_lcdc_deint(lcdc_dev);
3915         rk_disp_pwr_disable(&lcdc_dev->driver);
3916 }
3917
3918 #if defined(CONFIG_OF)
3919 static const struct of_device_id rk3288_lcdc_dt_ids[] = {
3920         {.compatible = "rockchip,rk3288-lcdc",},
3921         {}
3922 };
3923 #endif
3924
3925 static struct platform_driver rk3288_lcdc_driver = {
3926         .probe = rk3288_lcdc_probe,
3927         .remove = rk3288_lcdc_remove,
3928         .driver = {
3929                    .name = "rk3288-lcdc",
3930                    .owner = THIS_MODULE,
3931                    .of_match_table = of_match_ptr(rk3288_lcdc_dt_ids),
3932                    },
3933         .suspend = rk3288_lcdc_suspend,
3934         .resume = rk3288_lcdc_resume,
3935         .shutdown = rk3288_lcdc_shutdown,
3936 };
3937
3938 static int __init rk3288_lcdc_module_init(void)
3939 {
3940         return platform_driver_register(&rk3288_lcdc_driver);
3941 }
3942
3943 static void __exit rk3288_lcdc_module_exit(void)
3944 {
3945         platform_driver_unregister(&rk3288_lcdc_driver);
3946 }
3947
3948 fs_initcall(rk3288_lcdc_module_init);
3949 module_exit(rk3288_lcdc_module_exit);
3950
3951