4 #include<linux/rk_fb.h>
7 #include<linux/mfd/syscon.h>
8 #include<linux/regmap.h>
10 #define VOP_INPUT_MAX_WIDTH 4096
12 * Registers in this file
13 * REG_CFG_DONE: Register config done flag
14 * VERSION_INFO: Version for vop
15 * SYS_CTRL: System control register0
16 * SYS_CTRL1: System control register1
17 * DSP_CTRL0: Display control register0
18 * DSP_CTRL1: Display control register1
19 * DSP_BG: Background color
20 * MCU_CTRL: MCU mode control register
21 * WB_CTRL0: write back ctrl0
22 * WB_CTRL1: write back ctrl1
23 * WB_YRGB_MST: write back yrgb mst
24 * WB_CBR_MST: write back cbr mst
25 * WIN0_CTRL0: Win0 ctrl register0
26 * WIN0_CTRL1: Win0 ctrl register1
27 * WIN0_COLOR_KEY: Win0 color key register
28 * WIN0_VIR: Win0 virtual stride
29 * WIN0_YRGB_MST: Win0 YRGB memory start address
30 * WIN0_CBR_MST: Win0 Cbr memory start address
31 * WIN0_ACT_INFO: Win0 active window width/height
32 * WIN0_DSP_INFO: Win0 display width/height on panel
33 * WIN0_DSP_ST: Win0 display start point on panel
34 * WIN0_SCL_FACTOR_YRGB: Win0 YRGB scaling factor
35 * WIN0_SCL_FACTOR_CBR: Win0 Cbr scaling factor
36 * WIN0_SCL_OFFSET: Win0 scaling start point offset
37 * WIN0_SRC_ALPHA_CTRL: Win0 alpha source control register
38 * WIN0_DST_ALPHA_CTRL: Win0 alpha destination control register
39 * WIN0_FADING_CTRL: Win0 fading contrl register
40 * WIN0_CTRL2: Win0 ctrl register2
41 * WIN1_CTRL0: Win1 ctrl register0
42 * WIN1_CTRL1: Win1 ctrl register1
43 * WIN1_COLOR_KEY: Win1 color key register
44 * WIN1_VIR: win1 virtual stride
45 * WIN1_YRGB_MST: Win1 YRGB memory start address
46 * WIN1_CBR_MST: Win1 Cbr memory start address
47 * WIN1_ACT_INFO: Win1 active window width/height
48 * WIN1_DSP_INFO: Win1 display width/height on panel
49 * WIN1_DSP_ST: Win1 display start point on panel
50 * WIN1_SCL_FACTOR_YRGB: Win1 YRGB scaling factor
51 * WIN1_SCL_FACTOR_CBR: Win1 Cbr scaling factor
52 * WIN1_SCL_OFFSET: Win1 scaling start point offset
53 * WIN1_SRC_ALPHA_CTRL: Win1 alpha source control register
54 * WIN1_DST_ALPHA_CTRL: Win1 alpha destination control register
55 * WIN1_FADING_CTRL: Win1 fading contrl register
56 * WIN1_CTRL2: Win1 ctrl register2
57 * WIN2_CTRL0: win2 ctrl register0
58 * WIN2_CTRL1: win2 ctrl register1
59 * WIN2_VIR0_1: Win2 virtual stride0 and virtaul stride1
60 * WIN2_VIR2_3: Win2 virtual stride2 and virtaul stride3
61 * WIN2_MST0: Win2 memory start address0
62 * WIN2_DSP_INFO0: Win2 display width0/height0 on panel
63 * WIN2_DSP_ST0: Win2 display start point0 on panel
64 * WIN2_COLOR_KEY: Win2 color key register
65 * WIN2_MST1: Win2 memory start address1
66 * WIN2_DSP_INFO1: Win2 display width1/height1 on panel
67 * WIN2_DSP_ST1: Win2 display start point1 on panel
68 * WIN2_SRC_ALPHA_CTRL: Win2 alpha source control register
69 * WIN2_MST2: Win2 memory start address2
70 * WIN2_DSP_INFO2: Win2 display width2/height2 on panel
71 * WIN2_DSP_ST2: Win2 display start point2 on panel
72 * WIN2_DST_ALPHA_CTRL: Win2 alpha destination control register
73 * WIN2_MST3: Win2 memory start address3
74 * WIN2_DSP_INFO3: Win2 display width3/height3 on panel
75 * WIN2_DSP_ST3: Win2 display start point3 on panel
76 * WIN2_FADING_CTRL: Win2 fading contrl register
77 * WIN3_CTRL0: Win3 ctrl register0
78 * WIN3_CTRL1: Win3 ctrl register1
79 * WIN3_VIR0_1: Win3 virtual stride0 and virtaul stride1
80 * WIN3_VIR2_3: Win3 virtual stride2 and virtaul stride3
81 * WIN3_MST0: Win3 memory start address0
82 * WIN3_DSP_INFO0: Win3 display width0/height0 on panel
83 * WIN3_DSP_ST0: Win3 display start point0 on panel
84 * WIN3_COLOR_KEY: Win3 color key register
85 * WIN3_MST1: Win3 memory start address1
86 * WIN3_DSP_INFO1: Win3 display width1/height1 on panel
87 * WIN3_DSP_ST1: Win3 display start point1 on panel
88 * WIN3_SRC_ALPHA_CTRL: Win3 alpha source control register
89 * WIN3_MST2: Win3 memory start address2
90 * WIN3_DSP_INFO2: Win3 display width2/height2 on panel
91 * WIN3_DSP_ST2: Win3 display start point2 on panel
92 * WIN3_DST_ALPHA_CTRL: Win3 alpha destination control register
93 * WIN3_MST3: Win3 memory start address3
94 * WIN3_DSP_INFO3: Win3 display width3/height3 on panel
95 * WIN3_DSP_ST3: Win3 display start point3 on panel
96 * WIN3_FADING_CTRL: Win3 fading contrl register
97 * HWC_CTRL0: Hwc ctrl register0
98 * HWC_CTRL1: Hwc ctrl register1
99 * HWC_MST: Hwc memory start address
100 * HWC_DSP_ST: Hwc display start point on panel
101 * HWC_SRC_ALPHA_CTRL: Hwc alpha source control register
102 * HWC_DST_ALPHA_CTRL: Hwc alpha destination control register
103 * HWC_FADING_CTRL: Hwc fading contrl register
104 * HWC_RESERVED1: Hwc reserved
105 * POST_DSP_HACT_INFO: Post scaler down horizontal start and end
106 * POST_DSP_VACT_INFO: Panel active horizontal scanning start point
108 * POST_SCL_FACTOR_YRGB: Post yrgb scaling factor
109 * POST_RESERVED: Post reserved
110 * POST_SCL_CTRL: Post scaling start point offset
111 * POST_DSP_VACT_INFO_F1: Panel active horizontal scanning start point
113 * DSP_HTOTAL_HS_END: Panel scanning horizontal width and hsync pulse end point
114 * DSP_HACT_ST_END: Panel active horizontal scanning start point and end point
115 * DSP_VTOTAL_VS_END: Panel scanning vertical height and vsync pulse end point
116 * DSP_VACT_ST_END: Panel active vertical scanning start point and end point
117 * DSP_VS_ST_END_F1: Vertical scanning start point and vsync pulse end point
118 * of even filed in interlace mode
119 * DSP_VACT_ST_END_F1: Vertical scanning active start point and end point of
120 * even filed in interlace mode
121 * PWM_CTRL: PWM Control Register
122 * PWM_PERIOD_HPR: PWM Period Register/High Polarity Capture Register
123 * PWM_DUTY_LPR: PWM Duty Register/Low Polarity Capture Register
124 * PWM_CNT: PWM Counter Register
125 * BCSH_COLOR_BAR: Color bar config register
126 * BCSH_BCS: Brightness contrast saturation*contrast config register
127 * BCSH_H: Sin hue and cos hue config register
128 * BCSH_CTRL: BCSH contrl register
129 * CABC_CTRL0: Content Adaptive Backlight Control register0
130 * CABC_CTRL1: Content Adaptive Backlight Control register1
131 * CABC_CTRL2: Content Adaptive Backlight Control register2
132 * CABC_CTRL3: Content Adaptive Backlight Control register3
133 * CABC_GAUSS_LINE0_0: CABC gauss line config register00
134 * CABC_GAUSS_LINE0_1: CABC gauss line config register01
135 * CABC_GAUSS_LINE1_0: CABC gauss line config register10
136 * CABC_GAUSS_LINE1_1: CABC gauss line config register11
137 * CABC_GAUSS_LINE2_0: CABC gauss line config register20
138 * CABC_GAUSS_LINE2_1: CABC gauss line config register21
139 * FRC_LOWER01_0: FRC lookup table config register010
140 * FRC_LOWER01_1: FRC lookup table config register011
141 * FRC_LOWER10_0: FRC lookup table config register100
142 * FRC_LOWER10_1: FRC lookup table config register101
143 * FRC_LOWER11_0: FRC lookup table config register110
144 * FRC_LOWER11_1: FRC lookup table config register111
161 * INTR_EN0: Interrupt enable register
162 * INTR_CLEAR0: Interrupt clear register
163 * INTR_STATUS0: interrupt status
164 * INTR_RAW_STATUS0: raw interrupt status
165 * INTR_EN1: Interrupt enable register
166 * INTR_CLEAR1: Interrupt clear register
167 * INTR_STATUS1: interrupt status
168 * INTR_RAW_STATUS1: raw interrupt status
169 * LINE_FLAG: Line flag config register
170 * VOP_STATUS: vop status register
171 * BLANKING_VALUE: Register0000 Abstract
172 * MCU_BYPASS_PORT: Mcu bypass value
173 * WIN0_DSP_BG: Win0 layer background color
174 * WIN1_DSP_BG: Win1 layer background color
175 * WIN2_DSP_BG: Win2 layer background color
176 * WIN3_DSP_BG: Win3 layer background color
177 * YUV2YUV_WIN: YUV to YUV win
178 * YUV2YUV_POST: Post YUV to YUV
179 * AUTO_GATING_EN: Auto gating enable
180 * DBG_PERF_LATENCY_CTRL0: Axi performance latency module contrl register0
181 * DBG_PERF_RD_MAX_LATENCY_NUM0: Read max latency number
182 * DBG_PERF_RD_LATENCY_THR_NUM0: The number of bigger than configed
184 * DBG_PERF_RD_LATENCY_SAMP_NUM0: Total sample number
185 * DBG_CABC0: CABC debug register0
186 * DBG_CABC1: CABC debug register1
187 * DBG_CABC2: CABC debug register2
188 * DBG_CABC3: CABC debug register3
189 * DBG_WIN0_REG0: Vop debug win0 register0
190 * DBG_WIN0_REG1: Vop debug win0 register1
191 * DBG_WIN0_REG2: Vop debug win0 register2
192 * DBG_WIN0_RESERVED: Vop debug win0 register3 reserved
193 * DBG_WIN1_REG0: Vop debug win1 register0
194 * DBG_WIN1_REG1: Vop debug win1 register1
195 * DBG_WIN1_REG2: Vop debug win1 register2
196 * DBG_WIN1_RESERVED: Vop debug win1 register3 reserved
197 * DBG_WIN2_REG0: Vop debug win2 register0
198 * DBG_WIN2_REG1: Vop debug win2 register1
199 * DBG_WIN2_REG2: Vop debug win2 register2
200 * DBG_WIN2_REG3: Vop debug win2 register3
201 * DBG_WIN3_REG0: Vop debug win3 register0
202 * DBG_WIN3_REG1: Vop debug win3 register1
203 * DBG_WIN3_REG2: Vop debug win3 register2
204 * DBG_WIN3_REG3: Vop debug win3 register3
205 * DBG_PRE_REG0: Vop debug pre register0
206 * DBG_PRE_RESERVED: Vop debug pre register1 reserved
207 * DBG_POST_REG0: Vop debug post register0
208 * DBG_POST_REG1: Vop debug
209 * DBG_DATAO: debug data output path
210 * DBG_DATAO_2: debug data output path 2
211 * WIN2_LUT_ADDR: Win2 lut base address
212 * WIN3_LUT_ADDR: Win3 lut base address
213 * HWC_LUT_ADDR: Hwc lut base address
214 * GAMMA0_LUT_ADDR: GAMMA lut base address
215 * GAMMA1_LUT_ADDR: GAMMA lut base address
216 * CABC_GAMMA_LUT_ADDR: CABC GAMMA lut base address
221 static inline u64 val_mask(int val, u64 msk, int shift)
223 return (msk << (shift + 32)) | ((msk & val) << shift);
226 #define VAL_MASK(x, width, shift) val_mask(x, (1 << width) - 1, shift)
228 #define MASK(x) (V_##x(0) >> 32)
230 #define REG_CFG_DONE 0x00000000
231 #define V_REG_LOAD_EN(x) VAL_MASK(x, 1, 0)
232 #define V_REG_LOAD_WIN0_EN(x) VAL_MASK(x, 1, 1)
233 #define V_REG_LOAD_WIN1_EN(x) VAL_MASK(x, 1, 2)
234 #define V_REG_LOAD_WIN2_EN(x) VAL_MASK(x, 1, 3)
235 #define V_REG_LOAD_WIN3_EN(x) VAL_MASK(x, 1, 4)
236 #define V_REG_LOAD_HWC_EN(x) VAL_MASK(x, 1, 5)
237 #define V_REG_LOAD_IEP_EN(x) VAL_MASK(x, 1, 6)
238 #define V_REG_LOAD_FBDC_EN(x) VAL_MASK(x, 1, 7)
239 #define V_REG_LOAD_SYS_EN(x) VAL_MASK(x, 1, 8)
240 #define V_WRITE_MASK(x) VAL_MASK(x, 16, 16)
241 #define VERSION_INFO 0x00000004
242 #define V_SVNBUILD(x) VAL_MASK(x, 16, 0)
243 #define V_MINOR(x) VAL_MASK(x, 8, 16)
244 #define V_MAJOR(x) VAL_MASK(x, 8, 24)
245 #define SYS_CTRL 0x00000008
246 #define V_DIRECT_PATH_EN(x) VAL_MASK(x, 1, 0)
247 #define V_DIRECT_PATH_LAYER_SEL(x) VAL_MASK(x, 2, 1)
248 #define V_EDPI_HALT_EN(x) VAL_MASK(x, 1, 8)
249 #define V_EDPI_WMS_MODE(x) VAL_MASK(x, 1, 9)
250 #define V_EDPI_WMS_FS(x) VAL_MASK(x, 1, 10)
251 #define V_GLOBAL_REGDONE_EN(x) VAL_MASK(x, 1, 11)
252 #define V_RGB_OUT_EN(x) VAL_MASK(x, 1, 12)
253 #define V_HDMI_OUT_EN(x) VAL_MASK(x, 1, 13)
254 #define V_EDP_OUT_EN(x) VAL_MASK(x, 1, 14)
255 #define V_MIPI_OUT_EN(x) VAL_MASK(x, 1, 15)
256 #define V_OVERLAY_MODE(x) VAL_MASK(x, 1, 16)
258 #define V_FS_SAME_ADDR_MASK_EN(x) VAL_MASK(x, 1, 17)
259 #define V_POST_LB_MODE(x) VAL_MASK(x, 1, 18)
260 #define V_WIN23_PRI_OPT_MODE(x) VAL_MASK(x, 1, 19)
262 #define V_VOP_MMU_EN(x) VAL_MASK(x, 1, 20)
264 #define V_VOP_FIELD_TVE_TIMING_POL(x) VAL_MASK(x, 1, 20)
265 #define V_VOP_DMA_STOP(x) VAL_MASK(x, 1, 21)
266 #define V_VOP_STANDBY_EN(x) VAL_MASK(x, 1, 22)
267 #define V_AUTO_GATING_EN(x) VAL_MASK(x, 1, 23)
268 #define V_SW_IMD_TVE_DCLK_EN(x) VAL_MASK(x, 1, 24)
269 #define V_SW_IMD_TVE_DCLK_POL(x) VAL_MASK(x, 1, 25)
270 #define V_SW_TVE_MODE(x) VAL_MASK(x, 1, 26)
271 #define V_SW_UV_OFFSET_EN(x) VAL_MASK(x, 1, 27)
272 #define V_SW_GENLOCK(x) VAL_MASK(x, 1, 28)
273 #define V_SW_DAC_SEL(x) VAL_MASK(x, 1, 29)
274 #define V_VOP_FIELD_TVE_POL(x) VAL_MASK(x, 1, 30)
275 #define V_IO_PAD_CLK_SEL(x) VAL_MASK(x, 1, 31)
276 #define SYS_CTRL1 0x0000000c
277 #define V_NOC_HURRY_EN(x) VAL_MASK(x, 1, 0)
278 #define V_NOC_HURRY_VALUE(x) VAL_MASK(x, 2, 1)
279 #define V_NOC_HURRY_THRESHOLD(x) VAL_MASK(x, 6, 3)
280 #define V_NOC_QOS_EN(x) VAL_MASK(x, 1, 9)
281 #define V_NOC_WIN_QOS(x) VAL_MASK(x, 2, 10)
282 #define V_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 12)
283 #define V_AXI_OUTSTANDING_MAX_NUM(x) VAL_MASK(x, 5, 13)
284 #define V_NOC_HURRY_W_MODE(x) VAL_MASK(x, 2, 20)
285 #define V_NOC_HURRY_W_VALUE(x) VAL_MASK(x, 2, 22)
286 #define V_REG_DONE_FRM(x) VAL_MASK(x, 1, 24)
287 #define V_DSP_FP_STANDBY(x) VAL_MASK(x, 1, 31)
288 #define DSP_CTRL0 0x00000010
289 #define V_DSP_OUT_MODE(x) VAL_MASK(x, 4, 0)
290 #define V_SW_CORE_DCLK_SEL(x) VAL_MASK(x, 1, 4)
292 #define V_SW_HDMI_CLK_I_SEL(x) VAL_MASK(x, 1, 5)
294 #define V_P2I_EN(x) VAL_MASK(x, 1, 5)
295 #define V_DSP_DCLK_DDR(x) VAL_MASK(x, 1, 8)
296 #define V_DSP_DDR_PHASE(x) VAL_MASK(x, 1, 9)
297 #define V_DSP_INTERLACE(x) VAL_MASK(x, 1, 10)
298 #define V_DSP_FIELD_POL(x) VAL_MASK(x, 1, 11)
299 #define V_DSP_BG_SWAP(x) VAL_MASK(x, 1, 12)
300 #define V_DSP_RB_SWAP(x) VAL_MASK(x, 1, 13)
301 #define V_DSP_RG_SWAP(x) VAL_MASK(x, 1, 14)
302 #define V_DSP_DELTA_SWAP(x) VAL_MASK(x, 1, 15)
303 #define V_DSP_DUMMY_SWAP(x) VAL_MASK(x, 1, 16)
304 #define V_DSP_OUT_ZERO(x) VAL_MASK(x, 1, 17)
305 #define V_DSP_BLANK_EN(x) VAL_MASK(x, 1, 18)
306 #define V_DSP_BLACK_EN(x) VAL_MASK(x, 1, 19)
307 #define V_DSP_CCIR656_AVG(x) VAL_MASK(x, 1, 20)
308 #define V_DSP_YUV_CLIP(x) VAL_MASK(x, 1, 21)
309 #define V_DSP_X_MIR_EN(x) VAL_MASK(x, 1, 22)
310 #define V_DSP_Y_MIR_EN(x) VAL_MASK(x, 1, 23)
312 #define V_SW_TVE_OUTPUT_SEL(x) VAL_MASK(x, 1, 25)
313 #define V_DSP_FIELD(x) VAL_MASK(x, 1, 31)
314 #define DSP_CTRL1 0x00000014
315 #define V_DSP_LUT_EN(x) VAL_MASK(x, 1, 0)
316 #define V_PRE_DITHER_DOWN_EN(x) VAL_MASK(x, 1, 1)
317 #define V_DITHER_DOWN_EN(x) VAL_MASK(x, 1, 2)
318 #define V_DITHER_DOWN_MODE(x) VAL_MASK(x, 1, 3)
319 #define V_DITHER_DOWN_SEL(x) VAL_MASK(x, 1, 4)
320 #define V_DITHER_UP_EN(x) VAL_MASK(x, 1, 6)
321 #define V_UPDATE_GAMMA_LUT(x) VAL_MASK(x, 1, 7)
322 #define V_DSP_LAYER0_SEL(x) VAL_MASK(x, 2, 8)
323 #define V_DSP_LAYER1_SEL(x) VAL_MASK(x, 2, 10)
324 #define V_DSP_LAYER2_SEL(x) VAL_MASK(x, 2, 12)
325 #define V_DSP_LAYER3_SEL(x) VAL_MASK(x, 2, 14)
326 #define V_RGB_LVDS_HSYNC_POL(x) VAL_MASK(x, 1, 16)
327 #define V_RGB_LVDS_VSYNC_POL(x) VAL_MASK(x, 1, 17)
328 #define V_RGB_LVDS_DEN_POL(x) VAL_MASK(x, 1, 18)
329 #define V_RGB_LVDS_DCLK_POL(x) VAL_MASK(x, 1, 19)
330 #define V_HDMI_HSYNC_POL(x) VAL_MASK(x, 1, 20)
331 #define V_HDMI_VSYNC_POL(x) VAL_MASK(x, 1, 21)
332 #define V_HDMI_DEN_POL(x) VAL_MASK(x, 1, 22)
333 #define V_HDMI_DCLK_POL(x) VAL_MASK(x, 1, 23)
334 #define V_EDP_HSYNC_POL(x) VAL_MASK(x, 1, 24)
335 #define V_EDP_VSYNC_POL(x) VAL_MASK(x, 1, 25)
336 #define V_EDP_DEN_POL(x) VAL_MASK(x, 1, 26)
337 #define V_EDP_DCLK_POL(x) VAL_MASK(x, 1, 27)
338 #define V_MIPI_HSYNC_POL(x) VAL_MASK(x, 1, 28)
339 #define V_MIPI_VSYNC_POL(x) VAL_MASK(x, 1, 29)
340 #define V_MIPI_DEN_POL(x) VAL_MASK(x, 1, 30)
341 #define V_MIPI_DCLK_POL(x) VAL_MASK(x, 1, 31)
342 #define DSP_BG 0x00000018
343 #define V_DSP_BG_BLUE(x) VAL_MASK(x, 10, 0)
344 #define V_DSP_BG_GREEN(x) VAL_MASK(x, 10, 10)
345 #define V_DSP_BG_RED(x) VAL_MASK(x, 10, 20)
346 #define MCU_CTRL 0x0000001c
347 #define V_MCU_PIX_TOTAL(x) VAL_MASK(x, 6, 0)
348 #define V_MCU_CS_PST(x) VAL_MASK(x, 4, 6)
349 #define V_MCU_CS_PEND(x) VAL_MASK(x, 6, 10)
350 #define V_MCU_RW_PST(x) VAL_MASK(x, 4, 16)
351 #define V_MCU_RW_PEND(x) VAL_MASK(x, 6, 20)
352 #define V_MCU_CLK_SEL(x) VAL_MASK(x, 1, 26)
353 #define V_MCU_HOLD_MODE(x) VAL_MASK(x, 1, 27)
354 #define V_MCU_FRAME_ST(x) VAL_MASK(x, 1, 28)
355 #define V_MCU_RS(x) VAL_MASK(x, 1, 29)
356 #define V_MCU_BYPASS(x) VAL_MASK(x, 1, 30)
357 #define V_MCU_TYPE(x) VAL_MASK(x, 1, 31)
358 #define WB_CTRL0 0x00000020
359 #define V_WB_EN(x) VAL_MASK(x, 1, 0)
360 #define V_WB_FMT(x) VAL_MASK(x, 3, 1)
361 #define V_WB_DITHER_EN(x) VAL_MASK(x, 1, 4)
362 #define V_WB_RGB2YUV_EN(x) VAL_MASK(x, 1, 5)
363 #define V_WB_RGB2YUV_MODE(x) VAL_MASK(x, 1, 6)
364 #define V_WB_XPSD_BIL_EN(x) VAL_MASK(x, 1, 7)
365 #define V_WB_YTHROW_EN(x) VAL_MASK(x, 1, 8)
366 #define V_WB_YTHROW_MODE(x) VAL_MASK(x, 1, 9)
367 #define V_WB_HANDSHAKE_MODE(x) VAL_MASK(x, 1, 11)
368 #define V_WB_YRGB_ID(x) VAL_MASK(x, 4, 24)
369 #define V_WB_UV_ID(x) VAL_MASK(x, 4, 28)
370 #define WB_CTRL1 0x00000024
371 #define V_WB_WIDTH(x) VAL_MASK(x, 12, 0)
372 #define V_WB_XPSD_BIL_FACTOR(x) VAL_MASK(x, 14, 16)
373 #define WB_YRGB_MST 0x00000028
374 #define V_WB_YRGB_MST(x) VAL_MASK(x, 32, 0)
375 #define WB_CBR_MST 0x0000002c
376 #define V_WB_CBR_MST(x) VAL_MASK(x, 32, 0)
377 #define WIN0_CTRL0 0x00000030
378 #define V_WIN0_EN(x) VAL_MASK(x, 1, 0)
379 #define V_WIN0_DATA_FMT(x) VAL_MASK(x, 3, 1)
380 #define V_WIN0_FMT_10(x) VAL_MASK(x, 1, 4)
381 #define V_WIN0_LB_MODE(x) VAL_MASK(x, 3, 5)
382 #define V_WIN0_INTERLACE_READ(x) VAL_MASK(x, 1, 8)
383 #define V_WIN0_NO_OUTSTANDING(x) VAL_MASK(x, 1, 9)
384 #define V_WIN0_CSC_MODE(x) VAL_MASK(x, 2, 10)
385 #define V_WIN0_RB_SWAP(x) VAL_MASK(x, 1, 12)
386 #define V_WIN0_ALPHA_SWAP(x) VAL_MASK(x, 1, 13)
387 #define V_WIN0_MID_SWAP(x) VAL_MASK(x, 1, 14)
388 #define V_WIN0_UV_SWAP(x) VAL_MASK(x, 1, 15)
389 #define V_WIN0_HW_PRE_MUL_EN(x) VAL_MASK(x, 1, 16)
391 #define V_WIN0_YUYV(x) VAL_MASK(x, 1, 17)
392 #define V_WIN0_YRGB_DEFLICK(x) VAL_MASK(x, 1, 18)
393 #define V_WIN0_CBR_DEFLICK(x) VAL_MASK(x, 1, 19)
394 #define V_WIN0_YUV_CLIP(x) VAL_MASK(x, 1, 20)
395 #define V_WIN0_X_MIR_EN(x) VAL_MASK(x, 1, 21)
396 #define V_WIN0_Y_MIR_EN(x) VAL_MASK(x, 1, 22)
397 #define V_WIN0_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 24)
398 #define V_WIN0_AXI_OUTSTANDING_MAX_NUM(x) VAL_MASK(x, 5, 25)
399 #define V_WIN0_DMA_BURST_LENGTH(x) VAL_MASK(x, 2, 30)
400 #define WIN0_CTRL1 0x00000034
401 #define V_WIN0_YRGB_AXI_GATHER_EN(x) VAL_MASK(x, 1, 0)
402 #define V_WIN0_CBR_AXI_GATHER_EN(x) VAL_MASK(x, 1, 1)
403 #define V_WIN0_BIC_COE_SEL(x) VAL_MASK(x, 2, 2)
404 #define V_WIN0_VSD_YRGB_GT4(x) VAL_MASK(x, 1, 4)
405 #define V_WIN0_VSD_YRGB_GT2(x) VAL_MASK(x, 1, 5)
406 #define V_WIN0_VSD_CBR_GT4(x) VAL_MASK(x, 1, 6)
407 #define V_WIN0_VSD_CBR_GT2(x) VAL_MASK(x, 1, 7)
408 #define V_WIN0_YRGB_AXI_GATHER_NUM(x) VAL_MASK(x, 4, 8)
409 #define V_WIN0_CBR_AXI_GATHER_NUM(x) VAL_MASK(x, 3, 12)
410 #define V_WIN0_LINE_LOAD_MODE(x) VAL_MASK(x, 1, 15)
411 #define V_WIN0_YRGB_HOR_SCL_MODE(x) VAL_MASK(x, 2, 16)
412 #define V_WIN0_YRGB_VER_SCL_MODE(x) VAL_MASK(x, 2, 18)
413 #define V_WIN0_YRGB_HSD_MODE(x) VAL_MASK(x, 2, 20)
414 #define V_WIN0_YRGB_VSU_MODE(x) VAL_MASK(x, 1, 22)
415 #define V_WIN0_YRGB_VSD_MODE(x) VAL_MASK(x, 1, 23)
416 #define V_WIN0_CBR_HOR_SCL_MODE(x) VAL_MASK(x, 2, 24)
417 #define V_WIN0_CBR_VER_SCL_MODE(x) VAL_MASK(x, 2, 26)
418 #define V_WIN0_CBR_HSD_MODE(x) VAL_MASK(x, 2, 28)
419 #define V_WIN0_CBR_VSU_MODE(x) VAL_MASK(x, 1, 30)
420 #define V_WIN0_CBR_VSD_MODE(x) VAL_MASK(x, 1, 31)
421 #define WIN0_COLOR_KEY 0x00000038
422 #define V_WIN0_KEY_COLOR(x) VAL_MASK(x, 24, 0)
423 #define V_WIN0_KEY_EN(x) VAL_MASK(x, 1, 31)
424 #define WIN0_VIR 0x0000003c
425 #define V_WIN0_VIR_STRIDE(x) VAL_MASK(x, 16, 0)
426 #define V_WIN0_VIR_STRIDE_UV(x) VAL_MASK(x, 16, 16)
427 #define WIN0_YRGB_MST 0x00000040
428 #define V_WIN0_YRGB_MST(x) VAL_MASK(x, 32, 0)
429 #define WIN0_CBR_MST 0x00000044
430 #define V_WIN0_CBR_MST(x) VAL_MASK(x, 32, 0)
431 #define WIN0_ACT_INFO 0x00000048
432 #define V_WIN0_ACT_WIDTH(x) VAL_MASK(x, 13, 0)
433 #define V_FIELD0002(x) VAL_MASK(x, 1, 13)
434 #define V_FIELD0001(x) VAL_MASK(x, 1, 14)
435 #define V_FIELD0000(x) VAL_MASK(x, 1, 15)
436 #define V_WIN0_ACT_HEIGHT(x) VAL_MASK(x, 13, 16)
437 #define WIN0_DSP_INFO 0x0000004c
438 #define V_WIN0_DSP_WIDTH(x) VAL_MASK(x, 12, 0)
439 #define V_WIN0_DSP_HEIGHT(x) VAL_MASK(x, 12, 16)
440 #define WIN0_DSP_ST 0x00000050
441 #define V_WIN0_DSP_XST(x) VAL_MASK(x, 13, 0)
442 #define V_WIN0_DSP_YST(x) VAL_MASK(x, 13, 16)
443 #define WIN0_SCL_FACTOR_YRGB 0x00000054
444 #define V_WIN0_HS_FACTOR_YRGB(x) VAL_MASK(x, 16, 0)
445 #define V_WIN0_VS_FACTOR_YRGB(x) VAL_MASK(x, 16, 16)
446 #define WIN0_SCL_FACTOR_CBR 0x00000058
447 #define V_WIN0_HS_FACTOR_CBR(x) VAL_MASK(x, 16, 0)
448 #define V_WIN0_VS_FACTOR_CBR(x) VAL_MASK(x, 16, 16)
449 #define WIN0_SCL_OFFSET 0x0000005c
450 #define V_WIN0_HS_OFFSET_YRGB(x) VAL_MASK(x, 8, 0)
451 #define V_WIN0_HS_OFFSET_CBR(x) VAL_MASK(x, 8, 8)
452 #define V_WIN0_VS_OFFSET_YRGB(x) VAL_MASK(x, 8, 16)
453 #define V_WIN0_VS_OFFSET_CBR(x) VAL_MASK(x, 8, 24)
454 #define WIN0_SRC_ALPHA_CTRL 0x00000060
455 #define V_WIN0_SRC_ALPHA_EN(x) VAL_MASK(x, 1, 0)
456 #define V_WIN0_SRC_COLOR_MODE(x) VAL_MASK(x, 1, 1)
457 #define V_WIN0_SRC_ALPHA_MODE(x) VAL_MASK(x, 1, 2)
458 #define V_WIN0_SRC_BLEND_MODE(x) VAL_MASK(x, 2, 3)
459 #define V_WIN0_SRC_ALPHA_CAL_MODE(x) VAL_MASK(x, 1, 5)
460 #define V_WIN0_SRC_FACTOR_MODE(x) VAL_MASK(x, 3, 6)
461 #define V_WIN0_SRC_GLOBAL_ALPHA(x) VAL_MASK(x, 8, 16)
462 #define V_WIN0_FADING_VALUE(x) VAL_MASK(x, 8, 24)
463 #define WIN0_DST_ALPHA_CTRL 0x00000064
464 #define V_WIN0_DST_M0_RESERVED(x) VAL_MASK(x, 6, 0)
465 #define V_WIN0_DST_FACTOR_MODE(x) VAL_MASK(x, 3, 6)
466 #define WIN0_FADING_CTRL 0x00000068
467 #define V_LAYER0_FADING_OFFSET_R(x) VAL_MASK(x, 8, 0)
468 #define V_LAYER0_FADING_OFFSET_G(x) VAL_MASK(x, 8, 8)
469 #define V_LAYER0_FADING_OFFSET_B(x) VAL_MASK(x, 8, 16)
470 #define V_LAYER0_FADING_EN(x) VAL_MASK(x, 1, 24)
471 #define WIN0_CTRL2 0x0000006c
472 #define V_WIN_RID_WIN0_YRGB(x) VAL_MASK(x, 4, 0)
473 #define V_WIN_RID_WIN0_CBR(x) VAL_MASK(x, 4, 4)
474 #define WIN1_CTRL0 0x00000070
475 #define V_WIN1_EN(x) VAL_MASK(x, 1, 0)
476 #define V_WIN1_DATA_FMT(x) VAL_MASK(x, 3, 1)
477 #define V_WIN1_FMT_10(x) VAL_MASK(x, 1, 4)
478 #define V_WIN1_LB_MODE(x) VAL_MASK(x, 3, 5)
479 #define V_WIN1_INTERLACE_READ(x) VAL_MASK(x, 1, 8)
480 #define V_WIN1_NO_OUTSTANDING(x) VAL_MASK(x, 1, 9)
481 #define V_WIN1_CSC_MODE(x) VAL_MASK(x, 2, 10)
482 #define V_WIN1_RB_SWAP(x) VAL_MASK(x, 1, 12)
483 #define V_WIN1_ALPHA_SWAP(x) VAL_MASK(x, 1, 13)
484 #define V_WIN1_MID_SWAP(x) VAL_MASK(x, 1, 14)
485 #define V_WIN1_UV_SWAP(x) VAL_MASK(x, 1, 15)
486 #define V_WIN1_HW_PRE_MUL_EN(x) VAL_MASK(x, 1, 16)
488 #define V_WIN1_YUYV(x) VAL_MASK(x, 1, 17)
489 #define V_WIN1_YRGB_DEFLICK(x) VAL_MASK(x, 1, 18)
490 #define V_WIN1_CBR_DEFLICK(x) VAL_MASK(x, 1, 19)
491 #define V_WIN1_YUV_CLIP(x) VAL_MASK(x, 1, 20)
492 #define V_WIN1_X_MIR_EN(x) VAL_MASK(x, 1, 21)
493 #define V_WIN1_Y_MIR_EN(x) VAL_MASK(x, 1, 22)
494 #define V_WIN1_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 24)
495 #define V_WIN1_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 25)
496 #define V_WIN1_DMA_BURST_LENGTH(x) VAL_MASK(x, 2, 30)
497 #define WIN1_CTRL1 0x00000074
498 #define V_WIN1_YRGB_AXI_GATHER_EN(x) VAL_MASK(x, 1, 0)
499 #define V_WIN1_CBR_AXI_GATHER_EN(x) VAL_MASK(x, 1, 1)
500 #define V_WIN1_BIC_COE_SEL(x) VAL_MASK(x, 2, 2)
501 #define V_WIN1_VSD_YRGB_GT4(x) VAL_MASK(x, 1, 4)
502 #define V_WIN1_VSD_YRGB_GT2(x) VAL_MASK(x, 1, 5)
503 #define V_WIN1_VSD_CBR_GT4(x) VAL_MASK(x, 1, 6)
504 #define V_WIN1_VSD_CBR_GT2(x) VAL_MASK(x, 1, 7)
505 #define V_WIN1_YRGB_AXI_GATHER_NUM(x) VAL_MASK(x, 4, 8)
506 #define V_WIN1_CBR_AXI_GATHER_NUM(x) VAL_MASK(x, 3, 12)
507 #define V_WIN1_LINE_LOAD_MODE(x) VAL_MASK(x, 1, 15)
508 #define V_WIN1_YRGB_HOR_SCL_MODE(x) VAL_MASK(x, 2, 16)
509 #define V_WIN1_YRGB_VER_SCL_MODE(x) VAL_MASK(x, 2, 18)
510 #define V_WIN1_YRGB_HSD_MODE(x) VAL_MASK(x, 2, 20)
511 #define V_WIN1_YRGB_VSU_MODE(x) VAL_MASK(x, 1, 22)
512 #define V_WIN1_YRGB_VSD_MODE(x) VAL_MASK(x, 1, 23)
513 #define V_WIN1_CBR_HOR_SCL_MODE(x) VAL_MASK(x, 2, 24)
514 #define V_WIN1_CBR_VER_SCL_MODE(x) VAL_MASK(x, 2, 26)
515 #define V_WIN1_CBR_HSD_MODE(x) VAL_MASK(x, 2, 28)
516 #define V_WIN1_CBR_VSU_MODE(x) VAL_MASK(x, 1, 30)
517 #define V_WIN1_CBR_VSD_MODE(x) VAL_MASK(x, 1, 31)
518 #define WIN1_COLOR_KEY 0x00000078
519 #define V_WIN1_KEY_COLOR(x) VAL_MASK(x, 24, 0)
520 #define V_WIN1_KEY_EN(x) VAL_MASK(x, 1, 31)
521 #define WIN1_VIR 0x0000007c
522 #define V_WIN1_VIR_STRIDE(x) VAL_MASK(x, 16, 0)
523 #define V_WIN1_VIR_STRIDE_UV(x) VAL_MASK(x, 16, 16)
524 #define WIN1_YRGB_MST 0x00000080
525 #define V_WIN1_YRGB_MST(x) VAL_MASK(x, 32, 0)
526 #define WIN1_CBR_MST 0x00000084
527 #define V_WIN1_CBR_MST(x) VAL_MASK(x, 32, 0)
528 #define WIN1_ACT_INFO 0x00000088
529 #define V_WIN1_ACT_WIDTH(x) VAL_MASK(x, 13, 0)
530 #define V_WIN1_ACT_HEIGHT(x) VAL_MASK(x, 13, 16)
531 #define WIN1_DSP_INFO 0x0000008c
532 #define V_WIN1_DSP_WIDTH(x) VAL_MASK(x, 12, 0)
533 #define V_WIN1_DSP_HEIGHT(x) VAL_MASK(x, 12, 16)
534 #define WIN1_DSP_ST 0x00000090
535 #define V_WIN1_DSP_XST(x) VAL_MASK(x, 13, 0)
536 #define V_WIN1_DSP_YST(x) VAL_MASK(x, 13, 16)
537 #define WIN1_SCL_FACTOR_YRGB 0x00000094
538 #define V_WIN1_HS_FACTOR_YRGB(x) VAL_MASK(x, 16, 0)
539 #define V_WIN1_VS_FACTOR_YRGB(x) VAL_MASK(x, 16, 16)
540 #define WIN1_SCL_FACTOR_CBR 0x00000098
541 #define V_WIN1_HS_FACTOR_CBR(x) VAL_MASK(x, 16, 0)
542 #define V_WIN1_VS_FACTOR_CBR(x) VAL_MASK(x, 16, 16)
543 #define WIN1_SCL_OFFSET 0x0000009c
544 #define V_WIN1_HS_OFFSET_YRGB(x) VAL_MASK(x, 8, 0)
545 #define V_WIN1_HS_OFFSET_CBR(x) VAL_MASK(x, 8, 8)
546 #define V_WIN1_VS_OFFSET_YRGB(x) VAL_MASK(x, 8, 16)
547 #define V_WIN1_VS_OFFSET_CBR(x) VAL_MASK(x, 8, 24)
548 #define WIN1_SRC_ALPHA_CTRL 0x000000a0
549 #define V_WIN1_SRC_ALPHA_EN(x) VAL_MASK(x, 1, 0)
550 #define V_WIN1_SRC_COLOR_MODE(x) VAL_MASK(x, 1, 1)
551 #define V_WIN1_SRC_ALPHA_MODE(x) VAL_MASK(x, 1, 2)
552 #define V_WIN1_SRC_BLEND_MODE(x) VAL_MASK(x, 2, 3)
553 #define V_WIN1_SRC_ALPHA_CAL_MODE(x) VAL_MASK(x, 1, 5)
554 #define V_WIN1_SRC_FACTOR_MODE(x) VAL_MASK(x, 3, 6)
555 #define V_WIN1_SRC_GLOBAL_ALPHA(x) VAL_MASK(x, 8, 16)
556 #define V_WIN1_FADING_VALUE(x) VAL_MASK(x, 8, 24)
557 #define WIN1_DST_ALPHA_CTRL 0x000000a4
558 #define V_WIN1_DSP_M0_RESERVED(x) VAL_MASK(x, 6, 0)
559 #define V_WIN1_DST_FACTOR_M0(x) VAL_MASK(x, 3, 6)
560 #define WIN1_FADING_CTRL 0x000000a8
561 #define V_WIN1_FADING_OFFSET_R(x) VAL_MASK(x, 8, 0)
562 #define V_WIN1_FADING_OFFSET_G(x) VAL_MASK(x, 8, 8)
563 #define V_WIN1_FADING_OFFSET_B(x) VAL_MASK(x, 8, 16)
564 #define V_WIN1_FADING_EN(x) VAL_MASK(x, 1, 24)
565 #define WIN1_CTRL2 0x000000ac
566 #define V_WIN_RID_WIN1_YRGB(x) VAL_MASK(x, 4, 0)
567 #define V_WIN_RID_WIN1_CBR(x) VAL_MASK(x, 4, 4)
568 #define WIN2_CTRL0 0x000000b0
569 #define V_WIN2_EN(x) VAL_MASK(x, 1, 0)
570 #define V_WIN2_INTERLACE_READ(x) VAL_MASK(x, 1, 1)
571 #define V_WIN2_CSC_MODE(x) VAL_MASK(x, 2, 2)
572 #define V_WIN2_MST0_EN(x) VAL_MASK(x, 1, 4)
573 #define V_WIN2_DATA_FMT0(x) VAL_MASK(x, 2, 5)
574 #define V_WIN2_MST1_EN(x) VAL_MASK(x, 1, 8)
575 #define V_WIN2_DATA_FMT1(x) VAL_MASK(x, 2, 9)
576 #define V_WIN2_MST2_EN(x) VAL_MASK(x, 1, 12)
577 #define V_WIN2_DATA_FMT2(x) VAL_MASK(x, 2, 13)
578 #define V_WIN2_MST3_EN(x) VAL_MASK(x, 1, 16)
579 #define V_WIN2_DATA_FMT3(x) VAL_MASK(x, 2, 17)
580 #define V_WIN2_RB_SWAP0(x) VAL_MASK(x, 1, 20)
581 #define V_WIN2_ALPHA_SWAP0(x) VAL_MASK(x, 1, 21)
582 #define V_WIN2_ENDIAN_SWAP0(x) VAL_MASK(x, 1, 22)
583 #define V_WIN2_RB_SWAP1(x) VAL_MASK(x, 1, 23)
584 #define V_WIN2_ALPHA_SWAP1(x) VAL_MASK(x, 1, 24)
585 #define V_WIN2_ENDIAN_SWAP1(x) VAL_MASK(x, 1, 25)
586 #define V_WIN2_RB_SWAP2(x) VAL_MASK(x, 1, 26)
587 #define V_WIN2_ALPHA_SWAP2(x) VAL_MASK(x, 1, 27)
588 #define V_WIN2_ENDIAN_SWAP2(x) VAL_MASK(x, 1, 28)
589 #define V_WIN2_RB_SWAP3(x) VAL_MASK(x, 1, 29)
590 #define V_WIN2_ALPHA_SWAP3(x) VAL_MASK(x, 1, 30)
591 #define V_WIN2_ENDIAN_SWAP3(x) VAL_MASK(x, 1, 31)
592 #define WIN2_CTRL1 0x000000b4
593 #define V_WIN2_AXI_GATHER_EN(x) VAL_MASK(x, 1, 0)
594 #define V_WIN2_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 1)
595 #define V_WIN2_DMA_BURST_LENGTH(x) VAL_MASK(x, 2, 2)
596 #define V_WIN2_AXI_GATHER_NUM(x) VAL_MASK(x, 4, 4)
597 #define V_WIN2_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 8)
598 #define V_WIN2_NO_OUTSTANDING(x) VAL_MASK(x, 1, 14)
599 #define V_WIN2_Y_MIR_EN(x) VAL_MASK(x, 1, 15)
600 #define V_WIN2_LUT_EN(x) VAL_MASK(x, 1, 16)
601 #define V_WIN_RID_WIN2(x) VAL_MASK(x, 4, 20)
602 #define WIN2_VIR0_1 0x000000b8
603 #define V_WIN2_VIR_STRIDE0(x) VAL_MASK(x, 16, 0)
604 #define V_WIN2_VIR_STRIDE1(x) VAL_MASK(x, 16, 16)
605 #define WIN2_VIR2_3 0x000000bc
606 #define V_WIN2_VIR_STRIDE2(x) VAL_MASK(x, 16, 0)
607 #define V_WIN2_VIR_STRIDE3(x) VAL_MASK(x, 16, 16)
608 #define WIN2_MST0 0x000000c0
609 #define V_WIN2_MST0(x) VAL_MASK(x, 32, 0)
610 #define WIN2_DSP_INFO0 0x000000c4
611 #define V_WIN2_DSP_WIDTH0(x) VAL_MASK(x, 12, 0)
612 #define V_WIN2_DSP_HEIGHT0(x) VAL_MASK(x, 12, 16)
613 #define WIN2_DSP_ST0 0x000000c8
614 #define V_WIN2_DSP_XST0(x) VAL_MASK(x, 13, 0)
615 #define V_WIN2_DSP_YST0(x) VAL_MASK(x, 13, 16)
616 #define WIN2_COLOR_KEY 0x000000cc
617 #define V_WIN2_KEY_COLOR(x) VAL_MASK(x, 24, 0)
618 #define V_WIN2_KEY_EN(x) VAL_MASK(x, 1, 24)
619 #define WIN2_MST1 0x000000d0
620 #define V_WIN2_MST1(x) VAL_MASK(x, 32, 0)
621 #define WIN2_DSP_INFO1 0x000000d4
622 #define V_WIN2_DSP_WIDTH1(x) VAL_MASK(x, 12, 0)
623 #define V_WIN2_DSP_HEIGHT1(x) VAL_MASK(x, 12, 16)
624 #define WIN2_DSP_ST1 0x000000d8
625 #define V_WIN2_DSP_XST1(x) VAL_MASK(x, 13, 0)
626 #define V_WIN2_DSP_YST1(x) VAL_MASK(x, 13, 16)
627 #define WIN2_SRC_ALPHA_CTRL 0x000000dc
628 #define V_WIN2_SRC_ALPHA_EN(x) VAL_MASK(x, 1, 0)
629 #define V_WIN2_SRC_COLOR_MODE(x) VAL_MASK(x, 1, 1)
630 #define V_WIN2_SRC_ALPHA_MODE(x) VAL_MASK(x, 1, 2)
631 #define V_WIN2_SRC_BLEND_MODE(x) VAL_MASK(x, 2, 3)
632 #define V_WIN2_SRC_ALPHA_CAL_MODE(x) VAL_MASK(x, 1, 5)
633 #define V_WIN2_SRC_FACTOR_MODE(x) VAL_MASK(x, 3, 6)
634 #define V_WIN2_SRC_GLOBAL_ALPHA(x) VAL_MASK(x, 8, 16)
635 #define V_WIN2_FADING_VALUE(x) VAL_MASK(x, 8, 24)
636 #define WIN2_MST2 0x000000e0
637 #define V_WIN2_MST2(x) VAL_MASK(x, 32, 0)
638 #define WIN2_DSP_INFO2 0x000000e4
639 #define V_WIN2_DSP_WIDTH2(x) VAL_MASK(x, 12, 0)
640 #define V_WIN2_DSP_HEIGHT2(x) VAL_MASK(x, 12, 16)
641 #define WIN2_DSP_ST2 0x000000e8
642 #define V_WIN2_DSP_XST2(x) VAL_MASK(x, 13, 0)
643 #define V_WIN2_DSP_YST2(x) VAL_MASK(x, 13, 16)
644 #define WIN2_DST_ALPHA_CTRL 0x000000ec
645 #define V_WIN2_DST_M0_RESERVED(x) VAL_MASK(x, 6, 0)
646 #define V_WIN2_DST_FACTOR_MODE(x) VAL_MASK(x, 3, 6)
647 #define WIN2_MST3 0x000000f0
648 #define V_WIN2_MST3(x) VAL_MASK(x, 32, 0)
649 #define WIN2_DSP_INFO3 0x000000f4
650 #define V_WIN2_DSP_WIDTH3(x) VAL_MASK(x, 12, 0)
651 #define V_WIN2_DSP_HEIGHT3(x) VAL_MASK(x, 12, 16)
652 #define WIN2_DSP_ST3 0x000000f8
653 #define V_WIN2_DSP_XST3(x) VAL_MASK(x, 13, 0)
654 #define V_WIN2_DSP_YST3(x) VAL_MASK(x, 13, 16)
655 #define WIN2_FADING_CTRL 0x000000fc
656 #define V_WIN2_FADING_OFFSET_R(x) VAL_MASK(x, 8, 0)
657 #define V_WIN2_FADING_OFFSET_G(x) VAL_MASK(x, 8, 8)
658 #define V_WIN2_FADING_OFFSET_B(x) VAL_MASK(x, 8, 16)
659 #define V_WIN2_FADING_EN(x) VAL_MASK(x, 1, 24)
660 #define WIN3_CTRL0 0x00000100
661 #define V_WIN3_EN(x) VAL_MASK(x, 1, 0)
662 #define V_WIN3_INTERLACE_READ(x) VAL_MASK(x, 1, 1)
663 #define V_WIN3_CSC_MODE(x) VAL_MASK(x, 2, 2)
664 #define V_WIN3_MST0_EN(x) VAL_MASK(x, 1, 4)
665 #define V_WIN3_DATA_FMT0(x) VAL_MASK(x, 2, 5)
666 #define V_WIN3_MST1_EN(x) VAL_MASK(x, 1, 8)
667 #define V_WIN3_DATA_FMT1(x) VAL_MASK(x, 2, 9)
668 #define V_WIN3_MST2_EN(x) VAL_MASK(x, 1, 12)
669 #define V_WIN3_DATA_FMT2(x) VAL_MASK(x, 2, 13)
670 #define V_WIN3_MST3_EN(x) VAL_MASK(x, 1, 16)
671 #define V_WIN3_DATA_FMT3(x) VAL_MASK(x, 2, 17)
672 #define V_WIN3_RB_SWAP0(x) VAL_MASK(x, 1, 20)
673 #define V_WIN3_ALPHA_SWAP0(x) VAL_MASK(x, 1, 21)
674 #define V_WIN3_ENDIAN_SWAP0(x) VAL_MASK(x, 1, 22)
675 #define V_WIN3_RB_SWAP1(x) VAL_MASK(x, 1, 23)
676 #define V_WIN3_ALPHA_SWAP1(x) VAL_MASK(x, 1, 24)
677 #define V_WIN3_ENDIAN_SWAP1(x) VAL_MASK(x, 1, 25)
678 #define V_WIN3_RB_SWAP2(x) VAL_MASK(x, 1, 26)
679 #define V_WIN3_ALPHA_SWAP2(x) VAL_MASK(x, 1, 27)
680 #define V_WIN3_ENDIAN_SWAP2(x) VAL_MASK(x, 1, 28)
681 #define V_WIN3_RB_SWAP3(x) VAL_MASK(x, 1, 29)
682 #define V_WIN3_ALPHA_SWAP3(x) VAL_MASK(x, 1, 30)
683 #define V_WIN3_ENDIAN_SWAP3(x) VAL_MASK(x, 1, 31)
684 #define WIN3_CTRL1 0x00000104
685 #define V_WIN3_AXI_GATHER_EN(x) VAL_MASK(x, 1, 0)
686 #define V_WIN3_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 1)
687 #define V_WIN3_DMA_BURST_LENGTH(x) VAL_MASK(x, 2, 2)
688 #define V_WIN3_AXI_GATHER_NUM(x) VAL_MASK(x, 4, 4)
689 #define V_WIN3_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 8)
690 #define V_WIN3_NO_OUTSTANDING(x) VAL_MASK(x, 1, 14)
691 #define V_WIN3_Y_MIR_EN(x) VAL_MASK(x, 1, 15)
692 #define V_WIN3_LUT_EN(x) VAL_MASK(x, 1, 16)
693 #define V_WIN_RID_WIN3(x) VAL_MASK(x, 4, 20)
694 #define WIN3_VIR0_1 0x00000108
695 #define V_WIN3_VIR_STRIDE0(x) VAL_MASK(x, 16, 0)
696 #define V_WIN3_VIR_STRIDE1(x) VAL_MASK(x, 16, 16)
697 #define WIN3_VIR2_3 0x0000010c
698 #define V_WIN3_VIR_STRIDE2(x) VAL_MASK(x, 16, 0)
699 #define V_WIN3_VIR_STRIDE3(x) VAL_MASK(x, 16, 16)
700 #define WIN3_MST0 0x00000110
701 #define V_WIN3_MST0(x) VAL_MASK(x, 32, 0)
702 #define WIN3_DSP_INFO0 0x00000114
703 #define V_WIN3_DSP_WIDTH0(x) VAL_MASK(x, 12, 0)
704 #define V_WIN3_DSP_HEIGHT0(x) VAL_MASK(x, 12, 16)
705 #define WIN3_DSP_ST0 0x00000118
706 #define V_WIN3_DSP_XST0(x) VAL_MASK(x, 13, 0)
707 #define V_WIN3_DSP_YST0(x) VAL_MASK(x, 13, 16)
708 #define WIN3_COLOR_KEY 0x0000011c
709 #define V_WIN3_KEY_COLOR(x) VAL_MASK(x, 24, 0)
710 #define V_WIN3_KEY_EN(x) VAL_MASK(x, 1, 24)
711 #define WIN3_MST1 0x00000120
712 #define V_WIN3_MST1(x) VAL_MASK(x, 32, 0)
713 #define WIN3_DSP_INFO1 0x00000124
714 #define V_WIN3_DSP_WIDTH1(x) VAL_MASK(x, 12, 0)
715 #define V_WIN3_DSP_HEIGHT1(x) VAL_MASK(x, 12, 16)
716 #define WIN3_DSP_ST1 0x00000128
717 #define V_WIN3_DSP_XST1(x) VAL_MASK(x, 13, 0)
718 #define V_WIN3_DSP_YST1(x) VAL_MASK(x, 13, 16)
719 #define WIN3_SRC_ALPHA_CTRL 0x0000012c
720 #define V_WIN3_SRC_ALPHA_EN(x) VAL_MASK(x, 1, 0)
721 #define V_WIN3_SRC_COLOR_MODE(x) VAL_MASK(x, 1, 1)
722 #define V_WIN3_SRC_ALPHA_MODE(x) VAL_MASK(x, 1, 2)
723 #define V_WIN3_SRC_BLEND_MODE(x) VAL_MASK(x, 2, 3)
724 #define V_WIN3_SRC_ALPHA_CAL_MODE(x) VAL_MASK(x, 1, 5)
725 #define V_WIN3_SRC_FACTOR_MODE(x) VAL_MASK(x, 3, 6)
726 #define V_WIN3_SRC_GLOBAL_ALPHA(x) VAL_MASK(x, 8, 16)
727 #define V_WIN3_FADING_VALUE(x) VAL_MASK(x, 8, 24)
728 #define WIN3_MST2 0x00000130
729 #define V_WIN3_MST2(x) VAL_MASK(x, 32, 0)
730 #define WIN3_DSP_INFO2 0x00000134
731 #define V_WIN3_DSP_WIDTH2(x) VAL_MASK(x, 12, 0)
732 #define V_WIN3_DSP_HEIGHT2(x) VAL_MASK(x, 12, 16)
733 #define WIN3_DSP_ST2 0x00000138
734 #define V_WIN3_DSP_XST2(x) VAL_MASK(x, 13, 0)
735 #define V_WIN3_DSP_YST2(x) VAL_MASK(x, 13, 16)
736 #define WIN3_DST_ALPHA_CTRL 0x0000013c
737 #define V_WIN3_DST_FACTOR_RESERVED(x) VAL_MASK(x, 6, 0)
738 #define V_WIN3_DST_FACTOR_MODE(x) VAL_MASK(x, 3, 6)
739 #define WIN3_MST3 0x00000140
740 #define V_WIN3_MST3(x) VAL_MASK(x, 32, 0)
741 #define WIN3_DSP_INFO3 0x00000144
742 #define V_WIN3_DSP_WIDTH3(x) VAL_MASK(x, 12, 0)
743 #define V_WIN3_DSP_HEIGHT3(x) VAL_MASK(x, 12, 16)
744 #define WIN3_DSP_ST3 0x00000148
745 #define V_WIN3_DSP_XST3(x) VAL_MASK(x, 13, 0)
746 #define V_WIN3_DSP_YST3(x) VAL_MASK(x, 13, 16)
747 #define WIN3_FADING_CTRL 0x0000014c
748 #define V_WIN3_FADING_OFFSET_R(x) VAL_MASK(x, 8, 0)
749 #define V_WIN3_FADING_OFFSET_G(x) VAL_MASK(x, 8, 8)
750 #define V_WIN3_FADING_OFFSET_B(x) VAL_MASK(x, 8, 16)
751 #define V_WIN3_FADING_EN(x) VAL_MASK(x, 1, 24)
752 #define HWC_CTRL0 0x00000150
753 #define V_HWC_EN(x) VAL_MASK(x, 1, 0)
754 #define V_HWC_DATA_FMT(x) VAL_MASK(x, 3, 1)
755 #define V_HWC_MODE(x) VAL_MASK(x, 1, 4)
756 #define V_HWC_SIZE(x) VAL_MASK(x, 2, 5)
757 #define V_HWC_INTERLACE_READ(x) VAL_MASK(x, 1, 8)
758 #define V_HWC_CSC_MODE(x) VAL_MASK(x, 2, 10)
759 #define V_HWC_RB_SWAP(x) VAL_MASK(x, 1, 12)
760 #define V_HWC_ALPHA_SWAP(x) VAL_MASK(x, 1, 13)
761 #define V_HWC_ENDIAN_SWAP(x) VAL_MASK(x, 1, 14)
762 #define HWC_CTRL1 0x00000154
763 #define V_HWC_AXI_GATHER_EN(x) VAL_MASK(x, 1, 0)
764 #define V_HWC_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 1)
765 #define V_HWC_DMA_BURST_LENGTH(x) VAL_MASK(x, 2, 2)
766 #define V_HWC_AXI_GATHER_NUM(x) VAL_MASK(x, 3, 4)
767 #define V_HWC_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 8)
768 #define V_HWC_RGB2YUV_EN(x) VAL_MASK(x, 1, 13)
769 #define V_HWC_NO_OUTSTANDING(x) VAL_MASK(x, 1, 14)
770 #define V_HWC_Y_MIR_EN(x) VAL_MASK(x, 1, 15)
771 #define V_HWC_LUT_EN(x) VAL_MASK(x, 1, 16)
772 #define V_WIN_RID_HWC(x) VAL_MASK(x, 4, 20)
773 #define HWC_MST 0x00000158
774 #define V_HWC_MST(x) VAL_MASK(x, 32, 0)
775 #define HWC_DSP_ST 0x0000015c
776 #define V_HWC_DSP_XST(x) VAL_MASK(x, 13, 0)
777 #define V_HWC_DSP_YST(x) VAL_MASK(x, 13, 16)
778 #define HWC_SRC_ALPHA_CTRL 0x00000160
779 #define V_HWC_SRC_ALPHA_EN(x) VAL_MASK(x, 1, 0)
780 #define V_HWC_SRC_COLOR_MODE(x) VAL_MASK(x, 1, 1)
781 #define V_HWC_SRC_ALPHA_MODE(x) VAL_MASK(x, 1, 2)
782 #define V_HWC_SRC_BLEND_MODE(x) VAL_MASK(x, 2, 3)
783 #define V_HWC_SRC_ALPHA_CAL_MODE(x) VAL_MASK(x, 1, 5)
784 #define V_HWC_SRC_FACTOR_MODE(x) VAL_MASK(x, 3, 6)
785 #define V_HWC_SRC_GLOBAL_ALPHA(x) VAL_MASK(x, 8, 16)
786 #define V_HWC_FADING_VALUE(x) VAL_MASK(x, 8, 24)
787 #define HWC_DST_ALPHA_CTRL 0x00000164
788 #define V_HWC_DST_M0_RESERVED(x) VAL_MASK(x, 6, 0)
789 #define V_HWC_DST_FACTOR_MODE(x) VAL_MASK(x, 3, 6)
790 #define HWC_FADING_CTRL 0x00000168
791 #define V_HWC_FADING_OFFSET_R(x) VAL_MASK(x, 8, 0)
792 #define V_HWC_FADING_OFFSET_G(x) VAL_MASK(x, 8, 8)
793 #define V_HWC_FADING_OFFSET_B(x) VAL_MASK(x, 8, 16)
794 #define V_HWC_FADING_EN(x) VAL_MASK(x, 1, 24)
795 #define HWC_RESERVED1 0x0000016c
796 #define POST_DSP_HACT_INFO 0x00000170
797 #define V_DSP_HACT_END_POST(x) VAL_MASK(x, 13, 0)
798 #define V_DSP_HACT_ST_POST(x) VAL_MASK(x, 13, 16)
799 #define POST_DSP_VACT_INFO 0x00000174
800 #define V_DSP_VACT_END_POST(x) VAL_MASK(x, 13, 0)
801 #define V_DSP_VACT_ST_POST(x) VAL_MASK(x, 13, 16)
802 #define POST_SCL_FACTOR_YRGB 0x00000178
803 #define V_POST_HS_FACTOR_YRGB(x) VAL_MASK(x, 16, 0)
804 #define V_POST_VS_FACTOR_YRGB(x) VAL_MASK(x, 16, 16)
805 #define POST_RESERVED 0x0000017c
806 #define POST_SCL_CTRL 0x00000180
807 #define V_POST_HOR_SD_EN(x) VAL_MASK(x, 1, 0)
808 #define V_POST_VER_SD_EN(x) VAL_MASK(x, 1, 1)
809 #define V_DSP_OUT_RGB_YUV(x) VAL_MASK(x, 1, 2)
810 #define POST_DSP_VACT_INFO_F1 0x00000184
811 #define V_DSP_VACT_END_POST(x) VAL_MASK(x, 13, 0)
812 #define V_DSP_VACT_ST_POST(x) VAL_MASK(x, 13, 16)
813 #define DSP_HTOTAL_HS_END 0x00000188
814 #define V_DSP_HS_END(x) VAL_MASK(x, 13, 0)
815 #define V_DSP_HTOTAL(x) VAL_MASK(x, 13, 16)
816 #define DSP_HACT_ST_END 0x0000018c
817 #define V_DSP_HACT_END(x) VAL_MASK(x, 13, 0)
818 #define V_DSP_HACT_ST(x) VAL_MASK(x, 13, 16)
819 #define DSP_VTOTAL_VS_END 0x00000190
820 #define V_DSP_VS_END(x) VAL_MASK(x, 13, 0)
821 #define V_SW_DSP_VTOTAL_IMD(x) VAL_MASK(x, 1, 15)
822 #define V_DSP_VTOTAL(x) VAL_MASK(x, 13, 16)
823 #define DSP_VACT_ST_END 0x00000194
824 #define V_DSP_VACT_END(x) VAL_MASK(x, 13, 0)
825 #define V_DSP_VACT_ST(x) VAL_MASK(x, 13, 16)
826 #define DSP_VS_ST_END_F1 0x00000198
827 #define V_DSP_VS_END_F1(x) VAL_MASK(x, 13, 0)
828 #define V_DSP_VS_ST_F1(x) VAL_MASK(x, 13, 16)
829 #define DSP_VACT_ST_END_F1 0x0000019c
830 #define V_DSP_VACT_END_F1(x) VAL_MASK(x, 13, 0)
831 #define V_DSP_VACT_ST_F1(x) VAL_MASK(x, 13, 16)
832 #define PWM_CTRL 0x000001a0
833 #define V_PWM_EN(x) VAL_MASK(x, 1, 0)
834 #define V_PWM_MODE(x) VAL_MASK(x, 2, 1)
835 #define V_DUTY_POL(x) VAL_MASK(x, 1, 3)
836 #define V_INACTIVE_POL(x) VAL_MASK(x, 1, 4)
837 #define V_OUTPUT_MODE(x) VAL_MASK(x, 1, 5)
838 #define V_LP_EN(x) VAL_MASK(x, 1, 8)
839 #define V_CLK_SEL(x) VAL_MASK(x, 1, 9)
840 #define V_PRESCALE(x) VAL_MASK(x, 3, 12)
841 #define V_SCALE(x) VAL_MASK(x, 8, 16)
842 #define V_RPT(x) VAL_MASK(x, 8, 24)
843 #define PWM_PERIOD_HPR 0x000001a4
844 #define V_PWM_PERIOD(x) VAL_MASK(x, 32, 0)
845 #define PWM_DUTY_LPR 0x000001a8
846 #define V_PWM_DUTY(x) VAL_MASK(x, 32, 0)
847 #define PWM_CNT 0x000001ac
848 #define V_PWM_CNT(x) VAL_MASK(x, 32, 0)
849 #define BCSH_COLOR_BAR 0x000001b0
850 #define V_BCSH_EN(x) VAL_MASK(x, 1, 0)
851 #define V_COLOR_BAR_Y(x) VAL_MASK(x, 8, 8)
852 #define V_COLOR_BAR_U(x) VAL_MASK(x, 8, 16)
853 #define V_COLOR_BAR_V(x) VAL_MASK(x, 8, 24)
854 #define BCSH_BCS 0x000001b4
855 #define V_BRIGHTNESS(x) VAL_MASK(x, 8, 0)
856 #define V_CONTRAST(x) VAL_MASK(x, 9, 8)
857 #define V_SAT_CON(x) VAL_MASK(x, 10, 20)
858 #define V_OUT_MODE(x) VAL_MASK(x, 2, 30)
859 #define BCSH_H 0x000001b8
860 #define V_SIN_HUE(x) VAL_MASK(x, 9, 0)
861 #define V_COS_HUE(x) VAL_MASK(x, 9, 16)
862 #define BCSH_CTRL 0x000001bc
863 #define V_BCSH_Y2R_EN(x) VAL_MASK(x, 1, 0)
864 #define V_BCSH_Y2R_CSC_MODE(x) VAL_MASK(x, 2, 2)
865 #define V_BCSH_R2Y_EN(x) VAL_MASK(x, 1, 4)
866 #define V_BCSH_R2Y_CSC_MODE(x) VAL_MASK(x, 1, 6)
867 #define CABC_CTRL0 0x000001c0
868 #define V_CABC_EN(x) VAL_MASK(x, 1, 0)
869 #define V_PWM_CONFIG_MODE(x) VAL_MASK(x, 2, 1)
870 #define V_CABC_HANDLE_EN(x) VAL_MASK(x, 1, 3)
871 #define V_CABC_CALC_PIXEL_NUM(x) VAL_MASK(x, 23, 4)
872 #define CABC_CTRL1 0x000001c4
873 #define V_CABC_LUT_EN(x) VAL_MASK(x, 1, 0)
874 #define V_CABC_TOTAL_NUM(x) VAL_MASK(x, 23, 4)
875 #define CABC_CTRL2 0x000001c8
876 #define V_CABC_STAGE_DOWN(x) VAL_MASK(x, 8, 0)
877 #define V_CABC_STAGE_UP(x) VAL_MASK(x, 9, 8)
878 #define V_CABC_STAGE_UP_MODE(x) VAL_MASK(x, 1, 19)
879 #define V_MAX_SCALE_CFG_VALUE(x) VAL_MASK(x, 9, 20)
880 #define V_MAX_SCALE_CFG_ENABLE(x) VAL_MASK(x, 1, 31)
881 #define CABC_CTRL3 0x000001cc
882 #define V_CABC_GLOBAL_DN(x) VAL_MASK(x, 8, 0)
883 #define V_CABC_GLOBAL_DN_LIMIT_EN(x) VAL_MASK(x, 1, 8)
884 #define CABC_GAUSS_LINE0_0 0x000001d0
885 #define V_T_LINE0_0(x) VAL_MASK(x, 8, 0)
886 #define V_T_LINE0_1(x) VAL_MASK(x, 8, 8)
887 #define V_T_LINE0_2(x) VAL_MASK(x, 8, 16)
888 #define V_T_LINE0_3(x) VAL_MASK(x, 8, 24)
889 #define CABC_GAUSS_LINE0_1 0x000001d4
890 #define V_T_LINE0_4(x) VAL_MASK(x, 8, 0)
891 #define V_T_LINE0_5(x) VAL_MASK(x, 8, 8)
892 #define V_T_LINE0_6(x) VAL_MASK(x, 8, 16)
893 #define CABC_GAUSS_LINE1_0 0x000001d8
894 #define V_T_LINE1_0(x) VAL_MASK(x, 8, 0)
895 #define V_T_LINE1_1(x) VAL_MASK(x, 8, 8)
896 #define V_T_LINE1_2(x) VAL_MASK(x, 8, 16)
897 #define V_T_LINE1_3(x) VAL_MASK(x, 8, 24)
898 #define CABC_GAUSS_LINE1_1 0x000001dc
899 #define V_T_LINE1_4(x) VAL_MASK(x, 8, 0)
900 #define V_T_LINE1_5(x) VAL_MASK(x, 8, 8)
901 #define V_T_LINE1_6(x) VAL_MASK(x, 8, 16)
902 #define CABC_GAUSS_LINE2_0 0x000001e0
903 #define V_T_LINE2_0(x) VAL_MASK(x, 8, 0)
904 #define V_T_LINE2_1(x) VAL_MASK(x, 8, 8)
905 #define V_T_LINE2_2(x) VAL_MASK(x, 8, 16)
906 #define V_T_LINE2_3(x) VAL_MASK(x, 8, 24)
907 #define CABC_GAUSS_LINE2_1 0x000001e4
908 #define V_T_LINE2_4(x) VAL_MASK(x, 8, 0)
909 #define V_T_LINE2_5(x) VAL_MASK(x, 8, 8)
910 #define V_T_LINE2_6(x) VAL_MASK(x, 8, 16)
911 #define FRC_LOWER01_0 0x000001e8
912 #define V_LOWER01_FRM0(x) VAL_MASK(x, 16, 0)
913 #define V_LOWER01_FRM1(x) VAL_MASK(x, 16, 16)
914 #define FRC_LOWER01_1 0x000001ec
915 #define V_LOWER01_FRM2(x) VAL_MASK(x, 16, 0)
916 #define V_LOWER01_FRM3(x) VAL_MASK(x, 16, 16)
917 #define FRC_LOWER10_0 0x000001f0
918 #define V_LOWER10_FRM0(x) VAL_MASK(x, 16, 0)
919 #define V_LOWER10_FRM1(x) VAL_MASK(x, 16, 16)
920 #define FRC_LOWER10_1 0x000001f4
921 #define V_LOWER10_FRM2(x) VAL_MASK(x, 16, 0)
922 #define V_LOWER10_FRM3(x) VAL_MASK(x, 16, 16)
923 #define FRC_LOWER11_0 0x000001f8
924 #define V_LOWER11_FRM0(x) VAL_MASK(x, 16, 0)
925 #define V_LOWER11_FRM1(x) VAL_MASK(x, 16, 16)
926 #define FRC_LOWER11_1 0x000001fc
927 #define V_LOWER11_FRM2(x) VAL_MASK(x, 16, 0)
928 #define V_LOWER11_FRM3(x) VAL_MASK(x, 16, 16)
929 #define AFBCD0_CTRL 0x00000200
930 #define V_VOP_FBDC_EN(x) VAL_MASK(x, 1, 0)
931 #define V_VOP_FBDC_WIN_SEL(x) VAL_MASK(x, 2, 1)
932 #define V_FBDC_RSTN(x) VAL_MASK(x, 1, 3)
933 #define V_VOP_FBDC_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 4)
934 #define V_VOP_FBDC_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 9)
935 #define V_FBDC_RID(x) VAL_MASK(x, 4, 12)
936 #define V_AFBCD_HREG_PIXEL_PACKING_FMT(x) VAL_MASK(x, 5, 16)
937 #define V_AFBCD_HREG_BLOCK_SPLIT(x) VAL_MASK(x, 1, 21)
938 #define AFBCD0_HDR_PTR 0x00000204
939 #define V_AFBCD_HREG_HDR_PTR(x) VAL_MASK(x, 32, 0)
940 #define AFBCD0_PIC_SIZE 0x00000208
941 #define V_AFBCD_HREG_PIC_WIDTH(x) VAL_MASK(x, 16, 0)
942 #define V_AFBCD_HREG_PIC_HEIGHT(x) VAL_MASK(x, 16, 16)
943 #define AFBCD0_STATUS 0x0000020c
944 #define V_AFBCD_HREG_IDLE_N(x) VAL_MASK(x, 1, 0)
945 #define V_AFBCD_HREG_DEC_RESP(x) VAL_MASK(x, 1, 1)
946 #define V_AFBCD_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 2)
947 #define AFBCD1_CTRL 0x00000220
948 #define V_VOP_FBDC1_EN(x) VAL_MASK(x, 1, 0)
949 #define V_VOP_FBDC1_WIN_SEL(x) VAL_MASK(x, 2, 1)
950 #define V_FBDC1_RSTN(x) VAL_MASK(x, 1, 3)
951 #define V_VOP_FBDC1_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 4)
952 #define V_VOP_FBDC1_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 9)
953 #define V_FBDC1_RID(x) VAL_MASK(x, 4, 12)
954 #define V_AFBCD1_HREG_PIXEL_PACKING_FMT(x) VAL_MASK(x, 5, 16)
955 #define V_AFBCD1_HREG_BLOCK_SPLIT(x) VAL_MASK(x, 1, 21)
956 #define AFBCD1_HDR_PTR 0x00000224
957 #define V_AFBCD1_HREG_HDR_PTR(x) VAL_MASK(x, 32, 0)
958 #define AFBCD1_PIC_SIZE 0x00000228
959 #define V_AFBCD1_HREG_PIC_WIDTH(x) VAL_MASK(x, 16, 0)
960 #define V_AFBCD1_HREG_PIC_HEIGHT(x) VAL_MASK(x, 16, 16)
961 #define AFBCD1_STATUS 0x0000022c
962 #define V_AFBCD1_HREG_IDLE_N(x) VAL_MASK(x, 1, 0)
963 #define V_AFBCD1_HREG_DEC_RESP(x) VAL_MASK(x, 1, 1)
964 #define V_AFBCD1_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 2)
965 #define AFBCD2_CTRL 0x00000240
966 #define V_VOP_FBDC2_EN(x) VAL_MASK(x, 1, 0)
967 #define V_VOP_FBDC2_WIN_SEL(x) VAL_MASK(x, 2, 1)
968 #define V_FBDC2_RSTN(x) VAL_MASK(x, 1, 3)
969 #define V_VOP_FBDC2_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 4)
970 #define V_VOP_FBDC2_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 9)
971 #define V_FBDC2_RID(x) VAL_MASK(x, 4, 12)
972 #define V_AFBCD2_HREG_PIXEL_PACKING_FMT(x) VAL_MASK(x, 5, 16)
973 #define V_AFBCD2_HREG_BLOCK_SPLIT(x) VAL_MASK(x, 1, 21)
974 #define AFBCD2_HDR_PTR 0x00000244
975 #define V_AFBCD2_HREG_HDR_PTR(x) VAL_MASK(x, 32, 0)
976 #define AFBCD2_PIC_SIZE 0x00000248
977 #define V_AFBCD2_HREG_PIC_WIDTH(x) VAL_MASK(x, 16, 0)
978 #define V_AFBCD2_HREG_PIC_HEIGHT(x) VAL_MASK(x, 16, 16)
979 #define AFBCD2_STATUS 0x0000024c
980 #define V_AFBCD2_HREG_IDLE_N(x) VAL_MASK(x, 1, 0)
981 #define V_AFBCD2_HREG_DEC_RESP(x) VAL_MASK(x, 1, 1)
982 #define V_AFBCD2_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 2)
983 #define AFBCD3_CTRL 0x00000260
984 #define V_VOP_FBDC3_EN(x) VAL_MASK(x, 1, 0)
985 #define V_VOP_FBDC3_WIN_SEL(x) VAL_MASK(x, 1, 1)
986 #define V_FBDC3_RSTN(x) VAL_MASK(x, 1, 2)
987 #define V_VOP_FBDC3_AXI_MAX_OUTSTANDING_NUM(x) VAL_MASK(x, 5, 3)
988 #define V_VOP_FBDC3_AXI_MAX_OUTSTANDING_EN(x) VAL_MASK(x, 1, 8)
989 #define V_FBDC3_RID(x) VAL_MASK(x, 4, 12)
990 #define V_AFBCD3_HREG_PIXEL_PACKING_FMT(x) VAL_MASK(x, 5, 16)
991 #define V_AFBCD3_HREG_BLOCK_SPLIT(x) VAL_MASK(x, 1, 21)
992 #define AFBCD3_HDR_PTR 0x00000264
993 #define V_AFBCD3_HREG_HDR_PTR(x) VAL_MASK(x, 32, 0)
994 #define AFBCD3_PIC_SIZE 0x00000268
995 #define V_AFBCD3_HREG_PIC_WIDTH(x) VAL_MASK(x, 16, 0)
996 #define V_AFBCD3_HREG_PIC_HEIGHT(x) VAL_MASK(x, 16, 16)
997 #define AFBCD3_STATUS 0x0000026c
998 #define V_AFBCD3_HREG_IDLE_N(x) VAL_MASK(x, 1, 0)
999 #define V_AFBCD3_HREG_DEC_RESP(x) VAL_MASK(x, 1, 1)
1000 #define V_AFBCD3_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 2)
1001 #define INTR_EN0 0x00000280
1002 #define V_INTR_EN_FS(x) VAL_MASK(x, 1, 0)
1003 #define V_INTR_EN_FS_NEW(x) VAL_MASK(x, 1, 1)
1004 #define V_INTR_EN_ADDR_SAME(x) VAL_MASK(x, 1, 2)
1005 #define V_INTR_EN_LINE_FLAG0(x) VAL_MASK(x, 1, 3)
1006 #define V_INTR_EN_LINE_FLAG1(x) VAL_MASK(x, 1, 4)
1007 #define V_INTR_EN_BUS_ERROR(x) VAL_MASK(x, 1, 5)
1008 #define V_INTR_EN_WIN0_EMPTY(x) VAL_MASK(x, 1, 6)
1009 #define V_INTR_EN_WIN1_EMPTY(x) VAL_MASK(x, 1, 7)
1010 #define V_INTR_EN_WIN2_EMPTY(x) VAL_MASK(x, 1, 8)
1011 #define V_INTR_EN_WIN3_EMPTY(x) VAL_MASK(x, 1, 9)
1012 #define V_INTR_EN_HWC_EMPTY(x) VAL_MASK(x, 1, 10)
1013 #define V_INTR_EN_POST_BUF_EMPTY(x) VAL_MASK(x, 1, 11)
1015 #define V_INTR_EN_FS_FIELD(x) VAL_MASK(x, 1, 12)
1017 #define V_INTR_EN_PWM_GEN(x) VAL_MASK(x, 1, 12)
1018 #define V_INTR_EN_DSP_HOLD_VALID(x) VAL_MASK(x, 1, 13)
1019 #define V_INTR_EN_MMU(x) VAL_MASK(x, 1, 14)
1020 #define V_INTR_EN_DMA_FINISH(x) VAL_MASK(x, 1, 15)
1021 #define V_WRITE_MASK(x) VAL_MASK(x, 16, 16)
1022 #define INTR_CLEAR0 0x00000284
1023 #define V_INT_CLR_FS(x) VAL_MASK(x, 1, 0)
1024 #define V_INT_CLR_FS_NEW(x) VAL_MASK(x, 1, 1)
1025 #define V_INT_CLR_ADDR_SAME(x) VAL_MASK(x, 1, 2)
1026 #define V_INT_CLR_LINE_FLAG0(x) VAL_MASK(x, 1, 3)
1027 #define V_INT_CLR_LINE_FLAG1(x) VAL_MASK(x, 1, 4)
1028 #define V_INT_CLR_BUS_ERROR(x) VAL_MASK(x, 1, 5)
1029 #define V_INT_CLR_WIN0_EMPTY(x) VAL_MASK(x, 1, 6)
1030 #define V_INT_CLR_WIN1_EMPTY(x) VAL_MASK(x, 1, 7)
1031 #define V_INT_CLR_WIN2_EMPTY(x) VAL_MASK(x, 1, 8)
1032 #define V_INT_CLR_WIN3_EMPTY(x) VAL_MASK(x, 1, 9)
1033 #define V_INT_CLR_HWC_EMPTY(x) VAL_MASK(x, 1, 10)
1034 #define V_INT_CLR_POST_BUF_EMPTY(x) VAL_MASK(x, 1, 11)
1036 #define V_INT_CLR_FS_FIELD(x) VAL_MASK(x, 1, 12)
1038 #define V_INT_CLR_PWM_GEN(x) VAL_MASK(x, 1, 12)
1039 #define V_INT_CLR_DSP_HOLD_VALID(x) VAL_MASK(x, 1, 13)
1040 #define V_INT_CLR_MMU(x) VAL_MASK(x, 1, 14)
1041 #define V_INT_CLR_DMA_FINISH(x) VAL_MASK(x, 1, 15)
1042 #define V_WRITE_MASK(x) VAL_MASK(x, 16, 16)
1043 #define INTR_STATUS0 0x00000288
1044 #define V_INT_STATUS_FS(x) VAL_MASK(x, 1, 0)
1045 #define V_INT_STATUS_FS_NEW(x) VAL_MASK(x, 1, 1)
1046 #define V_INT_STATUS_ADDR_SAME(x) VAL_MASK(x, 1, 2)
1047 #define V_INT_STATUS_LINE_FLAG0(x) VAL_MASK(x, 1, 3)
1048 #define V_INT_STATUS_LINE_FLAG1(x) VAL_MASK(x, 1, 4)
1049 #define V_INT_STATUS_BUS_ERROR(x) VAL_MASK(x, 1, 5)
1050 #define V_INT_STATUS_WIN0_EMPTY(x) VAL_MASK(x, 1, 6)
1051 #define V_INT_STATUS_WIN1_EMPTY(x) VAL_MASK(x, 1, 7)
1052 #define V_INT_STATUS_WIN2_EMPTY(x) VAL_MASK(x, 1, 8)
1053 #define V_INT_STATUS_WIN3_EMPTY(x) VAL_MASK(x, 1, 9)
1054 #define V_INT_STATUS_HWC_EMPTY(x) VAL_MASK(x, 1, 10)
1055 #define V_INT_STATUS_POST_BUF_EMPTY(x) VAL_MASK(x, 1, 11)
1057 #define V_INT_STATUS_FS_FIELD(x) VAL_MASK(x, 1, 12)
1059 #define V_INT_STATUS_PWM_GEN(x) VAL_MASK(x, 1, 12)
1060 #define V_INT_STATUS_DSP_HOLD_VALID(x) VAL_MASK(x, 1, 13)
1061 #define V_INT_STATUS_MMU(x) VAL_MASK(x, 1, 14)
1062 #define V_INT_STATUS_DMA_FINISH(x) VAL_MASK(x, 1, 15)
1063 #define INTR_RAW_STATUS0 0x0000028c
1064 #define V_INT_RAW_STATUS_FS(x) VAL_MASK(x, 1, 0)
1065 #define V_INT_RAW_STATUS_FS_NEW(x) VAL_MASK(x, 1, 1)
1066 #define V_INT_RAW_STATUS_ADDR_SAME(x) VAL_MASK(x, 1, 2)
1067 #define V_INT_RAW_STATUS_LINE_FRAG0(x) VAL_MASK(x, 1, 3)
1068 #define V_INT_RAW_STATUS_LINE_FRAG1(x) VAL_MASK(x, 1, 4)
1069 #define V_INT_RAW_STATUS_BUS_ERROR(x) VAL_MASK(x, 1, 5)
1070 #define V_INT_RAW_STATUS_WIN0_EMPTY(x) VAL_MASK(x, 1, 6)
1071 #define V_INT_RAW_STATUS_WIN1_EMPTY(x) VAL_MASK(x, 1, 7)
1072 #define V_INT_RAW_STATUS_WIN2_EMPTY(x) VAL_MASK(x, 1, 8)
1073 #define V_INT_RAW_STATUS_WIN3_EMPTY(x) VAL_MASK(x, 1, 9)
1074 #define V_INT_RAW_STATUS_HWC_EMPTY(x) VAL_MASK(x, 1, 10)
1075 #define V_INT_RAW_STATUS_POST_BUF_EMPTY(x) VAL_MASK(x, 1, 11)
1077 #define V_INT_RAW_STATUS_FS_FIELD(x) VAL_MASK(x, 1, 12)
1079 #define V_INT_RAW_STATUS_PWM_GEN(x) VAL_MASK(x, 1, 12)
1080 #define V_INT_RAW_STATUS_DSP_HOLD_VALID(x) VAL_MASK(x, 1, 13)
1081 #define V_INT_RAW_STATUS_MMU(x) VAL_MASK(x, 1, 14)
1082 #define V_INT_RAW_STATUS_DMA_FINISH(x) VAL_MASK(x, 1, 15)
1083 #define INTR_EN1 0x00000290
1084 #define V_INT_EN_FBCD0(x) VAL_MASK(x, 1, 0)
1085 #define V_INT_EN_FBCD1(x) VAL_MASK(x, 1, 1)
1086 #define V_INT_EN_FBCD2(x) VAL_MASK(x, 1, 2)
1087 #define V_INT_EN_FBCD3(x) VAL_MASK(x, 1, 3)
1088 #define V_INT_EN_AFBCD0_HREG_DEC_RESP(x) VAL_MASK(x, 1, 4)
1089 #define V_INT_EN_AFBCD0_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 5)
1090 #define V_INT_EN_AFBCD1_HREG_DEC_RESP(x) VAL_MASK(x, 1, 6)
1091 #define V_INT_EN_AFBCD1_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 7)
1092 #define V_INT_EN_AFBCD2_HREG_DEC_RESP(x) VAL_MASK(x, 1, 8)
1093 #define V_INT_EN_AFBCD2_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 9)
1094 #define V_INT_EN_AFBCD3_HREG_DEC_RESP(x) VAL_MASK(x, 1, 10)
1095 #define V_INT_EN_AFBCD3_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 11)
1096 #define V_INT_EN_WB_YRGB_FIFO_FULL(x) VAL_MASK(x, 1, 12)
1097 #define V_INT_EN_WB_UV_FIFO_FULL(x) VAL_MASK(x, 1, 13)
1098 #define V_INT_EN_WB_FINISH(x) VAL_MASK(x, 1, 14)
1099 #define V_INT_EN_VFP(x) VAL_MASK(x, 1, 15)
1100 #define V_WRITE_MASK(x) VAL_MASK(x, 16, 16)
1101 #define INTR_CLEAR1 0x00000294
1102 #define V_INT_CLR_FBCD0(x) VAL_MASK(x, 1, 0)
1103 #define V_INT_CLR_FBCD1(x) VAL_MASK(x, 1, 1)
1104 #define V_INT_CLR_FBCD2(x) VAL_MASK(x, 1, 2)
1105 #define V_INT_CLR_FBCD3(x) VAL_MASK(x, 1, 3)
1106 #define V_INT_CLR_AFBCD0_HREG_DEC_RESP(x) VAL_MASK(x, 1, 4)
1107 #define V_INT_CLR_AFBCD0_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 5)
1108 #define V_INT_CLR_AFBCD1_HREG_DEC_RESP(x) VAL_MASK(x, 1, 6)
1109 #define V_INT_CLR_AFBCD1_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 7)
1110 #define V_INT_CLR_AFBCD2_HREG_DEC_RESP(x) VAL_MASK(x, 1, 8)
1111 #define V_INT_CLR_AFBCD2_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 9)
1112 #define V_INT_CLR_AFBCD3_HREG_DEC_RESP(x) VAL_MASK(x, 1, 10)
1113 #define V_INT_CLR_AFBCD3_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 11)
1114 #define V_INT_CLR_WB_YRGB_FIFO_FULL(x) VAL_MASK(x, 1, 12)
1115 #define V_INT_CLR_WB_UV_FIFO_FULL(x) VAL_MASK(x, 1, 13)
1116 #define V_INT_CLR_WB_DMA_FINISH(x) VAL_MASK(x, 1, 14)
1117 #define V_INT_CLR_VFP(x) VAL_MASK(x, 1, 15)
1118 #define INTR_STATUS1 0x00000298
1119 #define V_INT_STATUS_FBCD0(x) VAL_MASK(x, 1, 0)
1120 #define V_INT_STATUS_FBCD1(x) VAL_MASK(x, 1, 1)
1121 #define V_INT_STATUS_FBCD2(x) VAL_MASK(x, 1, 2)
1122 #define V_INT_STATUS_FBCD3(x) VAL_MASK(x, 1, 3)
1123 #define V_INT_STATUS_AFBCD0_HREG_DEC_RESP(x) VAL_MASK(x, 1, 4)
1124 #define V_INT_STATUS_AFBCD0_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 5)
1125 #define V_INT_STATUS_AFBCD1_HREG_DEC_RESP(x) VAL_MASK(x, 1, 6)
1126 #define V_INT_STATUS_AFBCD1_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 7)
1127 #define V_INT_STATUS_AFBCD2_HREG_DEC_RESP(x) VAL_MASK(x, 1, 8)
1128 #define V_INT_STATUS_AFBCD2_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 9)
1129 #define V_INT_STATUS_AFBCD3_HREG_DEC_RESP(x) VAL_MASK(x, 1, 10)
1130 #define V_INT_STATUS_AFBCD4_HREG_DEC_RESP(x) VAL_MASK(x, 1, 11)
1131 #define V_INT_STATUS_WB_YRGB_FIFO_FULL(x) VAL_MASK(x, 1, 12)
1132 #define V_INT_STATUS_WB_UV_FIFO_FULL(x) VAL_MASK(x, 1, 13)
1133 #define V_INT_STATUS_WB_DMA_FINISH(x) VAL_MASK(x, 1, 14)
1134 #define V_INT_STATUS_VFP(x) VAL_MASK(x, 1, 15)
1135 #define INTR_RAW_STATUS1 0x0000029c
1136 #define V_INT_RAW_STATUS_FBCD0(x) VAL_MASK(x, 1, 0)
1137 #define V_INT_RAW_STATUS_FBCD1(x) VAL_MASK(x, 1, 1)
1138 #define V_INT_RAW_STATUS_FBCD2(x) VAL_MASK(x, 1, 2)
1139 #define V_INT_RAW_STATUS_FBCD3(x) VAL_MASK(x, 1, 3)
1140 #define V_INT_RAW_STATUS_AFBCD0_HREG_DEC_RESP(x) VAL_MASK(x, 1, 4)
1141 #define V_INT_RAW_STATUS_AFBCD0_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 5)
1142 #define V_INT_RAW_STATUS_AFBCD1_HREG_DEC_RESP(x) VAL_MASK(x, 1, 6)
1143 #define V_INT_RAW_STATUS_AFBCD1_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 7)
1144 #define V_INT_RAW_STATUS_AFBCD2_HREG_DEC_RESP(x) VAL_MASK(x, 1, 8)
1145 #define V_INT_RAW_STATUS_AFBCD2_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 9)
1146 #define V_INT_RAW_STATUS_AFBCD3_HREG_DEC_RESP(x) VAL_MASK(x, 1, 10)
1147 #define V_INT_RAW_STATUS_AFBCD3_HREG_AXI_RRESP(x) VAL_MASK(x, 1, 11)
1148 #define V_INT_RAW_STATUS_WB_YRGB_FIFO_FULL(x) VAL_MASK(x, 1, 12)
1149 #define V_INT_RAW_STATUS_WB_UV_FIFO_FULL(x) VAL_MASK(x, 1, 13)
1150 #define V_INT_RAW_STATUS_WB_DMA_FINISH(x) VAL_MASK(x, 1, 14)
1151 #define V_INT_RAW_STATUS_VFP(x) VAL_MASK(x, 1, 15)
1152 #define LINE_FLAG 0x000002a0
1153 #define V_DSP_LINE_FLAG_NUM_0(x) VAL_MASK(x, 13, 0)
1154 #define V_DSP_LINE_FLAG_NUM_1(x) VAL_MASK(x, 13, 16)
1155 #define VOP_STATUS 0x000002a4
1156 #define V_DSP_VCNT(x) VAL_MASK(x, 13, 0)
1157 #define V_MMU_IDLE(x) VAL_MASK(x, 1, 16)
1158 #define V_DMA_STOP_VALID(x) VAL_MASK(x, 1, 17)
1159 #define BLANKING_VALUE 0x000002a8
1160 #define V_BLANKING_VALUE(x) VAL_MASK(x, 24, 0)
1161 #define V_BLANKING_VALUE_CONFIG_EN(x) VAL_MASK(x, 1, 24)
1162 #define MCU_BYPASS_PORT 0x000002ac
1163 #define WIN0_DSP_BG 0x000002b0
1164 #define V_WIN0_DSP_BG_BLUE(x) VAL_MASK(x, 10, 0)
1165 #define V_WIN0_DSP_BG_GREEN(x) VAL_MASK(x, 10, 10)
1166 #define V_WIN0_DSP_BG_RED(x) VAL_MASK(x, 10, 20)
1167 #define V_WIN0_BG_EN(x) VAL_MASK(x, 1, 31)
1168 #define WIN1_DSP_BG 0x000002b4
1169 #define V_WIN1_DSP_BG_BLUE(x) VAL_MASK(x, 10, 0)
1170 #define V_WIN1_DSP_BG_GREEN(x) VAL_MASK(x, 10, 10)
1171 #define V_WIN1_DSP_BG_RED(x) VAL_MASK(x, 10, 20)
1172 #define V_WIN1_BG_EN(x) VAL_MASK(x, 1, 31)
1173 #define WIN2_DSP_BG 0x000002b8
1174 #define V_WIN2_DSP_BG_BLUE(x) VAL_MASK(x, 10, 0)
1175 #define V_WIN2_DSP_BG_GREEN(x) VAL_MASK(x, 10, 10)
1176 #define V_WIN2_DSP_BG_RED(x) VAL_MASK(x, 10, 20)
1177 #define V_WIN2_BG_EN(x) VAL_MASK(x, 1, 31)
1178 #define WIN3_DSP_BG 0x000002bc
1179 #define V_WIN3_DSP_BG_BLUE(x) VAL_MASK(x, 10, 0)
1180 #define V_WIN3_DSP_BG_GREEN(x) VAL_MASK(x, 10, 10)
1181 #define V_WIN3_DSP_BG_RED(x) VAL_MASK(x, 10, 20)
1182 #define V_WIN3_BG_EN(x) VAL_MASK(x, 1, 31)
1183 #define YUV2YUV_WIN 0x000002c0
1184 #define V_WIN0_YUV2YUV_EN(x) VAL_MASK(x, 1, 0)
1185 #define V_WIN0_YUV2YUV_Y2R_EN(x) VAL_MASK(x, 1, 1)
1186 #define V_WIN0_YUV2YUV_R2Y_EN(x) VAL_MASK(x, 1, 2)
1187 #define V_WIN0_YUV2YUV_GAMMA_MODE(x) VAL_MASK(x, 1, 3)
1188 #define V_WIN0_YUV2YUV_Y2R_MODE(x) VAL_MASK(x, 2, 4)
1189 #define V_WIN0_YUV2YUV_R2Y_MODE(x) VAL_MASK(x, 2, 6)
1190 #define V_WIN1_YUV2YUV_EN(x) VAL_MASK(x, 1, 8)
1191 #define V_WIN1_YUV2YUV_Y2R_EN(x) VAL_MASK(x, 1, 9)
1192 #define V_WIN1_YUV2YUV_R2Y_EN(x) VAL_MASK(x, 1, 10)
1193 #define V_WIN1_YUV2YUV_GAMMA_MODE(x) VAL_MASK(x, 1, 11)
1194 #define V_WIN1_YUV2YUV_Y2R_MODE(x) VAL_MASK(x, 2, 12)
1195 #define V_WIN1_YUV2YUV_R2Y_MODE(x) VAL_MASK(x, 2, 14)
1196 #define V_WIN2_YUV2YUV_EN(x) VAL_MASK(x, 1, 16)
1197 #define V_WIN2_YUV2YUV_R2Y_EN(x) VAL_MASK(x, 1, 18)
1198 #define V_WIN2_YUV2YUV_GAMMA_MODE(x) VAL_MASK(x, 1, 19)
1199 #define V_WIN2_YUV2YUV_R2Y_MODE(x) VAL_MASK(x, 2, 22)
1200 #define V_WIN3_YUV2YUV_EN(x) VAL_MASK(x, 1, 24)
1201 #define V_WIN3_YUV2YUV_R2Y_EN(x) VAL_MASK(x, 1, 26)
1202 #define V_WIN3_YUV2YUV_GAMMA_MODE(x) VAL_MASK(x, 1, 27)
1203 #define V_WIN3_YUV2YUV_R2Y_MODE(x) VAL_MASK(x, 2, 30)
1204 #define YUV2YUV_POST 0x000002c4
1205 #define V_YUV2YUV_POST_EN(x) VAL_MASK(x, 1, 0)
1206 #define V_YUV2YUV_POST_Y2R_EN(x) VAL_MASK(x, 1, 1)
1207 #define V_YUV2YUV_POST_R2Y_EN(x) VAL_MASK(x, 1, 2)
1208 #define V_YUV2YUV_GAMMA_MODE(x) VAL_MASK(x, 1, 3)
1209 #define V_YUV2YUV_POST_Y2R_MODE(x) VAL_MASK(x, 2, 4)
1210 #define V_YUV2YUV_POST_R2Y_MODE(x) VAL_MASK(x, 2, 6)
1211 #define AUTO_GATING_EN 0x000002cc
1212 #define V_WIN0_ACLK_GATING_EN(x) VAL_MASK(x, 1, 0)
1213 #define V_WIN1_ACLK_GATING_EN(x) VAL_MASK(x, 1, 1)
1214 #define V_WIN2_ACLK_GATING_EN(x) VAL_MASK(x, 1, 2)
1215 #define V_WIN3_ACLK_GATING_EN(x) VAL_MASK(x, 1, 3)
1216 #define V_HWC_ACLK_GATING_EN(x) VAL_MASK(x, 1, 4)
1217 #define V_OVERLAY_ACLK_GATING_EN(x) VAL_MASK(x, 1, 5)
1218 #define V_GAMMA_ACLK_GATING_EN(x) VAL_MASK(x, 1, 6)
1219 #define V_CABC_ACLK_GATING_EN(x) VAL_MASK(x, 1, 7)
1220 #define V_WB_ACLK_GATING_EN(x) VAL_MASK(x, 1, 8)
1221 #define V_PWM_PWMCLK_GATING_EN(x) VAL_MASK(x, 1, 9)
1222 #define V_DIRECT_PATH_ACLK_GATING_EN(x) VAL_MASK(x, 1, 10)
1223 #define V_FBCD0_ACLK_GATING_EN(x) VAL_MASK(x, 1, 12)
1224 #define V_FBCD1_ACLK_GATING_EN(x) VAL_MASK(x, 1, 13)
1225 #define V_FBCD2_ACLK_GATING_EN(x) VAL_MASK(x, 1, 14)
1226 #define V_FBCD3_ACLK_GATING_EN(x) VAL_MASK(x, 1, 15)
1227 #define DBG_PERF_LATENCY_CTRL0 0x00000300
1228 #define V_RD_LATENCY_EN(x) VAL_MASK(x, 1, 0)
1229 #define V_HAND_LATENCY_CLR(x) VAL_MASK(x, 1, 1)
1230 #define V_RD_LATENCY_MODE(x) VAL_MASK(x, 1, 2)
1231 #define V_RD_LATENCY_ID0(x) VAL_MASK(x, 4, 4)
1232 #define V_RD_LATENCY_THR(x) VAL_MASK(x, 12, 8)
1233 #define V_RD_LATENCY_ST_NUM(x) VAL_MASK(x, 5, 20)
1234 #define DBG_PERF_RD_MAX_LATENCY_NUM0 0x00000304
1235 #define V_RD_MAX_LATENCY_NUM_CH0(x) VAL_MASK(x, 12, 0)
1236 #define V_RD_LATENCY_OVERFLOW_CH0(x) VAL_MASK(x, 1, 16)
1237 #define DBG_PERF_RD_LATENCY_THR_NUM0 0x00000308
1238 #define V_RD_LATENCY_THR_NUM_CH0(x) VAL_MASK(x, 24, 0)
1239 #define DBG_PERF_RD_LATENCY_SAMP_NUM0 0x0000030c
1240 #define V_RD_LATENCY_SAMP_NUM_CH0(x) VAL_MASK(x, 24, 0)
1241 #define DBG_CABC0 0x00000310
1242 #define DBG_CABC1 0x00000314
1243 #define DBG_CABC2 0x00000318
1244 #define V_PWM_MUL_POST_VALUE(x) VAL_MASK(x, 8, 8)
1245 #define DBG_CABC3 0x0000031c
1246 #define DBG_WIN0_REG0 0x00000320
1247 #define DBG_WIN0_REG1 0x00000324
1248 #define DBG_WIN0_REG2 0x00000328
1249 #define V_DBG_WIN0_YRGB_CMD_LINE_CNT(x) VAL_MASK(x, 13, 16)
1250 #define DBG_WIN0_RESERVED 0x0000032c
1251 #define DBG_WIN1_REG0 0x00000330
1252 #define DBG_WIN1_REG1 0x00000334
1253 #define DBG_WIN1_REG2 0x00000338
1254 #define DBG_WIN1_RESERVED 0x0000033c
1255 #define DBG_WIN2_REG0 0x00000340
1256 #define DBG_WIN2_REG1 0x00000344
1257 #define DBG_WIN2_REG2 0x00000348
1258 #define DBG_WIN2_REG3 0x0000034c
1259 #define DBG_WIN3_REG0 0x00000350
1260 #define DBG_WIN3_REG1 0x00000354
1261 #define DBG_WIN3_REG2 0x00000358
1262 #define DBG_WIN3_REG3 0x0000035c
1263 #define DBG_PRE_REG0 0x00000360
1264 #define DBG_PRE_RESERVED 0x00000364
1265 #define DBG_POST_REG0 0x00000368
1266 #define DBG_POST_REG1 0x0000036c
1267 #define V_GAMMA_A2HCLK_CHANGE_DONE(x) VAL_MASK(x, 1, 0)
1268 #define V_WHICH_GAMMA_LUT_WORKING(x) VAL_MASK(x, 1, 1)
1269 #define DBG_DATAO 0x00000370
1270 #define V_SW_DATAO_SEL(x) VAL_MASK(x, 2, 30)
1271 #define DBG_DATAO_2 0x00000374
1272 #define V_VOP_DATA_O_2(x) VAL_MASK(x, 30, 0)
1273 #define V_SW_DATAO_SEL_2(x) VAL_MASK(x, 2, 30)
1274 #define WIN0_CSC_COE 0x000003a0
1275 #define WIN1_CSC_COE 0x000003c0
1276 #define WIN2_CSC_COE 0x000003e0
1277 #define WIN3_CSC_COE 0x00000400
1278 #define HWC_CSC_COE 0x00000420
1279 #define BCSH_R2Y_CSC_COE 0x00000440
1280 #define BCSH_Y2R_CSC_COE 0x00000460
1281 #define POST_YUV2YUV_Y2R_COE 0x00000480
1282 #define POST_YUV2YUV_3x3_COE 0x000004a0
1283 #define POST_YUV2YUV_R2Y_COE 0x000004c0
1284 #define WIN0_YUV2YUV_Y2R 0x000004e0
1285 #define WIN0_YUV2YUV_R2R 0x00000500
1286 #define WIN0_YUV2YUV_R2Y 0x00000520
1287 #define WIN1_YUV2YUV_Y2R 0x00000540
1288 #define WIN1_YUV2YUV_R2R 0x00000560
1289 #define WIN1_YUV2YUV_R2Y 0x00000580
1290 #define WIN2_YUV2YUV_Y2R 0x000005a0
1291 #define WIN2_YUV2YUV_R2R 0x000005c0
1292 #define WIN2_YUV2YUV_R2Y 0x000005e0
1293 #define WIN3_YUV2YUV_Y2R 0x00000600
1294 #define WIN3_YUV2YUV_R2R 0x00000620
1295 #define WIN3_YUV2YUV_R2Y 0x00000640
1296 #define WIN2_LUT_ADDR 0x00001000
1297 #define V_WIN2_LUT_ADDR(x) VAL_MASK(x, 32, 0)
1298 #define WIN3_LUT_ADDR 0x00001400
1299 #define V_WIN3_LUT_ADDR(x) VAL_MASK(x, 32, 0)
1300 #define HWC_LUT_ADDR 0x00001800
1301 #define V_HWC_LUT_ADDR(x) VAL_MASK(x, 32, 0)
1302 #define CABC_GAMMA_LUT_ADDR 0x00001c00
1303 #define V_GAMMA_LUT_ADDR(x) VAL_MASK(x, 32, 0)
1304 #define GAMMA_LUT_ADDR 0x00002000
1305 #define V_GAMMA_LUT_ADDR(x) VAL_MASK(x, 32, 0)
1306 #define TVE 0x00003e00
1308 #define INTR_FS (1 << 0)
1309 #define INTR_FS_NEW (1 << 1)
1310 #define INTR_ADDR_SAME (1 << 2)
1311 #define INTR_LINE_FLAG0 (1 << 3)
1312 #define INTR_LINE_FLAG1 (1 << 4)
1313 #define INTR_BUS_ERROR (1 << 5)
1314 #define INTR_WIN0_EMPTY (1 << 6)
1315 #define INTR_WIN1_EMPTY (1 << 7)
1316 #define INTR_WIN2_EMPTY (1 << 8)
1317 #define INTR_WIN3_EMPTY (1 << 9)
1318 #define INTR_HWC_EMPTY (1 << 10)
1319 #define INTR_POST_BUF_EMPTY (1 << 11)
1321 #define INTR_PWM_GEN (1 << 12)
1323 #define INTR_FS_FIELD (1 << 12)
1324 #define INTR_DSP_HOLD_VALID (1 << 13)
1325 #define INTR_MMU (1 << 14)
1326 #define INTR_DMA_FINISH (1 << 15)
1328 #define INTR_MASK (INTR_FS | INTR_FS_NEW | INTR_ADDR_SAME | INTR_LINE_FLAG0 | \
1329 INTR_LINE_FLAG1 | INTR_BUS_ERROR | INTR_WIN0_EMPTY | \
1330 INTR_WIN1_EMPTY | INTR_WIN2_EMPTY | INTR_WIN3_EMPTY | \
1331 INTR_HWC_EMPTY | INTR_POST_BUF_EMPTY | INTR_PWM_GEN | \
1332 INTR_DSP_HOLD_VALID | INTR_MMU | INTR_DMA_FINISH)
1334 #define INTR1_FBCD0 (1 << 0)
1335 #define INTR1_FBCD1 (1 << 1)
1336 #define INTR1_FBCD2 (1 << 2)
1337 #define INTR1_FBCD3 (1 << 3)
1338 #define INTR1_AFBCD0_HREG_DEC_RESP (1 << 4)
1339 #define INTR1_AFBCD0_HREG_AXI_RRESP (1 << 5)
1340 #define INTR1_AFBCD1_HREG_DEC_RESP (1 << 6)
1341 #define INTR1_AFBCD1_HREG_AXI_RRESP (1 << 7)
1342 #define INTR1_AFBCD2_HREG_DEC_RESP (1 << 8)
1343 #define INTR1_AFBCD2_HREG_AXI_RRESP (1 << 9)
1344 #define INTR1_AFBCD3_HREG_DEC_RESP (1 << 10)
1345 #define INTR1_AFBCD3_HREG_AXI_RRESP (1 << 11)
1346 #define INTR1_WB_YRGB_FIFO_FULL (1 << 12)
1347 #define INTR1_WB_UV_FIFO_FULL (1 << 13)
1348 #define INTR1_WB_FINISH (1 << 14)
1350 #define OUT_CCIR656_MODE_0 5
1351 #define OUT_CCIR656_MODE_1 6
1352 #define OUT_CCIR656_MODE_2 7
1354 enum cabc_stage_mode {
1355 LAST_FRAME_PWM_VAL = 0x0,
1356 CUR_FRAME_PWM_VAL = 0x1,
1357 STAGE_BY_STAGE = 0x2
1376 struct rk_lcdc_win *win;
1382 const struct vop_data *data;
1383 struct rk_lcdc_driver driver;
1385 struct rk_screen *screen;
1386 struct regmap *grf_base;
1393 int __iomem *dsp_lut_addr_base;
1394 int __iomem *cabc_lut_addr_base;
1395 /* one time only one process allowed to config the register */
1396 spinlock_t reg_lock;
1398 int prop; /*used for primary or extended display device*/
1400 bool pwr18; /*if lcdc use 1.8v power supply*/
1401 /*if aclk or hclk is closed ,acess to register is not allowed*/
1403 /*active layer counter,when atv_layer_cnt = 0,disable lcdc*/
1405 /* point write back status */
1410 struct clk *hclk; /*lcdc AHP clk*/
1411 struct clk *dclk; /*lcdc dclk*/
1412 struct clk *aclk; /*lcdc share memory frequency*/
1413 struct clk *hclk_noc;
1414 struct clk *aclk_noc;
1417 u32 standby; /*1:standby,0:wrok*/
1419 struct backlight_device *backlight;
1420 struct clk *pll_sclk;
1422 /* lock vop irq reg */
1423 spinlock_t irq_lock;
1426 static inline void vop_writel(struct vop_device *vop_dev, u32 offset, u32 v)
1428 u32 *_pv = (u32 *)vop_dev->regsbak;
1430 _pv += (offset >> 2);
1432 writel_relaxed(v, vop_dev->regs + offset);
1435 static inline u32 vop_readl(struct vop_device *vop_dev, u32 offset)
1439 v = readl_relaxed(vop_dev->regs + offset);
1443 static inline u32 vop_readl_backup(struct vop_device *vop_dev, u32 offset)
1446 u32 *_pv = (u32 *)vop_dev->regsbak;
1448 _pv += (offset >> 2);
1449 v = readl_relaxed(vop_dev->regs + offset);
1454 static inline u32 vop_read_bit(struct vop_device *vop_dev, u32 offset, u64 v)
1456 u32 _v = readl_relaxed(vop_dev->regs + offset);
1463 static inline void vop_set_bit(struct vop_device *vop_dev, u32 offset, u64 v)
1465 u32 *_pv = (u32 *)vop_dev->regsbak;
1467 _pv += (offset >> 2);
1469 writel_relaxed(*_pv, vop_dev->regs + offset);
1472 static inline void vop_clr_bit(struct vop_device *vop_dev, u32 offset, u64 v)
1474 u32 *_pv = (u32 *)vop_dev->regsbak;
1476 _pv += (offset >> 2);
1477 (*_pv) &= (~(v >> 32));
1478 writel_relaxed(*_pv, vop_dev->regs + offset);
1481 static inline void vop_msk_reg(struct vop_device *vop_dev, u32 offset, u64 v)
1483 u32 *_pv = (u32 *)vop_dev->regsbak;
1485 _pv += (offset >> 2);
1486 (*_pv) &= (~(v >> 32));
1488 writel_relaxed(*_pv, vop_dev->regs + offset);
1491 static inline void vop_msk_reg_nobak(struct vop_device *vop_dev,
1494 u32 *_pv = (u32 *)vop_dev->regsbak;
1496 _pv += (offset >> 2);
1497 writel_relaxed((*_pv & (~(v >> 32))) | (u32)v, vop_dev->regs + offset);
1500 static inline void vop_mask_writel(struct vop_device *vop_dev, u32 offset,
1504 writel_relaxed(v , vop_dev->regs + offset);
1507 static inline void vop_cfg_done(struct vop_device *vop_dev)
1509 writel_relaxed(0x001f001f, vop_dev->regs + REG_CFG_DONE);
1513 static inline int vop_grf_writel(struct regmap *base, u32 offset, u32 val)
1515 regmap_write(base, offset, val);
1521 static inline int vop_cru_writel(struct regmap *base, u32 offset, u32 val)
1523 regmap_write(base, offset, val);
1529 static inline int vop_cru_readl(struct regmap *base, u32 offset)
1533 regmap_read(base, offset, &v);
1539 LB_YUV_3840X5 = 0x0,
1540 LB_YUV_2560X8 = 0x1,
1541 LB_RGB_3840X2 = 0x2,
1542 LB_RGB_2560X4 = 0x3,
1543 LB_RGB_1920X5 = 0x4,
1547 enum sacle_up_mode {
1552 enum scale_down_mode {
1553 SCALE_DOWN_BIL = 0x0,
1554 SCALE_DOWN_AVG = 0x1
1557 /*ALPHA BLENDING MODE*/
1558 enum alpha_mode { /* Fs Fd */
1559 AB_USER_DEFINE = 0x0,
1560 AB_CLEAR = 0x1,/* 0 0*/
1561 AB_SRC = 0x2,/* 1 0*/
1562 AB_DST = 0x3,/* 0 1 */
1563 AB_SRC_OVER = 0x4,/* 1 1-As''*/
1564 AB_DST_OVER = 0x5,/* 1-Ad'' 1*/
1572 AB_SRC_OVER_GLOBAL = 0xd
1573 }; /*alpha_blending_mode*/
1575 enum src_alpha_mode {
1578 };/*src_alpha_mode*/
1580 enum global_alpha_mode {
1583 AA_PER_PIX_GLOBAL = 0x2
1584 };/*src_global_alpha_mode*/
1586 enum src_alpha_sel {
1591 enum src_color_mode {
1592 AA_SRC_PRE_MUL = 0x0,
1593 AA_SRC_NO_PRE_MUL = 0x1
1594 };/*src_color_mode*/
1600 AA_SRC_INVERSE = 0x3,
1602 };/*src_factor_mode && dst_factor_mode*/
1604 enum _vop_r2y_csc_mode {
1605 VOP_R2Y_CSC_BT601 = 0,
1609 enum _vop_y2r_csc_mode {
1610 VOP_Y2R_CSC_MPEG = 0,
1616 VOP_FORMAT_ARGB888 = 0,
1619 VOP_FORMAT_YCBCR420 = 4,
1620 VOP_FORMAT_YCBCR422,
1624 #define IS_YUV(x) ((x) >= VOP_FORMAT_YCBCR420)
1626 enum _vop_overlay_mode {
1631 struct alpha_config {
1632 enum src_alpha_mode src_alpha_mode; /*win0_src_alpha_m0*/
1633 u32 src_global_alpha_val; /*win0_src_global_alpha*/
1634 enum global_alpha_mode src_global_alpha_mode;/*win0_src_blend_m0*/
1635 enum src_alpha_sel src_alpha_cal_m0; /*win0_src_alpha_cal_m0*/
1636 enum src_color_mode src_color_mode; /*win0_src_color_m0*/
1637 enum factor_mode src_factor_mode; /*win0_src_factor_m0*/
1638 enum factor_mode dst_factor_mode; /*win0_dst_factor_m0*/
1641 struct lcdc_cabc_mode {
1642 u32 pixel_num; /* pixel precent number */
1643 u16 stage_up; /* up stride */
1644 u16 stage_down; /* down stride */
1648 #define CUBIC_PRECISE 0
1649 #define CUBIC_SPLINE 1
1650 #define CUBIC_CATROM 2
1651 #define CUBIC_MITCHELL 3
1653 #define AFBDC_FMT_RGB565 0x0
1654 #define AFBDC_FMT_U8U8U8U8 0x5 /*ARGB888*/
1655 #define AFBDC_FMT_U8U8U8 0x4 /*RGBP888*/
1657 #define CUBIC_MODE_SELETION CUBIC_PRECISE
1659 /*************************************************************/
1660 #define SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT 12 /* 4.12*/
1661 #define SCALE_FACTOR_BILI_DN_FIXPOINT(x) \
1662 ((INT32)((x) * (1 << SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT)))
1664 #define SCALE_FACTOR_BILI_UP_FIXPOINT_SHIFT 16 /* 0.16*/
1666 #define SCALE_FACTOR_AVRG_FIXPOINT_SHIFT 16 /*0.16*/
1667 #define SCALE_FACTOR_AVRG_FIXPOINT(x) \
1668 ((INT32)((x) * (1 << SCALE_FACTOR_AVRG_FIXPOINT_SHIFT)))
1670 #define SCALE_FACTOR_BIC_FIXPOINT_SHIFT 16 /* 0.16*/
1671 #define SCALE_FACTOR_BIC_FIXPOINT(x) \
1672 ((INT32)((x) * (1 << SCALE_FACTOR_BIC_FIXPOINT_SHIFT)))
1674 #define SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT 12 /*NONE SCALE,vsd_bil*/
1675 #define SCALE_FACTOR_VSDBIL_FIXPOINT_SHIFT 12 /*VER SCALE DOWN BIL*/
1677 /*********************************************************/
1679 /*#define GET_SCALE_FACTOR_BILI(src, dst) \
1680 ((((src) - 1) << SCALE_FACTOR_BILI_FIXPOINT_SHIFT) / ((dst) - 1))*/
1681 /*#define GET_SCALE_FACTOR_BIC(src, dst) \
1682 ((((src) - 1) << SCALE_FACTOR_BIC_FIXPOINT_SHIFT) / ((dst) - 1))*/
1684 #define GET_SCALE_FACTOR_BILI_DN(src, dst) \
1685 ((((src) * 2 - 3) << (SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT - 1)) \
1687 #define GET_SCALE_FACTOR_BILI_UP(src, dst) \
1688 ((((src) * 2 - 3) << (SCALE_FACTOR_BILI_UP_FIXPOINT_SHIFT - 1)) \
1690 #define GET_SCALE_FACTOR_BIC(src, dst) \
1691 ((((src) * 2 - 3) << (SCALE_FACTOR_BIC_FIXPOINT_SHIFT - 1)) \
1694 /*********************************************************/
1695 /*NOTE: hardware in order to save resource , srch first to get interlace line
1696 (srch+vscalednmult-1)/vscalednmult; and do scale*/
1697 #define GET_SCALE_DN_ACT_HEIGHT(srch, vscalednmult) \
1698 (((srch) + (vscalednmult) - 1) / (vscalednmult))
1700 /*#define VSKIP_MORE_PRECISE*/
1702 #ifdef VSKIP_MORE_PRECISE
1703 #define MIN_SCALE_FACTOR_AFTER_VSKIP 1.5f
1704 #define GET_SCALE_FACTOR_BILI_DN_VSKIP(srch, dsth, vscalednmult) \
1705 (GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT((srch),\
1706 (vscalednmult)), (dsth)))
1708 #define MIN_SCALE_FACTOR_AFTER_VSKIP 1
1709 #define GET_SCALE_FACTOR_BILI_DN_VSKIP(srch, dsth, vscalednmult) \
1710 ((GET_SCALE_DN_ACT_HEIGHT((srch) , (vscalednmult)) == (dsth)) \
1711 ? (GET_SCALE_FACTOR_BILI_DN((srch) , (dsth)) / (vscalednmult)) \
1712 : (GET_SCALE_DN_ACT_HEIGHT((srch) , (vscalednmult)) == ((dsth) * 2)) \
1713 ? GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT(((srch) - 1),\
1714 (vscalednmult)) , (dsth)) : \
1715 GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT((srch),\
1716 (vscalednmult)) , (dsth)))
1719 /*****************************************************************/
1721 /*scalefactor must >= dst/src, or pixels at end of line may be unused*/
1722 /*scalefactor must < dst/(src-1), or dst buffer may overflow*/
1723 /*avrg old code: ((((dst) << SCALE_FACTOR_AVRG_FIXPOINT_SHIFT))\
1724 /((src) - 1)) hxx_chgsrc*/
1725 /*modified by hpz:*/
1726 #define GET_SCALE_FACTOR_AVRG(src, dst) ((((dst) << \
1727 (SCALE_FACTOR_AVRG_FIXPOINT_SHIFT + 1))) / (2 * (src) - 1))
1729 /*************************************************************************/
1730 /*Scale Coordinate Accumulate, x.16*/
1731 #define SCALE_COOR_ACC_FIXPOINT_SHIFT 16
1732 #define SCALE_COOR_ACC_FIXPOINT_ONE (1 << SCALE_COOR_ACC_FIXPOINT_SHIFT)
1733 #define SCALE_COOR_ACC_FIXPOINT(x) \
1734 ((INT32)((x)*(1 << SCALE_COOR_ACC_FIXPOINT_SHIFT)))
1735 #define SCALE_COOR_ACC_FIXPOINT_REVERT(x) \
1736 ((((x) >> (SCALE_COOR_ACC_FIXPOINT_SHIFT - 1)) + 1) >> 1)
1738 #define SCALE_GET_COOR_ACC_FIXPOINT(scalefactor, factorfixpointshift) \
1740 (SCALE_COOR_ACC_FIXPOINT_SHIFT - (factorfixpointshift)))
1742 /************************************************************************/
1743 /*CoarsePart of Scale Coordinate Accumulate, used for pixel mult-add factor, 0.8*/
1744 #define SCALE_FILTER_FACTOR_FIXPOINT_SHIFT 8
1745 #define SCALE_FILTER_FACTOR_FIXPOINT_ONE \
1746 (1 << SCALE_FILTER_FACTOR_FIXPOINT_SHIFT)
1747 #define SCALE_FILTER_FACTOR_FIXPOINT(x) \
1748 ((INT32)((x) * (1 << SCALE_FILTER_FACTOR_FIXPOINT_SHIFT)))
1749 #define SCALE_FILTER_FACTOR_FIXPOINT_REVERT(x) \
1750 ((((x) >> (SCALE_FILTER_FACTOR_FIXPOINT_SHIFT-1)) + 1) >> 1)
1752 #define SCALE_GET_FILTER_FACTOR_FIXPOINT(cooraccumulate, \
1753 cooraccfixpointshift) \
1754 (((cooraccumulate) >> \
1755 ((cooraccfixpointshift) - SCALE_FILTER_FACTOR_FIXPOINT_SHIFT)) & \
1756 (SCALE_FILTER_FACTOR_FIXPOINT_ONE - 1))
1758 #define SCALE_OFFSET_FIXPOINT_SHIFT 8
1759 #define SCALE_OFFSET_FIXPOINT(x) \
1760 ((INT32)((x) * (1 << SCALE_OFFSET_FIXPOINT_SHIFT)))
1762 static inline u32 vop_get_hard_ware_vskiplines(u32 srch, u32 dsth)
1766 if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
1768 else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
1773 return vscalednmult;
projects / firefly-linux-kernel-4.4.55.git / blob