drivers/video/rockchip/lcdc/rk322x_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk322x_lcdc.c
   3  *
   4  * Copyright (C) 2015 ROCKCHIP, Inc.
   5  * Author: Mark Yao <mark.yao@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk322x_lcdc.h"
  39
  40 /*#define CONFIG_RK_FPGA 1*/
  41
  42 static int dbg_thresd;
  43 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  44
  45 #define DBG(level, x...) do {                   \
  46         if (unlikely(dbg_thresd >= level))      \
  47                 pr_info(x);\
  48         } while (0)
  49
  50 static const uint32_t csc_y2r_bt601_limit[12] = {
  51         0x04a8,      0,  0x0662, 0xfffc8654,
  52         0x04a8, 0xfe6f,  0xfcbf, 0x00022056,
  53         0x04a8, 0x0812,       0, 0xfffbaeac,
  54 };
  55
  56 static const uint32_t csc_y2r_bt709_full[12] = {
  57         0x04a8,      0,  0x072c, 0xfffc219e,
  58         0x04a8, 0xff26,  0xfdde, 0x0001357b,
  59         0x04a8, 0x0873,       0, 0xfffb7dee,
  60 };
  61
  62 static const uint32_t csc_y2r_bt601_full[12] = {
  63         0x0400,      0,  0x059c, 0xfffd342d,
  64         0x0400, 0xfea0,  0xfd25, 0x00021fcc,
  65         0x0400, 0x0717,       0, 0xfffc76bc,
  66 };
  67
  68 static const uint32_t csc_y2r_bt601_limit_10[12] = {
  69         0x04a8,      0,  0x0662, 0xfff2134e,
  70         0x04a8, 0xfe6f,  0xfcbf, 0x00087b58,
  71         0x04a8, 0x0812,       0, 0xffeeb4b0,
  72 };
  73
  74 static const uint32_t csc_y2r_bt709_full_10[12] = {
  75         0x04a8,      0,  0x072c, 0xfff08077,
  76         0x04a8, 0xff26,  0xfdde, 0x0004cfed,
  77         0x04a8, 0x0873,       0, 0xffedf1b8,
  78 };
  79
  80 static const uint32_t csc_y2r_bt601_full_10[12] = {
  81         0x0400,      0,  0x059c, 0xfff4cab4,
  82         0x0400, 0xfea0,  0xfd25, 0x00087932,
  83         0x0400, 0x0717,       0, 0xfff1d4f2,
  84 };
  85
  86 static const uint32_t csc_y2r_bt2020[12] = {
  87         0x04a8,      0, 0x06b6, 0xfff16bfc,
  88         0x04a8, 0xff40, 0xfd66, 0x58ae9,
  89         0x04a8, 0x0890,      0, 0xffedb828,
  90 };
  91
  92 static const uint32_t csc_r2y_bt601_limit[12] = {
  93         0x0107, 0x0204, 0x0064, 0x04200,
  94         0xff68, 0xfed6, 0x01c2, 0x20200,
  95         0x01c2, 0xfe87, 0xffb7, 0x20200,
  96 };
  97
  98 static const uint32_t csc_r2y_bt709_full[12] = {
  99         0x00bb, 0x0275, 0x003f, 0x04200,
 100         0xff99, 0xfea5, 0x01c2, 0x20200,
 101         0x01c2, 0xfe68, 0xffd7, 0x20200,
 102 };
 103
 104 static const uint32_t csc_r2y_bt601_full[12] = {
 105         0x0132, 0x0259, 0x0075, 0x200,
 106         0xff53, 0xfead, 0x0200, 0x20200,
 107         0x0200, 0xfe53, 0xffad, 0x20200,
 108 };
 109
 110 static const uint32_t csc_r2y_bt601_limit_10[12] = {
 111         0x0107, 0x0204, 0x0064, 0x10200,
 112         0xff68, 0xfed6, 0x01c2, 0x80200,
 113         0x01c2, 0xfe87, 0xffb7, 0x80200,
 114 };
 115
 116 static const uint32_t csc_r2y_bt709_full_10[12] = {
 117         0x00bb, 0x0275, 0x003f, 0x10200,
 118         0xff99, 0xfea5, 0x01c2, 0x80200,
 119         0x01c2, 0xfe68, 0xffd7, 0x80200,
 120 };
 121
 122 static const uint32_t csc_r2y_bt601_full_10[12] = {
 123         0x0132, 0x0259, 0x0075, 0x200,
 124         0xff53, 0xfead, 0x0200, 0x80200,
 125         0x0200, 0xfe53, 0xffad, 0x80200,
 126 };
 127
 128 static const uint32_t csc_r2y_bt2020[12] = {
 129         0x00e6, 0x0253, 0x0034, 0x10200,
 130         0xff83, 0xfebd, 0x01c1, 0x80200,
 131         0x01c1, 0xfe64, 0xffdc, 0x80200,
 132 };
 133
 134 static const uint32_t csc_r2r_bt2020to709[12] = {
 135         0x06a4, 0xfda6, 0xffb5, 0x200,
 136         0xff80, 0x0488, 0xfff8, 0x200,
 137         0xffed, 0xff99, 0x047a, 0x200,
 138 };
 139
 140 static const uint32_t csc_r2r_bt709to2020[12] = {
 141         0x282, 0x151, 0x02c, 0x200,
 142         0x047, 0x3ae, 0x00c, 0x200,
 143         0x011, 0x05a, 0x395, 0x200,
 144 };
 145
 146 static struct rk_lcdc_win vop_win[] = {
 147         { .name = "win0", .id = 0},
 148         { .name = "win1", .id = 1},
 149         { .name = "hwc",  .id = 2}
 150 };
 151
 152 static void vop_load_csc_table(struct vop_device *vop_dev, u32 offset,
 153                                const uint32_t *table)
 154 {
 155         uint32_t csc_val;
 156
 157         csc_val = table[1] << 16 | table[0];
 158         vop_writel(vop_dev, offset, csc_val);
 159         csc_val = table[4] << 16 | table[2];
 160         vop_writel(vop_dev, offset + 4, csc_val);
 161         csc_val = table[6] << 16 | table[5];
 162         vop_writel(vop_dev, offset + 8, csc_val);
 163         csc_val = table[9] << 16 | table[8];
 164         vop_writel(vop_dev, offset + 0xc, csc_val);
 165         csc_val = table[10];
 166         vop_writel(vop_dev, offset + 0x10, csc_val);
 167         csc_val = table[3];
 168         vop_writel(vop_dev, offset + 0x14, csc_val);
 169         csc_val = table[7];
 170         vop_writel(vop_dev, offset + 0x18, csc_val);
 171         csc_val = table[11];
 172         vop_writel(vop_dev, offset + 0x1c, csc_val);
 173 }
 174
 175 static int vop_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
 176
 177 static int vop_clk_enable(struct vop_device *vop_dev)
 178 {
 179         if (!vop_dev->clk_on) {
 180                 clk_prepare_enable(vop_dev->hclk);
 181                 clk_prepare_enable(vop_dev->dclk);
 182                 clk_prepare_enable(vop_dev->aclk);
 183                 clk_prepare_enable(vop_dev->hclk_noc);
 184                 clk_prepare_enable(vop_dev->aclk_noc);
 185                 spin_lock(&vop_dev->reg_lock);
 186                 vop_dev->clk_on = 1;
 187                 spin_unlock(&vop_dev->reg_lock);
 188         }
 189
 190         return 0;
 191 }
 192
 193 static int vop_clk_disable(struct vop_device *vop_dev)
 194 {
 195         if (vop_dev->clk_on) {
 196                 spin_lock(&vop_dev->reg_lock);
 197                 vop_dev->clk_on = 0;
 198                 spin_unlock(&vop_dev->reg_lock);
 199                 mdelay(25);
 200                 clk_disable_unprepare(vop_dev->dclk);
 201                 clk_disable_unprepare(vop_dev->hclk);
 202                 clk_disable_unprepare(vop_dev->aclk);
 203                 clk_disable_unprepare(vop_dev->hclk_noc);
 204                 clk_disable_unprepare(vop_dev->aclk_noc);
 205         }
 206
 207         return 0;
 208 }
 209
 210 static int __maybe_unused vop_disable_irq(struct vop_device *vop_dev)
 211 {
 212         if (likely(vop_dev->clk_on)) {
 213                 spin_lock(&vop_dev->reg_lock);
 214                 vop_writel(vop_dev, INTR_EN0, 0xffff0000);
 215                 vop_writel(vop_dev, INTR_EN1, 0xffff0000);
 216                 vop_writel(vop_dev, INTR_CLEAR0, 0xffffffff);
 217                 vop_writel(vop_dev, INTR_CLEAR1, 0xffffffff);
 218                 vop_cfg_done(vop_dev);
 219                 spin_unlock(&vop_dev->reg_lock);
 220         };
 221
 222         return 0;
 223 }
 224
 225 static int vop_reg_dump(struct rk_lcdc_driver *dev_drv)
 226 {
 227         struct vop_device *vop_dev =
 228             container_of(dev_drv, struct vop_device, driver);
 229         int *cbase = (int *)vop_dev->regs;
 230         int *regsbak = (int *)vop_dev->regsbak;
 231         int i, j, val;
 232         char dbg_message[30];
 233         char buf[10];
 234
 235         pr_info("lcd back up reg:\n");
 236         memset(dbg_message, 0, sizeof(dbg_message));
 237         memset(buf, 0, sizeof(buf));
 238         for (i = 0; i <= (0x200 >> 4); i++) {
 239                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 240                 for (j = 0; j < 4; j++) {
 241                         val = sprintf(buf, "%08x  ", *(regsbak + i * 4 + j));
 242                         strcat(dbg_message, buf);
 243                 }
 244                 pr_info("%s\n", dbg_message);
 245                 memset(dbg_message, 0, sizeof(dbg_message));
 246                 memset(buf, 0, sizeof(buf));
 247         }
 248
 249         pr_info("lcdc reg:\n");
 250         for (i = 0; i <= (0x200 >> 4); i++) {
 251                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 252                 for (j = 0; j < 4; j++) {
 253                         sprintf(buf, "%08x  ",
 254                                 readl_relaxed(cbase + i * 4 + j));
 255                         strcat(dbg_message, buf);
 256                 }
 257                 pr_info("%s\n", dbg_message);
 258                 memset(dbg_message, 0, sizeof(dbg_message));
 259                 memset(buf, 0, sizeof(buf));
 260         }
 261
 262         return 0;
 263 }
 264
 265 #define WIN_EN(id)              \
 266 static int win##id##_enable(struct vop_device *vop_dev, int en) \
 267 { \
 268         spin_lock(&vop_dev->reg_lock);                                  \
 269         vop_msk_reg(vop_dev, WIN##id##_CTRL0, V_WIN##id##_EN((u64)en)); \
 270         vop_cfg_done(vop_dev);                                          \
 271         spin_unlock(&vop_dev->reg_lock);                                \
 272         return 0;                                                       \
 273 }
 274
 275 WIN_EN(0);
 276 WIN_EN(1);
 277
 278 /*enable/disable win directly*/
 279 static int vop_win_direct_en(struct rk_lcdc_driver *drv,
 280                              int win_id, int en)
 281 {
 282         struct vop_device *vop_dev =
 283             container_of(drv, struct vop_device, driver);
 284         if (win_id == 0)
 285                 win0_enable(vop_dev, en);
 286         else if (win_id == 1)
 287                 win1_enable(vop_dev, en);
 288         else
 289                 dev_err(vop_dev->dev, "invalid win number:%d\n", win_id);
 290         return 0;
 291 }
 292
 293 #define SET_WIN_ADDR(id) \
 294 static int set_win##id##_addr(struct vop_device *vop_dev, u32 addr) \
 295 {                                                       \
 296         spin_lock(&vop_dev->reg_lock);                  \
 297         vop_writel(vop_dev, WIN##id##_YRGB_MST, addr);  \
 298         vop_msk_reg(vop_dev, WIN##id##_CTRL0, V_WIN##id##_EN(1));       \
 299         vop_cfg_done(vop_dev);                  \
 300         spin_unlock(&vop_dev->reg_lock);                \
 301         return 0;                                       \
 302 }
 303
 304 SET_WIN_ADDR(0);
 305 SET_WIN_ADDR(1);
 306 int vop_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
 307                             int win_id, u32 addr)
 308 {
 309         struct vop_device *vop_dev =
 310             container_of(dev_drv, struct vop_device, driver);
 311         if (win_id == 0)
 312                 set_win0_addr(vop_dev, addr);
 313         else
 314                 set_win1_addr(vop_dev, addr);
 315
 316         return 0;
 317 }
 318
 319 static void lcdc_read_reg_defalut_cfg(struct vop_device *vop_dev)
 320 {
 321         int reg = 0;
 322         u32 val = 0;
 323         struct rk_screen *screen = vop_dev->driver.cur_screen;
 324         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 325         u32 V_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 326         u32 st_x, st_y;
 327         struct rk_lcdc_win *win0 = vop_dev->driver.win[0];
 328
 329         spin_lock(&vop_dev->reg_lock);
 330         for (reg = 0; reg < vop_dev->len; reg += 4) {
 331                 val = vop_readl_backup(vop_dev, reg);
 332                 switch (reg) {
 333                 case WIN0_ACT_INFO:
 334                         win0->area[0].xact = (val & MASK(WIN0_ACT_WIDTH)) + 1;
 335                         win0->area[0].yact =
 336                                 ((val & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1;
 337                         break;
 338                 case WIN0_DSP_INFO:
 339                         win0->area[0].xsize = (val & MASK(WIN0_DSP_WIDTH)) + 1;
 340                         win0->area[0].ysize =
 341                             ((val & MASK(WIN0_DSP_HEIGHT)) >> 16) + 1;
 342                         break;
 343                 case WIN0_DSP_ST:
 344                         st_x = val & MASK(WIN0_DSP_XST);
 345                         st_y = (val & MASK(WIN0_DSP_YST)) >> 16;
 346                         win0->area[0].xpos = st_x - h_pw_bp;
 347                         win0->area[0].ypos = st_y - V_pw_bp;
 348                         break;
 349                 case WIN0_CTRL0:
 350                         win0->state = val & MASK(WIN0_EN);
 351                         win0->area[0].fmt_cfg =
 352                                         (val & MASK(WIN0_DATA_FMT)) >> 1;
 353                         win0->fmt_10 = (val & MASK(WIN0_FMT_10)) >> 4;
 354                         win0->area[0].format = win0->area[0].fmt_cfg;
 355                         break;
 356                 case WIN0_VIR:
 357                         win0->area[0].y_vir_stride =
 358                                         val & MASK(WIN0_VIR_STRIDE);
 359                         win0->area[0].uv_vir_stride =
 360                             (val & MASK(WIN0_VIR_STRIDE_UV)) >> 16;
 361                         if (win0->area[0].format == ARGB888)
 362                                 win0->area[0].xvir = win0->area[0].y_vir_stride;
 363                         else if (win0->area[0].format == RGB888)
 364                                 win0->area[0].xvir =
 365                                     win0->area[0].y_vir_stride * 4 / 3;
 366                         else if (win0->area[0].format == RGB565)
 367                                 win0->area[0].xvir =
 368                                     2 * win0->area[0].y_vir_stride;
 369                         else
 370                                 win0->area[0].xvir =
 371                                     4 * win0->area[0].y_vir_stride;
 372                         break;
 373                 case WIN0_YRGB_MST:
 374                         win0->area[0].smem_start = val;
 375                         break;
 376                 case WIN0_CBR_MST:
 377                         win0->area[0].cbr_start = val;
 378                         break;
 379                 default:
 380                         break;
 381                 }
 382         }
 383         spin_unlock(&vop_dev->reg_lock);
 384 }
 385
 386 /********do basic init*********/
 387 static int vop_pre_init(struct rk_lcdc_driver *dev_drv)
 388 {
 389         struct vop_device *vop_dev =
 390             container_of(dev_drv, struct vop_device, driver);
 391         if (vop_dev->pre_init)
 392                 return 0;
 393
 394         vop_dev->hclk = devm_clk_get(vop_dev->dev, "hclk_vop");
 395         vop_dev->aclk = devm_clk_get(vop_dev->dev, "aclk_vop");
 396         vop_dev->dclk = devm_clk_get(vop_dev->dev, "dclk_vop");
 397         vop_dev->hclk_noc = devm_clk_get(vop_dev->dev, "hclk_vop_noc");
 398         vop_dev->aclk_noc = devm_clk_get(vop_dev->dev, "aclk_vop_noc");
 399
 400         if (IS_ERR(vop_dev->aclk) || IS_ERR(vop_dev->dclk) ||
 401             IS_ERR(vop_dev->hclk) || IS_ERR(vop_dev->hclk_noc) ||
 402             IS_ERR(vop_dev->aclk_noc))
 403                 dev_err(vop_dev->dev, "failed to get clk source\n");
 404         if (!support_uboot_display())
 405                 rk_disp_pwr_enable(dev_drv);
 406         vop_clk_enable(vop_dev);
 407
 408         memcpy(vop_dev->regsbak, vop_dev->regs, vop_dev->len);
 409         /*backup reg config at uboot */
 410         lcdc_read_reg_defalut_cfg(vop_dev);
 411         #ifndef CONFIG_RK_FPGA
 412         /*
 413          * Todo, not verified
 414          *
 415         if (vop_dev->pwr18 == 1) {
 416                 v = 0x00200020;
 417                 vop_grf_writel(vop_dev->pmugrf_base,
 418                                 PMUGRF_SOC_CON0_VOP, v);
 419         } else {
 420                 v = 0x00200000;
 421                 vop_grf_writel(vop_dev->pmugrf_base,
 422                                 PMUGRF_SOC_CON0_VOP, v);
 423         }
 424         */
 425         #endif
 426         vop_writel(vop_dev, FRC_LOWER01_0, 0x12844821);
 427         vop_writel(vop_dev, FRC_LOWER01_1, 0x21488412);
 428         vop_writel(vop_dev, FRC_LOWER10_0, 0xa55a9696);
 429         vop_writel(vop_dev, FRC_LOWER10_1, 0x5aa56969);
 430         vop_writel(vop_dev, FRC_LOWER11_0, 0xdeb77deb);
 431         vop_writel(vop_dev, FRC_LOWER11_1, 0xed7bb7de);
 432
 433         vop_msk_reg(vop_dev, SYS_CTRL, V_AUTO_GATING_EN(0));
 434         vop_msk_reg(vop_dev, DSP_CTRL1, V_DITHER_UP_EN(1));
 435         vop_cfg_done(vop_dev);
 436         vop_dev->pre_init = true;
 437
 438         return 0;
 439 }
 440
 441 static void vop_deint(struct vop_device *vop_dev)
 442 {
 443         if (vop_dev->clk_on) {
 444                 vop_disable_irq(vop_dev);
 445                 spin_lock(&vop_dev->reg_lock);
 446                 vop_msk_reg(vop_dev, WIN0_CTRL0, V_WIN0_EN(0));
 447                 vop_msk_reg(vop_dev, WIN1_CTRL0, V_WIN0_EN(0));
 448
 449                 vop_cfg_done(vop_dev);
 450                 spin_unlock(&vop_dev->reg_lock);
 451                 mdelay(50);
 452         }
 453 }
 454
 455
 456 static void vop_win_csc_mode(struct vop_device *vop_dev,
 457                              struct rk_lcdc_win *win,
 458                              int csc_mode)
 459 {
 460         u64 val;
 461
 462         if (win->id == 0) {
 463                 val = V_WIN0_CSC_MODE(csc_mode);
 464                 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
 465         } else if (win->id == 1) {
 466                 val = V_WIN1_CSC_MODE(csc_mode);
 467                 vop_msk_reg(vop_dev, WIN1_CTRL0, val);
 468         } else {
 469                 val = V_HWC_CSC_MODE(csc_mode);
 470                 vop_msk_reg(vop_dev, HWC_CTRL0, val);
 471         }
 472 }
 473
 474 /*
 475  * colorspace path:
 476  *      Input        Win csc            Post csc              Output
 477  * 1. YUV(2020)  --> bypass   ---+ Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
 478  *    RGB        --> R2Y(709) __/
 479  *
 480  * 2. YUV(2020)  --> bypass   ---+       bypass        --> YUV_OUTPUT(2020)
 481  *    RGB        --> R2Y(709) __/
 482  *
 483  * 3. YUV(2020)  --> bypass   ---+    Y2R->2020To709   --> RGB_OUTPUT(709)
 484  *    RGB        --> R2Y(709) __/
 485  *
 486  * 4. YUV(601/709)-> bypass   ---+ Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
 487  *    RGB        --> R2Y(709) __/
 488  *
 489  * 5. YUV(601/709)-> bypass   ---+       bypass        --> YUV_OUTPUT(709)
 490  *    RGB        --> R2Y(709) __/
 491  *
 492  * 6. YUV(601/709)-> bypass   ---+       bypass        --> YUV_OUTPUT(601)
 493  *    RGB        --> R2Y(601) __/
 494  *
 495  * 7. YUV(601)   --> Y2R(601/mpeg)-+     bypass        --> RGB_OUTPUT(709)
 496  *    RGB        --> bypass   ____/
 497  *
 498  * 8. YUV(709)   --> Y2R(709/hd) --+     bypass        --> RGB_OUTPUT(709)
 499  *    RGB        --> bypass   ____/
 500  *
 501  * 9. RGB        --> bypass   --->    709To2020->R2Y   --> YUV_OUTPUT(2020)
 502  *
 503  * 10. RGB        --> R2Y(709) --->       Y2R          --> YUV_OUTPUT(709)
 504  *
 505  * 11. RGB       --> R2Y(601) --->       Y2R           --> YUV_OUTPUT(601)
 506  *
 507  * 12. RGB       --> bypass   --->       bypass        --> RGB_OUTPUT(709)
 508  */
 509
 510 static void vop_post_csc_cfg(struct rk_lcdc_driver *dev_drv)
 511 {
 512         struct vop_device *vop_dev =
 513             container_of(dev_drv, struct vop_device, driver);
 514         struct rk_lcdc_win *win;
 515         int output_color = dev_drv->output_color;
 516         int i, r2y_mode;
 517         int overlay_mode;
 518         int win_csc = COLOR_RGB;
 519         u64 val;
 520
 521         if (output_color == COLOR_RGB)
 522                 overlay_mode = VOP_RGB_DOMAIN;
 523         else
 524                 overlay_mode = VOP_YUV_DOMAIN;
 525
 526         if (output_color == COLOR_YCBCR)
 527                 r2y_mode = VOP_R2Y_CSC_BT601;
 528         else
 529                 r2y_mode = VOP_R2Y_CSC_BT709;
 530
 531         for (i = 0; i < dev_drv->lcdc_win_num; i++) {
 532                 win = dev_drv->win[i];
 533                 if (!win->state)
 534                         continue;
 535                 /*
 536                  * force use yuv domain when there is a windows's csc is bt2020.
 537                  */
 538                 if (win->colorspace == CSC_BT2020) {
 539                         overlay_mode = VOP_YUV_DOMAIN;
 540                         r2y_mode = VOP_R2Y_CSC_BT709;
 541                         win_csc = COLOR_YCBCR_BT2020;
 542                         break;
 543                 }
 544                 if (IS_YUV(win->area[0].fmt_cfg))
 545                         win_csc = COLOR_YCBCR;
 546         }
 547
 548         for (i = 0; i < dev_drv->lcdc_win_num; i++) {
 549                 win = dev_drv->win[i];
 550                 if (!win->state)
 551                         continue;
 552                 if (overlay_mode == VOP_YUV_DOMAIN &&
 553                     !IS_YUV(win->area[0].fmt_cfg))
 554                         vop_win_csc_mode(vop_dev, win, r2y_mode);
 555                 if (overlay_mode == VOP_RGB_DOMAIN &&
 556                     IS_YUV(win->area[0].fmt_cfg)) {
 557                         if (win->colorspace == CSC_BT709)
 558                                 vop_win_csc_mode(vop_dev, win, VOP_Y2R_CSC_HD);
 559                         else if (win->colorspace == CSC_BT601)
 560                                 vop_win_csc_mode(vop_dev, win,
 561                                                  VOP_Y2R_CSC_MPEG);
 562                         else
 563                                 pr_err("Error Y2R path, colorspace=%d\n",
 564                                        win->colorspace);
 565                 }
 566         }
 567
 568         if (win_csc == COLOR_RGB && overlay_mode == VOP_YUV_DOMAIN)
 569                 win_csc = COLOR_YCBCR;
 570         else if (IS_YUV_COLOR(win_csc) && overlay_mode == VOP_RGB_DOMAIN)
 571                 win_csc = COLOR_RGB;
 572
 573         val = V_YUV2YUV_POST_Y2R_EN(0) | V_YUV2YUV_POST_EN(0) |
 574                 V_YUV2YUV_POST_R2Y_EN(0);
 575         /* Y2R */
 576         if (win_csc == COLOR_YCBCR && output_color == COLOR_YCBCR_BT2020) {
 577                 win_csc = COLOR_RGB;
 578                 val |= V_YUV2YUV_POST_Y2R_EN(1);
 579                 vop_load_csc_table(vop_dev, POST_YUV2YUV_Y2R_COE,
 580                                    csc_y2r_bt709_full);
 581         }
 582         if (win_csc == COLOR_YCBCR_BT2020 &&
 583             output_color != COLOR_YCBCR_BT2020) {
 584                 win_csc = COLOR_RGB_BT2020;
 585                 val |= V_YUV2YUV_POST_Y2R_EN(1);
 586                 vop_load_csc_table(vop_dev, POST_YUV2YUV_Y2R_COE,
 587                                    csc_y2r_bt2020);
 588         }
 589
 590         /* R2R */
 591         if (win_csc == COLOR_RGB && output_color == COLOR_YCBCR_BT2020) {
 592                 win_csc = COLOR_RGB_BT2020;
 593                 val |= V_YUV2YUV_POST_EN(1);
 594                 vop_load_csc_table(vop_dev, POST_YUV2YUV_3x3_COE,
 595                                    csc_r2r_bt709to2020);
 596         }
 597         if (win_csc == COLOR_RGB_BT2020 &&
 598             (output_color == COLOR_YCBCR ||
 599              output_color == COLOR_YCBCR_BT709 ||
 600              output_color == COLOR_RGB)) {
 601                 win_csc = COLOR_RGB;
 602                 val |= V_YUV2YUV_POST_EN(1);
 603                 vop_load_csc_table(vop_dev, POST_YUV2YUV_3x3_COE,
 604                                    csc_r2r_bt2020to709);
 605         }
 606
 607         /* R2Y */
 608         if (!IS_YUV_COLOR(win_csc) && IS_YUV_COLOR(output_color)) {
 609                 val |= V_YUV2YUV_POST_R2Y_EN(1);
 610
 611                 if (output_color == COLOR_YCBCR_BT2020)
 612                         vop_load_csc_table(vop_dev, POST_YUV2YUV_R2Y_COE,
 613                                            csc_r2y_bt2020);
 614                 else
 615                         vop_load_csc_table(vop_dev, POST_YUV2YUV_R2Y_COE,
 616                                            csc_r2y_bt709_full);
 617         }
 618
 619         DBG(1, "win_csc=%d output_color=%d val=%llx overlay_mode=%d\n",
 620             win_csc, output_color, val, overlay_mode);
 621         vop_msk_reg(vop_dev, SYS_CTRL, V_OVERLAY_MODE(overlay_mode));
 622         vop_msk_reg(vop_dev, YUV2YUV_POST, val);
 623 }
 624
 625 static int vop_post_cfg(struct rk_lcdc_driver *dev_drv)
 626 {
 627         struct vop_device *vop_dev =
 628             container_of(dev_drv, struct vop_device, driver);
 629         struct rk_screen *screen = dev_drv->cur_screen;
 630         u16 x_res = screen->mode.xres;
 631         u16 y_res = screen->mode.yres;
 632         u64 val;
 633         u16 h_total, v_total;
 634         u16 post_hsd_en, post_vsd_en;
 635         u16 post_dsp_hact_st, post_dsp_hact_end;
 636         u16 post_dsp_vact_st, post_dsp_vact_end;
 637         u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
 638         u16 post_h_fac, post_v_fac;
 639
 640         screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200;
 641         screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200;
 642         screen->post_xsize = x_res *
 643             (dev_drv->overscan.left + dev_drv->overscan.right) / 200;
 644         screen->post_ysize = y_res *
 645             (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200;
 646
 647         h_total = screen->mode.hsync_len + screen->mode.left_margin +
 648             x_res + screen->mode.right_margin;
 649         v_total = screen->mode.vsync_len + screen->mode.upper_margin +
 650             y_res + screen->mode.lower_margin;
 651
 652         if (screen->post_dsp_stx + screen->post_xsize > x_res) {
 653                 dev_warn(vop_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
 654                          screen->post_dsp_stx, screen->post_xsize, x_res);
 655                 screen->post_dsp_stx = x_res - screen->post_xsize;
 656         }
 657         if (screen->x_mirror == 0) {
 658                 post_dsp_hact_st = screen->post_dsp_stx +
 659                     screen->mode.hsync_len + screen->mode.left_margin;
 660                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 661         } else {
 662                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 663                     screen->post_dsp_stx;
 664                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 665         }
 666         if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
 667                 post_hsd_en = 1;
 668                 post_h_fac =
 669                     GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
 670         } else {
 671                 post_hsd_en = 0;
 672                 post_h_fac = 0x1000;
 673         }
 674
 675         if (screen->post_dsp_sty + screen->post_ysize > y_res) {
 676                 dev_warn(vop_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
 677                          screen->post_dsp_sty, screen->post_ysize, y_res);
 678                 screen->post_dsp_sty = y_res - screen->post_ysize;
 679         }
 680
 681         if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
 682                 post_vsd_en = 1;
 683                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
 684                                                       screen->post_ysize);
 685         } else {
 686                 post_vsd_en = 0;
 687                 post_v_fac = 0x1000;
 688         }
 689
 690         if (screen->mode.vmode & FB_VMODE_INTERLACED) {
 691                 post_dsp_vact_st = screen->post_dsp_sty / 2 +
 692                                         screen->mode.vsync_len +
 693                                         screen->mode.upper_margin;
 694                 post_dsp_vact_end = post_dsp_vact_st +
 695                                         screen->post_ysize / 2;
 696
 697                 post_dsp_vact_st_f1 = screen->mode.vsync_len +
 698                                         screen->mode.upper_margin +
 699                                         y_res / 2 +
 700                                         screen->mode.lower_margin +
 701                                         screen->mode.vsync_len +
 702                                         screen->mode.upper_margin +
 703                                         screen->post_dsp_sty / 2 +
 704                                         1;
 705                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
 706                                         screen->post_ysize/2;
 707         } else {
 708                 if (screen->y_mirror == 0) {
 709                         post_dsp_vact_st = screen->post_dsp_sty +
 710                             screen->mode.vsync_len +
 711                             screen->mode.upper_margin;
 712                         post_dsp_vact_end = post_dsp_vact_st +
 713                                 screen->post_ysize;
 714                 } else {
 715                         post_dsp_vact_end = v_total -
 716                                 screen->mode.lower_margin -
 717                             screen->post_dsp_sty;
 718                         post_dsp_vact_st = post_dsp_vact_end -
 719                                 screen->post_ysize;
 720                 }
 721                 post_dsp_vact_st_f1 = 0;
 722                 post_dsp_vact_end_f1 = 0;
 723         }
 724         DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
 725             screen->post_xsize, screen->post_ysize, screen->xpos);
 726         DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 727             screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
 728         val = V_DSP_HACT_END_POST(post_dsp_hact_end) |
 729             V_DSP_HACT_ST_POST(post_dsp_hact_st);
 730         vop_msk_reg(vop_dev, POST_DSP_HACT_INFO, val);
 731
 732         val = V_DSP_VACT_END_POST(post_dsp_vact_end) |
 733             V_DSP_VACT_ST_POST(post_dsp_vact_st);
 734         vop_msk_reg(vop_dev, POST_DSP_VACT_INFO, val);
 735
 736         val = V_POST_HS_FACTOR_YRGB(post_h_fac) |
 737             V_POST_VS_FACTOR_YRGB(post_v_fac);
 738         vop_msk_reg(vop_dev, POST_SCL_FACTOR_YRGB, val);
 739         val = V_DSP_VACT_END_POST(post_dsp_vact_end_f1) |
 740             V_DSP_VACT_ST_POST(post_dsp_vact_st_f1);
 741         vop_msk_reg(vop_dev, POST_DSP_VACT_INFO_F1, val);
 742         val = V_POST_HOR_SD_EN(post_hsd_en) | V_POST_VER_SD_EN(post_vsd_en);
 743         vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
 744
 745         vop_post_csc_cfg(dev_drv);
 746
 747         return 0;
 748 }
 749
 750 static int vop_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 751 {
 752         struct vop_device *vop_dev =
 753             container_of(dev_drv, struct vop_device, driver);
 754         struct rk_lcdc_win *win;
 755         u32 colorkey_r, colorkey_g, colorkey_b;
 756         int i, key_val;
 757
 758         for (i = 0; i < dev_drv->lcdc_win_num; i++) {
 759                 win = dev_drv->win[i];
 760                 key_val = win->color_key_val;
 761                 colorkey_r = (key_val & 0xff) << 2;
 762                 colorkey_g = ((key_val >> 8) & 0xff) << 12;
 763                 colorkey_b = ((key_val >> 16) & 0xff) << 22;
 764                 /* color key dither 565/888->aaa */
 765                 key_val = colorkey_r | colorkey_g | colorkey_b;
 766                 switch (i) {
 767                 case 0:
 768                         vop_writel(vop_dev, WIN0_COLOR_KEY, key_val);
 769                         break;
 770                 case 1:
 771                         vop_writel(vop_dev, WIN1_COLOR_KEY, key_val);
 772                         break;
 773                 default:
 774                         pr_info("%s:un support win num:%d\n",
 775                                 __func__, i);
 776                         break;
 777                 }
 778         }
 779         return 0;
 780 }
 781
 782 static int vop_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
 783 {
 784         struct vop_device *vop_dev =
 785             container_of(dev_drv, struct vop_device, driver);
 786         struct rk_lcdc_win *win = dev_drv->win[win_id];
 787         struct alpha_config alpha_config;
 788         u64 val;
 789         int ppixel_alpha = 0, global_alpha = 0, i;
 790         u32 src_alpha_ctl, dst_alpha_ctl;
 791         int alpha_en = 1;
 792
 793         for (i = 0; i < win->area_num; i++) {
 794                 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
 795                                  (win->area[i].format == FBDC_ARGB_888) ||
 796                                  (win->area[i].format == FBDC_ABGR_888) ||
 797                                  (win->area[i].format == ABGR888)) ? 1 : 0;
 798         }
 799
 800         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 801
 802         for (i = 0; i < dev_drv->lcdc_win_num; i++) {
 803                 if (!dev_drv->win[i]->state)
 804                         continue;
 805                 if (win->z_order > dev_drv->win[i]->z_order)
 806                         break;
 807         }
 808
 809         /*
 810          * The bottom layer not support ppixel_alpha mode.
 811          */
 812         if (i == dev_drv->lcdc_win_num)
 813                 ppixel_alpha = 0;
 814         alpha_config.src_global_alpha_val = win->g_alpha_val;
 815         win->alpha_mode = AB_SRC_OVER;
 816
 817         switch (win->alpha_mode) {
 818         case AB_USER_DEFINE:
 819                 break;
 820         case AB_CLEAR:
 821                 alpha_config.src_factor_mode = AA_ZERO;
 822                 alpha_config.dst_factor_mode = AA_ZERO;
 823                 break;
 824         case AB_SRC:
 825                 alpha_config.src_factor_mode = AA_ONE;
 826                 alpha_config.dst_factor_mode = AA_ZERO;
 827                 break;
 828         case AB_DST:
 829                 alpha_config.src_factor_mode = AA_ZERO;
 830                 alpha_config.dst_factor_mode = AA_ONE;
 831                 break;
 832         case AB_SRC_OVER:
 833                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 834                 if (global_alpha)
 835                         alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 836                 else
 837                         alpha_config.src_factor_mode = AA_ONE;
 838                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 839                 break;
 840         case AB_DST_OVER:
 841                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 842                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 843                 alpha_config.dst_factor_mode = AA_ONE;
 844                 break;
 845         case AB_SRC_IN:
 846                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 847                 alpha_config.src_factor_mode = AA_SRC;
 848                 alpha_config.dst_factor_mode = AA_ZERO;
 849                 break;
 850         case AB_DST_IN:
 851                 alpha_config.src_factor_mode = AA_ZERO;
 852                 alpha_config.dst_factor_mode = AA_SRC;
 853                 break;
 854         case AB_SRC_OUT:
 855                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 856                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 857                 alpha_config.dst_factor_mode = AA_ZERO;
 858                 break;
 859         case AB_DST_OUT:
 860                 alpha_config.src_factor_mode = AA_ZERO;
 861                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 862                 break;
 863         case AB_SRC_ATOP:
 864                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 865                 alpha_config.src_factor_mode = AA_SRC;
 866                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 867                 break;
 868         case AB_DST_ATOP:
 869                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 870                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 871                 alpha_config.dst_factor_mode = AA_SRC;
 872                 break;
 873         case XOR:
 874                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 875                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 876                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 877                 break;
 878         case AB_SRC_OVER_GLOBAL:
 879                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 880                 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
 881                 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 882                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 883                 break;
 884         default:
 885                 pr_err("alpha mode error\n");
 886                 break;
 887         }
 888         if ((ppixel_alpha == 1) && (global_alpha == 1))
 889                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 890         else if (ppixel_alpha == 1)
 891                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 892         else if (global_alpha == 1)
 893                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 894         else
 895                 alpha_en = 0;
 896         alpha_config.src_alpha_mode = AA_STRAIGHT;
 897         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 898
 899         switch (win_id) {
 900         case 0:
 901                 src_alpha_ctl = 0x60;
 902                 dst_alpha_ctl = 0x64;
 903                 break;
 904         case 1:
 905                 src_alpha_ctl = 0xa0;
 906                 dst_alpha_ctl = 0xa4;
 907                 break;
 908         case 2:
 909                 src_alpha_ctl = 0x160;
 910                 dst_alpha_ctl = 0x164;
 911                 break;
 912         }
 913         val = V_WIN0_DST_FACTOR_MODE(alpha_config.dst_factor_mode);
 914         vop_msk_reg(vop_dev, dst_alpha_ctl, val);
 915         val = V_WIN0_SRC_ALPHA_EN(alpha_en) |
 916             V_WIN0_SRC_COLOR_MODE(alpha_config.src_color_mode) |
 917             V_WIN0_SRC_ALPHA_MODE(alpha_config.src_alpha_mode) |
 918             V_WIN0_SRC_BLEND_MODE(alpha_config.src_global_alpha_mode) |
 919             V_WIN0_SRC_ALPHA_CAL_MODE(alpha_config.src_alpha_cal_m0) |
 920             V_WIN0_SRC_FACTOR_MODE(alpha_config.src_factor_mode) |
 921             V_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 922
 923         vop_msk_reg(vop_dev, src_alpha_ctl, val);
 924
 925         return 0;
 926 }
 927
 928 static int vop_axi_gather_cfg(struct vop_device *vop_dev,
 929                               struct rk_lcdc_win *win)
 930 {
 931         u64 val;
 932         u16 yrgb_gather_num = 3;
 933         u16 cbcr_gather_num = 1;
 934
 935         switch (win->area[0].format) {
 936         case ARGB888:
 937         case XBGR888:
 938         case ABGR888:
 939                 yrgb_gather_num = 3;
 940                 break;
 941         case RGB888:
 942         case RGB565:
 943                 yrgb_gather_num = 2;
 944                 break;
 945         case YUV444:
 946         case YUV422:
 947         case YUV420:
 948         case YUV420_A:
 949         case YUV422_A:
 950         case YUV444_A:
 951         case YUV420_NV21:
 952                 yrgb_gather_num = 1;
 953                 cbcr_gather_num = 2;
 954                 break;
 955         default:
 956                 dev_err(vop_dev->driver.dev, "%s:un supported format[%d]\n",
 957                         __func__, win->area[0].format);
 958                 return -EINVAL;
 959         }
 960
 961         if ((win->id == 0) || (win->id == 1)) {
 962                 val = V_WIN0_YRGB_AXI_GATHER_EN(1) |
 963                         V_WIN0_CBR_AXI_GATHER_EN(1) |
 964                         V_WIN0_YRGB_AXI_GATHER_NUM(yrgb_gather_num) |
 965                         V_WIN0_CBR_AXI_GATHER_NUM(cbcr_gather_num);
 966                 vop_msk_reg(vop_dev, WIN0_CTRL1 + (win->id * 0x40), val);
 967         } else if (win->id == 2) {
 968                 val = V_HWC_AXI_GATHER_EN(1) |
 969                         V_HWC_AXI_GATHER_NUM(yrgb_gather_num);
 970                 vop_msk_reg(vop_dev, HWC_CTRL1, val);
 971         }
 972         return 0;
 973 }
 974
 975 static int vop_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
 976 {
 977         struct vop_device *vop_dev =
 978             container_of(dev_drv, struct vop_device, driver);
 979         struct rk_lcdc_win *win = dev_drv->win[win_id];
 980         u64 val;
 981         uint32_t off;
 982         int format;
 983
 984         off = win_id * 0x40;
 985
 986         if (win->state == 1) {
 987                 vop_axi_gather_cfg(vop_dev, win);
 988
 989                 /*
 990                  * rk322x have a bug on windows 0 and 1:
 991                  *
 992                  * When switch win format from RGB to YUV, would flash
 993                  * some green lines on the top of the windows.
 994                  *
 995                  * Use bg_en show one blank frame to skip the error frame.
 996                  */
 997                 if (IS_YUV(win->area[0].fmt_cfg)) {
 998                         val = vop_readl(vop_dev, WIN0_CTRL0);
 999                         format = (val & MASK(WIN0_DATA_FMT)) >> 1;
1000
1001                         if (!IS_YUV(format)) {
1002                                 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1003                                         val = V_WIN0_DSP_BG_RED(0x200) |
1004                                                 V_WIN0_DSP_BG_GREEN(0x40) |
1005                                                 V_WIN0_DSP_BG_BLUE(0x200) |
1006                                                 V_WIN0_BG_EN(1);
1007                                         vop_msk_reg(vop_dev, WIN0_DSP_BG + off,
1008                                                     val);
1009                                 } else {
1010                                         val = V_WIN0_DSP_BG_RED(0) |
1011                                                 V_WIN0_DSP_BG_GREEN(0) |
1012                                                 V_WIN0_DSP_BG_BLUE(0) |
1013                                                 V_WIN0_BG_EN(1);
1014                                         vop_msk_reg(vop_dev, WIN0_DSP_BG + off,
1015                                                     val);
1016                                 }
1017                         } else {
1018                                 val = V_WIN0_BG_EN(0);
1019                                 vop_msk_reg(vop_dev, WIN0_DSP_BG + off, val);
1020                         }
1021                 } else {
1022                         val = V_WIN0_BG_EN(0);
1023                         vop_msk_reg(vop_dev, WIN0_DSP_BG + off, val);
1024                 }
1025
1026                 val = V_WIN0_EN(win->state) |
1027                         V_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1028                         V_WIN0_FMT_10(win->fmt_10) |
1029                         V_WIN0_LB_MODE(win->win_lb_mode) |
1030                         V_WIN0_RB_SWAP(win->area[0].swap_rb) |
1031                         V_WIN0_X_MIR_EN(win->xmirror) |
1032                         V_WIN0_Y_MIR_EN(win->ymirror) |
1033                         V_WIN0_UV_SWAP(win->area[0].swap_uv);
1034                 vop_msk_reg(vop_dev, WIN0_CTRL0 + off, val);
1035                 val = V_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1036                     V_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1037                     V_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1038                     V_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1039                     V_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1040                     V_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1041                     V_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1042                     V_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1043                     V_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1044                     V_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1045                     V_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1046                     V_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1047                     V_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1048                     V_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1049                     V_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1050                 vop_msk_reg(vop_dev, WIN0_CTRL1 + off, val);
1051                 val = V_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1052                     V_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1053                 vop_writel(vop_dev, WIN0_VIR + off, val);
1054                 val = V_WIN0_ACT_WIDTH(win->area[0].xact - 1) |
1055                     V_WIN0_ACT_HEIGHT(win->area[0].yact - 1);
1056                 vop_writel(vop_dev, WIN0_ACT_INFO + off, val);
1057
1058                 val = V_WIN0_DSP_WIDTH(win->area[0].xsize - 1) |
1059                     V_WIN0_DSP_HEIGHT(win->area[0].ysize - 1);
1060                 vop_writel(vop_dev, WIN0_DSP_INFO + off, val);
1061
1062                 val = V_WIN0_DSP_XST(win->area[0].dsp_stx) |
1063                     V_WIN0_DSP_YST(win->area[0].dsp_sty);
1064                 vop_writel(vop_dev, WIN0_DSP_ST + off, val);
1065
1066                 val = V_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1067                     V_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1068                 vop_writel(vop_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1069
1070                 val = V_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1071                     V_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1072                 vop_writel(vop_dev, WIN0_SCL_FACTOR_CBR + off, val);
1073                 if (win->alpha_en == 1) {
1074                         vop_alpha_cfg(dev_drv, win_id);
1075                 } else {
1076                         val = V_WIN0_SRC_ALPHA_EN(0);
1077                         vop_msk_reg(vop_dev, WIN0_SRC_ALPHA_CTRL + off, val);
1078                 }
1079
1080         } else {
1081                 val = V_WIN0_EN(win->state);
1082                 vop_msk_reg(vop_dev, WIN0_CTRL0 + off, val);
1083         }
1084
1085         return 0;
1086 }
1087
1088 static int vop_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1089 {
1090         struct vop_device *vop_dev =
1091             container_of(dev_drv, struct vop_device, driver);
1092         struct rk_lcdc_win *win = dev_drv->win[win_id];
1093         unsigned int hwc_size = 0;
1094         u64 val;
1095
1096         if (win->state == 1) {
1097                 vop_axi_gather_cfg(vop_dev, win);
1098                 val = V_HWC_EN(1) | V_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1099                     V_HWC_RB_SWAP(win->area[0].swap_rb);
1100                 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1101
1102                 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1103                         hwc_size = 0;
1104                 else if ((win->area[0].xsize == 64) &&
1105                          (win->area[0].ysize == 64))
1106                         hwc_size = 1;
1107                 else if ((win->area[0].xsize == 96) &&
1108                          (win->area[0].ysize == 96))
1109                         hwc_size = 2;
1110                 else if ((win->area[0].xsize == 128) &&
1111                          (win->area[0].ysize == 128))
1112                         hwc_size = 3;
1113                 else
1114                         dev_err(vop_dev->dev, "un supported hwc size[%dx%d]!\n",
1115                                 win->area[0].xsize, win->area[0].ysize);
1116
1117                 val = V_HWC_SIZE(hwc_size);
1118                 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1119
1120                 val = V_HWC_DSP_XST(win->area[0].dsp_stx) |
1121                     V_HWC_DSP_YST(win->area[0].dsp_sty);
1122                 vop_msk_reg(vop_dev, HWC_DSP_ST, val);
1123
1124                 if (win->alpha_en == 1) {
1125                         vop_alpha_cfg(dev_drv, win_id);
1126                 } else {
1127                         val = V_WIN2_SRC_ALPHA_EN(0);
1128                         vop_msk_reg(vop_dev, HWC_SRC_ALPHA_CTRL, val);
1129                 }
1130         } else {
1131                 val = V_HWC_EN(win->state);
1132                 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1133         }
1134
1135         return 0;
1136 }
1137
1138 static int vop_layer_update_regs(struct vop_device *vop_dev,
1139                                  struct rk_lcdc_win *win)
1140 {
1141         struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
1142
1143         if (likely(vop_dev->clk_on)) {
1144                 vop_msk_reg(vop_dev, SYS_CTRL,
1145                             V_VOP_STANDBY_EN(vop_dev->standby));
1146                 if ((win->id == 0) || (win->id == 1))
1147                         vop_win_0_1_reg_update(dev_drv, win->id);
1148                 else if (win->id == 2)
1149                         vop_hwc_reg_update(dev_drv, win->id);
1150                 vop_cfg_done(vop_dev);
1151         }
1152
1153         DBG(2, "%s for lcdc%d\n", __func__, vop_dev->id);
1154         return 0;
1155 }
1156
1157 static int __maybe_unused vop_mmu_en(struct rk_lcdc_driver *dev_drv)
1158 {
1159         u64 val;
1160         struct vop_device *vop_dev =
1161             container_of(dev_drv, struct vop_device, driver);
1162
1163         if (unlikely(!vop_dev->clk_on)) {
1164                 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
1165                 return 0;
1166         }
1167 #if defined(CONFIG_ROCKCHIP_IOMMU)
1168         if (dev_drv->iommu_enabled) {
1169                 if (!vop_dev->iommu_status && dev_drv->mmu_dev) {
1170                         if (likely(vop_dev->clk_on)) {
1171                                 val = V_VOP_MMU_EN(1);
1172                                 vop_msk_reg(vop_dev, SYS_CTRL, val);
1173                                 val = V_AXI_OUTSTANDING_MAX_NUM(31) |
1174                                         V_AXI_MAX_OUTSTANDING_EN(1);
1175                                 vop_msk_reg(vop_dev, SYS_CTRL1, val);
1176                         }
1177                         vop_dev->iommu_status = 1;
1178                         rockchip_iovmm_activate(dev_drv->dev);
1179                 }
1180         }
1181 #endif
1182         return 0;
1183 }
1184
1185 static int vop_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate)
1186 {
1187         int ret = 0, fps = 0;
1188         struct vop_device *vop_dev =
1189             container_of(dev_drv, struct vop_device, driver);
1190         struct rk_screen *screen = dev_drv->cur_screen;
1191 #ifdef CONFIG_RK_FPGA
1192         return 0;
1193 #endif
1194         if (reset_rate)
1195                 ret = clk_set_rate(vop_dev->dclk, screen->mode.pixclock);
1196         if (ret)
1197                 dev_err(dev_drv->dev, "set lcdc%d dclk[%d] failed\n",
1198                         vop_dev->id, screen->mode.pixclock);
1199         vop_dev->pixclock =
1200             div_u64(1000000000000llu, clk_get_rate(vop_dev->dclk));
1201         vop_dev->driver.pixclock = vop_dev->pixclock;
1202
1203         fps = rk_fb_calc_fps(screen, vop_dev->pixclock);
1204         screen->ft = 1000 / fps;
1205         dev_info(vop_dev->dev, "%s: dclk:%lu>>fps:%d ",
1206                  vop_dev->driver.name, clk_get_rate(vop_dev->dclk), fps);
1207         return 0;
1208 }
1209
1210 static int vop_config_timing(struct rk_lcdc_driver *dev_drv)
1211 {
1212         struct vop_device *vop_dev =
1213             container_of(dev_drv, struct vop_device, driver);
1214         struct rk_screen *screen = dev_drv->cur_screen;
1215         u16 hsync_len = screen->mode.hsync_len;
1216         u16 left_margin = screen->mode.left_margin;
1217         u16 right_margin = screen->mode.right_margin;
1218         u16 vsync_len = screen->mode.vsync_len;
1219         u16 upper_margin = screen->mode.upper_margin;
1220         u16 lower_margin = screen->mode.lower_margin;
1221         u16 x_res = screen->mode.xres;
1222         u16 y_res = screen->mode.yres;
1223         u64 val;
1224         u16 h_total, v_total;
1225         u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1226
1227         h_total = hsync_len + left_margin + x_res + right_margin;
1228         v_total = vsync_len + upper_margin + y_res + lower_margin;
1229
1230         val = V_DSP_HS_END(hsync_len) | V_DSP_HTOTAL(h_total);
1231         vop_msk_reg(vop_dev, DSP_HTOTAL_HS_END, val);
1232
1233         val = V_DSP_HACT_END(hsync_len + left_margin + x_res) |
1234             V_DSP_HACT_ST(hsync_len + left_margin);
1235         vop_msk_reg(vop_dev, DSP_HACT_ST_END, val);
1236
1237         if (screen->mode.vmode & FB_VMODE_INTERLACED) {
1238                 /* First Field Timing */
1239                 val = V_DSP_VS_END(vsync_len) |
1240                     V_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1241                                       lower_margin) + y_res + 1);
1242                 vop_msk_reg(vop_dev, DSP_VTOTAL_VS_END, val);
1243
1244                 val = V_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1245                     V_DSP_VACT_ST(vsync_len + upper_margin);
1246                 vop_msk_reg(vop_dev, DSP_VACT_ST_END, val);
1247
1248                 /* Second Field Timing */
1249                 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1250                 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1251                     lower_margin;
1252                 val = V_DSP_VS_ST_F1(vs_st_f1) | V_DSP_VS_END_F1(vs_end_f1);
1253                 vop_msk_reg(vop_dev, DSP_VS_ST_END_F1, val);
1254
1255                 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1256                     lower_margin + 1;
1257                 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1258                     lower_margin + 1;
1259                 val = V_DSP_VACT_END_F1(vact_end_f1) |
1260                         V_DSP_VACT_ST_F1(vact_st_f1);
1261                 vop_msk_reg(vop_dev, DSP_VACT_ST_END_F1, val);
1262                 vop_msk_reg(vop_dev, DSP_CTRL0,
1263                             V_DSP_INTERLACE(1) | V_DSP_FIELD_POL(0));
1264
1265                 val = V_DSP_LINE_FLAG_NUM_0(lower_margin ?
1266                                             vact_end_f1 : vact_end_f1 - 1);
1267
1268                 val |= V_DSP_LINE_FLAG_NUM_1(lower_margin ?
1269                                              vact_end_f1 : vact_end_f1 - 1);
1270                 vop_msk_reg(vop_dev, LINE_FLAG, val);
1271         } else {
1272                 val = V_DSP_VS_END(vsync_len) | V_DSP_VTOTAL(v_total);
1273                 vop_msk_reg(vop_dev, DSP_VTOTAL_VS_END, val);
1274
1275                 val = V_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1276                     V_DSP_VACT_ST(vsync_len + upper_margin);
1277                 vop_msk_reg(vop_dev, DSP_VACT_ST_END, val);
1278
1279                 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_INTERLACE(0) |
1280                             V_DSP_FIELD_POL(0));
1281
1282                 val = V_DSP_LINE_FLAG_NUM_0(vsync_len + upper_margin + y_res) |
1283                         V_DSP_LINE_FLAG_NUM_1(vsync_len + upper_margin + y_res);
1284                 vop_msk_reg(vop_dev, LINE_FLAG, val);
1285         }
1286         vop_post_cfg(dev_drv);
1287
1288         return 0;
1289 }
1290
1291 static void vop_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1292 {
1293         struct vop_device *vop_dev =
1294             container_of(dev_drv, struct vop_device, driver);
1295         u32 bcsh_ctrl;
1296
1297         vop_msk_reg(vop_dev, SYS_CTRL, V_OVERLAY_MODE(dev_drv->overlay_mode));
1298         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1299                 if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1300                         vop_msk_reg(vop_dev, BCSH_CTRL,
1301                                     V_BCSH_Y2R_EN(0) | V_BCSH_R2Y_EN(0));
1302                 else            /* YUV2RGB */
1303                         vop_msk_reg(vop_dev, BCSH_CTRL, V_BCSH_Y2R_EN(1) |
1304                                     V_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1305                                     V_BCSH_R2Y_EN(0));
1306         } else {
1307                 /* overlay_mode=VOP_RGB_DOMAIN */
1308                 /* bypass  --need check,if bcsh close? */
1309                 if (dev_drv->output_color == COLOR_RGB) {
1310                         bcsh_ctrl = vop_readl(vop_dev, BCSH_CTRL);
1311                         if (((bcsh_ctrl & MASK(BCSH_EN)) == 1) ||
1312                             (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1313                                 vop_msk_reg(vop_dev, BCSH_CTRL,
1314                                             V_BCSH_R2Y_EN(1) |
1315                                             V_BCSH_Y2R_EN(1));
1316                         else
1317                                 vop_msk_reg(vop_dev, BCSH_CTRL,
1318                                             V_BCSH_R2Y_EN(0) |
1319                                             V_BCSH_Y2R_EN(0));
1320                 } else {
1321                         /* RGB2YUV */
1322                         vop_msk_reg(vop_dev, BCSH_CTRL,
1323                                     V_BCSH_R2Y_EN(1) |
1324                                     V_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1325                                     V_BCSH_Y2R_EN(0));
1326                 }
1327         }
1328 }
1329
1330 static int vop_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1331                                u16 *yact, int *format, u32 *dsp_addr,
1332                                int *ymirror)
1333 {
1334         struct vop_device *vop_dev =
1335                         container_of(dev_drv, struct vop_device, driver);
1336         u32 val;
1337
1338         spin_lock(&vop_dev->reg_lock);
1339
1340         val = vop_readl(vop_dev, WIN0_ACT_INFO);
1341         *xact = (val & MASK(WIN0_ACT_WIDTH)) + 1;
1342         *yact = ((val & MASK(WIN0_ACT_HEIGHT))>>16) + 1;
1343
1344         val = vop_readl(vop_dev, WIN0_CTRL0);
1345         *format = (val & MASK(WIN0_DATA_FMT)) >> 1;
1346         *ymirror = (val & MASK(WIN0_Y_MIR_EN)) >> 22;
1347         *dsp_addr = vop_readl(vop_dev, WIN0_YRGB_MST);
1348
1349         spin_unlock(&vop_dev->reg_lock);
1350
1351         return 0;
1352 }
1353
1354 static int vop_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1355                            int format, u16 xact, u16 yact, u16 xvir,
1356                            int ymirror)
1357 {
1358         struct vop_device *vop_dev =
1359                         container_of(dev_drv, struct vop_device, driver);
1360         int swap = (format == RGB888) ? 1 : 0;
1361         struct rk_lcdc_win *win = dev_drv->win[0];
1362         u64 val;
1363
1364         val = V_WIN0_DATA_FMT(format) | V_WIN0_RB_SWAP(swap) |
1365                 V_WIN0_Y_MIR_EN(ymirror);
1366         vop_msk_reg(vop_dev, WIN0_CTRL0, val);
1367
1368         vop_msk_reg(vop_dev, WIN0_VIR,  V_WIN0_VIR_STRIDE(xvir));
1369         vop_writel(vop_dev, WIN0_ACT_INFO, V_WIN0_ACT_WIDTH(xact - 1) |
1370                    V_WIN0_ACT_HEIGHT(yact - 1));
1371
1372         vop_writel(vop_dev, WIN0_YRGB_MST, rgb_mst);
1373
1374         vop_cfg_done(vop_dev);
1375
1376         if (format == RGB888)
1377                 win->area[0].format = BGR888;
1378         else
1379                 win->area[0].format = format;
1380
1381         win->ymirror = ymirror;
1382         win->state = 1;
1383         win->last_state = 1;
1384
1385         return 0;
1386 }
1387
1388 /*
1389 static int lcdc_reset(struct rk_lcdc_driver *dev_drv, bool initscreen)
1390 {
1391         struct vop_device *vop_dev =
1392             container_of(dev_drv, struct vop_device, driver);
1393         u64 val;
1394         u32 __maybe_unused v;
1395
1396         if (!vop_dev->standby && initscreen && (dev_drv->first_frame != 1)) {
1397                 mdelay(150);
1398                 val = V_WIN0_EN(0);
1399                 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
1400                 vop_msk_reg(vop_dev, WIN1_CTRL0, val);
1401
1402                 val = V_WIN2_EN(0) | V_WIN2_MST0_EN(0) |
1403                         V_WIN2_MST1_EN(0) |
1404                         V_WIN2_MST2_EN(0) | V_WIN2_MST3_EN(0);
1405                 vop_msk_reg(vop_dev, WIN2_CTRL0, val);
1406                 vop_msk_reg(vop_dev, WIN3_CTRL0, val);
1407                 val = V_HDMI_OUT_EN(0);
1408                 vop_msk_reg(vop_dev, SYS_CTRL, val);
1409                 vop_cfg_done(vop_dev);
1410                 mdelay(50);
1411                 vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(1));
1412                 writel_relaxed(0, vop_dev->regs + REG_CFG_DONE);
1413                 mdelay(50);
1414         }
1415
1416         return 0;
1417 }
1418 */
1419
1420 static int vop_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1421 {
1422         u16 face = 0;
1423         u16 dclk_ddr = 0;
1424         struct vop_device *vop_dev =
1425             container_of(dev_drv, struct vop_device, driver);
1426         struct rk_screen *screen = dev_drv->cur_screen;
1427         u64 val;
1428
1429         if (unlikely(!vop_dev->clk_on)) {
1430                 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
1431                 return 0;
1432         }
1433
1434         if (!vop_dev->standby && initscreen && (dev_drv->first_frame != 1))
1435                 flush_kthread_worker(&dev_drv->update_regs_worker);
1436
1437         spin_lock(&vop_dev->reg_lock);
1438         if (likely(vop_dev->clk_on)) {
1439                 switch (screen->face) {
1440                 case OUT_P888:
1441                         if (rockchip_get_cpu_version())
1442                                 face = OUT_P101010;
1443                         else
1444                                 face = OUT_P888;
1445
1446                         val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(0)
1447                                 | V_PRE_DITHER_DOWN_EN(1);
1448                         break;
1449                 case OUT_YUV_420:
1450                         if (rockchip_get_cpu_version()) {
1451                                 face = OUT_YUV_420;
1452                                 dclk_ddr = 1;
1453                                 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(0)
1454                                         | V_PRE_DITHER_DOWN_EN(1);
1455                                 break;
1456                         }
1457                         dev_err(vop_dev->dev,
1458                                 "This chip can't supported screen face[%d]\n",
1459                                 screen->face);
1460                         break;
1461                 case OUT_YUV_420_10BIT:
1462                         if (rockchip_get_cpu_version()) {
1463                                 face = OUT_YUV_420;
1464                                 dclk_ddr = 1;
1465                                 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1)
1466                                         | V_PRE_DITHER_DOWN_EN(0);
1467                                 break;
1468                         }
1469                         dev_err(vop_dev->dev,
1470                                 "This chip can't supported screen face[%d]\n",
1471                                 screen->face);
1472                         break;
1473                 case OUT_P101010:
1474                         if (rockchip_get_cpu_version()) {
1475                                 face = OUT_P101010;
1476                                 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1)
1477                                         | V_PRE_DITHER_DOWN_EN(0);
1478                                 break;
1479                         }
1480                         dev_err(vop_dev->dev,
1481                                 "This chip can't supported screen face[%d]\n",
1482                                 screen->face);
1483                         break;
1484                 default:
1485                         dev_err(vop_dev->dev, "un supported screen face[%d]!\n",
1486                                 screen->face);
1487                         break;
1488                 }
1489
1490                 vop_msk_reg(vop_dev, DSP_CTRL1, val);
1491                 switch (screen->type) {
1492                 case SCREEN_TVOUT:
1493                         val = V_SW_UV_OFFSET_EN(1) | V_SW_IMD_TVE_DCLK_EN(1) |
1494                                 V_SW_IMD_TVE_DCLK_EN(1) |
1495                                 V_SW_IMD_TVE_DCLK_POL(1) |
1496                                 V_SW_GENLOCK(1) | V_SW_DAC_SEL(1);
1497                         if (screen->mode.xres == 720 &&
1498                             screen->mode.yres == 576)
1499                                 val |= V_SW_TVE_MODE(1);
1500                         else
1501                                 val |= V_SW_TVE_MODE(0);
1502                         vop_msk_reg(vop_dev, SYS_CTRL, val);
1503                         break;
1504                 case SCREEN_HDMI:
1505                         val = V_HDMI_OUT_EN(1) | V_SW_UV_OFFSET_EN(0);
1506                         vop_msk_reg(vop_dev, SYS_CTRL, val);
1507                         break;
1508                 default:
1509                         dev_err(vop_dev->dev, "un supported interface[%d]!\n",
1510                                 screen->type);
1511                         break;
1512                 }
1513                 val = V_HDMI_HSYNC_POL(screen->pin_hsync) |
1514                         V_HDMI_VSYNC_POL(screen->pin_vsync) |
1515                         V_HDMI_DEN_POL(screen->pin_den) |
1516                         V_HDMI_DCLK_POL(screen->pin_dclk);
1517                 /*hsync vsync den dclk polo,dither */
1518                 vop_msk_reg(vop_dev, DSP_CTRL1, val);
1519
1520                 if (screen->color_mode == COLOR_RGB)
1521                         dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1522                 else
1523                         dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1524
1525 #ifndef CONFIG_RK_FPGA
1526                 /*
1527                  * Todo:
1528                  * writel_relaxed(v, RK_GRF_VIRT + vop_GRF_SOC_CON7);
1529                  *  move to  lvds driver
1530                  */
1531                 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
1532 #endif
1533                 val = V_DSP_OUT_MODE(face) | V_DSP_DCLK_DDR(dclk_ddr) |
1534                     V_DSP_BG_SWAP(screen->swap_gb) |
1535                     V_DSP_RB_SWAP(screen->swap_rb) |
1536                     V_DSP_RG_SWAP(screen->swap_rg) |
1537                     V_DSP_DELTA_SWAP(screen->swap_delta) |
1538                     V_DSP_DUMMY_SWAP(screen->swap_dumy) | V_DSP_OUT_ZERO(0) |
1539                     V_DSP_BLANK_EN(0) | V_DSP_BLACK_EN(0) |
1540                     V_DSP_X_MIR_EN(screen->x_mirror) |
1541                     V_DSP_Y_MIR_EN(screen->y_mirror);
1542                 val |= V_SW_CORE_DCLK_SEL(!!screen->pixelrepeat);
1543                 if (screen->mode.vmode & FB_VMODE_INTERLACED)
1544                         val |= V_SW_HDMI_CLK_I_SEL(1);
1545                 else
1546                         val |= V_SW_HDMI_CLK_I_SEL(0);
1547                 vop_msk_reg(vop_dev, DSP_CTRL0, val);
1548
1549                 if (screen->mode.vmode & FB_VMODE_INTERLACED)
1550                         vop_msk_reg(vop_dev, SYS_CTRL1, V_REG_DONE_FRM(1));
1551                 else
1552                         vop_msk_reg(vop_dev, SYS_CTRL1, V_REG_DONE_FRM(0));
1553                 /* BG color */
1554                 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1555                         val = V_DSP_OUT_RGB_YUV(1);
1556                         vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
1557                         val = V_DSP_BG_BLUE(0x200) | V_DSP_BG_GREEN(0x40) |
1558                                 V_DSP_BG_RED(0x200);
1559                         vop_msk_reg(vop_dev, DSP_BG, val);
1560                 } else {
1561                         val = V_DSP_OUT_RGB_YUV(0);
1562                         vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
1563                         val = V_DSP_BG_BLUE(0) | V_DSP_BG_GREEN(0) |
1564                                 V_DSP_BG_RED(0);
1565                         vop_msk_reg(vop_dev, DSP_BG, val);
1566                 }
1567                 dev_drv->output_color = screen->color_mode;
1568                 vop_bcsh_path_sel(dev_drv);
1569                 vop_config_timing(dev_drv);
1570                 vop_cfg_done(vop_dev);
1571         }
1572         spin_unlock(&vop_dev->reg_lock);
1573         vop_set_dclk(dev_drv, 1);
1574         if (screen->type != SCREEN_HDMI && screen->type != SCREEN_TVOUT &&
1575             dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1576                 dev_drv->trsm_ops->enable();
1577         if (screen->init)
1578                 screen->init();
1579
1580         return 0;
1581 }
1582
1583 /*enable layer,open:1,enable;0 disable*/
1584 static void vop_layer_enable(struct vop_device *vop_dev,
1585                              unsigned int win_id, bool open)
1586 {
1587         spin_lock(&vop_dev->reg_lock);
1588         if (likely(vop_dev->clk_on) &&
1589             vop_dev->driver.win[win_id]->state != open) {
1590                 if (open) {
1591                         if (!vop_dev->atv_layer_cnt) {
1592                                 dev_info(vop_dev->dev,
1593                                          "wakeup from standby!\n");
1594                                 vop_dev->standby = 0;
1595                         }
1596                         vop_dev->atv_layer_cnt |= (1 << win_id);
1597                 } else {
1598                         if (vop_dev->atv_layer_cnt & (1 << win_id))
1599                                 vop_dev->atv_layer_cnt &= ~(1 << win_id);
1600                 }
1601                 vop_dev->driver.win[win_id]->state = open;
1602                 if (!open) {
1603                         vop_layer_update_regs(vop_dev,
1604                                               vop_dev->driver.win[win_id]);
1605                         vop_cfg_done(vop_dev);
1606                 }
1607                 /* if no layer used,disable lcdc */
1608                 if (!vop_dev->atv_layer_cnt) {
1609                         dev_info(vop_dev->dev,
1610                                  "no layer is used,go to standby!\n");
1611                         vop_dev->standby = 1;
1612                 }
1613         }
1614         spin_unlock(&vop_dev->reg_lock);
1615 }
1616
1617 static int vop_enable_irq(struct rk_lcdc_driver *dev_drv)
1618 {
1619         struct vop_device *vop_dev = container_of(dev_drv,
1620                                                     struct vop_device, driver);
1621         u64 val;
1622         /* struct rk_screen *screen = dev_drv->cur_screen; */
1623
1624         vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, INTR_MASK);
1625
1626         val = INTR_FS | INTR_LINE_FLAG0 | INTR_BUS_ERROR | INTR_LINE_FLAG1 |
1627                 INTR_WIN0_EMPTY | INTR_WIN1_EMPTY | INTR_HWC_EMPTY |
1628                 INTR_POST_BUF_EMPTY;
1629
1630         vop_mask_writel(vop_dev, INTR_EN0, INTR_MASK, val);
1631
1632         return 0;
1633 }
1634
1635 static int vop_open(struct rk_lcdc_driver *dev_drv, int win_id,
1636                     bool open)
1637 {
1638         struct vop_device *vop_dev =
1639             container_of(dev_drv, struct vop_device, driver);
1640
1641         /* enable clk,when first layer open */
1642         if ((open) && (!vop_dev->atv_layer_cnt)) {
1643                 /* rockchip_set_system_status(sys_status); */
1644                 vop_pre_init(dev_drv);
1645                 vop_clk_enable(vop_dev);
1646                 vop_enable_irq(dev_drv);
1647 #if defined(CONFIG_ROCKCHIP_IOMMU)
1648                 if (dev_drv->iommu_enabled) {
1649                         if (!dev_drv->mmu_dev) {
1650                                 dev_drv->mmu_dev =
1651                                     rk_fb_get_sysmmu_device_by_compatible
1652                                     (dev_drv->mmu_dts_name);
1653                                 if (dev_drv->mmu_dev) {
1654                                         rk_fb_platform_set_sysmmu
1655                                             (dev_drv->mmu_dev, dev_drv->dev);
1656                                 } else {
1657                                         dev_err(dev_drv->dev,
1658                                                 "fail get rk iommu device\n");
1659                                         return -1;
1660                                 }
1661                         }
1662                 }
1663 #endif
1664                 if ((support_uboot_display() && (vop_dev->prop == PRMRY)))
1665                         vop_set_dclk(dev_drv, 0);
1666                 else
1667                         vop_load_screen(dev_drv, 1);
1668                 if (dev_drv->bcsh.enable)
1669                         vop_set_bcsh(dev_drv, 1);
1670                 spin_lock(&vop_dev->reg_lock);
1671                 spin_unlock(&vop_dev->reg_lock);
1672         }
1673
1674         if (win_id < ARRAY_SIZE(vop_win))
1675                 vop_layer_enable(vop_dev, win_id, open);
1676         else
1677                 dev_err(vop_dev->dev, "invalid win id:%d\n", win_id);
1678
1679         dev_drv->first_frame = 0;
1680         return 0;
1681 }
1682
1683 static int win_0_1_display(struct vop_device *vop_dev,
1684                            struct rk_lcdc_win *win)
1685 {
1686         u32 y_addr;
1687         u32 uv_addr;
1688         unsigned int off;
1689
1690         off = win->id * 0x40;
1691         /*win->smem_start + win->y_offset; */
1692         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1693         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1694         DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
1695             vop_dev->id, win->id, y_addr, uv_addr);
1696         DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
1697             win->area[0].y_offset, win->area[0].c_offset);
1698         spin_lock(&vop_dev->reg_lock);
1699         if (likely(vop_dev->clk_on)) {
1700                 win->area[0].y_addr = y_addr;
1701                 win->area[0].uv_addr = uv_addr;
1702                 vop_writel(vop_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
1703                 vop_writel(vop_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
1704         }
1705         spin_unlock(&vop_dev->reg_lock);
1706
1707         return 0;
1708 }
1709
1710 static int hwc_display(struct vop_device *vop_dev, struct rk_lcdc_win *win)
1711 {
1712         u32 y_addr;
1713
1714         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1715         DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
1716             vop_dev->id, __func__, y_addr);
1717         spin_lock(&vop_dev->reg_lock);
1718         if (likely(vop_dev->clk_on)) {
1719                 win->area[0].y_addr = y_addr;
1720                 vop_writel(vop_dev, HWC_MST, win->area[0].y_addr);
1721         }
1722         spin_unlock(&vop_dev->reg_lock);
1723
1724         return 0;
1725 }
1726
1727 static int vop_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
1728 {
1729         struct vop_device *vop_dev =
1730             container_of(dev_drv, struct vop_device, driver);
1731         struct rk_lcdc_win *win = NULL;
1732         struct rk_screen *screen = dev_drv->cur_screen;
1733
1734         win = dev_drv->win[win_id];
1735         if (!screen) {
1736                 dev_err(dev_drv->dev, "screen is null!\n");
1737                 return -ENOENT;
1738         }
1739         if (unlikely(!vop_dev->clk_on)) {
1740                 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
1741                 return 0;
1742         }
1743         if (win_id == 0) {
1744                 win_0_1_display(vop_dev, win);
1745         } else if (win_id == 1) {
1746                 win_0_1_display(vop_dev, win);
1747         } else if (win_id == 2) {
1748                 hwc_display(vop_dev, win);
1749         } else {
1750                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1751                 return -EINVAL;
1752         }
1753
1754         return 0;
1755 }
1756
1757 static int vop_cal_scl_fac(struct rk_lcdc_win *win, struct rk_screen *screen)
1758 {
1759         u16 srcW;
1760         u16 srcH;
1761         u16 dstW;
1762         u16 dstH;
1763         u16 yrgb_srcW;
1764         u16 yrgb_srcH;
1765         u16 yrgb_dstW;
1766         u16 yrgb_dstH;
1767         u32 yrgb_vscalednmult;
1768         u32 yrgb_xscl_factor;
1769         u32 yrgb_yscl_factor;
1770         u8 yrgb_vsd_bil_gt2 = 0;
1771         u8 yrgb_vsd_bil_gt4 = 0;
1772
1773         u16 cbcr_srcW;
1774         u16 cbcr_srcH;
1775         u16 cbcr_dstW;
1776         u16 cbcr_dstH;
1777         u32 cbcr_vscalednmult;
1778         u32 cbcr_xscl_factor;
1779         u32 cbcr_yscl_factor;
1780         u8 cbcr_vsd_bil_gt2 = 0;
1781         u8 cbcr_vsd_bil_gt4 = 0;
1782         u8 yuv_fmt = 0;
1783
1784         srcW = win->area[0].xact;
1785         if ((screen->mode.vmode & FB_VMODE_INTERLACED) &&
1786             (win->area[0].yact == 2 * win->area[0].ysize)) {
1787                 srcH = win->area[0].yact / 2;
1788                 yrgb_vsd_bil_gt2 = 1;
1789                 cbcr_vsd_bil_gt2 = 1;
1790         } else {
1791                 srcH = win->area[0].yact;
1792         }
1793         dstW = win->area[0].xsize;
1794         dstH = win->area[0].ysize;
1795
1796         /*yrgb scl mode */
1797         yrgb_srcW = srcW;
1798         yrgb_srcH = srcH;
1799         yrgb_dstW = dstW;
1800         yrgb_dstH = dstH;
1801         if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
1802                 pr_err("ERROR: yrgb scale exceed 8,");
1803                 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
1804                        yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
1805         }
1806         if (yrgb_srcW < yrgb_dstW)
1807                 win->yrgb_hor_scl_mode = SCALE_UP;
1808         else if (yrgb_srcW > yrgb_dstW)
1809                 win->yrgb_hor_scl_mode = SCALE_DOWN;
1810         else
1811                 win->yrgb_hor_scl_mode = SCALE_NONE;
1812
1813         if (yrgb_srcH < yrgb_dstH)
1814                 win->yrgb_ver_scl_mode = SCALE_UP;
1815         else if (yrgb_srcH > yrgb_dstH)
1816                 win->yrgb_ver_scl_mode = SCALE_DOWN;
1817         else
1818                 win->yrgb_ver_scl_mode = SCALE_NONE;
1819
1820         /*cbcr scl mode */
1821         switch (win->area[0].format) {
1822         case YUV422:
1823         case YUV422_A:
1824                 cbcr_srcW = srcW / 2;
1825                 cbcr_dstW = dstW;
1826                 cbcr_srcH = srcH;
1827                 cbcr_dstH = dstH;
1828                 yuv_fmt = 1;
1829                 break;
1830         case YUV420:
1831         case YUV420_A:
1832         case YUV420_NV21:
1833                 cbcr_srcW = srcW / 2;
1834                 cbcr_dstW = dstW;
1835                 cbcr_srcH = srcH / 2;
1836                 cbcr_dstH = dstH;
1837                 yuv_fmt = 1;
1838                 break;
1839         case YUV444:
1840         case YUV444_A:
1841                 cbcr_srcW = srcW;
1842                 cbcr_dstW = dstW;
1843                 cbcr_srcH = srcH;
1844                 cbcr_dstH = dstH;
1845                 yuv_fmt = 1;
1846                 break;
1847         default:
1848                 cbcr_srcW = 0;
1849                 cbcr_dstW = 0;
1850                 cbcr_srcH = 0;
1851                 cbcr_dstH = 0;
1852                 yuv_fmt = 0;
1853                 break;
1854         }
1855         if (yuv_fmt) {
1856                 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
1857                     (cbcr_dstH * 8 <= cbcr_srcH)) {
1858                         pr_err("ERROR: cbcr scale exceed 8,");
1859                         pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
1860                                cbcr_srcH, cbcr_dstW, cbcr_dstH);
1861                 }
1862         }
1863
1864         if (cbcr_srcW < cbcr_dstW)
1865                 win->cbr_hor_scl_mode = SCALE_UP;
1866         else if (cbcr_srcW > cbcr_dstW)
1867                 win->cbr_hor_scl_mode = SCALE_DOWN;
1868         else
1869                 win->cbr_hor_scl_mode = SCALE_NONE;
1870
1871         if (cbcr_srcH < cbcr_dstH)
1872                 win->cbr_ver_scl_mode = SCALE_UP;
1873         else if (cbcr_srcH > cbcr_dstH)
1874                 win->cbr_ver_scl_mode = SCALE_DOWN;
1875         else
1876                 win->cbr_ver_scl_mode = SCALE_NONE;
1877
1878         /* line buffer mode */
1879         if ((win->area[0].format == YUV422) ||
1880             (win->area[0].format == YUV420) ||
1881             (win->area[0].format == YUV420_NV21) ||
1882             (win->area[0].format == YUV422_A) ||
1883             (win->area[0].format == YUV420_A)) {
1884                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
1885                         if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
1886                             (cbcr_dstW == 0))
1887                                 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
1888                                        cbcr_dstW);
1889                         else if (cbcr_dstW > 1280)
1890                                 win->win_lb_mode = LB_YUV_3840X5;
1891                         else
1892                                 win->win_lb_mode = LB_YUV_2560X8;
1893                 } else {        /* SCALE_UP or SCALE_NONE */
1894                         if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
1895                             (cbcr_srcW == 0))
1896                                 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
1897                                        cbcr_srcW);
1898                         else if (cbcr_srcW > 1280)
1899                                 win->win_lb_mode = LB_YUV_3840X5;
1900                         else
1901                                 win->win_lb_mode = LB_YUV_2560X8;
1902                 }
1903         } else {
1904                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
1905                         if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
1906                             (yrgb_dstW == 0))
1907                                 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
1908                         else if (yrgb_dstW > 2560)
1909                                 win->win_lb_mode = LB_RGB_3840X2;
1910                         else if (yrgb_dstW > 1920)
1911                                 win->win_lb_mode = LB_RGB_2560X4;
1912                         else if (yrgb_dstW > 1280)
1913                                 win->win_lb_mode = LB_RGB_1920X5;
1914                         else
1915                                 win->win_lb_mode = LB_RGB_1280X8;
1916                 } else {        /* SCALE_UP or SCALE_NONE */
1917                         if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
1918                             (yrgb_srcW == 0))
1919                                 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
1920                         else if (yrgb_srcW > 2560)
1921                                 win->win_lb_mode = LB_RGB_3840X2;
1922                         else if (yrgb_srcW > 1920)
1923                                 win->win_lb_mode = LB_RGB_2560X4;
1924                         else if (yrgb_srcW > 1280)
1925                                 win->win_lb_mode = LB_RGB_1920X5;
1926                         else
1927                                 win->win_lb_mode = LB_RGB_1280X8;
1928                 }
1929         }
1930         DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
1931
1932         /* vsd/vsu scale ALGORITHM */
1933         win->yrgb_hsd_mode = SCALE_DOWN_BIL;    /*not to specify */
1934         win->cbr_hsd_mode = SCALE_DOWN_BIL;     /*not to specify */
1935         win->yrgb_vsd_mode = SCALE_DOWN_BIL;    /*not to specify */
1936         win->cbr_vsd_mode = SCALE_DOWN_BIL;     /*not to specify */
1937         switch (win->win_lb_mode) {
1938         case LB_YUV_3840X5:
1939         case LB_YUV_2560X8:
1940         case LB_RGB_1920X5:
1941         case LB_RGB_1280X8:
1942                 win->yrgb_vsu_mode = SCALE_UP_BIC;
1943                 win->cbr_vsu_mode = SCALE_UP_BIC;
1944                 break;
1945         case LB_RGB_3840X2:
1946                 if (win->yrgb_ver_scl_mode != SCALE_NONE)
1947                         pr_err("ERROR : not allow yrgb ver scale\n");
1948                 if (win->cbr_ver_scl_mode != SCALE_NONE)
1949                         pr_err("ERROR : not allow cbcr ver scale\n");
1950                 break;
1951         case LB_RGB_2560X4:
1952                 win->yrgb_vsu_mode = SCALE_UP_BIL;
1953                 win->cbr_vsu_mode = SCALE_UP_BIL;
1954                 break;
1955         default:
1956                 pr_info("%s:un supported win_lb_mode:%d\n",
1957                         __func__, win->win_lb_mode);
1958                 break;
1959         }
1960
1961         if (win->ymirror == 1)
1962                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
1963         if (screen->mode.vmode & FB_VMODE_INTERLACED) {
1964                 /* interlace mode must bill */
1965                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
1966                 win->cbr_vsd_mode = SCALE_DOWN_BIL;
1967         }
1968         if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
1969             (win->area[0].fbdc_en == 1)) {
1970                 /* in this pattern,use bil mode,not support souble scd,
1971                 use avg mode, support double scd, but aclk should be
1972                 bigger than dclk,aclk>>dclk */
1973                 if (yrgb_srcH >= 2 * yrgb_dstH) {
1974                         pr_err("ERROR : fbdc mode,not support y scale down:");
1975                         pr_err("srcH[%d] > 2 *dstH[%d]\n",
1976                                yrgb_srcH, yrgb_dstH);
1977                 }
1978         }
1979         DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
1980             win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
1981             win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
1982
1983         /* SCALE FACTOR */
1984
1985         /* (1.1)YRGB HOR SCALE FACTOR */
1986         switch (win->yrgb_hor_scl_mode) {
1987         case SCALE_NONE:
1988                 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
1989                 break;
1990         case SCALE_UP:
1991                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
1992                 break;
1993         case SCALE_DOWN:
1994                 switch (win->yrgb_hsd_mode) {
1995                 case SCALE_DOWN_BIL:
1996                         yrgb_xscl_factor =
1997                             GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
1998                         break;
1999                 case SCALE_DOWN_AVG:
2000                         yrgb_xscl_factor =
2001                             GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2002                         break;
2003                 default:
2004                         pr_info("%s:un supported yrgb_hsd_mode:%d\n", __func__,
2005                                 win->yrgb_hsd_mode);
2006                         break;
2007                 }
2008                 break;
2009         default:
2010                 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2011                         __func__, win->yrgb_hor_scl_mode);
2012                 break;
2013         }
2014
2015         /* (1.2)YRGB VER SCALE FACTOR */
2016         switch (win->yrgb_ver_scl_mode) {
2017         case SCALE_NONE:
2018                 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2019                 break;
2020         case SCALE_UP:
2021                 switch (win->yrgb_vsu_mode) {
2022                 case SCALE_UP_BIL:
2023                         yrgb_yscl_factor =
2024                             GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2025                         break;
2026                 case SCALE_UP_BIC:
2027                         if (yrgb_srcH < 3) {
2028                                 pr_err("yrgb_srcH should be");
2029                                 pr_err(" greater than 3 !!!\n");
2030                         }
2031                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2032                                                                 yrgb_dstH);
2033                         break;
2034                 default:
2035                         pr_info("%s:un support yrgb_vsu_mode:%d\n",
2036                                 __func__, win->yrgb_vsu_mode);
2037                         break;
2038                 }
2039                 break;
2040         case SCALE_DOWN:
2041                 switch (win->yrgb_vsd_mode) {
2042                 case SCALE_DOWN_BIL:
2043                         yrgb_vscalednmult =
2044                             vop_get_hard_ware_vskiplines(yrgb_srcH, yrgb_dstH);
2045                         yrgb_yscl_factor =
2046                             GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2047                                                            yrgb_vscalednmult);
2048                         if (yrgb_yscl_factor >= 0x2000) {
2049                                 pr_err("yrgb_yscl_factor should less 0x2000");
2050                                 pr_err("yrgb_yscl_factor=%4x;\n",
2051                                        yrgb_yscl_factor);
2052                         }
2053                         if (yrgb_vscalednmult == 4) {
2054                                 yrgb_vsd_bil_gt4 = 1;
2055                                 yrgb_vsd_bil_gt2 = 0;
2056                         } else if (yrgb_vscalednmult == 2) {
2057                                 yrgb_vsd_bil_gt4 = 0;
2058                                 yrgb_vsd_bil_gt2 = 1;
2059                         } else {
2060                                 yrgb_vsd_bil_gt4 = 0;
2061                                 yrgb_vsd_bil_gt2 = 0;
2062                         }
2063                         break;
2064                 case SCALE_DOWN_AVG:
2065                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2066                                                                  yrgb_dstH);
2067                         break;
2068                 default:
2069                         pr_info("%s:un support yrgb_vsd_mode:%d\n",
2070                                 __func__, win->yrgb_vsd_mode);
2071                         break;
2072                 }               /*win->yrgb_vsd_mode */
2073                 break;
2074         default:
2075                 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2076                         __func__, win->yrgb_ver_scl_mode);
2077                 break;
2078         }
2079         win->scale_yrgb_x = yrgb_xscl_factor;
2080         win->scale_yrgb_y = yrgb_yscl_factor;
2081         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2082         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2083         DBG(1, "yrgb:h_fac=%d, V_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2084             yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2085
2086         /*(2.1)CBCR HOR SCALE FACTOR */
2087         switch (win->cbr_hor_scl_mode) {
2088         case SCALE_NONE:
2089                 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2090                 break;
2091         case SCALE_UP:
2092                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2093                 break;
2094         case SCALE_DOWN:
2095                 switch (win->cbr_hsd_mode) {
2096                 case SCALE_DOWN_BIL:
2097                         cbcr_xscl_factor =
2098                             GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2099                         break;
2100                 case SCALE_DOWN_AVG:
2101                         cbcr_xscl_factor =
2102                             GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2103                         break;
2104                 default:
2105                         pr_info("%s:un support cbr_hsd_mode:%d\n",
2106                                 __func__, win->cbr_hsd_mode);
2107                         break;
2108                 }
2109                 break;
2110         default:
2111                 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2112                         __func__, win->cbr_hor_scl_mode);
2113                 break;
2114         }                       /*win->cbr_hor_scl_mode */
2115
2116         /* (2.2)CBCR VER SCALE FACTOR */
2117         switch (win->cbr_ver_scl_mode) {
2118         case SCALE_NONE:
2119                 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2120                 break;
2121         case SCALE_UP:
2122                 switch (win->cbr_vsu_mode) {
2123                 case SCALE_UP_BIL:
2124                         cbcr_yscl_factor =
2125                             GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2126                         break;
2127                 case SCALE_UP_BIC:
2128                         if (cbcr_srcH < 3) {
2129                                 pr_err("cbcr_srcH should be ");
2130                                 pr_err("greater than 3 !!!\n");
2131                         }
2132                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2133                                                                 cbcr_dstH);
2134                         break;
2135                 default:
2136                         pr_info("%s:un support cbr_vsu_mode:%d\n",
2137                                 __func__, win->cbr_vsu_mode);
2138                         break;
2139                 }
2140                 break;
2141         case SCALE_DOWN:
2142                 switch (win->cbr_vsd_mode) {
2143                 case SCALE_DOWN_BIL:
2144                         cbcr_vscalednmult =
2145                             vop_get_hard_ware_vskiplines(cbcr_srcH, cbcr_dstH);
2146                         cbcr_yscl_factor =
2147                             GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2148                                                            cbcr_vscalednmult);
2149                         if (cbcr_yscl_factor >= 0x2000) {
2150                                 pr_err("cbcr_yscl_factor should be less ");
2151                                 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2152                                        cbcr_yscl_factor);
2153                         }
2154
2155                         if (cbcr_vscalednmult == 4) {
2156                                 cbcr_vsd_bil_gt4 = 1;
2157                                 cbcr_vsd_bil_gt2 = 0;
2158                         } else if (cbcr_vscalednmult == 2) {
2159                                 cbcr_vsd_bil_gt4 = 0;
2160                                 cbcr_vsd_bil_gt2 = 1;
2161                         } else {
2162                                 cbcr_vsd_bil_gt4 = 0;
2163                                 cbcr_vsd_bil_gt2 = 0;
2164                         }
2165                         break;
2166                 case SCALE_DOWN_AVG:
2167                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2168                                                                  cbcr_dstH);
2169                         break;
2170                 default:
2171                         pr_info("%s:un support cbr_vsd_mode:%d\n",
2172                                 __func__, win->cbr_vsd_mode);
2173                         break;
2174                 }
2175                 break;
2176         default:
2177                 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2178                         __func__, win->cbr_ver_scl_mode);
2179                 break;
2180         }
2181         win->scale_cbcr_x = cbcr_xscl_factor;
2182         win->scale_cbcr_y = cbcr_yscl_factor;
2183         win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2184         win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2185
2186         DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2187             cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2188         return 0;
2189 }
2190
2191 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2192                      struct rk_lcdc_win_area *area)
2193 {
2194         int pos;
2195
2196         if (screen->x_mirror && mirror_en)
2197                 pr_err("not support both win and global mirror\n");
2198
2199         if ((!mirror_en) && (!screen->x_mirror))
2200                 pos = area->xpos + screen->mode.left_margin +
2201                         screen->mode.hsync_len;
2202         else
2203                 pos = screen->mode.xres - area->xpos -
2204                         area->xsize + screen->mode.left_margin +
2205                         screen->mode.hsync_len;
2206
2207         return pos;
2208 }
2209
2210 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2211                      struct rk_lcdc_win_area *area)
2212 {
2213         int pos;
2214
2215         if (screen->y_mirror && mirror_en)
2216                 pr_err("not support both win and global mirror\n");
2217
2218         if ((!mirror_en) && (!screen->y_mirror))
2219                 pos = area->ypos + screen->mode.upper_margin +
2220                         screen->mode.vsync_len;
2221         else
2222                 pos = screen->mode.yres - area->ypos -
2223                         area->ysize + screen->mode.upper_margin +
2224                         screen->mode.vsync_len;
2225
2226         return pos;
2227 }
2228
2229 static int win_0_1_set_par(struct vop_device *vop_dev,
2230                            struct rk_screen *screen, struct rk_lcdc_win *win)
2231 {
2232         u32 xact, yact, xvir, yvir, xpos, ypos;
2233         u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2234         char fmt[9] = "NULL";
2235
2236         xpos = dsp_x_pos(win->xmirror, screen, &win->area[0]);
2237         ypos = dsp_y_pos(win->ymirror, screen, &win->area[0]);
2238
2239         spin_lock(&vop_dev->reg_lock);
2240         if (likely(vop_dev->clk_on)) {
2241                 vop_cal_scl_fac(win, screen);
2242                 switch (win->area[0].format) {
2243                 case FBDC_RGB_565:
2244                         fmt_cfg = 2;
2245                         swap_rb = 0;
2246                         win->fmt_10 = 0;
2247                         win->area[0].fbdc_fmt_cfg = 0x05;
2248                         break;
2249                 case FBDC_ARGB_888:
2250                         fmt_cfg = 0;
2251                         swap_rb = 0;
2252                         win->fmt_10 = 0;
2253                         win->area[0].fbdc_fmt_cfg = 0x0c;
2254                         break;
2255                 case FBDC_ABGR_888:
2256                         fmt_cfg = 0;
2257                         swap_rb = 1;
2258                         win->fmt_10 = 0;
2259                         win->area[0].fbdc_fmt_cfg = 0x0c;
2260                         break;
2261                 case FBDC_RGBX_888:
2262                         fmt_cfg = 0;
2263                         swap_rb = 0;
2264                         win->fmt_10 = 0;
2265                         win->area[0].fbdc_fmt_cfg = 0x3a;
2266                         break;
2267                 case ARGB888:
2268                         fmt_cfg = 0;
2269                         swap_rb = 0;
2270                         win->fmt_10 = 0;
2271                         break;
2272                 case XBGR888:
2273                 case ABGR888:
2274                         fmt_cfg = 0;
2275                         swap_rb = 1;
2276                         win->fmt_10 = 0;
2277                         break;
2278                 case BGR888:
2279                         fmt_cfg = 1;
2280                         swap_rb = 1;
2281                         win->fmt_10 = 0;
2282                         break;
2283                 case RGB888:
2284                         fmt_cfg = 1;
2285                         swap_rb = 0;
2286                         win->fmt_10 = 0;
2287                         break;
2288                 case RGB565:
2289                         fmt_cfg = 2;
2290                         swap_rb = 0;
2291                         win->fmt_10 = 0;
2292                         break;
2293                 case YUV422:
2294                         fmt_cfg = 5;
2295                         swap_rb = 0;
2296                         win->fmt_10 = 0;
2297                         break;
2298                 case YUV420:
2299                         fmt_cfg = 4;
2300                         swap_rb = 0;
2301                         win->fmt_10 = 0;
2302                         break;
2303                 case YUV420_NV21:
2304                         fmt_cfg = 4;
2305                         swap_rb = 0;
2306                         swap_uv = 1;
2307                         win->fmt_10 = 0;
2308                         break;
2309                 case YUV444:
2310                         fmt_cfg = 6;
2311                         swap_rb = 0;
2312                         win->fmt_10 = 0;
2313                         break;
2314                 case YUV422_A:
2315                         fmt_cfg = 5;
2316                         swap_rb = 0;
2317                         win->fmt_10 = 1;
2318                         break;
2319                 case YUV420_A:
2320                         fmt_cfg = 4;
2321                         swap_rb = 0;
2322                         win->fmt_10 = 1;
2323                         break;
2324                 case YUV444_A:
2325                         fmt_cfg = 6;
2326                         swap_rb = 0;
2327                         win->fmt_10 = 1;
2328                         break;
2329                 default:
2330                         dev_err(vop_dev->dev, "%s:unsupport format[%d]!\n",
2331                                 __func__, win->area[0].format);
2332                         break;
2333                 }
2334                 win->area[0].fmt_cfg = fmt_cfg;
2335                 win->area[0].swap_rb = swap_rb;
2336                 win->area[0].swap_uv = swap_uv;
2337                 win->area[0].dsp_stx = xpos;
2338                 win->area[0].dsp_sty = ypos;
2339                 xact = win->area[0].xact;
2340                 yact = win->area[0].yact;
2341                 xvir = win->area[0].xvir;
2342                 yvir = win->area[0].yvir;
2343         }
2344         vop_win_0_1_reg_update(&vop_dev->driver, win->id);
2345         spin_unlock(&vop_dev->reg_lock);
2346
2347         DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2348             vop_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2349             xact, yact, win->area[0].xsize);
2350         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2351             win->area[0].ysize, xvir, yvir, xpos, ypos);
2352
2353         return 0;
2354 }
2355
2356 static int hwc_set_par(struct vop_device *vop_dev,
2357                        struct rk_screen *screen, struct rk_lcdc_win *win)
2358 {
2359         u32 xact, yact, xvir, yvir, xpos, ypos;
2360         u8 fmt_cfg = 0, swap_rb;
2361         char fmt[9] = "NULL";
2362
2363         xpos = win->area[0].xpos + screen->mode.left_margin +
2364             screen->mode.hsync_len;
2365         ypos = win->area[0].ypos + screen->mode.upper_margin +
2366             screen->mode.vsync_len;
2367
2368         spin_lock(&vop_dev->reg_lock);
2369         if (likely(vop_dev->clk_on)) {
2370                 switch (win->area[0].format) {
2371                 case ARGB888:
2372                         fmt_cfg = 0;
2373                         swap_rb = 0;
2374                         break;
2375                 case XBGR888:
2376                 case ABGR888:
2377                         fmt_cfg = 0;
2378                         swap_rb = 1;
2379                         break;
2380                 case RGB888:
2381                         fmt_cfg = 1;
2382                         swap_rb = 0;
2383                         break;
2384                 case RGB565:
2385                         fmt_cfg = 2;
2386                         swap_rb = 0;
2387                         break;
2388                 default:
2389                         dev_err(vop_dev->dev, "%s:un supported format[%d]!\n",
2390                                 __func__, win->area[0].format);
2391                         break;
2392                 }
2393                 win->area[0].fmt_cfg = fmt_cfg;
2394                 win->area[0].swap_rb = swap_rb;
2395                 win->area[0].dsp_stx = xpos;
2396                 win->area[0].dsp_sty = ypos;
2397                 xact = win->area[0].xact;
2398                 yact = win->area[0].yact;
2399                 xvir = win->area[0].xvir;
2400                 yvir = win->area[0].yvir;
2401         }
2402         vop_hwc_reg_update(&vop_dev->driver, 2);
2403         spin_unlock(&vop_dev->reg_lock);
2404
2405         DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2406             vop_dev->id, __func__, get_format_string(win->area[0].format, fmt),
2407             xact, yact, win->area[0].xsize);
2408         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2409             win->area[0].ysize, xvir, yvir, xpos, ypos);
2410         return 0;
2411 }
2412
2413 static int vop_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
2414 {
2415         struct vop_device *vop_dev =
2416             container_of(dev_drv, struct vop_device, driver);
2417         struct rk_lcdc_win *win = NULL;
2418         struct rk_screen *screen = dev_drv->cur_screen;
2419
2420         if (unlikely(!vop_dev->clk_on)) {
2421                 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
2422                 return 0;
2423         }
2424         win = dev_drv->win[win_id];
2425         switch (win_id) {
2426         case 0:
2427                 win_0_1_set_par(vop_dev, screen, win);
2428                 break;
2429         case 1:
2430                 win_0_1_set_par(vop_dev, screen, win);
2431                 break;
2432         case 2:
2433                 hwc_set_par(vop_dev, screen, win);
2434                 break;
2435         default:
2436                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2437                 break;
2438         }
2439         return 0;
2440 }
2441
2442 static int vop_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2443                      unsigned long arg, int win_id)
2444 {
2445         struct vop_device *vop_dev =
2446                         container_of(dev_drv, struct vop_device, driver);
2447         u32 panel_size[2];
2448         void __user *argp = (void __user *)arg;
2449         struct color_key_cfg clr_key_cfg;
2450
2451         switch (cmd) {
2452         case RK_FBIOGET_PANEL_SIZE:
2453                 panel_size[0] = vop_dev->screen->mode.xres;
2454                 panel_size[1] = vop_dev->screen->mode.yres;
2455                 if (copy_to_user(argp, panel_size, 8))
2456                         return -EFAULT;
2457                 break;
2458         case RK_FBIOPUT_COLOR_KEY_CFG:
2459                 if (copy_from_user(&clr_key_cfg, argp,
2460                                    sizeof(struct color_key_cfg)))
2461                         return -EFAULT;
2462                 vop_clr_key_cfg(dev_drv);
2463                 vop_writel(vop_dev, WIN0_COLOR_KEY,
2464                            clr_key_cfg.win0_color_key_cfg);
2465                 vop_writel(vop_dev, WIN1_COLOR_KEY,
2466                            clr_key_cfg.win1_color_key_cfg);
2467                 break;
2468
2469         default:
2470                 break;
2471         }
2472         return 0;
2473 }
2474
2475 static int vop_get_backlight_device(struct rk_lcdc_driver *dev_drv)
2476 {
2477         struct vop_device *vop_dev = container_of(dev_drv,
2478                                                     struct vop_device, driver);
2479         struct device_node *backlight;
2480         struct property *prop;
2481         u32 *brightness_levels;
2482         u32 length, max, last;
2483
2484         if (vop_dev->backlight)
2485                 return 0;
2486         backlight = of_parse_phandle(vop_dev->dev->of_node, "backlight", 0);
2487         if (backlight) {
2488                 vop_dev->backlight = of_find_backlight_by_node(backlight);
2489                 if (!vop_dev->backlight)
2490                         dev_info(vop_dev->dev, "No find backlight device\n");
2491         } else {
2492                 dev_info(vop_dev->dev, "No find backlight device node\n");
2493         }
2494         prop = of_find_property(backlight, "brightness-levels", &length);
2495         if (!prop)
2496                 return -EINVAL;
2497         max = length / sizeof(u32);
2498         last = max - 1;
2499         brightness_levels = kmalloc(256, GFP_KERNEL);
2500         if (brightness_levels)
2501                 return -ENOMEM;
2502
2503         if (!of_property_read_u32_array(backlight, "brightness-levels",
2504                                         brightness_levels, max)) {
2505                 if (brightness_levels[0] > brightness_levels[last])
2506                         dev_drv->cabc_pwm_pol = 1;/*negative*/
2507                 else
2508                         dev_drv->cabc_pwm_pol = 0;/*positive*/
2509         } else {
2510                 dev_info(vop_dev->dev,
2511                          "Can not read brightness-levels value\n");
2512         }
2513
2514         kfree(brightness_levels);
2515
2516         return 0;
2517 }
2518
2519 static int vop_early_suspend(struct rk_lcdc_driver *dev_drv)
2520 {
2521         struct vop_device *vop_dev =
2522             container_of(dev_drv, struct vop_device, driver);
2523
2524         if (dev_drv->suspend_flag)
2525                 return 0;
2526
2527         dev_drv->suspend_flag = 1;
2528         flush_kthread_worker(&dev_drv->update_regs_worker);
2529
2530         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
2531                 dev_drv->trsm_ops->disable();
2532
2533         if (likely(vop_dev->clk_on)) {
2534                 spin_lock(&vop_dev->reg_lock);
2535                 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLANK_EN(1));
2536                 vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, INTR_MASK);
2537                 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_OUT_ZERO(1));
2538                 vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(1));
2539                 vop_cfg_done(vop_dev);
2540
2541                 if (dev_drv->iommu_enabled && dev_drv->mmu_dev)
2542                                 rockchip_iovmm_deactivate(dev_drv->dev);
2543
2544                 spin_unlock(&vop_dev->reg_lock);
2545         }
2546
2547         vop_clk_disable(vop_dev);
2548         rk_disp_pwr_disable(dev_drv);
2549
2550         return 0;
2551 }
2552
2553 static int vop_early_resume(struct rk_lcdc_driver *dev_drv)
2554 {
2555         struct vop_device *vop_dev =
2556             container_of(dev_drv, struct vop_device, driver);
2557
2558         if (!dev_drv->suspend_flag)
2559                 return 0;
2560         rk_disp_pwr_enable(dev_drv);
2561
2562         vop_clk_enable(vop_dev);
2563         memcpy(vop_dev->regs, vop_dev->regsbak, vop_dev->len);
2564
2565         spin_lock(&vop_dev->reg_lock);
2566
2567         vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_OUT_ZERO(0));
2568         vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(0));
2569         vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLANK_EN(0));
2570         vop_cfg_done(vop_dev);
2571         spin_unlock(&vop_dev->reg_lock);
2572
2573         if (dev_drv->iommu_enabled && dev_drv->mmu_dev) {
2574                 /* win address maybe effect after next frame start,
2575                  * but mmu maybe effect right now, so we delay 50ms
2576                  */
2577                 mdelay(50);
2578                 rockchip_iovmm_activate(dev_drv->dev);
2579         }
2580
2581         dev_drv->suspend_flag = 0;
2582
2583         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2584                 dev_drv->trsm_ops->enable();
2585
2586         return 0;
2587 }
2588
2589 static int vop_blank(struct rk_lcdc_driver *dev_drv, int win_id, int blank_mode)
2590 {
2591         switch (blank_mode) {
2592         case FB_BLANK_UNBLANK:
2593                 vop_early_resume(dev_drv);
2594                 break;
2595         case FB_BLANK_NORMAL:
2596                 vop_early_suspend(dev_drv);
2597                 break;
2598         default:
2599                 vop_early_suspend(dev_drv);
2600                 break;
2601         }
2602
2603         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
2604
2605         return 0;
2606 }
2607
2608 static int vop_get_win_state(struct rk_lcdc_driver *dev_drv,
2609                              int win_id, int area_id)
2610 {
2611         struct vop_device *vop_dev =
2612                         container_of(dev_drv, struct vop_device, driver);
2613         u32 area_status = 0, state = 0;
2614
2615         switch (win_id) {
2616         case 0:
2617                 area_status = vop_read_bit(vop_dev, WIN0_CTRL0, V_WIN0_EN(0));
2618                 break;
2619         case 1:
2620                 area_status = vop_read_bit(vop_dev, WIN1_CTRL0, V_WIN1_EN(0));
2621                 break;
2622         case 2:
2623                 area_status = vop_read_bit(vop_dev, HWC_CTRL0, V_HWC_EN(0));
2624                 break;
2625         default:
2626                 pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n",
2627                        __func__, win_id, area_id);
2628                 break;
2629         }
2630
2631         state = (area_status > 0) ? 1 : 0;
2632         return state;
2633 }
2634
2635 static int vop_get_area_num(struct rk_lcdc_driver *dev_drv,
2636                             unsigned int *area_support)
2637 {
2638         area_support[0] = 1;
2639         area_support[1] = 1;
2640
2641         return 0;
2642 }
2643
2644 /*overlay will be do at regupdate*/
2645 static int vop_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, bool set)
2646 {
2647         struct vop_device *vop_dev =
2648             container_of(dev_drv, struct vop_device, driver);
2649         struct rk_lcdc_win *win = NULL;
2650         int i, ovl;
2651         u64 val;
2652         int z_order_num = 0;
2653         int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
2654
2655         if (swap == 0) {
2656                 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
2657                         win = dev_drv->win[i];
2658                         if (win->state == 1)
2659                                 z_order_num++;
2660                 }
2661                 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
2662                         win = dev_drv->win[i];
2663                         if (win->state == 0)
2664                                 win->z_order = z_order_num++;
2665                         switch (win->z_order) {
2666                         case 0:
2667                                 layer0_sel = win->id;
2668                                 break;
2669                         case 1:
2670                                 layer1_sel = win->id;
2671                                 break;
2672                         case 2:
2673                                 layer2_sel = win->id;
2674                                 break;
2675                         case 3:
2676                                 layer3_sel = win->id;
2677                                 break;
2678                         default:
2679                                 break;
2680                         }
2681                 }
2682         } else {
2683                 layer0_sel = swap % 10;
2684                 layer1_sel = swap / 10 % 10;
2685                 layer2_sel = swap / 100 % 10;
2686                 layer3_sel = swap / 1000;
2687         }
2688
2689         spin_lock(&vop_dev->reg_lock);
2690         if (vop_dev->clk_on) {
2691                 if (set) {
2692                         val = V_DSP_LAYER0_SEL(layer0_sel) |
2693                             V_DSP_LAYER1_SEL(layer1_sel) |
2694                             V_DSP_LAYER2_SEL(layer2_sel) |
2695                             V_DSP_LAYER3_SEL(layer3_sel);
2696                         vop_msk_reg(vop_dev, DSP_CTRL1, val);
2697                 } else {
2698                         layer0_sel = vop_read_bit(vop_dev, DSP_CTRL1,
2699                                                   V_DSP_LAYER0_SEL(0));
2700                         layer1_sel = vop_read_bit(vop_dev, DSP_CTRL1,
2701                                                   V_DSP_LAYER1_SEL(0));
2702                         layer2_sel = vop_read_bit(vop_dev, DSP_CTRL1,
2703                                                   V_DSP_LAYER2_SEL(0));
2704                         layer3_sel = vop_read_bit(vop_dev, DSP_CTRL1,
2705                                                   V_DSP_LAYER3_SEL(0));
2706                         ovl = layer3_sel * 1000 + layer2_sel * 100 +
2707                             layer1_sel * 10 + layer0_sel;
2708                 }
2709         } else {
2710                 ovl = -EPERM;
2711         }
2712         spin_unlock(&vop_dev->reg_lock);
2713
2714         return ovl;
2715 }
2716
2717 static char *vop_format_to_string(int format, char *fmt)
2718 {
2719         if (!fmt)
2720                 return NULL;
2721
2722         switch (format) {
2723         case 0:
2724                 strcpy(fmt, "ARGB888");
2725                 break;
2726         case 1:
2727                 strcpy(fmt, "RGB888");
2728                 break;
2729         case 2:
2730                 strcpy(fmt, "RGB565");
2731                 break;
2732         case 4:
2733                 strcpy(fmt, "YCbCr420");
2734                 break;
2735         case 5:
2736                 strcpy(fmt, "YCbCr422");
2737                 break;
2738         case 6:
2739                 strcpy(fmt, "YCbCr444");
2740                 break;
2741         default:
2742                 strcpy(fmt, "invalid\n");
2743                 break;
2744         }
2745         return fmt;
2746 }
2747 static ssize_t vop_get_disp_info(struct rk_lcdc_driver *dev_drv,
2748                                  char *buf, int win_id)
2749 {
2750         struct vop_device *vop_dev =
2751             container_of(dev_drv, struct vop_device, driver);
2752         struct rk_screen *screen = dev_drv->cur_screen;
2753         u16 hsync_len = screen->mode.hsync_len;
2754         u16 left_margin = screen->mode.left_margin;
2755         u16 vsync_len = screen->mode.vsync_len;
2756         u16 upper_margin = screen->mode.upper_margin;
2757         u32 h_pw_bp = hsync_len + left_margin;
2758         u32 v_pw_bp = vsync_len + upper_margin;
2759         u32 fmt_id;
2760         char format_w0[9] = "NULL";
2761         char format_w1[9] = "NULL";
2762         char dsp_buf[100];
2763         u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
2764         u32 y_factor, uv_factor;
2765         u8 layer0_sel, layer1_sel;
2766         u8 w0_state, w1_state;
2767
2768         u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
2769         u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
2770         u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
2771         u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
2772         u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
2773         u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
2774
2775         u32 dclk_freq;
2776         int size = 0;
2777
2778         dclk_freq = screen->mode.pixclock;
2779         /*vop_reg_dump(dev_drv); */
2780
2781         spin_lock(&vop_dev->reg_lock);
2782         if (vop_dev->clk_on) {
2783                 zorder = vop_readl(vop_dev, DSP_CTRL1);
2784                 layer0_sel = (zorder & MASK(DSP_LAYER0_SEL)) >> 8;
2785                 layer1_sel = (zorder & MASK(DSP_LAYER1_SEL)) >> 10;
2786                 /* WIN0 */
2787                 win_ctrl = vop_readl(vop_dev, WIN0_CTRL0);
2788                 w0_state = win_ctrl & MASK(WIN0_EN);
2789                 fmt_id = (win_ctrl & MASK(WIN0_DATA_FMT)) >> 1;
2790                 vop_format_to_string(fmt_id, format_w0);
2791                 vir_info = vop_readl(vop_dev, WIN0_VIR);
2792                 act_info = vop_readl(vop_dev, WIN0_ACT_INFO);
2793                 dsp_info = vop_readl(vop_dev, WIN0_DSP_INFO);
2794                 dsp_st = vop_readl(vop_dev, WIN0_DSP_ST);
2795                 y_factor = vop_readl(vop_dev, WIN0_SCL_FACTOR_YRGB);
2796                 uv_factor = vop_readl(vop_dev, WIN0_SCL_FACTOR_CBR);
2797                 w0_vir_y = vir_info & MASK(WIN0_VIR_STRIDE);
2798                 w0_vir_uv = (vir_info & MASK(WIN0_VIR_STRIDE_UV)) >> 16;
2799                 w0_act_x = (act_info & MASK(WIN0_ACT_WIDTH)) + 1;
2800                 w0_act_y = ((act_info & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1;
2801                 w0_dsp_x = (dsp_info & MASK(WIN0_DSP_WIDTH)) + 1;
2802                 w0_dsp_y = ((dsp_info & MASK(WIN0_DSP_HEIGHT)) >> 16) + 1;
2803                 if (w0_state) {
2804                         w0_st_x = dsp_st & MASK(WIN0_DSP_XST);
2805                         w0_st_y = (dsp_st & MASK(WIN0_DSP_YST)) >> 16;
2806                 }
2807                 w0_y_h_fac = y_factor & MASK(WIN0_HS_FACTOR_YRGB);
2808                 w0_y_v_fac = (y_factor & MASK(WIN0_VS_FACTOR_YRGB)) >> 16;
2809                 w0_uv_h_fac = uv_factor & MASK(WIN0_HS_FACTOR_CBR);
2810                 w0_uv_v_fac = (uv_factor & MASK(WIN0_VS_FACTOR_CBR)) >> 16;
2811
2812                 /* WIN1 */
2813                 win_ctrl = vop_readl(vop_dev, WIN1_CTRL0);
2814                 w1_state = win_ctrl & MASK(WIN1_EN);
2815                 fmt_id = (win_ctrl & MASK(WIN1_DATA_FMT)) >> 1;
2816                 vop_format_to_string(fmt_id, format_w1);
2817                 vir_info = vop_readl(vop_dev, WIN1_VIR);
2818                 act_info = vop_readl(vop_dev, WIN1_ACT_INFO);
2819                 dsp_info = vop_readl(vop_dev, WIN1_DSP_INFO);
2820                 dsp_st = vop_readl(vop_dev, WIN1_DSP_ST);
2821                 y_factor = vop_readl(vop_dev, WIN1_SCL_FACTOR_YRGB);
2822                 uv_factor = vop_readl(vop_dev, WIN1_SCL_FACTOR_CBR);
2823                 w1_vir_y = vir_info & MASK(WIN1_VIR_STRIDE);
2824                 w1_vir_uv = (vir_info & MASK(WIN1_VIR_STRIDE_UV)) >> 16;
2825                 w1_act_x = (act_info & MASK(WIN1_ACT_WIDTH)) + 1;
2826                 w1_act_y = ((act_info & MASK(WIN1_ACT_HEIGHT)) >> 16) + 1;
2827                 w1_dsp_x = (dsp_info & MASK(WIN1_DSP_WIDTH)) + 1;
2828                 w1_dsp_y = ((dsp_info & MASK(WIN1_DSP_HEIGHT)) >> 16) + 1;
2829                 if (w1_state) {
2830                         w1_st_x = dsp_st & MASK(WIN1_DSP_XST);
2831                         w1_st_y = (dsp_st & MASK(WIN1_DSP_YST)) >> 16;
2832                 }
2833                 w1_y_h_fac = y_factor & MASK(WIN1_HS_FACTOR_YRGB);
2834                 w1_y_v_fac = (y_factor & MASK(WIN1_VS_FACTOR_YRGB)) >> 16;
2835                 w1_uv_h_fac = uv_factor & MASK(WIN1_HS_FACTOR_CBR);
2836                 w1_uv_v_fac = (uv_factor & MASK(WIN1_VS_FACTOR_CBR)) >> 16;
2837         } else {
2838                 spin_unlock(&vop_dev->reg_lock);
2839                 return -EPERM;
2840         }
2841         spin_unlock(&vop_dev->reg_lock);
2842         size += snprintf(dsp_buf, 80,
2843                 "z-order:\n  win[%d]\n  win[%d]\n",
2844                 layer1_sel, layer0_sel);
2845         strcat(buf, dsp_buf);
2846         memset(dsp_buf, 0, sizeof(dsp_buf));
2847         /* win0 */
2848         size += snprintf(dsp_buf, 80,
2849                  "win0:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
2850                  w0_state, format_w0, w0_vir_y, w0_vir_uv);
2851         strcat(buf, dsp_buf);
2852         memset(dsp_buf, 0, sizeof(dsp_buf));
2853
2854         size += snprintf(dsp_buf, 80,
2855                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
2856                  w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
2857         strcat(buf, dsp_buf);
2858         memset(dsp_buf, 0, sizeof(dsp_buf));
2859
2860         size += snprintf(dsp_buf, 80,
2861                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
2862                  w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
2863         strcat(buf, dsp_buf);
2864         memset(dsp_buf, 0, sizeof(dsp_buf));
2865
2866         size += snprintf(dsp_buf, 80,
2867                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
2868                  w0_uv_h_fac, w0_uv_v_fac, vop_readl(vop_dev, WIN0_YRGB_MST),
2869                  vop_readl(vop_dev, WIN0_CBR_MST));
2870         strcat(buf, dsp_buf);
2871         memset(dsp_buf, 0, sizeof(dsp_buf));
2872
2873         /* win1 */
2874         size += snprintf(dsp_buf, 80,
2875                  "win1:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
2876                  w1_state, format_w1, w1_vir_y, w1_vir_uv);
2877         strcat(buf, dsp_buf);
2878         memset(dsp_buf, 0, sizeof(dsp_buf));
2879
2880         size += snprintf(dsp_buf, 80,
2881                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
2882                  w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
2883         strcat(buf, dsp_buf);
2884         memset(dsp_buf, 0, sizeof(dsp_buf));
2885
2886         size += snprintf(dsp_buf, 80,
2887                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
2888                  w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
2889         strcat(buf, dsp_buf);
2890         memset(dsp_buf, 0, sizeof(dsp_buf));
2891
2892         size += snprintf(dsp_buf, 80,
2893                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
2894                  w1_uv_h_fac, w1_uv_v_fac, vop_readl(vop_dev, WIN1_YRGB_MST),
2895                  vop_readl(vop_dev, WIN1_CBR_MST));
2896         strcat(buf, dsp_buf);
2897         memset(dsp_buf, 0, sizeof(dsp_buf));
2898
2899         return size;
2900 }
2901
2902 static int vop_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, bool set)
2903 {
2904         struct vop_device *vop_dev =
2905             container_of(dev_drv, struct vop_device, driver);
2906         struct rk_screen *screen = dev_drv->cur_screen;
2907         u64 ft = 0;
2908         u32 dotclk;
2909         int ret;
2910         u32 pixclock;
2911         u32 x_total, y_total;
2912
2913         if (set) {
2914                 if (fps == 0) {
2915                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
2916                         return 0;
2917                 }
2918                 ft = div_u64(1000000000000llu, fps);
2919                 x_total =
2920                     screen->mode.upper_margin + screen->mode.lower_margin +
2921                     screen->mode.yres + screen->mode.vsync_len;
2922                 y_total =
2923                     screen->mode.left_margin + screen->mode.right_margin +
2924                     screen->mode.xres + screen->mode.hsync_len;
2925                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
2926                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
2927                 ret = clk_set_rate(vop_dev->dclk, dotclk);
2928         }
2929
2930         pixclock = div_u64(1000000000000llu, clk_get_rate(vop_dev->dclk));
2931         vop_dev->pixclock = pixclock;
2932         dev_drv->pixclock = vop_dev->pixclock;
2933         fps = rk_fb_calc_fps(screen, pixclock);
2934         screen->ft = 1000 / fps;        /*one frame time in ms */
2935
2936         if (set)
2937                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
2938                          clk_get_rate(vop_dev->dclk), fps);
2939
2940         return fps;
2941 }
2942
2943 static int vop_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
2944 {
2945         mutex_lock(&dev_drv->fb_win_id_mutex);
2946         if (order == FB_DEFAULT_ORDER)
2947                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
2948         dev_drv->fb4_win_id = order / 10000;
2949         dev_drv->fb3_win_id = (order / 1000) % 10;
2950         dev_drv->fb2_win_id = (order / 100) % 10;
2951         dev_drv->fb1_win_id = (order / 10) % 10;
2952         dev_drv->fb0_win_id = order % 10;
2953         mutex_unlock(&dev_drv->fb_win_id_mutex);
2954
2955         return 0;
2956 }
2957
2958 static int vop_get_win_id(struct rk_lcdc_driver *dev_drv, const char *id)
2959 {
2960         int win_id = 0;
2961
2962         mutex_lock(&dev_drv->fb_win_id_mutex);
2963         if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
2964                 win_id = dev_drv->fb0_win_id;
2965         else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
2966                 win_id = dev_drv->fb1_win_id;
2967         else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
2968                 win_id = dev_drv->fb2_win_id;
2969         else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
2970                 win_id = dev_drv->fb3_win_id;
2971         else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
2972                 win_id = dev_drv->fb4_win_id;
2973         mutex_unlock(&dev_drv->fb_win_id_mutex);
2974
2975         return win_id;
2976 }
2977
2978 static int vop_config_done(struct rk_lcdc_driver *dev_drv)
2979 {
2980         struct vop_device *vop_dev =
2981             container_of(dev_drv, struct vop_device, driver);
2982         int i;
2983         u64 val;
2984         struct rk_lcdc_win *win = NULL;
2985
2986         spin_lock(&vop_dev->reg_lock);
2987         vop_post_cfg(dev_drv);
2988         vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(vop_dev->standby));
2989         for (i = 0; i < dev_drv->lcdc_win_num; i++) {
2990                 win = dev_drv->win[i];
2991                 if ((win->state == 0) && (win->last_state == 1)) {
2992                         switch (win->id) {
2993                         case 0:
2994                                 val = V_WIN0_EN(0);
2995                                 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
2996                                 break;
2997                         case 1:
2998                                 val = V_WIN1_EN(0);
2999                                 vop_msk_reg(vop_dev, WIN1_CTRL0, val);
3000                                 break;
3001                         case 2:
3002                                 val = V_HWC_EN(0);
3003                                 vop_msk_reg(vop_dev, HWC_CTRL0, val);
3004                                 break;
3005                         default:
3006                                 break;
3007                         }
3008                 }
3009                 win->last_state = win->state;
3010         }
3011         vop_cfg_done(vop_dev);
3012         spin_unlock(&vop_dev->reg_lock);
3013         return 0;
3014 }
3015
3016 static int vop_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3017 {
3018         struct vop_device *vop_dev =
3019             container_of(dev_drv, struct vop_device, driver);
3020         spin_lock(&vop_dev->reg_lock);
3021         vop_msk_reg(vop_dev, SYS_CTRL, V_DIRECT_PATH_EN(open));
3022         vop_cfg_done(vop_dev);
3023         spin_unlock(&vop_dev->reg_lock);
3024         return 0;
3025 }
3026
3027 static int vop_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3028 {
3029         struct vop_device *vop_dev = container_of(dev_drv,
3030                                                     struct vop_device, driver);
3031         spin_lock(&vop_dev->reg_lock);
3032         vop_msk_reg(vop_dev, SYS_CTRL, V_DIRECT_PATH_LAYER_SEL(win_id));
3033         vop_cfg_done(vop_dev);
3034         spin_unlock(&vop_dev->reg_lock);
3035         return 0;
3036 }
3037
3038 static int vop_dpi_status(struct rk_lcdc_driver *dev_drv)
3039 {
3040         struct vop_device *vop_dev =
3041             container_of(dev_drv, struct vop_device, driver);
3042         int ovl;
3043
3044         spin_lock(&vop_dev->reg_lock);
3045         ovl = vop_read_bit(vop_dev, SYS_CTRL, V_DIRECT_PATH_EN(0));
3046         spin_unlock(&vop_dev->reg_lock);
3047         return ovl;
3048 }
3049
3050 static int vop_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv, int enable)
3051 {
3052         struct vop_device *vop_dev =
3053                         container_of(dev_drv, struct vop_device, driver);
3054         if (enable)
3055                 enable_irq(vop_dev->irq);
3056         else
3057                 disable_irq(vop_dev->irq);
3058         return 0;
3059 }
3060
3061 int vop_poll_vblank(struct rk_lcdc_driver *dev_drv)
3062 {
3063         struct vop_device *vop_dev =
3064             container_of(dev_drv, struct vop_device, driver);
3065         u32 int_reg;
3066         int ret;
3067
3068         if (vop_dev->clk_on && (!dev_drv->suspend_flag)) {
3069                 int_reg = vop_readl(vop_dev, INTR_STATUS0);
3070                 if (int_reg & INTR_LINE_FLAG0) {
3071                         vop_dev->driver.frame_time.last_framedone_t =
3072                             vop_dev->driver.frame_time.framedone_t;
3073                         vop_dev->driver.frame_time.framedone_t = cpu_clock(0);
3074                         vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_LINE_FLAG0,
3075                                         INTR_LINE_FLAG0);
3076                         ret = RK_LF_STATUS_FC;
3077                 } else {
3078                         ret = RK_LF_STATUS_FR;
3079                 }
3080         } else {
3081                 ret = RK_LF_STATUS_NC;
3082         }
3083
3084         return ret;
3085 }
3086
3087 static int vop_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3088                             unsigned int dsp_addr[][4])
3089 {
3090         struct vop_device *vop_dev =
3091             container_of(dev_drv, struct vop_device, driver);
3092         spin_lock(&vop_dev->reg_lock);
3093         if (vop_dev->clk_on) {
3094                 dsp_addr[0][0] = vop_readl(vop_dev, WIN0_YRGB_MST);
3095                 dsp_addr[1][0] = vop_readl(vop_dev, WIN1_YRGB_MST);
3096                 dsp_addr[2][0] = vop_readl(vop_dev, HWC_MST);
3097         }
3098         spin_unlock(&vop_dev->reg_lock);
3099         return 0;
3100 }
3101
3102 static u32 pwm_period_hpr, pwm_duty_lpr;
3103
3104 int vop_update_pwm(int bl_pwm_period, int bl_pwm_duty)
3105 {
3106         pwm_period_hpr = bl_pwm_period;
3107         pwm_duty_lpr = bl_pwm_duty;
3108         /*pr_info("bl_pwm_period_hpr = 0x%x, bl_pwm_duty_lpr = 0x%x\n",
3109         bl_pwm_period, bl_pwm_duty);*/
3110         return 0;
3111 }
3112
3113 /*
3114         a:[-30~0]:
3115             sin_hue = sin(a)*256 +0x100;
3116             cos_hue = cos(a)*256;
3117         a:[0~30]
3118             sin_hue = sin(a)*256;
3119             cos_hue = cos(a)*256;
3120 */
3121 static int vop_get_bcsh_hue(struct rk_lcdc_driver *dev_drv, bcsh_hue_mode mode)
3122 {
3123 #if 1
3124         struct vop_device *vop_dev =
3125             container_of(dev_drv, struct vop_device, driver);
3126         u32 val;
3127
3128         spin_lock(&vop_dev->reg_lock);
3129         if (vop_dev->clk_on) {
3130                 val = vop_readl(vop_dev, BCSH_H);
3131                 switch (mode) {
3132                 case H_SIN:
3133                         val &= MASK(SIN_HUE);
3134                         break;
3135                 case H_COS:
3136                         val &= MASK(COS_HUE);
3137                         val >>= 16;
3138                         break;
3139                 default:
3140                         break;
3141                 }
3142         }
3143         spin_unlock(&vop_dev->reg_lock);
3144
3145         return val;
3146 #endif
3147         return 0;
3148 }
3149
3150 static int vop_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3151                             int sin_hue, int cos_hue)
3152 {
3153         struct vop_device *vop_dev =
3154             container_of(dev_drv, struct vop_device, driver);
3155         u64 val;
3156
3157         spin_lock(&vop_dev->reg_lock);
3158         if (vop_dev->clk_on) {
3159                 val = V_SIN_HUE(sin_hue) | V_COS_HUE(cos_hue);
3160                 vop_msk_reg(vop_dev, BCSH_H, val);
3161                 vop_cfg_done(vop_dev);
3162         }
3163         spin_unlock(&vop_dev->reg_lock);
3164
3165         return 0;
3166 }
3167
3168 static int vop_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
3169                             bcsh_bcs_mode mode, int value)
3170 {
3171         struct vop_device *vop_dev =
3172             container_of(dev_drv, struct vop_device, driver);
3173         u64 val;
3174
3175         spin_lock(&vop_dev->reg_lock);
3176         if (vop_dev->clk_on) {
3177                 switch (mode) {
3178                 case BRIGHTNESS:
3179                         /*from 0 to 255,typical is 128 */
3180                         if (value < 0x80)
3181                                 value += 0x80;
3182                         else if (value >= 0x80)
3183                                 value = value - 0x80;
3184                         val = V_BRIGHTNESS(value);
3185                         break;
3186                 case CONTRAST:
3187                         /*from 0 to 510,typical is 256 */
3188                         val = V_CONTRAST(value);
3189                         break;
3190                 case SAT_CON:
3191                         /*from 0 to 1015,typical is 256 */
3192                         val = V_SAT_CON(value);
3193                         break;
3194                 default:
3195                         break;
3196                 }
3197                 vop_msk_reg(vop_dev, BCSH_BCS, val);
3198                 vop_cfg_done(vop_dev);
3199         }
3200         spin_unlock(&vop_dev->reg_lock);
3201
3202         return val;
3203 }
3204
3205 static int vop_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv, bcsh_bcs_mode mode)
3206 {
3207         struct vop_device *vop_dev =
3208             container_of(dev_drv, struct vop_device, driver);
3209         u64 val;
3210
3211         spin_lock(&vop_dev->reg_lock);
3212         if (vop_dev->clk_on) {
3213                 val = vop_readl(vop_dev, BCSH_BCS);
3214                 switch (mode) {
3215                 case BRIGHTNESS:
3216                         val &= MASK(BRIGHTNESS);
3217                         if (val > 0x80)
3218                                 val -= 0x80;
3219                         else
3220                                 val += 0x80;
3221                         break;
3222                 case CONTRAST:
3223                         val &= MASK(CONTRAST);
3224                         val >>= 8;
3225                         break;
3226                 case SAT_CON:
3227                         val &= MASK(SAT_CON);
3228                         val >>= 20;
3229                         break;
3230                 default:
3231                         break;
3232                 }
3233         }
3234         spin_unlock(&vop_dev->reg_lock);
3235         return val;
3236 }
3237
3238 static int vop_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
3239 {
3240         struct vop_device *vop_dev =
3241             container_of(dev_drv, struct vop_device, driver);
3242
3243         spin_lock(&vop_dev->reg_lock);
3244         if (vop_dev->clk_on) {
3245                 if (open) {
3246                         vop_writel(vop_dev, BCSH_COLOR_BAR, 0x1);
3247                         vop_writel(vop_dev, BCSH_BCS, 0xd0010000);
3248                         vop_writel(vop_dev, BCSH_H, 0x01000000);
3249                         dev_drv->bcsh.enable = 1;
3250                 } else {
3251                         vop_msk_reg(vop_dev, BCSH_COLOR_BAR, V_BCSH_EN(0));
3252                         dev_drv->bcsh.enable = 0;
3253                 }
3254                 vop_bcsh_path_sel(dev_drv);
3255                 vop_cfg_done(vop_dev);
3256         }
3257         spin_unlock(&vop_dev->reg_lock);
3258
3259         return 0;
3260 }
3261
3262 static int vop_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
3263 {
3264         if (!enable || !dev_drv->bcsh.enable) {
3265                 vop_open_bcsh(dev_drv, false);
3266                 return 0;
3267         }
3268
3269         if (dev_drv->bcsh.brightness <= 255 ||
3270             dev_drv->bcsh.contrast <= 510 ||
3271             dev_drv->bcsh.sat_con <= 1015 ||
3272             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
3273                 vop_open_bcsh(dev_drv, true);
3274                 if (dev_drv->bcsh.brightness <= 255)
3275                         vop_set_bcsh_bcs(dev_drv, BRIGHTNESS,
3276                                          dev_drv->bcsh.brightness);
3277                 if (dev_drv->bcsh.contrast <= 510)
3278                         vop_set_bcsh_bcs(dev_drv, CONTRAST,
3279                                          dev_drv->bcsh.contrast);
3280                 if (dev_drv->bcsh.sat_con <= 1015)
3281                         vop_set_bcsh_bcs(dev_drv, SAT_CON,
3282                                          dev_drv->bcsh.sat_con);
3283                 if (dev_drv->bcsh.sin_hue <= 511 &&
3284                     dev_drv->bcsh.cos_hue <= 511)
3285                         vop_set_bcsh_hue(dev_drv, dev_drv->bcsh.sin_hue,
3286                                          dev_drv->bcsh.cos_hue);
3287         }
3288
3289         return 0;
3290 }
3291
3292 static int __maybe_unused
3293 vop_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
3294 {
3295         struct vop_device *vop_dev =
3296             container_of(dev_drv, struct vop_device, driver);
3297
3298         if (enable) {
3299                 spin_lock(&vop_dev->reg_lock);
3300                 if (likely(vop_dev->clk_on)) {
3301                         vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLACK_EN(1));
3302                         vop_cfg_done(vop_dev);
3303                 }
3304                 spin_unlock(&vop_dev->reg_lock);
3305         } else {
3306                 spin_lock(&vop_dev->reg_lock);
3307                 if (likely(vop_dev->clk_on)) {
3308                         vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLACK_EN(0));
3309
3310                         vop_cfg_done(vop_dev);
3311                 }
3312                 spin_unlock(&vop_dev->reg_lock);
3313         }
3314
3315         return 0;
3316 }
3317
3318 static int vop_backlight_close(struct rk_lcdc_driver *dev_drv, int enable)
3319 {
3320         struct vop_device *vop_dev =
3321             container_of(dev_drv, struct vop_device, driver);
3322
3323         if (unlikely(!vop_dev->clk_on)) {
3324                 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
3325                 return 0;
3326         }
3327         vop_get_backlight_device(dev_drv);
3328
3329         if (enable) {
3330                 /* close the backlight */
3331                 if (vop_dev->backlight) {
3332                         vop_dev->backlight->props.power = FB_BLANK_POWERDOWN;
3333                         backlight_update_status(vop_dev->backlight);
3334                 }
3335                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3336                         dev_drv->trsm_ops->disable();
3337         } else {
3338                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3339                         dev_drv->trsm_ops->enable();
3340                 msleep(100);
3341                 /* open the backlight */
3342                 if (vop_dev->backlight) {
3343                         vop_dev->backlight->props.power = FB_BLANK_UNBLANK;
3344                         backlight_update_status(vop_dev->backlight);
3345                 }
3346         }
3347
3348         return 0;
3349 }
3350
3351 static int vop_set_overscan(struct rk_lcdc_driver *dev_drv,
3352                             struct overscan *overscan)
3353 {
3354         struct vop_device *vop_dev =
3355             container_of(dev_drv, struct vop_device, driver);
3356
3357         if (unlikely(!vop_dev->clk_on)) {
3358                 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
3359                 return 0;
3360         }
3361         /*vop_post_cfg(dev_drv);*/
3362
3363         return 0;
3364 }
3365
3366 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
3367         .open = vop_open,
3368         .win_direct_en = vop_win_direct_en,
3369         .load_screen = vop_load_screen,
3370         .get_dspbuf_info = vop_get_dspbuf_info,
3371         .post_dspbuf = vop_post_dspbuf,
3372         .set_par = vop_set_par,
3373         .pan_display = vop_pan_display,
3374         .direct_set_addr = vop_direct_set_win_addr,
3375         /*.lcdc_reg_update = vop_reg_update,*/
3376         .blank = vop_blank,
3377         .ioctl = vop_ioctl,
3378         .suspend = vop_early_suspend,
3379         .resume = vop_early_resume,
3380         .get_win_state = vop_get_win_state,
3381         .area_support_num = vop_get_area_num,
3382         .ovl_mgr = vop_ovl_mgr,
3383         .get_disp_info = vop_get_disp_info,
3384         .fps_mgr = vop_fps_mgr,
3385         .fb_get_win_id = vop_get_win_id,
3386         .fb_win_remap = vop_fb_win_remap,
3387         .poll_vblank = vop_poll_vblank,
3388         .dpi_open = vop_dpi_open,
3389         .dpi_win_sel = vop_dpi_win_sel,
3390         .dpi_status = vop_dpi_status,
3391         .get_dsp_addr = vop_get_dsp_addr,
3392         .set_dsp_bcsh_hue = vop_set_bcsh_hue,
3393         .set_dsp_bcsh_bcs = vop_set_bcsh_bcs,
3394         .get_dsp_bcsh_hue = vop_get_bcsh_hue,
3395         .get_dsp_bcsh_bcs = vop_get_bcsh_bcs,
3396         .open_bcsh = vop_open_bcsh,
3397         .dump_reg = vop_reg_dump,
3398         .cfg_done = vop_config_done,
3399         .set_irq_to_cpu = vop_set_irq_to_cpu,
3400         /*.dsp_black = vop_dsp_black,*/
3401         .backlight_close = vop_backlight_close,
3402         .mmu_en    = vop_mmu_en,
3403         .set_overscan   = vop_set_overscan,
3404 };
3405
3406 static irqreturn_t vop_isr(int irq, void *dev_id)
3407 {
3408         struct vop_device *vop_dev = (struct vop_device *)dev_id;
3409         ktime_t timestamp = ktime_get();
3410         u32 intr_status;
3411         unsigned long flags;
3412
3413         spin_lock_irqsave(&vop_dev->irq_lock, flags);
3414
3415         intr_status = vop_readl(vop_dev, INTR_STATUS0);
3416         vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, intr_status);
3417
3418         spin_unlock_irqrestore(&vop_dev->irq_lock, flags);
3419         /* This is expected for vop iommu irqs, since the irq is shared */
3420         if (!intr_status)
3421                 return IRQ_NONE;
3422
3423         if (intr_status & INTR_FS) {
3424                 timestamp = ktime_get();
3425                 vop_dev->driver.vsync_info.timestamp = timestamp;
3426                 wake_up_interruptible_all(&vop_dev->driver.vsync_info.wait);
3427                 intr_status &= ~INTR_FS;
3428         }
3429
3430         if (intr_status & INTR_LINE_FLAG0)
3431                 intr_status &= ~INTR_LINE_FLAG0;
3432
3433         if (intr_status & INTR_LINE_FLAG1)
3434                 intr_status &= ~INTR_LINE_FLAG1;
3435
3436         if (intr_status & INTR_FS_NEW)
3437                 intr_status &= ~INTR_FS_NEW;
3438
3439         if (intr_status & INTR_BUS_ERROR) {
3440                 intr_status &= ~INTR_BUS_ERROR;
3441                 dev_warn_ratelimited(vop_dev->dev, "bus error!");
3442         }
3443
3444         if (intr_status & INTR_WIN0_EMPTY) {
3445                 intr_status &= ~INTR_WIN0_EMPTY;
3446                 dev_warn_ratelimited(vop_dev->dev, "intr win0 empty!");
3447         }
3448
3449         if (intr_status & INTR_WIN1_EMPTY) {
3450                 intr_status &= ~INTR_WIN1_EMPTY;
3451                 dev_warn_ratelimited(vop_dev->dev, "intr win1 empty!");
3452         }
3453
3454         if (intr_status & INTR_HWC_EMPTY) {
3455                 intr_status &= ~INTR_HWC_EMPTY;
3456                 dev_warn_ratelimited(vop_dev->dev, "intr hwc empty!");
3457         }
3458
3459         if (intr_status & INTR_POST_BUF_EMPTY) {
3460                 intr_status &= ~INTR_POST_BUF_EMPTY;
3461                 dev_warn_ratelimited(vop_dev->dev, "intr post buf empty!");
3462         }
3463
3464         if (intr_status)
3465                 dev_err(vop_dev->dev, "Unknown VOP IRQs: %#02x\n", intr_status);
3466
3467         return IRQ_HANDLED;
3468 }
3469
3470 #if defined(CONFIG_PM)
3471 static int vop_suspend(struct platform_device *pdev, pm_message_t state)
3472 {
3473         return 0;
3474 }
3475
3476 static int vop_resume(struct platform_device *pdev)
3477 {
3478         return 0;
3479 }
3480 #else
3481 #define vop_suspend NULL
3482 #define vop_resume  NULL
3483 #endif
3484
3485 static int vop_parse_dt(struct vop_device *vop_dev)
3486 {
3487         struct device_node *np = vop_dev->dev->of_node;
3488         struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
3489         int val;
3490
3491         if (of_property_read_u32(np, "rockchip,prop", &val))
3492                 vop_dev->prop = PRMRY;  /*default set it as primary */
3493         else
3494                 vop_dev->prop = val;
3495
3496         if (of_property_read_u32(np, "rockchip,mirror", &val))
3497                 dev_drv->rotate_mode = NO_MIRROR;
3498         else
3499                 dev_drv->rotate_mode = val;
3500
3501         if (of_property_read_u32(np, "rockchip,pwr18", &val))
3502                 /*default set it as 3.xv power supply */
3503                 vop_dev->pwr18 = false;
3504         else
3505                 vop_dev->pwr18 = (val ? true : false);
3506
3507         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
3508                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
3509         else
3510                 dev_drv->fb_win_map = val;
3511
3512         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
3513                 dev_drv->bcsh.enable = false;
3514         else
3515                 dev_drv->bcsh.enable = (val ? true : false);
3516
3517         if (of_property_read_u32(np, "rockchip,brightness", &val))
3518                 dev_drv->bcsh.brightness = 0xffff;
3519         else
3520                 dev_drv->bcsh.brightness = val;
3521
3522         if (of_property_read_u32(np, "rockchip,contrast", &val))
3523                 dev_drv->bcsh.contrast = 0xffff;
3524         else
3525                 dev_drv->bcsh.contrast = val;
3526
3527         if (of_property_read_u32(np, "rockchip,sat-con", &val))
3528                 dev_drv->bcsh.sat_con = 0xffff;
3529         else
3530                 dev_drv->bcsh.sat_con = val;
3531
3532         if (of_property_read_u32(np, "rockchip,hue", &val)) {
3533                 dev_drv->bcsh.sin_hue = 0xffff;
3534                 dev_drv->bcsh.cos_hue = 0xffff;
3535         } else {
3536                 dev_drv->bcsh.sin_hue = val & 0xff;
3537                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
3538         }
3539
3540 #if defined(CONFIG_ROCKCHIP_IOMMU)
3541         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
3542                 dev_drv->iommu_enabled = 0;
3543         else
3544                 dev_drv->iommu_enabled = val;
3545 #else
3546         dev_drv->iommu_enabled = 0;
3547 #endif
3548         return 0;
3549 }
3550
3551 static int vop_probe(struct platform_device *pdev)
3552 {
3553         struct vop_device *vop_dev = NULL;
3554         struct rk_lcdc_driver *dev_drv;
3555         struct device *dev = &pdev->dev;
3556         struct resource *res;
3557         struct device_node *np = pdev->dev.of_node;
3558         int prop;
3559         int ret = 0;
3560
3561         /* if the primary lcdc has not registered ,the extend
3562          * lcdc register later
3563          */
3564         of_property_read_u32(np, "rockchip,prop", &prop);
3565         if (prop == EXTEND) {
3566                 if (!is_prmry_rk_lcdc_registered())
3567                         return -EPROBE_DEFER;
3568         }
3569         vop_dev = devm_kzalloc(dev, sizeof(struct vop_device), GFP_KERNEL);
3570         if (!vop_dev)
3571                 return -ENOMEM;
3572
3573         platform_set_drvdata(pdev, vop_dev);
3574         vop_dev->dev = dev;
3575         vop_parse_dt(vop_dev);
3576         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3577         vop_dev->reg_phy_base = res->start;
3578         vop_dev->len = resource_size(res);
3579         vop_dev->regs = devm_ioremap_resource(dev, res);
3580         if (IS_ERR(vop_dev->regs))
3581                 return PTR_ERR(vop_dev->regs);
3582         else
3583                 dev_info(dev, "vop_dev->regs=0x%lx\n", (long)vop_dev->regs);
3584
3585         vop_dev->regsbak = devm_kzalloc(dev, vop_dev->len, GFP_KERNEL);
3586         if (IS_ERR(vop_dev->regsbak))
3587                 return PTR_ERR(vop_dev->regsbak);
3588
3589         vop_dev->id = 0;
3590         dev_set_name(vop_dev->dev, "vop%d", vop_dev->id);
3591         dev_drv = &vop_dev->driver;
3592         dev_drv->dev = dev;
3593         dev_drv->prop = prop;
3594         dev_drv->id = vop_dev->id;
3595         dev_drv->ops = &lcdc_drv_ops;
3596         dev_drv->lcdc_win_num = ARRAY_SIZE(vop_win);
3597         dev_drv->reserved_fb = 0;
3598         spin_lock_init(&vop_dev->reg_lock);
3599         spin_lock_init(&vop_dev->irq_lock);
3600
3601         vop_dev->irq = platform_get_irq(pdev, 0);
3602         if (vop_dev->irq < 0) {
3603                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
3604                         vop_dev->id);
3605                 return -ENXIO;
3606         }
3607
3608         ret = devm_request_irq(dev, vop_dev->irq, vop_isr,
3609                                IRQF_DISABLED | IRQF_SHARED,
3610                                dev_name(dev), vop_dev);
3611         if (ret) {
3612                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
3613                         vop_dev->irq, ret);
3614                 return ret;
3615         }
3616
3617         if (dev_drv->iommu_enabled)
3618                 strcpy(dev_drv->mmu_dts_name, VOP_IOMMU_COMPATIBLE_NAME);
3619
3620         ret = rk_fb_register(dev_drv, vop_win, vop_dev->id);
3621         if (ret < 0) {
3622                 dev_err(dev, "register fb for failed!\n");
3623                 return ret;
3624         }
3625         vop_dev->screen = dev_drv->screen0;
3626         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
3627                  vop_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
3628
3629         return 0;
3630 }
3631
3632 static int vop_remove(struct platform_device *pdev)
3633 {
3634         return 0;
3635 }
3636
3637 static void vop_shutdown(struct platform_device *pdev)
3638 {
3639         struct vop_device *vop_dev = platform_get_drvdata(pdev);
3640         struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
3641
3642         dev_drv->suspend_flag = 1;
3643         mdelay(100);
3644         flush_kthread_worker(&dev_drv->update_regs_worker);
3645         kthread_stop(dev_drv->update_regs_thread);
3646         vop_deint(vop_dev);
3647         /*if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3648                 dev_drv->trsm_ops->disable();*/
3649
3650         vop_clk_disable(vop_dev);
3651         rk_disp_pwr_disable(dev_drv);
3652 }
3653
3654 #if defined(CONFIG_OF)
3655 static const struct of_device_id vop_dt_ids[] = {
3656         {.compatible = "rockchip,rk322x-lcdc",},
3657         {}
3658 };
3659 #endif
3660
3661 static struct platform_driver vop_driver = {
3662         .probe = vop_probe,
3663         .remove = vop_remove,
3664         .driver = {
3665                    .name = "rk322x-lcdc",
3666                    .owner = THIS_MODULE,
3667                    .of_match_table = of_match_ptr(vop_dt_ids),
3668                    },
3669         .suspend = vop_suspend,
3670         .resume = vop_resume,
3671         .shutdown = vop_shutdown,
3672 };
3673
3674 static int __init vop_module_init(void)
3675 {
3676         return platform_driver_register(&vop_driver);
3677 }
3678
3679 static void __exit vop_module_exit(void)
3680 {
3681         platform_driver_unregister(&vop_driver);
3682 }
3683
3684 fs_initcall(vop_module_init);
3685 module_exit(vop_module_exit);