drivers/video/rockchip/lcdc/rk322x_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk322x_lcdc.c
   3  *
   4  * Copyright (C) 2015 ROCKCHIP, Inc.
   5  * Author: Mark Yao <mark.yao@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/of_device.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <linux/rockchip-iovmm.h>
  31 #include <asm/div64.h>
  32 #include <linux/uaccess.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk322x_lcdc.h"
  39
  40 /*#define CONFIG_RK_FPGA 1*/
  41 #define VOP_CHIP(dev)   (dev->data->chip_type)
  42
  43 static int dbg_thresd;
  44 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  45
  46 #define DBG(level, x...) do {                   \
  47         if (unlikely(dbg_thresd >= level))      \
  48                 pr_info(x);\
  49         } while (0)
  50
  51 static struct rk_lcdc_win rk322x_vop_win[] = {
  52         { .name = "win0",
  53           .id = VOP_WIN0,
  54           .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
  55                                 SUPPORT_SCALE | SUPPORT_YUV |
  56                                 SUPPORT_YUV10BIT,
  57           .property.max_input_x = 4096,
  58           .property.max_input_y = 2304},
  59         { .name = "win1",
  60           .id = VOP_WIN1,
  61           .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
  62                                 SUPPORT_SCALE | SUPPORT_YUV |
  63                                 SUPPORT_YUV10BIT,
  64           .property.max_input_x = 4096,
  65           .property.max_input_y = 2304},
  66         {
  67           .name = "hwc",
  68           .id = VOP_HWC,
  69           .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
  70                                 SUPPORT_HWC_LAYER,
  71           .property.max_input_x = 128,
  72           .property.max_input_y = 128
  73         }
  74 };
  75
  76 static struct rk_lcdc_win rk3399_vop_win[] = {
  77         { .name = "win0",
  78           .id = VOP_WIN0,
  79           .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
  80                                 SUPPORT_SCALE | SUPPORT_YUV |
  81                                 SUPPORT_YUV10BIT,
  82           .property.max_input_x = 4096,
  83           .property.max_input_y = 2304},
  84         { .name = "win1",
  85           .id = VOP_WIN1,
  86           .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
  87                                 SUPPORT_SCALE | SUPPORT_YUV |
  88                                 SUPPORT_YUV10BIT,
  89           .property.max_input_x = 4096,
  90           .property.max_input_y = 2304},
  91         { .name = "win2",
  92           .id = VOP_WIN2,
  93           .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
  94                                 SUPPORT_MULTI_AREA,
  95           .property.max_input_x = 4096,
  96           .property.max_input_y = 2304},
  97         { .name = "win3",
  98           .id = VOP_WIN3,
  99           .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
 100                                 SUPPORT_MULTI_AREA,
 101           .property.max_input_x = 4096,
 102           .property.max_input_y = 2304},
 103         {
 104           .name = "hwc",
 105           .id = VOP_HWC,
 106           .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
 107                                 SUPPORT_HWC_LAYER,
 108           .property.max_input_x = 128,
 109           .property.max_input_y = 128
 110         }
 111 };
 112
 113 static const struct vop_data rk322x_data = {
 114         .chip_type = VOP_RK322X,
 115         .win = rk322x_vop_win,
 116         .n_wins = ARRAY_SIZE(rk322x_vop_win),
 117 };
 118
 119 static const struct vop_data rk3399_data = {
 120         .chip_type = VOP_RK3399,
 121         .win = rk3399_vop_win,
 122         .n_wins = ARRAY_SIZE(rk3399_vop_win),
 123 };
 124
 125 #if defined(CONFIG_OF)
 126 static const struct of_device_id vop_dt_ids[] = {
 127         {.compatible = "rockchip,rk322x-lcdc",
 128          .data = &rk322x_data, },
 129         {.compatible = "rockchip,rk3399-lcdc",
 130          .data = &rk3399_data, },
 131         {}
 132 };
 133 #endif
 134
 135 static const u32 csc_y2r_bt601_limit[12] = {
 136         0x04a8,      0,  0x0662, 0xfffc8654,
 137         0x04a8, 0xfe6f,  0xfcbf, 0x00022056,
 138         0x04a8, 0x0812,       0, 0xfffbaeac,
 139 };
 140
 141 static const u32 csc_y2r_bt709_full[12] = {
 142         0x04a8,      0,  0x072c, 0xfffc219e,
 143         0x04a8, 0xff26,  0xfdde, 0x0001357b,
 144         0x04a8, 0x0873,       0, 0xfffb7dee,
 145 };
 146
 147 static const u32 csc_y2r_bt601_full[12] = {
 148         0x0400,      0,  0x059c, 0xfffd342d,
 149         0x0400, 0xfea0,  0xfd25, 0x00021fcc,
 150         0x0400, 0x0717,       0, 0xfffc76bc,
 151 };
 152
 153 static const u32 csc_y2r_bt601_limit_10[12] = {
 154         0x04a8,      0,  0x0662, 0xfff2134e,
 155         0x04a8, 0xfe6f,  0xfcbf, 0x00087b58,
 156         0x04a8, 0x0812,       0, 0xffeeb4b0,
 157 };
 158
 159 static const u32 csc_y2r_bt709_full_10[12] = {
 160         0x04a8,      0,  0x072c, 0xfff08077,
 161         0x04a8, 0xff26,  0xfdde, 0x0004cfed,
 162         0x04a8, 0x0873,       0, 0xffedf1b8,
 163 };
 164
 165 static const u32 csc_y2r_bt601_full_10[12] = {
 166         0x0400,      0,  0x059c, 0xfff4cab4,
 167         0x0400, 0xfea0,  0xfd25, 0x00087932,
 168         0x0400, 0x0717,       0, 0xfff1d4f2,
 169 };
 170
 171 static const u32 csc_y2r_bt2020[12] = {
 172         0x04a8,      0, 0x06b6, 0xfff16bfc,
 173         0x04a8, 0xff40, 0xfd66, 0x58ae9,
 174         0x04a8, 0x0890,      0, 0xffedb828,
 175 };
 176
 177 static const u32 csc_r2y_bt601_limit[12] = {
 178         0x0107, 0x0204, 0x0064, 0x04200,
 179         0xff68, 0xfed6, 0x01c2, 0x20200,
 180         0x01c2, 0xfe87, 0xffb7, 0x20200,
 181 };
 182
 183 static const u32 csc_r2y_bt709_full[12] = {
 184         0x00bb, 0x0275, 0x003f, 0x04200,
 185         0xff99, 0xfea5, 0x01c2, 0x20200,
 186         0x01c2, 0xfe68, 0xffd7, 0x20200,
 187 };
 188
 189 static const u32 csc_r2y_bt601_full[12] = {
 190         0x0132, 0x0259, 0x0075, 0x200,
 191         0xff53, 0xfead, 0x0200, 0x20200,
 192         0x0200, 0xfe53, 0xffad, 0x20200,
 193 };
 194
 195 static const u32 csc_r2y_bt601_limit_10[12] = {
 196         0x0107, 0x0204, 0x0064, 0x10200,
 197         0xff68, 0xfed6, 0x01c2, 0x80200,
 198         0x01c2, 0xfe87, 0xffb7, 0x80200,
 199 };
 200
 201 static const u32 csc_r2y_bt709_full_10[12] = {
 202         0x00bb, 0x0275, 0x003f, 0x10200,
 203         0xff99, 0xfea5, 0x01c2, 0x80200,
 204         0x01c2, 0xfe68, 0xffd7, 0x80200,
 205 };
 206
 207 static const u32 csc_r2y_bt601_full_10[12] = {
 208         0x0132, 0x0259, 0x0075, 0x200,
 209         0xff53, 0xfead, 0x0200, 0x80200,
 210         0x0200, 0xfe53, 0xffad, 0x80200,
 211 };
 212
 213 static const u32 csc_r2y_bt2020[12] = {
 214         0x00e6, 0x0253, 0x0034, 0x10200,
 215         0xff83, 0xfebd, 0x01c1, 0x80200,
 216         0x01c1, 0xfe64, 0xffdc, 0x80200,
 217 };
 218
 219 static const u32 csc_r2r_bt2020to709[12] = {
 220         0x06a4, 0xfda6, 0xffb5, 0x200,
 221         0xff80, 0x0488, 0xfff8, 0x200,
 222         0xffed, 0xff99, 0x047a, 0x200,
 223 };
 224
 225 static const u32 csc_r2r_bt709to2020[12] = {
 226         0x282, 0x151, 0x02c, 0x200,
 227         0x047, 0x3ae, 0x00c, 0x200,
 228         0x011, 0x05a, 0x395, 0x200,
 229 };
 230
 231 static int vop_get_id(struct vop_device *vop_dev, u32 phy_base)
 232 {
 233         if (VOP_CHIP(vop_dev) == VOP_RK3399) {
 234                 if (phy_base == 0xff900000) /* vop big */
 235                         return 0;
 236                 else if (phy_base == 0xff8f0000) /* vop lit */
 237                         return 1;
 238                 else
 239                         return -EINVAL;
 240         } else {
 241                 return 0;
 242         }
 243 }
 244
 245 static void vop_load_csc_table(struct vop_device *vop_dev, u32 offset,
 246                                const u32 *table)
 247 {
 248         u32 csc_val;
 249
 250         csc_val = table[1] << 16 | table[0];
 251         vop_writel(vop_dev, offset, csc_val);
 252         csc_val = table[4] << 16 | table[2];
 253         vop_writel(vop_dev, offset + 4, csc_val);
 254         csc_val = table[6] << 16 | table[5];
 255         vop_writel(vop_dev, offset + 8, csc_val);
 256         csc_val = table[9] << 16 | table[8];
 257         vop_writel(vop_dev, offset + 0xc, csc_val);
 258         csc_val = table[10];
 259         vop_writel(vop_dev, offset + 0x10, csc_val);
 260         csc_val = table[3];
 261         vop_writel(vop_dev, offset + 0x14, csc_val);
 262         csc_val = table[7];
 263         vop_writel(vop_dev, offset + 0x18, csc_val);
 264         csc_val = table[11];
 265         vop_writel(vop_dev, offset + 0x1c, csc_val);
 266 }
 267
 268 #define LOAD_CSC(dev, mode, table, win_id) \
 269                 vop_load_csc_table(dev, \
 270                                    WIN0_YUV2YUV_##mode + 0x60 * win_id, \
 271                                    table)
 272
 273 static int vop_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
 274
 275 static int vop_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
 276 {
 277         struct vop_device *vop_dev =
 278                         container_of(dev_drv, struct vop_device, driver);
 279         int i, j;
 280
 281         if (!vop_dev->dsp_lut_addr_base) {
 282                 dev_warn(vop_dev->dev, "not support dsp lut config\n");
 283                 return 0;
 284         }
 285
 286         if (!dsp_lut) {
 287                 dev_err(vop_dev->dev, "dsp lut table is null\n");
 288                 return -EINVAL;
 289         }
 290
 291         spin_lock(&vop_dev->reg_lock);
 292         for (i = 0; i < 256; i++) {
 293                 u32 v, r, g, b;
 294                 int __iomem *c;
 295
 296                 v = dsp_lut[i];
 297                 c = vop_dev->dsp_lut_addr_base + (i << 2);
 298                 b = (v & 0xff) << 2;
 299                 g = (v & 0xff00) << 4;
 300                 r = (v & 0xff0000) << 6;
 301                 v = r + g + b;
 302                 for (j = 0; j < 4; j++) {
 303                         writel_relaxed(v, c);
 304                         v += (1 + (1 << 10) + (1 << 20));
 305                         c++;
 306                 }
 307         }
 308         vop_msk_reg(vop_dev, DSP_CTRL1, V_DSP_LUT_EN(1));
 309         /*
 310          * update_gamma value auto clean to 0 by HW, should not
 311          * bakeup it.
 312          */
 313         vop_msk_reg_nobak(vop_dev, DSP_CTRL1, V_UPDATE_GAMMA_LUT(1));
 314
 315         vop_cfg_done(vop_dev);
 316         spin_unlock(&vop_dev->reg_lock);
 317
 318         return 0;
 319 }
 320
 321 static int vop_set_cabc(struct rk_lcdc_driver *dev_drv, int *cabc_lut)
 322 {
 323         struct vop_device *vop_dev =
 324                         container_of(dev_drv, struct vop_device, driver);
 325         int i;
 326
 327         if (!vop_dev->cabc_lut_addr_base) {
 328                 dev_warn(vop_dev->dev, "not support cabc config\n");
 329                 return 0;
 330         }
 331
 332         if (!cabc_lut) {
 333                 dev_err(vop_dev->dev, "cabc lut table is null\n");
 334                 return -EINVAL;
 335         }
 336         spin_lock(&vop_dev->reg_lock);
 337         vop_msk_reg(vop_dev, CABC_CTRL1, V_CABC_LUT_EN(0));
 338         vop_cfg_done(vop_dev);
 339         spin_unlock(&vop_dev->reg_lock);
 340
 341         mdelay(25);
 342
 343         spin_lock(&vop_dev->reg_lock);
 344         for (i = 0; i < 128; i++) {
 345                 u32 v;
 346
 347                 v = cabc_lut[i];
 348
 349                 writel_relaxed(v, vop_dev->cabc_lut_addr_base + i);
 350         }
 351         vop_msk_reg(vop_dev, CABC_CTRL1, V_CABC_LUT_EN(1));
 352         spin_unlock(&vop_dev->reg_lock);
 353
 354         return 0;
 355 }
 356
 357 static int vop_clk_enable(struct vop_device *vop_dev)
 358 {
 359         if (!vop_dev->clk_on) {
 360                 clk_prepare_enable(vop_dev->hclk);
 361                 clk_prepare_enable(vop_dev->dclk);
 362                 clk_prepare_enable(vop_dev->aclk);
 363                 if (vop_dev->hclk_noc)
 364                         clk_prepare_enable(vop_dev->hclk_noc);
 365                 if (vop_dev->aclk_noc)
 366                         clk_prepare_enable(vop_dev->aclk_noc);
 367 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
 368                 pm_runtime_get_sync(vop_dev->dev);
 369 #endif
 370                 spin_lock(&vop_dev->reg_lock);
 371                 vop_dev->clk_on = 1;
 372                 spin_unlock(&vop_dev->reg_lock);
 373         }
 374
 375         return 0;
 376 }
 377
 378 static int vop_clk_disable(struct vop_device *vop_dev)
 379 {
 380         if (vop_dev->clk_on) {
 381                 spin_lock(&vop_dev->reg_lock);
 382                 vop_dev->clk_on = 0;
 383                 spin_unlock(&vop_dev->reg_lock);
 384                 mdelay(25);
 385 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
 386                 pm_runtime_put(vop_dev->dev);
 387 #endif
 388                 clk_disable_unprepare(vop_dev->dclk);
 389                 clk_disable_unprepare(vop_dev->hclk);
 390                 clk_disable_unprepare(vop_dev->aclk);
 391                 if (vop_dev->hclk_noc)
 392                         clk_disable_unprepare(vop_dev->hclk_noc);
 393                 if (vop_dev->aclk_noc)
 394                         clk_disable_unprepare(vop_dev->aclk_noc);
 395         }
 396
 397         return 0;
 398 }
 399
 400 static int __maybe_unused vop_disable_irq(struct vop_device *vop_dev)
 401 {
 402         if (likely(vop_dev->clk_on)) {
 403                 spin_lock(&vop_dev->reg_lock);
 404                 vop_writel(vop_dev, INTR_EN0, 0xffff0000);
 405                 vop_writel(vop_dev, INTR_EN1, 0xffff0000);
 406                 vop_writel(vop_dev, INTR_CLEAR0, 0xffffffff);
 407                 vop_writel(vop_dev, INTR_CLEAR1, 0xffffffff);
 408                 vop_cfg_done(vop_dev);
 409                 spin_unlock(&vop_dev->reg_lock);
 410         };
 411
 412         return 0;
 413 }
 414
 415 static int vop_reg_dump(struct rk_lcdc_driver *dev_drv)
 416 {
 417         struct vop_device *vop_dev =
 418             container_of(dev_drv, struct vop_device, driver);
 419         int *cbase = (int *)vop_dev->regs;
 420         int *regsbak = (int *)vop_dev->regsbak;
 421         int i, j, val;
 422         char dbg_message[30];
 423         char buf[10];
 424
 425         pr_info("lcd back up reg:\n");
 426         memset(dbg_message, 0, sizeof(dbg_message));
 427         memset(buf, 0, sizeof(buf));
 428         for (i = 0; i <= (0x200 >> 4); i++) {
 429                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 430                 for (j = 0; j < 4; j++) {
 431                         val = sprintf(buf, "%08x  ", *(regsbak + i * 4 + j));
 432                         strcat(dbg_message, buf);
 433                 }
 434                 pr_info("%s\n", dbg_message);
 435                 memset(dbg_message, 0, sizeof(dbg_message));
 436                 memset(buf, 0, sizeof(buf));
 437         }
 438
 439         pr_info("lcdc reg:\n");
 440         for (i = 0; i <= (0x200 >> 4); i++) {
 441                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 442                 for (j = 0; j < 4; j++) {
 443                         sprintf(buf, "%08x  ",
 444                                 readl_relaxed(cbase + i * 4 + j));
 445                         strcat(dbg_message, buf);
 446                 }
 447                 pr_info("%s\n", dbg_message);
 448                 memset(dbg_message, 0, sizeof(dbg_message));
 449                 memset(buf, 0, sizeof(buf));
 450         }
 451
 452         return 0;
 453 }
 454
 455 #define WIN_EN(id)              \
 456 static int win##id##_enable(struct vop_device *vop_dev, int en) \
 457 { \
 458         spin_lock(&vop_dev->reg_lock);                                  \
 459         vop_msk_reg(vop_dev, WIN##id##_CTRL0, V_WIN##id##_EN((u64)en)); \
 460         vop_cfg_done(vop_dev);                                          \
 461         spin_unlock(&vop_dev->reg_lock);                                \
 462         return 0;                                                       \
 463 }
 464
 465 WIN_EN(0);
 466 WIN_EN(1);
 467 WIN_EN(2);
 468 WIN_EN(3);
 469
 470 /*enable/disable win directly*/
 471 static int vop_win_direct_en(struct rk_lcdc_driver *drv,
 472                              int win_id, int en)
 473 {
 474         struct vop_device *vop_dev =
 475             container_of(drv, struct vop_device, driver);
 476
 477         drv->win[win_id]->state = en;
 478         if (win_id == 0)
 479                 win0_enable(vop_dev, en);
 480         else if (win_id == 1)
 481                 win1_enable(vop_dev, en);
 482         else if (win_id == 2)
 483                 win2_enable(vop_dev, en);
 484         else if (win_id == 3)
 485                 win3_enable(vop_dev, en);
 486         else
 487                 dev_err(vop_dev->dev, "invalid win number:%d\n", win_id);
 488         return 0;
 489 }
 490
 491 #define SET_WIN_ADDR(id) \
 492 static int set_win##id##_addr(struct vop_device *vop_dev, u32 addr) \
 493 {                                                       \
 494         spin_lock(&vop_dev->reg_lock);                  \
 495         vop_writel(vop_dev, WIN##id##_YRGB_MST, addr);  \
 496         vop_msk_reg(vop_dev, WIN##id##_CTRL0, V_WIN##id##_EN(1));       \
 497         vop_cfg_done(vop_dev);                  \
 498         spin_unlock(&vop_dev->reg_lock);                \
 499         return 0;                                       \
 500 }
 501
 502 SET_WIN_ADDR(0);
 503 SET_WIN_ADDR(1);
 504 int vop_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
 505                             int win_id, u32 addr)
 506 {
 507         struct vop_device *vop_dev =
 508             container_of(dev_drv, struct vop_device, driver);
 509         if (win_id == 0)
 510                 set_win0_addr(vop_dev, addr);
 511         else
 512                 set_win1_addr(vop_dev, addr);
 513
 514         return 0;
 515 }
 516
 517 static void lcdc_read_reg_defalut_cfg(struct vop_device *vop_dev)
 518 {
 519         int reg = 0;
 520         u32 val = 0;
 521         struct rk_screen *screen = vop_dev->driver.cur_screen;
 522         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 523         u32 V_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 524         u32 st_x, st_y;
 525         struct rk_lcdc_win *win0 = vop_dev->driver.win[0];
 526
 527         spin_lock(&vop_dev->reg_lock);
 528         for (reg = 0; reg < vop_dev->len; reg += 4) {
 529                 val = vop_readl_backup(vop_dev, reg);
 530                 switch (reg) {
 531                 case WIN0_ACT_INFO:
 532                         win0->area[0].xact = (val & MASK(WIN0_ACT_WIDTH)) + 1;
 533                         win0->area[0].yact =
 534                                 ((val & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1;
 535                         break;
 536                 case WIN0_DSP_INFO:
 537                         win0->area[0].xsize = (val & MASK(WIN0_DSP_WIDTH)) + 1;
 538                         win0->area[0].ysize =
 539                             ((val & MASK(WIN0_DSP_HEIGHT)) >> 16) + 1;
 540                         break;
 541                 case WIN0_DSP_ST:
 542                         st_x = val & MASK(WIN0_DSP_XST);
 543                         st_y = (val & MASK(WIN0_DSP_YST)) >> 16;
 544                         win0->area[0].xpos = st_x - h_pw_bp;
 545                         win0->area[0].ypos = st_y - V_pw_bp;
 546                         break;
 547                 case WIN0_CTRL0:
 548                         win0->state = val & MASK(WIN0_EN);
 549                         win0->area[0].fmt_cfg =
 550                                         (val & MASK(WIN0_DATA_FMT)) >> 1;
 551                         win0->fmt_10 = (val & MASK(WIN0_FMT_10)) >> 4;
 552                         win0->area[0].format = win0->area[0].fmt_cfg;
 553                         break;
 554                 case WIN0_VIR:
 555                         win0->area[0].y_vir_stride =
 556                                         val & MASK(WIN0_VIR_STRIDE);
 557                         win0->area[0].uv_vir_stride =
 558                             (val & MASK(WIN0_VIR_STRIDE_UV)) >> 16;
 559                         if (win0->area[0].format == ARGB888)
 560                                 win0->area[0].xvir = win0->area[0].y_vir_stride;
 561                         else if (win0->area[0].format == RGB888)
 562                                 win0->area[0].xvir =
 563                                     win0->area[0].y_vir_stride * 4 / 3;
 564                         else if (win0->area[0].format == RGB565)
 565                                 win0->area[0].xvir =
 566                                     2 * win0->area[0].y_vir_stride;
 567                         else
 568                                 win0->area[0].xvir =
 569                                     4 * win0->area[0].y_vir_stride;
 570                         break;
 571                 case WIN0_YRGB_MST:
 572                         win0->area[0].smem_start = val;
 573                         break;
 574                 case WIN0_CBR_MST:
 575                         win0->area[0].cbr_start = val;
 576                         break;
 577                 default:
 578                         break;
 579                 }
 580         }
 581         spin_unlock(&vop_dev->reg_lock);
 582 }
 583
 584 /********do basic init*********/
 585 static int vop_pre_init(struct rk_lcdc_driver *dev_drv)
 586 {
 587         struct vop_device *vop_dev =
 588             container_of(dev_drv, struct vop_device, driver);
 589         if (vop_dev->pre_init)
 590                 return 0;
 591         vop_dev->hclk = devm_clk_get(vop_dev->dev, "hclk_lcdc");
 592         vop_dev->aclk = devm_clk_get(vop_dev->dev, "aclk_lcdc");
 593         vop_dev->dclk = devm_clk_get(vop_dev->dev, "dclk_lcdc");
 594         if (IS_ERR(vop_dev->aclk) || IS_ERR(vop_dev->dclk) ||
 595             IS_ERR(vop_dev->hclk))
 596                 dev_err(vop_dev->dev, "failed to get clk source\n");
 597         vop_dev->hclk_noc = devm_clk_get(vop_dev->dev, "hclk_vop_noc");
 598         if (IS_ERR(vop_dev->hclk_noc)) {
 599                 vop_dev->hclk_noc = NULL;
 600                 dev_err(vop_dev->dev, "failed to get clk source\n");
 601         }
 602         vop_dev->aclk_noc = devm_clk_get(vop_dev->dev, "aclk_vop_noc");
 603         if (IS_ERR(vop_dev->aclk_noc)) {
 604                 vop_dev->aclk_noc = NULL;
 605                 dev_err(vop_dev->dev, "failed to get clk source\n");
 606         }
 607         if (!support_uboot_display())
 608                 rk_disp_pwr_enable(dev_drv);
 609         vop_clk_enable(vop_dev);
 610
 611         memcpy(vop_dev->regsbak, vop_dev->regs, vop_dev->len);
 612         /*backup reg config at uboot */
 613         lcdc_read_reg_defalut_cfg(vop_dev);
 614         #ifndef CONFIG_RK_FPGA
 615         /*
 616          * Todo, not verified
 617          *
 618         if (vop_dev->pwr18 == 1) {
 619                 v = 0x00200020;
 620                 vop_grf_writel(vop_dev->pmugrf_base,
 621                                 PMUGRF_SOC_CON0_VOP, v);
 622         } else {
 623                 v = 0x00200000;
 624                 vop_grf_writel(vop_dev->pmugrf_base,
 625                                 PMUGRF_SOC_CON0_VOP, v);
 626         }
 627         */
 628         #endif
 629         vop_writel(vop_dev, FRC_LOWER01_0, 0x12844821);
 630         vop_writel(vop_dev, FRC_LOWER01_1, 0x21488412);
 631         vop_writel(vop_dev, FRC_LOWER10_0, 0xa55a9696);
 632         vop_writel(vop_dev, FRC_LOWER10_1, 0x5aa56969);
 633         vop_writel(vop_dev, FRC_LOWER11_0, 0xdeb77deb);
 634         vop_writel(vop_dev, FRC_LOWER11_1, 0xed7bb7de);
 635
 636         vop_msk_reg(vop_dev, SYS_CTRL, V_AUTO_GATING_EN(1));
 637         vop_msk_reg(vop_dev, DSP_CTRL1, V_DITHER_UP_EN(1));
 638         vop_cfg_done(vop_dev);
 639         vop_dev->pre_init = true;
 640
 641         return 0;
 642 }
 643
 644 static void vop_deint(struct vop_device *vop_dev)
 645 {
 646         if (vop_dev->clk_on) {
 647                 u64 val;
 648
 649                 vop_disable_irq(vop_dev);
 650                 spin_lock(&vop_dev->reg_lock);
 651                 vop_msk_reg(vop_dev, WIN0_CTRL0, V_WIN0_EN(0));
 652                 vop_msk_reg(vop_dev, WIN1_CTRL0, V_WIN0_EN(0));
 653
 654                 val = V_WIN2_EN(0) | V_WIN2_MST0_EN(0) | V_WIN2_MST1_EN(0) |
 655                         V_WIN2_MST2_EN(0) | V_WIN2_MST3_EN(0);
 656                 vop_msk_reg(vop_dev, WIN2_CTRL0, val);
 657                 vop_msk_reg(vop_dev, WIN3_CTRL0, val);
 658                 vop_cfg_done(vop_dev);
 659                 spin_unlock(&vop_dev->reg_lock);
 660                 mdelay(50);
 661         }
 662 }
 663
 664 static void vop_win_csc_mode(struct vop_device *vop_dev,
 665                              struct rk_lcdc_win *win,
 666                              int csc_mode)
 667 {
 668         u64 val;
 669
 670         if (win->id == VOP_WIN0) {
 671                 val = V_WIN0_CSC_MODE(csc_mode);
 672                 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
 673         } else if (win->id == VOP_WIN1) {
 674                 val = V_WIN1_CSC_MODE(csc_mode);
 675                 vop_msk_reg(vop_dev, WIN1_CTRL0, val);
 676         } else {
 677                 val = V_HWC_CSC_MODE(csc_mode);
 678                 vop_msk_reg(vop_dev, HWC_CTRL0, val);
 679         }
 680 }
 681
 682 static int rk3399_vop_win_csc_cfg(struct rk_lcdc_driver *dev_drv)
 683 {
 684         struct vop_device *vop_dev =
 685             container_of(dev_drv, struct vop_device, driver);
 686         int output_color = dev_drv->output_color;
 687         int i;
 688
 689         for (i = 0; i < dev_drv->lcdc_win_num && i <= 4; i++) {
 690                 struct rk_lcdc_win *win = dev_drv->win[i];
 691                 int shift = i * 8;
 692                 u64 val = V_WIN0_YUV2YUV_EN(0) | V_WIN0_YUV2YUV_R2Y_EN(0) |
 693                                 V_WIN0_YUV2YUV_Y2R_EN(0);
 694
 695                 if (!win->state)
 696                         continue;
 697                 if (output_color == COLOR_RGB &&
 698                     !(IS_YUV(win->area[0].fmt_cfg) || win->area[0].yuyv_fmt))
 699                         goto post;
 700
 701                 if (output_color == COLOR_RGB) {
 702                         val |= V_WIN0_YUV2YUV_Y2R_EN(1);
 703                         if (win->colorspace == CSC_BT601) {
 704                                 /*
 705                                  * Win Y2Y moudle always use 10bit mode.
 706                                  */
 707                                 LOAD_CSC(vop_dev, Y2R,
 708                                          csc_y2r_bt601_full_10, i);
 709                         } else if (win->colorspace == CSC_BT709) {
 710                                 LOAD_CSC(vop_dev, Y2R,
 711                                          csc_y2r_bt709_full_10, i);
 712                         } else if (win->colorspace == CSC_BT2020) {
 713                                 val |= V_WIN0_YUV2YUV_EN(1);
 714                                 LOAD_CSC(vop_dev, Y2R, csc_y2r_bt2020, i);
 715                                 LOAD_CSC(vop_dev, R2R, csc_r2r_bt2020to709, i);
 716                         }
 717                 } else if (output_color == COLOR_YCBCR ||
 718                                 output_color == COLOR_YCBCR_BT709) {
 719                         if (!(IS_YUV(win->area[0].fmt_cfg) ||
 720                               win->area[0].yuyv_fmt)) {
 721                                 val |= V_WIN0_YUV2YUV_R2Y_EN(1);
 722                                 LOAD_CSC(vop_dev, R2Y, csc_r2y_bt709_full_10, i);
 723                         } else if (win->colorspace == CSC_BT2020) {
 724                                 val |= V_WIN0_YUV2YUV_EN(1) |
 725                                         V_WIN0_YUV2YUV_Y2R_EN(1) |
 726                                         V_WIN0_YUV2YUV_R2Y_EN(1);
 727                                 LOAD_CSC(vop_dev, Y2R, csc_y2r_bt2020, i);
 728                                 LOAD_CSC(vop_dev, R2R, csc_r2r_bt2020to709, i);
 729                                 LOAD_CSC(vop_dev, R2Y, csc_r2y_bt709_full_10, i);
 730                         }
 731                 } else if (output_color == COLOR_YCBCR_BT2020) {
 732                         if (!(IS_YUV(win->area[0].fmt_cfg) ||
 733                               win->area[0].yuyv_fmt)) {
 734                                 val |= V_WIN0_YUV2YUV_R2Y_EN(1) |
 735                                         V_WIN0_YUV2YUV_EN(1);
 736                                 LOAD_CSC(vop_dev, R2R, csc_r2r_bt709to2020, i);
 737                                 LOAD_CSC(vop_dev, R2Y, csc_r2y_bt2020, i);
 738                         } else if (win->colorspace == CSC_BT601 ||
 739                                         win->colorspace == CSC_BT709) {
 740                                 val |= V_WIN0_YUV2YUV_Y2R_EN(1) |
 741                                         V_WIN0_YUV2YUV_R2Y_EN(1) |
 742                                         V_WIN0_YUV2YUV_EN(1);
 743                                 LOAD_CSC(vop_dev, Y2R, csc_y2r_bt709_full_10, i);
 744                                 LOAD_CSC(vop_dev, R2R, csc_r2r_bt709to2020, i);
 745                                 LOAD_CSC(vop_dev, R2Y, csc_r2y_bt2020, i);
 746                         }
 747                 }
 748 post:
 749                 vop_msk_reg(vop_dev, YUV2YUV_WIN, val << shift);
 750         }
 751
 752         return output_color;
 753 }
 754
 755 /*
 756  * colorspace path:
 757  *      Input        Win csc            Post csc              Output
 758  * 1. YUV(2020)  --> bypass   ---+ Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
 759  *    RGB        --> R2Y(709) __/
 760  *
 761  * 2. YUV(2020)  --> bypass   ---+       bypass        --> YUV_OUTPUT(2020)
 762  *    RGB        --> R2Y(709) __/
 763  *
 764  * 3. YUV(2020)  --> bypass   ---+    Y2R->2020To709   --> RGB_OUTPUT(709)
 765  *    RGB        --> R2Y(709) __/
 766  *
 767  * 4. YUV(601/709)-> bypass   ---+ Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
 768  *    RGB        --> R2Y(709) __/
 769  *
 770  * 5. YUV(601/709)-> bypass   ---+       bypass        --> YUV_OUTPUT(709)
 771  *    RGB        --> R2Y(709) __/
 772  *
 773  * 6. YUV(601/709)-> bypass   ---+       bypass        --> YUV_OUTPUT(601)
 774  *    RGB        --> R2Y(601) __/
 775  *
 776  * 7. YUV(601)   --> Y2R(601/mpeg)-+     bypass        --> RGB_OUTPUT(709)
 777  *    RGB        --> bypass   ____/
 778  *
 779  * 8. YUV(709)   --> Y2R(709/hd) --+     bypass        --> RGB_OUTPUT(709)
 780  *    RGB        --> bypass   ____/
 781  *
 782  * 9. RGB        --> bypass   --->    709To2020->R2Y   --> YUV_OUTPUT(2020)
 783  *
 784  * 10. RGB       --> R2Y(709) --->      bypass        --> YUV_OUTPUT(709)
 785  *
 786  * 11. RGB       --> R2Y(601) --->       bypass        --> YUV_OUTPUT(601)
 787  *
 788  * 12. RGB       --> bypass   --->       bypass        --> RGB_OUTPUT(709)
 789  */
 790 static int rk3228_vop_win_csc_cfg(struct rk_lcdc_driver *dev_drv)
 791 {
 792         struct vop_device *vop_dev =
 793             container_of(dev_drv, struct vop_device, driver);
 794         struct rk_lcdc_win *win;
 795         int output_color = dev_drv->output_color;
 796         int win_csc = COLOR_RGB;
 797         int r2y_mode = VOP_R2Y_CSC_BT709;
 798         int i;
 799
 800         for (i = 0; i < dev_drv->lcdc_win_num; i++) {
 801                 win = dev_drv->win[i];
 802                 if (!win->state)
 803                         continue;
 804
 805                 if (IS_YUV(win->area[0].fmt_cfg)) {
 806                         if (win->colorspace == CSC_BT2020 &&
 807                             win_csc < COLOR_YCBCR_BT2020) {
 808                                 r2y_mode = VOP_R2Y_CSC_BT709;
 809                                 win_csc = COLOR_YCBCR_BT2020;
 810                         }
 811
 812                         if (win->colorspace == CSC_BT709 &&
 813                             win_csc < COLOR_YCBCR_BT709) {
 814                                 r2y_mode = VOP_R2Y_CSC_BT709;
 815                                 win_csc = COLOR_YCBCR_BT709;
 816                         }
 817
 818                         if (win->colorspace == CSC_BT601 &&
 819                             win_csc < COLOR_YCBCR) {
 820                                 r2y_mode = VOP_R2Y_CSC_BT709;
 821                                 win_csc = COLOR_YCBCR;
 822                         }
 823                 }
 824         }
 825
 826         if (win_csc == COLOR_RGB) {
 827                 if (output_color == COLOR_YCBCR_BT709) {
 828                         r2y_mode = VOP_R2Y_CSC_BT709;
 829                         win_csc = COLOR_YCBCR_BT709;
 830                 } else if (output_color == COLOR_YCBCR) {
 831                         r2y_mode = VOP_R2Y_CSC_BT601;
 832                         win_csc = COLOR_YCBCR;
 833                 }
 834         }
 835
 836         for (i = 0; i < dev_drv->lcdc_win_num; i++) {
 837                 win = dev_drv->win[i];
 838                 if (!win->state)
 839                         continue;
 840
 841                 if (win_csc != COLOR_RGB && !IS_YUV(win->area[0].fmt_cfg))
 842                         vop_win_csc_mode(vop_dev, win, r2y_mode);
 843
 844                 if (IS_YUV(win->area[0].fmt_cfg)) {
 845                         if (win_csc == COLOR_YCBCR)
 846                                 vop_win_csc_mode(vop_dev, win,
 847                                                  VOP_Y2R_CSC_MPEG);
 848                         else if (win_csc == COLOR_YCBCR_BT709)
 849                                 vop_win_csc_mode(vop_dev, win, VOP_Y2R_CSC_HD);
 850                 }
 851         }
 852
 853         return win_csc;
 854 }
 855
 856 static int vop_post_csc_cfg(struct rk_lcdc_driver *dev_drv)
 857 {
 858         struct vop_device *vop_dev =
 859             container_of(dev_drv, struct vop_device, driver);
 860         int output_color = dev_drv->output_color;
 861         int win_csc = 0, overlay_mode = 0;
 862         u64 val;
 863
 864         if (VOP_CHIP(vop_dev) == VOP_RK322X) {
 865                 win_csc = rk3228_vop_win_csc_cfg(dev_drv);
 866         } else if (VOP_CHIP(vop_dev) == VOP_RK3399) {
 867                 win_csc = rk3399_vop_win_csc_cfg(dev_drv);
 868
 869                 /*
 870                  * RK3399 not support post csc config.
 871                  */
 872                 goto done;
 873         }
 874
 875         val = V_YUV2YUV_POST_Y2R_EN(0) | V_YUV2YUV_POST_EN(0) |
 876                 V_YUV2YUV_POST_R2Y_EN(0);
 877         /* Y2R */
 878         if (win_csc == COLOR_YCBCR && output_color == COLOR_YCBCR_BT2020) {
 879                 val |= V_YUV2YUV_POST_Y2R_EN(1);
 880                 vop_load_csc_table(vop_dev, POST_YUV2YUV_Y2R_COE,
 881                                    csc_y2r_bt709_full);
 882         }
 883         if (win_csc == COLOR_YCBCR_BT2020 &&
 884             output_color != COLOR_YCBCR_BT2020) {
 885                 val |= V_YUV2YUV_POST_Y2R_EN(1);
 886                 vop_load_csc_table(vop_dev, POST_YUV2YUV_Y2R_COE,
 887                                    csc_y2r_bt2020);
 888         }
 889
 890         /* R2R */
 891         if ((win_csc == COLOR_YCBCR ||
 892              win_csc == COLOR_YCBCR_BT709 ||
 893              win_csc == COLOR_RGB) && output_color == COLOR_YCBCR_BT2020) {
 894                 val |= V_YUV2YUV_POST_EN(1);
 895                 vop_load_csc_table(vop_dev, POST_YUV2YUV_3x3_COE,
 896                                    csc_r2r_bt709to2020);
 897         }
 898         if (win_csc == COLOR_YCBCR_BT2020 &&
 899             (output_color == COLOR_YCBCR ||
 900              output_color == COLOR_YCBCR_BT709 ||
 901              output_color == COLOR_RGB)) {
 902                 val |= V_YUV2YUV_POST_EN(1);
 903                 vop_load_csc_table(vop_dev, POST_YUV2YUV_3x3_COE,
 904                                    csc_r2r_bt2020to709);
 905         }
 906
 907         /* Y2R */
 908         if (output_color != COLOR_RGB) {
 909                 val |= V_YUV2YUV_POST_R2Y_EN(1);
 910
 911                 if (output_color == COLOR_YCBCR_BT2020)
 912                         vop_load_csc_table(vop_dev, POST_YUV2YUV_R2Y_COE,
 913                                            csc_r2y_bt2020);
 914                 else
 915                         vop_load_csc_table(vop_dev, POST_YUV2YUV_R2Y_COE,
 916                                            csc_r2y_bt709_full);
 917         }
 918
 919         DBG(1, "win_csc=%d output_color=%d val=%llx\n",
 920             win_csc, output_color, val);
 921         vop_msk_reg(vop_dev, YUV2YUV_POST, val);
 922 done:
 923         overlay_mode = (win_csc != COLOR_RGB) ? VOP_YUV_DOMAIN : VOP_RGB_DOMAIN;
 924         vop_msk_reg(vop_dev, SYS_CTRL, V_OVERLAY_MODE(overlay_mode));
 925
 926         return 0;
 927 }
 928
 929 static int vop_post_cfg(struct rk_lcdc_driver *dev_drv)
 930 {
 931         struct vop_device *vop_dev =
 932             container_of(dev_drv, struct vop_device, driver);
 933         struct rk_screen *screen = dev_drv->cur_screen;
 934         u16 x_res = screen->mode.xres;
 935         u16 y_res = screen->mode.yres;
 936         u64 val;
 937         u16 h_total, v_total;
 938         u16 post_hsd_en, post_vsd_en;
 939         u16 post_dsp_hact_st, post_dsp_hact_end;
 940         u16 post_dsp_vact_st, post_dsp_vact_end;
 941         u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
 942         u16 post_h_fac, post_v_fac;
 943
 944         screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200;
 945         screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200;
 946         screen->post_xsize = x_res *
 947             (dev_drv->overscan.left + dev_drv->overscan.right) / 200;
 948         screen->post_ysize = y_res *
 949             (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200;
 950
 951         h_total = screen->mode.hsync_len + screen->mode.left_margin +
 952             x_res + screen->mode.right_margin;
 953         v_total = screen->mode.vsync_len + screen->mode.upper_margin +
 954             y_res + screen->mode.lower_margin;
 955
 956         if (screen->post_dsp_stx + screen->post_xsize > x_res) {
 957                 dev_warn(vop_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
 958                          screen->post_dsp_stx, screen->post_xsize, x_res);
 959                 screen->post_dsp_stx = x_res - screen->post_xsize;
 960         }
 961         if (screen->x_mirror == 0) {
 962                 post_dsp_hact_st = screen->post_dsp_stx +
 963                     screen->mode.hsync_len + screen->mode.left_margin;
 964                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 965         } else {
 966                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 967                     screen->post_dsp_stx;
 968                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 969         }
 970         if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
 971                 post_hsd_en = 1;
 972                 post_h_fac =
 973                     GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
 974         } else {
 975                 post_hsd_en = 0;
 976                 post_h_fac = 0x1000;
 977         }
 978
 979         if (screen->post_dsp_sty + screen->post_ysize > y_res) {
 980                 dev_warn(vop_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
 981                          screen->post_dsp_sty, screen->post_ysize, y_res);
 982                 screen->post_dsp_sty = y_res - screen->post_ysize;
 983         }
 984
 985         if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
 986                 post_vsd_en = 1;
 987                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
 988                                                       screen->post_ysize);
 989         } else {
 990                 post_vsd_en = 0;
 991                 post_v_fac = 0x1000;
 992         }
 993
 994         if (screen->mode.vmode & FB_VMODE_INTERLACED) {
 995                 post_dsp_vact_st = screen->post_dsp_sty / 2 +
 996                                         screen->mode.vsync_len +
 997                                         screen->mode.upper_margin;
 998                 post_dsp_vact_end = post_dsp_vact_st +
 999                                         screen->post_ysize / 2;
1000
1001                 post_dsp_vact_st_f1 = screen->mode.vsync_len +
1002                                         screen->mode.upper_margin +
1003                                         y_res / 2 +
1004                                         screen->mode.lower_margin +
1005                                         screen->mode.vsync_len +
1006                                         screen->mode.upper_margin +
1007                                         screen->post_dsp_sty / 2 +
1008                                         1;
1009                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
1010                                         screen->post_ysize / 2;
1011         } else {
1012                 if (screen->y_mirror == 0) {
1013                         post_dsp_vact_st = screen->post_dsp_sty +
1014                             screen->mode.vsync_len +
1015                             screen->mode.upper_margin;
1016                         post_dsp_vact_end = post_dsp_vact_st +
1017                                 screen->post_ysize;
1018                 } else {
1019                         post_dsp_vact_end = v_total -
1020                                 screen->mode.lower_margin -
1021                             screen->post_dsp_sty;
1022                         post_dsp_vact_st = post_dsp_vact_end -
1023                                 screen->post_ysize;
1024                 }
1025                 post_dsp_vact_st_f1 = 0;
1026                 post_dsp_vact_end_f1 = 0;
1027         }
1028         DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
1029             screen->post_xsize, screen->post_ysize, screen->xpos);
1030         DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
1031             screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
1032         val = V_DSP_HACT_END_POST(post_dsp_hact_end) |
1033             V_DSP_HACT_ST_POST(post_dsp_hact_st);
1034         vop_msk_reg(vop_dev, POST_DSP_HACT_INFO, val);
1035
1036         val = V_DSP_VACT_END_POST(post_dsp_vact_end) |
1037             V_DSP_VACT_ST_POST(post_dsp_vact_st);
1038         vop_msk_reg(vop_dev, POST_DSP_VACT_INFO, val);
1039
1040         val = V_POST_HS_FACTOR_YRGB(post_h_fac) |
1041             V_POST_VS_FACTOR_YRGB(post_v_fac);
1042         vop_msk_reg(vop_dev, POST_SCL_FACTOR_YRGB, val);
1043         val = V_DSP_VACT_END_POST(post_dsp_vact_end_f1) |
1044             V_DSP_VACT_ST_POST(post_dsp_vact_st_f1);
1045         vop_msk_reg(vop_dev, POST_DSP_VACT_INFO_F1, val);
1046         val = V_POST_HOR_SD_EN(post_hsd_en) | V_POST_VER_SD_EN(post_vsd_en);
1047         vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
1048
1049         vop_post_csc_cfg(dev_drv);
1050
1051         return 0;
1052 }
1053
1054 static int vop_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
1055 {
1056         struct vop_device *vop_dev =
1057             container_of(dev_drv, struct vop_device, driver);
1058         struct rk_lcdc_win *win;
1059         u32 colorkey_r, colorkey_g, colorkey_b;
1060         int i, key_val;
1061
1062         for (i = 0; i < dev_drv->lcdc_win_num; i++) {
1063                 win = dev_drv->win[i];
1064                 key_val = win->color_key_val;
1065                 colorkey_r = (key_val & 0xff) << 2;
1066                 colorkey_g = ((key_val >> 8) & 0xff) << 12;
1067                 colorkey_b = ((key_val >> 16) & 0xff) << 22;
1068                 /* color key dither 565/888->aaa */
1069                 key_val = colorkey_r | colorkey_g | colorkey_b;
1070                 switch (i) {
1071                 case 0:
1072                         vop_writel(vop_dev, WIN0_COLOR_KEY, key_val);
1073                         break;
1074                 case 1:
1075                         vop_writel(vop_dev, WIN1_COLOR_KEY, key_val);
1076                         break;
1077                 case 2:
1078                         vop_writel(vop_dev, WIN2_COLOR_KEY, key_val);
1079                         break;
1080                 case 3:
1081                         vop_writel(vop_dev, WIN3_COLOR_KEY, key_val);
1082                         break;
1083                 default:
1084                         pr_info("%s:un support win num:%d\n",
1085                                 __func__, i);
1086                         break;
1087                 }
1088         }
1089         return 0;
1090 }
1091
1092 static int vop_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
1093 {
1094         struct vop_device *vop_dev =
1095             container_of(dev_drv, struct vop_device, driver);
1096         struct rk_lcdc_win *win = dev_drv->win[win_id];
1097         struct alpha_config alpha_config;
1098         u64 val;
1099         int ppixel_alpha = 0, global_alpha = 0, i;
1100         u32 src_alpha_ctl = 0, dst_alpha_ctl = 0;
1101         int alpha_en = 1;
1102
1103         memset(&alpha_config, 0, sizeof(struct alpha_config));
1104         for (i = 0; i < win->area_num; i++) {
1105                 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
1106                                  (win->area[i].format == FBDC_ARGB_888) ||
1107                                  (win->area[i].format == FBDC_ABGR_888) ||
1108                                  (win->area[i].format == ABGR888)) ? 1 : 0;
1109         }
1110
1111         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
1112
1113         for (i = 0; i < dev_drv->lcdc_win_num; i++) {
1114                 if (!dev_drv->win[i]->state)
1115                         continue;
1116                 if (win->z_order > dev_drv->win[i]->z_order)
1117                         break;
1118         }
1119
1120         /*
1121          * The bottom layer not support ppixel_alpha mode.
1122          */
1123         if (i == dev_drv->lcdc_win_num)
1124                 ppixel_alpha = 0;
1125         alpha_config.src_global_alpha_val = win->g_alpha_val;
1126         win->alpha_mode = AB_SRC_OVER;
1127
1128         switch (win->alpha_mode) {
1129         case AB_USER_DEFINE:
1130                 break;
1131         case AB_CLEAR:
1132                 alpha_config.src_factor_mode = AA_ZERO;
1133                 alpha_config.dst_factor_mode = AA_ZERO;
1134                 break;
1135         case AB_SRC:
1136                 alpha_config.src_factor_mode = AA_ONE;
1137                 alpha_config.dst_factor_mode = AA_ZERO;
1138                 break;
1139         case AB_DST:
1140                 alpha_config.src_factor_mode = AA_ZERO;
1141                 alpha_config.dst_factor_mode = AA_ONE;
1142                 break;
1143         case AB_SRC_OVER:
1144                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1145                 if (global_alpha)
1146                         alpha_config.src_factor_mode = AA_SRC_GLOBAL;
1147                 else
1148                         alpha_config.src_factor_mode = AA_ONE;
1149                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1150                 break;
1151         case AB_DST_OVER:
1152                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1153                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
1154                 alpha_config.dst_factor_mode = AA_ONE;
1155                 break;
1156         case AB_SRC_IN:
1157                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1158                 alpha_config.src_factor_mode = AA_SRC;
1159                 alpha_config.dst_factor_mode = AA_ZERO;
1160                 break;
1161         case AB_DST_IN:
1162                 alpha_config.src_factor_mode = AA_ZERO;
1163                 alpha_config.dst_factor_mode = AA_SRC;
1164                 break;
1165         case AB_SRC_OUT:
1166                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1167                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
1168                 alpha_config.dst_factor_mode = AA_ZERO;
1169                 break;
1170         case AB_DST_OUT:
1171                 alpha_config.src_factor_mode = AA_ZERO;
1172                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1173                 break;
1174         case AB_SRC_ATOP:
1175                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1176                 alpha_config.src_factor_mode = AA_SRC;
1177                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1178                 break;
1179         case AB_DST_ATOP:
1180                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1181                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
1182                 alpha_config.dst_factor_mode = AA_SRC;
1183                 break;
1184         case XOR:
1185                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1186                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
1187                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1188                 break;
1189         case AB_SRC_OVER_GLOBAL:
1190                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
1191                 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
1192                 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
1193                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1194                 break;
1195         default:
1196                 pr_err("alpha mode error\n");
1197                 break;
1198         }
1199         if ((ppixel_alpha == 1) && (global_alpha == 1))
1200                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
1201         else if (ppixel_alpha == 1)
1202                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
1203         else if (global_alpha == 1)
1204                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
1205         else
1206                 alpha_en = 0;
1207         alpha_config.src_alpha_mode = AA_STRAIGHT;
1208         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
1209
1210         switch (win_id) {
1211         case 0:
1212                 src_alpha_ctl = 0x60;
1213                 dst_alpha_ctl = 0x64;
1214                 break;
1215         case 1:
1216                 src_alpha_ctl = 0xa0;
1217                 dst_alpha_ctl = 0xa4;
1218                 break;
1219         case 2:
1220                 src_alpha_ctl = 0xdc;
1221                 dst_alpha_ctl = 0xec;
1222                 break;
1223         case 3:
1224                 src_alpha_ctl = 0x12c;
1225                 dst_alpha_ctl = 0x13c;
1226                 break;
1227         case 4:
1228                 src_alpha_ctl = 0x160;
1229                 dst_alpha_ctl = 0x164;
1230                 break;
1231         }
1232         val = V_WIN0_DST_FACTOR_MODE(alpha_config.dst_factor_mode);
1233         vop_msk_reg(vop_dev, dst_alpha_ctl, val);
1234         val = V_WIN0_SRC_ALPHA_EN(alpha_en) |
1235             V_WIN0_SRC_COLOR_MODE(alpha_config.src_color_mode) |
1236             V_WIN0_SRC_ALPHA_MODE(alpha_config.src_alpha_mode) |
1237             V_WIN0_SRC_BLEND_MODE(alpha_config.src_global_alpha_mode) |
1238             V_WIN0_SRC_ALPHA_CAL_MODE(alpha_config.src_alpha_cal_m0) |
1239             V_WIN0_SRC_FACTOR_MODE(alpha_config.src_factor_mode) |
1240             V_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
1241
1242         vop_msk_reg(vop_dev, src_alpha_ctl, val);
1243
1244         return 0;
1245 }
1246
1247 static int vop_axi_gather_cfg(struct vop_device *vop_dev,
1248                               struct rk_lcdc_win *win)
1249 {
1250         u64 val;
1251         u16 yrgb_gather_num = 3;
1252         u16 cbcr_gather_num = 1;
1253
1254         switch (win->area[0].format) {
1255         case ARGB888:
1256         case XBGR888:
1257         case ABGR888:
1258         case FBDC_ARGB_888:
1259         case FBDC_RGBX_888:
1260         case FBDC_ABGR_888:
1261                 yrgb_gather_num = 3;
1262                 break;
1263         case RGB888:
1264         case RGB565:
1265         case FBDC_RGB_565:
1266                 yrgb_gather_num = 2;
1267                 break;
1268         case YUV444:
1269         case YUV422:
1270         case YUV420:
1271         case YUV420_A:
1272         case YUV422_A:
1273         case YUV444_A:
1274         case YUV420_NV21:
1275         case YUYV420:
1276         case UYVY420:
1277                 yrgb_gather_num = 1;
1278                 cbcr_gather_num = 2;
1279                 break;
1280         case YUYV422:
1281         case UYVY422:
1282                 yrgb_gather_num = 2;
1283                 cbcr_gather_num = 2;
1284                 break;
1285         default:
1286                 dev_err(vop_dev->driver.dev, "%s:un supported format[%d]\n",
1287                         __func__, win->area[0].format);
1288                 return -EINVAL;
1289         }
1290
1291         if ((win->id == VOP_WIN0) || (win->id == VOP_WIN1)) {
1292                 val = V_WIN0_YRGB_AXI_GATHER_EN(1) |
1293                         V_WIN0_CBR_AXI_GATHER_EN(1) |
1294                         V_WIN0_YRGB_AXI_GATHER_NUM(yrgb_gather_num) |
1295                         V_WIN0_CBR_AXI_GATHER_NUM(cbcr_gather_num);
1296                 vop_msk_reg(vop_dev, WIN0_CTRL1 + (win->id * 0x40), val);
1297         } else if ((win->id == VOP_WIN2) || (win->id == VOP_WIN3)) {
1298                 val = V_WIN2_AXI_GATHER_EN(1) |
1299                         V_WIN2_AXI_GATHER_NUM(yrgb_gather_num);
1300                 vop_msk_reg(vop_dev, WIN2_CTRL1 + ((win->id - 2) * 0x50), val);
1301         } else if (win->id == VOP_HWC) {
1302                 val = V_HWC_AXI_GATHER_EN(1) |
1303                         V_HWC_AXI_GATHER_NUM(yrgb_gather_num);
1304                 vop_msk_reg(vop_dev, HWC_CTRL1, val);
1305         }
1306         return 0;
1307 }
1308
1309 static int vop_fbdc_reg_update(struct vop_device *vop_dev, int win_id)
1310 {
1311         struct rk_lcdc_win *win = vop_dev->driver.win[win_id];
1312         u64 val;
1313
1314         val = V_VOP_FBDC_WIN_SEL(win_id) |
1315                 V_AFBCD_HREG_PIXEL_PACKING_FMT(win->area[0].fbdc_fmt_cfg) |
1316                 V_AFBCD_HREG_BLOCK_SPLIT(win->area[0].fbdc_cor_en);
1317         vop_msk_reg(vop_dev, AFBCD0_CTRL, val);
1318
1319         val = V_AFBCD_HREG_PIC_WIDTH(win->area[0].fbdc_mb_width - 1) |
1320                 V_AFBCD_HREG_PIC_HEIGHT(win->area[0].fbdc_mb_height - 1);
1321         vop_msk_reg(vop_dev, AFBCD0_PIC_SIZE, val);
1322
1323         return 0;
1324 }
1325
1326 static int vop_init_fbdc_config(struct vop_device *vop_dev, int win_id)
1327 {
1328         struct rk_lcdc_driver *vop_drv = &vop_dev->driver;
1329         struct rk_lcdc_win *win = vop_drv->win[win_id];
1330         struct rk_screen *screen = vop_drv->cur_screen;
1331
1332         if (screen->mode.flag & FB_VMODE_INTERLACED) {
1333                 dev_err(vop_dev->dev, "unsupport fbdc+interlace!\n");
1334                 return 0;
1335         }
1336
1337         if (VOP_CHIP(vop_dev) != VOP_RK3399) {
1338                 pr_err("soc: 0x%08x not support FBDC\n", VOP_CHIP(vop_dev));
1339                 return 0;
1340         }
1341
1342         win->area[0].fbdc_mb_width = win->area[0].xvir;
1343         win->area[0].fbdc_mb_height = win->area[0].yact;
1344         win->area[0].fbdc_cor_en = 0; /* hreg_block_split */
1345         win->area[0].fbdc_fmt_cfg |= AFBDC_YUV_COLOR_TRANSFORM << 4;
1346
1347         return 0;
1348 }
1349
1350 static int vop_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1351 {
1352         struct vop_device *vop_dev =
1353             container_of(dev_drv, struct vop_device, driver);
1354         struct rk_lcdc_win *win = dev_drv->win[win_id];
1355         u64 val;
1356         u32 off;
1357         int format;
1358         struct rk_win_property *win_property =
1359                                 &dev_drv->win[win_id]->property;
1360
1361         off = win_id * 0x40;
1362
1363         if (win->state == 1) {
1364                 if (!(win_property->feature & SUPPORT_HW_EXIST)) {
1365                         pr_err("vop[%d] win[%d] hardware unsupport\n",
1366                                vop_dev->id, win_id);
1367                         return 0;
1368                 }
1369                 vop_axi_gather_cfg(vop_dev, win);
1370                 if (win->area[0].fbdc_en)
1371                         vop_fbdc_reg_update(vop_dev, win_id);
1372                 /*
1373                  * rk322x have a bug on windows 0 and 1:
1374                  *
1375                  * When switch win format from RGB to YUV, would flash
1376                  * some green lines on the top of the windows.
1377                  *
1378                  * Use bg_en show one blank frame to skip the error frame.
1379                  */
1380                 if (IS_YUV(win->area[0].fmt_cfg)) {
1381                         val = vop_readl(vop_dev, WIN0_CTRL0);
1382                         format = (val & MASK(WIN0_DATA_FMT)) >> 1;
1383
1384                         if (!IS_YUV(format)) {
1385                                 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1386                                         val = V_WIN0_DSP_BG_RED(0x200) |
1387                                                 V_WIN0_DSP_BG_GREEN(0x40) |
1388                                                 V_WIN0_DSP_BG_BLUE(0x200) |
1389                                                 V_WIN0_BG_EN(1);
1390                                         vop_msk_reg(vop_dev, WIN0_DSP_BG + off,
1391                                                     val);
1392                                 } else {
1393                                         val = V_WIN0_DSP_BG_RED(0) |
1394                                                 V_WIN0_DSP_BG_GREEN(0) |
1395                                                 V_WIN0_DSP_BG_BLUE(0) |
1396                                                 V_WIN0_BG_EN(1);
1397                                         vop_msk_reg(vop_dev, WIN0_DSP_BG + off,
1398                                                     val);
1399                                 }
1400                         } else {
1401                                 val = V_WIN0_BG_EN(0);
1402                                 vop_msk_reg(vop_dev, WIN0_DSP_BG + off, val);
1403                         }
1404                 } else {
1405                         val = V_WIN0_BG_EN(0);
1406                         vop_msk_reg(vop_dev, WIN0_DSP_BG + off, val);
1407                 }
1408
1409                 val = V_WIN0_EN(win->state) |
1410                         V_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1411                         V_WIN0_FMT_10(win->fmt_10) |
1412                         V_WIN0_LB_MODE(win->win_lb_mode) |
1413                         V_WIN0_RB_SWAP(win->area[0].swap_rb) |
1414                         V_WIN0_X_MIR_EN(win->xmirror) |
1415                         V_WIN0_Y_MIR_EN(win->ymirror) |
1416                         V_WIN0_UV_SWAP(win->area[0].swap_uv);
1417                 if (VOP_CHIP(vop_dev) == VOP_RK3399)
1418                         val |= V_WIN0_YUYV(win->area[0].yuyv_fmt);
1419                 vop_msk_reg(vop_dev, WIN0_CTRL0 + off, val);
1420                 val = V_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1421                     V_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1422                     V_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1423                     V_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1424                     V_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1425                     V_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1426                     V_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1427                     V_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1428                     V_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1429                     V_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1430                     V_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1431                     V_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1432                     V_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1433                     V_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1434                     V_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1435                 vop_msk_reg(vop_dev, WIN0_CTRL1 + off, val);
1436                 val = V_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1437                     V_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1438                 vop_writel(vop_dev, WIN0_VIR + off, val);
1439                 val = V_WIN0_ACT_WIDTH(win->area[0].xact - 1) |
1440                     V_WIN0_ACT_HEIGHT(win->area[0].yact - 1);
1441                 vop_writel(vop_dev, WIN0_ACT_INFO + off, val);
1442
1443                 val = V_WIN0_DSP_WIDTH(win->area[0].xsize - 1) |
1444                     V_WIN0_DSP_HEIGHT(win->area[0].ysize - 1);
1445                 vop_writel(vop_dev, WIN0_DSP_INFO + off, val);
1446
1447                 val = V_WIN0_DSP_XST(win->area[0].dsp_stx) |
1448                     V_WIN0_DSP_YST(win->area[0].dsp_sty);
1449                 vop_writel(vop_dev, WIN0_DSP_ST + off, val);
1450
1451                 val = V_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1452                     V_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1453                 vop_writel(vop_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1454
1455                 val = V_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1456                     V_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1457                 vop_writel(vop_dev, WIN0_SCL_FACTOR_CBR + off, val);
1458         } else {
1459                 val = V_WIN0_EN(win->state);
1460                 vop_msk_reg(vop_dev, WIN0_CTRL0 + off, val);
1461         }
1462
1463         return 0;
1464 }
1465
1466 static int area_xst(struct rk_lcdc_win *win, int area_num)
1467 {
1468         struct rk_lcdc_win_area area_temp;
1469         int i, j;
1470
1471         for (i = 0; i < area_num; i++) {
1472                 for (j = i + 1; j < area_num; j++) {
1473                         if (win->area[i].dsp_stx >  win->area[j].dsp_stx) {
1474                                 memcpy(&area_temp, &win->area[i],
1475                                        sizeof(struct rk_lcdc_win_area));
1476                                 memcpy(&win->area[i], &win->area[j],
1477                                        sizeof(struct rk_lcdc_win_area));
1478                                 memcpy(&win->area[j], &area_temp,
1479                                        sizeof(struct rk_lcdc_win_area));
1480                         }
1481                 }
1482         }
1483
1484         return 0;
1485 }
1486
1487 static int vop_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1488 {
1489         struct vop_device *vop_dev =
1490                         container_of(dev_drv, struct vop_device, driver);
1491         struct rk_lcdc_win *win = dev_drv->win[win_id];
1492         unsigned int off;
1493         u64 val;
1494         struct rk_win_property *win_property =
1495                                 &dev_drv->win[win_id]->property;
1496
1497         off = (win_id - 2) * 0x50;
1498         area_xst(win, win->area_num);
1499
1500         if (win->state == 1) {
1501                 if (!(win_property->feature & SUPPORT_HW_EXIST)) {
1502                         pr_err("vop[%d] win[%d] hardware unsupport\n",
1503                                vop_dev->id, win_id);
1504                         return 0;
1505                 }
1506                 vop_axi_gather_cfg(vop_dev, win);
1507                 if (win->area[0].fbdc_en)
1508                         vop_fbdc_reg_update(vop_dev, win_id);
1509                 val = V_WIN2_EN(1) | V_WIN1_CSC_MODE(win->csc_mode);
1510                 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1511                 /* area 0 */
1512                 if (win->area[0].state == 1) {
1513                         val = V_WIN2_MST0_EN(win->area[0].state) |
1514                             V_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1515                             V_WIN2_RB_SWAP0(win->area[0].swap_rb);
1516                         vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1517
1518                         val = V_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1519                         vop_msk_reg(vop_dev, WIN2_VIR0_1 + off, val);
1520
1521                         val = V_WIN2_DSP_WIDTH0(win->area[0].xsize - 1) |
1522                             V_WIN2_DSP_HEIGHT0(win->area[0].ysize - 1);
1523                         vop_writel(vop_dev, WIN2_DSP_INFO0 + off, val);
1524                         val = V_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1525                             V_WIN2_DSP_YST0(win->area[0].dsp_sty);
1526                         vop_writel(vop_dev, WIN2_DSP_ST0 + off, val);
1527                 } else {
1528                         val = V_WIN2_MST0_EN(0);
1529                         vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1530                 }
1531                 /* area 1 */
1532                 if (win->area[1].state == 1) {
1533                         val = V_WIN2_MST1_EN(win->area[1].state) |
1534                             V_WIN2_DATA_FMT1(win->area[1].fmt_cfg) |
1535                             V_WIN2_RB_SWAP1(win->area[1].swap_rb);
1536                         vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1537
1538                         val = V_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1539                         vop_msk_reg(vop_dev, WIN2_VIR0_1 + off, val);
1540
1541                         val = V_WIN2_DSP_WIDTH1(win->area[1].xsize - 1) |
1542                             V_WIN2_DSP_HEIGHT1(win->area[1].ysize - 1);
1543                         vop_writel(vop_dev, WIN2_DSP_INFO1 + off, val);
1544                         val = V_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1545                             V_WIN2_DSP_YST1(win->area[1].dsp_sty);
1546                         vop_writel(vop_dev, WIN2_DSP_ST1 + off, val);
1547                 } else {
1548                         val = V_WIN2_MST1_EN(0);
1549                         vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1550                 }
1551                 /* area 2 */
1552                 if (win->area[2].state == 1) {
1553                         val = V_WIN2_MST2_EN(win->area[2].state) |
1554                             V_WIN2_DATA_FMT2(win->area[2].fmt_cfg) |
1555                             V_WIN2_RB_SWAP2(win->area[2].swap_rb);
1556                         vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1557
1558                         val = V_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1559                         vop_msk_reg(vop_dev, WIN2_VIR2_3 + off, val);
1560
1561                         val = V_WIN2_DSP_WIDTH2(win->area[2].xsize - 1) |
1562                             V_WIN2_DSP_HEIGHT2(win->area[2].ysize - 1);
1563                         vop_writel(vop_dev, WIN2_DSP_INFO2 + off, val);
1564                         val = V_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1565                             V_WIN2_DSP_YST2(win->area[2].dsp_sty);
1566                         vop_writel(vop_dev, WIN2_DSP_ST2 + off, val);
1567                 } else {
1568                         val = V_WIN2_MST2_EN(0);
1569                         vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1570                 }
1571                 /* area 3 */
1572                 if (win->area[3].state == 1) {
1573                         val = V_WIN2_MST3_EN(win->area[3].state) |
1574                             V_WIN2_DATA_FMT3(win->area[3].fmt_cfg) |
1575                             V_WIN2_RB_SWAP3(win->area[3].swap_rb);
1576                         vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1577
1578                         val = V_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1579                         vop_msk_reg(vop_dev, WIN2_VIR2_3 + off, val);
1580
1581                         val = V_WIN2_DSP_WIDTH3(win->area[3].xsize - 1) |
1582                             V_WIN2_DSP_HEIGHT3(win->area[3].ysize - 1);
1583                         vop_writel(vop_dev, WIN2_DSP_INFO3 + off, val);
1584                         val = V_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1585                             V_WIN2_DSP_YST3(win->area[3].dsp_sty);
1586                         vop_writel(vop_dev, WIN2_DSP_ST3 + off, val);
1587                 } else {
1588                         val = V_WIN2_MST3_EN(0);
1589                         vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1590                 }
1591         } else {
1592                 val = V_WIN2_EN(win->state) | V_WIN2_MST0_EN(0) |
1593                     V_WIN2_MST1_EN(0) | V_WIN2_MST2_EN(0) | V_WIN2_MST3_EN(0);
1594                 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1595         }
1596
1597         return 0;
1598 }
1599
1600 static int vop_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1601 {
1602         struct vop_device *vop_dev =
1603             container_of(dev_drv, struct vop_device, driver);
1604         struct rk_lcdc_win *win = dev_drv->win[win_id];
1605         unsigned int hwc_size = 0;
1606         u64 val;
1607
1608         if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32)) {
1609                 hwc_size = 0;
1610         } else if ((win->area[0].xsize == 64) && (win->area[0].ysize == 64)) {
1611                 hwc_size = 1;
1612         } else if ((win->area[0].xsize == 96) && (win->area[0].ysize == 96)) {
1613                 hwc_size = 2;
1614         } else if ((win->area[0].xsize == 128) &&
1615                    (win->area[0].ysize == 128)) {
1616                 hwc_size = 3;
1617         } else {
1618                 dev_err(vop_dev->dev, "un supported hwc size[%dx%d]!\n",
1619                                 win->area[0].xsize, win->area[0].ysize);
1620                 return -EINVAL;
1621         }
1622
1623         if (win->state == 1) {
1624                 vop_axi_gather_cfg(vop_dev, win);
1625                 val = V_HWC_EN(1) | V_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1626                     V_HWC_RB_SWAP(win->area[0].swap_rb);
1627                 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1628
1629                 val = V_HWC_SIZE(hwc_size);
1630                 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1631
1632                 val = V_HWC_DSP_XST(win->area[0].dsp_stx) |
1633                     V_HWC_DSP_YST(win->area[0].dsp_sty);
1634                 vop_msk_reg(vop_dev, HWC_DSP_ST, val);
1635         } else {
1636                 val = V_HWC_EN(win->state);
1637                 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1638         }
1639
1640         return 0;
1641 }
1642
1643 static int vop_layer_update_regs(struct vop_device *vop_dev,
1644                                  struct rk_lcdc_win *win)
1645 {
1646         struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
1647
1648         if (likely(vop_dev->clk_on)) {
1649                 vop_msk_reg(vop_dev, SYS_CTRL,
1650                             V_VOP_STANDBY_EN(vop_dev->standby));
1651                 if ((win->id == VOP_WIN0) || (win->id == VOP_WIN1))
1652                         vop_win_0_1_reg_update(dev_drv, win->id);
1653                 else if ((win->id == VOP_WIN2) || (win->id == VOP_WIN3))
1654                         vop_win_2_3_reg_update(dev_drv, win->id);
1655                 else if (win->id == VOP_HWC)
1656                         vop_hwc_reg_update(dev_drv, win->id);
1657                 vop_cfg_done(vop_dev);
1658         }
1659
1660         DBG(2, "%s for lcdc%d\n", __func__, vop_dev->id);
1661         return 0;
1662 }
1663
1664 static int __maybe_unused vop_mmu_en(struct rk_lcdc_driver *dev_drv)
1665 {
1666         u64 val;
1667         struct vop_device *vop_dev =
1668             container_of(dev_drv, struct vop_device, driver);
1669
1670         if (unlikely(!vop_dev->clk_on)) {
1671                 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
1672                 return 0;
1673         }
1674         if (dev_drv->iommu_enabled) {
1675                 if (!vop_dev->iommu_status && dev_drv->mmu_dev) {
1676                         if (likely(vop_dev->clk_on)) {
1677                                 val = V_VOP_MMU_EN(1);
1678                                 vop_msk_reg(vop_dev, SYS_CTRL, val);
1679                                 val = V_AXI_OUTSTANDING_MAX_NUM(31) |
1680                                         V_AXI_MAX_OUTSTANDING_EN(1);
1681                                 vop_msk_reg(vop_dev, SYS_CTRL1, val);
1682                         }
1683                         vop_dev->iommu_status = 1;
1684                         rockchip_iovmm_activate(dev_drv->dev);
1685                 }
1686         }
1687         return 0;
1688 }
1689
1690 static int vop_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate)
1691 {
1692         int ret = 0, fps = 0;
1693         struct vop_device *vop_dev =
1694             container_of(dev_drv, struct vop_device, driver);
1695         struct rk_screen *screen = dev_drv->cur_screen;
1696 #ifdef CONFIG_RK_FPGA
1697         return 0;
1698 #endif
1699         if (reset_rate)
1700                 ret = clk_set_rate(vop_dev->dclk, screen->mode.pixclock);
1701         if (ret)
1702                 dev_err(dev_drv->dev, "set lcdc%d dclk[%d] failed\n",
1703                         vop_dev->id, screen->mode.pixclock);
1704         vop_dev->pixclock =
1705             div_u64(1000000000000llu, clk_get_rate(vop_dev->dclk));
1706         vop_dev->driver.pixclock = vop_dev->pixclock;
1707
1708         fps = rk_fb_calc_fps(screen, vop_dev->pixclock);
1709         screen->ft = 1000 / fps;
1710         dev_info(vop_dev->dev, "%s: dclk:%lu>>fps:%d ",
1711                  vop_dev->driver.name, clk_get_rate(vop_dev->dclk), fps);
1712         return 0;
1713 }
1714
1715 static int vop_config_timing(struct rk_lcdc_driver *dev_drv)
1716 {
1717         struct vop_device *vop_dev =
1718             container_of(dev_drv, struct vop_device, driver);
1719         struct rk_screen *screen = dev_drv->cur_screen;
1720         u16 hsync_len = screen->mode.hsync_len;
1721         u16 left_margin = screen->mode.left_margin;
1722         u16 right_margin = screen->mode.right_margin;
1723         u16 vsync_len = screen->mode.vsync_len;
1724         u16 upper_margin = screen->mode.upper_margin;
1725         u16 lower_margin = screen->mode.lower_margin;
1726         u16 x_res = screen->mode.xres;
1727         u16 y_res = screen->mode.yres;
1728         u64 val;
1729         u16 h_total, v_total;
1730         u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1731
1732         h_total = hsync_len + left_margin + x_res + right_margin;
1733         v_total = vsync_len + upper_margin + y_res + lower_margin;
1734
1735         val = V_DSP_HS_END(hsync_len) | V_DSP_HTOTAL(h_total);
1736         vop_msk_reg(vop_dev, DSP_HTOTAL_HS_END, val);
1737
1738         val = V_DSP_HACT_END(hsync_len + left_margin + x_res) |
1739             V_DSP_HACT_ST(hsync_len + left_margin);
1740         vop_msk_reg(vop_dev, DSP_HACT_ST_END, val);
1741
1742         if (screen->mode.vmode & FB_VMODE_INTERLACED) {
1743                 /* First Field Timing */
1744                 val = V_DSP_VS_END(vsync_len) |
1745                     V_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1746                                       lower_margin) + y_res + 1);
1747                 vop_msk_reg(vop_dev, DSP_VTOTAL_VS_END, val);
1748
1749                 val = V_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1750                     V_DSP_VACT_ST(vsync_len + upper_margin);
1751                 vop_msk_reg(vop_dev, DSP_VACT_ST_END, val);
1752
1753                 /* Second Field Timing */
1754                 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1755                 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1756                     lower_margin;
1757                 val = V_DSP_VS_ST_F1(vs_st_f1) | V_DSP_VS_END_F1(vs_end_f1);
1758                 vop_msk_reg(vop_dev, DSP_VS_ST_END_F1, val);
1759
1760                 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1761                     lower_margin + 1;
1762                 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1763                     lower_margin + 1;
1764                 val = V_DSP_VACT_END_F1(vact_end_f1) |
1765                         V_DSP_VACT_ST_F1(vact_st_f1);
1766                 vop_msk_reg(vop_dev, DSP_VACT_ST_END_F1, val);
1767                 vop_msk_reg(vop_dev, DSP_CTRL0,
1768                             V_DSP_INTERLACE(1) | V_DSP_FIELD_POL(0));
1769
1770                 val = V_DSP_LINE_FLAG_NUM_0(lower_margin ?
1771                                             vact_end_f1 : vact_end_f1 - 1);
1772
1773                 val |= V_DSP_LINE_FLAG_NUM_1(lower_margin ?
1774                                              vact_end_f1 : vact_end_f1 - 1);
1775                 vop_msk_reg(vop_dev, LINE_FLAG, val);
1776         } else {
1777                 val = V_DSP_VS_END(vsync_len) | V_DSP_VTOTAL(v_total);
1778                 vop_msk_reg(vop_dev, DSP_VTOTAL_VS_END, val);
1779
1780                 val = V_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1781                     V_DSP_VACT_ST(vsync_len + upper_margin);
1782                 vop_msk_reg(vop_dev, DSP_VACT_ST_END, val);
1783
1784                 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_INTERLACE(0) |
1785                             V_DSP_FIELD_POL(0));
1786
1787                 val = V_DSP_LINE_FLAG_NUM_0(vsync_len + upper_margin + y_res) |
1788                         V_DSP_LINE_FLAG_NUM_1(vsync_len + upper_margin + y_res);
1789                 vop_msk_reg(vop_dev, LINE_FLAG, val);
1790         }
1791         vop_post_cfg(dev_drv);
1792         if ((x_res <= VOP_INPUT_MAX_WIDTH / 2) && (vop_dev->id == 0))
1793                 vop_msk_reg(vop_dev, SYS_CTRL, V_POST_LB_MODE(1));
1794         else
1795                 vop_msk_reg(vop_dev, SYS_CTRL, V_POST_LB_MODE(0));
1796
1797         return 0;
1798 }
1799
1800 static void vop_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1801 {
1802         struct vop_device *vop_dev =
1803             container_of(dev_drv, struct vop_device, driver);
1804         u32 bcsh_ctrl;
1805
1806         vop_msk_reg(vop_dev, SYS_CTRL, V_OVERLAY_MODE(dev_drv->overlay_mode));
1807         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1808                 if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1809                         vop_msk_reg(vop_dev, BCSH_CTRL,
1810                                     V_BCSH_Y2R_EN(0) | V_BCSH_R2Y_EN(0));
1811                 else            /* YUV2RGB */
1812                         vop_msk_reg(vop_dev, BCSH_CTRL, V_BCSH_Y2R_EN(1) |
1813                                     V_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1814                                     V_BCSH_R2Y_EN(0));
1815         } else {
1816                 /* overlay_mode=VOP_RGB_DOMAIN */
1817                 /* bypass  --need check,if bcsh close? */
1818                 if (dev_drv->output_color == COLOR_RGB) {
1819                         bcsh_ctrl = vop_readl(vop_dev, BCSH_CTRL);
1820                         if (((bcsh_ctrl & MASK(BCSH_EN)) == 1) ||
1821                             (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1822                                 vop_msk_reg(vop_dev, BCSH_CTRL,
1823                                             V_BCSH_R2Y_EN(1) |
1824                                             V_BCSH_Y2R_EN(1));
1825                         else
1826                                 vop_msk_reg(vop_dev, BCSH_CTRL,
1827                                             V_BCSH_R2Y_EN(0) |
1828                                             V_BCSH_Y2R_EN(0));
1829                 } else {
1830                         /* RGB2YUV */
1831                         vop_msk_reg(vop_dev, BCSH_CTRL,
1832                                     V_BCSH_R2Y_EN(1) |
1833                                     V_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1834                                     V_BCSH_Y2R_EN(0));
1835                 }
1836         }
1837 }
1838
1839 static int vop_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1840                                u16 *yact, int *format, u32 *dsp_addr,
1841                                int *ymirror)
1842 {
1843         struct vop_device *vop_dev =
1844                         container_of(dev_drv, struct vop_device, driver);
1845         u32 val;
1846
1847         spin_lock(&vop_dev->reg_lock);
1848
1849         val = vop_readl(vop_dev, WIN0_ACT_INFO);
1850         *xact = (val & MASK(WIN0_ACT_WIDTH)) + 1;
1851         *yact = ((val & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1;
1852
1853         val = vop_readl(vop_dev, WIN0_CTRL0);
1854         *format = (val & MASK(WIN0_DATA_FMT)) >> 1;
1855         *ymirror = (val & MASK(WIN0_Y_MIR_EN)) >> 22;
1856         *dsp_addr = vop_readl(vop_dev, WIN0_YRGB_MST);
1857
1858         spin_unlock(&vop_dev->reg_lock);
1859
1860         return 0;
1861 }
1862
1863 static int vop_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1864                            int format, u16 xact, u16 yact, u16 xvir,
1865                            int ymirror)
1866 {
1867         struct vop_device *vop_dev =
1868                         container_of(dev_drv, struct vop_device, driver);
1869         int swap = (format == RGB888) ? 1 : 0;
1870         struct rk_lcdc_win *win = dev_drv->win[0];
1871         u64 val;
1872
1873         val = V_WIN0_DATA_FMT(format) | V_WIN0_RB_SWAP(swap) |
1874                 V_WIN0_Y_MIR_EN(ymirror);
1875         vop_msk_reg(vop_dev, WIN0_CTRL0, val);
1876
1877         vop_msk_reg(vop_dev, WIN0_VIR, V_WIN0_VIR_STRIDE(xvir));
1878         vop_writel(vop_dev, WIN0_ACT_INFO, V_WIN0_ACT_WIDTH(xact - 1) |
1879                    V_WIN0_ACT_HEIGHT(yact - 1));
1880
1881         vop_writel(vop_dev, WIN0_YRGB_MST, rgb_mst);
1882
1883         vop_cfg_done(vop_dev);
1884
1885         if (format == RGB888)
1886                 win->area[0].format = BGR888;
1887         else
1888                 win->area[0].format = format;
1889
1890         win->ymirror = ymirror;
1891         win->state = 1;
1892         win->last_state = 1;
1893
1894         return 0;
1895 }
1896
1897 static int vop_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1898 {
1899         u16 face = 0;
1900         u16 dclk_ddr = 0;
1901         struct vop_device *vop_dev =
1902             container_of(dev_drv, struct vop_device, driver);
1903         struct rk_screen *screen = dev_drv->cur_screen;
1904         u64 val = 0;
1905
1906         if (unlikely(!vop_dev->clk_on)) {
1907                 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
1908                 return 0;
1909         }
1910
1911         if (!vop_dev->standby && initscreen && (dev_drv->first_frame != 1))
1912                 flush_kthread_worker(&dev_drv->update_regs_worker);
1913
1914         spin_lock(&vop_dev->reg_lock);
1915         if (likely(vop_dev->clk_on)) {
1916                 switch (screen->face) {
1917                 case OUT_P565:
1918                         face = OUT_P565;
1919                         val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) |
1920                                 V_PRE_DITHER_DOWN_EN(1) |
1921                                 V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(0);
1922                         break;
1923                 case OUT_P666:
1924                         face = OUT_P666;
1925                         val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) |
1926                                 V_PRE_DITHER_DOWN_EN(1) |
1927                                 V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(1);
1928                         break;
1929                 case OUT_D888_P565:
1930                         face = OUT_P888;
1931                         val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) |
1932                                 V_PRE_DITHER_DOWN_EN(1) |
1933                                 V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(0);
1934                         break;
1935                 case OUT_D888_P666:
1936                         face = OUT_P888;
1937                         val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) |
1938                                 V_PRE_DITHER_DOWN_EN(1) |
1939                                 V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(1);
1940                         break;
1941                 case OUT_P888:
1942                         face = OUT_P888;
1943                         val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1)
1944                                 | V_PRE_DITHER_DOWN_EN(1) |
1945                                 V_DITHER_DOWN_SEL(0) | V_DITHER_DOWN_MODE(0);
1946                         break;
1947                 case OUT_YUV_420:
1948                         face = OUT_YUV_420;
1949                         dclk_ddr = 1;
1950                         val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) |
1951                                 V_PRE_DITHER_DOWN_EN(1) |
1952                                 V_DITHER_DOWN_SEL(0) |
1953                                 V_DITHER_DOWN_MODE(0);
1954                         break;
1955                 case OUT_YUV_420_10BIT:
1956                         face = OUT_YUV_420;
1957                         dclk_ddr = 1;
1958                         val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) |
1959                                 V_PRE_DITHER_DOWN_EN(0) |
1960                                 V_DITHER_DOWN_SEL(0) |
1961                                 V_DITHER_DOWN_MODE(0);
1962                         break;
1963                 case OUT_P101010:
1964                         face = OUT_P101010;
1965                         val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) |
1966                                 V_PRE_DITHER_DOWN_EN(0) |
1967                                 V_DITHER_DOWN_SEL(0) |
1968                                 V_DITHER_DOWN_MODE(0);
1969                         break;
1970                 default:
1971                         dev_err(vop_dev->dev, "un supported screen face[%d]!\n",
1972                                 screen->face);
1973                         break;
1974                 }
1975
1976                 vop_msk_reg(vop_dev, DSP_CTRL1, val);
1977                 switch (screen->type) {
1978                 case SCREEN_TVOUT:
1979                         val = V_SW_UV_OFFSET_EN(1) | V_SW_IMD_TVE_DCLK_EN(1) |
1980                                 V_SW_IMD_TVE_DCLK_EN(1) |
1981                                 V_SW_IMD_TVE_DCLK_POL(1) |
1982                                 V_SW_GENLOCK(1) | V_SW_DAC_SEL(1);
1983                         if (screen->mode.xres == 720 &&
1984                             screen->mode.yres == 576)
1985                                 val |= V_SW_TVE_MODE(1);
1986                         else
1987                                 val |= V_SW_TVE_MODE(0);
1988                         vop_msk_reg(vop_dev, SYS_CTRL, val);
1989                         break;
1990                 case SCREEN_HDMI:
1991                         if ((VOP_CHIP(vop_dev) == VOP_RK3399) &&
1992                             ((screen->face == OUT_P888) ||
1993                              (screen->face == OUT_P101010))) {
1994                                 if (vop_dev->id == 0)
1995                                         face = OUT_P101010; /*RGB 10bit output*/
1996                                 else
1997                                         face = OUT_P888;
1998                         }
1999                         val = V_HDMI_OUT_EN(1) | V_SW_UV_OFFSET_EN(0);
2000                         vop_msk_reg(vop_dev, SYS_CTRL, val);
2001                         break;
2002                 case SCREEN_RGB:
2003                 case SCREEN_LVDS:
2004                         val = V_RGB_OUT_EN(1);
2005                         vop_msk_reg(vop_dev, SYS_CTRL, val);
2006                         break;
2007                 case SCREEN_MIPI:
2008                         val = V_MIPI_OUT_EN(1);
2009                         vop_msk_reg(vop_dev, SYS_CTRL, val);
2010                         break;
2011                 case SCREEN_DUAL_MIPI:
2012                         val = V_MIPI_OUT_EN(1) | V_MIPI_DUAL_CHANNEL_EN(1);
2013                         vop_msk_reg(vop_dev, SYS_CTRL, val);
2014                         break;
2015                 case SCREEN_EDP:
2016                         if ((VOP_CHIP(vop_dev) == VOP_RK3399) &&
2017                             (vop_dev->id == 0))
2018                                 face = OUT_P101010;
2019                         val = V_EDP_OUT_EN(1);
2020                         vop_msk_reg(vop_dev, SYS_CTRL, val);
2021                         break;
2022                 default:
2023                         dev_err(vop_dev->dev, "un supported interface[%d]!\n",
2024                                 screen->type);
2025                         break;
2026                 }
2027                 val = V_HDMI_HSYNC_POL(screen->pin_hsync) |
2028                         V_HDMI_VSYNC_POL(screen->pin_vsync) |
2029                         V_HDMI_DEN_POL(screen->pin_den) |
2030                         V_HDMI_DCLK_POL(screen->pin_dclk);
2031                 /*hsync vsync den dclk polo,dither */
2032                 vop_msk_reg(vop_dev, DSP_CTRL1, val);
2033
2034                 if (screen->color_mode == COLOR_RGB)
2035                         dev_drv->overlay_mode = VOP_RGB_DOMAIN;
2036                 else
2037                         dev_drv->overlay_mode = VOP_YUV_DOMAIN;
2038
2039 #ifndef CONFIG_RK_FPGA
2040                 /*
2041                  * Todo:
2042                  * writel_relaxed(v, RK_GRF_VIRT + vop_GRF_SOC_CON7);
2043                  *  move to  lvds driver
2044                  */
2045                 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
2046 #endif
2047                 val = V_DSP_OUT_MODE(face) | V_DSP_DCLK_DDR(dclk_ddr) |
2048                     V_DSP_BG_SWAP(screen->swap_gb) |
2049                     V_DSP_RB_SWAP(screen->swap_rb) |
2050                     V_DSP_RG_SWAP(screen->swap_rg) |
2051                     V_DSP_DELTA_SWAP(screen->swap_delta) |
2052                     V_DSP_DUMMY_SWAP(screen->swap_dumy) | V_DSP_OUT_ZERO(0) |
2053                     V_DSP_BLANK_EN(0) | V_DSP_BLACK_EN(0) |
2054                     V_DSP_X_MIR_EN(screen->x_mirror) |
2055                     V_DSP_Y_MIR_EN(screen->y_mirror);
2056                 val |= V_SW_CORE_DCLK_SEL(!!screen->pixelrepeat);
2057                 if (screen->mode.vmode & FB_VMODE_INTERLACED)
2058                         val |= V_SW_HDMI_CLK_I_SEL(1);
2059                 else
2060                         val |= V_SW_HDMI_CLK_I_SEL(0);
2061                 vop_msk_reg(vop_dev, DSP_CTRL0, val);
2062
2063                 if (screen->mode.vmode & FB_VMODE_INTERLACED)
2064                         vop_msk_reg(vop_dev, SYS_CTRL1, V_REG_DONE_FRM(1));
2065                 else
2066                         vop_msk_reg(vop_dev, SYS_CTRL1, V_REG_DONE_FRM(0));
2067                 /* BG color */
2068                 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
2069                         val = V_DSP_OUT_RGB_YUV(1);
2070                         vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
2071                         val = V_DSP_BG_BLUE(0x200) | V_DSP_BG_GREEN(0x40) |
2072                                 V_DSP_BG_RED(0x200);
2073                         vop_msk_reg(vop_dev, DSP_BG, val);
2074                 } else {
2075                         val = V_DSP_OUT_RGB_YUV(0);
2076                         vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
2077                         val = V_DSP_BG_BLUE(0x55) | V_DSP_BG_GREEN(0x55) |
2078                                 V_DSP_BG_RED(0x55);
2079                         vop_msk_reg(vop_dev, DSP_BG, val);
2080                 }
2081                 dev_drv->output_color = screen->color_mode;
2082                 vop_bcsh_path_sel(dev_drv);
2083                 vop_config_timing(dev_drv);
2084                 vop_cfg_done(vop_dev);
2085         }
2086         spin_unlock(&vop_dev->reg_lock);
2087         vop_set_dclk(dev_drv, 1);
2088         if (screen->type != SCREEN_HDMI && screen->type != SCREEN_TVOUT &&
2089             dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2090                 dev_drv->trsm_ops->enable();
2091         if (screen->init)
2092                 screen->init();
2093
2094         return 0;
2095 }
2096
2097 static int vop_early_suspend(struct rk_lcdc_driver *dev_drv);
2098 static int vop_early_resume(struct rk_lcdc_driver *dev_drv);
2099 /*enable layer,open:1,enable;0 disable*/
2100 static void vop_layer_enable(struct vop_device *vop_dev,
2101                              unsigned int win_id, bool open)
2102 {
2103         spin_lock(&vop_dev->reg_lock);
2104         if (likely(vop_dev->clk_on) &&
2105             vop_dev->driver.win[win_id]->state != open) {
2106                 if (open) {
2107                         if (!vop_dev->atv_layer_cnt) {
2108                                 dev_info(vop_dev->dev,
2109                                          "wakeup from standby!\n");
2110                                 vop_dev->standby = 0;
2111                         }
2112                         vop_dev->atv_layer_cnt |= (1 << win_id);
2113                 } else {
2114                         if (vop_dev->atv_layer_cnt & (1 << win_id))
2115                                 vop_dev->atv_layer_cnt &= ~(1 << win_id);
2116                 }
2117                 vop_dev->driver.win[win_id]->state = open;
2118                 if (!open) {
2119                         vop_layer_update_regs(vop_dev,
2120                                               vop_dev->driver.win[win_id]);
2121                         vop_cfg_done(vop_dev);
2122                 }
2123         }
2124         spin_unlock(&vop_dev->reg_lock);
2125         /* if no layer used,disable lcdc */
2126         if (vop_dev->prop == EXTEND) {
2127                 if (!vop_dev->atv_layer_cnt && !open) {
2128                         vop_early_suspend(&vop_dev->driver);
2129                         dev_info(vop_dev->dev,
2130                                  "no layer is used,go to standby!\n");
2131                         vop_dev->standby = 1;
2132                 } else if (open) {
2133                         vop_early_resume(&vop_dev->driver);
2134                         dev_info(vop_dev->dev, "wake up from standby!\n");
2135                 }
2136         }
2137
2138 }
2139
2140 static int vop_enable_irq(struct rk_lcdc_driver *dev_drv)
2141 {
2142         struct vop_device *vop_dev = container_of(dev_drv,
2143                                                     struct vop_device, driver);
2144         u64 val;
2145         /* struct rk_screen *screen = dev_drv->cur_screen; */
2146
2147         vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, INTR_MASK);
2148
2149         val = INTR_FS | INTR_LINE_FLAG0 | INTR_BUS_ERROR | INTR_LINE_FLAG1 |
2150                 INTR_WIN0_EMPTY | INTR_WIN1_EMPTY | INTR_HWC_EMPTY |
2151                 INTR_POST_BUF_EMPTY;
2152         val |= val << 16;
2153
2154         vop_msk_reg(vop_dev, INTR_EN0, val);
2155
2156         return 0;
2157 }
2158
2159 static int vop_open(struct rk_lcdc_driver *dev_drv, int win_id,
2160                     bool open)
2161 {
2162         struct vop_device *vop_dev =
2163             container_of(dev_drv, struct vop_device, driver);
2164
2165         /* enable clk,when first layer open */
2166         if ((open) && (!vop_dev->atv_layer_cnt)) {
2167                 /* rockchip_set_system_status(sys_status); */
2168                 vop_pre_init(dev_drv);
2169                 vop_clk_enable(vop_dev);
2170                 vop_enable_irq(dev_drv);
2171                 if (dev_drv->iommu_enabled) {
2172                         if (!dev_drv->mmu_dev) {
2173                                 dev_drv->mmu_dev =
2174                                     rk_fb_get_sysmmu_device_by_compatible
2175                                     (dev_drv->mmu_dts_name);
2176                                 if (dev_drv->mmu_dev) {
2177                                         rk_fb_platform_set_sysmmu
2178                                             (dev_drv->mmu_dev, dev_drv->dev);
2179                                 } else {
2180                                         dev_err(dev_drv->dev,
2181                                                 "fail get rk iommu device\n");
2182                                         return -1;
2183                                 }
2184                         }
2185                 }
2186                 if ((support_uboot_display() && (vop_dev->prop == PRMRY)))
2187                         vop_set_dclk(dev_drv, 0);
2188                 else
2189                         vop_load_screen(dev_drv, 1);
2190                 if (dev_drv->bcsh.enable)
2191                         vop_set_bcsh(dev_drv, 1);
2192                 vop_set_lut(dev_drv, dev_drv->cur_screen->dsp_lut);
2193                 vop_set_cabc(dev_drv, dev_drv->cur_screen->cabc_lut);
2194         }
2195
2196         if (win_id < dev_drv->lcdc_win_num)
2197                 vop_layer_enable(vop_dev, win_id, open);
2198         else
2199                 dev_err(vop_dev->dev, "invalid win id:%d\n", win_id);
2200
2201         dev_drv->first_frame = 0;
2202         return 0;
2203 }
2204
2205 static int win_0_1_display(struct vop_device *vop_dev,
2206                            struct rk_lcdc_win *win)
2207 {
2208         u32 y_addr;
2209         u32 uv_addr;
2210         unsigned int off;
2211
2212         off = win->id * 0x40;
2213         /*win->smem_start + win->y_offset; */
2214         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2215         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
2216         DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
2217             vop_dev->id, win->id, y_addr, uv_addr);
2218         DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
2219             win->area[0].y_offset, win->area[0].c_offset);
2220         spin_lock(&vop_dev->reg_lock);
2221         if (likely(vop_dev->clk_on)) {
2222                 win->area[0].y_addr = y_addr;
2223                 win->area[0].uv_addr = uv_addr;
2224                 vop_writel(vop_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
2225                 vop_writel(vop_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
2226                 if (win->area[0].fbdc_en == 1)
2227                         vop_writel(vop_dev, AFBCD0_HDR_PTR,
2228                                    win->area[0].y_addr);
2229         }
2230         spin_unlock(&vop_dev->reg_lock);
2231
2232         return 0;
2233 }
2234
2235 static int win_2_3_display(struct vop_device *vop_dev,
2236                            struct rk_lcdc_win *win)
2237 {
2238         u32 i, y_addr;
2239         unsigned int off;
2240
2241         off = (win->id - 2) * 0x50;
2242         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2243         DBG(2, "lcdc[%d]:win[%d]:", vop_dev->id, win->id);
2244
2245         if (likely(vop_dev->clk_on)) {
2246                 for (i = 0; i < win->area_num; i++) {
2247                         DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2248                             i, win->area[i].y_addr, win->area[i].y_offset);
2249                         win->area[i].y_addr =
2250                             win->area[i].smem_start + win->area[i].y_offset;
2251                         }
2252                 spin_lock(&vop_dev->reg_lock);
2253                 vop_writel(vop_dev, WIN2_MST0 + off, win->area[0].y_addr);
2254                 vop_writel(vop_dev, WIN2_MST1 + off, win->area[1].y_addr);
2255                 vop_writel(vop_dev, WIN2_MST2 + off, win->area[2].y_addr);
2256                 vop_writel(vop_dev, WIN2_MST3 + off, win->area[3].y_addr);
2257                 if (win->area[0].fbdc_en == 1)
2258                         vop_writel(vop_dev, AFBCD0_HDR_PTR,
2259                                    win->area[0].y_addr);
2260                 spin_unlock(&vop_dev->reg_lock);
2261         }
2262         return 0;
2263 }
2264
2265 static int hwc_display(struct vop_device *vop_dev, struct rk_lcdc_win *win)
2266 {
2267         u32 y_addr;
2268
2269         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2270         DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2271             vop_dev->id, __func__, y_addr);
2272         spin_lock(&vop_dev->reg_lock);
2273         if (likely(vop_dev->clk_on)) {
2274                 win->area[0].y_addr = y_addr;
2275                 vop_writel(vop_dev, HWC_MST, win->area[0].y_addr);
2276         }
2277         spin_unlock(&vop_dev->reg_lock);
2278
2279         return 0;
2280 }
2281
2282 static int vop_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2283 {
2284         struct vop_device *vop_dev =
2285             container_of(dev_drv, struct vop_device, driver);
2286         struct rk_lcdc_win *win = NULL;
2287         struct rk_screen *screen = dev_drv->cur_screen;
2288
2289         win = dev_drv->win[win_id];
2290         if (!screen) {
2291                 dev_err(dev_drv->dev, "screen is null!\n");
2292                 return -ENOENT;
2293         }
2294         if (unlikely(!vop_dev->clk_on)) {
2295                 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
2296                 return 0;
2297         }
2298         if (win_id == 0) {
2299                 win_0_1_display(vop_dev, win);
2300         } else if (win_id == 1) {
2301                 win_0_1_display(vop_dev, win);
2302         } else if (win_id == 2) {
2303                 win_2_3_display(vop_dev, win);
2304         } else if (win_id == 3) {
2305                 win_2_3_display(vop_dev, win);
2306         } else if (win_id == 4) {
2307                 hwc_display(vop_dev, win);
2308         } else {
2309                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2310                 return -EINVAL;
2311         }
2312
2313         return 0;
2314 }
2315
2316 static int vop_cal_scl_fac(struct rk_lcdc_win *win, struct rk_screen *screen)
2317 {
2318         u16 srcW = 0;
2319         u16 srcH = 0;
2320         u16 dstW = 0;
2321         u16 dstH = 0;
2322         u16 yrgb_srcW = 0;
2323         u16 yrgb_srcH = 0;
2324         u16 yrgb_dstW = 0;
2325         u16 yrgb_dstH = 0;
2326         u32 yrgb_vscalednmult = 0;
2327         u32 yrgb_xscl_factor = 0;
2328         u32 yrgb_yscl_factor = 0;
2329         u8 yrgb_vsd_bil_gt2 = 0;
2330         u8 yrgb_vsd_bil_gt4 = 0;
2331
2332         u16 cbcr_srcW = 0;
2333         u16 cbcr_srcH = 0;
2334         u16 cbcr_dstW = 0;
2335         u16 cbcr_dstH = 0;
2336         u32 cbcr_vscalednmult = 0;
2337         u32 cbcr_xscl_factor = 0;
2338         u32 cbcr_yscl_factor = 0;
2339         u8 cbcr_vsd_bil_gt2 = 0;
2340         u8 cbcr_vsd_bil_gt4 = 0;
2341         u8 yuv_fmt = 0;
2342
2343         srcW = win->area[0].xact;
2344         if ((screen->mode.vmode & FB_VMODE_INTERLACED) &&
2345             (win->area[0].yact == 2 * win->area[0].ysize)) {
2346                 srcH = win->area[0].yact / 2;
2347                 yrgb_vsd_bil_gt2 = 1;
2348                 cbcr_vsd_bil_gt2 = 1;
2349         } else {
2350                 srcH = win->area[0].yact;
2351         }
2352         dstW = win->area[0].xsize;
2353         dstH = win->area[0].ysize;
2354
2355         /*yrgb scl mode */
2356         yrgb_srcW = srcW;
2357         yrgb_srcH = srcH;
2358         yrgb_dstW = dstW;
2359         yrgb_dstH = dstH;
2360         if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2361                 pr_err("ERROR: yrgb scale exceed 8,");
2362                 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2363                        yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2364         }
2365         if (yrgb_srcW < yrgb_dstW)
2366                 win->yrgb_hor_scl_mode = SCALE_UP;
2367         else if (yrgb_srcW > yrgb_dstW)
2368                 win->yrgb_hor_scl_mode = SCALE_DOWN;
2369         else
2370                 win->yrgb_hor_scl_mode = SCALE_NONE;
2371
2372         if (yrgb_srcH < yrgb_dstH)
2373                 win->yrgb_ver_scl_mode = SCALE_UP;
2374         else if (yrgb_srcH > yrgb_dstH)
2375                 win->yrgb_ver_scl_mode = SCALE_DOWN;
2376         else
2377                 win->yrgb_ver_scl_mode = SCALE_NONE;
2378
2379         /*cbcr scl mode */
2380         switch (win->area[0].format) {
2381         case YUV422:
2382         case YUYV422:
2383         case UYVY422:
2384         case YUV422_A:
2385                 cbcr_srcW = srcW / 2;
2386                 cbcr_dstW = dstW;
2387                 cbcr_srcH = srcH;
2388                 cbcr_dstH = dstH;
2389                 yuv_fmt = 1;
2390                 break;
2391         case YUV420:
2392         case YUYV420:
2393         case UYVY420:
2394         case YUV420_A:
2395         case YUV420_NV21:
2396                 cbcr_srcW = srcW / 2;
2397                 cbcr_dstW = dstW;
2398                 cbcr_srcH = srcH / 2;
2399                 cbcr_dstH = dstH;
2400                 yuv_fmt = 1;
2401                 break;
2402         case YUV444:
2403         case YUV444_A:
2404                 cbcr_srcW = srcW;
2405                 cbcr_dstW = dstW;
2406                 cbcr_srcH = srcH;
2407                 cbcr_dstH = dstH;
2408                 yuv_fmt = 1;
2409                 break;
2410         default:
2411                 cbcr_srcW = 0;
2412                 cbcr_dstW = 0;
2413                 cbcr_srcH = 0;
2414                 cbcr_dstH = 0;
2415                 yuv_fmt = 0;
2416                 break;
2417         }
2418         if (yuv_fmt) {
2419                 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2420                     (cbcr_dstH * 8 <= cbcr_srcH)) {
2421                         pr_err("ERROR: cbcr scale exceed 8,");
2422                         pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2423                                cbcr_srcH, cbcr_dstW, cbcr_dstH);
2424                 }
2425         }
2426
2427         if (cbcr_srcW < cbcr_dstW)
2428                 win->cbr_hor_scl_mode = SCALE_UP;
2429         else if (cbcr_srcW > cbcr_dstW)
2430                 win->cbr_hor_scl_mode = SCALE_DOWN;
2431         else
2432                 win->cbr_hor_scl_mode = SCALE_NONE;
2433
2434         if (cbcr_srcH < cbcr_dstH)
2435                 win->cbr_ver_scl_mode = SCALE_UP;
2436         else if (cbcr_srcH > cbcr_dstH)
2437                 win->cbr_ver_scl_mode = SCALE_DOWN;
2438         else
2439                 win->cbr_ver_scl_mode = SCALE_NONE;
2440
2441         /* line buffer mode */
2442         if ((win->area[0].format == YUV422) ||
2443             (win->area[0].format == YUV420) ||
2444             (win->area[0].format == YUYV422) ||
2445             (win->area[0].format == YUYV420) ||
2446             (win->area[0].format == UYVY422) ||
2447             (win->area[0].format == UYVY420) ||
2448             (win->area[0].format == YUV420_NV21) ||
2449             (win->area[0].format == YUV422_A) ||
2450             (win->area[0].format == YUV420_A)) {
2451                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2452                         if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2453                             (cbcr_dstW == 0))
2454                                 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2455                                        cbcr_dstW);
2456                         else if (cbcr_dstW > 1280)
2457                                 win->win_lb_mode = LB_YUV_3840X5;
2458                         else
2459                                 win->win_lb_mode = LB_YUV_2560X8;
2460                 } else {        /* SCALE_UP or SCALE_NONE */
2461                         if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2462                             (cbcr_srcW == 0))
2463                                 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2464                                        cbcr_srcW);
2465                         else if (cbcr_srcW > 1280)
2466                                 win->win_lb_mode = LB_YUV_3840X5;
2467                         else
2468                                 win->win_lb_mode = LB_YUV_2560X8;
2469                 }
2470         } else {
2471                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2472                         if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2473                             (yrgb_dstW == 0))
2474                                 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2475                         else if (yrgb_dstW > 2560)
2476                                 win->win_lb_mode = LB_RGB_3840X2;
2477                         else if (yrgb_dstW > 1920)
2478                                 win->win_lb_mode = LB_RGB_2560X4;
2479                         else if (yrgb_dstW > 1280)
2480                                 win->win_lb_mode = LB_RGB_1920X5;
2481                         else
2482                                 win->win_lb_mode = LB_RGB_1280X8;
2483                 } else {        /* SCALE_UP or SCALE_NONE */
2484                         if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2485                             (yrgb_srcW == 0))
2486                                 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2487                         else if (yrgb_srcW > 2560)
2488                                 win->win_lb_mode = LB_RGB_3840X2;
2489                         else if (yrgb_srcW > 1920)
2490                                 win->win_lb_mode = LB_RGB_2560X4;
2491                         else if (yrgb_srcW > 1280)
2492                                 win->win_lb_mode = LB_RGB_1920X5;
2493                         else
2494                                 win->win_lb_mode = LB_RGB_1280X8;
2495                 }
2496         }
2497         DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2498
2499         /* vsd/vsu scale ALGORITHM */
2500         win->yrgb_hsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2501         win->cbr_hsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2502         win->yrgb_vsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2503         win->cbr_vsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2504
2505         /* if (VOP_CHIP(vop_dev) == VOP_RK3399) { */
2506         if ((win->area[0].format == YUYV422) ||
2507             (win->area[0].format == YUYV420) ||
2508             (win->area[0].format == UYVY422) ||
2509             (win->area[0].format == UYVY420)) {
2510                 yrgb_vscalednmult =
2511                         vop_get_hard_ware_vskiplines(yrgb_srcH, yrgb_dstH);
2512                 if (yrgb_vscalednmult == 4) {
2513                         yrgb_vsd_bil_gt4 = 1;
2514                         yrgb_vsd_bil_gt2 = 0;
2515                 } else if (yrgb_vscalednmult == 2) {
2516                         yrgb_vsd_bil_gt4 = 0;
2517                         yrgb_vsd_bil_gt2 = 1;
2518                 } else {
2519                         yrgb_vsd_bil_gt4 = 0;
2520                         yrgb_vsd_bil_gt2 = 0;
2521                 }
2522                 if ((win->area[0].format == YUYV420) ||
2523                     (win->area[0].format == UYVY420)) {
2524                         if ((yrgb_vsd_bil_gt4 == 1) || (yrgb_vsd_bil_gt2 == 1))
2525                                 win->yrgb_vsd_mode = SCALE_DOWN_AVG;
2526                 }
2527
2528                 cbcr_vscalednmult =
2529                         vop_get_hard_ware_vskiplines(cbcr_srcH, cbcr_dstH);
2530                 if (cbcr_vscalednmult == 4) {
2531                         cbcr_vsd_bil_gt4 = 1;
2532                         cbcr_vsd_bil_gt2 = 0;
2533                 } else if (cbcr_vscalednmult == 2) {
2534                         cbcr_vsd_bil_gt4 = 0;
2535                         cbcr_vsd_bil_gt2 = 1;
2536                 } else {
2537                         cbcr_vsd_bil_gt4 = 0;
2538                         cbcr_vsd_bil_gt2 = 0;
2539                 }
2540                 if ((win->area[0].format == YUYV420) ||
2541                     (win->area[0].format == UYVY420)) {
2542                         if ((cbcr_vsd_bil_gt4 == 1) || (cbcr_vsd_bil_gt2 == 1))
2543                                 win->cbr_vsd_mode = SCALE_DOWN_AVG;
2544                 }
2545                 /* CBCR vsd_mode must same to YRGB for YUYV when gt2 or gt4 */
2546                 if ((cbcr_vsd_bil_gt4 == 1) || (cbcr_vsd_bil_gt2 == 1)) {
2547                         if (win->yrgb_vsd_mode != win->cbr_vsd_mode)
2548                                 win->cbr_vsd_mode = win->yrgb_vsd_mode;
2549                 }
2550         }
2551         /* 3399 yuyv support*/
2552         if (win->ymirror == 1) {
2553                 if (win->yrgb_vsd_mode == SCALE_DOWN_AVG)
2554                         pr_info("y_mirror enable, y-vsd AVG mode unsupprot\n");
2555                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2556         }
2557         if (screen->mode.vmode & FB_VMODE_INTERLACED) {
2558                 if (win->yrgb_vsd_mode == SCALE_DOWN_AVG)
2559                         pr_info("interlace mode, y-vsd AVG mode unsupprot\n");
2560                 /* interlace mode must bill */
2561                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2562                 win->cbr_vsd_mode = SCALE_DOWN_BIL;
2563         }
2564         switch (win->win_lb_mode) {
2565         case LB_YUV_3840X5:
2566         case LB_YUV_2560X8:
2567         case LB_RGB_1920X5:
2568         case LB_RGB_1280X8:
2569                 win->yrgb_vsu_mode = SCALE_UP_BIC;
2570                 win->cbr_vsu_mode = SCALE_UP_BIC;
2571                 break;
2572         case LB_RGB_3840X2:
2573                 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2574                         pr_err("ERROR : not allow yrgb ver scale\n");
2575                 if (win->cbr_ver_scl_mode != SCALE_NONE)
2576                         pr_err("ERROR : not allow cbcr ver scale\n");
2577                 break;
2578         case LB_RGB_2560X4:
2579                 win->yrgb_vsu_mode = SCALE_UP_BIL;
2580                 win->cbr_vsu_mode = SCALE_UP_BIL;
2581                 break;
2582         default:
2583                 pr_info("%s:un supported win_lb_mode:%d\n",
2584                         __func__, win->win_lb_mode);
2585                 break;
2586         }
2587
2588         if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2589             (win->area[0].fbdc_en == 1)) {
2590                 /* in this pattern,use bil mode,not support souble scd,
2591                  * use avg mode, support double scd, but aclk should be
2592                  * bigger than dclk.
2593                  */
2594                 if (yrgb_srcH >= 2 * yrgb_dstH) {
2595                         pr_err("ERROR : fbdc mode,not support y scale down:");
2596                         pr_err("srcH[%d] > 2 *dstH[%d]\n",
2597                                yrgb_srcH, yrgb_dstH);
2598                 }
2599         }
2600         DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2601             win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2602             win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2603
2604         /* SCALE FACTOR */
2605
2606         /* (1.1)YRGB HOR SCALE FACTOR */
2607         switch (win->yrgb_hor_scl_mode) {
2608         case SCALE_NONE:
2609                 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2610                 break;
2611         case SCALE_UP:
2612                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2613                 break;
2614         case SCALE_DOWN:
2615                 switch (win->yrgb_hsd_mode) {
2616                 case SCALE_DOWN_BIL:
2617                         yrgb_xscl_factor =
2618                             GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2619                         break;
2620                 case SCALE_DOWN_AVG:
2621                         yrgb_xscl_factor =
2622                             GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2623                         break;
2624                 default:
2625                         pr_info("%s:un supported yrgb_hsd_mode:%d\n", __func__,
2626                                 win->yrgb_hsd_mode);
2627                         break;
2628                 }
2629                 break;
2630         default:
2631                 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2632                         __func__, win->yrgb_hor_scl_mode);
2633                 break;
2634         }
2635
2636         /* (1.2)YRGB VER SCALE FACTOR */
2637         switch (win->yrgb_ver_scl_mode) {
2638         case SCALE_NONE:
2639                 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2640                 break;
2641         case SCALE_UP:
2642                 switch (win->yrgb_vsu_mode) {
2643                 case SCALE_UP_BIL:
2644                         yrgb_yscl_factor =
2645                             GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2646                         break;
2647                 case SCALE_UP_BIC:
2648                         if (yrgb_srcH < 3) {
2649                                 pr_err("yrgb_srcH should be");
2650                                 pr_err(" greater than 3 !!!\n");
2651                         }
2652                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2653                                                                 yrgb_dstH);
2654                         break;
2655                 default:
2656                         pr_info("%s:un support yrgb_vsu_mode:%d\n",
2657                                 __func__, win->yrgb_vsu_mode);
2658                         break;
2659                 }
2660                 break;
2661         case SCALE_DOWN:
2662                 switch (win->yrgb_vsd_mode) {
2663                 case SCALE_DOWN_BIL:
2664                         yrgb_vscalednmult =
2665                             vop_get_hard_ware_vskiplines(yrgb_srcH, yrgb_dstH);
2666                         yrgb_yscl_factor =
2667                             GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2668                                                            yrgb_vscalednmult);
2669                         if (yrgb_yscl_factor >= 0x2000) {
2670                                 pr_err("yrgb_yscl_factor should less 0x2000");
2671                                 pr_err("yrgb_yscl_factor=%4x;\n",
2672                                        yrgb_yscl_factor);
2673                         }
2674                         if (yrgb_vscalednmult == 4) {
2675                                 yrgb_vsd_bil_gt4 = 1;
2676                                 yrgb_vsd_bil_gt2 = 0;
2677                         } else if (yrgb_vscalednmult == 2) {
2678                                 yrgb_vsd_bil_gt4 = 0;
2679                                 yrgb_vsd_bil_gt2 = 1;
2680                         } else {
2681                                 yrgb_vsd_bil_gt4 = 0;
2682                                 yrgb_vsd_bil_gt2 = 0;
2683                         }
2684                         break;
2685                 case SCALE_DOWN_AVG:
2686                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2687                                                                  yrgb_dstH);
2688                         break;
2689                 default:
2690                         pr_info("%s:un support yrgb_vsd_mode:%d\n",
2691                                 __func__, win->yrgb_vsd_mode);
2692                         break;
2693                 }               /*win->yrgb_vsd_mode */
2694                 break;
2695         default:
2696                 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2697                         __func__, win->yrgb_ver_scl_mode);
2698                 break;
2699         }
2700         win->scale_yrgb_x = yrgb_xscl_factor;
2701         win->scale_yrgb_y = yrgb_yscl_factor;
2702         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2703         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2704         DBG(1, "yrgb:h_fac=%d, V_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2705             yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2706
2707         /*(2.1)CBCR HOR SCALE FACTOR */
2708         switch (win->cbr_hor_scl_mode) {
2709         case SCALE_NONE:
2710                 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2711                 break;
2712         case SCALE_UP:
2713                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2714                 break;
2715         case SCALE_DOWN:
2716                 switch (win->cbr_hsd_mode) {
2717                 case SCALE_DOWN_BIL:
2718                         cbcr_xscl_factor =
2719                             GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2720                         break;
2721                 case SCALE_DOWN_AVG:
2722                         cbcr_xscl_factor =
2723                             GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2724                         break;
2725                 default:
2726                         pr_info("%s:un support cbr_hsd_mode:%d\n",
2727                                 __func__, win->cbr_hsd_mode);
2728                         break;
2729                 }
2730                 break;
2731         default:
2732                 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2733                         __func__, win->cbr_hor_scl_mode);
2734                 break;
2735         }                       /*win->cbr_hor_scl_mode */
2736
2737         /* (2.2)CBCR VER SCALE FACTOR */
2738         switch (win->cbr_ver_scl_mode) {
2739         case SCALE_NONE:
2740                 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2741                 break;
2742         case SCALE_UP:
2743                 switch (win->cbr_vsu_mode) {
2744                 case SCALE_UP_BIL:
2745                         cbcr_yscl_factor =
2746                             GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2747                         break;
2748                 case SCALE_UP_BIC:
2749                         if (cbcr_srcH < 3) {
2750                                 pr_err("cbcr_srcH should be ");
2751                                 pr_err("greater than 3 !!!\n");
2752                         }
2753                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2754                                                                 cbcr_dstH);
2755                         break;
2756                 default:
2757                         pr_info("%s:un support cbr_vsu_mode:%d\n",
2758                                 __func__, win->cbr_vsu_mode);
2759                         break;
2760                 }
2761                 break;
2762         case SCALE_DOWN:
2763                 switch (win->cbr_vsd_mode) {
2764                 case SCALE_DOWN_BIL:
2765                         cbcr_vscalednmult =
2766                             vop_get_hard_ware_vskiplines(cbcr_srcH, cbcr_dstH);
2767                         cbcr_yscl_factor =
2768                             GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2769                                                            cbcr_vscalednmult);
2770                         if (cbcr_yscl_factor >= 0x2000) {
2771                                 pr_err("cbcr_yscl_factor should be less ");
2772                                 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2773                                        cbcr_yscl_factor);
2774                         }
2775
2776                         if (cbcr_vscalednmult == 4) {
2777                                 cbcr_vsd_bil_gt4 = 1;
2778                                 cbcr_vsd_bil_gt2 = 0;
2779                         } else if (cbcr_vscalednmult == 2) {
2780                                 cbcr_vsd_bil_gt4 = 0;
2781                                 cbcr_vsd_bil_gt2 = 1;
2782                         } else {
2783                                 cbcr_vsd_bil_gt4 = 0;
2784                                 cbcr_vsd_bil_gt2 = 0;
2785                         }
2786                         break;
2787                 case SCALE_DOWN_AVG:
2788                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2789                                                                  cbcr_dstH);
2790                         break;
2791                 default:
2792                         pr_info("%s:un support cbr_vsd_mode:%d\n",
2793                                 __func__, win->cbr_vsd_mode);
2794                         break;
2795                 }
2796                 break;
2797         default:
2798                 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2799                         __func__, win->cbr_ver_scl_mode);
2800                 break;
2801         }
2802         win->scale_cbcr_x = cbcr_xscl_factor;
2803         win->scale_cbcr_y = cbcr_yscl_factor;
2804         win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2805         win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2806
2807         DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2808             cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2809         return 0;
2810 }
2811
2812 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2813                      struct rk_lcdc_win_area *area)
2814 {
2815         int pos;
2816
2817         if (screen->x_mirror && mirror_en)
2818                 pr_err("not support both win and global mirror\n");
2819
2820         if ((!mirror_en) && (!screen->x_mirror))
2821                 pos = area->xpos + screen->mode.left_margin +
2822                         screen->mode.hsync_len;
2823         else
2824                 pos = screen->mode.xres - area->xpos -
2825                         area->xsize + screen->mode.left_margin +
2826                         screen->mode.hsync_len;
2827
2828         return pos;
2829 }
2830
2831 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2832                      struct rk_lcdc_win_area *area)
2833 {
2834         int pos;
2835
2836         if (screen->y_mirror && mirror_en)
2837                 pr_err("not support both win and global mirror\n");
2838
2839         if ((!mirror_en) && (!screen->y_mirror))
2840                 pos = area->ypos + screen->mode.upper_margin +
2841                         screen->mode.vsync_len;
2842         else
2843                 pos = screen->mode.yres - area->ypos -
2844                         area->ysize + screen->mode.upper_margin +
2845                         screen->mode.vsync_len;
2846
2847         return pos;
2848 }
2849
2850 static int win_0_1_set_par(struct vop_device *vop_dev,
2851                            struct rk_screen *screen, struct rk_lcdc_win *win)
2852 {
2853         u32 xact = 0, yact = 0, xvir = 0, yvir = 0, xpos = 0, ypos = 0;
2854         u8 fmt_cfg = 0, swap_rb = 0, swap_uv = 0;
2855         char fmt[9] = "NULL";
2856
2857         xpos = dsp_x_pos(win->xmirror, screen, &win->area[0]);
2858         ypos = dsp_y_pos(win->ymirror, screen, &win->area[0]);
2859
2860         spin_lock(&vop_dev->reg_lock);
2861         if (likely(vop_dev->clk_on)) {
2862                 vop_cal_scl_fac(win, screen);
2863                 switch (win->area[0].format) {
2864                 case FBDC_RGB_565:
2865                         fmt_cfg = 2;
2866                         swap_rb = 0;
2867                         win->fmt_10 = 0;
2868                         win->area[0].fbdc_fmt_cfg = AFBDC_FMT_RGB565;
2869                         break;
2870                 case FBDC_ARGB_888:
2871                         fmt_cfg = 0;
2872                         swap_rb = 1;
2873                         win->fmt_10 = 0;
2874                         win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8;
2875                         break;
2876                 case FBDC_ABGR_888:
2877                         fmt_cfg = 0;
2878                         swap_rb = 0;
2879                         win->fmt_10 = 0;
2880                         win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8;
2881                         break;
2882                 case FBDC_RGBX_888:
2883                         fmt_cfg = 0;
2884                         swap_rb = 0;
2885                         win->fmt_10 = 0;
2886                         win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8;
2887                         break;
2888                 case ARGB888:
2889                         fmt_cfg = 0;
2890                         swap_rb = 0;
2891                         win->fmt_10 = 0;
2892                         break;
2893                 case XBGR888:
2894                 case ABGR888:
2895                         fmt_cfg = 0;
2896                         swap_rb = 1;
2897                         win->fmt_10 = 0;
2898                         break;
2899                 case BGR888:
2900                         fmt_cfg = 1;
2901                         swap_rb = 1;
2902                         win->fmt_10 = 0;
2903                         break;
2904                 case RGB888:
2905                         fmt_cfg = 1;
2906                         swap_rb = 0;
2907                         win->fmt_10 = 0;
2908                         break;
2909                 case RGB565:
2910                         fmt_cfg = 2;
2911                         swap_rb = 0;
2912                         win->fmt_10 = 0;
2913                         break;
2914                 case YUV422:
2915                         fmt_cfg = 5;
2916                         swap_rb = 0;
2917                         win->fmt_10 = 0;
2918                         break;
2919                 case YUV420:
2920                         fmt_cfg = 4;
2921                         swap_rb = 0;
2922                         win->fmt_10 = 0;
2923                         break;
2924                 case YUV420_NV21:
2925                         fmt_cfg = 4;
2926                         swap_rb = 0;
2927                         swap_uv = 1;
2928                         win->fmt_10 = 0;
2929                         break;
2930                 case YUV444:
2931                         fmt_cfg = 6;
2932                         swap_rb = 0;
2933                         win->fmt_10 = 0;
2934                         break;
2935                 case YUV422_A:
2936                         fmt_cfg = 5;
2937                         swap_rb = 0;
2938                         win->fmt_10 = 1;
2939                         break;
2940                 case YUV420_A:
2941                         fmt_cfg = 4;
2942                         swap_rb = 0;
2943                         win->fmt_10 = 1;
2944                         break;
2945                 case YUV444_A:
2946                         fmt_cfg = 6;
2947                         swap_rb = 0;
2948                         win->fmt_10 = 1;
2949                         break;
2950                 case YUYV422:
2951                         fmt_cfg = 0;
2952                         swap_rb = 0;
2953                         win->fmt_10 = 0;
2954                         win->area[0].yuyv_fmt = 1;
2955                         break;
2956                 case YUYV420:
2957                         fmt_cfg = 1;
2958                         swap_rb = 0;
2959                         win->fmt_10 = 0;
2960                         win->area[0].yuyv_fmt = 1;
2961                         break;
2962                 case UYVY422:
2963                         fmt_cfg = 2;
2964                         swap_rb = 0;
2965                         win->fmt_10 = 0;
2966                         win->area[0].yuyv_fmt = 1;
2967                         break;
2968                 case UYVY420:
2969                         fmt_cfg = 3;
2970                         swap_rb = 0;
2971                         win->fmt_10 = 0;
2972                         win->area[0].yuyv_fmt = 1;
2973                         break;
2974                 default:
2975                         dev_err(vop_dev->dev, "%s:unsupport format[%d]!\n",
2976                                 __func__, win->area[0].format);
2977                         break;
2978                 }
2979                 win->area[0].fmt_cfg = fmt_cfg;
2980                 win->area[0].swap_rb = swap_rb;
2981                 win->area[0].swap_uv = swap_uv;
2982                 win->area[0].dsp_stx = xpos;
2983                 win->area[0].dsp_sty = ypos;
2984                 xact = win->area[0].xact;
2985                 yact = win->area[0].yact;
2986                 xvir = win->area[0].xvir;
2987                 yvir = win->area[0].yvir;
2988         }
2989         if (win->area[0].fbdc_en)
2990                 vop_init_fbdc_config(vop_dev, win->id);
2991         vop_win_0_1_reg_update(&vop_dev->driver, win->id);
2992         spin_unlock(&vop_dev->reg_lock);
2993
2994         DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2995             vop_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2996             xact, yact, win->area[0].xsize);
2997         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2998             win->area[0].ysize, xvir, yvir, xpos, ypos);
2999
3000         return 0;
3001 }
3002
3003 static int win_2_3_set_par(struct vop_device *vop_dev,
3004                            struct rk_screen *screen, struct rk_lcdc_win *win)
3005 {
3006         int i;
3007         u8 fmt_cfg = 0, swap_rb = 0;
3008         char fmt[9] = "NULL";
3009
3010         if (VOP_CHIP(vop_dev) == VOP_RK322X) {
3011                 pr_err("rk3228 not support win2/3 set par\n");
3012                 return -EINVAL;
3013         }
3014         if (win->ymirror) {
3015                 pr_err("win[%d] not support y mirror\n", win->id);
3016                 return -EINVAL;
3017         }
3018         spin_lock(&vop_dev->reg_lock);
3019         if (likely(vop_dev->clk_on)) {
3020                 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", vop_dev->id, win->id);
3021                 for (i = 0; i < win->area_num; i++) {
3022                         switch (win->area[i].format) {
3023                         case FBDC_RGB_565:
3024                                 fmt_cfg = 2;
3025                                 swap_rb = 0;
3026                                 win->fmt_10 = 0;
3027                                 win->area[0].fbdc_fmt_cfg = 0x05;
3028                                 break;
3029                         case FBDC_ARGB_888:
3030                                 fmt_cfg = 0;
3031                                 swap_rb = 0;
3032                                 win->fmt_10 = 0;
3033                                 win->area[0].fbdc_fmt_cfg = 0x0c;
3034                                 break;
3035                         case FBDC_RGBX_888:
3036                                 fmt_cfg = 0;
3037                                 swap_rb = 0;
3038                                 win->fmt_10 = 0;
3039                                 win->area[0].fbdc_fmt_cfg = 0x3a;
3040                                 break;
3041                         case ARGB888:
3042                                 fmt_cfg = 0;
3043                                 swap_rb = 0;
3044                                 break;
3045                         case XBGR888:
3046                         case ABGR888:
3047                                 fmt_cfg = 0;
3048                                 swap_rb = 1;
3049                                 break;
3050                         case RGB888:
3051                                 fmt_cfg = 1;
3052                                 swap_rb = 0;
3053                                 break;
3054                         case RGB565:
3055                                 fmt_cfg = 2;
3056                                 swap_rb = 0;
3057                                 break;
3058                         default:
3059                                 dev_err(vop_dev->driver.dev,
3060                                         "%s:un supported format!\n", __func__);
3061                                 spin_unlock(&vop_dev->reg_lock);
3062                                 return -EINVAL;
3063                         }
3064                         win->area[i].fmt_cfg = fmt_cfg;
3065                         win->area[i].swap_rb = swap_rb;
3066                         win->area[i].dsp_stx = dsp_x_pos(win->xmirror, screen,
3067                                                          &win->area[i]);
3068                         win->area[i].dsp_sty = dsp_y_pos(win->ymirror, screen,
3069                                                          &win->area[i]);
3070                         if (((win->area[i].xact != win->area[i].xsize) ||
3071                              (win->area[i].yact != win->area[i].ysize)) &&
3072                             (screen->mode.vmode == FB_VMODE_NONINTERLACED)) {
3073                                 pr_err("win[%d]->area[%d],not support scale\n",
3074                                        win->id, i);
3075                                 pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
3076                                        win->area[i].xact, win->area[i].yact,
3077                                        win->area[i].xsize, win->area[i].ysize);
3078                                 win->area[i].xsize = win->area[i].xact;
3079                                 win->area[i].ysize = win->area[i].yact;
3080                         }
3081                         DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
3082                             get_format_string(win->area[i].format, fmt),
3083                             win->area[i].xsize, win->area[i].ysize,
3084                             win->area[i].xpos, win->area[i].ypos);
3085                 }
3086         }
3087         if (win->area[0].fbdc_en)
3088                 vop_init_fbdc_config(vop_dev, win->id);
3089         vop_win_2_3_reg_update(&vop_dev->driver, win->id);
3090         spin_unlock(&vop_dev->reg_lock);
3091         return 0;
3092 }
3093
3094 static int hwc_set_par(struct vop_device *vop_dev,
3095                        struct rk_screen *screen, struct rk_lcdc_win *win)
3096 {
3097         u32 xact = 0, yact = 0, xvir = 0, yvir = 0, xpos = 0, ypos = 0;
3098         u8 fmt_cfg = 0, swap_rb = 0;
3099         char fmt[9] = "NULL";
3100
3101         xpos = win->area[0].xpos + screen->mode.left_margin +
3102             screen->mode.hsync_len;
3103         ypos = win->area[0].ypos + screen->mode.upper_margin +
3104             screen->mode.vsync_len;
3105
3106         spin_lock(&vop_dev->reg_lock);
3107         if (likely(vop_dev->clk_on)) {
3108                 switch (win->area[0].format) {
3109                 case ARGB888:
3110                         fmt_cfg = 0;
3111                         swap_rb = 0;
3112                         break;
3113                 case XBGR888:
3114                 case ABGR888:
3115                         fmt_cfg = 0;
3116                         swap_rb = 1;
3117                         break;
3118                 case RGB888:
3119                         fmt_cfg = 1;
3120                         swap_rb = 0;
3121                         break;
3122                 case RGB565:
3123                         fmt_cfg = 2;
3124                         swap_rb = 0;
3125                         break;
3126                 default:
3127                         dev_err(vop_dev->dev, "%s:un supported format[%d]!\n",
3128                                 __func__, win->area[0].format);
3129                         break;
3130                 }
3131                 win->area[0].fmt_cfg = fmt_cfg;
3132                 win->area[0].swap_rb = swap_rb;
3133                 win->area[0].dsp_stx = xpos;
3134                 win->area[0].dsp_sty = ypos;
3135                 xact = win->area[0].xact;
3136                 yact = win->area[0].yact;
3137                 xvir = win->area[0].xvir;
3138                 yvir = win->area[0].yvir;
3139         }
3140         vop_hwc_reg_update(&vop_dev->driver, 4);
3141         spin_unlock(&vop_dev->reg_lock);
3142
3143         DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
3144             vop_dev->id, __func__, get_format_string(win->area[0].format, fmt),
3145             xact, yact, win->area[0].xsize);
3146         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
3147             win->area[0].ysize, xvir, yvir, xpos, ypos);
3148         return 0;
3149 }
3150
3151 static int vop_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
3152 {
3153         struct vop_device *vop_dev =
3154             container_of(dev_drv, struct vop_device, driver);
3155         struct rk_lcdc_win *win = NULL;
3156         struct rk_screen *screen = dev_drv->cur_screen;
3157
3158         if (unlikely(!vop_dev->clk_on)) {
3159                 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
3160                 return 0;
3161         }
3162         win = dev_drv->win[win_id];
3163         if (win)
3164         switch (win_id) {
3165         case 0:
3166                 win_0_1_set_par(vop_dev, screen, win);
3167                 break;
3168         case 1:
3169                 win_0_1_set_par(vop_dev, screen, win);
3170                 break;
3171         case 2:
3172                 win_2_3_set_par(vop_dev, screen, win);
3173                 break;
3174         case 3:
3175                 win_2_3_set_par(vop_dev, screen, win);
3176                 break;
3177         case 4:
3178                 hwc_set_par(vop_dev, screen, win);
3179                 break;
3180         default:
3181                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
3182                 break;
3183         }
3184         return 0;
3185 }
3186
3187 static int vop_set_writeback(struct rk_lcdc_driver *dev_drv)
3188 {
3189         struct vop_device *vop_dev =
3190             container_of(dev_drv, struct vop_device, driver);
3191         int output_color = dev_drv->output_color;
3192         struct rk_screen *screen = dev_drv->cur_screen;
3193         struct rk_fb_reg_wb_data *wb_data;
3194         int xact = screen->mode.xres;
3195         int yact = screen->mode.yres;
3196         u32 fmt_cfg;
3197         int xsize, ysize;
3198         u64 v;
3199
3200         if (unlikely(!vop_dev->clk_on)) {
3201                 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
3202                 return 0;
3203         }
3204         wb_data = &dev_drv->wb_data;
3205         if ((wb_data->xsize == 0) || (wb_data->ysize == 0))
3206                 return 0;
3207
3208         xsize = wb_data->xsize;
3209         ysize = wb_data->ysize;
3210
3211         /*
3212          * RGB overlay mode support ARGB888, RGB888, RGB565, NV12,
3213          * but YUV overlay mode only support NV12, it's hard to judge RGB
3214          * or YUV overlay mode by userspace, so here force only support
3215          * NV12 mode.
3216          */
3217         if (wb_data->data_format != YUV420 && output_color != COLOR_RGB) {
3218                 pr_err("writeback only support NV12 when overlay is not RGB\n");
3219                 return -EINVAL;
3220         }
3221
3222         if (ysize != yact && ysize != (yact / 2)) {
3223                 pr_err("WriteBack only support yact=%d, ysize=%d\n",
3224                        yact, ysize);
3225                 return -EINVAL;
3226         }
3227
3228         switch (wb_data->data_format) {
3229         case ARGB888:
3230         case ABGR888:
3231         case XRGB888:
3232         case XBGR888:
3233                 fmt_cfg = 0;
3234                 break;
3235         case RGB888:
3236         case BGR888:
3237                 fmt_cfg = 1;
3238                 break;
3239         case RGB565:
3240         case BGR565:
3241                 fmt_cfg = 2;
3242                 break;
3243         case YUV420:
3244                 fmt_cfg = 8;
3245                 break;
3246         default:
3247                 pr_info("unsupport fmt: %d\n", wb_data->data_format);
3248                 return -EINVAL;
3249         }
3250
3251         v = V_WB_EN(wb_data->state) | V_WB_FMT(fmt_cfg) | V_WB_RGB2YUV_MODE(1) |
3252                 V_WB_XPSD_BIL_EN(xact != xsize) |
3253                 V_WB_YTHROW_EN(ysize == (yact / 2)) |
3254                 V_WB_YTHROW_MODE(0);
3255
3256         v |= V_WB_RGB2YUV_EN((output_color == COLOR_RGB) &&
3257                              (wb_data->data_format == YUV420));
3258
3259         vop_msk_reg(vop_dev, WB_CTRL0, v);
3260
3261         v = V_WB_WIDTH(xsize) | V_WB_XPSD_BIL_FACTOR((xact << 12) / xsize);
3262
3263         vop_msk_reg(vop_dev, WB_CTRL1, v);
3264
3265         vop_writel(vop_dev, WB_YRGB_MST, wb_data->smem_start);
3266         if (wb_data->data_format == YUV420)
3267                 vop_writel(vop_dev, WB_CBR_MST, wb_data->smem_start);
3268
3269         return 0;
3270 }
3271
3272 static int vop_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
3273                      unsigned long arg, int win_id)
3274 {
3275         struct vop_device *vop_dev =
3276                         container_of(dev_drv, struct vop_device, driver);
3277         u32 panel_size[2];
3278         void __user *argp = (void __user *)arg;
3279         struct color_key_cfg clr_key_cfg;
3280
3281         switch (cmd) {
3282         case RK_FBIOGET_PANEL_SIZE:
3283                 panel_size[0] = vop_dev->screen->mode.xres;
3284                 panel_size[1] = vop_dev->screen->mode.yres;
3285                 if (copy_to_user(argp, panel_size, 8))
3286                         return -EFAULT;
3287                 break;
3288         case RK_FBIOPUT_COLOR_KEY_CFG:
3289                 if (copy_from_user(&clr_key_cfg, argp, sizeof(clr_key_cfg)))
3290                         return -EFAULT;
3291                 vop_clr_key_cfg(dev_drv);
3292                 vop_writel(vop_dev, WIN0_COLOR_KEY,
3293                            clr_key_cfg.win0_color_key_cfg);
3294                 vop_writel(vop_dev, WIN1_COLOR_KEY,
3295                            clr_key_cfg.win1_color_key_cfg);
3296                 break;
3297
3298         default:
3299                 break;
3300         }
3301         return 0;
3302 }
3303
3304 static int vop_get_backlight_device(struct rk_lcdc_driver *dev_drv)
3305 {
3306         struct vop_device *vop_dev = container_of(dev_drv,
3307                                                     struct vop_device, driver);
3308         struct device_node *backlight;
3309         struct property *prop;
3310         u32 *brightness_levels;
3311         u32 length, max, last;
3312
3313         if (vop_dev->backlight)
3314                 return 0;
3315         backlight = of_parse_phandle(vop_dev->dev->of_node, "backlight", 0);
3316         if (backlight) {
3317                 vop_dev->backlight = of_find_backlight_by_node(backlight);
3318                 if (!vop_dev->backlight)
3319                         dev_info(vop_dev->dev, "No find backlight device\n");
3320         } else {
3321                 dev_info(vop_dev->dev, "No find backlight device node\n");
3322         }
3323         prop = of_find_property(backlight, "brightness-levels", &length);
3324         if (!prop)
3325                 return -EINVAL;
3326         max = length / sizeof(u32);
3327         last = max - 1;
3328         brightness_levels = kmalloc(256, GFP_KERNEL);
3329         if (brightness_levels)
3330                 return -ENOMEM;
3331
3332         if (!of_property_read_u32_array(backlight, "brightness-levels",
3333                                         brightness_levels, max)) {
3334                 if (brightness_levels[0] > brightness_levels[last])
3335                         dev_drv->cabc_pwm_pol = 1;/*negative*/
3336                 else
3337                         dev_drv->cabc_pwm_pol = 0;/*positive*/
3338         } else {
3339                 dev_info(vop_dev->dev,
3340                          "Can not read brightness-levels value\n");
3341         }
3342
3343         kfree(brightness_levels);
3344
3345         return 0;
3346 }
3347
3348 static int vop_early_suspend(struct rk_lcdc_driver *dev_drv)
3349 {
3350         struct vop_device *vop_dev =
3351             container_of(dev_drv, struct vop_device, driver);
3352
3353         if (dev_drv->suspend_flag)
3354                 return 0;
3355
3356         dev_drv->suspend_flag = 1;
3357         /* ensure suspend_flag take effect on multi process */
3358         smp_wmb();
3359         flush_kthread_worker(&dev_drv->update_regs_worker);
3360
3361         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3362                 dev_drv->trsm_ops->disable();
3363
3364         if (likely(vop_dev->clk_on)) {
3365                 spin_lock(&vop_dev->reg_lock);
3366                 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLANK_EN(1));
3367                 vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, INTR_MASK);
3368                 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_OUT_ZERO(1));
3369                 vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(1));
3370                 vop_cfg_done(vop_dev);
3371
3372                 if (dev_drv->iommu_enabled && dev_drv->mmu_dev) {
3373                         mdelay(50);
3374                         rockchip_iovmm_deactivate(dev_drv->dev);
3375                 }
3376
3377                 spin_unlock(&vop_dev->reg_lock);
3378         }
3379
3380         vop_clk_disable(vop_dev);
3381         rk_disp_pwr_disable(dev_drv);
3382
3383         return 0;
3384 }
3385
3386 static int vop_early_resume(struct rk_lcdc_driver *dev_drv)
3387 {
3388         struct vop_device *vop_dev =
3389             container_of(dev_drv, struct vop_device, driver);
3390
3391         if (!dev_drv->suspend_flag)
3392                 return 0;
3393         rk_disp_pwr_enable(dev_drv);
3394
3395         vop_clk_enable(vop_dev);
3396         spin_lock(&vop_dev->reg_lock);
3397         memcpy(vop_dev->regs, vop_dev->regsbak, vop_dev->len);
3398         spin_unlock(&vop_dev->reg_lock);
3399
3400         vop_set_lut(dev_drv, dev_drv->cur_screen->dsp_lut);
3401         vop_set_cabc(dev_drv, dev_drv->cur_screen->cabc_lut);
3402         spin_lock(&vop_dev->reg_lock);
3403
3404         vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_OUT_ZERO(0));
3405         vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(0));
3406         vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLANK_EN(0));
3407         vop_cfg_done(vop_dev);
3408         spin_unlock(&vop_dev->reg_lock);
3409
3410         if (dev_drv->iommu_enabled && dev_drv->mmu_dev) {
3411                 /* win address maybe effect after next frame start,
3412                  * but mmu maybe effect right now, so we delay 50ms
3413                  */
3414                 mdelay(50);
3415                 rockchip_iovmm_activate(dev_drv->dev);
3416         }
3417
3418         dev_drv->suspend_flag = 0;
3419
3420         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3421                 dev_drv->trsm_ops->enable();
3422
3423         return 0;
3424 }
3425
3426 static int vop_blank(struct rk_lcdc_driver *dev_drv, int win_id, int blank_mode)
3427 {
3428         switch (blank_mode) {
3429         case FB_BLANK_UNBLANK:
3430                 vop_early_resume(dev_drv);
3431                 break;
3432         case FB_BLANK_NORMAL:
3433                 vop_early_suspend(dev_drv);
3434                 break;
3435         default:
3436                 vop_early_suspend(dev_drv);
3437                 break;
3438         }
3439
3440         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
3441
3442         return 0;
3443 }
3444
3445 static int vop_get_win_state(struct rk_lcdc_driver *dev_drv,
3446                              int win_id, int area_id)
3447 {
3448         struct vop_device *vop_dev =
3449                         container_of(dev_drv, struct vop_device, driver);
3450         u32 area_status = 0, state = 0;
3451
3452         switch (win_id) {
3453         case 0:
3454                 area_status = vop_read_bit(vop_dev, WIN0_CTRL0, V_WIN0_EN(0));
3455                 break;
3456         case 1:
3457                 area_status = vop_read_bit(vop_dev, WIN1_CTRL0, V_WIN1_EN(0));
3458                 break;
3459         case 2:
3460                 if (area_id == 0)
3461                         area_status = vop_read_bit(vop_dev, WIN2_CTRL0,
3462                                                    V_WIN2_MST0_EN(0));
3463                 if (area_id == 1)
3464                         area_status = vop_read_bit(vop_dev, WIN2_CTRL0,
3465                                                    V_WIN2_MST1_EN(0));
3466                 if (area_id == 2)
3467                         area_status = vop_read_bit(vop_dev, WIN2_CTRL0,
3468                                                    V_WIN2_MST2_EN(0));
3469                 if (area_id == 3)
3470                         area_status = vop_read_bit(vop_dev, WIN2_CTRL0,
3471                                                    V_WIN2_MST3_EN(0));
3472                 break;
3473         case 3:
3474                 if (area_id == 0)
3475                         area_status = vop_read_bit(vop_dev, WIN3_CTRL0,
3476                                                    V_WIN3_MST0_EN(0));
3477                 if (area_id == 1)
3478                         area_status = vop_read_bit(vop_dev, WIN3_CTRL0,
3479                                                    V_WIN3_MST1_EN(0));
3480                 if (area_id == 2)
3481                         area_status = vop_read_bit(vop_dev, WIN3_CTRL0,
3482                                                    V_WIN3_MST2_EN(0));
3483                 if (area_id == 3)
3484                         area_status = vop_read_bit(vop_dev, WIN3_CTRL0,
3485                                                    V_WIN3_MST3_EN(0));
3486                 break;
3487         case 4:
3488                 area_status = vop_read_bit(vop_dev, HWC_CTRL0, V_HWC_EN(0));
3489                 break;
3490         default:
3491                 pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n",
3492                        __func__, win_id, area_id);
3493                 break;
3494         }
3495
3496         state = (area_status > 0) ? 1 : 0;
3497         return state;
3498 }
3499
3500 static int vop_get_area_num(struct rk_lcdc_driver *dev_drv,
3501                             unsigned int *area_support)
3502 {
3503         struct vop_device *vop_dev =
3504             container_of(dev_drv, struct vop_device, driver);
3505
3506         area_support[0] = 1;
3507         area_support[1] = 1;
3508
3509         if (VOP_CHIP(vop_dev) == VOP_RK3399) {
3510                 area_support[2] = 4;
3511                 area_support[3] = 4;
3512         }
3513
3514         return 0;
3515 }
3516
3517 /*overlay will be do at regupdate*/
3518 static int vop_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, bool set)
3519 {
3520         struct vop_device *vop_dev =
3521             container_of(dev_drv, struct vop_device, driver);
3522         struct rk_lcdc_win *win = NULL;
3523         int i, ovl = 0;
3524         u64 val;
3525         int z_order_num = 0;
3526         int layer0_sel = 0, layer1_sel = 1, layer2_sel = 2, layer3_sel = 3;
3527
3528         if (swap == 0) {
3529                 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
3530                         win = dev_drv->win[i];
3531                         if (win->state == 1)
3532                                 z_order_num++;
3533                 }
3534                 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
3535                         win = dev_drv->win[i];
3536                         if (win->state == 0)
3537                                 win->z_order = z_order_num++;
3538                         switch (win->z_order) {
3539                         case 0:
3540                                 layer0_sel = win->id;
3541                                 break;
3542                         case 1:
3543                                 layer1_sel = win->id;
3544                                 break;
3545                         case 2:
3546                                 layer2_sel = win->id;
3547                                 break;
3548                         case 3:
3549                                 layer3_sel = win->id;
3550                                 break;
3551                         default:
3552                                 break;
3553                         }
3554                 }
3555         } else {
3556                 layer0_sel = swap % 10;
3557                 layer1_sel = swap / 10 % 10;
3558                 layer2_sel = swap / 100 % 10;
3559                 layer3_sel = swap / 1000;
3560         }
3561
3562         spin_lock(&vop_dev->reg_lock);
3563         if (vop_dev->clk_on) {
3564                 if (set) {
3565                         val = V_DSP_LAYER0_SEL(layer0_sel) |
3566                             V_DSP_LAYER1_SEL(layer1_sel) |
3567                             V_DSP_LAYER2_SEL(layer2_sel) |
3568                             V_DSP_LAYER3_SEL(layer3_sel);
3569                         vop_msk_reg(vop_dev, DSP_CTRL1, val);
3570                 } else {
3571                         layer0_sel = vop_read_bit(vop_dev, DSP_CTRL1,
3572                                                   V_DSP_LAYER0_SEL(0));
3573                         layer1_sel = vop_read_bit(vop_dev, DSP_CTRL1,
3574                                                   V_DSP_LAYER1_SEL(0));
3575                         layer2_sel = vop_read_bit(vop_dev, DSP_CTRL1,
3576                                                   V_DSP_LAYER2_SEL(0));
3577                         layer3_sel = vop_read_bit(vop_dev, DSP_CTRL1,
3578                                                   V_DSP_LAYER3_SEL(0));
3579                         ovl = layer3_sel * 1000 + layer2_sel * 100 +
3580                             layer1_sel * 10 + layer0_sel;
3581                 }
3582         } else {
3583                 ovl = -EPERM;
3584         }
3585         spin_unlock(&vop_dev->reg_lock);
3586
3587         return ovl;
3588 }
3589
3590 static char *vop_format_to_string(int format, char *fmt)
3591 {
3592         if (!fmt)
3593                 return NULL;
3594
3595         switch (format) {
3596         case 0:
3597                 strcpy(fmt, "ARGB888");
3598                 break;
3599         case 1:
3600                 strcpy(fmt, "RGB888");
3601                 break;
3602         case 2:
3603                 strcpy(fmt, "RGB565");
3604                 break;
3605         case 4:
3606                 strcpy(fmt, "YCbCr420");
3607                 break;
3608         case 5:
3609                 strcpy(fmt, "YCbCr422");
3610                 break;
3611         case 6:
3612                 strcpy(fmt, "YCbCr444");
3613         case 8:
3614                 strcpy(fmt, "YUYV422");
3615                 break;
3616         case 9:
3617                 strcpy(fmt, "YUYV420");
3618                 break;
3619         case 10:
3620                 strcpy(fmt, "UYVY422");
3621                 break;
3622         case 11:
3623                 strcpy(fmt, "UYVY420");
3624                 break;
3625         default:
3626                 strcpy(fmt, "invalid\n");
3627                 break;
3628         }
3629         return fmt;
3630 }
3631
3632 static ssize_t vop_get_disp_info(struct rk_lcdc_driver *dev_drv,
3633                                  char *buf, int win_id)
3634 {
3635         struct vop_device *vop_dev =
3636             container_of(dev_drv, struct vop_device, driver);
3637         struct rk_screen *screen = dev_drv->cur_screen;
3638         u16 hsync_len = screen->mode.hsync_len;
3639         u16 left_margin = screen->mode.left_margin;
3640         u16 vsync_len = screen->mode.vsync_len;
3641         u16 upper_margin = screen->mode.upper_margin;
3642         u32 h_pw_bp = hsync_len + left_margin;
3643         u32 v_pw_bp = vsync_len + upper_margin;
3644         u32 fmt_id;
3645         char format_w0[9] = "NULL";
3646         char format_w1[9] = "NULL";
3647         char format_w2_0[9] = "NULL";
3648         char format_w2_1[9] = "NULL";
3649         char format_w2_2[9] = "NULL";
3650         char format_w2_3[9] = "NULL";
3651         char format_w3_0[9] = "NULL";
3652         char format_w3_1[9] = "NULL";
3653         char format_w3_2[9] = "NULL";
3654         char format_w3_3[9] = "NULL";
3655         char dsp_buf[100];
3656         u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3657         u32 y_factor, uv_factor;
3658         u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3659         u8 w0_state, w1_state, w2_state, w3_state;
3660         u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3661         u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3662
3663         u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3664         u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3665         u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3666         u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3667         u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3668         u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3669
3670         u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3671         u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3672         u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3673         u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3674         u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3675         u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3676         u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3677
3678         u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3679         u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3680         u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3681         u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3682         u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3683         u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3684         u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3685         u32 dclk_freq;
3686         int size = 0;
3687
3688         dclk_freq = screen->mode.pixclock;
3689         /*vop_reg_dump(dev_drv); */
3690
3691         spin_lock(&vop_dev->reg_lock);
3692         if (vop_dev->clk_on) {
3693                 zorder = vop_readl(vop_dev, DSP_CTRL1);
3694                 layer0_sel = (zorder & MASK(DSP_LAYER0_SEL)) >> 8;
3695                 layer1_sel = (zorder & MASK(DSP_LAYER1_SEL)) >> 10;
3696                 layer2_sel = (zorder & MASK(DSP_LAYER2_SEL)) >> 12;
3697                 layer3_sel = (zorder & MASK(DSP_LAYER3_SEL)) >> 14;
3698                 /* WIN0 */
3699                 win_ctrl = vop_readl(vop_dev, WIN0_CTRL0);
3700                 w0_state = win_ctrl & MASK(WIN0_EN);
3701                 fmt_id = (win_ctrl & MASK(WIN0_DATA_FMT)) >> 1;
3702                 fmt_id |= (win_ctrl & MASK(WIN0_YUYV)) >> 14; /* yuyv*/
3703                 vop_format_to_string(fmt_id, format_w0);
3704                 vir_info = vop_readl(vop_dev, WIN0_VIR);
3705                 act_info = vop_readl(vop_dev, WIN0_ACT_INFO);
3706                 dsp_info = vop_readl(vop_dev, WIN0_DSP_INFO);
3707                 dsp_st = vop_readl(vop_dev, WIN0_DSP_ST);
3708                 y_factor = vop_readl(vop_dev, WIN0_SCL_FACTOR_YRGB);
3709                 uv_factor = vop_readl(vop_dev, WIN0_SCL_FACTOR_CBR);
3710                 w0_vir_y = vir_info & MASK(WIN0_VIR_STRIDE);
3711                 w0_vir_uv = (vir_info & MASK(WIN0_VIR_STRIDE_UV)) >> 16;
3712                 w0_act_x = (act_info & MASK(WIN0_ACT_WIDTH)) + 1;
3713                 w0_act_y = ((act_info & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1;
3714                 w0_dsp_x = (dsp_info & MASK(WIN0_DSP_WIDTH)) + 1;
3715                 w0_dsp_y = ((dsp_info & MASK(WIN0_DSP_HEIGHT)) >> 16) + 1;
3716                 if (w0_state) {
3717                         w0_st_x = dsp_st & MASK(WIN0_DSP_XST);
3718                         w0_st_y = (dsp_st & MASK(WIN0_DSP_YST)) >> 16;
3719                 }
3720                 w0_y_h_fac = y_factor & MASK(WIN0_HS_FACTOR_YRGB);
3721                 w0_y_v_fac = (y_factor & MASK(WIN0_VS_FACTOR_YRGB)) >> 16;
3722                 w0_uv_h_fac = uv_factor & MASK(WIN0_HS_FACTOR_CBR);
3723                 w0_uv_v_fac = (uv_factor & MASK(WIN0_VS_FACTOR_CBR)) >> 16;
3724
3725                 /* WIN1 */
3726                 win_ctrl = vop_readl(vop_dev, WIN1_CTRL0);
3727                 w1_state = win_ctrl & MASK(WIN1_EN);
3728                 fmt_id = (win_ctrl & MASK(WIN1_DATA_FMT)) >> 1;
3729                 fmt_id |= (win_ctrl & MASK(WIN1_YUYV)) >> 14; /* yuyv*/
3730                 vop_format_to_string(fmt_id, format_w1);
3731                 vir_info = vop_readl(vop_dev, WIN1_VIR);
3732                 act_info = vop_readl(vop_dev, WIN1_ACT_INFO);
3733                 dsp_info = vop_readl(vop_dev, WIN1_DSP_INFO);
3734                 dsp_st = vop_readl(vop_dev, WIN1_DSP_ST);
3735                 y_factor = vop_readl(vop_dev, WIN1_SCL_FACTOR_YRGB);
3736                 uv_factor = vop_readl(vop_dev, WIN1_SCL_FACTOR_CBR);
3737                 w1_vir_y = vir_info & MASK(WIN1_VIR_STRIDE);
3738                 w1_vir_uv = (vir_info & MASK(WIN1_VIR_STRIDE_UV)) >> 16;
3739                 w1_act_x = (act_info & MASK(WIN1_ACT_WIDTH)) + 1;
3740                 w1_act_y = ((act_info & MASK(WIN1_ACT_HEIGHT)) >> 16) + 1;
3741                 w1_dsp_x = (dsp_info & MASK(WIN1_DSP_WIDTH)) + 1;
3742                 w1_dsp_y = ((dsp_info & MASK(WIN1_DSP_HEIGHT)) >> 16) + 1;
3743                 if (w1_state) {
3744                         w1_st_x = dsp_st & MASK(WIN1_DSP_XST);
3745                         w1_st_y = (dsp_st & MASK(WIN1_DSP_YST)) >> 16;
3746                 }
3747                 w1_y_h_fac = y_factor & MASK(WIN1_HS_FACTOR_YRGB);
3748                 w1_y_v_fac = (y_factor & MASK(WIN1_VS_FACTOR_YRGB)) >> 16;
3749                 w1_uv_h_fac = uv_factor & MASK(WIN1_HS_FACTOR_CBR);
3750                 w1_uv_v_fac = (uv_factor & MASK(WIN1_VS_FACTOR_CBR)) >> 16;
3751
3752                 /*WIN2 */
3753                 win_ctrl = vop_readl(vop_dev, WIN2_CTRL0);
3754                 w2_state = win_ctrl & MASK(WIN2_EN);
3755                 w2_0_state = (win_ctrl & 0x10) >> 4;
3756                 w2_1_state = (win_ctrl & 0x100) >> 8;
3757                 w2_2_state = (win_ctrl & 0x1000) >> 12;
3758                 w2_3_state = (win_ctrl & 0x10000) >> 16;
3759                 vir_info = vop_readl(vop_dev, WIN2_VIR0_1);
3760                 w2_0_vir_y = vir_info & MASK(WIN2_VIR_STRIDE0);
3761                 w2_1_vir_y = (vir_info & MASK(WIN2_VIR_STRIDE1)) >> 16;
3762                 vir_info = vop_readl(vop_dev, WIN2_VIR2_3);
3763                 w2_2_vir_y = vir_info & MASK(WIN2_VIR_STRIDE2);
3764                 w2_3_vir_y = (vir_info & MASK(WIN2_VIR_STRIDE3)) >> 16;
3765
3766                 fmt_id = (win_ctrl & MASK(WIN2_DATA_FMT0)) >> 5;
3767                 vop_format_to_string(fmt_id, format_w2_0);
3768                 fmt_id = (win_ctrl & MASK(WIN2_DATA_FMT1)) >> 9;
3769                 vop_format_to_string(fmt_id, format_w2_1);
3770                 fmt_id = (win_ctrl & MASK(WIN2_DATA_FMT2)) >> 13;
3771                 vop_format_to_string(fmt_id, format_w2_2);
3772                 fmt_id = (win_ctrl & MASK(WIN2_DATA_FMT3)) >> 17;
3773                 vop_format_to_string(fmt_id, format_w2_3);
3774
3775                 dsp_info = vop_readl(vop_dev, WIN2_DSP_INFO0);
3776                 dsp_st = vop_readl(vop_dev, WIN2_DSP_ST0);
3777                 w2_0_dsp_x = (dsp_info & MASK(WIN2_DSP_WIDTH0)) + 1;
3778                 w2_0_dsp_y = ((dsp_info & MASK(WIN2_DSP_HEIGHT0)) >> 16) + 1;
3779                 if (w2_0_state) {
3780                         w2_0_st_x = dsp_st & MASK(WIN2_DSP_XST0);
3781                         w2_0_st_y = (dsp_st & MASK(WIN2_DSP_YST0)) >> 16;
3782                 }
3783                 dsp_info = vop_readl(vop_dev, WIN2_DSP_INFO1);
3784                 dsp_st = vop_readl(vop_dev, WIN2_DSP_ST1);
3785                 w2_1_dsp_x = (dsp_info & MASK(WIN2_DSP_WIDTH1)) + 1;
3786                 w2_1_dsp_y = ((dsp_info & MASK(WIN2_DSP_HEIGHT1)) >> 16) + 1;
3787                 if (w2_1_state) {
3788                         w2_1_st_x = dsp_st & MASK(WIN2_DSP_XST1);
3789                         w2_1_st_y = (dsp_st & MASK(WIN2_DSP_YST1)) >> 16;
3790                 }
3791                 dsp_info = vop_readl(vop_dev, WIN2_DSP_INFO2);
3792                 dsp_st = vop_readl(vop_dev, WIN2_DSP_ST2);
3793                 w2_2_dsp_x = (dsp_info & MASK(WIN2_DSP_WIDTH2)) + 1;
3794                 w2_2_dsp_y = ((dsp_info & MASK(WIN2_DSP_HEIGHT2)) >> 16) + 1;
3795                 if (w2_2_state) {
3796                         w2_2_st_x = dsp_st & MASK(WIN2_DSP_XST2);
3797                         w2_2_st_y = (dsp_st & MASK(WIN2_DSP_YST2)) >> 16;
3798                 }
3799                 dsp_info = vop_readl(vop_dev, WIN2_DSP_INFO3);
3800                 dsp_st = vop_readl(vop_dev, WIN2_DSP_ST3);
3801                 w2_3_dsp_x = (dsp_info & MASK(WIN2_DSP_WIDTH3)) + 1;
3802                 w2_3_dsp_y = ((dsp_info & MASK(WIN2_DSP_HEIGHT3)) >> 16) + 1;
3803                 if (w2_3_state) {
3804                         w2_3_st_x = dsp_st & MASK(WIN2_DSP_XST3);
3805                         w2_3_st_y = (dsp_st & MASK(WIN2_DSP_YST3)) >> 16;
3806                 }
3807
3808                 /*WIN3 */
3809                 win_ctrl = vop_readl(vop_dev, WIN3_CTRL0);
3810                 w3_state = win_ctrl & MASK(WIN3_EN);
3811                 w3_0_state = (win_ctrl & 0x10) >> 4;
3812                 w3_1_state = (win_ctrl & 0x100) >> 8;
3813                 w3_2_state = (win_ctrl & 0x1000) >> 12;
3814                 w3_3_state = (win_ctrl & 0x10000) >> 16;
3815                 vir_info = vop_readl(vop_dev, WIN3_VIR0_1);
3816                 w3_0_vir_y = vir_info & MASK(WIN3_VIR_STRIDE0);
3817                 w3_1_vir_y = (vir_info & MASK(WIN3_VIR_STRIDE1)) >> 16;
3818                 vir_info = vop_readl(vop_dev, WIN3_VIR2_3);
3819                 w3_2_vir_y = vir_info & MASK(WIN3_VIR_STRIDE2);
3820                 w3_3_vir_y = (vir_info & MASK(WIN3_VIR_STRIDE3)) >> 16;
3821
3822                 fmt_id = (win_ctrl & MASK(WIN3_DATA_FMT0)) >> 5;
3823                 vop_format_to_string(fmt_id, format_w3_0);
3824                 fmt_id = (win_ctrl & MASK(WIN3_DATA_FMT1)) >> 9;
3825                 vop_format_to_string(fmt_id, format_w3_1);
3826                 fmt_id = (win_ctrl & MASK(WIN3_DATA_FMT2)) >> 13;
3827                 vop_format_to_string(fmt_id, format_w3_2);
3828                 fmt_id = (win_ctrl & MASK(WIN3_DATA_FMT3)) >> 17;
3829                 vop_format_to_string(fmt_id, format_w3_3);
3830
3831                 dsp_info = vop_readl(vop_dev, WIN3_DSP_INFO0);
3832                 dsp_st = vop_readl(vop_dev, WIN3_DSP_ST0);
3833                 w3_0_dsp_x = (dsp_info & MASK(WIN3_DSP_WIDTH0)) + 1;
3834                 w3_0_dsp_y = ((dsp_info & MASK(WIN3_DSP_HEIGHT0)) >> 16) + 1;
3835                 if (w3_0_state) {
3836                         w3_0_st_x = dsp_st & MASK(WIN3_DSP_XST0);
3837                         w3_0_st_y = (dsp_st & MASK(WIN3_DSP_YST0)) >> 16;
3838                 }
3839                 dsp_info = vop_readl(vop_dev, WIN3_DSP_INFO1);
3840                 dsp_st = vop_readl(vop_dev, WIN3_DSP_ST1);
3841                 w3_1_dsp_x = (dsp_info & MASK(WIN3_DSP_WIDTH1)) + 1;
3842                 w3_1_dsp_y = ((dsp_info & MASK(WIN3_DSP_HEIGHT1)) >> 16) + 1;
3843                 if (w3_1_state) {
3844                         w3_1_st_x = dsp_st & MASK(WIN3_DSP_XST1);
3845                         w3_1_st_y = (dsp_st & MASK(WIN3_DSP_YST1)) >> 16;
3846                 }
3847                 dsp_info = vop_readl(vop_dev, WIN3_DSP_INFO2);
3848                 dsp_st = vop_readl(vop_dev, WIN3_DSP_ST2);
3849                 w3_2_dsp_x = (dsp_info & MASK(WIN3_DSP_WIDTH2)) + 1;
3850                 w3_2_dsp_y = ((dsp_info & MASK(WIN3_DSP_HEIGHT2)) >> 16) + 1;
3851                 if (w3_2_state) {
3852                         w3_2_st_x = dsp_st & MASK(WIN3_DSP_XST2);
3853                         w3_2_st_y = (dsp_st & MASK(WIN3_DSP_YST2)) >> 16;
3854                 }
3855                 dsp_info = vop_readl(vop_dev, WIN3_DSP_INFO3);
3856                 dsp_st = vop_readl(vop_dev, WIN3_DSP_ST3);
3857                 w3_3_dsp_x = (dsp_info & MASK(WIN3_DSP_WIDTH3)) + 1;
3858                 w3_3_dsp_y = ((dsp_info & MASK(WIN3_DSP_HEIGHT3)) >> 16) + 1;
3859                 if (w3_3_state) {
3860                         w3_3_st_x = dsp_st & MASK(WIN3_DSP_XST3);
3861                         w3_3_st_y = (dsp_st & MASK(WIN3_DSP_YST3)) >> 16;
3862                 }
3863         } else {
3864                 spin_unlock(&vop_dev->reg_lock);
3865                 return -EPERM;
3866         }
3867         spin_unlock(&vop_dev->reg_lock);
3868         size += snprintf(dsp_buf, 80,
3869                 "z-order:\n  win[%d]\n  win[%d]\n  win[%d]\n  win[%d]\n",
3870                 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3871         strcat(buf, dsp_buf);
3872         memset(dsp_buf, 0, sizeof(dsp_buf));
3873         /* win0 */
3874         size += snprintf(dsp_buf, 80,
3875                  "win0:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3876                  w0_state, format_w0, w0_vir_y, w0_vir_uv);
3877         strcat(buf, dsp_buf);
3878         memset(dsp_buf, 0, sizeof(dsp_buf));
3879
3880         size += snprintf(dsp_buf, 80,
3881                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3882                  w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3883         strcat(buf, dsp_buf);
3884         memset(dsp_buf, 0, sizeof(dsp_buf));
3885
3886         size += snprintf(dsp_buf, 80,
3887                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3888                  w0_st_x - h_pw_bp, w0_st_y - v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3889         strcat(buf, dsp_buf);
3890         memset(dsp_buf, 0, sizeof(dsp_buf));
3891
3892         size += snprintf(dsp_buf, 80,
3893                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3894                  w0_uv_h_fac, w0_uv_v_fac, vop_readl(vop_dev, WIN0_YRGB_MST),
3895                  vop_readl(vop_dev, WIN0_CBR_MST));
3896         strcat(buf, dsp_buf);
3897         memset(dsp_buf, 0, sizeof(dsp_buf));
3898
3899         /* win1 */
3900         size += snprintf(dsp_buf, 80,
3901                  "win1:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3902                  w1_state, format_w1, w1_vir_y, w1_vir_uv);
3903         strcat(buf, dsp_buf);
3904         memset(dsp_buf, 0, sizeof(dsp_buf));
3905
3906         size += snprintf(dsp_buf, 80,
3907                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3908                  w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3909         strcat(buf, dsp_buf);
3910         memset(dsp_buf, 0, sizeof(dsp_buf));
3911
3912         size += snprintf(dsp_buf, 80,
3913                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3914                  w1_st_x - h_pw_bp, w1_st_y - v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3915         strcat(buf, dsp_buf);
3916         memset(dsp_buf, 0, sizeof(dsp_buf));
3917
3918         size += snprintf(dsp_buf, 80,
3919                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3920                  w1_uv_h_fac, w1_uv_v_fac, vop_readl(vop_dev, WIN1_YRGB_MST),
3921                  vop_readl(vop_dev, WIN1_CBR_MST));
3922         strcat(buf, dsp_buf);
3923         memset(dsp_buf, 0, sizeof(dsp_buf));
3924
3925         /*win2*/
3926         size += snprintf(dsp_buf, 80,
3927                  "win2:\n  state:%d\n",
3928                  w2_state);
3929         strcat(buf, dsp_buf);
3930         memset(dsp_buf, 0, sizeof(dsp_buf));
3931         /*area 0*/
3932         size += snprintf(dsp_buf, 80,
3933                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3934                  w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3935         strcat(buf, dsp_buf);
3936         memset(dsp_buf, 0, sizeof(dsp_buf));
3937         size += snprintf(dsp_buf, 80,
3938                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3939                  w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3940                  vop_readl(vop_dev, WIN2_MST0));
3941         strcat(buf, dsp_buf);
3942         memset(dsp_buf, 0, sizeof(dsp_buf));
3943
3944         /*area 1*/
3945         size += snprintf(dsp_buf, 80,
3946                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3947                  w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3948         strcat(buf, dsp_buf);
3949         memset(dsp_buf, 0, sizeof(dsp_buf));
3950         size += snprintf(dsp_buf, 80,
3951                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3952                  w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3953                  vop_readl(vop_dev, WIN2_MST1));
3954         strcat(buf, dsp_buf);
3955         memset(dsp_buf, 0, sizeof(dsp_buf));
3956
3957         /*area 2*/
3958         size += snprintf(dsp_buf, 80,
3959                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3960                  w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3961         strcat(buf, dsp_buf);
3962         memset(dsp_buf, 0, sizeof(dsp_buf));
3963         size += snprintf(dsp_buf, 80,
3964                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3965                  w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3966                  vop_readl(vop_dev, WIN2_MST2));
3967         strcat(buf, dsp_buf);
3968         memset(dsp_buf, 0, sizeof(dsp_buf));
3969
3970         /*area 3*/
3971         size += snprintf(dsp_buf, 80,
3972                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3973                  w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3974         strcat(buf, dsp_buf);
3975         memset(dsp_buf, 0, sizeof(dsp_buf));
3976         size += snprintf(dsp_buf, 80,
3977                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3978                  w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3979                  vop_readl(vop_dev, WIN2_MST3));
3980         strcat(buf, dsp_buf);
3981         memset(dsp_buf, 0, sizeof(dsp_buf));
3982
3983         /*win3*/
3984         size += snprintf(dsp_buf, 80,
3985                  "win3:\n  state:%d\n",
3986                  w3_state);
3987         strcat(buf, dsp_buf);
3988         memset(dsp_buf, 0, sizeof(dsp_buf));
3989         /*area 0*/
3990         size += snprintf(dsp_buf, 80,
3991                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3992                  w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
3993         strcat(buf, dsp_buf);
3994         memset(dsp_buf, 0, sizeof(dsp_buf));
3995         size += snprintf(dsp_buf, 80,
3996                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3997                  w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
3998                  vop_readl(vop_dev, WIN3_MST0));
3999         strcat(buf, dsp_buf);
4000         memset(dsp_buf, 0, sizeof(dsp_buf));
4001
4002         /*area 1*/
4003         size += snprintf(dsp_buf, 80,
4004                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4005                  w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
4006         strcat(buf, dsp_buf);
4007         memset(dsp_buf, 0, sizeof(dsp_buf));
4008         size += snprintf(dsp_buf, 80,
4009                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4010                  w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
4011                  vop_readl(vop_dev, WIN3_MST1));
4012         strcat(buf, dsp_buf);
4013         memset(dsp_buf, 0, sizeof(dsp_buf));
4014
4015         /*area 2*/
4016         size += snprintf(dsp_buf, 80,
4017                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4018                  w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
4019         strcat(buf, dsp_buf);
4020         memset(dsp_buf, 0, sizeof(dsp_buf));
4021         size += snprintf(dsp_buf, 80,
4022                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4023                  w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
4024                  vop_readl(vop_dev, WIN3_MST2));
4025         strcat(buf, dsp_buf);
4026         memset(dsp_buf, 0, sizeof(dsp_buf));
4027
4028         /*area 3*/
4029         size += snprintf(dsp_buf, 80,
4030                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4031                  w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
4032         strcat(buf, dsp_buf);
4033         memset(dsp_buf, 0, sizeof(dsp_buf));
4034         size += snprintf(dsp_buf, 80,
4035                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4036                  w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
4037                  vop_readl(vop_dev, WIN3_MST3));
4038         strcat(buf, dsp_buf);
4039         memset(dsp_buf, 0, sizeof(dsp_buf));
4040
4041         return size;
4042 }
4043
4044 static int vop_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, bool set)
4045 {
4046         struct vop_device *vop_dev =
4047             container_of(dev_drv, struct vop_device, driver);
4048         struct rk_screen *screen = dev_drv->cur_screen;
4049         u64 ft = 0;
4050         u32 dotclk;
4051         int ret;
4052         u32 pixclock;
4053         u32 x_total, y_total;
4054
4055         if (set) {
4056                 if (fps == 0) {
4057                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
4058                         return 0;
4059                 }
4060                 ft = div_u64(1000000000000llu, fps);
4061                 x_total =
4062                     screen->mode.upper_margin + screen->mode.lower_margin +
4063                     screen->mode.yres + screen->mode.vsync_len;
4064                 y_total =
4065                     screen->mode.left_margin + screen->mode.right_margin +
4066                     screen->mode.xres + screen->mode.hsync_len;
4067                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
4068                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
4069                 ret = clk_set_rate(vop_dev->dclk, dotclk);
4070         }
4071
4072         pixclock = div_u64(1000000000000llu, clk_get_rate(vop_dev->dclk));
4073         vop_dev->pixclock = pixclock;
4074         dev_drv->pixclock = vop_dev->pixclock;
4075         fps = rk_fb_calc_fps(screen, pixclock);
4076         screen->ft = 1000 / fps;        /*one frame time in ms */
4077
4078         if (set)
4079                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
4080                          clk_get_rate(vop_dev->dclk), fps);
4081
4082         return fps;
4083 }
4084
4085 static int vop_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
4086 {
4087         mutex_lock(&dev_drv->fb_win_id_mutex);
4088         if (order == FB_DEFAULT_ORDER)
4089                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
4090         dev_drv->fb4_win_id = order / 10000;
4091         dev_drv->fb3_win_id = (order / 1000) % 10;
4092         dev_drv->fb2_win_id = (order / 100) % 10;
4093         dev_drv->fb1_win_id = (order / 10) % 10;
4094         dev_drv->fb0_win_id = order % 10;
4095         mutex_unlock(&dev_drv->fb_win_id_mutex);
4096
4097         return 0;
4098 }
4099
4100 static int vop_get_win_id(struct rk_lcdc_driver *dev_drv, const char *id)
4101 {
4102         int win_id = 0;
4103
4104         mutex_lock(&dev_drv->fb_win_id_mutex);
4105         if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
4106                 win_id = dev_drv->fb0_win_id;
4107         else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
4108                 win_id = dev_drv->fb1_win_id;
4109         else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
4110                 win_id = dev_drv->fb2_win_id;
4111         else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
4112                 win_id = dev_drv->fb3_win_id;
4113         else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
4114                 win_id = dev_drv->fb4_win_id;
4115         mutex_unlock(&dev_drv->fb_win_id_mutex);
4116
4117         return win_id;
4118 }
4119
4120 static int vop_config_done(struct rk_lcdc_driver *dev_drv)
4121 {
4122         struct vop_device *vop_dev =
4123             container_of(dev_drv, struct vop_device, driver);
4124         int i, fbdc_en = 0;
4125         u64 val;
4126         struct rk_lcdc_win *win = NULL;
4127
4128         spin_lock(&vop_dev->reg_lock);
4129         vop_post_cfg(dev_drv);
4130         vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(vop_dev->standby));
4131         for (i = 0; i < dev_drv->lcdc_win_num; i++) {
4132                 win = dev_drv->win[i];
4133                 vop_alpha_cfg(dev_drv, i);
4134                 fbdc_en |= win->area[0].fbdc_en;
4135                 vop_dev->atv_layer_cnt &= ~(1 << win->id);
4136                 vop_dev->atv_layer_cnt |= (win->state << win->id);
4137                 if ((win->state == 0) && (win->last_state == 1)) {
4138                         switch (win->id) {
4139                         case 0:
4140                                 val = V_WIN0_EN(0);
4141                                 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
4142                                 break;
4143                         case 1:
4144                                 val = V_WIN1_EN(0);
4145                                 vop_msk_reg(vop_dev, WIN1_CTRL0, val);
4146                                 break;
4147                         case 2:
4148                                 val = V_WIN2_EN(0) | V_WIN2_MST0_EN(0) |
4149                                     V_WIN2_MST1_EN(0) |
4150                                     V_WIN2_MST2_EN(0) | V_WIN2_MST3_EN(0);
4151                                 vop_msk_reg(vop_dev, WIN2_CTRL0, val);
4152                                 break;
4153                         case 3:
4154                                 val = V_WIN3_EN(0) | V_WIN3_MST0_EN(0) |
4155                                     V_WIN3_MST1_EN(0) |
4156                                     V_WIN3_MST2_EN(0) | V_WIN3_MST3_EN(0);
4157                                 vop_msk_reg(vop_dev, WIN3_CTRL0, val);
4158                                 break;
4159                         case 4:
4160                                 val = V_HWC_EN(0);
4161                                 vop_msk_reg(vop_dev, HWC_CTRL0, val);
4162                                 break;
4163                         default:
4164                                 break;
4165                         }
4166                 }
4167                 win->last_state = win->state;
4168         }
4169         if (VOP_CHIP(vop_dev) == VOP_RK3399) {
4170                 val = V_VOP_FBDC_EN(fbdc_en);
4171                 vop_msk_reg(vop_dev, AFBCD0_CTRL, val);
4172         }
4173         vop_cfg_done(vop_dev);
4174         spin_unlock(&vop_dev->reg_lock);
4175         return 0;
4176 }
4177
4178 static int vop_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
4179 {
4180         struct vop_device *vop_dev =
4181             container_of(dev_drv, struct vop_device, driver);
4182         spin_lock(&vop_dev->reg_lock);
4183         vop_msk_reg(vop_dev, SYS_CTRL, V_DIRECT_PATH_EN(open));
4184         vop_cfg_done(vop_dev);
4185         spin_unlock(&vop_dev->reg_lock);
4186         return 0;
4187 }
4188
4189 static int vop_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
4190 {
4191         struct vop_device *vop_dev = container_of(dev_drv,
4192                                                     struct vop_device, driver);
4193         spin_lock(&vop_dev->reg_lock);
4194         vop_msk_reg(vop_dev, SYS_CTRL, V_DIRECT_PATH_LAYER_SEL(win_id));
4195         vop_cfg_done(vop_dev);
4196         spin_unlock(&vop_dev->reg_lock);
4197         return 0;
4198 }
4199
4200 static int vop_dpi_status(struct rk_lcdc_driver *dev_drv)
4201 {
4202         struct vop_device *vop_dev =
4203             container_of(dev_drv, struct vop_device, driver);
4204         int ovl;
4205
4206         spin_lock(&vop_dev->reg_lock);
4207         ovl = vop_read_bit(vop_dev, SYS_CTRL, V_DIRECT_PATH_EN(0));
4208         spin_unlock(&vop_dev->reg_lock);
4209         return ovl;
4210 }
4211
4212 static int vop_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv, int enable)
4213 {
4214         struct vop_device *vop_dev =
4215                         container_of(dev_drv, struct vop_device, driver);
4216         if (enable)
4217                 enable_irq(vop_dev->irq);
4218         else
4219                 disable_irq_nosync(vop_dev->irq);
4220         return 0;
4221 }
4222
4223 int vop_poll_vblank(struct rk_lcdc_driver *dev_drv)
4224 {
4225         struct vop_device *vop_dev =
4226             container_of(dev_drv, struct vop_device, driver);
4227         u32 int_reg;
4228         int ret;
4229
4230         if (vop_dev->clk_on && (!dev_drv->suspend_flag)) {
4231                 int_reg = vop_readl(vop_dev, INTR_STATUS0);
4232                 if (int_reg & INTR_LINE_FLAG0) {
4233                         vop_dev->driver.frame_time.last_framedone_t =
4234                             vop_dev->driver.frame_time.framedone_t;
4235                         vop_dev->driver.frame_time.framedone_t = cpu_clock(0);
4236                         vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_LINE_FLAG0,
4237                                         INTR_LINE_FLAG0);
4238                         ret = RK_LF_STATUS_FC;
4239                 } else {
4240                         ret = RK_LF_STATUS_FR;
4241                 }
4242         } else {
4243                 ret = RK_LF_STATUS_NC;
4244         }
4245
4246         return ret;
4247 }
4248
4249 static int vop_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
4250                             unsigned int dsp_addr[][4])
4251 {
4252         struct vop_device *vop_dev =
4253             container_of(dev_drv, struct vop_device, driver);
4254         spin_lock(&vop_dev->reg_lock);
4255         if (vop_dev->clk_on) {
4256                 dsp_addr[0][0] = vop_readl(vop_dev, WIN0_YRGB_MST);
4257                 dsp_addr[1][0] = vop_readl(vop_dev, WIN1_YRGB_MST);
4258                 dsp_addr[2][0] = vop_readl(vop_dev, WIN2_MST0);
4259                 dsp_addr[2][1] = vop_readl(vop_dev, WIN2_MST1);
4260                 dsp_addr[2][2] = vop_readl(vop_dev, WIN2_MST2);
4261                 dsp_addr[2][3] = vop_readl(vop_dev, WIN2_MST3);
4262                 dsp_addr[3][0] = vop_readl(vop_dev, WIN3_MST0);
4263                 dsp_addr[3][1] = vop_readl(vop_dev, WIN3_MST1);
4264                 dsp_addr[3][2] = vop_readl(vop_dev, WIN3_MST2);
4265                 dsp_addr[3][3] = vop_readl(vop_dev, WIN3_MST3);
4266                 dsp_addr[4][0] = vop_readl(vop_dev, HWC_MST);
4267         }
4268         spin_unlock(&vop_dev->reg_lock);
4269         return 0;
4270 }
4271
4272
4273 int vop_update_pwm(int bl_pwm_period, int bl_pwm_duty)
4274 {
4275         /*
4276          * TODO:
4277          * pwm_period_hpr = bl_pwm_period;
4278          * pwm_duty_lpr = bl_pwm_duty;
4279          * pr_info("bl_pwm_period_hpr = 0x%x, bl_pwm_duty_lpr = 0x%x\n",
4280          * bl_pwm_period, bl_pwm_duty);
4281          */
4282
4283         return 0;
4284 }
4285
4286 /*
4287  *  a:[-30~0]:
4288  *    sin_hue = sin(a)*256 +0x100;
4289  *    cos_hue = cos(a)*256;
4290  *  a:[0~30]
4291  *    sin_hue = sin(a)*256;
4292  *    cos_hue = cos(a)*256;
4293  */
4294 static int vop_get_bcsh_hue(struct rk_lcdc_driver *dev_drv, bcsh_hue_mode mode)
4295 {
4296         struct vop_device *vop_dev =
4297             container_of(dev_drv, struct vop_device, driver);
4298         u32 val = 0;
4299
4300         spin_lock(&vop_dev->reg_lock);
4301         if (vop_dev->clk_on) {
4302                 val = vop_readl(vop_dev, BCSH_H);
4303                 switch (mode) {
4304                 case H_SIN:
4305                         val &= MASK(SIN_HUE);
4306                         break;
4307                 case H_COS:
4308                         val &= MASK(COS_HUE);
4309                         val >>= 16;
4310                         break;
4311                 default:
4312                         break;
4313                 }
4314         }
4315         spin_unlock(&vop_dev->reg_lock);
4316
4317         return val;
4318 }
4319
4320 static int vop_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode,
4321                             int calc, int up, int down, int global)
4322 {
4323         struct vop_device *vop_dev =
4324                         container_of(dev_drv, struct vop_device, driver);
4325         struct rk_screen *screen = dev_drv->cur_screen;
4326         u32 total_pixel, calc_pixel, stage_up, stage_down;
4327         u32 pixel_num, global_dn;
4328
4329         if (!vop_dev->cabc_lut_addr_base) {
4330                 pr_err("vop chip[%d] not supoort cabc\n", VOP_CHIP(vop_dev));
4331                 return 0;
4332         }
4333
4334         if (!screen->cabc_lut) {
4335                 pr_err("screen cabc lut not config, so not open cabc\n");
4336                 return 0;
4337         }
4338
4339         dev_drv->cabc_mode = mode;
4340         if (!dev_drv->cabc_mode) {
4341                 spin_lock(&vop_dev->reg_lock);
4342                 if (vop_dev->clk_on) {
4343                         vop_msk_reg(vop_dev, CABC_CTRL0,
4344                                     V_CABC_EN(0) | V_CABC_HANDLE_EN(0));
4345                         vop_cfg_done(vop_dev);
4346                 }
4347                 pr_info("mode = 0, close cabc\n");
4348                 spin_unlock(&vop_dev->reg_lock);
4349                 return 0;
4350         }
4351
4352         total_pixel = screen->mode.xres * screen->mode.yres;
4353         pixel_num = 1000 - calc;
4354         calc_pixel = (total_pixel * pixel_num) / 1000;
4355         stage_up = up;
4356         stage_down = down;
4357         global_dn = global;
4358         pr_info("enable cabc:mode=%d, calc=%d, up=%d, down=%d, global=%d\n",
4359                 mode, calc, stage_up, stage_down, global_dn);
4360
4361         spin_lock(&vop_dev->reg_lock);
4362         if (vop_dev->clk_on) {
4363                 u64 val = 0;
4364
4365                 val = V_CABC_EN(1) | V_CABC_HANDLE_EN(1) |
4366                         V_PWM_CONFIG_MODE(STAGE_BY_STAGE) |
4367                         V_CABC_CALC_PIXEL_NUM(calc_pixel);
4368                 vop_msk_reg(vop_dev, CABC_CTRL0, val);
4369
4370                 val = V_CABC_LUT_EN(1) | V_CABC_TOTAL_NUM(total_pixel);
4371                 vop_msk_reg(vop_dev, CABC_CTRL1, val);
4372
4373                 val = V_CABC_STAGE_DOWN(stage_down) |
4374                         V_CABC_STAGE_UP(stage_up) |
4375                         V_CABC_STAGE_UP_MODE(0) | V_MAX_SCALE_CFG_VALUE(1) |
4376                         V_MAX_SCALE_CFG_ENABLE(0);
4377                 vop_msk_reg(vop_dev, CABC_CTRL2, val);
4378
4379                 val = V_CABC_GLOBAL_DN(global_dn) |
4380                         V_CABC_GLOBAL_DN_LIMIT_EN(1);
4381                 vop_msk_reg(vop_dev, CABC_CTRL3, val);
4382                 vop_cfg_done(vop_dev);
4383         }
4384         spin_unlock(&vop_dev->reg_lock);
4385
4386         return 0;
4387 }
4388
4389 static int vop_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
4390                             int sin_hue, int cos_hue)
4391 {
4392         struct vop_device *vop_dev =
4393             container_of(dev_drv, struct vop_device, driver);
4394         u64 val;
4395
4396         spin_lock(&vop_dev->reg_lock);
4397         if (vop_dev->clk_on) {
4398                 val = V_SIN_HUE(sin_hue) | V_COS_HUE(cos_hue);
4399                 vop_msk_reg(vop_dev, BCSH_H, val);
4400                 vop_cfg_done(vop_dev);
4401         }
4402         spin_unlock(&vop_dev->reg_lock);
4403
4404         return 0;
4405 }
4406
4407 static int vop_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4408                             bcsh_bcs_mode mode, int value)
4409 {
4410         struct vop_device *vop_dev =
4411             container_of(dev_drv, struct vop_device, driver);
4412         u64 val = 0;
4413
4414         spin_lock(&vop_dev->reg_lock);
4415         if (vop_dev->clk_on) {
4416                 switch (mode) {
4417                 case BRIGHTNESS:
4418                         /*from 0 to 255,typical is 128 */
4419                         if (value < 0x80)
4420                                 value += 0x80;
4421                         else if (value >= 0x80)
4422                                 value = value - 0x80;
4423                         val = V_BRIGHTNESS(value);
4424                         break;
4425                 case CONTRAST:
4426                         /*from 0 to 510,typical is 256 */
4427                         val = V_CONTRAST(value);
4428                         break;
4429                 case SAT_CON:
4430                         /*from 0 to 1015,typical is 256 */
4431                         val = V_SAT_CON(value);
4432                         break;
4433                 default:
4434                         break;
4435                 }
4436                 vop_msk_reg(vop_dev, BCSH_BCS, val);
4437                 vop_cfg_done(vop_dev);
4438         }
4439         spin_unlock(&vop_dev->reg_lock);
4440
4441         return val;
4442 }
4443
4444 static int vop_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv, bcsh_bcs_mode mode)
4445 {
4446         struct vop_device *vop_dev =
4447             container_of(dev_drv, struct vop_device, driver);
4448         u64 val = 0;
4449
4450         spin_lock(&vop_dev->reg_lock);
4451         if (vop_dev->clk_on) {
4452                 val = vop_readl(vop_dev, BCSH_BCS);
4453                 switch (mode) {
4454                 case BRIGHTNESS:
4455                         val &= MASK(BRIGHTNESS);
4456                         if (val > 0x80)
4457                                 val -= 0x80;
4458                         else
4459                                 val += 0x80;
4460                         break;
4461                 case CONTRAST:
4462                         val &= MASK(CONTRAST);
4463                         val >>= 8;
4464                         break;
4465                 case SAT_CON:
4466                         val &= MASK(SAT_CON);
4467                         val >>= 20;
4468                         break;
4469                 default:
4470                         break;
4471                 }
4472         }
4473         spin_unlock(&vop_dev->reg_lock);
4474         return val;
4475 }
4476
4477 static int vop_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
4478 {
4479         struct vop_device *vop_dev =
4480             container_of(dev_drv, struct vop_device, driver);
4481
4482         spin_lock(&vop_dev->reg_lock);
4483         if (vop_dev->clk_on) {
4484                 if (open) {
4485                         vop_writel(vop_dev, BCSH_COLOR_BAR, 0x1);
4486                         vop_writel(vop_dev, BCSH_BCS, 0xd0010000);
4487                         vop_writel(vop_dev, BCSH_H, 0x01000000);
4488                         dev_drv->bcsh.enable = 1;
4489                 } else {
4490                         vop_msk_reg(vop_dev, BCSH_COLOR_BAR, V_BCSH_EN(0));
4491                         dev_drv->bcsh.enable = 0;
4492                 }
4493                 vop_bcsh_path_sel(dev_drv);
4494                 vop_cfg_done(vop_dev);
4495         }
4496         spin_unlock(&vop_dev->reg_lock);
4497
4498         return 0;
4499 }
4500
4501 static int vop_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4502 {
4503         if (!enable || !dev_drv->bcsh.enable) {
4504                 vop_open_bcsh(dev_drv, false);
4505                 return 0;
4506         }
4507
4508         if (dev_drv->bcsh.brightness <= 255 ||
4509             dev_drv->bcsh.contrast <= 510 ||
4510             dev_drv->bcsh.sat_con <= 1015 ||
4511             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4512                 vop_open_bcsh(dev_drv, true);
4513                 if (dev_drv->bcsh.brightness <= 255)
4514                         vop_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4515                                          dev_drv->bcsh.brightness);
4516                 if (dev_drv->bcsh.contrast <= 510)
4517                         vop_set_bcsh_bcs(dev_drv, CONTRAST,
4518                                          dev_drv->bcsh.contrast);
4519                 if (dev_drv->bcsh.sat_con <= 1015)
4520                         vop_set_bcsh_bcs(dev_drv, SAT_CON,
4521                                          dev_drv->bcsh.sat_con);
4522                 if (dev_drv->bcsh.sin_hue <= 511 &&
4523                     dev_drv->bcsh.cos_hue <= 511)
4524                         vop_set_bcsh_hue(dev_drv, dev_drv->bcsh.sin_hue,
4525                                          dev_drv->bcsh.cos_hue);
4526         }
4527
4528         return 0;
4529 }
4530
4531 static int __maybe_unused
4532 vop_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4533 {
4534         struct vop_device *vop_dev =
4535             container_of(dev_drv, struct vop_device, driver);
4536
4537         if (enable) {
4538                 spin_lock(&vop_dev->reg_lock);
4539                 if (likely(vop_dev->clk_on)) {
4540                         vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLACK_EN(1));
4541                         vop_cfg_done(vop_dev);
4542                 }
4543                 spin_unlock(&vop_dev->reg_lock);
4544         } else {
4545                 spin_lock(&vop_dev->reg_lock);
4546                 if (likely(vop_dev->clk_on)) {
4547                         vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLACK_EN(0));
4548
4549                         vop_cfg_done(vop_dev);
4550                 }
4551                 spin_unlock(&vop_dev->reg_lock);
4552         }
4553
4554         return 0;
4555 }
4556
4557 static int vop_backlight_close(struct rk_lcdc_driver *dev_drv, int enable)
4558 {
4559         struct vop_device *vop_dev =
4560             container_of(dev_drv, struct vop_device, driver);
4561
4562         if (unlikely(!vop_dev->clk_on)) {
4563                 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
4564                 return 0;
4565         }
4566         vop_get_backlight_device(dev_drv);
4567
4568         if (enable) {
4569                 /* close the backlight */
4570                 if (vop_dev->backlight) {
4571                         vop_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4572                         backlight_update_status(vop_dev->backlight);
4573                 }
4574                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4575                         dev_drv->trsm_ops->disable();
4576         } else {
4577                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4578                         dev_drv->trsm_ops->enable();
4579                 msleep(100);
4580                 /* open the backlight */
4581                 if (vop_dev->backlight) {
4582                         vop_dev->backlight->props.power = FB_BLANK_UNBLANK;
4583                         backlight_update_status(vop_dev->backlight);
4584                 }
4585         }
4586
4587         return 0;
4588 }
4589
4590 static int vop_set_overscan(struct rk_lcdc_driver *dev_drv,
4591                             struct overscan *overscan)
4592 {
4593         struct vop_device *vop_dev =
4594             container_of(dev_drv, struct vop_device, driver);
4595
4596         if (unlikely(!vop_dev->clk_on)) {
4597                 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
4598                 return 0;
4599         }
4600         /*vop_post_cfg(dev_drv);*/
4601
4602         return 0;
4603 }
4604
4605 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4606         .open = vop_open,
4607         .win_direct_en = vop_win_direct_en,
4608         .load_screen = vop_load_screen,
4609         .get_dspbuf_info = vop_get_dspbuf_info,
4610         .post_dspbuf = vop_post_dspbuf,
4611         .set_par = vop_set_par,
4612         .pan_display = vop_pan_display,
4613         .set_wb = vop_set_writeback,
4614         .direct_set_addr = vop_direct_set_win_addr,
4615         /*.lcdc_reg_update = vop_reg_update,*/
4616         .blank = vop_blank,
4617         .ioctl = vop_ioctl,
4618         .suspend = vop_early_suspend,
4619         .resume = vop_early_resume,
4620         .get_win_state = vop_get_win_state,
4621         .area_support_num = vop_get_area_num,
4622         .ovl_mgr = vop_ovl_mgr,
4623         .get_disp_info = vop_get_disp_info,
4624         .fps_mgr = vop_fps_mgr,
4625         .fb_get_win_id = vop_get_win_id,
4626         .fb_win_remap = vop_fb_win_remap,
4627         .poll_vblank = vop_poll_vblank,
4628         .dpi_open = vop_dpi_open,
4629         .dpi_win_sel = vop_dpi_win_sel,
4630         .dpi_status = vop_dpi_status,
4631         .get_dsp_addr = vop_get_dsp_addr,
4632         .set_dsp_lut = vop_set_lut,
4633         .set_cabc_lut = vop_set_cabc,
4634         .set_dsp_cabc = vop_set_dsp_cabc,
4635         .set_dsp_bcsh_hue = vop_set_bcsh_hue,
4636         .set_dsp_bcsh_bcs = vop_set_bcsh_bcs,
4637         .get_dsp_bcsh_hue = vop_get_bcsh_hue,
4638         .get_dsp_bcsh_bcs = vop_get_bcsh_bcs,
4639         .open_bcsh = vop_open_bcsh,
4640         .dump_reg = vop_reg_dump,
4641         .cfg_done = vop_config_done,
4642         .set_irq_to_cpu = vop_set_irq_to_cpu,
4643         /*.dsp_black = vop_dsp_black,*/
4644         .backlight_close = vop_backlight_close,
4645         .mmu_en    = vop_mmu_en,
4646         .set_overscan   = vop_set_overscan,
4647 };
4648
4649 static irqreturn_t vop_isr(int irq, void *dev_id)
4650 {
4651         struct vop_device *vop_dev = (struct vop_device *)dev_id;
4652         ktime_t timestamp = ktime_get();
4653         u32 intr_status;
4654         unsigned long flags;
4655
4656         spin_lock_irqsave(&vop_dev->irq_lock, flags);
4657
4658         intr_status = vop_readl(vop_dev, INTR_STATUS0);
4659         vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, intr_status);
4660
4661         spin_unlock_irqrestore(&vop_dev->irq_lock, flags);
4662         /* This is expected for vop iommu irqs, since the irq is shared */
4663         if (!intr_status)
4664                 return IRQ_NONE;
4665
4666         if (intr_status & INTR_FS) {
4667                 timestamp = ktime_get();
4668                 if (vop_dev->driver.wb_data.state) {
4669                         u32 wb_status;
4670
4671                         spin_lock_irqsave(&vop_dev->irq_lock, flags);
4672                         wb_status = vop_read_bit(vop_dev, WB_CTRL0, V_WB_EN(0));
4673
4674                         if (wb_status)
4675                                 vop_clr_bit(vop_dev, WB_CTRL0, V_WB_EN(0));
4676
4677                         vop_cfg_done(vop_dev);
4678                         vop_dev->driver.wb_data.state = 0;
4679                         spin_unlock_irqrestore(&vop_dev->irq_lock, flags);
4680                 }
4681                 vop_dev->driver.vsync_info.timestamp = timestamp;
4682                 wake_up_interruptible_all(&vop_dev->driver.vsync_info.wait);
4683                 intr_status &= ~INTR_FS;
4684         }
4685
4686         if (intr_status & INTR_LINE_FLAG0)
4687                 intr_status &= ~INTR_LINE_FLAG0;
4688
4689         if (intr_status & INTR_LINE_FLAG1)
4690                 intr_status &= ~INTR_LINE_FLAG1;
4691
4692         if (intr_status & INTR_FS_NEW)
4693                 intr_status &= ~INTR_FS_NEW;
4694
4695         if (intr_status & INTR_BUS_ERROR) {
4696                 intr_status &= ~INTR_BUS_ERROR;
4697                 dev_warn_ratelimited(vop_dev->dev, "bus error!");
4698         }
4699
4700         if (intr_status & INTR_WIN0_EMPTY) {
4701                 intr_status &= ~INTR_WIN0_EMPTY;
4702                 dev_warn_ratelimited(vop_dev->dev, "intr win0 empty!");
4703         }
4704
4705         if (intr_status & INTR_WIN1_EMPTY) {
4706                 intr_status &= ~INTR_WIN1_EMPTY;
4707                 dev_warn_ratelimited(vop_dev->dev, "intr win1 empty!");
4708         }
4709
4710         if (intr_status & INTR_HWC_EMPTY) {
4711                 intr_status &= ~INTR_HWC_EMPTY;
4712                 dev_warn_ratelimited(vop_dev->dev, "intr hwc empty!");
4713         }
4714
4715         if (intr_status & INTR_POST_BUF_EMPTY) {
4716                 intr_status &= ~INTR_POST_BUF_EMPTY;
4717                 dev_warn_ratelimited(vop_dev->dev, "intr post buf empty!");
4718         }
4719
4720         if (intr_status)
4721                 dev_err(vop_dev->dev, "Unknown VOP IRQs: %#02x\n", intr_status);
4722
4723         return IRQ_HANDLED;
4724 }
4725
4726 #if defined(CONFIG_PM)
4727 static int vop_suspend(struct platform_device *pdev, pm_message_t state)
4728 {
4729         return 0;
4730 }
4731
4732 static int vop_resume(struct platform_device *pdev)
4733 {
4734         return 0;
4735 }
4736 #else
4737 #define vop_suspend NULL
4738 #define vop_resume  NULL
4739 #endif
4740
4741 static int vop_parse_dt(struct vop_device *vop_dev)
4742 {
4743         struct device_node *np = vop_dev->dev->of_node;
4744         struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
4745         int val;
4746
4747         if (of_property_read_u32(np, "rockchip,prop", &val))
4748                 vop_dev->prop = PRMRY;  /*default set it as primary */
4749         else
4750                 vop_dev->prop = val;
4751
4752         if (of_property_read_u32(np, "rockchip,mirror", &val))
4753                 dev_drv->rotate_mode = NO_MIRROR;
4754         else
4755                 dev_drv->rotate_mode = val;
4756
4757         if (of_property_read_u32(np, "rockchip,pwr18", &val))
4758                 /*default set it as 3.xv power supply */
4759                 vop_dev->pwr18 = false;
4760         else
4761                 vop_dev->pwr18 = (val ? true : false);
4762
4763         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4764                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4765         else
4766                 dev_drv->fb_win_map = val;
4767
4768         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4769                 dev_drv->bcsh.enable = false;
4770         else
4771                 dev_drv->bcsh.enable = (val ? true : false);
4772
4773         if (of_property_read_u32(np, "rockchip,brightness", &val))
4774                 dev_drv->bcsh.brightness = 0xffff;
4775         else
4776                 dev_drv->bcsh.brightness = val;
4777
4778         if (of_property_read_u32(np, "rockchip,contrast", &val))
4779                 dev_drv->bcsh.contrast = 0xffff;
4780         else
4781                 dev_drv->bcsh.contrast = val;
4782
4783         if (of_property_read_u32(np, "rockchip,sat-con", &val))
4784                 dev_drv->bcsh.sat_con = 0xffff;
4785         else
4786                 dev_drv->bcsh.sat_con = val;
4787
4788         if (of_property_read_u32(np, "rockchip,hue", &val)) {
4789                 dev_drv->bcsh.sin_hue = 0xffff;
4790                 dev_drv->bcsh.cos_hue = 0xffff;
4791         } else {
4792                 dev_drv->bcsh.sin_hue = val & 0xff;
4793                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4794         }
4795
4796         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4797                 dev_drv->iommu_enabled = 0;
4798         else
4799                 dev_drv->iommu_enabled = val;
4800         return 0;
4801 }
4802
4803 static int vop_probe(struct platform_device *pdev)
4804 {
4805         struct vop_device *vop_dev = NULL;
4806         struct rk_lcdc_driver *dev_drv;
4807         const struct of_device_id *of_id;
4808         struct device *dev = &pdev->dev;
4809         struct resource *res;
4810         struct device_node *np = pdev->dev.of_node;
4811         int prop;
4812         int ret = 0;
4813
4814         /* if the primary lcdc has not registered ,the extend
4815          * lcdc register later
4816          */
4817         of_property_read_u32(np, "rockchip,prop", &prop);
4818         if (prop == EXTEND) {
4819                 if (!is_prmry_rk_lcdc_registered())
4820                         return -EPROBE_DEFER;
4821         }
4822         vop_dev = devm_kzalloc(dev, sizeof(struct vop_device), GFP_KERNEL);
4823         if (!vop_dev)
4824                 return -ENOMEM;
4825         of_id = of_match_device(vop_dt_ids, dev);
4826         vop_dev->data = of_id->data;
4827         if (VOP_CHIP(vop_dev) != VOP_RK322X && VOP_CHIP(vop_dev) != VOP_RK3399)
4828                 return -ENODEV;
4829         platform_set_drvdata(pdev, vop_dev);
4830         vop_dev->dev = dev;
4831         vop_parse_dt(vop_dev);
4832 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
4833         /* enable power domain */
4834         pm_runtime_enable(dev);
4835 #endif
4836         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4837         vop_dev->reg_phy_base = res->start;
4838         vop_dev->len = resource_size(res);
4839         vop_dev->regs = devm_ioremap(&pdev->dev, res->start,
4840                                      resource_size(res));
4841         if (IS_ERR(vop_dev->regs))
4842                 return PTR_ERR(vop_dev->regs);
4843
4844         dev_info(dev, "vop_dev->regs=0x%lx\n", (long)vop_dev->regs);
4845
4846         vop_dev->regsbak = devm_kzalloc(dev, vop_dev->len, GFP_KERNEL);
4847         if (IS_ERR(vop_dev->regsbak))
4848                 return PTR_ERR(vop_dev->regsbak);
4849         if (VOP_CHIP(vop_dev) == VOP_RK3399) {
4850                 vop_dev->dsp_lut_addr_base = vop_dev->regs + GAMMA_LUT_ADDR;
4851                 vop_dev->cabc_lut_addr_base = vop_dev->regs +
4852                                                 CABC_GAMMA_LUT_ADDR;
4853         }
4854         vop_dev->grf_base =
4855                 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
4856         if (IS_ERR(vop_dev->grf_base)) {
4857                 dev_err(&pdev->dev, "can't find lcdc grf property\n");
4858                 vop_dev->grf_base = NULL;
4859         }
4860
4861         vop_dev->id = vop_get_id(vop_dev, vop_dev->reg_phy_base);
4862         dev_set_name(vop_dev->dev, "vop%d", vop_dev->id);
4863         dev_drv = &vop_dev->driver;
4864         dev_drv->dev = dev;
4865         dev_drv->prop = prop;
4866         dev_drv->id = vop_dev->id;
4867         dev_drv->ops = &lcdc_drv_ops;
4868         dev_drv->lcdc_win_num = vop_dev->data->n_wins;
4869         dev_drv->reserved_fb = 0;
4870         spin_lock_init(&vop_dev->reg_lock);
4871         spin_lock_init(&vop_dev->irq_lock);
4872         vop_dev->irq = platform_get_irq(pdev, 0);
4873         if (vop_dev->irq < 0) {
4874                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4875                         vop_dev->id);
4876                 return -ENXIO;
4877         }
4878
4879         ret = devm_request_irq(dev, vop_dev->irq, vop_isr,
4880                                IRQF_SHARED, dev_name(dev), vop_dev);
4881         if (ret) {
4882                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4883                         vop_dev->irq, ret);
4884                 return ret;
4885         }
4886         if (dev_drv->iommu_enabled) {
4887                 if (VOP_CHIP(vop_dev) == VOP_RK322X) {
4888                         strcpy(dev_drv->mmu_dts_name,
4889                                VOP_IOMMU_COMPATIBLE_NAME);
4890                 } else {
4891                         if (vop_dev->id == 0)
4892                                 strcpy(dev_drv->mmu_dts_name,
4893                                        VOPB_IOMMU_COMPATIBLE_NAME);
4894                         else
4895                                 strcpy(dev_drv->mmu_dts_name,
4896                                        VOPL_IOMMU_COMPATIBLE_NAME);
4897                 }
4898         }
4899         if (VOP_CHIP(vop_dev) == VOP_RK3399)
4900                 dev_drv->property.feature |= SUPPORT_WRITE_BACK | SUPPORT_AFBDC;
4901         dev_drv->property.feature |= SUPPORT_VOP_IDENTIFY |
4902                                         SUPPORT_YUV420_OUTPUT;
4903         dev_drv->property.max_output_x = 4096;
4904         dev_drv->property.max_output_y = 2160;
4905
4906         if ((VOP_CHIP(vop_dev) == VOP_RK3399) && (vop_dev->id == 1)) {
4907                 vop_dev->data->win[1].property.feature &= ~SUPPORT_HW_EXIST;
4908                 vop_dev->data->win[3].property.feature &= ~SUPPORT_HW_EXIST;
4909         }
4910
4911         ret = rk_fb_register(dev_drv, vop_dev->data->win, vop_dev->id);
4912         if (ret < 0) {
4913                 dev_err(dev, "register fb for lcdc%d failed!\n", vop_dev->id);
4914                 return ret;
4915         }
4916         vop_dev->screen = dev_drv->screen0;
4917         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4918                  vop_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4919
4920         return 0;
4921 }
4922
4923 static int vop_remove(struct platform_device *pdev)
4924 {
4925         return 0;
4926 }
4927
4928 static void vop_shutdown(struct platform_device *pdev)
4929 {
4930         struct vop_device *vop_dev = platform_get_drvdata(pdev);
4931         struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
4932
4933         dev_drv->suspend_flag = 1;
4934         /* ensure suspend_flag take effect on multi process */
4935         smp_wmb();
4936         flush_kthread_worker(&dev_drv->update_regs_worker);
4937         kthread_stop(dev_drv->update_regs_thread);
4938         vop_deint(vop_dev);
4939
4940         vop_clk_disable(vop_dev);
4941 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
4942         pm_runtime_disable(vop_dev->dev);
4943 #endif
4944         rk_disp_pwr_disable(dev_drv);
4945 }
4946
4947 static struct platform_driver vop_driver = {
4948         .probe = vop_probe,
4949         .remove = vop_remove,
4950         .driver = {
4951                    .name = "rk322x-lcdc",
4952                    .owner = THIS_MODULE,
4953                    .of_match_table = of_match_ptr(vop_dt_ids),
4954                    },
4955         .suspend = vop_suspend,
4956         .resume = vop_resume,
4957         .shutdown = vop_shutdown,
4958 };
4959
4960 static int __init vop_module_init(void)
4961 {
4962         return platform_driver_register(&vop_driver);
4963 }
4964
4965 static void __exit vop_module_exit(void)
4966 {
4967         platform_driver_unregister(&vop_driver);
4968 }
4969
4970 fs_initcall(vop_module_init);
4971 module_exit(vop_module_exit);