2 * drivers/video/rockchip/lcdc/rk322x_lcdc.c
4 * Copyright (C) 2015 ROCKCHIP, Inc.
5 * Author: Mark Yao <mark.yao@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/string.h>
22 #include <linux/slab.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/of_device.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <linux/rockchip-iovmm.h>
31 #include <asm/div64.h>
32 #include <linux/uaccess.h>
33 #include <linux/rockchip/iomap.h>
34 #include <linux/rockchip/grf.h>
35 #include <linux/rockchip/common.h>
36 #include <dt-bindings/clock/rk_system_status.h>
38 #include "rk322x_lcdc.h"
40 /*#define CONFIG_RK_FPGA 1*/
41 #define VOP_CHIP(dev) (dev->data->chip_type)
43 static int dbg_thresd;
44 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
46 #define DBG(level, x...) do { \
47 if (unlikely(dbg_thresd >= level)) \
51 static struct rk_lcdc_win rk322x_vop_win[] = {
52 { .name = "win0", .id = VOP_WIN0},
53 { .name = "win1", .id = VOP_WIN1},
54 { .name = "hwc", .id = VOP_HWC}
57 static struct rk_lcdc_win rk3399_vop_win[] = {
58 { .name = "win0", .id = VOP_WIN0},
59 { .name = "win1", .id = VOP_WIN1},
60 { .name = "win2", .id = VOP_WIN2},
61 { .name = "win3", .id = VOP_WIN3},
62 { .name = "hwc", .id = VOP_HWC}
65 static const struct vop_data rk322x_data = {
66 .chip_type = VOP_RK322X,
67 .win = rk322x_vop_win,
68 .n_wins = ARRAY_SIZE(rk322x_vop_win),
71 static const struct vop_data rk3399_data = {
72 .chip_type = VOP_RK3399,
73 .win = rk3399_vop_win,
74 .n_wins = ARRAY_SIZE(rk3399_vop_win),
77 #if defined(CONFIG_OF)
78 static const struct of_device_id vop_dt_ids[] = {
79 {.compatible = "rockchip,rk322x-lcdc",
80 .data = &rk322x_data, },
81 {.compatible = "rockchip,rk3399-lcdc",
82 .data = &rk3399_data, },
87 static const u32 csc_y2r_bt601_limit[12] = {
88 0x04a8, 0, 0x0662, 0xfffc8654,
89 0x04a8, 0xfe6f, 0xfcbf, 0x00022056,
90 0x04a8, 0x0812, 0, 0xfffbaeac,
93 static const u32 csc_y2r_bt709_full[12] = {
94 0x04a8, 0, 0x072c, 0xfffc219e,
95 0x04a8, 0xff26, 0xfdde, 0x0001357b,
96 0x04a8, 0x0873, 0, 0xfffb7dee,
99 static const u32 csc_y2r_bt601_full[12] = {
100 0x0400, 0, 0x059c, 0xfffd342d,
101 0x0400, 0xfea0, 0xfd25, 0x00021fcc,
102 0x0400, 0x0717, 0, 0xfffc76bc,
105 static const u32 csc_y2r_bt601_limit_10[12] = {
106 0x04a8, 0, 0x0662, 0xfff2134e,
107 0x04a8, 0xfe6f, 0xfcbf, 0x00087b58,
108 0x04a8, 0x0812, 0, 0xffeeb4b0,
111 static const u32 csc_y2r_bt709_full_10[12] = {
112 0x04a8, 0, 0x072c, 0xfff08077,
113 0x04a8, 0xff26, 0xfdde, 0x0004cfed,
114 0x04a8, 0x0873, 0, 0xffedf1b8,
117 static const u32 csc_y2r_bt601_full_10[12] = {
118 0x0400, 0, 0x059c, 0xfff4cab4,
119 0x0400, 0xfea0, 0xfd25, 0x00087932,
120 0x0400, 0x0717, 0, 0xfff1d4f2,
123 static const u32 csc_y2r_bt2020[12] = {
124 0x04a8, 0, 0x06b6, 0xfff16bfc,
125 0x04a8, 0xff40, 0xfd66, 0x58ae9,
126 0x04a8, 0x0890, 0, 0xffedb828,
129 static const u32 csc_r2y_bt601_limit[12] = {
130 0x0107, 0x0204, 0x0064, 0x04200,
131 0xff68, 0xfed6, 0x01c2, 0x20200,
132 0x01c2, 0xfe87, 0xffb7, 0x20200,
135 static const u32 csc_r2y_bt709_full[12] = {
136 0x00bb, 0x0275, 0x003f, 0x04200,
137 0xff99, 0xfea5, 0x01c2, 0x20200,
138 0x01c2, 0xfe68, 0xffd7, 0x20200,
141 static const u32 csc_r2y_bt601_full[12] = {
142 0x0132, 0x0259, 0x0075, 0x200,
143 0xff53, 0xfead, 0x0200, 0x20200,
144 0x0200, 0xfe53, 0xffad, 0x20200,
147 static const u32 csc_r2y_bt601_limit_10[12] = {
148 0x0107, 0x0204, 0x0064, 0x10200,
149 0xff68, 0xfed6, 0x01c2, 0x80200,
150 0x01c2, 0xfe87, 0xffb7, 0x80200,
153 static const u32 csc_r2y_bt709_full_10[12] = {
154 0x00bb, 0x0275, 0x003f, 0x10200,
155 0xff99, 0xfea5, 0x01c2, 0x80200,
156 0x01c2, 0xfe68, 0xffd7, 0x80200,
159 static const u32 csc_r2y_bt601_full_10[12] = {
160 0x0132, 0x0259, 0x0075, 0x200,
161 0xff53, 0xfead, 0x0200, 0x80200,
162 0x0200, 0xfe53, 0xffad, 0x80200,
165 static const u32 csc_r2y_bt2020[12] = {
166 0x00e6, 0x0253, 0x0034, 0x10200,
167 0xff83, 0xfebd, 0x01c1, 0x80200,
168 0x01c1, 0xfe64, 0xffdc, 0x80200,
171 static const u32 csc_r2r_bt2020to709[12] = {
172 0x06a4, 0xfda6, 0xffb5, 0x200,
173 0xff80, 0x0488, 0xfff8, 0x200,
174 0xffed, 0xff99, 0x047a, 0x200,
177 static const u32 csc_r2r_bt709to2020[12] = {
178 0x282, 0x151, 0x02c, 0x200,
179 0x047, 0x3ae, 0x00c, 0x200,
180 0x011, 0x05a, 0x395, 0x200,
183 static int vop_get_id(struct vop_device *vop_dev, u32 phy_base)
185 if (VOP_CHIP(vop_dev) == VOP_RK3399) {
186 if (phy_base == 0xff900000) /* vop big */
188 else if (phy_base == 0xff8f0000) /* vop lit */
197 static void vop_load_csc_table(struct vop_device *vop_dev, u32 offset,
202 csc_val = table[1] << 16 | table[0];
203 vop_writel(vop_dev, offset, csc_val);
204 csc_val = table[4] << 16 | table[2];
205 vop_writel(vop_dev, offset + 4, csc_val);
206 csc_val = table[6] << 16 | table[5];
207 vop_writel(vop_dev, offset + 8, csc_val);
208 csc_val = table[9] << 16 | table[8];
209 vop_writel(vop_dev, offset + 0xc, csc_val);
211 vop_writel(vop_dev, offset + 0x10, csc_val);
213 vop_writel(vop_dev, offset + 0x14, csc_val);
215 vop_writel(vop_dev, offset + 0x18, csc_val);
217 vop_writel(vop_dev, offset + 0x1c, csc_val);
220 #define LOAD_CSC(dev, mode, table, win_id) \
221 vop_load_csc_table(dev, \
222 WIN0_YUV2YUV_##mode + 0x60 * win_id, \
225 static int vop_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
227 static int vop_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
229 struct vop_device *vop_dev =
230 container_of(dev_drv, struct vop_device, driver);
233 if (!vop_dev->dsp_lut_addr_base) {
234 dev_warn(vop_dev->dev, "not support dsp lut config\n");
239 dev_err(vop_dev->dev, "dsp lut table is null\n");
243 spin_lock(&vop_dev->reg_lock);
244 for (i = 0; i < 256; i++) {
249 c = vop_dev->dsp_lut_addr_base + (i << 2);
251 g = (v & 0xff00) << 4;
252 r = (v & 0xff0000) << 6;
254 for (j = 0; j < 4; j++) {
255 writel_relaxed(v, c);
256 v += (1 + (1 << 10) + (1 << 20));
260 vop_msk_reg(vop_dev, DSP_CTRL1, V_DSP_LUT_EN(1));
262 * update_gamma value auto clean to 0 by HW, should not
265 vop_msk_reg_nobak(vop_dev, DSP_CTRL1, V_UPDATE_GAMMA_LUT(1));
267 vop_cfg_done(vop_dev);
268 spin_unlock(&vop_dev->reg_lock);
273 static int vop_set_cabc(struct rk_lcdc_driver *dev_drv, int *cabc_lut)
275 struct vop_device *vop_dev =
276 container_of(dev_drv, struct vop_device, driver);
279 if (!vop_dev->cabc_lut_addr_base) {
280 dev_warn(vop_dev->dev, "not support cabc config\n");
285 dev_err(vop_dev->dev, "cabc lut table is null\n");
288 spin_lock(&vop_dev->reg_lock);
289 vop_msk_reg(vop_dev, CABC_CTRL1, V_CABC_LUT_EN(0));
290 vop_cfg_done(vop_dev);
291 spin_unlock(&vop_dev->reg_lock);
295 spin_lock(&vop_dev->reg_lock);
296 for (i = 0; i < 128; i++) {
301 writel_relaxed(v, vop_dev->cabc_lut_addr_base + i);
303 vop_msk_reg(vop_dev, CABC_CTRL1, V_CABC_LUT_EN(1));
304 spin_unlock(&vop_dev->reg_lock);
309 static int vop_clk_enable(struct vop_device *vop_dev)
311 if (!vop_dev->clk_on) {
312 clk_prepare_enable(vop_dev->hclk);
313 clk_prepare_enable(vop_dev->dclk);
314 clk_prepare_enable(vop_dev->aclk);
315 if (vop_dev->hclk_noc)
316 clk_prepare_enable(vop_dev->hclk_noc);
317 if (vop_dev->aclk_noc)
318 clk_prepare_enable(vop_dev->aclk_noc);
319 spin_lock(&vop_dev->reg_lock);
321 spin_unlock(&vop_dev->reg_lock);
327 static int vop_clk_disable(struct vop_device *vop_dev)
329 if (vop_dev->clk_on) {
330 spin_lock(&vop_dev->reg_lock);
332 spin_unlock(&vop_dev->reg_lock);
334 clk_disable_unprepare(vop_dev->dclk);
335 clk_disable_unprepare(vop_dev->hclk);
336 clk_disable_unprepare(vop_dev->aclk);
337 if (vop_dev->hclk_noc)
338 clk_disable_unprepare(vop_dev->hclk_noc);
339 if (vop_dev->aclk_noc)
340 clk_disable_unprepare(vop_dev->aclk_noc);
346 static int __maybe_unused vop_disable_irq(struct vop_device *vop_dev)
348 if (likely(vop_dev->clk_on)) {
349 spin_lock(&vop_dev->reg_lock);
350 vop_writel(vop_dev, INTR_EN0, 0xffff0000);
351 vop_writel(vop_dev, INTR_EN1, 0xffff0000);
352 vop_writel(vop_dev, INTR_CLEAR0, 0xffffffff);
353 vop_writel(vop_dev, INTR_CLEAR1, 0xffffffff);
354 vop_cfg_done(vop_dev);
355 spin_unlock(&vop_dev->reg_lock);
361 static int vop_reg_dump(struct rk_lcdc_driver *dev_drv)
363 struct vop_device *vop_dev =
364 container_of(dev_drv, struct vop_device, driver);
365 int *cbase = (int *)vop_dev->regs;
366 int *regsbak = (int *)vop_dev->regsbak;
368 char dbg_message[30];
371 pr_info("lcd back up reg:\n");
372 memset(dbg_message, 0, sizeof(dbg_message));
373 memset(buf, 0, sizeof(buf));
374 for (i = 0; i <= (0x200 >> 4); i++) {
375 val = sprintf(dbg_message, "0x%04x: ", i * 16);
376 for (j = 0; j < 4; j++) {
377 val = sprintf(buf, "%08x ", *(regsbak + i * 4 + j));
378 strcat(dbg_message, buf);
380 pr_info("%s\n", dbg_message);
381 memset(dbg_message, 0, sizeof(dbg_message));
382 memset(buf, 0, sizeof(buf));
385 pr_info("lcdc reg:\n");
386 for (i = 0; i <= (0x200 >> 4); i++) {
387 val = sprintf(dbg_message, "0x%04x: ", i * 16);
388 for (j = 0; j < 4; j++) {
389 sprintf(buf, "%08x ",
390 readl_relaxed(cbase + i * 4 + j));
391 strcat(dbg_message, buf);
393 pr_info("%s\n", dbg_message);
394 memset(dbg_message, 0, sizeof(dbg_message));
395 memset(buf, 0, sizeof(buf));
402 static int win##id##_enable(struct vop_device *vop_dev, int en) \
404 spin_lock(&vop_dev->reg_lock); \
405 vop_msk_reg(vop_dev, WIN##id##_CTRL0, V_WIN##id##_EN((u64)en)); \
406 vop_cfg_done(vop_dev); \
407 spin_unlock(&vop_dev->reg_lock); \
416 /*enable/disable win directly*/
417 static int vop_win_direct_en(struct rk_lcdc_driver *drv,
420 struct vop_device *vop_dev =
421 container_of(drv, struct vop_device, driver);
423 win0_enable(vop_dev, en);
424 else if (win_id == 1)
425 win1_enable(vop_dev, en);
426 else if (win_id == 2)
427 win2_enable(vop_dev, en);
428 else if (win_id == 3)
429 win3_enable(vop_dev, en);
431 dev_err(vop_dev->dev, "invalid win number:%d\n", win_id);
435 #define SET_WIN_ADDR(id) \
436 static int set_win##id##_addr(struct vop_device *vop_dev, u32 addr) \
438 spin_lock(&vop_dev->reg_lock); \
439 vop_writel(vop_dev, WIN##id##_YRGB_MST, addr); \
440 vop_msk_reg(vop_dev, WIN##id##_CTRL0, V_WIN##id##_EN(1)); \
441 vop_cfg_done(vop_dev); \
442 spin_unlock(&vop_dev->reg_lock); \
448 int vop_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
449 int win_id, u32 addr)
451 struct vop_device *vop_dev =
452 container_of(dev_drv, struct vop_device, driver);
454 set_win0_addr(vop_dev, addr);
456 set_win1_addr(vop_dev, addr);
461 static void lcdc_read_reg_defalut_cfg(struct vop_device *vop_dev)
465 struct rk_screen *screen = vop_dev->driver.cur_screen;
466 u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
467 u32 V_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
469 struct rk_lcdc_win *win0 = vop_dev->driver.win[0];
471 spin_lock(&vop_dev->reg_lock);
472 for (reg = 0; reg < vop_dev->len; reg += 4) {
473 val = vop_readl_backup(vop_dev, reg);
476 win0->area[0].xact = (val & MASK(WIN0_ACT_WIDTH)) + 1;
478 ((val & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1;
481 win0->area[0].xsize = (val & MASK(WIN0_DSP_WIDTH)) + 1;
482 win0->area[0].ysize =
483 ((val & MASK(WIN0_DSP_HEIGHT)) >> 16) + 1;
486 st_x = val & MASK(WIN0_DSP_XST);
487 st_y = (val & MASK(WIN0_DSP_YST)) >> 16;
488 win0->area[0].xpos = st_x - h_pw_bp;
489 win0->area[0].ypos = st_y - V_pw_bp;
492 win0->state = val & MASK(WIN0_EN);
493 win0->area[0].fmt_cfg =
494 (val & MASK(WIN0_DATA_FMT)) >> 1;
495 win0->fmt_10 = (val & MASK(WIN0_FMT_10)) >> 4;
496 win0->area[0].format = win0->area[0].fmt_cfg;
499 win0->area[0].y_vir_stride =
500 val & MASK(WIN0_VIR_STRIDE);
501 win0->area[0].uv_vir_stride =
502 (val & MASK(WIN0_VIR_STRIDE_UV)) >> 16;
503 if (win0->area[0].format == ARGB888)
504 win0->area[0].xvir = win0->area[0].y_vir_stride;
505 else if (win0->area[0].format == RGB888)
507 win0->area[0].y_vir_stride * 4 / 3;
508 else if (win0->area[0].format == RGB565)
510 2 * win0->area[0].y_vir_stride;
513 4 * win0->area[0].y_vir_stride;
516 win0->area[0].smem_start = val;
519 win0->area[0].cbr_start = val;
525 spin_unlock(&vop_dev->reg_lock);
528 /********do basic init*********/
529 static int vop_pre_init(struct rk_lcdc_driver *dev_drv)
531 struct vop_device *vop_dev =
532 container_of(dev_drv, struct vop_device, driver);
533 if (vop_dev->pre_init)
535 vop_dev->hclk = devm_clk_get(vop_dev->dev, "hclk_lcdc");
536 vop_dev->aclk = devm_clk_get(vop_dev->dev, "aclk_lcdc");
537 vop_dev->dclk = devm_clk_get(vop_dev->dev, "dclk_lcdc");
538 if (IS_ERR(vop_dev->aclk) || IS_ERR(vop_dev->dclk) ||
539 IS_ERR(vop_dev->hclk))
540 dev_err(vop_dev->dev, "failed to get clk source\n");
541 vop_dev->hclk_noc = devm_clk_get(vop_dev->dev, "hclk_vop_noc");
542 if (IS_ERR(vop_dev->hclk_noc)) {
543 vop_dev->hclk_noc = NULL;
544 dev_err(vop_dev->dev, "failed to get clk source\n");
546 vop_dev->aclk_noc = devm_clk_get(vop_dev->dev, "aclk_vop_noc");
547 if (IS_ERR(vop_dev->aclk_noc)) {
548 vop_dev->aclk_noc = NULL;
549 dev_err(vop_dev->dev, "failed to get clk source\n");
551 if (!support_uboot_display())
552 rk_disp_pwr_enable(dev_drv);
553 vop_clk_enable(vop_dev);
555 memcpy(vop_dev->regsbak, vop_dev->regs, vop_dev->len);
556 /*backup reg config at uboot */
557 lcdc_read_reg_defalut_cfg(vop_dev);
558 #ifndef CONFIG_RK_FPGA
562 if (vop_dev->pwr18 == 1) {
564 vop_grf_writel(vop_dev->pmugrf_base,
565 PMUGRF_SOC_CON0_VOP, v);
568 vop_grf_writel(vop_dev->pmugrf_base,
569 PMUGRF_SOC_CON0_VOP, v);
573 vop_writel(vop_dev, FRC_LOWER01_0, 0x12844821);
574 vop_writel(vop_dev, FRC_LOWER01_1, 0x21488412);
575 vop_writel(vop_dev, FRC_LOWER10_0, 0xa55a9696);
576 vop_writel(vop_dev, FRC_LOWER10_1, 0x5aa56969);
577 vop_writel(vop_dev, FRC_LOWER11_0, 0xdeb77deb);
578 vop_writel(vop_dev, FRC_LOWER11_1, 0xed7bb7de);
580 vop_msk_reg(vop_dev, SYS_CTRL, V_AUTO_GATING_EN(0));
581 vop_msk_reg(vop_dev, DSP_CTRL1, V_DITHER_UP_EN(1));
582 vop_cfg_done(vop_dev);
583 vop_dev->pre_init = true;
588 static void vop_deint(struct vop_device *vop_dev)
590 if (vop_dev->clk_on) {
593 vop_disable_irq(vop_dev);
594 spin_lock(&vop_dev->reg_lock);
595 vop_msk_reg(vop_dev, WIN0_CTRL0, V_WIN0_EN(0));
596 vop_msk_reg(vop_dev, WIN1_CTRL0, V_WIN0_EN(0));
598 val = V_WIN2_EN(0) | V_WIN2_MST0_EN(0) | V_WIN2_MST1_EN(0) |
599 V_WIN2_MST2_EN(0) | V_WIN2_MST3_EN(0);
600 vop_msk_reg(vop_dev, WIN2_CTRL0, val);
601 vop_msk_reg(vop_dev, WIN3_CTRL0, val);
602 vop_cfg_done(vop_dev);
603 spin_unlock(&vop_dev->reg_lock);
608 static void vop_win_csc_mode(struct vop_device *vop_dev,
609 struct rk_lcdc_win *win,
614 if (win->id == VOP_WIN0) {
615 val = V_WIN0_CSC_MODE(csc_mode);
616 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
617 } else if (win->id == VOP_WIN1) {
618 val = V_WIN1_CSC_MODE(csc_mode);
619 vop_msk_reg(vop_dev, WIN1_CTRL0, val);
621 val = V_HWC_CSC_MODE(csc_mode);
622 vop_msk_reg(vop_dev, HWC_CTRL0, val);
626 static int rk3399_vop_win_csc_cfg(struct rk_lcdc_driver *dev_drv)
628 struct vop_device *vop_dev =
629 container_of(dev_drv, struct vop_device, driver);
630 int output_color = dev_drv->output_color;
633 for (i = 0; i < dev_drv->lcdc_win_num && i <= 4; i++) {
634 struct rk_lcdc_win *win = dev_drv->win[i];
636 u64 val = V_WIN0_YUV2YUV_EN(0) | V_WIN0_YUV2YUV_R2Y_EN(0) |
637 V_WIN0_YUV2YUV_Y2R_EN(0);
641 if (output_color == COLOR_RGB &&
642 !(IS_YUV(win->area[0].fmt_cfg) || win->area[0].yuyv_fmt))
645 if (output_color == COLOR_RGB) {
646 val |= V_WIN0_YUV2YUV_Y2R_EN(1);
647 if (win->colorspace == CSC_BT601) {
649 * Win Y2Y moudle always use 10bit mode.
651 LOAD_CSC(vop_dev, Y2R,
652 csc_y2r_bt601_full_10, i);
653 } else if (win->colorspace == CSC_BT709) {
654 LOAD_CSC(vop_dev, Y2R,
655 csc_y2r_bt709_full_10, i);
656 } else if (win->colorspace == CSC_BT2020) {
657 val |= V_WIN0_YUV2YUV_EN(1);
658 LOAD_CSC(vop_dev, Y2R, csc_y2r_bt2020, i);
659 LOAD_CSC(vop_dev, 3x3, csc_r2r_bt2020to709, i);
661 } else if (output_color == COLOR_YCBCR ||
662 output_color == COLOR_YCBCR_BT709) {
663 if (!(IS_YUV(win->area[0].fmt_cfg) ||
664 win->area[0].yuyv_fmt)) {
665 val |= V_WIN0_YUV2YUV_R2Y_EN(1);
666 LOAD_CSC(vop_dev, R2Y, csc_r2y_bt709_full, i);
667 } else if (win->colorspace == CSC_BT2020) {
668 val |= V_WIN0_YUV2YUV_EN(1) |
669 V_WIN0_YUV2YUV_Y2R_EN(1) |
670 V_WIN0_YUV2YUV_R2Y_EN(1);
671 LOAD_CSC(vop_dev, R2Y, csc_y2r_bt2020, i);
672 LOAD_CSC(vop_dev, R2Y, csc_r2r_bt2020to709, i);
673 LOAD_CSC(vop_dev, R2Y, csc_r2y_bt709_full, i);
675 } else if (output_color == COLOR_YCBCR_BT2020) {
676 if (!(IS_YUV(win->area[0].fmt_cfg) ||
677 win->area[0].yuyv_fmt)) {
678 val |= V_WIN0_YUV2YUV_R2Y_EN(1) |
679 V_WIN0_YUV2YUV_EN(1);
680 LOAD_CSC(vop_dev, R2Y, csc_r2r_bt709to2020, i);
681 LOAD_CSC(vop_dev, R2Y, csc_r2y_bt2020, i);
682 } else if (win->colorspace == CSC_BT601 ||
683 win->colorspace == CSC_BT709) {
684 val |= V_WIN0_YUV2YUV_Y2R_EN(1) |
685 V_WIN0_YUV2YUV_R2Y_EN(1) |
686 V_WIN0_YUV2YUV_EN(1);
687 LOAD_CSC(vop_dev, R2Y, csc_y2r_bt709_full, i);
688 LOAD_CSC(vop_dev, R2Y, csc_r2r_bt709to2020, i);
689 LOAD_CSC(vop_dev, R2Y, csc_r2y_bt2020, i);
693 vop_msk_reg(vop_dev, YUV2YUV_WIN, val << shift);
701 * Input Win csc Post csc Output
702 * 1. YUV(2020) --> bypass ---+ Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
703 * RGB --> R2Y(709) __/
705 * 2. YUV(2020) --> bypass ---+ bypass --> YUV_OUTPUT(2020)
706 * RGB --> R2Y(709) __/
708 * 3. YUV(2020) --> bypass ---+ Y2R->2020To709 --> RGB_OUTPUT(709)
709 * RGB --> R2Y(709) __/
711 * 4. YUV(601/709)-> bypass ---+ Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
712 * RGB --> R2Y(709) __/
714 * 5. YUV(601/709)-> bypass ---+ bypass --> YUV_OUTPUT(709)
715 * RGB --> R2Y(709) __/
717 * 6. YUV(601/709)-> bypass ---+ bypass --> YUV_OUTPUT(601)
718 * RGB --> R2Y(601) __/
720 * 7. YUV(601) --> Y2R(601/mpeg)-+ bypass --> RGB_OUTPUT(709)
721 * RGB --> bypass ____/
723 * 8. YUV(709) --> Y2R(709/hd) --+ bypass --> RGB_OUTPUT(709)
724 * RGB --> bypass ____/
726 * 9. RGB --> bypass ---> 709To2020->R2Y --> YUV_OUTPUT(2020)
728 * 10. RGB --> R2Y(709) ---> bypass --> YUV_OUTPUT(709)
730 * 11. RGB --> R2Y(601) ---> bypass --> YUV_OUTPUT(601)
732 * 12. RGB --> bypass ---> bypass --> RGB_OUTPUT(709)
734 static int rk3228_vop_win_csc_cfg(struct rk_lcdc_driver *dev_drv)
736 struct vop_device *vop_dev =
737 container_of(dev_drv, struct vop_device, driver);
738 struct rk_lcdc_win *win;
739 int output_color = dev_drv->output_color;
740 int win_csc = COLOR_RGB;
741 int r2y_mode = VOP_R2Y_CSC_BT709;
744 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
745 win = dev_drv->win[i];
749 if (IS_YUV(win->area[0].fmt_cfg)) {
750 if (win->colorspace == CSC_BT2020 &&
751 win_csc < COLOR_YCBCR_BT2020) {
752 r2y_mode = VOP_R2Y_CSC_BT709;
753 win_csc = COLOR_YCBCR_BT2020;
756 if (win->colorspace == CSC_BT709 &&
757 win_csc < COLOR_YCBCR_BT709) {
758 r2y_mode = VOP_R2Y_CSC_BT709;
759 win_csc = COLOR_YCBCR_BT709;
762 if (win->colorspace == CSC_BT601 &&
763 win_csc < COLOR_YCBCR) {
764 r2y_mode = VOP_R2Y_CSC_BT709;
765 win_csc = COLOR_YCBCR;
770 if (win_csc == COLOR_RGB) {
771 if (output_color == COLOR_YCBCR_BT709) {
772 r2y_mode = VOP_R2Y_CSC_BT709;
773 win_csc = COLOR_YCBCR_BT709;
774 } else if (output_color == COLOR_YCBCR) {
775 r2y_mode = VOP_R2Y_CSC_BT601;
776 win_csc = COLOR_YCBCR;
780 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
781 win = dev_drv->win[i];
785 if (win_csc != COLOR_RGB && !IS_YUV(win->area[0].fmt_cfg))
786 vop_win_csc_mode(vop_dev, win, r2y_mode);
788 if (IS_YUV(win->area[0].fmt_cfg)) {
789 if (win_csc == COLOR_YCBCR)
790 vop_win_csc_mode(vop_dev, win,
792 else if (win_csc == COLOR_YCBCR_BT709)
793 vop_win_csc_mode(vop_dev, win, VOP_Y2R_CSC_HD);
800 static int vop_post_csc_cfg(struct rk_lcdc_driver *dev_drv)
802 struct vop_device *vop_dev =
803 container_of(dev_drv, struct vop_device, driver);
804 int output_color = dev_drv->output_color;
805 int win_csc, overlay_mode;
808 if (VOP_CHIP(vop_dev) == VOP_RK322X) {
809 win_csc = rk3228_vop_win_csc_cfg(dev_drv);
810 } else if (VOP_CHIP(vop_dev) == VOP_RK3399) {
811 win_csc = rk3399_vop_win_csc_cfg(dev_drv);
814 * RK3399 not support post csc config.
819 val = V_YUV2YUV_POST_Y2R_EN(0) | V_YUV2YUV_POST_EN(0) |
820 V_YUV2YUV_POST_R2Y_EN(0);
822 if (win_csc == COLOR_YCBCR && output_color == COLOR_YCBCR_BT2020) {
823 val |= V_YUV2YUV_POST_Y2R_EN(1);
824 vop_load_csc_table(vop_dev, POST_YUV2YUV_Y2R_COE,
827 if (win_csc == COLOR_YCBCR_BT2020 &&
828 output_color != COLOR_YCBCR_BT2020) {
829 val |= V_YUV2YUV_POST_Y2R_EN(1);
830 vop_load_csc_table(vop_dev, POST_YUV2YUV_Y2R_COE,
835 if ((win_csc == COLOR_YCBCR ||
836 win_csc == COLOR_YCBCR_BT709 ||
837 win_csc == COLOR_RGB) && output_color == COLOR_YCBCR_BT2020) {
838 val |= V_YUV2YUV_POST_EN(1);
839 vop_load_csc_table(vop_dev, POST_YUV2YUV_3x3_COE,
840 csc_r2r_bt709to2020);
842 if (win_csc == COLOR_YCBCR_BT2020 &&
843 (output_color == COLOR_YCBCR ||
844 output_color == COLOR_YCBCR_BT709 ||
845 output_color == COLOR_RGB)) {
846 val |= V_YUV2YUV_POST_EN(1);
847 vop_load_csc_table(vop_dev, POST_YUV2YUV_3x3_COE,
848 csc_r2r_bt2020to709);
852 if (output_color != COLOR_RGB) {
853 val |= V_YUV2YUV_POST_R2Y_EN(1);
855 if (output_color == COLOR_YCBCR_BT2020)
856 vop_load_csc_table(vop_dev, POST_YUV2YUV_R2Y_COE,
859 vop_load_csc_table(vop_dev, POST_YUV2YUV_R2Y_COE,
863 DBG(1, "win_csc=%d output_color=%d val=%llx\n",
864 win_csc, output_color, val);
865 vop_msk_reg(vop_dev, YUV2YUV_POST, val);
867 overlay_mode = (win_csc != COLOR_RGB) ? VOP_YUV_DOMAIN : VOP_RGB_DOMAIN;
868 vop_msk_reg(vop_dev, SYS_CTRL, V_OVERLAY_MODE(overlay_mode));
873 static int vop_post_cfg(struct rk_lcdc_driver *dev_drv)
875 struct vop_device *vop_dev =
876 container_of(dev_drv, struct vop_device, driver);
877 struct rk_screen *screen = dev_drv->cur_screen;
878 u16 x_res = screen->mode.xres;
879 u16 y_res = screen->mode.yres;
881 u16 h_total, v_total;
882 u16 post_hsd_en, post_vsd_en;
883 u16 post_dsp_hact_st, post_dsp_hact_end;
884 u16 post_dsp_vact_st, post_dsp_vact_end;
885 u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
886 u16 post_h_fac, post_v_fac;
888 screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200;
889 screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200;
890 screen->post_xsize = x_res *
891 (dev_drv->overscan.left + dev_drv->overscan.right) / 200;
892 screen->post_ysize = y_res *
893 (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200;
895 h_total = screen->mode.hsync_len + screen->mode.left_margin +
896 x_res + screen->mode.right_margin;
897 v_total = screen->mode.vsync_len + screen->mode.upper_margin +
898 y_res + screen->mode.lower_margin;
900 if (screen->post_dsp_stx + screen->post_xsize > x_res) {
901 dev_warn(vop_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
902 screen->post_dsp_stx, screen->post_xsize, x_res);
903 screen->post_dsp_stx = x_res - screen->post_xsize;
905 if (screen->x_mirror == 0) {
906 post_dsp_hact_st = screen->post_dsp_stx +
907 screen->mode.hsync_len + screen->mode.left_margin;
908 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
910 post_dsp_hact_end = h_total - screen->mode.right_margin -
911 screen->post_dsp_stx;
912 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
914 if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
917 GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
923 if (screen->post_dsp_sty + screen->post_ysize > y_res) {
924 dev_warn(vop_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
925 screen->post_dsp_sty, screen->post_ysize, y_res);
926 screen->post_dsp_sty = y_res - screen->post_ysize;
929 if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
931 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
938 if (screen->mode.vmode & FB_VMODE_INTERLACED) {
939 post_dsp_vact_st = screen->post_dsp_sty / 2 +
940 screen->mode.vsync_len +
941 screen->mode.upper_margin;
942 post_dsp_vact_end = post_dsp_vact_st +
943 screen->post_ysize / 2;
945 post_dsp_vact_st_f1 = screen->mode.vsync_len +
946 screen->mode.upper_margin +
948 screen->mode.lower_margin +
949 screen->mode.vsync_len +
950 screen->mode.upper_margin +
951 screen->post_dsp_sty / 2 +
953 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
954 screen->post_ysize / 2;
956 if (screen->y_mirror == 0) {
957 post_dsp_vact_st = screen->post_dsp_sty +
958 screen->mode.vsync_len +
959 screen->mode.upper_margin;
960 post_dsp_vact_end = post_dsp_vact_st +
963 post_dsp_vact_end = v_total -
964 screen->mode.lower_margin -
965 screen->post_dsp_sty;
966 post_dsp_vact_st = post_dsp_vact_end -
969 post_dsp_vact_st_f1 = 0;
970 post_dsp_vact_end_f1 = 0;
972 DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
973 screen->post_xsize, screen->post_ysize, screen->xpos);
974 DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
975 screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
976 val = V_DSP_HACT_END_POST(post_dsp_hact_end) |
977 V_DSP_HACT_ST_POST(post_dsp_hact_st);
978 vop_msk_reg(vop_dev, POST_DSP_HACT_INFO, val);
980 val = V_DSP_VACT_END_POST(post_dsp_vact_end) |
981 V_DSP_VACT_ST_POST(post_dsp_vact_st);
982 vop_msk_reg(vop_dev, POST_DSP_VACT_INFO, val);
984 val = V_POST_HS_FACTOR_YRGB(post_h_fac) |
985 V_POST_VS_FACTOR_YRGB(post_v_fac);
986 vop_msk_reg(vop_dev, POST_SCL_FACTOR_YRGB, val);
987 val = V_DSP_VACT_END_POST(post_dsp_vact_end_f1) |
988 V_DSP_VACT_ST_POST(post_dsp_vact_st_f1);
989 vop_msk_reg(vop_dev, POST_DSP_VACT_INFO_F1, val);
990 val = V_POST_HOR_SD_EN(post_hsd_en) | V_POST_VER_SD_EN(post_vsd_en);
991 vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
993 vop_post_csc_cfg(dev_drv);
998 static int vop_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
1000 struct vop_device *vop_dev =
1001 container_of(dev_drv, struct vop_device, driver);
1002 struct rk_lcdc_win *win;
1003 u32 colorkey_r, colorkey_g, colorkey_b;
1006 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
1007 win = dev_drv->win[i];
1008 key_val = win->color_key_val;
1009 colorkey_r = (key_val & 0xff) << 2;
1010 colorkey_g = ((key_val >> 8) & 0xff) << 12;
1011 colorkey_b = ((key_val >> 16) & 0xff) << 22;
1012 /* color key dither 565/888->aaa */
1013 key_val = colorkey_r | colorkey_g | colorkey_b;
1016 vop_writel(vop_dev, WIN0_COLOR_KEY, key_val);
1019 vop_writel(vop_dev, WIN1_COLOR_KEY, key_val);
1022 vop_writel(vop_dev, WIN2_COLOR_KEY, key_val);
1025 vop_writel(vop_dev, WIN3_COLOR_KEY, key_val);
1028 pr_info("%s:un support win num:%d\n",
1036 static int vop_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
1038 struct vop_device *vop_dev =
1039 container_of(dev_drv, struct vop_device, driver);
1040 struct rk_lcdc_win *win = dev_drv->win[win_id];
1041 struct alpha_config alpha_config;
1043 int ppixel_alpha = 0, global_alpha = 0, i;
1044 u32 src_alpha_ctl, dst_alpha_ctl;
1047 for (i = 0; i < win->area_num; i++) {
1048 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
1049 (win->area[i].format == FBDC_ARGB_888) ||
1050 (win->area[i].format == FBDC_ABGR_888) ||
1051 (win->area[i].format == ABGR888)) ? 1 : 0;
1054 global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
1056 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
1057 if (!dev_drv->win[i]->state)
1059 if (win->z_order > dev_drv->win[i]->z_order)
1064 * The bottom layer not support ppixel_alpha mode.
1066 if (i == dev_drv->lcdc_win_num)
1068 alpha_config.src_global_alpha_val = win->g_alpha_val;
1069 win->alpha_mode = AB_SRC_OVER;
1071 switch (win->alpha_mode) {
1072 case AB_USER_DEFINE:
1075 alpha_config.src_factor_mode = AA_ZERO;
1076 alpha_config.dst_factor_mode = AA_ZERO;
1079 alpha_config.src_factor_mode = AA_ONE;
1080 alpha_config.dst_factor_mode = AA_ZERO;
1083 alpha_config.src_factor_mode = AA_ZERO;
1084 alpha_config.dst_factor_mode = AA_ONE;
1087 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1089 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
1091 alpha_config.src_factor_mode = AA_ONE;
1092 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1095 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1096 alpha_config.src_factor_mode = AA_SRC_INVERSE;
1097 alpha_config.dst_factor_mode = AA_ONE;
1100 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1101 alpha_config.src_factor_mode = AA_SRC;
1102 alpha_config.dst_factor_mode = AA_ZERO;
1105 alpha_config.src_factor_mode = AA_ZERO;
1106 alpha_config.dst_factor_mode = AA_SRC;
1109 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1110 alpha_config.src_factor_mode = AA_SRC_INVERSE;
1111 alpha_config.dst_factor_mode = AA_ZERO;
1114 alpha_config.src_factor_mode = AA_ZERO;
1115 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1118 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1119 alpha_config.src_factor_mode = AA_SRC;
1120 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1123 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1124 alpha_config.src_factor_mode = AA_SRC_INVERSE;
1125 alpha_config.dst_factor_mode = AA_SRC;
1128 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1129 alpha_config.src_factor_mode = AA_SRC_INVERSE;
1130 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1132 case AB_SRC_OVER_GLOBAL:
1133 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
1134 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
1135 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
1136 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1139 pr_err("alpha mode error\n");
1142 if ((ppixel_alpha == 1) && (global_alpha == 1))
1143 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
1144 else if (ppixel_alpha == 1)
1145 alpha_config.src_global_alpha_mode = AA_PER_PIX;
1146 else if (global_alpha == 1)
1147 alpha_config.src_global_alpha_mode = AA_GLOBAL;
1150 alpha_config.src_alpha_mode = AA_STRAIGHT;
1151 alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
1155 src_alpha_ctl = 0x60;
1156 dst_alpha_ctl = 0x64;
1159 src_alpha_ctl = 0xa0;
1160 dst_alpha_ctl = 0xa4;
1163 src_alpha_ctl = 0xdc;
1164 dst_alpha_ctl = 0xec;
1167 src_alpha_ctl = 0x12c;
1168 dst_alpha_ctl = 0x13c;
1171 src_alpha_ctl = 0x160;
1172 dst_alpha_ctl = 0x164;
1175 val = V_WIN0_DST_FACTOR_MODE(alpha_config.dst_factor_mode);
1176 vop_msk_reg(vop_dev, dst_alpha_ctl, val);
1177 val = V_WIN0_SRC_ALPHA_EN(alpha_en) |
1178 V_WIN0_SRC_COLOR_MODE(alpha_config.src_color_mode) |
1179 V_WIN0_SRC_ALPHA_MODE(alpha_config.src_alpha_mode) |
1180 V_WIN0_SRC_BLEND_MODE(alpha_config.src_global_alpha_mode) |
1181 V_WIN0_SRC_ALPHA_CAL_MODE(alpha_config.src_alpha_cal_m0) |
1182 V_WIN0_SRC_FACTOR_MODE(alpha_config.src_factor_mode) |
1183 V_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
1185 vop_msk_reg(vop_dev, src_alpha_ctl, val);
1190 static int vop_axi_gather_cfg(struct vop_device *vop_dev,
1191 struct rk_lcdc_win *win)
1194 u16 yrgb_gather_num = 3;
1195 u16 cbcr_gather_num = 1;
1197 switch (win->area[0].format) {
1204 yrgb_gather_num = 3;
1209 yrgb_gather_num = 2;
1220 yrgb_gather_num = 1;
1221 cbcr_gather_num = 2;
1225 yrgb_gather_num = 2;
1226 cbcr_gather_num = 2;
1229 dev_err(vop_dev->driver.dev, "%s:un supported format[%d]\n",
1230 __func__, win->area[0].format);
1234 if ((win->id == VOP_WIN0) || (win->id == VOP_WIN1)) {
1235 val = V_WIN0_YRGB_AXI_GATHER_EN(1) |
1236 V_WIN0_CBR_AXI_GATHER_EN(1) |
1237 V_WIN0_YRGB_AXI_GATHER_NUM(yrgb_gather_num) |
1238 V_WIN0_CBR_AXI_GATHER_NUM(cbcr_gather_num);
1239 vop_msk_reg(vop_dev, WIN0_CTRL1 + (win->id * 0x40), val);
1240 } else if ((win->id == VOP_WIN2) || (win->id == VOP_WIN3)) {
1241 val = V_WIN2_AXI_GATHER_EN(1) |
1242 V_WIN2_AXI_GATHER_NUM(yrgb_gather_num);
1243 vop_msk_reg(vop_dev, WIN2_CTRL1 + ((win->id - 2) * 0x50), val);
1244 } else if (win->id == VOP_HWC) {
1245 val = V_HWC_AXI_GATHER_EN(1) |
1246 V_HWC_AXI_GATHER_NUM(yrgb_gather_num);
1247 vop_msk_reg(vop_dev, HWC_CTRL1, val);
1252 static int vop_fbdc_reg_update(struct vop_device *vop_dev, int win_id)
1254 struct rk_lcdc_win *win = vop_dev->driver.win[win_id];
1257 val = V_VOP_FBDC_WIN_SEL(win_id) |
1258 V_AFBCD_HREG_PIXEL_PACKING_FMT(win->area[0].fbdc_fmt_cfg) |
1259 V_AFBCD_HREG_BLOCK_SPLIT(win->area[0].fbdc_cor_en);
1260 vop_msk_reg(vop_dev, AFBCD0_CTRL, val);
1262 val = V_AFBCD_HREG_PIC_WIDTH(win->area[0].fbdc_mb_width - 1) |
1263 V_AFBCD_HREG_PIC_HEIGHT(win->area[0].fbdc_mb_height - 1);
1264 vop_msk_reg(vop_dev, AFBCD0_PIC_SIZE, val);
1269 static int vop_init_fbdc_config(struct vop_device *vop_dev, int win_id)
1271 struct rk_lcdc_driver *vop_drv = &vop_dev->driver;
1272 struct rk_lcdc_win *win = vop_drv->win[win_id];
1273 struct rk_screen *screen = vop_drv->cur_screen;
1275 if (screen->mode.flag & FB_VMODE_INTERLACED) {
1276 dev_err(vop_dev->dev, "unsupport fbdc+interlace!\n");
1280 if (VOP_CHIP(vop_dev) != VOP_RK3399) {
1281 pr_err("soc: 0x%08x not support FBDC\n", VOP_CHIP(vop_dev));
1285 win->area[0].fbdc_mb_width = win->area[0].xact;
1286 win->area[0].fbdc_mb_height = win->area[0].yact;
1287 win->area[0].fbdc_cor_en = 0; /* hreg_block_split */
1288 win->area[0].fbdc_fmt_cfg |= 0 << 4;
1293 static int vop_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1295 struct vop_device *vop_dev =
1296 container_of(dev_drv, struct vop_device, driver);
1297 struct rk_lcdc_win *win = dev_drv->win[win_id];
1302 off = win_id * 0x40;
1304 if (win->state == 1) {
1305 vop_axi_gather_cfg(vop_dev, win);
1306 if (win->area[0].fbdc_en)
1307 vop_fbdc_reg_update(vop_dev, win_id);
1309 * rk322x have a bug on windows 0 and 1:
1311 * When switch win format from RGB to YUV, would flash
1312 * some green lines on the top of the windows.
1314 * Use bg_en show one blank frame to skip the error frame.
1316 if (IS_YUV(win->area[0].fmt_cfg)) {
1317 val = vop_readl(vop_dev, WIN0_CTRL0);
1318 format = (val & MASK(WIN0_DATA_FMT)) >> 1;
1320 if (!IS_YUV(format)) {
1321 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1322 val = V_WIN0_DSP_BG_RED(0x200) |
1323 V_WIN0_DSP_BG_GREEN(0x40) |
1324 V_WIN0_DSP_BG_BLUE(0x200) |
1326 vop_msk_reg(vop_dev, WIN0_DSP_BG + off,
1329 val = V_WIN0_DSP_BG_RED(0) |
1330 V_WIN0_DSP_BG_GREEN(0) |
1331 V_WIN0_DSP_BG_BLUE(0) |
1333 vop_msk_reg(vop_dev, WIN0_DSP_BG + off,
1337 val = V_WIN0_BG_EN(0);
1338 vop_msk_reg(vop_dev, WIN0_DSP_BG + off, val);
1341 val = V_WIN0_BG_EN(0);
1342 vop_msk_reg(vop_dev, WIN0_DSP_BG + off, val);
1345 val = V_WIN0_EN(win->state) |
1346 V_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1347 V_WIN0_FMT_10(win->fmt_10) |
1348 V_WIN0_LB_MODE(win->win_lb_mode) |
1349 V_WIN0_RB_SWAP(win->area[0].swap_rb) |
1350 V_WIN0_X_MIR_EN(win->xmirror) |
1351 V_WIN0_Y_MIR_EN(win->ymirror) |
1352 V_WIN0_UV_SWAP(win->area[0].swap_uv);
1353 if (VOP_CHIP(vop_dev) == VOP_RK3399)
1354 val |= V_WIN0_YUYV(win->area[0].yuyv_fmt);
1355 vop_msk_reg(vop_dev, WIN0_CTRL0 + off, val);
1356 val = V_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1357 V_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1358 V_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1359 V_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1360 V_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1361 V_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1362 V_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1363 V_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1364 V_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1365 V_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1366 V_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1367 V_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1368 V_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1369 V_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1370 V_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1371 vop_msk_reg(vop_dev, WIN0_CTRL1 + off, val);
1372 val = V_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1373 V_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1374 vop_writel(vop_dev, WIN0_VIR + off, val);
1375 val = V_WIN0_ACT_WIDTH(win->area[0].xact - 1) |
1376 V_WIN0_ACT_HEIGHT(win->area[0].yact - 1);
1377 vop_writel(vop_dev, WIN0_ACT_INFO + off, val);
1379 val = V_WIN0_DSP_WIDTH(win->area[0].xsize - 1) |
1380 V_WIN0_DSP_HEIGHT(win->area[0].ysize - 1);
1381 vop_writel(vop_dev, WIN0_DSP_INFO + off, val);
1383 val = V_WIN0_DSP_XST(win->area[0].dsp_stx) |
1384 V_WIN0_DSP_YST(win->area[0].dsp_sty);
1385 vop_writel(vop_dev, WIN0_DSP_ST + off, val);
1387 val = V_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1388 V_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1389 vop_writel(vop_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1391 val = V_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1392 V_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1393 vop_writel(vop_dev, WIN0_SCL_FACTOR_CBR + off, val);
1394 if (win->alpha_en == 1) {
1395 vop_alpha_cfg(dev_drv, win_id);
1397 val = V_WIN0_SRC_ALPHA_EN(0);
1398 vop_msk_reg(vop_dev, WIN0_SRC_ALPHA_CTRL + off, val);
1402 val = V_WIN0_EN(win->state);
1403 vop_msk_reg(vop_dev, WIN0_CTRL0 + off, val);
1409 static int area_xst(struct rk_lcdc_win *win, int area_num)
1411 struct rk_lcdc_win_area area_temp;
1414 for (i = 0; i < area_num; i++) {
1415 for (j = i + 1; j < area_num; j++) {
1416 if (win->area[i].dsp_stx > win->area[j].dsp_stx) {
1417 memcpy(&area_temp, &win->area[i],
1418 sizeof(struct rk_lcdc_win_area));
1419 memcpy(&win->area[i], &win->area[j],
1420 sizeof(struct rk_lcdc_win_area));
1421 memcpy(&win->area[j], &area_temp,
1422 sizeof(struct rk_lcdc_win_area));
1430 static int vop_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1432 struct vop_device *vop_dev =
1433 container_of(dev_drv, struct vop_device, driver);
1434 struct rk_lcdc_win *win = dev_drv->win[win_id];
1438 off = (win_id - 2) * 0x50;
1439 area_xst(win, win->area_num);
1441 if (win->state == 1) {
1442 vop_axi_gather_cfg(vop_dev, win);
1443 if (win->area[0].fbdc_en)
1444 vop_fbdc_reg_update(vop_dev, win_id);
1445 val = V_WIN2_EN(1) | V_WIN1_CSC_MODE(win->csc_mode);
1446 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1448 if (win->area[0].state == 1) {
1449 val = V_WIN2_MST0_EN(win->area[0].state) |
1450 V_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1451 V_WIN2_RB_SWAP0(win->area[0].swap_rb);
1452 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1454 val = V_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1455 vop_msk_reg(vop_dev, WIN2_VIR0_1 + off, val);
1457 val = V_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1458 V_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1459 vop_writel(vop_dev, WIN2_DSP_INFO0 + off, val);
1460 val = V_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1461 V_WIN2_DSP_YST0(win->area[0].dsp_sty);
1462 vop_writel(vop_dev, WIN2_DSP_ST0 + off, val);
1464 val = V_WIN2_MST0_EN(0);
1465 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1468 if (win->area[1].state == 1) {
1469 val = V_WIN2_MST1_EN(win->area[1].state) |
1470 V_WIN2_DATA_FMT1(win->area[1].fmt_cfg) |
1471 V_WIN2_RB_SWAP1(win->area[1].swap_rb);
1472 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1474 val = V_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1475 vop_msk_reg(vop_dev, WIN2_VIR0_1 + off, val);
1477 val = V_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1478 V_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1479 vop_writel(vop_dev, WIN2_DSP_INFO1 + off, val);
1480 val = V_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1481 V_WIN2_DSP_YST1(win->area[1].dsp_sty);
1482 vop_writel(vop_dev, WIN2_DSP_ST1 + off, val);
1484 val = V_WIN2_MST1_EN(0);
1485 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1488 if (win->area[2].state == 1) {
1489 val = V_WIN2_MST2_EN(win->area[2].state) |
1490 V_WIN2_DATA_FMT2(win->area[2].fmt_cfg) |
1491 V_WIN2_RB_SWAP2(win->area[2].swap_rb);
1492 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1494 val = V_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1495 vop_msk_reg(vop_dev, WIN2_VIR2_3 + off, val);
1497 val = V_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1498 V_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1499 vop_writel(vop_dev, WIN2_DSP_INFO2 + off, val);
1500 val = V_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1501 V_WIN2_DSP_YST2(win->area[2].dsp_sty);
1502 vop_writel(vop_dev, WIN2_DSP_ST2 + off, val);
1504 val = V_WIN2_MST2_EN(0);
1505 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1508 if (win->area[3].state == 1) {
1509 val = V_WIN2_MST3_EN(win->area[3].state) |
1510 V_WIN2_DATA_FMT3(win->area[3].fmt_cfg) |
1511 V_WIN2_RB_SWAP3(win->area[3].swap_rb);
1512 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1514 val = V_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1515 vop_msk_reg(vop_dev, WIN2_VIR2_3 + off, val);
1517 val = V_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1518 V_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1519 vop_writel(vop_dev, WIN2_DSP_INFO3 + off, val);
1520 val = V_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1521 V_WIN2_DSP_YST3(win->area[3].dsp_sty);
1522 vop_writel(vop_dev, WIN2_DSP_ST3 + off, val);
1524 val = V_WIN2_MST3_EN(0);
1525 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1528 if (win->alpha_en == 1) {
1529 vop_alpha_cfg(dev_drv, win_id);
1531 val = V_WIN2_SRC_ALPHA_EN(0);
1532 vop_msk_reg(vop_dev, WIN2_SRC_ALPHA_CTRL + off, val);
1535 val = V_WIN2_EN(win->state) | V_WIN2_MST0_EN(0) |
1536 V_WIN2_MST1_EN(0) | V_WIN2_MST2_EN(0) | V_WIN2_MST3_EN(0);
1537 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1543 static int vop_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1545 struct vop_device *vop_dev =
1546 container_of(dev_drv, struct vop_device, driver);
1547 struct rk_lcdc_win *win = dev_drv->win[win_id];
1548 unsigned int hwc_size = 0;
1551 if (win->state == 1) {
1552 vop_axi_gather_cfg(vop_dev, win);
1553 val = V_HWC_EN(1) | V_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1554 V_HWC_RB_SWAP(win->area[0].swap_rb);
1555 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1557 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1559 else if ((win->area[0].xsize == 64) &&
1560 (win->area[0].ysize == 64))
1562 else if ((win->area[0].xsize == 96) &&
1563 (win->area[0].ysize == 96))
1565 else if ((win->area[0].xsize == 128) &&
1566 (win->area[0].ysize == 128))
1569 dev_err(vop_dev->dev, "un supported hwc size[%dx%d]!\n",
1570 win->area[0].xsize, win->area[0].ysize);
1572 val = V_HWC_SIZE(hwc_size);
1573 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1575 val = V_HWC_DSP_XST(win->area[0].dsp_stx) |
1576 V_HWC_DSP_YST(win->area[0].dsp_sty);
1577 vop_msk_reg(vop_dev, HWC_DSP_ST, val);
1579 if (win->alpha_en == 1) {
1580 vop_alpha_cfg(dev_drv, win_id);
1582 val = V_WIN2_SRC_ALPHA_EN(0);
1583 vop_msk_reg(vop_dev, HWC_SRC_ALPHA_CTRL, val);
1586 val = V_HWC_EN(win->state);
1587 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1593 static int vop_layer_update_regs(struct vop_device *vop_dev,
1594 struct rk_lcdc_win *win)
1596 struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
1598 if (likely(vop_dev->clk_on)) {
1599 vop_msk_reg(vop_dev, SYS_CTRL,
1600 V_VOP_STANDBY_EN(vop_dev->standby));
1601 if ((win->id == VOP_WIN0) || (win->id == VOP_WIN1))
1602 vop_win_0_1_reg_update(dev_drv, win->id);
1603 else if ((win->id == VOP_WIN2) || (win->id == VOP_WIN3))
1604 vop_win_2_3_reg_update(dev_drv, win->id);
1605 else if (win->id == VOP_HWC)
1606 vop_hwc_reg_update(dev_drv, win->id);
1607 vop_cfg_done(vop_dev);
1610 DBG(2, "%s for lcdc%d\n", __func__, vop_dev->id);
1614 static int __maybe_unused vop_mmu_en(struct rk_lcdc_driver *dev_drv)
1617 struct vop_device *vop_dev =
1618 container_of(dev_drv, struct vop_device, driver);
1620 if (unlikely(!vop_dev->clk_on)) {
1621 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
1624 if (dev_drv->iommu_enabled) {
1625 if (!vop_dev->iommu_status && dev_drv->mmu_dev) {
1626 if (likely(vop_dev->clk_on)) {
1627 val = V_VOP_MMU_EN(1);
1628 vop_msk_reg(vop_dev, SYS_CTRL, val);
1629 val = V_AXI_OUTSTANDING_MAX_NUM(31) |
1630 V_AXI_MAX_OUTSTANDING_EN(1);
1631 vop_msk_reg(vop_dev, SYS_CTRL1, val);
1633 vop_dev->iommu_status = 1;
1634 rockchip_iovmm_activate(dev_drv->dev);
1640 static int vop_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate)
1642 int ret = 0, fps = 0;
1643 struct vop_device *vop_dev =
1644 container_of(dev_drv, struct vop_device, driver);
1645 struct rk_screen *screen = dev_drv->cur_screen;
1646 #ifdef CONFIG_RK_FPGA
1650 ret = clk_set_rate(vop_dev->dclk, screen->mode.pixclock);
1652 dev_err(dev_drv->dev, "set lcdc%d dclk[%d] failed\n",
1653 vop_dev->id, screen->mode.pixclock);
1655 div_u64(1000000000000llu, clk_get_rate(vop_dev->dclk));
1656 vop_dev->driver.pixclock = vop_dev->pixclock;
1658 fps = rk_fb_calc_fps(screen, vop_dev->pixclock);
1659 screen->ft = 1000 / fps;
1660 dev_info(vop_dev->dev, "%s: dclk:%lu>>fps:%d ",
1661 vop_dev->driver.name, clk_get_rate(vop_dev->dclk), fps);
1665 static int vop_config_timing(struct rk_lcdc_driver *dev_drv)
1667 struct vop_device *vop_dev =
1668 container_of(dev_drv, struct vop_device, driver);
1669 struct rk_screen *screen = dev_drv->cur_screen;
1670 u16 hsync_len = screen->mode.hsync_len;
1671 u16 left_margin = screen->mode.left_margin;
1672 u16 right_margin = screen->mode.right_margin;
1673 u16 vsync_len = screen->mode.vsync_len;
1674 u16 upper_margin = screen->mode.upper_margin;
1675 u16 lower_margin = screen->mode.lower_margin;
1676 u16 x_res = screen->mode.xres;
1677 u16 y_res = screen->mode.yres;
1679 u16 h_total, v_total;
1680 u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1682 h_total = hsync_len + left_margin + x_res + right_margin;
1683 v_total = vsync_len + upper_margin + y_res + lower_margin;
1685 val = V_DSP_HS_END(hsync_len) | V_DSP_HTOTAL(h_total);
1686 vop_msk_reg(vop_dev, DSP_HTOTAL_HS_END, val);
1688 val = V_DSP_HACT_END(hsync_len + left_margin + x_res) |
1689 V_DSP_HACT_ST(hsync_len + left_margin);
1690 vop_msk_reg(vop_dev, DSP_HACT_ST_END, val);
1692 if (screen->mode.vmode & FB_VMODE_INTERLACED) {
1693 /* First Field Timing */
1694 val = V_DSP_VS_END(vsync_len) |
1695 V_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1696 lower_margin) + y_res + 1);
1697 vop_msk_reg(vop_dev, DSP_VTOTAL_VS_END, val);
1699 val = V_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1700 V_DSP_VACT_ST(vsync_len + upper_margin);
1701 vop_msk_reg(vop_dev, DSP_VACT_ST_END, val);
1703 /* Second Field Timing */
1704 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1705 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1707 val = V_DSP_VS_ST_F1(vs_st_f1) | V_DSP_VS_END_F1(vs_end_f1);
1708 vop_msk_reg(vop_dev, DSP_VS_ST_END_F1, val);
1710 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1712 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1714 val = V_DSP_VACT_END_F1(vact_end_f1) |
1715 V_DSP_VACT_ST_F1(vact_st_f1);
1716 vop_msk_reg(vop_dev, DSP_VACT_ST_END_F1, val);
1717 vop_msk_reg(vop_dev, DSP_CTRL0,
1718 V_DSP_INTERLACE(1) | V_DSP_FIELD_POL(0));
1720 val = V_DSP_LINE_FLAG_NUM_0(lower_margin ?
1721 vact_end_f1 : vact_end_f1 - 1);
1723 val |= V_DSP_LINE_FLAG_NUM_1(lower_margin ?
1724 vact_end_f1 : vact_end_f1 - 1);
1725 vop_msk_reg(vop_dev, LINE_FLAG, val);
1727 val = V_DSP_VS_END(vsync_len) | V_DSP_VTOTAL(v_total);
1728 vop_msk_reg(vop_dev, DSP_VTOTAL_VS_END, val);
1730 val = V_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1731 V_DSP_VACT_ST(vsync_len + upper_margin);
1732 vop_msk_reg(vop_dev, DSP_VACT_ST_END, val);
1734 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_INTERLACE(0) |
1735 V_DSP_FIELD_POL(0));
1737 val = V_DSP_LINE_FLAG_NUM_0(vsync_len + upper_margin + y_res) |
1738 V_DSP_LINE_FLAG_NUM_1(vsync_len + upper_margin + y_res);
1739 vop_msk_reg(vop_dev, LINE_FLAG, val);
1741 vop_post_cfg(dev_drv);
1746 static void vop_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1748 struct vop_device *vop_dev =
1749 container_of(dev_drv, struct vop_device, driver);
1752 vop_msk_reg(vop_dev, SYS_CTRL, V_OVERLAY_MODE(dev_drv->overlay_mode));
1753 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1754 if (dev_drv->output_color == COLOR_YCBCR) /* bypass */
1755 vop_msk_reg(vop_dev, BCSH_CTRL,
1756 V_BCSH_Y2R_EN(0) | V_BCSH_R2Y_EN(0));
1758 vop_msk_reg(vop_dev, BCSH_CTRL, V_BCSH_Y2R_EN(1) |
1759 V_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1762 /* overlay_mode=VOP_RGB_DOMAIN */
1763 /* bypass --need check,if bcsh close? */
1764 if (dev_drv->output_color == COLOR_RGB) {
1765 bcsh_ctrl = vop_readl(vop_dev, BCSH_CTRL);
1766 if (((bcsh_ctrl & MASK(BCSH_EN)) == 1) ||
1767 (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1768 vop_msk_reg(vop_dev, BCSH_CTRL,
1772 vop_msk_reg(vop_dev, BCSH_CTRL,
1777 vop_msk_reg(vop_dev, BCSH_CTRL,
1779 V_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1785 static int vop_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1786 u16 *yact, int *format, u32 *dsp_addr,
1789 struct vop_device *vop_dev =
1790 container_of(dev_drv, struct vop_device, driver);
1793 spin_lock(&vop_dev->reg_lock);
1795 val = vop_readl(vop_dev, WIN0_ACT_INFO);
1796 *xact = (val & MASK(WIN0_ACT_WIDTH)) + 1;
1797 *yact = ((val & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1;
1799 val = vop_readl(vop_dev, WIN0_CTRL0);
1800 *format = (val & MASK(WIN0_DATA_FMT)) >> 1;
1801 *ymirror = (val & MASK(WIN0_Y_MIR_EN)) >> 22;
1802 *dsp_addr = vop_readl(vop_dev, WIN0_YRGB_MST);
1804 spin_unlock(&vop_dev->reg_lock);
1809 static int vop_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1810 int format, u16 xact, u16 yact, u16 xvir,
1813 struct vop_device *vop_dev =
1814 container_of(dev_drv, struct vop_device, driver);
1815 int swap = (format == RGB888) ? 1 : 0;
1816 struct rk_lcdc_win *win = dev_drv->win[0];
1819 val = V_WIN0_DATA_FMT(format) | V_WIN0_RB_SWAP(swap) |
1820 V_WIN0_Y_MIR_EN(ymirror);
1821 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
1823 vop_msk_reg(vop_dev, WIN0_VIR, V_WIN0_VIR_STRIDE(xvir));
1824 vop_writel(vop_dev, WIN0_ACT_INFO, V_WIN0_ACT_WIDTH(xact - 1) |
1825 V_WIN0_ACT_HEIGHT(yact - 1));
1827 vop_writel(vop_dev, WIN0_YRGB_MST, rgb_mst);
1829 vop_cfg_done(vop_dev);
1831 if (format == RGB888)
1832 win->area[0].format = BGR888;
1834 win->area[0].format = format;
1836 win->ymirror = ymirror;
1838 win->last_state = 1;
1843 static int vop_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1847 struct vop_device *vop_dev =
1848 container_of(dev_drv, struct vop_device, driver);
1849 struct rk_screen *screen = dev_drv->cur_screen;
1852 if (unlikely(!vop_dev->clk_on)) {
1853 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
1857 if (!vop_dev->standby && initscreen && (dev_drv->first_frame != 1))
1858 flush_kthread_worker(&dev_drv->update_regs_worker);
1860 spin_lock(&vop_dev->reg_lock);
1861 if (likely(vop_dev->clk_on)) {
1862 switch (screen->face) {
1865 val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) |
1866 V_PRE_DITHER_DOWN_EN(1) |
1867 V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(0);
1871 val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) |
1872 V_PRE_DITHER_DOWN_EN(1) |
1873 V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(1);
1877 val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) |
1878 V_PRE_DITHER_DOWN_EN(1) |
1879 V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(0);
1883 val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) |
1884 V_PRE_DITHER_DOWN_EN(1) |
1885 V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(1);
1889 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1)
1890 | V_PRE_DITHER_DOWN_EN(1) |
1891 V_DITHER_DOWN_SEL(0) | V_DITHER_DOWN_MODE(0);
1896 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) |
1897 V_PRE_DITHER_DOWN_EN(1) |
1898 V_DITHER_DOWN_SEL(0) |
1899 V_DITHER_DOWN_MODE(0);
1901 case OUT_YUV_420_10BIT:
1904 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) |
1905 V_PRE_DITHER_DOWN_EN(0) |
1906 V_DITHER_DOWN_SEL(0) |
1907 V_DITHER_DOWN_MODE(0);
1911 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) |
1912 V_PRE_DITHER_DOWN_EN(0) |
1913 V_DITHER_DOWN_SEL(0) |
1914 V_DITHER_DOWN_MODE(0);
1917 dev_err(vop_dev->dev, "un supported screen face[%d]!\n",
1922 vop_msk_reg(vop_dev, DSP_CTRL1, val);
1923 switch (screen->type) {
1925 val = V_SW_UV_OFFSET_EN(1) | V_SW_IMD_TVE_DCLK_EN(1) |
1926 V_SW_IMD_TVE_DCLK_EN(1) |
1927 V_SW_IMD_TVE_DCLK_POL(1) |
1928 V_SW_GENLOCK(1) | V_SW_DAC_SEL(1);
1929 if (screen->mode.xres == 720 &&
1930 screen->mode.yres == 576)
1931 val |= V_SW_TVE_MODE(1);
1933 val |= V_SW_TVE_MODE(0);
1934 vop_msk_reg(vop_dev, SYS_CTRL, val);
1937 val = V_HDMI_OUT_EN(1) | V_SW_UV_OFFSET_EN(0);
1938 vop_msk_reg(vop_dev, SYS_CTRL, val);
1942 val = V_RGB_OUT_EN(1);
1943 vop_msk_reg(vop_dev, SYS_CTRL, val);
1945 val = V_MIPI_OUT_EN(1);
1946 vop_msk_reg(vop_dev, SYS_CTRL, val);
1948 val = V_EDP_OUT_EN(1);
1949 vop_msk_reg(vop_dev, SYS_CTRL, val);
1952 dev_err(vop_dev->dev, "un supported interface[%d]!\n",
1956 val = V_HDMI_HSYNC_POL(screen->pin_hsync) |
1957 V_HDMI_VSYNC_POL(screen->pin_vsync) |
1958 V_HDMI_DEN_POL(screen->pin_den) |
1959 V_HDMI_DCLK_POL(screen->pin_dclk);
1960 /*hsync vsync den dclk polo,dither */
1961 vop_msk_reg(vop_dev, DSP_CTRL1, val);
1963 if (screen->color_mode == COLOR_RGB)
1964 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1966 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1968 #ifndef CONFIG_RK_FPGA
1971 * writel_relaxed(v, RK_GRF_VIRT + vop_GRF_SOC_CON7);
1972 * move to lvds driver
1974 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
1976 val = V_DSP_OUT_MODE(face) | V_DSP_DCLK_DDR(dclk_ddr) |
1977 V_DSP_BG_SWAP(screen->swap_gb) |
1978 V_DSP_RB_SWAP(screen->swap_rb) |
1979 V_DSP_RG_SWAP(screen->swap_rg) |
1980 V_DSP_DELTA_SWAP(screen->swap_delta) |
1981 V_DSP_DUMMY_SWAP(screen->swap_dumy) | V_DSP_OUT_ZERO(0) |
1982 V_DSP_BLANK_EN(0) | V_DSP_BLACK_EN(0) |
1983 V_DSP_X_MIR_EN(screen->x_mirror) |
1984 V_DSP_Y_MIR_EN(screen->y_mirror);
1985 val |= V_SW_CORE_DCLK_SEL(!!screen->pixelrepeat);
1986 if (screen->mode.vmode & FB_VMODE_INTERLACED)
1987 val |= V_SW_HDMI_CLK_I_SEL(1);
1989 val |= V_SW_HDMI_CLK_I_SEL(0);
1990 vop_msk_reg(vop_dev, DSP_CTRL0, val);
1992 if (screen->mode.vmode & FB_VMODE_INTERLACED)
1993 vop_msk_reg(vop_dev, SYS_CTRL1, V_REG_DONE_FRM(1));
1995 vop_msk_reg(vop_dev, SYS_CTRL1, V_REG_DONE_FRM(0));
1997 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1998 val = V_DSP_OUT_RGB_YUV(1);
1999 vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
2000 val = V_DSP_BG_BLUE(0x200) | V_DSP_BG_GREEN(0x40) |
2001 V_DSP_BG_RED(0x200);
2002 vop_msk_reg(vop_dev, DSP_BG, val);
2004 val = V_DSP_OUT_RGB_YUV(0);
2005 vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
2006 val = V_DSP_BG_BLUE(0x55) | V_DSP_BG_GREEN(0x55) |
2008 vop_msk_reg(vop_dev, DSP_BG, val);
2010 dev_drv->output_color = screen->color_mode;
2011 vop_bcsh_path_sel(dev_drv);
2012 vop_config_timing(dev_drv);
2013 vop_cfg_done(vop_dev);
2015 spin_unlock(&vop_dev->reg_lock);
2016 vop_set_dclk(dev_drv, 1);
2017 if (screen->type != SCREEN_HDMI && screen->type != SCREEN_TVOUT &&
2018 dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2019 dev_drv->trsm_ops->enable();
2026 /*enable layer,open:1,enable;0 disable*/
2027 static void vop_layer_enable(struct vop_device *vop_dev,
2028 unsigned int win_id, bool open)
2030 spin_lock(&vop_dev->reg_lock);
2031 if (likely(vop_dev->clk_on) &&
2032 vop_dev->driver.win[win_id]->state != open) {
2034 if (!vop_dev->atv_layer_cnt) {
2035 dev_info(vop_dev->dev,
2036 "wakeup from standby!\n");
2037 vop_dev->standby = 0;
2039 vop_dev->atv_layer_cnt |= (1 << win_id);
2041 if (vop_dev->atv_layer_cnt & (1 << win_id))
2042 vop_dev->atv_layer_cnt &= ~(1 << win_id);
2044 vop_dev->driver.win[win_id]->state = open;
2046 vop_layer_update_regs(vop_dev,
2047 vop_dev->driver.win[win_id]);
2048 vop_cfg_done(vop_dev);
2050 /* if no layer used,disable lcdc */
2051 if (!vop_dev->atv_layer_cnt) {
2052 dev_info(vop_dev->dev,
2053 "no layer is used,go to standby!\n");
2054 vop_dev->standby = 1;
2057 spin_unlock(&vop_dev->reg_lock);
2060 static int vop_enable_irq(struct rk_lcdc_driver *dev_drv)
2062 struct vop_device *vop_dev = container_of(dev_drv,
2063 struct vop_device, driver);
2065 /* struct rk_screen *screen = dev_drv->cur_screen; */
2067 vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, INTR_MASK);
2069 val = INTR_FS | INTR_LINE_FLAG0 | INTR_BUS_ERROR | INTR_LINE_FLAG1 |
2070 INTR_WIN0_EMPTY | INTR_WIN1_EMPTY | INTR_HWC_EMPTY |
2071 INTR_POST_BUF_EMPTY;
2073 vop_mask_writel(vop_dev, INTR_EN0, INTR_MASK, val);
2078 static int vop_open(struct rk_lcdc_driver *dev_drv, int win_id,
2081 struct vop_device *vop_dev =
2082 container_of(dev_drv, struct vop_device, driver);
2084 /* enable clk,when first layer open */
2085 if ((open) && (!vop_dev->atv_layer_cnt)) {
2086 /* rockchip_set_system_status(sys_status); */
2087 vop_pre_init(dev_drv);
2088 vop_clk_enable(vop_dev);
2089 vop_enable_irq(dev_drv);
2090 if (dev_drv->iommu_enabled) {
2091 if (!dev_drv->mmu_dev) {
2093 rk_fb_get_sysmmu_device_by_compatible
2094 (dev_drv->mmu_dts_name);
2095 if (dev_drv->mmu_dev) {
2096 rk_fb_platform_set_sysmmu
2097 (dev_drv->mmu_dev, dev_drv->dev);
2099 dev_err(dev_drv->dev,
2100 "fail get rk iommu device\n");
2105 if ((support_uboot_display() && (vop_dev->prop == PRMRY)))
2106 vop_set_dclk(dev_drv, 0);
2108 vop_load_screen(dev_drv, 1);
2109 if (dev_drv->bcsh.enable)
2110 vop_set_bcsh(dev_drv, 1);
2111 vop_set_lut(dev_drv, dev_drv->cur_screen->dsp_lut);
2112 vop_set_cabc(dev_drv, dev_drv->cur_screen->cabc_lut);
2115 if (win_id < dev_drv->lcdc_win_num)
2116 vop_layer_enable(vop_dev, win_id, open);
2118 dev_err(vop_dev->dev, "invalid win id:%d\n", win_id);
2120 dev_drv->first_frame = 0;
2124 static int win_0_1_display(struct vop_device *vop_dev,
2125 struct rk_lcdc_win *win)
2131 off = win->id * 0x40;
2132 /*win->smem_start + win->y_offset; */
2133 y_addr = win->area[0].smem_start + win->area[0].y_offset;
2134 uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
2135 DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
2136 vop_dev->id, win->id, y_addr, uv_addr);
2137 DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
2138 win->area[0].y_offset, win->area[0].c_offset);
2139 spin_lock(&vop_dev->reg_lock);
2140 if (likely(vop_dev->clk_on)) {
2141 win->area[0].y_addr = y_addr;
2142 win->area[0].uv_addr = uv_addr;
2143 vop_writel(vop_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
2144 vop_writel(vop_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
2145 if (win->area[0].fbdc_en == 1)
2146 vop_writel(vop_dev, AFBCD0_HDR_PTR,
2147 win->area[0].y_addr);
2149 spin_unlock(&vop_dev->reg_lock);
2154 static int win_2_3_display(struct vop_device *vop_dev,
2155 struct rk_lcdc_win *win)
2160 off = (win->id - 2) * 0x50;
2161 y_addr = win->area[0].smem_start + win->area[0].y_offset;
2162 DBG(2, "lcdc[%d]:win[%d]:", vop_dev->id, win->id);
2164 if (likely(vop_dev->clk_on)) {
2165 for (i = 0; i < win->area_num; i++) {
2166 DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2167 i, win->area[i].y_addr, win->area[i].y_offset);
2168 win->area[i].y_addr =
2169 win->area[i].smem_start + win->area[i].y_offset;
2171 spin_lock(&vop_dev->reg_lock);
2172 vop_writel(vop_dev, WIN2_MST0 + off, win->area[0].y_addr);
2173 vop_writel(vop_dev, WIN2_MST1 + off, win->area[1].y_addr);
2174 vop_writel(vop_dev, WIN2_MST2 + off, win->area[2].y_addr);
2175 vop_writel(vop_dev, WIN2_MST3 + off, win->area[3].y_addr);
2176 if (win->area[0].fbdc_en == 1)
2177 vop_writel(vop_dev, AFBCD0_HDR_PTR,
2178 win->area[0].y_addr);
2179 spin_unlock(&vop_dev->reg_lock);
2184 static int hwc_display(struct vop_device *vop_dev, struct rk_lcdc_win *win)
2188 y_addr = win->area[0].smem_start + win->area[0].y_offset;
2189 DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2190 vop_dev->id, __func__, y_addr);
2191 spin_lock(&vop_dev->reg_lock);
2192 if (likely(vop_dev->clk_on)) {
2193 win->area[0].y_addr = y_addr;
2194 vop_writel(vop_dev, HWC_MST, win->area[0].y_addr);
2196 spin_unlock(&vop_dev->reg_lock);
2201 static int vop_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2203 struct vop_device *vop_dev =
2204 container_of(dev_drv, struct vop_device, driver);
2205 struct rk_lcdc_win *win = NULL;
2206 struct rk_screen *screen = dev_drv->cur_screen;
2208 win = dev_drv->win[win_id];
2210 dev_err(dev_drv->dev, "screen is null!\n");
2213 if (unlikely(!vop_dev->clk_on)) {
2214 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
2218 win_0_1_display(vop_dev, win);
2219 } else if (win_id == 1) {
2220 win_0_1_display(vop_dev, win);
2221 } else if (win_id == 2) {
2222 win_2_3_display(vop_dev, win);
2223 } else if (win_id == 3) {
2224 win_2_3_display(vop_dev, win);
2225 } else if (win_id == 4) {
2226 hwc_display(vop_dev, win);
2228 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2235 static int vop_cal_scl_fac(struct rk_lcdc_win *win, struct rk_screen *screen)
2245 u32 yrgb_vscalednmult;
2246 u32 yrgb_xscl_factor;
2247 u32 yrgb_yscl_factor;
2248 u8 yrgb_vsd_bil_gt2 = 0;
2249 u8 yrgb_vsd_bil_gt4 = 0;
2255 u32 cbcr_vscalednmult;
2256 u32 cbcr_xscl_factor;
2257 u32 cbcr_yscl_factor;
2258 u8 cbcr_vsd_bil_gt2 = 0;
2259 u8 cbcr_vsd_bil_gt4 = 0;
2262 srcW = win->area[0].xact;
2263 if ((screen->mode.vmode & FB_VMODE_INTERLACED) &&
2264 (win->area[0].yact == 2 * win->area[0].ysize)) {
2265 srcH = win->area[0].yact / 2;
2266 yrgb_vsd_bil_gt2 = 1;
2267 cbcr_vsd_bil_gt2 = 1;
2269 srcH = win->area[0].yact;
2271 dstW = win->area[0].xsize;
2272 dstH = win->area[0].ysize;
2279 if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2280 pr_err("ERROR: yrgb scale exceed 8,");
2281 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2282 yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2284 if (yrgb_srcW < yrgb_dstW)
2285 win->yrgb_hor_scl_mode = SCALE_UP;
2286 else if (yrgb_srcW > yrgb_dstW)
2287 win->yrgb_hor_scl_mode = SCALE_DOWN;
2289 win->yrgb_hor_scl_mode = SCALE_NONE;
2291 if (yrgb_srcH < yrgb_dstH)
2292 win->yrgb_ver_scl_mode = SCALE_UP;
2293 else if (yrgb_srcH > yrgb_dstH)
2294 win->yrgb_ver_scl_mode = SCALE_DOWN;
2296 win->yrgb_ver_scl_mode = SCALE_NONE;
2299 switch (win->area[0].format) {
2304 cbcr_srcW = srcW / 2;
2315 cbcr_srcW = srcW / 2;
2317 cbcr_srcH = srcH / 2;
2338 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2339 (cbcr_dstH * 8 <= cbcr_srcH)) {
2340 pr_err("ERROR: cbcr scale exceed 8,");
2341 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2342 cbcr_srcH, cbcr_dstW, cbcr_dstH);
2346 if (cbcr_srcW < cbcr_dstW)
2347 win->cbr_hor_scl_mode = SCALE_UP;
2348 else if (cbcr_srcW > cbcr_dstW)
2349 win->cbr_hor_scl_mode = SCALE_DOWN;
2351 win->cbr_hor_scl_mode = SCALE_NONE;
2353 if (cbcr_srcH < cbcr_dstH)
2354 win->cbr_ver_scl_mode = SCALE_UP;
2355 else if (cbcr_srcH > cbcr_dstH)
2356 win->cbr_ver_scl_mode = SCALE_DOWN;
2358 win->cbr_ver_scl_mode = SCALE_NONE;
2360 /* line buffer mode */
2361 if ((win->area[0].format == YUV422) ||
2362 (win->area[0].format == YUV420) ||
2363 (win->area[0].format == YUYV422) ||
2364 (win->area[0].format == YUYV420) ||
2365 (win->area[0].format == UYVY422) ||
2366 (win->area[0].format == UYVY420) ||
2367 (win->area[0].format == YUV420_NV21) ||
2368 (win->area[0].format == YUV422_A) ||
2369 (win->area[0].format == YUV420_A)) {
2370 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2371 if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2373 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2375 else if (cbcr_dstW > 1280)
2376 win->win_lb_mode = LB_YUV_3840X5;
2378 win->win_lb_mode = LB_YUV_2560X8;
2379 } else { /* SCALE_UP or SCALE_NONE */
2380 if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2382 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2384 else if (cbcr_srcW > 1280)
2385 win->win_lb_mode = LB_YUV_3840X5;
2387 win->win_lb_mode = LB_YUV_2560X8;
2390 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2391 if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2393 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2394 else if (yrgb_dstW > 2560)
2395 win->win_lb_mode = LB_RGB_3840X2;
2396 else if (yrgb_dstW > 1920)
2397 win->win_lb_mode = LB_RGB_2560X4;
2398 else if (yrgb_dstW > 1280)
2399 win->win_lb_mode = LB_RGB_1920X5;
2401 win->win_lb_mode = LB_RGB_1280X8;
2402 } else { /* SCALE_UP or SCALE_NONE */
2403 if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2405 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2406 else if (yrgb_srcW > 2560)
2407 win->win_lb_mode = LB_RGB_3840X2;
2408 else if (yrgb_srcW > 1920)
2409 win->win_lb_mode = LB_RGB_2560X4;
2410 else if (yrgb_srcW > 1280)
2411 win->win_lb_mode = LB_RGB_1920X5;
2413 win->win_lb_mode = LB_RGB_1280X8;
2416 DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2418 /* vsd/vsu scale ALGORITHM */
2419 win->yrgb_hsd_mode = SCALE_DOWN_BIL; /*not to specify */
2420 win->cbr_hsd_mode = SCALE_DOWN_BIL; /*not to specify */
2421 win->yrgb_vsd_mode = SCALE_DOWN_BIL; /*not to specify */
2422 win->cbr_vsd_mode = SCALE_DOWN_BIL; /*not to specify */
2424 /* if (VOP_CHIP(vop_dev) == VOP_RK3399) { */
2425 if ((win->area[0].format == YUYV422) ||
2426 (win->area[0].format == YUYV420) ||
2427 (win->area[0].format == UYVY422) ||
2428 (win->area[0].format == UYVY420)) {
2430 vop_get_hard_ware_vskiplines(yrgb_srcH, yrgb_dstH);
2431 if (yrgb_vscalednmult == 4) {
2432 yrgb_vsd_bil_gt4 = 1;
2433 yrgb_vsd_bil_gt2 = 0;
2434 } else if (yrgb_vscalednmult == 2) {
2435 yrgb_vsd_bil_gt4 = 0;
2436 yrgb_vsd_bil_gt2 = 1;
2438 yrgb_vsd_bil_gt4 = 0;
2439 yrgb_vsd_bil_gt2 = 0;
2441 if ((win->area[0].format == YUYV420) ||
2442 (win->area[0].format == UYVY420)) {
2443 if ((yrgb_vsd_bil_gt4 == 1) || (yrgb_vsd_bil_gt2 == 1))
2444 win->yrgb_vsd_mode = SCALE_DOWN_AVG;
2448 vop_get_hard_ware_vskiplines(cbcr_srcH, cbcr_dstH);
2449 if (cbcr_vscalednmult == 4) {
2450 cbcr_vsd_bil_gt4 = 1;
2451 cbcr_vsd_bil_gt2 = 0;
2452 } else if (cbcr_vscalednmult == 2) {
2453 cbcr_vsd_bil_gt4 = 0;
2454 cbcr_vsd_bil_gt2 = 1;
2456 cbcr_vsd_bil_gt4 = 0;
2457 cbcr_vsd_bil_gt2 = 0;
2459 if ((win->area[0].format == YUYV420) ||
2460 (win->area[0].format == UYVY420)) {
2461 if ((cbcr_vsd_bil_gt4 == 1) || (cbcr_vsd_bil_gt2 == 1))
2462 win->cbr_vsd_mode = SCALE_DOWN_AVG;
2464 /* CBCR vsd_mode must same to YRGB for YUYV when gt2 or gt4 */
2465 if ((cbcr_vsd_bil_gt4 == 1) || (cbcr_vsd_bil_gt2 == 1)) {
2466 if (win->yrgb_vsd_mode != win->cbr_vsd_mode)
2467 win->cbr_vsd_mode = win->yrgb_vsd_mode;
2470 /* 3399 yuyv support*/
2471 if (win->ymirror == 1) {
2472 if (win->yrgb_vsd_mode == SCALE_DOWN_AVG)
2473 pr_info("y_mirror enable, y-vsd AVG mode unsupprot\n");
2474 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2476 if (screen->mode.vmode & FB_VMODE_INTERLACED) {
2477 if (win->yrgb_vsd_mode == SCALE_DOWN_AVG)
2478 pr_info("interlace mode, y-vsd AVG mode unsupprot\n");
2479 /* interlace mode must bill */
2480 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2481 win->cbr_vsd_mode = SCALE_DOWN_BIL;
2483 switch (win->win_lb_mode) {
2488 win->yrgb_vsu_mode = SCALE_UP_BIC;
2489 win->cbr_vsu_mode = SCALE_UP_BIC;
2492 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2493 pr_err("ERROR : not allow yrgb ver scale\n");
2494 if (win->cbr_ver_scl_mode != SCALE_NONE)
2495 pr_err("ERROR : not allow cbcr ver scale\n");
2498 win->yrgb_vsu_mode = SCALE_UP_BIL;
2499 win->cbr_vsu_mode = SCALE_UP_BIL;
2502 pr_info("%s:un supported win_lb_mode:%d\n",
2503 __func__, win->win_lb_mode);
2507 if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2508 (win->area[0].fbdc_en == 1)) {
2509 /* in this pattern,use bil mode,not support souble scd,
2510 * use avg mode, support double scd, but aclk should be
2513 if (yrgb_srcH >= 2 * yrgb_dstH) {
2514 pr_err("ERROR : fbdc mode,not support y scale down:");
2515 pr_err("srcH[%d] > 2 *dstH[%d]\n",
2516 yrgb_srcH, yrgb_dstH);
2519 DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2520 win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2521 win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2525 /* (1.1)YRGB HOR SCALE FACTOR */
2526 switch (win->yrgb_hor_scl_mode) {
2528 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2531 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2534 switch (win->yrgb_hsd_mode) {
2535 case SCALE_DOWN_BIL:
2537 GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2539 case SCALE_DOWN_AVG:
2541 GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2544 pr_info("%s:un supported yrgb_hsd_mode:%d\n", __func__,
2545 win->yrgb_hsd_mode);
2550 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2551 __func__, win->yrgb_hor_scl_mode);
2555 /* (1.2)YRGB VER SCALE FACTOR */
2556 switch (win->yrgb_ver_scl_mode) {
2558 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2561 switch (win->yrgb_vsu_mode) {
2564 GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2567 if (yrgb_srcH < 3) {
2568 pr_err("yrgb_srcH should be");
2569 pr_err(" greater than 3 !!!\n");
2571 yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2575 pr_info("%s:un support yrgb_vsu_mode:%d\n",
2576 __func__, win->yrgb_vsu_mode);
2581 switch (win->yrgb_vsd_mode) {
2582 case SCALE_DOWN_BIL:
2584 vop_get_hard_ware_vskiplines(yrgb_srcH, yrgb_dstH);
2586 GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2588 if (yrgb_yscl_factor >= 0x2000) {
2589 pr_err("yrgb_yscl_factor should less 0x2000");
2590 pr_err("yrgb_yscl_factor=%4x;\n",
2593 if (yrgb_vscalednmult == 4) {
2594 yrgb_vsd_bil_gt4 = 1;
2595 yrgb_vsd_bil_gt2 = 0;
2596 } else if (yrgb_vscalednmult == 2) {
2597 yrgb_vsd_bil_gt4 = 0;
2598 yrgb_vsd_bil_gt2 = 1;
2600 yrgb_vsd_bil_gt4 = 0;
2601 yrgb_vsd_bil_gt2 = 0;
2604 case SCALE_DOWN_AVG:
2605 yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2609 pr_info("%s:un support yrgb_vsd_mode:%d\n",
2610 __func__, win->yrgb_vsd_mode);
2612 } /*win->yrgb_vsd_mode */
2615 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2616 __func__, win->yrgb_ver_scl_mode);
2619 win->scale_yrgb_x = yrgb_xscl_factor;
2620 win->scale_yrgb_y = yrgb_yscl_factor;
2621 win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2622 win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2623 DBG(1, "yrgb:h_fac=%d, V_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2624 yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2626 /*(2.1)CBCR HOR SCALE FACTOR */
2627 switch (win->cbr_hor_scl_mode) {
2629 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2632 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2635 switch (win->cbr_hsd_mode) {
2636 case SCALE_DOWN_BIL:
2638 GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2640 case SCALE_DOWN_AVG:
2642 GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2645 pr_info("%s:un support cbr_hsd_mode:%d\n",
2646 __func__, win->cbr_hsd_mode);
2651 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2652 __func__, win->cbr_hor_scl_mode);
2654 } /*win->cbr_hor_scl_mode */
2656 /* (2.2)CBCR VER SCALE FACTOR */
2657 switch (win->cbr_ver_scl_mode) {
2659 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2662 switch (win->cbr_vsu_mode) {
2665 GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2668 if (cbcr_srcH < 3) {
2669 pr_err("cbcr_srcH should be ");
2670 pr_err("greater than 3 !!!\n");
2672 cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2676 pr_info("%s:un support cbr_vsu_mode:%d\n",
2677 __func__, win->cbr_vsu_mode);
2682 switch (win->cbr_vsd_mode) {
2683 case SCALE_DOWN_BIL:
2685 vop_get_hard_ware_vskiplines(cbcr_srcH, cbcr_dstH);
2687 GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2689 if (cbcr_yscl_factor >= 0x2000) {
2690 pr_err("cbcr_yscl_factor should be less ");
2691 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2695 if (cbcr_vscalednmult == 4) {
2696 cbcr_vsd_bil_gt4 = 1;
2697 cbcr_vsd_bil_gt2 = 0;
2698 } else if (cbcr_vscalednmult == 2) {
2699 cbcr_vsd_bil_gt4 = 0;
2700 cbcr_vsd_bil_gt2 = 1;
2702 cbcr_vsd_bil_gt4 = 0;
2703 cbcr_vsd_bil_gt2 = 0;
2706 case SCALE_DOWN_AVG:
2707 cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2711 pr_info("%s:un support cbr_vsd_mode:%d\n",
2712 __func__, win->cbr_vsd_mode);
2717 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2718 __func__, win->cbr_ver_scl_mode);
2721 win->scale_cbcr_x = cbcr_xscl_factor;
2722 win->scale_cbcr_y = cbcr_yscl_factor;
2723 win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2724 win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2726 DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2727 cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2731 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2732 struct rk_lcdc_win_area *area)
2736 if (screen->x_mirror && mirror_en)
2737 pr_err("not support both win and global mirror\n");
2739 if ((!mirror_en) && (!screen->x_mirror))
2740 pos = area->xpos + screen->mode.left_margin +
2741 screen->mode.hsync_len;
2743 pos = screen->mode.xres - area->xpos -
2744 area->xsize + screen->mode.left_margin +
2745 screen->mode.hsync_len;
2750 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2751 struct rk_lcdc_win_area *area)
2755 if (screen->y_mirror && mirror_en)
2756 pr_err("not support both win and global mirror\n");
2758 if ((!mirror_en) && (!screen->y_mirror))
2759 pos = area->ypos + screen->mode.upper_margin +
2760 screen->mode.vsync_len;
2762 pos = screen->mode.yres - area->ypos -
2763 area->ysize + screen->mode.upper_margin +
2764 screen->mode.vsync_len;
2769 static int win_0_1_set_par(struct vop_device *vop_dev,
2770 struct rk_screen *screen, struct rk_lcdc_win *win)
2772 u32 xact, yact, xvir, yvir, xpos, ypos;
2773 u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2774 char fmt[9] = "NULL";
2776 xpos = dsp_x_pos(win->xmirror, screen, &win->area[0]);
2777 ypos = dsp_y_pos(win->ymirror, screen, &win->area[0]);
2779 spin_lock(&vop_dev->reg_lock);
2780 if (likely(vop_dev->clk_on)) {
2781 vop_cal_scl_fac(win, screen);
2782 switch (win->area[0].format) {
2787 win->area[0].fbdc_fmt_cfg = AFBDC_FMT_RGB565;
2793 win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8;
2799 win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8;
2805 win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8;
2873 win->area[0].yuyv_fmt = 1;
2879 win->area[0].yuyv_fmt = 1;
2885 win->area[0].yuyv_fmt = 1;
2891 win->area[0].yuyv_fmt = 1;
2894 dev_err(vop_dev->dev, "%s:unsupport format[%d]!\n",
2895 __func__, win->area[0].format);
2898 win->area[0].fmt_cfg = fmt_cfg;
2899 win->area[0].swap_rb = swap_rb;
2900 win->area[0].swap_uv = swap_uv;
2901 win->area[0].dsp_stx = xpos;
2902 win->area[0].dsp_sty = ypos;
2903 xact = win->area[0].xact;
2904 yact = win->area[0].yact;
2905 xvir = win->area[0].xvir;
2906 yvir = win->area[0].yvir;
2908 if (win->area[0].fbdc_en)
2909 vop_init_fbdc_config(vop_dev, win->id);
2910 vop_win_0_1_reg_update(&vop_dev->driver, win->id);
2911 spin_unlock(&vop_dev->reg_lock);
2913 DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2914 vop_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2915 xact, yact, win->area[0].xsize);
2916 DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2917 win->area[0].ysize, xvir, yvir, xpos, ypos);
2922 static int win_2_3_set_par(struct vop_device *vop_dev,
2923 struct rk_screen *screen, struct rk_lcdc_win *win)
2926 u8 fmt_cfg, swap_rb;
2927 char fmt[9] = "NULL";
2929 if (VOP_CHIP(vop_dev) == VOP_RK322X) {
2930 pr_err("rk3228 not support win2/3 set par\n");
2934 pr_err("win[%d] not support y mirror\n", win->id);
2937 spin_lock(&vop_dev->reg_lock);
2938 if (likely(vop_dev->clk_on)) {
2939 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", vop_dev->id, win->id);
2940 for (i = 0; i < win->area_num; i++) {
2941 switch (win->area[i].format) {
2946 win->area[0].fbdc_fmt_cfg = 0x05;
2952 win->area[0].fbdc_fmt_cfg = 0x0c;
2958 win->area[0].fbdc_fmt_cfg = 0x3a;
2978 dev_err(vop_dev->driver.dev,
2979 "%s:un supported format!\n", __func__);
2980 spin_unlock(&vop_dev->reg_lock);
2983 win->area[i].fmt_cfg = fmt_cfg;
2984 win->area[i].swap_rb = swap_rb;
2985 win->area[i].dsp_stx = dsp_x_pos(win->xmirror, screen,
2987 win->area[i].dsp_sty = dsp_y_pos(win->ymirror, screen,
2989 if (((win->area[i].xact != win->area[i].xsize) ||
2990 (win->area[i].yact != win->area[i].ysize)) &&
2991 (screen->mode.vmode == FB_VMODE_NONINTERLACED)) {
2992 pr_err("win[%d]->area[%d],not support scale\n",
2994 pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
2995 win->area[i].xact, win->area[i].yact,
2996 win->area[i].xsize, win->area[i].ysize);
2997 win->area[i].xsize = win->area[i].xact;
2998 win->area[i].ysize = win->area[i].yact;
3000 DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
3001 get_format_string(win->area[i].format, fmt),
3002 win->area[i].xsize, win->area[i].ysize,
3003 win->area[i].xpos, win->area[i].ypos);
3006 if (win->area[0].fbdc_en)
3007 vop_init_fbdc_config(vop_dev, win->id);
3008 vop_win_2_3_reg_update(&vop_dev->driver, win->id);
3009 spin_unlock(&vop_dev->reg_lock);
3013 static int hwc_set_par(struct vop_device *vop_dev,
3014 struct rk_screen *screen, struct rk_lcdc_win *win)
3016 u32 xact, yact, xvir, yvir, xpos, ypos;
3017 u8 fmt_cfg = 0, swap_rb;
3018 char fmt[9] = "NULL";
3020 xpos = win->area[0].xpos + screen->mode.left_margin +
3021 screen->mode.hsync_len;
3022 ypos = win->area[0].ypos + screen->mode.upper_margin +
3023 screen->mode.vsync_len;
3025 spin_lock(&vop_dev->reg_lock);
3026 if (likely(vop_dev->clk_on)) {
3027 switch (win->area[0].format) {
3046 dev_err(vop_dev->dev, "%s:un supported format[%d]!\n",
3047 __func__, win->area[0].format);
3050 win->area[0].fmt_cfg = fmt_cfg;
3051 win->area[0].swap_rb = swap_rb;
3052 win->area[0].dsp_stx = xpos;
3053 win->area[0].dsp_sty = ypos;
3054 xact = win->area[0].xact;
3055 yact = win->area[0].yact;
3056 xvir = win->area[0].xvir;
3057 yvir = win->area[0].yvir;
3059 vop_hwc_reg_update(&vop_dev->driver, 4);
3060 spin_unlock(&vop_dev->reg_lock);
3062 DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
3063 vop_dev->id, __func__, get_format_string(win->area[0].format, fmt),
3064 xact, yact, win->area[0].xsize);
3065 DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
3066 win->area[0].ysize, xvir, yvir, xpos, ypos);
3070 static int vop_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
3072 struct vop_device *vop_dev =
3073 container_of(dev_drv, struct vop_device, driver);
3074 struct rk_lcdc_win *win = NULL;
3075 struct rk_screen *screen = dev_drv->cur_screen;
3077 if (unlikely(!vop_dev->clk_on)) {
3078 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
3081 win = dev_drv->win[win_id];
3085 win_0_1_set_par(vop_dev, screen, win);
3088 win_0_1_set_par(vop_dev, screen, win);
3091 win_2_3_set_par(vop_dev, screen, win);
3094 win_2_3_set_par(vop_dev, screen, win);
3097 hwc_set_par(vop_dev, screen, win);
3100 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
3106 static int vop_set_writeback(struct rk_lcdc_driver *dev_drv)
3108 struct vop_device *vop_dev =
3109 container_of(dev_drv, struct vop_device, driver);
3110 int output_color = dev_drv->output_color;
3111 struct rk_screen *screen = dev_drv->cur_screen;
3112 struct rk_fb_reg_wb_data *wb_data;
3113 int xact = screen->mode.xres;
3114 int yact = screen->mode.yres;
3119 if (unlikely(!vop_dev->clk_on)) {
3120 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
3123 wb_data = &dev_drv->wb_data;
3125 xsize = wb_data->xsize;
3126 ysize = wb_data->ysize;
3129 * RGB overlay mode support ARGB888, RGB888, RGB565, NV12,
3130 * but YUV overlay mode only support NV12, it's hard to judge RGB
3131 * or YUV overlay mode by userspace, so here force only support
3134 if (wb_data->data_format != YUV420 && output_color != COLOR_RGB) {
3135 pr_err("writeback only support NV12 when overlay is not RGB\n");
3139 if (ysize != yact && ysize != (yact / 2)) {
3140 pr_err("WriteBack only support yact=%d, ysize=%d\n",
3145 switch (wb_data->data_format) {
3159 pr_info("unsupport fmt: %d\n", wb_data->data_format);
3163 v = V_WB_EN(wb_data->state) | V_WB_FMT(fmt_cfg) | V_WB_RGB2YUV_MODE(1) |
3164 V_WB_XPSD_BIL_EN(xact != xsize) |
3165 V_WB_YTHROW_EN(ysize == (yact / 2)) |
3166 V_WB_YTHROW_MODE(0);
3168 v |= V_WB_RGB2YUV_EN((output_color == COLOR_RGB) &&
3169 (wb_data->data_format == YUV420));
3171 vop_msk_reg(vop_dev, WB_CTRL0, v);
3173 v = V_WB_WIDTH(xsize) | V_WB_XPSD_BIL_FACTOR((xact << 12) / xsize);
3175 vop_msk_reg(vop_dev, WB_CTRL1, v);
3177 vop_writel(vop_dev, WB_YRGB_MST, wb_data->smem_start);
3178 if (wb_data->data_format == YUV420)
3179 vop_writel(vop_dev, WB_CBR_MST, wb_data->smem_start);
3184 static int vop_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
3185 unsigned long arg, int win_id)
3187 struct vop_device *vop_dev =
3188 container_of(dev_drv, struct vop_device, driver);
3190 void __user *argp = (void __user *)arg;
3191 struct color_key_cfg clr_key_cfg;
3194 case RK_FBIOGET_PANEL_SIZE:
3195 panel_size[0] = vop_dev->screen->mode.xres;
3196 panel_size[1] = vop_dev->screen->mode.yres;
3197 if (copy_to_user(argp, panel_size, 8))
3200 case RK_FBIOPUT_COLOR_KEY_CFG:
3201 if (copy_from_user(&clr_key_cfg, argp, sizeof(clr_key_cfg)))
3203 vop_clr_key_cfg(dev_drv);
3204 vop_writel(vop_dev, WIN0_COLOR_KEY,
3205 clr_key_cfg.win0_color_key_cfg);
3206 vop_writel(vop_dev, WIN1_COLOR_KEY,
3207 clr_key_cfg.win1_color_key_cfg);
3216 static int vop_get_backlight_device(struct rk_lcdc_driver *dev_drv)
3218 struct vop_device *vop_dev = container_of(dev_drv,
3219 struct vop_device, driver);
3220 struct device_node *backlight;
3221 struct property *prop;
3222 u32 *brightness_levels;
3223 u32 length, max, last;
3225 if (vop_dev->backlight)
3227 backlight = of_parse_phandle(vop_dev->dev->of_node, "backlight", 0);
3229 vop_dev->backlight = of_find_backlight_by_node(backlight);
3230 if (!vop_dev->backlight)
3231 dev_info(vop_dev->dev, "No find backlight device\n");
3233 dev_info(vop_dev->dev, "No find backlight device node\n");
3235 prop = of_find_property(backlight, "brightness-levels", &length);
3238 max = length / sizeof(u32);
3240 brightness_levels = kmalloc(256, GFP_KERNEL);
3241 if (brightness_levels)
3244 if (!of_property_read_u32_array(backlight, "brightness-levels",
3245 brightness_levels, max)) {
3246 if (brightness_levels[0] > brightness_levels[last])
3247 dev_drv->cabc_pwm_pol = 1;/*negative*/
3249 dev_drv->cabc_pwm_pol = 0;/*positive*/
3251 dev_info(vop_dev->dev,
3252 "Can not read brightness-levels value\n");
3255 kfree(brightness_levels);
3260 static int vop_early_suspend(struct rk_lcdc_driver *dev_drv)
3262 struct vop_device *vop_dev =
3263 container_of(dev_drv, struct vop_device, driver);
3265 if (dev_drv->suspend_flag)
3268 dev_drv->suspend_flag = 1;
3269 /* ensure suspend_flag take effect on multi process */
3271 flush_kthread_worker(&dev_drv->update_regs_worker);
3273 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3274 dev_drv->trsm_ops->disable();
3276 if (likely(vop_dev->clk_on)) {
3277 spin_lock(&vop_dev->reg_lock);
3278 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLANK_EN(1));
3279 vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, INTR_MASK);
3280 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_OUT_ZERO(1));
3281 vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(1));
3282 vop_cfg_done(vop_dev);
3284 if (dev_drv->iommu_enabled && dev_drv->mmu_dev) {
3286 rockchip_iovmm_deactivate(dev_drv->dev);
3289 spin_unlock(&vop_dev->reg_lock);
3292 vop_clk_disable(vop_dev);
3293 rk_disp_pwr_disable(dev_drv);
3298 static int vop_early_resume(struct rk_lcdc_driver *dev_drv)
3300 struct vop_device *vop_dev =
3301 container_of(dev_drv, struct vop_device, driver);
3303 if (!dev_drv->suspend_flag)
3305 rk_disp_pwr_enable(dev_drv);
3307 vop_clk_enable(vop_dev);
3308 spin_lock(&vop_dev->reg_lock);
3309 memcpy(vop_dev->regs, vop_dev->regsbak, vop_dev->len);
3310 spin_unlock(&vop_dev->reg_lock);
3312 vop_set_lut(dev_drv, dev_drv->cur_screen->dsp_lut);
3313 vop_set_cabc(dev_drv, dev_drv->cur_screen->cabc_lut);
3314 spin_lock(&vop_dev->reg_lock);
3316 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_OUT_ZERO(0));
3317 vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(0));
3318 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLANK_EN(0));
3319 vop_cfg_done(vop_dev);
3320 spin_unlock(&vop_dev->reg_lock);
3322 if (dev_drv->iommu_enabled && dev_drv->mmu_dev) {
3323 /* win address maybe effect after next frame start,
3324 * but mmu maybe effect right now, so we delay 50ms
3327 rockchip_iovmm_activate(dev_drv->dev);
3330 dev_drv->suspend_flag = 0;
3332 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3333 dev_drv->trsm_ops->enable();
3338 static int vop_blank(struct rk_lcdc_driver *dev_drv, int win_id, int blank_mode)
3340 switch (blank_mode) {
3341 case FB_BLANK_UNBLANK:
3342 vop_early_resume(dev_drv);
3344 case FB_BLANK_NORMAL:
3345 vop_early_suspend(dev_drv);
3348 vop_early_suspend(dev_drv);
3352 dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
3357 static int vop_get_win_state(struct rk_lcdc_driver *dev_drv,
3358 int win_id, int area_id)
3360 struct vop_device *vop_dev =
3361 container_of(dev_drv, struct vop_device, driver);
3362 u32 area_status = 0, state = 0;
3366 area_status = vop_read_bit(vop_dev, WIN0_CTRL0, V_WIN0_EN(0));
3369 area_status = vop_read_bit(vop_dev, WIN1_CTRL0, V_WIN1_EN(0));
3373 area_status = vop_read_bit(vop_dev, WIN2_CTRL0,
3376 area_status = vop_read_bit(vop_dev, WIN2_CTRL0,
3379 area_status = vop_read_bit(vop_dev, WIN2_CTRL0,
3382 area_status = vop_read_bit(vop_dev, WIN2_CTRL0,
3387 area_status = vop_read_bit(vop_dev, WIN3_CTRL0,
3390 area_status = vop_read_bit(vop_dev, WIN3_CTRL0,
3393 area_status = vop_read_bit(vop_dev, WIN3_CTRL0,
3396 area_status = vop_read_bit(vop_dev, WIN3_CTRL0,
3400 area_status = vop_read_bit(vop_dev, HWC_CTRL0, V_HWC_EN(0));
3403 pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n",
3404 __func__, win_id, area_id);
3408 state = (area_status > 0) ? 1 : 0;
3412 static int vop_get_area_num(struct rk_lcdc_driver *dev_drv,
3413 unsigned int *area_support)
3415 struct vop_device *vop_dev =
3416 container_of(dev_drv, struct vop_device, driver);
3418 area_support[0] = 1;
3419 area_support[1] = 1;
3421 if (VOP_CHIP(vop_dev) == VOP_RK3399) {
3422 area_support[2] = 4;
3423 area_support[3] = 4;
3429 /*overlay will be do at regupdate*/
3430 static int vop_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, bool set)
3432 struct vop_device *vop_dev =
3433 container_of(dev_drv, struct vop_device, driver);
3434 struct rk_lcdc_win *win = NULL;
3437 int z_order_num = 0;
3438 int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3441 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
3442 win = dev_drv->win[i];
3443 if (win->state == 1)
3446 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
3447 win = dev_drv->win[i];
3448 if (win->state == 0)
3449 win->z_order = z_order_num++;
3450 switch (win->z_order) {
3452 layer0_sel = win->id;
3455 layer1_sel = win->id;
3458 layer2_sel = win->id;
3461 layer3_sel = win->id;
3468 layer0_sel = swap % 10;
3469 layer1_sel = swap / 10 % 10;
3470 layer2_sel = swap / 100 % 10;
3471 layer3_sel = swap / 1000;
3474 spin_lock(&vop_dev->reg_lock);
3475 if (vop_dev->clk_on) {
3477 val = V_DSP_LAYER0_SEL(layer0_sel) |
3478 V_DSP_LAYER1_SEL(layer1_sel) |
3479 V_DSP_LAYER2_SEL(layer2_sel) |
3480 V_DSP_LAYER3_SEL(layer3_sel);
3481 vop_msk_reg(vop_dev, DSP_CTRL1, val);
3483 layer0_sel = vop_read_bit(vop_dev, DSP_CTRL1,
3484 V_DSP_LAYER0_SEL(0));
3485 layer1_sel = vop_read_bit(vop_dev, DSP_CTRL1,
3486 V_DSP_LAYER1_SEL(0));
3487 layer2_sel = vop_read_bit(vop_dev, DSP_CTRL1,
3488 V_DSP_LAYER2_SEL(0));
3489 layer3_sel = vop_read_bit(vop_dev, DSP_CTRL1,
3490 V_DSP_LAYER3_SEL(0));
3491 ovl = layer3_sel * 1000 + layer2_sel * 100 +
3492 layer1_sel * 10 + layer0_sel;
3497 spin_unlock(&vop_dev->reg_lock);
3502 static char *vop_format_to_string(int format, char *fmt)
3509 strcpy(fmt, "ARGB888");
3512 strcpy(fmt, "RGB888");
3515 strcpy(fmt, "RGB565");
3518 strcpy(fmt, "YCbCr420");
3521 strcpy(fmt, "YCbCr422");
3524 strcpy(fmt, "YCbCr444");
3527 strcpy(fmt, "invalid\n");
3533 static ssize_t vop_get_disp_info(struct rk_lcdc_driver *dev_drv,
3534 char *buf, int win_id)
3536 struct vop_device *vop_dev =
3537 container_of(dev_drv, struct vop_device, driver);
3538 struct rk_screen *screen = dev_drv->cur_screen;
3539 u16 hsync_len = screen->mode.hsync_len;
3540 u16 left_margin = screen->mode.left_margin;
3541 u16 vsync_len = screen->mode.vsync_len;
3542 u16 upper_margin = screen->mode.upper_margin;
3543 u32 h_pw_bp = hsync_len + left_margin;
3544 u32 v_pw_bp = vsync_len + upper_margin;
3546 char format_w0[9] = "NULL";
3547 char format_w1[9] = "NULL";
3549 u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3550 u32 y_factor, uv_factor;
3551 u8 layer0_sel, layer1_sel;
3552 u8 w0_state, w1_state;
3554 u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3555 u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3556 u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3557 u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3558 u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3559 u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3564 dclk_freq = screen->mode.pixclock;
3565 /*vop_reg_dump(dev_drv); */
3567 spin_lock(&vop_dev->reg_lock);
3568 if (vop_dev->clk_on) {
3569 zorder = vop_readl(vop_dev, DSP_CTRL1);
3570 layer0_sel = (zorder & MASK(DSP_LAYER0_SEL)) >> 8;
3571 layer1_sel = (zorder & MASK(DSP_LAYER1_SEL)) >> 10;
3573 win_ctrl = vop_readl(vop_dev, WIN0_CTRL0);
3574 w0_state = win_ctrl & MASK(WIN0_EN);
3575 fmt_id = (win_ctrl & MASK(WIN0_DATA_FMT)) >> 1;
3576 vop_format_to_string(fmt_id, format_w0);
3577 vir_info = vop_readl(vop_dev, WIN0_VIR);
3578 act_info = vop_readl(vop_dev, WIN0_ACT_INFO);
3579 dsp_info = vop_readl(vop_dev, WIN0_DSP_INFO);
3580 dsp_st = vop_readl(vop_dev, WIN0_DSP_ST);
3581 y_factor = vop_readl(vop_dev, WIN0_SCL_FACTOR_YRGB);
3582 uv_factor = vop_readl(vop_dev, WIN0_SCL_FACTOR_CBR);
3583 w0_vir_y = vir_info & MASK(WIN0_VIR_STRIDE);
3584 w0_vir_uv = (vir_info & MASK(WIN0_VIR_STRIDE_UV)) >> 16;
3585 w0_act_x = (act_info & MASK(WIN0_ACT_WIDTH)) + 1;
3586 w0_act_y = ((act_info & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1;
3587 w0_dsp_x = (dsp_info & MASK(WIN0_DSP_WIDTH)) + 1;
3588 w0_dsp_y = ((dsp_info & MASK(WIN0_DSP_HEIGHT)) >> 16) + 1;
3590 w0_st_x = dsp_st & MASK(WIN0_DSP_XST);
3591 w0_st_y = (dsp_st & MASK(WIN0_DSP_YST)) >> 16;
3593 w0_y_h_fac = y_factor & MASK(WIN0_HS_FACTOR_YRGB);
3594 w0_y_v_fac = (y_factor & MASK(WIN0_VS_FACTOR_YRGB)) >> 16;
3595 w0_uv_h_fac = uv_factor & MASK(WIN0_HS_FACTOR_CBR);
3596 w0_uv_v_fac = (uv_factor & MASK(WIN0_VS_FACTOR_CBR)) >> 16;
3599 win_ctrl = vop_readl(vop_dev, WIN1_CTRL0);
3600 w1_state = win_ctrl & MASK(WIN1_EN);
3601 fmt_id = (win_ctrl & MASK(WIN1_DATA_FMT)) >> 1;
3602 vop_format_to_string(fmt_id, format_w1);
3603 vir_info = vop_readl(vop_dev, WIN1_VIR);
3604 act_info = vop_readl(vop_dev, WIN1_ACT_INFO);
3605 dsp_info = vop_readl(vop_dev, WIN1_DSP_INFO);
3606 dsp_st = vop_readl(vop_dev, WIN1_DSP_ST);
3607 y_factor = vop_readl(vop_dev, WIN1_SCL_FACTOR_YRGB);
3608 uv_factor = vop_readl(vop_dev, WIN1_SCL_FACTOR_CBR);
3609 w1_vir_y = vir_info & MASK(WIN1_VIR_STRIDE);
3610 w1_vir_uv = (vir_info & MASK(WIN1_VIR_STRIDE_UV)) >> 16;
3611 w1_act_x = (act_info & MASK(WIN1_ACT_WIDTH)) + 1;
3612 w1_act_y = ((act_info & MASK(WIN1_ACT_HEIGHT)) >> 16) + 1;
3613 w1_dsp_x = (dsp_info & MASK(WIN1_DSP_WIDTH)) + 1;
3614 w1_dsp_y = ((dsp_info & MASK(WIN1_DSP_HEIGHT)) >> 16) + 1;
3616 w1_st_x = dsp_st & MASK(WIN1_DSP_XST);
3617 w1_st_y = (dsp_st & MASK(WIN1_DSP_YST)) >> 16;
3619 w1_y_h_fac = y_factor & MASK(WIN1_HS_FACTOR_YRGB);
3620 w1_y_v_fac = (y_factor & MASK(WIN1_VS_FACTOR_YRGB)) >> 16;
3621 w1_uv_h_fac = uv_factor & MASK(WIN1_HS_FACTOR_CBR);
3622 w1_uv_v_fac = (uv_factor & MASK(WIN1_VS_FACTOR_CBR)) >> 16;
3624 spin_unlock(&vop_dev->reg_lock);
3627 spin_unlock(&vop_dev->reg_lock);
3628 size += snprintf(dsp_buf, 80,
3629 "z-order:\n win[%d]\n win[%d]\n",
3630 layer1_sel, layer0_sel);
3631 strcat(buf, dsp_buf);
3632 memset(dsp_buf, 0, sizeof(dsp_buf));
3634 size += snprintf(dsp_buf, 80,
3635 "win0:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,",
3636 w0_state, format_w0, w0_vir_y, w0_vir_uv);
3637 strcat(buf, dsp_buf);
3638 memset(dsp_buf, 0, sizeof(dsp_buf));
3640 size += snprintf(dsp_buf, 80,
3641 " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n",
3642 w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3643 strcat(buf, dsp_buf);
3644 memset(dsp_buf, 0, sizeof(dsp_buf));
3646 size += snprintf(dsp_buf, 80,
3647 " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3648 w0_st_x - h_pw_bp, w0_st_y - v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3649 strcat(buf, dsp_buf);
3650 memset(dsp_buf, 0, sizeof(dsp_buf));
3652 size += snprintf(dsp_buf, 80,
3653 "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n",
3654 w0_uv_h_fac, w0_uv_v_fac, vop_readl(vop_dev, WIN0_YRGB_MST),
3655 vop_readl(vop_dev, WIN0_CBR_MST));
3656 strcat(buf, dsp_buf);
3657 memset(dsp_buf, 0, sizeof(dsp_buf));
3660 size += snprintf(dsp_buf, 80,
3661 "win1:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,",
3662 w1_state, format_w1, w1_vir_y, w1_vir_uv);
3663 strcat(buf, dsp_buf);
3664 memset(dsp_buf, 0, sizeof(dsp_buf));
3666 size += snprintf(dsp_buf, 80,
3667 " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n",
3668 w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3669 strcat(buf, dsp_buf);
3670 memset(dsp_buf, 0, sizeof(dsp_buf));
3672 size += snprintf(dsp_buf, 80,
3673 " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3674 w1_st_x - h_pw_bp, w1_st_y - v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3675 strcat(buf, dsp_buf);
3676 memset(dsp_buf, 0, sizeof(dsp_buf));
3678 size += snprintf(dsp_buf, 80,
3679 "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n",
3680 w1_uv_h_fac, w1_uv_v_fac, vop_readl(vop_dev, WIN1_YRGB_MST),
3681 vop_readl(vop_dev, WIN1_CBR_MST));
3682 strcat(buf, dsp_buf);
3683 memset(dsp_buf, 0, sizeof(dsp_buf));
3688 static int vop_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, bool set)
3690 struct vop_device *vop_dev =
3691 container_of(dev_drv, struct vop_device, driver);
3692 struct rk_screen *screen = dev_drv->cur_screen;
3697 u32 x_total, y_total;
3701 dev_info(dev_drv->dev, "unsupport set fps=0\n");
3704 ft = div_u64(1000000000000llu, fps);
3706 screen->mode.upper_margin + screen->mode.lower_margin +
3707 screen->mode.yres + screen->mode.vsync_len;
3709 screen->mode.left_margin + screen->mode.right_margin +
3710 screen->mode.xres + screen->mode.hsync_len;
3711 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3712 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3713 ret = clk_set_rate(vop_dev->dclk, dotclk);
3716 pixclock = div_u64(1000000000000llu, clk_get_rate(vop_dev->dclk));
3717 vop_dev->pixclock = pixclock;
3718 dev_drv->pixclock = vop_dev->pixclock;
3719 fps = rk_fb_calc_fps(screen, pixclock);
3720 screen->ft = 1000 / fps; /*one frame time in ms */
3723 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3724 clk_get_rate(vop_dev->dclk), fps);
3729 static int vop_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3731 mutex_lock(&dev_drv->fb_win_id_mutex);
3732 if (order == FB_DEFAULT_ORDER)
3733 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
3734 dev_drv->fb4_win_id = order / 10000;
3735 dev_drv->fb3_win_id = (order / 1000) % 10;
3736 dev_drv->fb2_win_id = (order / 100) % 10;
3737 dev_drv->fb1_win_id = (order / 10) % 10;
3738 dev_drv->fb0_win_id = order % 10;
3739 mutex_unlock(&dev_drv->fb_win_id_mutex);
3744 static int vop_get_win_id(struct rk_lcdc_driver *dev_drv, const char *id)
3748 mutex_lock(&dev_drv->fb_win_id_mutex);
3749 if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
3750 win_id = dev_drv->fb0_win_id;
3751 else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
3752 win_id = dev_drv->fb1_win_id;
3753 else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
3754 win_id = dev_drv->fb2_win_id;
3755 else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
3756 win_id = dev_drv->fb3_win_id;
3757 else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
3758 win_id = dev_drv->fb4_win_id;
3759 mutex_unlock(&dev_drv->fb_win_id_mutex);
3764 static int vop_config_done(struct rk_lcdc_driver *dev_drv)
3766 struct vop_device *vop_dev =
3767 container_of(dev_drv, struct vop_device, driver);
3770 struct rk_lcdc_win *win = NULL;
3772 spin_lock(&vop_dev->reg_lock);
3773 vop_post_cfg(dev_drv);
3774 vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(vop_dev->standby));
3775 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
3776 win = dev_drv->win[i];
3777 fbdc_en |= win->area[0].fbdc_en;
3778 if ((win->state == 0) && (win->last_state == 1)) {
3782 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
3786 vop_msk_reg(vop_dev, WIN1_CTRL0, val);
3789 val = V_WIN2_EN(0) | V_WIN2_MST0_EN(0) |
3791 V_WIN2_MST2_EN(0) | V_WIN2_MST3_EN(0);
3792 vop_msk_reg(vop_dev, WIN2_CTRL0, val);
3795 val = V_WIN3_EN(0) | V_WIN3_MST0_EN(0) |
3797 V_WIN3_MST2_EN(0) | V_WIN3_MST3_EN(0);
3798 vop_msk_reg(vop_dev, WIN3_CTRL0, val);
3802 vop_msk_reg(vop_dev, HWC_CTRL0, val);
3808 win->last_state = win->state;
3810 if (VOP_CHIP(vop_dev) == VOP_RK3399) {
3811 val = V_VOP_FBDC_EN(fbdc_en);
3812 vop_msk_reg(vop_dev, AFBCD0_CTRL, val);
3814 vop_cfg_done(vop_dev);
3815 spin_unlock(&vop_dev->reg_lock);
3819 static int vop_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3821 struct vop_device *vop_dev =
3822 container_of(dev_drv, struct vop_device, driver);
3823 spin_lock(&vop_dev->reg_lock);
3824 vop_msk_reg(vop_dev, SYS_CTRL, V_DIRECT_PATH_EN(open));
3825 vop_cfg_done(vop_dev);
3826 spin_unlock(&vop_dev->reg_lock);
3830 static int vop_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3832 struct vop_device *vop_dev = container_of(dev_drv,
3833 struct vop_device, driver);
3834 spin_lock(&vop_dev->reg_lock);
3835 vop_msk_reg(vop_dev, SYS_CTRL, V_DIRECT_PATH_LAYER_SEL(win_id));
3836 vop_cfg_done(vop_dev);
3837 spin_unlock(&vop_dev->reg_lock);
3841 static int vop_dpi_status(struct rk_lcdc_driver *dev_drv)
3843 struct vop_device *vop_dev =
3844 container_of(dev_drv, struct vop_device, driver);
3847 spin_lock(&vop_dev->reg_lock);
3848 ovl = vop_read_bit(vop_dev, SYS_CTRL, V_DIRECT_PATH_EN(0));
3849 spin_unlock(&vop_dev->reg_lock);
3853 static int vop_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv, int enable)
3855 struct vop_device *vop_dev =
3856 container_of(dev_drv, struct vop_device, driver);
3858 enable_irq(vop_dev->irq);
3860 disable_irq(vop_dev->irq);
3864 int vop_poll_vblank(struct rk_lcdc_driver *dev_drv)
3866 struct vop_device *vop_dev =
3867 container_of(dev_drv, struct vop_device, driver);
3871 if (vop_dev->clk_on && (!dev_drv->suspend_flag)) {
3872 int_reg = vop_readl(vop_dev, INTR_STATUS0);
3873 if (int_reg & INTR_LINE_FLAG0) {
3874 vop_dev->driver.frame_time.last_framedone_t =
3875 vop_dev->driver.frame_time.framedone_t;
3876 vop_dev->driver.frame_time.framedone_t = cpu_clock(0);
3877 vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_LINE_FLAG0,
3879 ret = RK_LF_STATUS_FC;
3881 ret = RK_LF_STATUS_FR;
3884 ret = RK_LF_STATUS_NC;
3890 static int vop_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3891 unsigned int dsp_addr[][4])
3893 struct vop_device *vop_dev =
3894 container_of(dev_drv, struct vop_device, driver);
3895 spin_lock(&vop_dev->reg_lock);
3896 if (vop_dev->clk_on) {
3897 dsp_addr[0][0] = vop_readl(vop_dev, WIN0_YRGB_MST);
3898 dsp_addr[1][0] = vop_readl(vop_dev, WIN1_YRGB_MST);
3899 dsp_addr[2][0] = vop_readl(vop_dev, WIN2_MST0);
3900 dsp_addr[2][1] = vop_readl(vop_dev, WIN2_MST1);
3901 dsp_addr[2][2] = vop_readl(vop_dev, WIN2_MST2);
3902 dsp_addr[2][3] = vop_readl(vop_dev, WIN2_MST3);
3903 dsp_addr[3][0] = vop_readl(vop_dev, WIN3_MST0);
3904 dsp_addr[3][1] = vop_readl(vop_dev, WIN3_MST1);
3905 dsp_addr[3][2] = vop_readl(vop_dev, WIN3_MST2);
3906 dsp_addr[3][3] = vop_readl(vop_dev, WIN3_MST3);
3907 dsp_addr[4][0] = vop_readl(vop_dev, HWC_MST);
3909 spin_unlock(&vop_dev->reg_lock);
3914 int vop_update_pwm(int bl_pwm_period, int bl_pwm_duty)
3918 * pwm_period_hpr = bl_pwm_period;
3919 * pwm_duty_lpr = bl_pwm_duty;
3920 * pr_info("bl_pwm_period_hpr = 0x%x, bl_pwm_duty_lpr = 0x%x\n",
3921 * bl_pwm_period, bl_pwm_duty);
3929 * sin_hue = sin(a)*256 +0x100;
3930 * cos_hue = cos(a)*256;
3932 * sin_hue = sin(a)*256;
3933 * cos_hue = cos(a)*256;
3935 static int vop_get_bcsh_hue(struct rk_lcdc_driver *dev_drv, bcsh_hue_mode mode)
3937 struct vop_device *vop_dev =
3938 container_of(dev_drv, struct vop_device, driver);
3941 spin_lock(&vop_dev->reg_lock);
3942 if (vop_dev->clk_on) {
3943 val = vop_readl(vop_dev, BCSH_H);
3946 val &= MASK(SIN_HUE);
3949 val &= MASK(COS_HUE);
3956 spin_unlock(&vop_dev->reg_lock);
3961 static int vop_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode,
3962 int calc, int up, int down, int global)
3964 struct vop_device *vop_dev =
3965 container_of(dev_drv, struct vop_device, driver);
3966 struct rk_screen *screen = dev_drv->cur_screen;
3967 u32 total_pixel, calc_pixel, stage_up, stage_down;
3968 u32 pixel_num, global_dn;
3970 if (!vop_dev->cabc_lut_addr_base) {
3971 pr_err("vop chip[%d] not supoort cabc\n", VOP_CHIP(vop_dev));
3975 if (!screen->cabc_lut) {
3976 pr_err("screen cabc lut not config, so not open cabc\n");
3980 dev_drv->cabc_mode = mode;
3981 if (!dev_drv->cabc_mode) {
3982 spin_lock(&vop_dev->reg_lock);
3983 if (vop_dev->clk_on) {
3984 vop_msk_reg(vop_dev, CABC_CTRL0,
3985 V_CABC_EN(0) | V_CABC_HANDLE_EN(0));
3986 vop_cfg_done(vop_dev);
3988 pr_info("mode = 0, close cabc\n");
3989 spin_unlock(&vop_dev->reg_lock);
3993 total_pixel = screen->mode.xres * screen->mode.yres;
3994 pixel_num = 1000 - calc;
3995 calc_pixel = (total_pixel * pixel_num) / 1000;
3999 pr_info("enable cabc:mode=%d, calc=%d, up=%d, down=%d, global=%d\n",
4000 mode, calc, stage_up, stage_down, global_dn);
4002 spin_lock(&vop_dev->reg_lock);
4003 if (vop_dev->clk_on) {
4006 val = V_CABC_EN(1) | V_CABC_HANDLE_EN(1) |
4007 V_PWM_CONFIG_MODE(STAGE_BY_STAGE) |
4008 V_CABC_CALC_PIXEL_NUM(calc_pixel);
4009 vop_msk_reg(vop_dev, CABC_CTRL0, val);
4011 val = V_CABC_LUT_EN(1) | V_CABC_TOTAL_NUM(total_pixel);
4012 vop_msk_reg(vop_dev, CABC_CTRL1, val);
4014 val = V_CABC_STAGE_DOWN(stage_down) |
4015 V_CABC_STAGE_UP(stage_up) |
4016 V_CABC_STAGE_UP_MODE(0) | V_MAX_SCALE_CFG_VALUE(1) |
4017 V_MAX_SCALE_CFG_ENABLE(0);
4018 vop_msk_reg(vop_dev, CABC_CTRL2, val);
4020 val = V_CABC_GLOBAL_DN(global_dn) |
4021 V_CABC_GLOBAL_DN_LIMIT_EN(1);
4022 vop_msk_reg(vop_dev, CABC_CTRL3, val);
4023 vop_cfg_done(vop_dev);
4025 spin_unlock(&vop_dev->reg_lock);
4030 static int vop_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
4031 int sin_hue, int cos_hue)
4033 struct vop_device *vop_dev =
4034 container_of(dev_drv, struct vop_device, driver);
4037 spin_lock(&vop_dev->reg_lock);
4038 if (vop_dev->clk_on) {
4039 val = V_SIN_HUE(sin_hue) | V_COS_HUE(cos_hue);
4040 vop_msk_reg(vop_dev, BCSH_H, val);
4041 vop_cfg_done(vop_dev);
4043 spin_unlock(&vop_dev->reg_lock);
4048 static int vop_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4049 bcsh_bcs_mode mode, int value)
4051 struct vop_device *vop_dev =
4052 container_of(dev_drv, struct vop_device, driver);
4055 spin_lock(&vop_dev->reg_lock);
4056 if (vop_dev->clk_on) {
4059 /*from 0 to 255,typical is 128 */
4062 else if (value >= 0x80)
4063 value = value - 0x80;
4064 val = V_BRIGHTNESS(value);
4067 /*from 0 to 510,typical is 256 */
4068 val = V_CONTRAST(value);
4071 /*from 0 to 1015,typical is 256 */
4072 val = V_SAT_CON(value);
4077 vop_msk_reg(vop_dev, BCSH_BCS, val);
4078 vop_cfg_done(vop_dev);
4080 spin_unlock(&vop_dev->reg_lock);
4085 static int vop_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv, bcsh_bcs_mode mode)
4087 struct vop_device *vop_dev =
4088 container_of(dev_drv, struct vop_device, driver);
4091 spin_lock(&vop_dev->reg_lock);
4092 if (vop_dev->clk_on) {
4093 val = vop_readl(vop_dev, BCSH_BCS);
4096 val &= MASK(BRIGHTNESS);
4103 val &= MASK(CONTRAST);
4107 val &= MASK(SAT_CON);
4114 spin_unlock(&vop_dev->reg_lock);
4118 static int vop_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
4120 struct vop_device *vop_dev =
4121 container_of(dev_drv, struct vop_device, driver);
4123 spin_lock(&vop_dev->reg_lock);
4124 if (vop_dev->clk_on) {
4126 vop_writel(vop_dev, BCSH_COLOR_BAR, 0x1);
4127 vop_writel(vop_dev, BCSH_BCS, 0xd0010000);
4128 vop_writel(vop_dev, BCSH_H, 0x01000000);
4129 dev_drv->bcsh.enable = 1;
4131 vop_msk_reg(vop_dev, BCSH_COLOR_BAR, V_BCSH_EN(0));
4132 dev_drv->bcsh.enable = 0;
4134 vop_bcsh_path_sel(dev_drv);
4135 vop_cfg_done(vop_dev);
4137 spin_unlock(&vop_dev->reg_lock);
4142 static int vop_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4144 if (!enable || !dev_drv->bcsh.enable) {
4145 vop_open_bcsh(dev_drv, false);
4149 if (dev_drv->bcsh.brightness <= 255 ||
4150 dev_drv->bcsh.contrast <= 510 ||
4151 dev_drv->bcsh.sat_con <= 1015 ||
4152 (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4153 vop_open_bcsh(dev_drv, true);
4154 if (dev_drv->bcsh.brightness <= 255)
4155 vop_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4156 dev_drv->bcsh.brightness);
4157 if (dev_drv->bcsh.contrast <= 510)
4158 vop_set_bcsh_bcs(dev_drv, CONTRAST,
4159 dev_drv->bcsh.contrast);
4160 if (dev_drv->bcsh.sat_con <= 1015)
4161 vop_set_bcsh_bcs(dev_drv, SAT_CON,
4162 dev_drv->bcsh.sat_con);
4163 if (dev_drv->bcsh.sin_hue <= 511 &&
4164 dev_drv->bcsh.cos_hue <= 511)
4165 vop_set_bcsh_hue(dev_drv, dev_drv->bcsh.sin_hue,
4166 dev_drv->bcsh.cos_hue);
4172 static int __maybe_unused
4173 vop_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4175 struct vop_device *vop_dev =
4176 container_of(dev_drv, struct vop_device, driver);
4179 spin_lock(&vop_dev->reg_lock);
4180 if (likely(vop_dev->clk_on)) {
4181 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLACK_EN(1));
4182 vop_cfg_done(vop_dev);
4184 spin_unlock(&vop_dev->reg_lock);
4186 spin_lock(&vop_dev->reg_lock);
4187 if (likely(vop_dev->clk_on)) {
4188 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLACK_EN(0));
4190 vop_cfg_done(vop_dev);
4192 spin_unlock(&vop_dev->reg_lock);
4198 static int vop_backlight_close(struct rk_lcdc_driver *dev_drv, int enable)
4200 struct vop_device *vop_dev =
4201 container_of(dev_drv, struct vop_device, driver);
4203 if (unlikely(!vop_dev->clk_on)) {
4204 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
4207 vop_get_backlight_device(dev_drv);
4210 /* close the backlight */
4211 if (vop_dev->backlight) {
4212 vop_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4213 backlight_update_status(vop_dev->backlight);
4215 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4216 dev_drv->trsm_ops->disable();
4218 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4219 dev_drv->trsm_ops->enable();
4221 /* open the backlight */
4222 if (vop_dev->backlight) {
4223 vop_dev->backlight->props.power = FB_BLANK_UNBLANK;
4224 backlight_update_status(vop_dev->backlight);
4231 static int vop_set_overscan(struct rk_lcdc_driver *dev_drv,
4232 struct overscan *overscan)
4234 struct vop_device *vop_dev =
4235 container_of(dev_drv, struct vop_device, driver);
4237 if (unlikely(!vop_dev->clk_on)) {
4238 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
4241 /*vop_post_cfg(dev_drv);*/
4246 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4248 .win_direct_en = vop_win_direct_en,
4249 .load_screen = vop_load_screen,
4250 .get_dspbuf_info = vop_get_dspbuf_info,
4251 .post_dspbuf = vop_post_dspbuf,
4252 .set_par = vop_set_par,
4253 .pan_display = vop_pan_display,
4254 .set_wb = vop_set_writeback,
4255 .direct_set_addr = vop_direct_set_win_addr,
4256 /*.lcdc_reg_update = vop_reg_update,*/
4259 .suspend = vop_early_suspend,
4260 .resume = vop_early_resume,
4261 .get_win_state = vop_get_win_state,
4262 .area_support_num = vop_get_area_num,
4263 .ovl_mgr = vop_ovl_mgr,
4264 .get_disp_info = vop_get_disp_info,
4265 .fps_mgr = vop_fps_mgr,
4266 .fb_get_win_id = vop_get_win_id,
4267 .fb_win_remap = vop_fb_win_remap,
4268 .poll_vblank = vop_poll_vblank,
4269 .dpi_open = vop_dpi_open,
4270 .dpi_win_sel = vop_dpi_win_sel,
4271 .dpi_status = vop_dpi_status,
4272 .get_dsp_addr = vop_get_dsp_addr,
4273 .set_dsp_lut = vop_set_lut,
4274 .set_cabc_lut = vop_set_cabc,
4275 .set_dsp_cabc = vop_set_dsp_cabc,
4276 .set_dsp_bcsh_hue = vop_set_bcsh_hue,
4277 .set_dsp_bcsh_bcs = vop_set_bcsh_bcs,
4278 .get_dsp_bcsh_hue = vop_get_bcsh_hue,
4279 .get_dsp_bcsh_bcs = vop_get_bcsh_bcs,
4280 .open_bcsh = vop_open_bcsh,
4281 .dump_reg = vop_reg_dump,
4282 .cfg_done = vop_config_done,
4283 .set_irq_to_cpu = vop_set_irq_to_cpu,
4284 /*.dsp_black = vop_dsp_black,*/
4285 .backlight_close = vop_backlight_close,
4286 .mmu_en = vop_mmu_en,
4287 .set_overscan = vop_set_overscan,
4290 static irqreturn_t vop_isr(int irq, void *dev_id)
4292 struct vop_device *vop_dev = (struct vop_device *)dev_id;
4293 ktime_t timestamp = ktime_get();
4295 unsigned long flags;
4297 spin_lock_irqsave(&vop_dev->irq_lock, flags);
4299 intr_status = vop_readl(vop_dev, INTR_STATUS0);
4300 vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, intr_status);
4302 spin_unlock_irqrestore(&vop_dev->irq_lock, flags);
4303 /* This is expected for vop iommu irqs, since the irq is shared */
4307 if (intr_status & INTR_FS) {
4308 timestamp = ktime_get();
4309 if (vop_dev->wb_on) {
4312 spin_lock_irqsave(&vop_dev->irq_lock, flags);
4313 wb_status = vop_read_bit(vop_dev, WB_CTRL0, V_WB_EN(0));
4315 vop_set_bit(vop_dev, WB_CTRL0, V_WB_EN(0));
4317 vop_cfg_done(vop_dev);
4318 vop_dev->driver.wb_data.state = 0;
4319 spin_unlock_irqrestore(&vop_dev->irq_lock, flags);
4321 vop_dev->driver.vsync_info.timestamp = timestamp;
4322 wake_up_interruptible_all(&vop_dev->driver.vsync_info.wait);
4323 intr_status &= ~INTR_FS;
4326 if (intr_status & INTR_LINE_FLAG0)
4327 intr_status &= ~INTR_LINE_FLAG0;
4329 if (intr_status & INTR_LINE_FLAG1)
4330 intr_status &= ~INTR_LINE_FLAG1;
4332 if (intr_status & INTR_FS_NEW)
4333 intr_status &= ~INTR_FS_NEW;
4335 if (intr_status & INTR_BUS_ERROR) {
4336 intr_status &= ~INTR_BUS_ERROR;
4337 dev_warn_ratelimited(vop_dev->dev, "bus error!");
4340 if (intr_status & INTR_WIN0_EMPTY) {
4341 intr_status &= ~INTR_WIN0_EMPTY;
4342 dev_warn_ratelimited(vop_dev->dev, "intr win0 empty!");
4345 if (intr_status & INTR_WIN1_EMPTY) {
4346 intr_status &= ~INTR_WIN1_EMPTY;
4347 dev_warn_ratelimited(vop_dev->dev, "intr win1 empty!");
4350 if (intr_status & INTR_HWC_EMPTY) {
4351 intr_status &= ~INTR_HWC_EMPTY;
4352 dev_warn_ratelimited(vop_dev->dev, "intr hwc empty!");
4355 if (intr_status & INTR_POST_BUF_EMPTY) {
4356 intr_status &= ~INTR_POST_BUF_EMPTY;
4357 dev_warn_ratelimited(vop_dev->dev, "intr post buf empty!");
4361 dev_err(vop_dev->dev, "Unknown VOP IRQs: %#02x\n", intr_status);
4366 #if defined(CONFIG_PM)
4367 static int vop_suspend(struct platform_device *pdev, pm_message_t state)
4372 static int vop_resume(struct platform_device *pdev)
4377 #define vop_suspend NULL
4378 #define vop_resume NULL
4381 static int vop_parse_dt(struct vop_device *vop_dev)
4383 struct device_node *np = vop_dev->dev->of_node;
4384 struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
4387 if (of_property_read_u32(np, "rockchip,prop", &val))
4388 vop_dev->prop = PRMRY; /*default set it as primary */
4390 vop_dev->prop = val;
4392 if (of_property_read_u32(np, "rockchip,mirror", &val))
4393 dev_drv->rotate_mode = NO_MIRROR;
4395 dev_drv->rotate_mode = val;
4397 if (of_property_read_u32(np, "rockchip,pwr18", &val))
4398 /*default set it as 3.xv power supply */
4399 vop_dev->pwr18 = false;
4401 vop_dev->pwr18 = (val ? true : false);
4403 if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4404 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4406 dev_drv->fb_win_map = val;
4408 if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4409 dev_drv->bcsh.enable = false;
4411 dev_drv->bcsh.enable = (val ? true : false);
4413 if (of_property_read_u32(np, "rockchip,brightness", &val))
4414 dev_drv->bcsh.brightness = 0xffff;
4416 dev_drv->bcsh.brightness = val;
4418 if (of_property_read_u32(np, "rockchip,contrast", &val))
4419 dev_drv->bcsh.contrast = 0xffff;
4421 dev_drv->bcsh.contrast = val;
4423 if (of_property_read_u32(np, "rockchip,sat-con", &val))
4424 dev_drv->bcsh.sat_con = 0xffff;
4426 dev_drv->bcsh.sat_con = val;
4428 if (of_property_read_u32(np, "rockchip,hue", &val)) {
4429 dev_drv->bcsh.sin_hue = 0xffff;
4430 dev_drv->bcsh.cos_hue = 0xffff;
4432 dev_drv->bcsh.sin_hue = val & 0xff;
4433 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4436 if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4437 dev_drv->iommu_enabled = 0;
4439 dev_drv->iommu_enabled = val;
4443 static int vop_probe(struct platform_device *pdev)
4445 struct vop_device *vop_dev = NULL;
4446 struct rk_lcdc_driver *dev_drv;
4447 const struct of_device_id *of_id;
4448 struct device *dev = &pdev->dev;
4449 struct resource *res;
4450 struct device_node *np = pdev->dev.of_node;
4454 /* if the primary lcdc has not registered ,the extend
4455 * lcdc register later
4457 of_property_read_u32(np, "rockchip,prop", &prop);
4458 if (prop == EXTEND) {
4459 if (!is_prmry_rk_lcdc_registered())
4460 return -EPROBE_DEFER;
4462 vop_dev = devm_kzalloc(dev, sizeof(struct vop_device), GFP_KERNEL);
4465 of_id = of_match_device(vop_dt_ids, dev);
4466 vop_dev->data = of_id->data;
4467 if (VOP_CHIP(vop_dev) != VOP_RK322X && VOP_CHIP(vop_dev) != VOP_RK3399)
4469 platform_set_drvdata(pdev, vop_dev);
4471 vop_parse_dt(vop_dev);
4472 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4473 vop_dev->reg_phy_base = res->start;
4474 vop_dev->len = resource_size(res);
4475 vop_dev->regs = devm_ioremap_resource(dev, res);
4476 if (IS_ERR(vop_dev->regs))
4477 return PTR_ERR(vop_dev->regs);
4479 dev_info(dev, "vop_dev->regs=0x%lx\n", (long)vop_dev->regs);
4481 vop_dev->regsbak = devm_kzalloc(dev, vop_dev->len, GFP_KERNEL);
4482 if (IS_ERR(vop_dev->regsbak))
4483 return PTR_ERR(vop_dev->regsbak);
4484 if (VOP_CHIP(vop_dev) == VOP_RK3399) {
4485 vop_dev->dsp_lut_addr_base = vop_dev->regs + GAMMA_LUT_ADDR;
4486 vop_dev->cabc_lut_addr_base = vop_dev->regs +
4487 CABC_GAMMA_LUT_ADDR;
4490 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
4491 if (IS_ERR(vop_dev->grf_base)) {
4492 dev_err(&pdev->dev, "can't find lcdc grf property\n");
4493 vop_dev->grf_base = NULL;
4496 vop_dev->id = vop_get_id(vop_dev, vop_dev->reg_phy_base);
4497 dev_set_name(vop_dev->dev, "vop%d", vop_dev->id);
4498 dev_drv = &vop_dev->driver;
4500 dev_drv->prop = prop;
4501 dev_drv->id = vop_dev->id;
4502 dev_drv->ops = &lcdc_drv_ops;
4503 dev_drv->lcdc_win_num = vop_dev->data->n_wins;
4504 dev_drv->reserved_fb = 0;
4505 spin_lock_init(&vop_dev->reg_lock);
4506 spin_lock_init(&vop_dev->irq_lock);
4507 vop_dev->irq = platform_get_irq(pdev, 0);
4508 if (vop_dev->irq < 0) {
4509 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4514 ret = devm_request_irq(dev, vop_dev->irq, vop_isr,
4515 IRQF_SHARED, dev_name(dev), vop_dev);
4517 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4521 if (dev_drv->iommu_enabled)
4522 strcpy(dev_drv->mmu_dts_name, VOP_IOMMU_COMPATIBLE_NAME);
4523 ret = rk_fb_register(dev_drv, vop_dev->data->win, vop_dev->id);
4525 dev_err(dev, "register fb for lcdc%d failed!\n", vop_dev->id);
4528 vop_dev->screen = dev_drv->screen0;
4529 dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4530 vop_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4535 static int vop_remove(struct platform_device *pdev)
4540 static void vop_shutdown(struct platform_device *pdev)
4542 struct vop_device *vop_dev = platform_get_drvdata(pdev);
4543 struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
4545 dev_drv->suspend_flag = 1;
4546 /* ensure suspend_flag take effect on multi process */
4548 flush_kthread_worker(&dev_drv->update_regs_worker);
4549 kthread_stop(dev_drv->update_regs_thread);
4552 vop_clk_disable(vop_dev);
4553 rk_disp_pwr_disable(dev_drv);
4556 static struct platform_driver vop_driver = {
4558 .remove = vop_remove,
4560 .name = "rk322x-lcdc",
4561 .owner = THIS_MODULE,
4562 .of_match_table = of_match_ptr(vop_dt_ids),
4564 .suspend = vop_suspend,
4565 .resume = vop_resume,
4566 .shutdown = vop_shutdown,
4569 static int __init vop_module_init(void)
4571 return platform_driver_register(&vop_driver);
4574 static void __exit vop_module_exit(void)
4576 platform_driver_unregister(&vop_driver);
4579 fs_initcall(vop_module_init);
4580 module_exit(vop_module_exit);