2 * drivers/video/rockchip/lcdc/rk322x_lcdc.c
4 * Copyright (C) 2015 ROCKCHIP, Inc.
5 * Author: Mark Yao <mark.yao@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/string.h>
22 #include <linux/slab.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/rockchip-iovmm.h>
30 #include <asm/div64.h>
31 #include <linux/uaccess.h>
32 #include <linux/rockchip/cpu.h>
33 #include <linux/rockchip/iomap.h>
34 #include <linux/rockchip/grf.h>
35 #include <linux/rockchip/common.h>
36 #include <dt-bindings/clock/rk_system_status.h>
38 #include "rk322x_lcdc.h"
40 /*#define CONFIG_RK_FPGA 1*/
42 static int dbg_thresd;
43 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
45 #define DBG(level, x...) do { \
46 if (unlikely(dbg_thresd >= level)) \
50 static const uint32_t csc_y2r_bt601_limit[12] = {
51 0x04a8, 0, 0x0662, 0xfffc8654,
52 0x04a8, 0xfe6f, 0xfcbf, 0x00022056,
53 0x04a8, 0x0812, 0, 0xfffbaeac,
56 static const uint32_t csc_y2r_bt709_full[12] = {
57 0x04a8, 0, 0x072c, 0xfffc219e,
58 0x04a8, 0xff26, 0xfdde, 0x0001357b,
59 0x04a8, 0x0873, 0, 0xfffb7dee,
62 static const uint32_t csc_y2r_bt601_full[12] = {
63 0x0400, 0, 0x059c, 0xfffd342d,
64 0x0400, 0xfea0, 0xfd25, 0x00021fcc,
65 0x0400, 0x0717, 0, 0xfffc76bc,
68 static const uint32_t csc_y2r_bt601_limit_10[12] = {
69 0x04a8, 0, 0x0662, 0xfff2134e,
70 0x04a8, 0xfe6f, 0xfcbf, 0x00087b58,
71 0x04a8, 0x0812, 0, 0xffeeb4b0,
74 static const uint32_t csc_y2r_bt709_full_10[12] = {
75 0x04a8, 0, 0x072c, 0xfff08077,
76 0x04a8, 0xff26, 0xfdde, 0x0004cfed,
77 0x04a8, 0x0873, 0, 0xffedf1b8,
80 static const uint32_t csc_y2r_bt601_full_10[12] = {
81 0x0400, 0, 0x059c, 0xfff4cab4,
82 0x0400, 0xfea0, 0xfd25, 0x00087932,
83 0x0400, 0x0717, 0, 0xfff1d4f2,
86 static const uint32_t csc_y2r_bt2020[12] = {
87 0x04a8, 0, 0x06b6, 0xfff16bfc,
88 0x04a8, 0xff40, 0xfd66, 0x58ae9,
89 0x04a8, 0x0890, 0, 0xffedb828,
92 static const uint32_t csc_r2y_bt601_limit[12] = {
93 0x0107, 0x0204, 0x0064, 0x04200,
94 0xff68, 0xfed6, 0x01c2, 0x20200,
95 0x01c2, 0xfe87, 0xffb7, 0x20200,
98 static const uint32_t csc_r2y_bt709_full[12] = {
99 0x00bb, 0x0275, 0x003f, 0x04200,
100 0xff99, 0xfea5, 0x01c2, 0x20200,
101 0x01c2, 0xfe68, 0xffd7, 0x20200,
104 static const uint32_t csc_r2y_bt601_full[12] = {
105 0x0132, 0x0259, 0x0075, 0x200,
106 0xff53, 0xfead, 0x0200, 0x20200,
107 0x0200, 0xfe53, 0xffad, 0x20200,
110 static const uint32_t csc_r2y_bt601_limit_10[12] = {
111 0x0107, 0x0204, 0x0064, 0x10200,
112 0xff68, 0xfed6, 0x01c2, 0x80200,
113 0x01c2, 0xfe87, 0xffb7, 0x80200,
116 static const uint32_t csc_r2y_bt709_full_10[12] = {
117 0x00bb, 0x0275, 0x003f, 0x10200,
118 0xff99, 0xfea5, 0x01c2, 0x80200,
119 0x01c2, 0xfe68, 0xffd7, 0x80200,
122 static const uint32_t csc_r2y_bt601_full_10[12] = {
123 0x0132, 0x0259, 0x0075, 0x200,
124 0xff53, 0xfead, 0x0200, 0x80200,
125 0x0200, 0xfe53, 0xffad, 0x80200,
128 static const uint32_t csc_r2y_bt2020[12] = {
129 0x00e6, 0x0253, 0x0034, 0x10200,
130 0xff83, 0xfebd, 0x01c1, 0x80200,
131 0x01c1, 0xfe64, 0xffdc, 0x80200,
134 static const uint32_t csc_r2r_bt2020to709[12] = {
135 0x06a4, 0xfda6, 0xffb5, 0x200,
136 0xff80, 0x0488, 0xfff8, 0x200,
137 0xffed, 0xff99, 0x047a, 0x200,
140 static const uint32_t csc_r2r_bt709to2020[12] = {
141 0x282, 0x151, 0x02c, 0x200,
142 0x047, 0x3ae, 0x00c, 0x200,
143 0x011, 0x05a, 0x395, 0x200,
146 static struct rk_lcdc_win vop_win[] = {
147 { .name = "win0", .id = 0},
148 { .name = "win1", .id = 1},
149 { .name = "hwc", .id = 2}
152 static void vop_load_csc_table(struct vop_device *vop_dev, u32 offset,
153 const uint32_t *table)
157 csc_val = table[1] << 16 | table[0];
158 vop_writel(vop_dev, offset, csc_val);
159 csc_val = table[4] << 16 | table[2];
160 vop_writel(vop_dev, offset + 4, csc_val);
161 csc_val = table[6] << 16 | table[5];
162 vop_writel(vop_dev, offset + 8, csc_val);
163 csc_val = table[9] << 16 | table[8];
164 vop_writel(vop_dev, offset + 0xc, csc_val);
166 vop_writel(vop_dev, offset + 0x10, csc_val);
168 vop_writel(vop_dev, offset + 0x14, csc_val);
170 vop_writel(vop_dev, offset + 0x18, csc_val);
172 vop_writel(vop_dev, offset + 0x1c, csc_val);
175 static int vop_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
177 static int vop_clk_enable(struct vop_device *vop_dev)
179 if (!vop_dev->clk_on) {
180 clk_prepare_enable(vop_dev->hclk);
181 clk_prepare_enable(vop_dev->dclk);
182 clk_prepare_enable(vop_dev->aclk);
183 clk_prepare_enable(vop_dev->hclk_noc);
184 clk_prepare_enable(vop_dev->aclk_noc);
185 spin_lock(&vop_dev->reg_lock);
187 spin_unlock(&vop_dev->reg_lock);
193 static int vop_clk_disable(struct vop_device *vop_dev)
195 if (vop_dev->clk_on) {
196 spin_lock(&vop_dev->reg_lock);
198 spin_unlock(&vop_dev->reg_lock);
200 clk_disable_unprepare(vop_dev->dclk);
201 clk_disable_unprepare(vop_dev->hclk);
202 clk_disable_unprepare(vop_dev->aclk);
203 clk_disable_unprepare(vop_dev->hclk_noc);
204 clk_disable_unprepare(vop_dev->aclk_noc);
210 static int __maybe_unused vop_disable_irq(struct vop_device *vop_dev)
212 if (likely(vop_dev->clk_on)) {
213 spin_lock(&vop_dev->reg_lock);
214 vop_writel(vop_dev, INTR_EN0, 0xffff0000);
215 vop_writel(vop_dev, INTR_EN1, 0xffff0000);
216 vop_writel(vop_dev, INTR_CLEAR0, 0xffffffff);
217 vop_writel(vop_dev, INTR_CLEAR1, 0xffffffff);
218 vop_cfg_done(vop_dev);
219 spin_unlock(&vop_dev->reg_lock);
225 static int vop_reg_dump(struct rk_lcdc_driver *dev_drv)
227 struct vop_device *vop_dev =
228 container_of(dev_drv, struct vop_device, driver);
229 int *cbase = (int *)vop_dev->regs;
230 int *regsbak = (int *)vop_dev->regsbak;
232 char dbg_message[30];
235 pr_info("lcd back up reg:\n");
236 memset(dbg_message, 0, sizeof(dbg_message));
237 memset(buf, 0, sizeof(buf));
238 for (i = 0; i <= (0x200 >> 4); i++) {
239 val = sprintf(dbg_message, "0x%04x: ", i * 16);
240 for (j = 0; j < 4; j++) {
241 val = sprintf(buf, "%08x ", *(regsbak + i * 4 + j));
242 strcat(dbg_message, buf);
244 pr_info("%s\n", dbg_message);
245 memset(dbg_message, 0, sizeof(dbg_message));
246 memset(buf, 0, sizeof(buf));
249 pr_info("lcdc reg:\n");
250 for (i = 0; i <= (0x200 >> 4); i++) {
251 val = sprintf(dbg_message, "0x%04x: ", i * 16);
252 for (j = 0; j < 4; j++) {
253 sprintf(buf, "%08x ",
254 readl_relaxed(cbase + i * 4 + j));
255 strcat(dbg_message, buf);
257 pr_info("%s\n", dbg_message);
258 memset(dbg_message, 0, sizeof(dbg_message));
259 memset(buf, 0, sizeof(buf));
266 static int win##id##_enable(struct vop_device *vop_dev, int en) \
268 spin_lock(&vop_dev->reg_lock); \
269 vop_msk_reg(vop_dev, WIN##id##_CTRL0, V_WIN##id##_EN((u64)en)); \
270 vop_cfg_done(vop_dev); \
271 spin_unlock(&vop_dev->reg_lock); \
278 /*enable/disable win directly*/
279 static int vop_win_direct_en(struct rk_lcdc_driver *drv,
282 struct vop_device *vop_dev =
283 container_of(drv, struct vop_device, driver);
285 win0_enable(vop_dev, en);
286 else if (win_id == 1)
287 win1_enable(vop_dev, en);
289 dev_err(vop_dev->dev, "invalid win number:%d\n", win_id);
293 #define SET_WIN_ADDR(id) \
294 static int set_win##id##_addr(struct vop_device *vop_dev, u32 addr) \
296 spin_lock(&vop_dev->reg_lock); \
297 vop_writel(vop_dev, WIN##id##_YRGB_MST, addr); \
298 vop_msk_reg(vop_dev, WIN##id##_CTRL0, V_WIN##id##_EN(1)); \
299 vop_cfg_done(vop_dev); \
300 spin_unlock(&vop_dev->reg_lock); \
306 int vop_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
307 int win_id, u32 addr)
309 struct vop_device *vop_dev =
310 container_of(dev_drv, struct vop_device, driver);
312 set_win0_addr(vop_dev, addr);
314 set_win1_addr(vop_dev, addr);
319 static void lcdc_read_reg_defalut_cfg(struct vop_device *vop_dev)
323 struct rk_screen *screen = vop_dev->driver.cur_screen;
324 u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
325 u32 V_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
327 struct rk_lcdc_win *win0 = vop_dev->driver.win[0];
329 spin_lock(&vop_dev->reg_lock);
330 for (reg = 0; reg < vop_dev->len; reg += 4) {
331 val = vop_readl_backup(vop_dev, reg);
334 win0->area[0].xact = (val & MASK(WIN0_ACT_WIDTH)) + 1;
336 ((val & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1;
339 win0->area[0].xsize = (val & MASK(WIN0_DSP_WIDTH)) + 1;
340 win0->area[0].ysize =
341 ((val & MASK(WIN0_DSP_HEIGHT)) >> 16) + 1;
344 st_x = val & MASK(WIN0_DSP_XST);
345 st_y = (val & MASK(WIN0_DSP_YST)) >> 16;
346 win0->area[0].xpos = st_x - h_pw_bp;
347 win0->area[0].ypos = st_y - V_pw_bp;
350 win0->state = val & MASK(WIN0_EN);
351 win0->area[0].fmt_cfg =
352 (val & MASK(WIN0_DATA_FMT)) >> 1;
353 win0->fmt_10 = (val & MASK(WIN0_FMT_10)) >> 4;
354 win0->area[0].format = win0->area[0].fmt_cfg;
357 win0->area[0].y_vir_stride =
358 val & MASK(WIN0_VIR_STRIDE);
359 win0->area[0].uv_vir_stride =
360 (val & MASK(WIN0_VIR_STRIDE_UV)) >> 16;
361 if (win0->area[0].format == ARGB888)
362 win0->area[0].xvir = win0->area[0].y_vir_stride;
363 else if (win0->area[0].format == RGB888)
365 win0->area[0].y_vir_stride * 4 / 3;
366 else if (win0->area[0].format == RGB565)
368 2 * win0->area[0].y_vir_stride;
371 4 * win0->area[0].y_vir_stride;
374 win0->area[0].smem_start = val;
377 win0->area[0].cbr_start = val;
383 spin_unlock(&vop_dev->reg_lock);
386 /********do basic init*********/
387 static int vop_pre_init(struct rk_lcdc_driver *dev_drv)
389 struct vop_device *vop_dev =
390 container_of(dev_drv, struct vop_device, driver);
391 if (vop_dev->pre_init)
394 vop_dev->hclk = devm_clk_get(vop_dev->dev, "hclk_vop");
395 vop_dev->aclk = devm_clk_get(vop_dev->dev, "aclk_vop");
396 vop_dev->dclk = devm_clk_get(vop_dev->dev, "dclk_vop");
397 vop_dev->hclk_noc = devm_clk_get(vop_dev->dev, "hclk_vop_noc");
398 vop_dev->aclk_noc = devm_clk_get(vop_dev->dev, "aclk_vop_noc");
400 if (IS_ERR(vop_dev->aclk) || IS_ERR(vop_dev->dclk) ||
401 IS_ERR(vop_dev->hclk) || IS_ERR(vop_dev->hclk_noc) ||
402 IS_ERR(vop_dev->aclk_noc))
403 dev_err(vop_dev->dev, "failed to get clk source\n");
404 if (!support_uboot_display())
405 rk_disp_pwr_enable(dev_drv);
406 vop_clk_enable(vop_dev);
408 memcpy(vop_dev->regsbak, vop_dev->regs, vop_dev->len);
409 /*backup reg config at uboot */
410 lcdc_read_reg_defalut_cfg(vop_dev);
411 #ifndef CONFIG_RK_FPGA
415 if (vop_dev->pwr18 == 1) {
417 vop_grf_writel(vop_dev->pmugrf_base,
418 PMUGRF_SOC_CON0_VOP, v);
421 vop_grf_writel(vop_dev->pmugrf_base,
422 PMUGRF_SOC_CON0_VOP, v);
426 vop_writel(vop_dev, FRC_LOWER01_0, 0x12844821);
427 vop_writel(vop_dev, FRC_LOWER01_1, 0x21488412);
428 vop_writel(vop_dev, FRC_LOWER10_0, 0xa55a9696);
429 vop_writel(vop_dev, FRC_LOWER10_1, 0x5aa56969);
430 vop_writel(vop_dev, FRC_LOWER11_0, 0xdeb77deb);
431 vop_writel(vop_dev, FRC_LOWER11_1, 0xed7bb7de);
433 vop_msk_reg(vop_dev, SYS_CTRL, V_AUTO_GATING_EN(0));
434 vop_msk_reg(vop_dev, DSP_CTRL1, V_DITHER_UP_EN(1));
435 vop_cfg_done(vop_dev);
436 vop_dev->pre_init = true;
441 static void vop_deint(struct vop_device *vop_dev)
443 if (vop_dev->clk_on) {
444 vop_disable_irq(vop_dev);
445 spin_lock(&vop_dev->reg_lock);
446 vop_msk_reg(vop_dev, WIN0_CTRL0, V_WIN0_EN(0));
447 vop_msk_reg(vop_dev, WIN1_CTRL0, V_WIN0_EN(0));
449 vop_cfg_done(vop_dev);
450 spin_unlock(&vop_dev->reg_lock);
456 static void vop_win_csc_mode(struct vop_device *vop_dev,
457 struct rk_lcdc_win *win,
463 val = V_WIN0_CSC_MODE(csc_mode);
464 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
465 } else if (win->id == 1) {
466 val = V_WIN1_CSC_MODE(csc_mode);
467 vop_msk_reg(vop_dev, WIN1_CTRL0, val);
469 val = V_HWC_CSC_MODE(csc_mode);
470 vop_msk_reg(vop_dev, HWC_CTRL0, val);
476 * Input Win csc Post csc Output
477 * 1. YUV(2020) --> bypass ---+ Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
478 * RGB --> R2Y(709) __/
480 * 2. YUV(2020) --> bypass ---+ bypass --> YUV_OUTPUT(2020)
481 * RGB --> R2Y(709) __/
483 * 3. YUV(2020) --> bypass ---+ Y2R->2020To709 --> RGB_OUTPUT(709)
484 * RGB --> R2Y(709) __/
486 * 4. YUV(601/709)-> bypass ---+ Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
487 * RGB --> R2Y(709) __/
489 * 5. YUV(601/709)-> bypass ---+ bypass --> YUV_OUTPUT(709)
490 * RGB --> R2Y(709) __/
492 * 6. YUV(601/709)-> bypass ---+ bypass --> YUV_OUTPUT(601)
493 * RGB --> R2Y(601) __/
495 * 7. YUV(601) --> Y2R(601/mpeg)-+ bypass --> RGB_OUTPUT(709)
496 * RGB --> bypass ____/
498 * 8. YUV(709) --> Y2R(709/hd) --+ bypass --> RGB_OUTPUT(709)
499 * RGB --> bypass ____/
501 * 9. RGB --> bypass ---> 709To2020->R2Y --> YUV_OUTPUT(2020)
503 * 10. RGB --> R2Y(709) ---> Y2R --> YUV_OUTPUT(709)
505 * 11. RGB --> R2Y(601) ---> Y2R --> YUV_OUTPUT(601)
507 * 12. RGB --> bypass ---> bypass --> RGB_OUTPUT(709)
510 static void vop_post_csc_cfg(struct rk_lcdc_driver *dev_drv)
512 struct vop_device *vop_dev =
513 container_of(dev_drv, struct vop_device, driver);
514 struct rk_lcdc_win *win;
515 int output_color = dev_drv->output_color;
518 int win_csc = COLOR_RGB;
521 if (output_color == COLOR_RGB)
522 overlay_mode = VOP_RGB_DOMAIN;
524 overlay_mode = VOP_YUV_DOMAIN;
526 if (output_color == COLOR_YCBCR)
527 r2y_mode = VOP_R2Y_CSC_BT601;
529 r2y_mode = VOP_R2Y_CSC_BT709;
531 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
532 win = dev_drv->win[i];
536 * force use yuv domain when there is a windows's csc is bt2020.
538 if (win->colorspace == CSC_BT2020) {
539 overlay_mode = VOP_YUV_DOMAIN;
540 r2y_mode = VOP_R2Y_CSC_BT709;
541 win_csc = COLOR_YCBCR_BT2020;
544 if (IS_YUV(win->area[0].fmt_cfg))
545 win_csc = COLOR_YCBCR;
548 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
549 win = dev_drv->win[i];
552 if (overlay_mode == VOP_YUV_DOMAIN &&
553 !IS_YUV(win->area[0].fmt_cfg))
554 vop_win_csc_mode(vop_dev, win, r2y_mode);
555 if (overlay_mode == VOP_RGB_DOMAIN &&
556 IS_YUV(win->area[0].fmt_cfg)) {
557 if (win->colorspace == CSC_BT709)
558 vop_win_csc_mode(vop_dev, win, VOP_Y2R_CSC_HD);
559 else if (win->colorspace == CSC_BT601)
560 vop_win_csc_mode(vop_dev, win,
563 pr_err("Error Y2R path, colorspace=%d\n",
568 if (win_csc == COLOR_RGB && overlay_mode == VOP_YUV_DOMAIN)
569 win_csc = COLOR_YCBCR;
570 else if (IS_YUV_COLOR(win_csc) && overlay_mode == VOP_RGB_DOMAIN)
573 val = V_YUV2YUV_POST_Y2R_EN(0) | V_YUV2YUV_POST_EN(0) |
574 V_YUV2YUV_POST_R2Y_EN(0);
576 if (win_csc == COLOR_YCBCR && output_color == COLOR_YCBCR_BT2020) {
578 val |= V_YUV2YUV_POST_Y2R_EN(1);
579 vop_load_csc_table(vop_dev, POST_YUV2YUV_Y2R_COE,
582 if (win_csc == COLOR_YCBCR_BT2020 &&
583 output_color != COLOR_YCBCR_BT2020) {
584 win_csc = COLOR_RGB_BT2020;
585 val |= V_YUV2YUV_POST_Y2R_EN(1);
586 vop_load_csc_table(vop_dev, POST_YUV2YUV_Y2R_COE,
591 if (win_csc == COLOR_RGB && output_color == COLOR_YCBCR_BT2020) {
592 win_csc = COLOR_RGB_BT2020;
593 val |= V_YUV2YUV_POST_EN(1);
594 vop_load_csc_table(vop_dev, POST_YUV2YUV_3x3_COE,
595 csc_r2r_bt709to2020);
597 if (win_csc == COLOR_RGB_BT2020 &&
598 (output_color == COLOR_YCBCR ||
599 output_color == COLOR_YCBCR_BT709 ||
600 output_color == COLOR_RGB)) {
602 val |= V_YUV2YUV_POST_EN(1);
603 vop_load_csc_table(vop_dev, POST_YUV2YUV_3x3_COE,
604 csc_r2r_bt2020to709);
608 if (!IS_YUV_COLOR(win_csc) && IS_YUV_COLOR(output_color)) {
609 val |= V_YUV2YUV_POST_R2Y_EN(1);
611 if (output_color == COLOR_YCBCR_BT2020)
612 vop_load_csc_table(vop_dev, POST_YUV2YUV_R2Y_COE,
615 vop_load_csc_table(vop_dev, POST_YUV2YUV_R2Y_COE,
619 DBG(1, "win_csc=%d output_color=%d val=%llx overlay_mode=%d\n",
620 win_csc, output_color, val, overlay_mode);
621 vop_msk_reg(vop_dev, SYS_CTRL, V_OVERLAY_MODE(overlay_mode));
622 vop_msk_reg(vop_dev, YUV2YUV_POST, val);
625 static int vop_post_cfg(struct rk_lcdc_driver *dev_drv)
627 struct vop_device *vop_dev =
628 container_of(dev_drv, struct vop_device, driver);
629 struct rk_screen *screen = dev_drv->cur_screen;
630 u16 x_res = screen->mode.xres;
631 u16 y_res = screen->mode.yres;
633 u16 h_total, v_total;
634 u16 post_hsd_en, post_vsd_en;
635 u16 post_dsp_hact_st, post_dsp_hact_end;
636 u16 post_dsp_vact_st, post_dsp_vact_end;
637 u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
638 u16 post_h_fac, post_v_fac;
640 screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200;
641 screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200;
642 screen->post_xsize = x_res *
643 (dev_drv->overscan.left + dev_drv->overscan.right) / 200;
644 screen->post_ysize = y_res *
645 (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200;
647 h_total = screen->mode.hsync_len + screen->mode.left_margin +
648 x_res + screen->mode.right_margin;
649 v_total = screen->mode.vsync_len + screen->mode.upper_margin +
650 y_res + screen->mode.lower_margin;
652 if (screen->post_dsp_stx + screen->post_xsize > x_res) {
653 dev_warn(vop_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
654 screen->post_dsp_stx, screen->post_xsize, x_res);
655 screen->post_dsp_stx = x_res - screen->post_xsize;
657 if (screen->x_mirror == 0) {
658 post_dsp_hact_st = screen->post_dsp_stx +
659 screen->mode.hsync_len + screen->mode.left_margin;
660 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
662 post_dsp_hact_end = h_total - screen->mode.right_margin -
663 screen->post_dsp_stx;
664 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
666 if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
669 GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
675 if (screen->post_dsp_sty + screen->post_ysize > y_res) {
676 dev_warn(vop_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
677 screen->post_dsp_sty, screen->post_ysize, y_res);
678 screen->post_dsp_sty = y_res - screen->post_ysize;
681 if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
683 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
690 if (screen->mode.vmode & FB_VMODE_INTERLACED) {
691 post_dsp_vact_st = screen->post_dsp_sty / 2 +
692 screen->mode.vsync_len +
693 screen->mode.upper_margin;
694 post_dsp_vact_end = post_dsp_vact_st +
695 screen->post_ysize / 2;
697 post_dsp_vact_st_f1 = screen->mode.vsync_len +
698 screen->mode.upper_margin +
700 screen->mode.lower_margin +
701 screen->mode.vsync_len +
702 screen->mode.upper_margin +
703 screen->post_dsp_sty / 2 +
705 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
706 screen->post_ysize/2;
708 if (screen->y_mirror == 0) {
709 post_dsp_vact_st = screen->post_dsp_sty +
710 screen->mode.vsync_len +
711 screen->mode.upper_margin;
712 post_dsp_vact_end = post_dsp_vact_st +
715 post_dsp_vact_end = v_total -
716 screen->mode.lower_margin -
717 screen->post_dsp_sty;
718 post_dsp_vact_st = post_dsp_vact_end -
721 post_dsp_vact_st_f1 = 0;
722 post_dsp_vact_end_f1 = 0;
724 DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
725 screen->post_xsize, screen->post_ysize, screen->xpos);
726 DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
727 screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
728 val = V_DSP_HACT_END_POST(post_dsp_hact_end) |
729 V_DSP_HACT_ST_POST(post_dsp_hact_st);
730 vop_msk_reg(vop_dev, POST_DSP_HACT_INFO, val);
732 val = V_DSP_VACT_END_POST(post_dsp_vact_end) |
733 V_DSP_VACT_ST_POST(post_dsp_vact_st);
734 vop_msk_reg(vop_dev, POST_DSP_VACT_INFO, val);
736 val = V_POST_HS_FACTOR_YRGB(post_h_fac) |
737 V_POST_VS_FACTOR_YRGB(post_v_fac);
738 vop_msk_reg(vop_dev, POST_SCL_FACTOR_YRGB, val);
739 val = V_DSP_VACT_END_POST(post_dsp_vact_end_f1) |
740 V_DSP_VACT_ST_POST(post_dsp_vact_st_f1);
741 vop_msk_reg(vop_dev, POST_DSP_VACT_INFO_F1, val);
742 val = V_POST_HOR_SD_EN(post_hsd_en) | V_POST_VER_SD_EN(post_vsd_en);
743 vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
745 vop_post_csc_cfg(dev_drv);
750 static int vop_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
752 struct vop_device *vop_dev =
753 container_of(dev_drv, struct vop_device, driver);
754 struct rk_lcdc_win *win;
755 u32 colorkey_r, colorkey_g, colorkey_b;
758 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
759 win = dev_drv->win[i];
760 key_val = win->color_key_val;
761 colorkey_r = (key_val & 0xff) << 2;
762 colorkey_g = ((key_val >> 8) & 0xff) << 12;
763 colorkey_b = ((key_val >> 16) & 0xff) << 22;
764 /* color key dither 565/888->aaa */
765 key_val = colorkey_r | colorkey_g | colorkey_b;
768 vop_writel(vop_dev, WIN0_COLOR_KEY, key_val);
771 vop_writel(vop_dev, WIN1_COLOR_KEY, key_val);
774 pr_info("%s:un support win num:%d\n",
782 static int vop_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
784 struct vop_device *vop_dev =
785 container_of(dev_drv, struct vop_device, driver);
786 struct rk_lcdc_win *win = dev_drv->win[win_id];
787 struct alpha_config alpha_config;
789 int ppixel_alpha = 0, global_alpha = 0, i;
790 u32 src_alpha_ctl, dst_alpha_ctl;
793 for (i = 0; i < win->area_num; i++) {
794 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
795 (win->area[i].format == FBDC_ARGB_888) ||
796 (win->area[i].format == FBDC_ABGR_888) ||
797 (win->area[i].format == ABGR888)) ? 1 : 0;
800 global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
802 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
803 if (!dev_drv->win[i]->state)
805 if (win->z_order > dev_drv->win[i]->z_order)
810 * The bottom layer not support ppixel_alpha mode.
812 if (i == dev_drv->lcdc_win_num)
814 alpha_config.src_global_alpha_val = win->g_alpha_val;
815 win->alpha_mode = AB_SRC_OVER;
817 switch (win->alpha_mode) {
821 alpha_config.src_factor_mode = AA_ZERO;
822 alpha_config.dst_factor_mode = AA_ZERO;
825 alpha_config.src_factor_mode = AA_ONE;
826 alpha_config.dst_factor_mode = AA_ZERO;
829 alpha_config.src_factor_mode = AA_ZERO;
830 alpha_config.dst_factor_mode = AA_ONE;
833 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
835 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
837 alpha_config.src_factor_mode = AA_ONE;
838 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
841 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
842 alpha_config.src_factor_mode = AA_SRC_INVERSE;
843 alpha_config.dst_factor_mode = AA_ONE;
846 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
847 alpha_config.src_factor_mode = AA_SRC;
848 alpha_config.dst_factor_mode = AA_ZERO;
851 alpha_config.src_factor_mode = AA_ZERO;
852 alpha_config.dst_factor_mode = AA_SRC;
855 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
856 alpha_config.src_factor_mode = AA_SRC_INVERSE;
857 alpha_config.dst_factor_mode = AA_ZERO;
860 alpha_config.src_factor_mode = AA_ZERO;
861 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
864 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
865 alpha_config.src_factor_mode = AA_SRC;
866 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
869 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
870 alpha_config.src_factor_mode = AA_SRC_INVERSE;
871 alpha_config.dst_factor_mode = AA_SRC;
874 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
875 alpha_config.src_factor_mode = AA_SRC_INVERSE;
876 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
878 case AB_SRC_OVER_GLOBAL:
879 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
880 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
881 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
882 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
885 pr_err("alpha mode error\n");
888 if ((ppixel_alpha == 1) && (global_alpha == 1))
889 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
890 else if (ppixel_alpha == 1)
891 alpha_config.src_global_alpha_mode = AA_PER_PIX;
892 else if (global_alpha == 1)
893 alpha_config.src_global_alpha_mode = AA_GLOBAL;
896 alpha_config.src_alpha_mode = AA_STRAIGHT;
897 alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
901 src_alpha_ctl = 0x60;
902 dst_alpha_ctl = 0x64;
905 src_alpha_ctl = 0xa0;
906 dst_alpha_ctl = 0xa4;
909 src_alpha_ctl = 0x160;
910 dst_alpha_ctl = 0x164;
913 val = V_WIN0_DST_FACTOR_MODE(alpha_config.dst_factor_mode);
914 vop_msk_reg(vop_dev, dst_alpha_ctl, val);
915 val = V_WIN0_SRC_ALPHA_EN(alpha_en) |
916 V_WIN0_SRC_COLOR_MODE(alpha_config.src_color_mode) |
917 V_WIN0_SRC_ALPHA_MODE(alpha_config.src_alpha_mode) |
918 V_WIN0_SRC_BLEND_MODE(alpha_config.src_global_alpha_mode) |
919 V_WIN0_SRC_ALPHA_CAL_MODE(alpha_config.src_alpha_cal_m0) |
920 V_WIN0_SRC_FACTOR_MODE(alpha_config.src_factor_mode) |
921 V_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
923 vop_msk_reg(vop_dev, src_alpha_ctl, val);
928 static int vop_axi_gather_cfg(struct vop_device *vop_dev,
929 struct rk_lcdc_win *win)
932 u16 yrgb_gather_num = 3;
933 u16 cbcr_gather_num = 1;
935 switch (win->area[0].format) {
956 dev_err(vop_dev->driver.dev, "%s:un supported format[%d]\n",
957 __func__, win->area[0].format);
961 if ((win->id == 0) || (win->id == 1)) {
962 val = V_WIN0_YRGB_AXI_GATHER_EN(1) |
963 V_WIN0_CBR_AXI_GATHER_EN(1) |
964 V_WIN0_YRGB_AXI_GATHER_NUM(yrgb_gather_num) |
965 V_WIN0_CBR_AXI_GATHER_NUM(cbcr_gather_num);
966 vop_msk_reg(vop_dev, WIN0_CTRL1 + (win->id * 0x40), val);
967 } else if (win->id == 2) {
968 val = V_HWC_AXI_GATHER_EN(1) |
969 V_HWC_AXI_GATHER_NUM(yrgb_gather_num);
970 vop_msk_reg(vop_dev, HWC_CTRL1, val);
975 static int vop_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
977 struct vop_device *vop_dev =
978 container_of(dev_drv, struct vop_device, driver);
979 struct rk_lcdc_win *win = dev_drv->win[win_id];
986 if (win->state == 1) {
987 vop_axi_gather_cfg(vop_dev, win);
990 * rk322x have a bug on windows 0 and 1:
992 * When switch win format from RGB to YUV, would flash
993 * some green lines on the top of the windows.
995 * Use bg_en show one blank frame to skip the error frame.
997 if (IS_YUV(win->area[0].fmt_cfg)) {
998 val = vop_readl(vop_dev, WIN0_CTRL0);
999 format = (val & MASK(WIN0_DATA_FMT)) >> 1;
1001 if (!IS_YUV(format)) {
1002 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1003 val = V_WIN0_DSP_BG_RED(0x200) |
1004 V_WIN0_DSP_BG_GREEN(0x40) |
1005 V_WIN0_DSP_BG_BLUE(0x200) |
1007 vop_msk_reg(vop_dev, WIN0_DSP_BG + off,
1010 val = V_WIN0_DSP_BG_RED(0) |
1011 V_WIN0_DSP_BG_GREEN(0) |
1012 V_WIN0_DSP_BG_BLUE(0) |
1014 vop_msk_reg(vop_dev, WIN0_DSP_BG + off,
1018 val = V_WIN0_BG_EN(0);
1019 vop_msk_reg(vop_dev, WIN0_DSP_BG + off, val);
1022 val = V_WIN0_BG_EN(0);
1023 vop_msk_reg(vop_dev, WIN0_DSP_BG + off, val);
1026 val = V_WIN0_EN(win->state) |
1027 V_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1028 V_WIN0_FMT_10(win->fmt_10) |
1029 V_WIN0_LB_MODE(win->win_lb_mode) |
1030 V_WIN0_RB_SWAP(win->area[0].swap_rb) |
1031 V_WIN0_X_MIR_EN(win->xmirror) |
1032 V_WIN0_Y_MIR_EN(win->ymirror) |
1033 V_WIN0_UV_SWAP(win->area[0].swap_uv);
1034 vop_msk_reg(vop_dev, WIN0_CTRL0 + off, val);
1035 val = V_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1036 V_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1037 V_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1038 V_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1039 V_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1040 V_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1041 V_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1042 V_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1043 V_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1044 V_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1045 V_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1046 V_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1047 V_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1048 V_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1049 V_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1050 vop_msk_reg(vop_dev, WIN0_CTRL1 + off, val);
1051 val = V_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1052 V_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1053 vop_writel(vop_dev, WIN0_VIR + off, val);
1054 val = V_WIN0_ACT_WIDTH(win->area[0].xact - 1) |
1055 V_WIN0_ACT_HEIGHT(win->area[0].yact - 1);
1056 vop_writel(vop_dev, WIN0_ACT_INFO + off, val);
1058 val = V_WIN0_DSP_WIDTH(win->area[0].xsize - 1) |
1059 V_WIN0_DSP_HEIGHT(win->area[0].ysize - 1);
1060 vop_writel(vop_dev, WIN0_DSP_INFO + off, val);
1062 val = V_WIN0_DSP_XST(win->area[0].dsp_stx) |
1063 V_WIN0_DSP_YST(win->area[0].dsp_sty);
1064 vop_writel(vop_dev, WIN0_DSP_ST + off, val);
1066 val = V_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1067 V_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1068 vop_writel(vop_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1070 val = V_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1071 V_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1072 vop_writel(vop_dev, WIN0_SCL_FACTOR_CBR + off, val);
1073 if (win->alpha_en == 1) {
1074 vop_alpha_cfg(dev_drv, win_id);
1076 val = V_WIN0_SRC_ALPHA_EN(0);
1077 vop_msk_reg(vop_dev, WIN0_SRC_ALPHA_CTRL + off, val);
1081 val = V_WIN0_EN(win->state);
1082 vop_msk_reg(vop_dev, WIN0_CTRL0 + off, val);
1088 static int vop_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1090 struct vop_device *vop_dev =
1091 container_of(dev_drv, struct vop_device, driver);
1092 struct rk_lcdc_win *win = dev_drv->win[win_id];
1093 unsigned int hwc_size = 0;
1096 if (win->state == 1) {
1097 vop_axi_gather_cfg(vop_dev, win);
1098 val = V_HWC_EN(1) | V_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1099 V_HWC_RB_SWAP(win->area[0].swap_rb);
1100 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1102 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1104 else if ((win->area[0].xsize == 64) &&
1105 (win->area[0].ysize == 64))
1107 else if ((win->area[0].xsize == 96) &&
1108 (win->area[0].ysize == 96))
1110 else if ((win->area[0].xsize == 128) &&
1111 (win->area[0].ysize == 128))
1114 dev_err(vop_dev->dev, "un supported hwc size[%dx%d]!\n",
1115 win->area[0].xsize, win->area[0].ysize);
1117 val = V_HWC_SIZE(hwc_size);
1118 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1120 val = V_HWC_DSP_XST(win->area[0].dsp_stx) |
1121 V_HWC_DSP_YST(win->area[0].dsp_sty);
1122 vop_msk_reg(vop_dev, HWC_DSP_ST, val);
1124 if (win->alpha_en == 1) {
1125 vop_alpha_cfg(dev_drv, win_id);
1127 val = V_WIN2_SRC_ALPHA_EN(0);
1128 vop_msk_reg(vop_dev, HWC_SRC_ALPHA_CTRL, val);
1131 val = V_HWC_EN(win->state);
1132 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1138 static int vop_layer_update_regs(struct vop_device *vop_dev,
1139 struct rk_lcdc_win *win)
1141 struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
1143 if (likely(vop_dev->clk_on)) {
1144 vop_msk_reg(vop_dev, SYS_CTRL,
1145 V_VOP_STANDBY_EN(vop_dev->standby));
1146 if ((win->id == 0) || (win->id == 1))
1147 vop_win_0_1_reg_update(dev_drv, win->id);
1148 else if (win->id == 2)
1149 vop_hwc_reg_update(dev_drv, win->id);
1150 vop_cfg_done(vop_dev);
1153 DBG(2, "%s for lcdc%d\n", __func__, vop_dev->id);
1157 static int __maybe_unused vop_mmu_en(struct rk_lcdc_driver *dev_drv)
1160 struct vop_device *vop_dev =
1161 container_of(dev_drv, struct vop_device, driver);
1163 if (unlikely(!vop_dev->clk_on)) {
1164 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
1167 #if defined(CONFIG_ROCKCHIP_IOMMU)
1168 if (dev_drv->iommu_enabled) {
1169 if (!vop_dev->iommu_status && dev_drv->mmu_dev) {
1170 if (likely(vop_dev->clk_on)) {
1171 val = V_VOP_MMU_EN(1);
1172 vop_msk_reg(vop_dev, SYS_CTRL, val);
1173 val = V_AXI_OUTSTANDING_MAX_NUM(31) |
1174 V_AXI_MAX_OUTSTANDING_EN(1);
1175 vop_msk_reg(vop_dev, SYS_CTRL1, val);
1177 vop_dev->iommu_status = 1;
1178 rockchip_iovmm_activate(dev_drv->dev);
1185 static int vop_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate)
1187 int ret = 0, fps = 0;
1188 struct vop_device *vop_dev =
1189 container_of(dev_drv, struct vop_device, driver);
1190 struct rk_screen *screen = dev_drv->cur_screen;
1191 #ifdef CONFIG_RK_FPGA
1195 ret = clk_set_rate(vop_dev->dclk, screen->mode.pixclock);
1197 dev_err(dev_drv->dev, "set lcdc%d dclk[%d] failed\n",
1198 vop_dev->id, screen->mode.pixclock);
1200 div_u64(1000000000000llu, clk_get_rate(vop_dev->dclk));
1201 vop_dev->driver.pixclock = vop_dev->pixclock;
1203 fps = rk_fb_calc_fps(screen, vop_dev->pixclock);
1204 screen->ft = 1000 / fps;
1205 dev_info(vop_dev->dev, "%s: dclk:%lu>>fps:%d ",
1206 vop_dev->driver.name, clk_get_rate(vop_dev->dclk), fps);
1210 static int vop_config_timing(struct rk_lcdc_driver *dev_drv)
1212 struct vop_device *vop_dev =
1213 container_of(dev_drv, struct vop_device, driver);
1214 struct rk_screen *screen = dev_drv->cur_screen;
1215 u16 hsync_len = screen->mode.hsync_len;
1216 u16 left_margin = screen->mode.left_margin;
1217 u16 right_margin = screen->mode.right_margin;
1218 u16 vsync_len = screen->mode.vsync_len;
1219 u16 upper_margin = screen->mode.upper_margin;
1220 u16 lower_margin = screen->mode.lower_margin;
1221 u16 x_res = screen->mode.xres;
1222 u16 y_res = screen->mode.yres;
1224 u16 h_total, v_total;
1225 u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1227 h_total = hsync_len + left_margin + x_res + right_margin;
1228 v_total = vsync_len + upper_margin + y_res + lower_margin;
1230 val = V_DSP_HS_END(hsync_len) | V_DSP_HTOTAL(h_total);
1231 vop_msk_reg(vop_dev, DSP_HTOTAL_HS_END, val);
1233 val = V_DSP_HACT_END(hsync_len + left_margin + x_res) |
1234 V_DSP_HACT_ST(hsync_len + left_margin);
1235 vop_msk_reg(vop_dev, DSP_HACT_ST_END, val);
1237 if (screen->mode.vmode & FB_VMODE_INTERLACED) {
1238 /* First Field Timing */
1239 val = V_DSP_VS_END(vsync_len) |
1240 V_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1241 lower_margin) + y_res + 1);
1242 vop_msk_reg(vop_dev, DSP_VTOTAL_VS_END, val);
1244 val = V_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1245 V_DSP_VACT_ST(vsync_len + upper_margin);
1246 vop_msk_reg(vop_dev, DSP_VACT_ST_END, val);
1248 /* Second Field Timing */
1249 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1250 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1252 val = V_DSP_VS_ST_F1(vs_st_f1) | V_DSP_VS_END_F1(vs_end_f1);
1253 vop_msk_reg(vop_dev, DSP_VS_ST_END_F1, val);
1255 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1257 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1259 val = V_DSP_VACT_END_F1(vact_end_f1) |
1260 V_DSP_VACT_ST_F1(vact_st_f1);
1261 vop_msk_reg(vop_dev, DSP_VACT_ST_END_F1, val);
1262 vop_msk_reg(vop_dev, DSP_CTRL0,
1263 V_DSP_INTERLACE(1) | V_DSP_FIELD_POL(0));
1265 val = V_DSP_LINE_FLAG_NUM_0(lower_margin ?
1266 vact_end_f1 : vact_end_f1 - 1);
1268 val |= V_DSP_LINE_FLAG_NUM_1(lower_margin ?
1269 vact_end_f1 : vact_end_f1 - 1);
1270 vop_msk_reg(vop_dev, LINE_FLAG, val);
1272 val = V_DSP_VS_END(vsync_len) | V_DSP_VTOTAL(v_total);
1273 vop_msk_reg(vop_dev, DSP_VTOTAL_VS_END, val);
1275 val = V_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1276 V_DSP_VACT_ST(vsync_len + upper_margin);
1277 vop_msk_reg(vop_dev, DSP_VACT_ST_END, val);
1279 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_INTERLACE(0) |
1280 V_DSP_FIELD_POL(0));
1282 val = V_DSP_LINE_FLAG_NUM_0(vsync_len + upper_margin + y_res) |
1283 V_DSP_LINE_FLAG_NUM_1(vsync_len + upper_margin + y_res);
1284 vop_msk_reg(vop_dev, LINE_FLAG, val);
1286 vop_post_cfg(dev_drv);
1291 static void vop_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1293 struct vop_device *vop_dev =
1294 container_of(dev_drv, struct vop_device, driver);
1297 vop_msk_reg(vop_dev, SYS_CTRL, V_OVERLAY_MODE(dev_drv->overlay_mode));
1298 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1299 if (dev_drv->output_color == COLOR_YCBCR) /* bypass */
1300 vop_msk_reg(vop_dev, BCSH_CTRL,
1301 V_BCSH_Y2R_EN(0) | V_BCSH_R2Y_EN(0));
1303 vop_msk_reg(vop_dev, BCSH_CTRL, V_BCSH_Y2R_EN(1) |
1304 V_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1307 /* overlay_mode=VOP_RGB_DOMAIN */
1308 /* bypass --need check,if bcsh close? */
1309 if (dev_drv->output_color == COLOR_RGB) {
1310 bcsh_ctrl = vop_readl(vop_dev, BCSH_CTRL);
1311 if (((bcsh_ctrl & MASK(BCSH_EN)) == 1) ||
1312 (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1313 vop_msk_reg(vop_dev, BCSH_CTRL,
1317 vop_msk_reg(vop_dev, BCSH_CTRL,
1322 vop_msk_reg(vop_dev, BCSH_CTRL,
1324 V_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1330 static int vop_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1331 u16 *yact, int *format, u32 *dsp_addr,
1334 struct vop_device *vop_dev =
1335 container_of(dev_drv, struct vop_device, driver);
1338 spin_lock(&vop_dev->reg_lock);
1340 val = vop_readl(vop_dev, WIN0_ACT_INFO);
1341 *xact = (val & MASK(WIN0_ACT_WIDTH)) + 1;
1342 *yact = ((val & MASK(WIN0_ACT_HEIGHT))>>16) + 1;
1344 val = vop_readl(vop_dev, WIN0_CTRL0);
1345 *format = (val & MASK(WIN0_DATA_FMT)) >> 1;
1346 *ymirror = (val & MASK(WIN0_Y_MIR_EN)) >> 22;
1347 *dsp_addr = vop_readl(vop_dev, WIN0_YRGB_MST);
1349 spin_unlock(&vop_dev->reg_lock);
1354 static int vop_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1355 int format, u16 xact, u16 yact, u16 xvir,
1358 struct vop_device *vop_dev =
1359 container_of(dev_drv, struct vop_device, driver);
1360 int swap = (format == RGB888) ? 1 : 0;
1361 struct rk_lcdc_win *win = dev_drv->win[0];
1364 val = V_WIN0_DATA_FMT(format) | V_WIN0_RB_SWAP(swap) |
1365 V_WIN0_Y_MIR_EN(ymirror);
1366 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
1368 vop_msk_reg(vop_dev, WIN0_VIR, V_WIN0_VIR_STRIDE(xvir));
1369 vop_writel(vop_dev, WIN0_ACT_INFO, V_WIN0_ACT_WIDTH(xact - 1) |
1370 V_WIN0_ACT_HEIGHT(yact - 1));
1372 vop_writel(vop_dev, WIN0_YRGB_MST, rgb_mst);
1374 vop_cfg_done(vop_dev);
1376 if (format == RGB888)
1377 win->area[0].format = BGR888;
1379 win->area[0].format = format;
1381 win->ymirror = ymirror;
1383 win->last_state = 1;
1389 static int lcdc_reset(struct rk_lcdc_driver *dev_drv, bool initscreen)
1391 struct vop_device *vop_dev =
1392 container_of(dev_drv, struct vop_device, driver);
1394 u32 __maybe_unused v;
1396 if (!vop_dev->standby && initscreen && (dev_drv->first_frame != 1)) {
1399 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
1400 vop_msk_reg(vop_dev, WIN1_CTRL0, val);
1402 val = V_WIN2_EN(0) | V_WIN2_MST0_EN(0) |
1404 V_WIN2_MST2_EN(0) | V_WIN2_MST3_EN(0);
1405 vop_msk_reg(vop_dev, WIN2_CTRL0, val);
1406 vop_msk_reg(vop_dev, WIN3_CTRL0, val);
1407 val = V_HDMI_OUT_EN(0);
1408 vop_msk_reg(vop_dev, SYS_CTRL, val);
1409 vop_cfg_done(vop_dev);
1411 vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(1));
1412 writel_relaxed(0, vop_dev->regs + REG_CFG_DONE);
1420 static int vop_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1424 struct vop_device *vop_dev =
1425 container_of(dev_drv, struct vop_device, driver);
1426 struct rk_screen *screen = dev_drv->cur_screen;
1429 if (unlikely(!vop_dev->clk_on)) {
1430 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
1434 if (!vop_dev->standby && initscreen && (dev_drv->first_frame != 1))
1435 flush_kthread_worker(&dev_drv->update_regs_worker);
1437 spin_lock(&vop_dev->reg_lock);
1438 if (likely(vop_dev->clk_on)) {
1439 switch (screen->face) {
1441 if (rockchip_get_cpu_version())
1446 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(0)
1447 | V_PRE_DITHER_DOWN_EN(1);
1450 if (rockchip_get_cpu_version()) {
1453 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(0)
1454 | V_PRE_DITHER_DOWN_EN(1);
1457 dev_err(vop_dev->dev,
1458 "This chip can't supported screen face[%d]\n",
1461 case OUT_YUV_420_10BIT:
1462 if (rockchip_get_cpu_version()) {
1465 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1)
1466 | V_PRE_DITHER_DOWN_EN(0);
1469 dev_err(vop_dev->dev,
1470 "This chip can't supported screen face[%d]\n",
1474 if (rockchip_get_cpu_version()) {
1476 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1)
1477 | V_PRE_DITHER_DOWN_EN(0);
1480 dev_err(vop_dev->dev,
1481 "This chip can't supported screen face[%d]\n",
1485 dev_err(vop_dev->dev, "un supported screen face[%d]!\n",
1490 vop_msk_reg(vop_dev, DSP_CTRL1, val);
1491 switch (screen->type) {
1493 val = V_SW_UV_OFFSET_EN(1) | V_SW_IMD_TVE_DCLK_EN(1) |
1494 V_SW_IMD_TVE_DCLK_EN(1) |
1495 V_SW_IMD_TVE_DCLK_POL(1) |
1496 V_SW_GENLOCK(1) | V_SW_DAC_SEL(1);
1497 if (screen->mode.xres == 720 &&
1498 screen->mode.yres == 576)
1499 val |= V_SW_TVE_MODE(1);
1501 val |= V_SW_TVE_MODE(0);
1502 vop_msk_reg(vop_dev, SYS_CTRL, val);
1505 val = V_HDMI_OUT_EN(1) | V_SW_UV_OFFSET_EN(0);
1506 vop_msk_reg(vop_dev, SYS_CTRL, val);
1509 dev_err(vop_dev->dev, "un supported interface[%d]!\n",
1513 val = V_HDMI_HSYNC_POL(screen->pin_hsync) |
1514 V_HDMI_VSYNC_POL(screen->pin_vsync) |
1515 V_HDMI_DEN_POL(screen->pin_den) |
1516 V_HDMI_DCLK_POL(screen->pin_dclk);
1517 /*hsync vsync den dclk polo,dither */
1518 vop_msk_reg(vop_dev, DSP_CTRL1, val);
1520 if (screen->color_mode == COLOR_RGB)
1521 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1523 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1525 #ifndef CONFIG_RK_FPGA
1528 * writel_relaxed(v, RK_GRF_VIRT + vop_GRF_SOC_CON7);
1529 * move to lvds driver
1531 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
1533 val = V_DSP_OUT_MODE(face) | V_DSP_DCLK_DDR(dclk_ddr) |
1534 V_DSP_BG_SWAP(screen->swap_gb) |
1535 V_DSP_RB_SWAP(screen->swap_rb) |
1536 V_DSP_RG_SWAP(screen->swap_rg) |
1537 V_DSP_DELTA_SWAP(screen->swap_delta) |
1538 V_DSP_DUMMY_SWAP(screen->swap_dumy) | V_DSP_OUT_ZERO(0) |
1539 V_DSP_BLANK_EN(0) | V_DSP_BLACK_EN(0) |
1540 V_DSP_X_MIR_EN(screen->x_mirror) |
1541 V_DSP_Y_MIR_EN(screen->y_mirror);
1542 val |= V_SW_CORE_DCLK_SEL(!!screen->pixelrepeat);
1543 if (screen->mode.vmode & FB_VMODE_INTERLACED)
1544 val |= V_SW_HDMI_CLK_I_SEL(1);
1546 val |= V_SW_HDMI_CLK_I_SEL(0);
1547 vop_msk_reg(vop_dev, DSP_CTRL0, val);
1549 if (screen->mode.vmode & FB_VMODE_INTERLACED)
1550 vop_msk_reg(vop_dev, SYS_CTRL1, V_REG_DONE_FRM(1));
1552 vop_msk_reg(vop_dev, SYS_CTRL1, V_REG_DONE_FRM(0));
1554 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1555 val = V_DSP_OUT_RGB_YUV(1);
1556 vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
1557 val = V_DSP_BG_BLUE(0x200) | V_DSP_BG_GREEN(0x40) |
1558 V_DSP_BG_RED(0x200);
1559 vop_msk_reg(vop_dev, DSP_BG, val);
1561 val = V_DSP_OUT_RGB_YUV(0);
1562 vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
1563 val = V_DSP_BG_BLUE(0) | V_DSP_BG_GREEN(0) |
1565 vop_msk_reg(vop_dev, DSP_BG, val);
1567 dev_drv->output_color = screen->color_mode;
1568 vop_bcsh_path_sel(dev_drv);
1569 vop_config_timing(dev_drv);
1570 vop_cfg_done(vop_dev);
1572 spin_unlock(&vop_dev->reg_lock);
1573 vop_set_dclk(dev_drv, 1);
1574 if (screen->type != SCREEN_HDMI && screen->type != SCREEN_TVOUT &&
1575 dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1576 dev_drv->trsm_ops->enable();
1583 /*enable layer,open:1,enable;0 disable*/
1584 static void vop_layer_enable(struct vop_device *vop_dev,
1585 unsigned int win_id, bool open)
1587 spin_lock(&vop_dev->reg_lock);
1588 if (likely(vop_dev->clk_on) &&
1589 vop_dev->driver.win[win_id]->state != open) {
1591 if (!vop_dev->atv_layer_cnt) {
1592 dev_info(vop_dev->dev,
1593 "wakeup from standby!\n");
1594 vop_dev->standby = 0;
1596 vop_dev->atv_layer_cnt |= (1 << win_id);
1598 if (vop_dev->atv_layer_cnt & (1 << win_id))
1599 vop_dev->atv_layer_cnt &= ~(1 << win_id);
1601 vop_dev->driver.win[win_id]->state = open;
1603 vop_layer_update_regs(vop_dev,
1604 vop_dev->driver.win[win_id]);
1605 vop_cfg_done(vop_dev);
1607 /* if no layer used,disable lcdc */
1608 if (!vop_dev->atv_layer_cnt) {
1609 dev_info(vop_dev->dev,
1610 "no layer is used,go to standby!\n");
1611 vop_dev->standby = 1;
1614 spin_unlock(&vop_dev->reg_lock);
1617 static int vop_enable_irq(struct rk_lcdc_driver *dev_drv)
1619 struct vop_device *vop_dev = container_of(dev_drv,
1620 struct vop_device, driver);
1622 /* struct rk_screen *screen = dev_drv->cur_screen; */
1624 vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, INTR_MASK);
1626 val = INTR_FS | INTR_LINE_FLAG0 | INTR_BUS_ERROR | INTR_LINE_FLAG1 |
1627 INTR_WIN0_EMPTY | INTR_WIN1_EMPTY | INTR_HWC_EMPTY |
1628 INTR_POST_BUF_EMPTY;
1630 vop_mask_writel(vop_dev, INTR_EN0, INTR_MASK, val);
1635 static int vop_open(struct rk_lcdc_driver *dev_drv, int win_id,
1638 struct vop_device *vop_dev =
1639 container_of(dev_drv, struct vop_device, driver);
1641 /* enable clk,when first layer open */
1642 if ((open) && (!vop_dev->atv_layer_cnt)) {
1643 /* rockchip_set_system_status(sys_status); */
1644 vop_pre_init(dev_drv);
1645 vop_clk_enable(vop_dev);
1646 vop_enable_irq(dev_drv);
1647 #if defined(CONFIG_ROCKCHIP_IOMMU)
1648 if (dev_drv->iommu_enabled) {
1649 if (!dev_drv->mmu_dev) {
1651 rk_fb_get_sysmmu_device_by_compatible
1652 (dev_drv->mmu_dts_name);
1653 if (dev_drv->mmu_dev) {
1654 rk_fb_platform_set_sysmmu
1655 (dev_drv->mmu_dev, dev_drv->dev);
1657 dev_err(dev_drv->dev,
1658 "fail get rk iommu device\n");
1664 if ((support_uboot_display() && (vop_dev->prop == PRMRY)))
1665 vop_set_dclk(dev_drv, 0);
1667 vop_load_screen(dev_drv, 1);
1668 if (dev_drv->bcsh.enable)
1669 vop_set_bcsh(dev_drv, 1);
1670 spin_lock(&vop_dev->reg_lock);
1671 spin_unlock(&vop_dev->reg_lock);
1674 if (win_id < ARRAY_SIZE(vop_win))
1675 vop_layer_enable(vop_dev, win_id, open);
1677 dev_err(vop_dev->dev, "invalid win id:%d\n", win_id);
1679 dev_drv->first_frame = 0;
1683 static int win_0_1_display(struct vop_device *vop_dev,
1684 struct rk_lcdc_win *win)
1690 off = win->id * 0x40;
1691 /*win->smem_start + win->y_offset; */
1692 y_addr = win->area[0].smem_start + win->area[0].y_offset;
1693 uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1694 DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
1695 vop_dev->id, win->id, y_addr, uv_addr);
1696 DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
1697 win->area[0].y_offset, win->area[0].c_offset);
1698 spin_lock(&vop_dev->reg_lock);
1699 if (likely(vop_dev->clk_on)) {
1700 win->area[0].y_addr = y_addr;
1701 win->area[0].uv_addr = uv_addr;
1702 vop_writel(vop_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
1703 vop_writel(vop_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
1705 spin_unlock(&vop_dev->reg_lock);
1710 static int hwc_display(struct vop_device *vop_dev, struct rk_lcdc_win *win)
1714 y_addr = win->area[0].smem_start + win->area[0].y_offset;
1715 DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
1716 vop_dev->id, __func__, y_addr);
1717 spin_lock(&vop_dev->reg_lock);
1718 if (likely(vop_dev->clk_on)) {
1719 win->area[0].y_addr = y_addr;
1720 vop_writel(vop_dev, HWC_MST, win->area[0].y_addr);
1722 spin_unlock(&vop_dev->reg_lock);
1727 static int vop_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
1729 struct vop_device *vop_dev =
1730 container_of(dev_drv, struct vop_device, driver);
1731 struct rk_lcdc_win *win = NULL;
1732 struct rk_screen *screen = dev_drv->cur_screen;
1734 win = dev_drv->win[win_id];
1736 dev_err(dev_drv->dev, "screen is null!\n");
1739 if (unlikely(!vop_dev->clk_on)) {
1740 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
1744 win_0_1_display(vop_dev, win);
1745 } else if (win_id == 1) {
1746 win_0_1_display(vop_dev, win);
1747 } else if (win_id == 2) {
1748 hwc_display(vop_dev, win);
1750 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1757 static int vop_cal_scl_fac(struct rk_lcdc_win *win, struct rk_screen *screen)
1767 u32 yrgb_vscalednmult;
1768 u32 yrgb_xscl_factor;
1769 u32 yrgb_yscl_factor;
1770 u8 yrgb_vsd_bil_gt2 = 0;
1771 u8 yrgb_vsd_bil_gt4 = 0;
1777 u32 cbcr_vscalednmult;
1778 u32 cbcr_xscl_factor;
1779 u32 cbcr_yscl_factor;
1780 u8 cbcr_vsd_bil_gt2 = 0;
1781 u8 cbcr_vsd_bil_gt4 = 0;
1784 srcW = win->area[0].xact;
1785 if ((screen->mode.vmode & FB_VMODE_INTERLACED) &&
1786 (win->area[0].yact == 2 * win->area[0].ysize)) {
1787 srcH = win->area[0].yact / 2;
1788 yrgb_vsd_bil_gt2 = 1;
1789 cbcr_vsd_bil_gt2 = 1;
1791 srcH = win->area[0].yact;
1793 dstW = win->area[0].xsize;
1794 dstH = win->area[0].ysize;
1801 if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
1802 pr_err("ERROR: yrgb scale exceed 8,");
1803 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
1804 yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
1806 if (yrgb_srcW < yrgb_dstW)
1807 win->yrgb_hor_scl_mode = SCALE_UP;
1808 else if (yrgb_srcW > yrgb_dstW)
1809 win->yrgb_hor_scl_mode = SCALE_DOWN;
1811 win->yrgb_hor_scl_mode = SCALE_NONE;
1813 if (yrgb_srcH < yrgb_dstH)
1814 win->yrgb_ver_scl_mode = SCALE_UP;
1815 else if (yrgb_srcH > yrgb_dstH)
1816 win->yrgb_ver_scl_mode = SCALE_DOWN;
1818 win->yrgb_ver_scl_mode = SCALE_NONE;
1821 switch (win->area[0].format) {
1824 cbcr_srcW = srcW / 2;
1833 cbcr_srcW = srcW / 2;
1835 cbcr_srcH = srcH / 2;
1856 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
1857 (cbcr_dstH * 8 <= cbcr_srcH)) {
1858 pr_err("ERROR: cbcr scale exceed 8,");
1859 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
1860 cbcr_srcH, cbcr_dstW, cbcr_dstH);
1864 if (cbcr_srcW < cbcr_dstW)
1865 win->cbr_hor_scl_mode = SCALE_UP;
1866 else if (cbcr_srcW > cbcr_dstW)
1867 win->cbr_hor_scl_mode = SCALE_DOWN;
1869 win->cbr_hor_scl_mode = SCALE_NONE;
1871 if (cbcr_srcH < cbcr_dstH)
1872 win->cbr_ver_scl_mode = SCALE_UP;
1873 else if (cbcr_srcH > cbcr_dstH)
1874 win->cbr_ver_scl_mode = SCALE_DOWN;
1876 win->cbr_ver_scl_mode = SCALE_NONE;
1878 /* line buffer mode */
1879 if ((win->area[0].format == YUV422) ||
1880 (win->area[0].format == YUV420) ||
1881 (win->area[0].format == YUV420_NV21) ||
1882 (win->area[0].format == YUV422_A) ||
1883 (win->area[0].format == YUV420_A)) {
1884 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
1885 if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
1887 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
1889 else if (cbcr_dstW > 1280)
1890 win->win_lb_mode = LB_YUV_3840X5;
1892 win->win_lb_mode = LB_YUV_2560X8;
1893 } else { /* SCALE_UP or SCALE_NONE */
1894 if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
1896 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
1898 else if (cbcr_srcW > 1280)
1899 win->win_lb_mode = LB_YUV_3840X5;
1901 win->win_lb_mode = LB_YUV_2560X8;
1904 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
1905 if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
1907 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
1908 else if (yrgb_dstW > 2560)
1909 win->win_lb_mode = LB_RGB_3840X2;
1910 else if (yrgb_dstW > 1920)
1911 win->win_lb_mode = LB_RGB_2560X4;
1912 else if (yrgb_dstW > 1280)
1913 win->win_lb_mode = LB_RGB_1920X5;
1915 win->win_lb_mode = LB_RGB_1280X8;
1916 } else { /* SCALE_UP or SCALE_NONE */
1917 if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
1919 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
1920 else if (yrgb_srcW > 2560)
1921 win->win_lb_mode = LB_RGB_3840X2;
1922 else if (yrgb_srcW > 1920)
1923 win->win_lb_mode = LB_RGB_2560X4;
1924 else if (yrgb_srcW > 1280)
1925 win->win_lb_mode = LB_RGB_1920X5;
1927 win->win_lb_mode = LB_RGB_1280X8;
1930 DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
1932 /* vsd/vsu scale ALGORITHM */
1933 win->yrgb_hsd_mode = SCALE_DOWN_BIL; /*not to specify */
1934 win->cbr_hsd_mode = SCALE_DOWN_BIL; /*not to specify */
1935 win->yrgb_vsd_mode = SCALE_DOWN_BIL; /*not to specify */
1936 win->cbr_vsd_mode = SCALE_DOWN_BIL; /*not to specify */
1937 switch (win->win_lb_mode) {
1942 win->yrgb_vsu_mode = SCALE_UP_BIC;
1943 win->cbr_vsu_mode = SCALE_UP_BIC;
1946 if (win->yrgb_ver_scl_mode != SCALE_NONE)
1947 pr_err("ERROR : not allow yrgb ver scale\n");
1948 if (win->cbr_ver_scl_mode != SCALE_NONE)
1949 pr_err("ERROR : not allow cbcr ver scale\n");
1952 win->yrgb_vsu_mode = SCALE_UP_BIL;
1953 win->cbr_vsu_mode = SCALE_UP_BIL;
1956 pr_info("%s:un supported win_lb_mode:%d\n",
1957 __func__, win->win_lb_mode);
1961 if (win->ymirror == 1)
1962 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
1963 if (screen->mode.vmode & FB_VMODE_INTERLACED) {
1964 /* interlace mode must bill */
1965 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
1966 win->cbr_vsd_mode = SCALE_DOWN_BIL;
1968 if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
1969 (win->area[0].fbdc_en == 1)) {
1970 /* in this pattern,use bil mode,not support souble scd,
1971 use avg mode, support double scd, but aclk should be
1972 bigger than dclk,aclk>>dclk */
1973 if (yrgb_srcH >= 2 * yrgb_dstH) {
1974 pr_err("ERROR : fbdc mode,not support y scale down:");
1975 pr_err("srcH[%d] > 2 *dstH[%d]\n",
1976 yrgb_srcH, yrgb_dstH);
1979 DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
1980 win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
1981 win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
1985 /* (1.1)YRGB HOR SCALE FACTOR */
1986 switch (win->yrgb_hor_scl_mode) {
1988 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
1991 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
1994 switch (win->yrgb_hsd_mode) {
1995 case SCALE_DOWN_BIL:
1997 GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
1999 case SCALE_DOWN_AVG:
2001 GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2004 pr_info("%s:un supported yrgb_hsd_mode:%d\n", __func__,
2005 win->yrgb_hsd_mode);
2010 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2011 __func__, win->yrgb_hor_scl_mode);
2015 /* (1.2)YRGB VER SCALE FACTOR */
2016 switch (win->yrgb_ver_scl_mode) {
2018 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2021 switch (win->yrgb_vsu_mode) {
2024 GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2027 if (yrgb_srcH < 3) {
2028 pr_err("yrgb_srcH should be");
2029 pr_err(" greater than 3 !!!\n");
2031 yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2035 pr_info("%s:un support yrgb_vsu_mode:%d\n",
2036 __func__, win->yrgb_vsu_mode);
2041 switch (win->yrgb_vsd_mode) {
2042 case SCALE_DOWN_BIL:
2044 vop_get_hard_ware_vskiplines(yrgb_srcH, yrgb_dstH);
2046 GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2048 if (yrgb_yscl_factor >= 0x2000) {
2049 pr_err("yrgb_yscl_factor should less 0x2000");
2050 pr_err("yrgb_yscl_factor=%4x;\n",
2053 if (yrgb_vscalednmult == 4) {
2054 yrgb_vsd_bil_gt4 = 1;
2055 yrgb_vsd_bil_gt2 = 0;
2056 } else if (yrgb_vscalednmult == 2) {
2057 yrgb_vsd_bil_gt4 = 0;
2058 yrgb_vsd_bil_gt2 = 1;
2060 yrgb_vsd_bil_gt4 = 0;
2061 yrgb_vsd_bil_gt2 = 0;
2064 case SCALE_DOWN_AVG:
2065 yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2069 pr_info("%s:un support yrgb_vsd_mode:%d\n",
2070 __func__, win->yrgb_vsd_mode);
2072 } /*win->yrgb_vsd_mode */
2075 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2076 __func__, win->yrgb_ver_scl_mode);
2079 win->scale_yrgb_x = yrgb_xscl_factor;
2080 win->scale_yrgb_y = yrgb_yscl_factor;
2081 win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2082 win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2083 DBG(1, "yrgb:h_fac=%d, V_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2084 yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2086 /*(2.1)CBCR HOR SCALE FACTOR */
2087 switch (win->cbr_hor_scl_mode) {
2089 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2092 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2095 switch (win->cbr_hsd_mode) {
2096 case SCALE_DOWN_BIL:
2098 GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2100 case SCALE_DOWN_AVG:
2102 GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2105 pr_info("%s:un support cbr_hsd_mode:%d\n",
2106 __func__, win->cbr_hsd_mode);
2111 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2112 __func__, win->cbr_hor_scl_mode);
2114 } /*win->cbr_hor_scl_mode */
2116 /* (2.2)CBCR VER SCALE FACTOR */
2117 switch (win->cbr_ver_scl_mode) {
2119 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2122 switch (win->cbr_vsu_mode) {
2125 GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2128 if (cbcr_srcH < 3) {
2129 pr_err("cbcr_srcH should be ");
2130 pr_err("greater than 3 !!!\n");
2132 cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2136 pr_info("%s:un support cbr_vsu_mode:%d\n",
2137 __func__, win->cbr_vsu_mode);
2142 switch (win->cbr_vsd_mode) {
2143 case SCALE_DOWN_BIL:
2145 vop_get_hard_ware_vskiplines(cbcr_srcH, cbcr_dstH);
2147 GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2149 if (cbcr_yscl_factor >= 0x2000) {
2150 pr_err("cbcr_yscl_factor should be less ");
2151 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2155 if (cbcr_vscalednmult == 4) {
2156 cbcr_vsd_bil_gt4 = 1;
2157 cbcr_vsd_bil_gt2 = 0;
2158 } else if (cbcr_vscalednmult == 2) {
2159 cbcr_vsd_bil_gt4 = 0;
2160 cbcr_vsd_bil_gt2 = 1;
2162 cbcr_vsd_bil_gt4 = 0;
2163 cbcr_vsd_bil_gt2 = 0;
2166 case SCALE_DOWN_AVG:
2167 cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2171 pr_info("%s:un support cbr_vsd_mode:%d\n",
2172 __func__, win->cbr_vsd_mode);
2177 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2178 __func__, win->cbr_ver_scl_mode);
2181 win->scale_cbcr_x = cbcr_xscl_factor;
2182 win->scale_cbcr_y = cbcr_yscl_factor;
2183 win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2184 win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2186 DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2187 cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2191 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2192 struct rk_lcdc_win_area *area)
2196 if (screen->x_mirror && mirror_en)
2197 pr_err("not support both win and global mirror\n");
2199 if ((!mirror_en) && (!screen->x_mirror))
2200 pos = area->xpos + screen->mode.left_margin +
2201 screen->mode.hsync_len;
2203 pos = screen->mode.xres - area->xpos -
2204 area->xsize + screen->mode.left_margin +
2205 screen->mode.hsync_len;
2210 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2211 struct rk_lcdc_win_area *area)
2215 if (screen->y_mirror && mirror_en)
2216 pr_err("not support both win and global mirror\n");
2218 if ((!mirror_en) && (!screen->y_mirror))
2219 pos = area->ypos + screen->mode.upper_margin +
2220 screen->mode.vsync_len;
2222 pos = screen->mode.yres - area->ypos -
2223 area->ysize + screen->mode.upper_margin +
2224 screen->mode.vsync_len;
2229 static int win_0_1_set_par(struct vop_device *vop_dev,
2230 struct rk_screen *screen, struct rk_lcdc_win *win)
2232 u32 xact, yact, xvir, yvir, xpos, ypos;
2233 u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2234 char fmt[9] = "NULL";
2236 xpos = dsp_x_pos(win->xmirror, screen, &win->area[0]);
2237 ypos = dsp_y_pos(win->ymirror, screen, &win->area[0]);
2239 spin_lock(&vop_dev->reg_lock);
2240 if (likely(vop_dev->clk_on)) {
2241 vop_cal_scl_fac(win, screen);
2242 switch (win->area[0].format) {
2247 win->area[0].fbdc_fmt_cfg = 0x05;
2253 win->area[0].fbdc_fmt_cfg = 0x0c;
2259 win->area[0].fbdc_fmt_cfg = 0x0c;
2265 win->area[0].fbdc_fmt_cfg = 0x3a;
2330 dev_err(vop_dev->dev, "%s:unsupport format[%d]!\n",
2331 __func__, win->area[0].format);
2334 win->area[0].fmt_cfg = fmt_cfg;
2335 win->area[0].swap_rb = swap_rb;
2336 win->area[0].swap_uv = swap_uv;
2337 win->area[0].dsp_stx = xpos;
2338 win->area[0].dsp_sty = ypos;
2339 xact = win->area[0].xact;
2340 yact = win->area[0].yact;
2341 xvir = win->area[0].xvir;
2342 yvir = win->area[0].yvir;
2344 vop_win_0_1_reg_update(&vop_dev->driver, win->id);
2345 spin_unlock(&vop_dev->reg_lock);
2347 DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2348 vop_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2349 xact, yact, win->area[0].xsize);
2350 DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2351 win->area[0].ysize, xvir, yvir, xpos, ypos);
2356 static int hwc_set_par(struct vop_device *vop_dev,
2357 struct rk_screen *screen, struct rk_lcdc_win *win)
2359 u32 xact, yact, xvir, yvir, xpos, ypos;
2360 u8 fmt_cfg = 0, swap_rb;
2361 char fmt[9] = "NULL";
2363 xpos = win->area[0].xpos + screen->mode.left_margin +
2364 screen->mode.hsync_len;
2365 ypos = win->area[0].ypos + screen->mode.upper_margin +
2366 screen->mode.vsync_len;
2368 spin_lock(&vop_dev->reg_lock);
2369 if (likely(vop_dev->clk_on)) {
2370 switch (win->area[0].format) {
2389 dev_err(vop_dev->dev, "%s:un supported format[%d]!\n",
2390 __func__, win->area[0].format);
2393 win->area[0].fmt_cfg = fmt_cfg;
2394 win->area[0].swap_rb = swap_rb;
2395 win->area[0].dsp_stx = xpos;
2396 win->area[0].dsp_sty = ypos;
2397 xact = win->area[0].xact;
2398 yact = win->area[0].yact;
2399 xvir = win->area[0].xvir;
2400 yvir = win->area[0].yvir;
2402 vop_hwc_reg_update(&vop_dev->driver, 2);
2403 spin_unlock(&vop_dev->reg_lock);
2405 DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2406 vop_dev->id, __func__, get_format_string(win->area[0].format, fmt),
2407 xact, yact, win->area[0].xsize);
2408 DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2409 win->area[0].ysize, xvir, yvir, xpos, ypos);
2413 static int vop_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
2415 struct vop_device *vop_dev =
2416 container_of(dev_drv, struct vop_device, driver);
2417 struct rk_lcdc_win *win = NULL;
2418 struct rk_screen *screen = dev_drv->cur_screen;
2420 if (unlikely(!vop_dev->clk_on)) {
2421 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
2424 win = dev_drv->win[win_id];
2427 win_0_1_set_par(vop_dev, screen, win);
2430 win_0_1_set_par(vop_dev, screen, win);
2433 hwc_set_par(vop_dev, screen, win);
2436 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2442 static int vop_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2443 unsigned long arg, int win_id)
2445 struct vop_device *vop_dev =
2446 container_of(dev_drv, struct vop_device, driver);
2448 void __user *argp = (void __user *)arg;
2449 struct color_key_cfg clr_key_cfg;
2452 case RK_FBIOGET_PANEL_SIZE:
2453 panel_size[0] = vop_dev->screen->mode.xres;
2454 panel_size[1] = vop_dev->screen->mode.yres;
2455 if (copy_to_user(argp, panel_size, 8))
2458 case RK_FBIOPUT_COLOR_KEY_CFG:
2459 if (copy_from_user(&clr_key_cfg, argp,
2460 sizeof(struct color_key_cfg)))
2462 vop_clr_key_cfg(dev_drv);
2463 vop_writel(vop_dev, WIN0_COLOR_KEY,
2464 clr_key_cfg.win0_color_key_cfg);
2465 vop_writel(vop_dev, WIN1_COLOR_KEY,
2466 clr_key_cfg.win1_color_key_cfg);
2475 static int vop_get_backlight_device(struct rk_lcdc_driver *dev_drv)
2477 struct vop_device *vop_dev = container_of(dev_drv,
2478 struct vop_device, driver);
2479 struct device_node *backlight;
2480 struct property *prop;
2481 u32 *brightness_levels;
2482 u32 length, max, last;
2484 if (vop_dev->backlight)
2486 backlight = of_parse_phandle(vop_dev->dev->of_node, "backlight", 0);
2488 vop_dev->backlight = of_find_backlight_by_node(backlight);
2489 if (!vop_dev->backlight)
2490 dev_info(vop_dev->dev, "No find backlight device\n");
2492 dev_info(vop_dev->dev, "No find backlight device node\n");
2494 prop = of_find_property(backlight, "brightness-levels", &length);
2497 max = length / sizeof(u32);
2499 brightness_levels = kmalloc(256, GFP_KERNEL);
2500 if (brightness_levels)
2503 if (!of_property_read_u32_array(backlight, "brightness-levels",
2504 brightness_levels, max)) {
2505 if (brightness_levels[0] > brightness_levels[last])
2506 dev_drv->cabc_pwm_pol = 1;/*negative*/
2508 dev_drv->cabc_pwm_pol = 0;/*positive*/
2510 dev_info(vop_dev->dev,
2511 "Can not read brightness-levels value\n");
2514 kfree(brightness_levels);
2519 static int vop_early_suspend(struct rk_lcdc_driver *dev_drv)
2521 struct vop_device *vop_dev =
2522 container_of(dev_drv, struct vop_device, driver);
2524 if (dev_drv->suspend_flag)
2527 dev_drv->suspend_flag = 1;
2529 flush_kthread_worker(&dev_drv->update_regs_worker);
2531 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
2532 dev_drv->trsm_ops->disable();
2534 if (likely(vop_dev->clk_on)) {
2535 spin_lock(&vop_dev->reg_lock);
2536 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLANK_EN(1));
2537 vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, INTR_MASK);
2538 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_OUT_ZERO(1));
2539 vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(1));
2540 vop_cfg_done(vop_dev);
2542 if (dev_drv->iommu_enabled && dev_drv->mmu_dev) {
2544 rockchip_iovmm_deactivate(dev_drv->dev);
2547 spin_unlock(&vop_dev->reg_lock);
2550 vop_clk_disable(vop_dev);
2551 rk_disp_pwr_disable(dev_drv);
2556 static int vop_early_resume(struct rk_lcdc_driver *dev_drv)
2558 struct vop_device *vop_dev =
2559 container_of(dev_drv, struct vop_device, driver);
2561 if (!dev_drv->suspend_flag)
2563 rk_disp_pwr_enable(dev_drv);
2565 vop_clk_enable(vop_dev);
2566 memcpy(vop_dev->regs, vop_dev->regsbak, vop_dev->len);
2568 spin_lock(&vop_dev->reg_lock);
2570 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_OUT_ZERO(0));
2571 vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(0));
2572 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLANK_EN(0));
2573 vop_cfg_done(vop_dev);
2574 spin_unlock(&vop_dev->reg_lock);
2576 if (dev_drv->iommu_enabled && dev_drv->mmu_dev) {
2577 /* win address maybe effect after next frame start,
2578 * but mmu maybe effect right now, so we delay 50ms
2581 rockchip_iovmm_activate(dev_drv->dev);
2584 dev_drv->suspend_flag = 0;
2586 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2587 dev_drv->trsm_ops->enable();
2592 static int vop_blank(struct rk_lcdc_driver *dev_drv, int win_id, int blank_mode)
2594 switch (blank_mode) {
2595 case FB_BLANK_UNBLANK:
2596 vop_early_resume(dev_drv);
2598 case FB_BLANK_NORMAL:
2599 vop_early_suspend(dev_drv);
2602 vop_early_suspend(dev_drv);
2606 dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
2611 static int vop_get_win_state(struct rk_lcdc_driver *dev_drv,
2612 int win_id, int area_id)
2614 struct vop_device *vop_dev =
2615 container_of(dev_drv, struct vop_device, driver);
2616 u32 area_status = 0, state = 0;
2620 area_status = vop_read_bit(vop_dev, WIN0_CTRL0, V_WIN0_EN(0));
2623 area_status = vop_read_bit(vop_dev, WIN1_CTRL0, V_WIN1_EN(0));
2626 area_status = vop_read_bit(vop_dev, HWC_CTRL0, V_HWC_EN(0));
2629 pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n",
2630 __func__, win_id, area_id);
2634 state = (area_status > 0) ? 1 : 0;
2638 static int vop_get_area_num(struct rk_lcdc_driver *dev_drv,
2639 unsigned int *area_support)
2641 area_support[0] = 1;
2642 area_support[1] = 1;
2647 /*overlay will be do at regupdate*/
2648 static int vop_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, bool set)
2650 struct vop_device *vop_dev =
2651 container_of(dev_drv, struct vop_device, driver);
2652 struct rk_lcdc_win *win = NULL;
2655 int z_order_num = 0;
2656 int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
2659 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
2660 win = dev_drv->win[i];
2661 if (win->state == 1)
2664 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
2665 win = dev_drv->win[i];
2666 if (win->state == 0)
2667 win->z_order = z_order_num++;
2668 switch (win->z_order) {
2670 layer0_sel = win->id;
2673 layer1_sel = win->id;
2676 layer2_sel = win->id;
2679 layer3_sel = win->id;
2686 layer0_sel = swap % 10;
2687 layer1_sel = swap / 10 % 10;
2688 layer2_sel = swap / 100 % 10;
2689 layer3_sel = swap / 1000;
2692 spin_lock(&vop_dev->reg_lock);
2693 if (vop_dev->clk_on) {
2695 val = V_DSP_LAYER0_SEL(layer0_sel) |
2696 V_DSP_LAYER1_SEL(layer1_sel) |
2697 V_DSP_LAYER2_SEL(layer2_sel) |
2698 V_DSP_LAYER3_SEL(layer3_sel);
2699 vop_msk_reg(vop_dev, DSP_CTRL1, val);
2701 layer0_sel = vop_read_bit(vop_dev, DSP_CTRL1,
2702 V_DSP_LAYER0_SEL(0));
2703 layer1_sel = vop_read_bit(vop_dev, DSP_CTRL1,
2704 V_DSP_LAYER1_SEL(0));
2705 layer2_sel = vop_read_bit(vop_dev, DSP_CTRL1,
2706 V_DSP_LAYER2_SEL(0));
2707 layer3_sel = vop_read_bit(vop_dev, DSP_CTRL1,
2708 V_DSP_LAYER3_SEL(0));
2709 ovl = layer3_sel * 1000 + layer2_sel * 100 +
2710 layer1_sel * 10 + layer0_sel;
2715 spin_unlock(&vop_dev->reg_lock);
2720 static char *vop_format_to_string(int format, char *fmt)
2727 strcpy(fmt, "ARGB888");
2730 strcpy(fmt, "RGB888");
2733 strcpy(fmt, "RGB565");
2736 strcpy(fmt, "YCbCr420");
2739 strcpy(fmt, "YCbCr422");
2742 strcpy(fmt, "YCbCr444");
2745 strcpy(fmt, "invalid\n");
2750 static ssize_t vop_get_disp_info(struct rk_lcdc_driver *dev_drv,
2751 char *buf, int win_id)
2753 struct vop_device *vop_dev =
2754 container_of(dev_drv, struct vop_device, driver);
2755 struct rk_screen *screen = dev_drv->cur_screen;
2756 u16 hsync_len = screen->mode.hsync_len;
2757 u16 left_margin = screen->mode.left_margin;
2758 u16 vsync_len = screen->mode.vsync_len;
2759 u16 upper_margin = screen->mode.upper_margin;
2760 u32 h_pw_bp = hsync_len + left_margin;
2761 u32 v_pw_bp = vsync_len + upper_margin;
2763 char format_w0[9] = "NULL";
2764 char format_w1[9] = "NULL";
2766 u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
2767 u32 y_factor, uv_factor;
2768 u8 layer0_sel, layer1_sel;
2769 u8 w0_state, w1_state;
2771 u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
2772 u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
2773 u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
2774 u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
2775 u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
2776 u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
2781 dclk_freq = screen->mode.pixclock;
2782 /*vop_reg_dump(dev_drv); */
2784 spin_lock(&vop_dev->reg_lock);
2785 if (vop_dev->clk_on) {
2786 zorder = vop_readl(vop_dev, DSP_CTRL1);
2787 layer0_sel = (zorder & MASK(DSP_LAYER0_SEL)) >> 8;
2788 layer1_sel = (zorder & MASK(DSP_LAYER1_SEL)) >> 10;
2790 win_ctrl = vop_readl(vop_dev, WIN0_CTRL0);
2791 w0_state = win_ctrl & MASK(WIN0_EN);
2792 fmt_id = (win_ctrl & MASK(WIN0_DATA_FMT)) >> 1;
2793 vop_format_to_string(fmt_id, format_w0);
2794 vir_info = vop_readl(vop_dev, WIN0_VIR);
2795 act_info = vop_readl(vop_dev, WIN0_ACT_INFO);
2796 dsp_info = vop_readl(vop_dev, WIN0_DSP_INFO);
2797 dsp_st = vop_readl(vop_dev, WIN0_DSP_ST);
2798 y_factor = vop_readl(vop_dev, WIN0_SCL_FACTOR_YRGB);
2799 uv_factor = vop_readl(vop_dev, WIN0_SCL_FACTOR_CBR);
2800 w0_vir_y = vir_info & MASK(WIN0_VIR_STRIDE);
2801 w0_vir_uv = (vir_info & MASK(WIN0_VIR_STRIDE_UV)) >> 16;
2802 w0_act_x = (act_info & MASK(WIN0_ACT_WIDTH)) + 1;
2803 w0_act_y = ((act_info & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1;
2804 w0_dsp_x = (dsp_info & MASK(WIN0_DSP_WIDTH)) + 1;
2805 w0_dsp_y = ((dsp_info & MASK(WIN0_DSP_HEIGHT)) >> 16) + 1;
2807 w0_st_x = dsp_st & MASK(WIN0_DSP_XST);
2808 w0_st_y = (dsp_st & MASK(WIN0_DSP_YST)) >> 16;
2810 w0_y_h_fac = y_factor & MASK(WIN0_HS_FACTOR_YRGB);
2811 w0_y_v_fac = (y_factor & MASK(WIN0_VS_FACTOR_YRGB)) >> 16;
2812 w0_uv_h_fac = uv_factor & MASK(WIN0_HS_FACTOR_CBR);
2813 w0_uv_v_fac = (uv_factor & MASK(WIN0_VS_FACTOR_CBR)) >> 16;
2816 win_ctrl = vop_readl(vop_dev, WIN1_CTRL0);
2817 w1_state = win_ctrl & MASK(WIN1_EN);
2818 fmt_id = (win_ctrl & MASK(WIN1_DATA_FMT)) >> 1;
2819 vop_format_to_string(fmt_id, format_w1);
2820 vir_info = vop_readl(vop_dev, WIN1_VIR);
2821 act_info = vop_readl(vop_dev, WIN1_ACT_INFO);
2822 dsp_info = vop_readl(vop_dev, WIN1_DSP_INFO);
2823 dsp_st = vop_readl(vop_dev, WIN1_DSP_ST);
2824 y_factor = vop_readl(vop_dev, WIN1_SCL_FACTOR_YRGB);
2825 uv_factor = vop_readl(vop_dev, WIN1_SCL_FACTOR_CBR);
2826 w1_vir_y = vir_info & MASK(WIN1_VIR_STRIDE);
2827 w1_vir_uv = (vir_info & MASK(WIN1_VIR_STRIDE_UV)) >> 16;
2828 w1_act_x = (act_info & MASK(WIN1_ACT_WIDTH)) + 1;
2829 w1_act_y = ((act_info & MASK(WIN1_ACT_HEIGHT)) >> 16) + 1;
2830 w1_dsp_x = (dsp_info & MASK(WIN1_DSP_WIDTH)) + 1;
2831 w1_dsp_y = ((dsp_info & MASK(WIN1_DSP_HEIGHT)) >> 16) + 1;
2833 w1_st_x = dsp_st & MASK(WIN1_DSP_XST);
2834 w1_st_y = (dsp_st & MASK(WIN1_DSP_YST)) >> 16;
2836 w1_y_h_fac = y_factor & MASK(WIN1_HS_FACTOR_YRGB);
2837 w1_y_v_fac = (y_factor & MASK(WIN1_VS_FACTOR_YRGB)) >> 16;
2838 w1_uv_h_fac = uv_factor & MASK(WIN1_HS_FACTOR_CBR);
2839 w1_uv_v_fac = (uv_factor & MASK(WIN1_VS_FACTOR_CBR)) >> 16;
2841 spin_unlock(&vop_dev->reg_lock);
2844 spin_unlock(&vop_dev->reg_lock);
2845 size += snprintf(dsp_buf, 80,
2846 "z-order:\n win[%d]\n win[%d]\n",
2847 layer1_sel, layer0_sel);
2848 strcat(buf, dsp_buf);
2849 memset(dsp_buf, 0, sizeof(dsp_buf));
2851 size += snprintf(dsp_buf, 80,
2852 "win0:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,",
2853 w0_state, format_w0, w0_vir_y, w0_vir_uv);
2854 strcat(buf, dsp_buf);
2855 memset(dsp_buf, 0, sizeof(dsp_buf));
2857 size += snprintf(dsp_buf, 80,
2858 " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n",
2859 w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
2860 strcat(buf, dsp_buf);
2861 memset(dsp_buf, 0, sizeof(dsp_buf));
2863 size += snprintf(dsp_buf, 80,
2864 " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
2865 w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
2866 strcat(buf, dsp_buf);
2867 memset(dsp_buf, 0, sizeof(dsp_buf));
2869 size += snprintf(dsp_buf, 80,
2870 "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n",
2871 w0_uv_h_fac, w0_uv_v_fac, vop_readl(vop_dev, WIN0_YRGB_MST),
2872 vop_readl(vop_dev, WIN0_CBR_MST));
2873 strcat(buf, dsp_buf);
2874 memset(dsp_buf, 0, sizeof(dsp_buf));
2877 size += snprintf(dsp_buf, 80,
2878 "win1:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,",
2879 w1_state, format_w1, w1_vir_y, w1_vir_uv);
2880 strcat(buf, dsp_buf);
2881 memset(dsp_buf, 0, sizeof(dsp_buf));
2883 size += snprintf(dsp_buf, 80,
2884 " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n",
2885 w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
2886 strcat(buf, dsp_buf);
2887 memset(dsp_buf, 0, sizeof(dsp_buf));
2889 size += snprintf(dsp_buf, 80,
2890 " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
2891 w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
2892 strcat(buf, dsp_buf);
2893 memset(dsp_buf, 0, sizeof(dsp_buf));
2895 size += snprintf(dsp_buf, 80,
2896 "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n",
2897 w1_uv_h_fac, w1_uv_v_fac, vop_readl(vop_dev, WIN1_YRGB_MST),
2898 vop_readl(vop_dev, WIN1_CBR_MST));
2899 strcat(buf, dsp_buf);
2900 memset(dsp_buf, 0, sizeof(dsp_buf));
2905 static int vop_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, bool set)
2907 struct vop_device *vop_dev =
2908 container_of(dev_drv, struct vop_device, driver);
2909 struct rk_screen *screen = dev_drv->cur_screen;
2914 u32 x_total, y_total;
2918 dev_info(dev_drv->dev, "unsupport set fps=0\n");
2921 ft = div_u64(1000000000000llu, fps);
2923 screen->mode.upper_margin + screen->mode.lower_margin +
2924 screen->mode.yres + screen->mode.vsync_len;
2926 screen->mode.left_margin + screen->mode.right_margin +
2927 screen->mode.xres + screen->mode.hsync_len;
2928 dev_drv->pixclock = div_u64(ft, x_total * y_total);
2929 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
2930 ret = clk_set_rate(vop_dev->dclk, dotclk);
2933 pixclock = div_u64(1000000000000llu, clk_get_rate(vop_dev->dclk));
2934 vop_dev->pixclock = pixclock;
2935 dev_drv->pixclock = vop_dev->pixclock;
2936 fps = rk_fb_calc_fps(screen, pixclock);
2937 screen->ft = 1000 / fps; /*one frame time in ms */
2940 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
2941 clk_get_rate(vop_dev->dclk), fps);
2946 static int vop_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
2948 mutex_lock(&dev_drv->fb_win_id_mutex);
2949 if (order == FB_DEFAULT_ORDER)
2950 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
2951 dev_drv->fb4_win_id = order / 10000;
2952 dev_drv->fb3_win_id = (order / 1000) % 10;
2953 dev_drv->fb2_win_id = (order / 100) % 10;
2954 dev_drv->fb1_win_id = (order / 10) % 10;
2955 dev_drv->fb0_win_id = order % 10;
2956 mutex_unlock(&dev_drv->fb_win_id_mutex);
2961 static int vop_get_win_id(struct rk_lcdc_driver *dev_drv, const char *id)
2965 mutex_lock(&dev_drv->fb_win_id_mutex);
2966 if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
2967 win_id = dev_drv->fb0_win_id;
2968 else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
2969 win_id = dev_drv->fb1_win_id;
2970 else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
2971 win_id = dev_drv->fb2_win_id;
2972 else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
2973 win_id = dev_drv->fb3_win_id;
2974 else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
2975 win_id = dev_drv->fb4_win_id;
2976 mutex_unlock(&dev_drv->fb_win_id_mutex);
2981 static int vop_config_done(struct rk_lcdc_driver *dev_drv)
2983 struct vop_device *vop_dev =
2984 container_of(dev_drv, struct vop_device, driver);
2987 struct rk_lcdc_win *win = NULL;
2989 spin_lock(&vop_dev->reg_lock);
2990 vop_post_cfg(dev_drv);
2991 vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(vop_dev->standby));
2992 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
2993 win = dev_drv->win[i];
2994 if ((win->state == 0) && (win->last_state == 1)) {
2998 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
3002 vop_msk_reg(vop_dev, WIN1_CTRL0, val);
3006 vop_msk_reg(vop_dev, HWC_CTRL0, val);
3012 win->last_state = win->state;
3014 vop_cfg_done(vop_dev);
3015 spin_unlock(&vop_dev->reg_lock);
3019 static int vop_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3021 struct vop_device *vop_dev =
3022 container_of(dev_drv, struct vop_device, driver);
3023 spin_lock(&vop_dev->reg_lock);
3024 vop_msk_reg(vop_dev, SYS_CTRL, V_DIRECT_PATH_EN(open));
3025 vop_cfg_done(vop_dev);
3026 spin_unlock(&vop_dev->reg_lock);
3030 static int vop_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3032 struct vop_device *vop_dev = container_of(dev_drv,
3033 struct vop_device, driver);
3034 spin_lock(&vop_dev->reg_lock);
3035 vop_msk_reg(vop_dev, SYS_CTRL, V_DIRECT_PATH_LAYER_SEL(win_id));
3036 vop_cfg_done(vop_dev);
3037 spin_unlock(&vop_dev->reg_lock);
3041 static int vop_dpi_status(struct rk_lcdc_driver *dev_drv)
3043 struct vop_device *vop_dev =
3044 container_of(dev_drv, struct vop_device, driver);
3047 spin_lock(&vop_dev->reg_lock);
3048 ovl = vop_read_bit(vop_dev, SYS_CTRL, V_DIRECT_PATH_EN(0));
3049 spin_unlock(&vop_dev->reg_lock);
3053 static int vop_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv, int enable)
3055 struct vop_device *vop_dev =
3056 container_of(dev_drv, struct vop_device, driver);
3058 enable_irq(vop_dev->irq);
3060 disable_irq(vop_dev->irq);
3064 int vop_poll_vblank(struct rk_lcdc_driver *dev_drv)
3066 struct vop_device *vop_dev =
3067 container_of(dev_drv, struct vop_device, driver);
3071 if (vop_dev->clk_on && (!dev_drv->suspend_flag)) {
3072 int_reg = vop_readl(vop_dev, INTR_STATUS0);
3073 if (int_reg & INTR_LINE_FLAG0) {
3074 vop_dev->driver.frame_time.last_framedone_t =
3075 vop_dev->driver.frame_time.framedone_t;
3076 vop_dev->driver.frame_time.framedone_t = cpu_clock(0);
3077 vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_LINE_FLAG0,
3079 ret = RK_LF_STATUS_FC;
3081 ret = RK_LF_STATUS_FR;
3084 ret = RK_LF_STATUS_NC;
3090 static int vop_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3091 unsigned int dsp_addr[][4])
3093 struct vop_device *vop_dev =
3094 container_of(dev_drv, struct vop_device, driver);
3095 spin_lock(&vop_dev->reg_lock);
3096 if (vop_dev->clk_on) {
3097 dsp_addr[0][0] = vop_readl(vop_dev, WIN0_YRGB_MST);
3098 dsp_addr[1][0] = vop_readl(vop_dev, WIN1_YRGB_MST);
3099 dsp_addr[2][0] = vop_readl(vop_dev, HWC_MST);
3101 spin_unlock(&vop_dev->reg_lock);
3105 static u32 pwm_period_hpr, pwm_duty_lpr;
3107 int vop_update_pwm(int bl_pwm_period, int bl_pwm_duty)
3109 pwm_period_hpr = bl_pwm_period;
3110 pwm_duty_lpr = bl_pwm_duty;
3111 /*pr_info("bl_pwm_period_hpr = 0x%x, bl_pwm_duty_lpr = 0x%x\n",
3112 bl_pwm_period, bl_pwm_duty);*/
3118 sin_hue = sin(a)*256 +0x100;
3119 cos_hue = cos(a)*256;
3121 sin_hue = sin(a)*256;
3122 cos_hue = cos(a)*256;
3124 static int vop_get_bcsh_hue(struct rk_lcdc_driver *dev_drv, bcsh_hue_mode mode)
3127 struct vop_device *vop_dev =
3128 container_of(dev_drv, struct vop_device, driver);
3131 spin_lock(&vop_dev->reg_lock);
3132 if (vop_dev->clk_on) {
3133 val = vop_readl(vop_dev, BCSH_H);
3136 val &= MASK(SIN_HUE);
3139 val &= MASK(COS_HUE);
3146 spin_unlock(&vop_dev->reg_lock);
3153 static int vop_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3154 int sin_hue, int cos_hue)
3156 struct vop_device *vop_dev =
3157 container_of(dev_drv, struct vop_device, driver);
3160 spin_lock(&vop_dev->reg_lock);
3161 if (vop_dev->clk_on) {
3162 val = V_SIN_HUE(sin_hue) | V_COS_HUE(cos_hue);
3163 vop_msk_reg(vop_dev, BCSH_H, val);
3164 vop_cfg_done(vop_dev);
3166 spin_unlock(&vop_dev->reg_lock);
3171 static int vop_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
3172 bcsh_bcs_mode mode, int value)
3174 struct vop_device *vop_dev =
3175 container_of(dev_drv, struct vop_device, driver);
3178 spin_lock(&vop_dev->reg_lock);
3179 if (vop_dev->clk_on) {
3182 /*from 0 to 255,typical is 128 */
3185 else if (value >= 0x80)
3186 value = value - 0x80;
3187 val = V_BRIGHTNESS(value);
3190 /*from 0 to 510,typical is 256 */
3191 val = V_CONTRAST(value);
3194 /*from 0 to 1015,typical is 256 */
3195 val = V_SAT_CON(value);
3200 vop_msk_reg(vop_dev, BCSH_BCS, val);
3201 vop_cfg_done(vop_dev);
3203 spin_unlock(&vop_dev->reg_lock);
3208 static int vop_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv, bcsh_bcs_mode mode)
3210 struct vop_device *vop_dev =
3211 container_of(dev_drv, struct vop_device, driver);
3214 spin_lock(&vop_dev->reg_lock);
3215 if (vop_dev->clk_on) {
3216 val = vop_readl(vop_dev, BCSH_BCS);
3219 val &= MASK(BRIGHTNESS);
3226 val &= MASK(CONTRAST);
3230 val &= MASK(SAT_CON);
3237 spin_unlock(&vop_dev->reg_lock);
3241 static int vop_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
3243 struct vop_device *vop_dev =
3244 container_of(dev_drv, struct vop_device, driver);
3246 spin_lock(&vop_dev->reg_lock);
3247 if (vop_dev->clk_on) {
3249 vop_writel(vop_dev, BCSH_COLOR_BAR, 0x1);
3250 vop_writel(vop_dev, BCSH_BCS, 0xd0010000);
3251 vop_writel(vop_dev, BCSH_H, 0x01000000);
3252 dev_drv->bcsh.enable = 1;
3254 vop_msk_reg(vop_dev, BCSH_COLOR_BAR, V_BCSH_EN(0));
3255 dev_drv->bcsh.enable = 0;
3257 vop_bcsh_path_sel(dev_drv);
3258 vop_cfg_done(vop_dev);
3260 spin_unlock(&vop_dev->reg_lock);
3265 static int vop_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
3267 if (!enable || !dev_drv->bcsh.enable) {
3268 vop_open_bcsh(dev_drv, false);
3272 if (dev_drv->bcsh.brightness <= 255 ||
3273 dev_drv->bcsh.contrast <= 510 ||
3274 dev_drv->bcsh.sat_con <= 1015 ||
3275 (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
3276 vop_open_bcsh(dev_drv, true);
3277 if (dev_drv->bcsh.brightness <= 255)
3278 vop_set_bcsh_bcs(dev_drv, BRIGHTNESS,
3279 dev_drv->bcsh.brightness);
3280 if (dev_drv->bcsh.contrast <= 510)
3281 vop_set_bcsh_bcs(dev_drv, CONTRAST,
3282 dev_drv->bcsh.contrast);
3283 if (dev_drv->bcsh.sat_con <= 1015)
3284 vop_set_bcsh_bcs(dev_drv, SAT_CON,
3285 dev_drv->bcsh.sat_con);
3286 if (dev_drv->bcsh.sin_hue <= 511 &&
3287 dev_drv->bcsh.cos_hue <= 511)
3288 vop_set_bcsh_hue(dev_drv, dev_drv->bcsh.sin_hue,
3289 dev_drv->bcsh.cos_hue);
3295 static int __maybe_unused
3296 vop_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
3298 struct vop_device *vop_dev =
3299 container_of(dev_drv, struct vop_device, driver);
3302 spin_lock(&vop_dev->reg_lock);
3303 if (likely(vop_dev->clk_on)) {
3304 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLACK_EN(1));
3305 vop_cfg_done(vop_dev);
3307 spin_unlock(&vop_dev->reg_lock);
3309 spin_lock(&vop_dev->reg_lock);
3310 if (likely(vop_dev->clk_on)) {
3311 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLACK_EN(0));
3313 vop_cfg_done(vop_dev);
3315 spin_unlock(&vop_dev->reg_lock);
3321 static int vop_backlight_close(struct rk_lcdc_driver *dev_drv, int enable)
3323 struct vop_device *vop_dev =
3324 container_of(dev_drv, struct vop_device, driver);
3326 if (unlikely(!vop_dev->clk_on)) {
3327 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
3330 vop_get_backlight_device(dev_drv);
3333 /* close the backlight */
3334 if (vop_dev->backlight) {
3335 vop_dev->backlight->props.power = FB_BLANK_POWERDOWN;
3336 backlight_update_status(vop_dev->backlight);
3338 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3339 dev_drv->trsm_ops->disable();
3341 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3342 dev_drv->trsm_ops->enable();
3344 /* open the backlight */
3345 if (vop_dev->backlight) {
3346 vop_dev->backlight->props.power = FB_BLANK_UNBLANK;
3347 backlight_update_status(vop_dev->backlight);
3354 static int vop_set_overscan(struct rk_lcdc_driver *dev_drv,
3355 struct overscan *overscan)
3357 struct vop_device *vop_dev =
3358 container_of(dev_drv, struct vop_device, driver);
3360 if (unlikely(!vop_dev->clk_on)) {
3361 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
3364 /*vop_post_cfg(dev_drv);*/
3369 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
3371 .win_direct_en = vop_win_direct_en,
3372 .load_screen = vop_load_screen,
3373 .get_dspbuf_info = vop_get_dspbuf_info,
3374 .post_dspbuf = vop_post_dspbuf,
3375 .set_par = vop_set_par,
3376 .pan_display = vop_pan_display,
3377 .direct_set_addr = vop_direct_set_win_addr,
3378 /*.lcdc_reg_update = vop_reg_update,*/
3381 .suspend = vop_early_suspend,
3382 .resume = vop_early_resume,
3383 .get_win_state = vop_get_win_state,
3384 .area_support_num = vop_get_area_num,
3385 .ovl_mgr = vop_ovl_mgr,
3386 .get_disp_info = vop_get_disp_info,
3387 .fps_mgr = vop_fps_mgr,
3388 .fb_get_win_id = vop_get_win_id,
3389 .fb_win_remap = vop_fb_win_remap,
3390 .poll_vblank = vop_poll_vblank,
3391 .dpi_open = vop_dpi_open,
3392 .dpi_win_sel = vop_dpi_win_sel,
3393 .dpi_status = vop_dpi_status,
3394 .get_dsp_addr = vop_get_dsp_addr,
3395 .set_dsp_bcsh_hue = vop_set_bcsh_hue,
3396 .set_dsp_bcsh_bcs = vop_set_bcsh_bcs,
3397 .get_dsp_bcsh_hue = vop_get_bcsh_hue,
3398 .get_dsp_bcsh_bcs = vop_get_bcsh_bcs,
3399 .open_bcsh = vop_open_bcsh,
3400 .dump_reg = vop_reg_dump,
3401 .cfg_done = vop_config_done,
3402 .set_irq_to_cpu = vop_set_irq_to_cpu,
3403 /*.dsp_black = vop_dsp_black,*/
3404 .backlight_close = vop_backlight_close,
3405 .mmu_en = vop_mmu_en,
3406 .set_overscan = vop_set_overscan,
3409 static irqreturn_t vop_isr(int irq, void *dev_id)
3411 struct vop_device *vop_dev = (struct vop_device *)dev_id;
3412 ktime_t timestamp = ktime_get();
3414 unsigned long flags;
3416 spin_lock_irqsave(&vop_dev->irq_lock, flags);
3418 intr_status = vop_readl(vop_dev, INTR_STATUS0);
3419 vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, intr_status);
3421 spin_unlock_irqrestore(&vop_dev->irq_lock, flags);
3422 /* This is expected for vop iommu irqs, since the irq is shared */
3426 if (intr_status & INTR_FS) {
3427 timestamp = ktime_get();
3428 vop_dev->driver.vsync_info.timestamp = timestamp;
3429 wake_up_interruptible_all(&vop_dev->driver.vsync_info.wait);
3430 intr_status &= ~INTR_FS;
3433 if (intr_status & INTR_LINE_FLAG0)
3434 intr_status &= ~INTR_LINE_FLAG0;
3436 if (intr_status & INTR_LINE_FLAG1)
3437 intr_status &= ~INTR_LINE_FLAG1;
3439 if (intr_status & INTR_FS_NEW)
3440 intr_status &= ~INTR_FS_NEW;
3442 if (intr_status & INTR_BUS_ERROR) {
3443 intr_status &= ~INTR_BUS_ERROR;
3444 dev_warn_ratelimited(vop_dev->dev, "bus error!");
3447 if (intr_status & INTR_WIN0_EMPTY) {
3448 intr_status &= ~INTR_WIN0_EMPTY;
3449 dev_warn_ratelimited(vop_dev->dev, "intr win0 empty!");
3452 if (intr_status & INTR_WIN1_EMPTY) {
3453 intr_status &= ~INTR_WIN1_EMPTY;
3454 dev_warn_ratelimited(vop_dev->dev, "intr win1 empty!");
3457 if (intr_status & INTR_HWC_EMPTY) {
3458 intr_status &= ~INTR_HWC_EMPTY;
3459 dev_warn_ratelimited(vop_dev->dev, "intr hwc empty!");
3462 if (intr_status & INTR_POST_BUF_EMPTY) {
3463 intr_status &= ~INTR_POST_BUF_EMPTY;
3464 dev_warn_ratelimited(vop_dev->dev, "intr post buf empty!");
3468 dev_err(vop_dev->dev, "Unknown VOP IRQs: %#02x\n", intr_status);
3473 #if defined(CONFIG_PM)
3474 static int vop_suspend(struct platform_device *pdev, pm_message_t state)
3479 static int vop_resume(struct platform_device *pdev)
3484 #define vop_suspend NULL
3485 #define vop_resume NULL
3488 static int vop_parse_dt(struct vop_device *vop_dev)
3490 struct device_node *np = vop_dev->dev->of_node;
3491 struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
3494 if (of_property_read_u32(np, "rockchip,prop", &val))
3495 vop_dev->prop = PRMRY; /*default set it as primary */
3497 vop_dev->prop = val;
3499 if (of_property_read_u32(np, "rockchip,mirror", &val))
3500 dev_drv->rotate_mode = NO_MIRROR;
3502 dev_drv->rotate_mode = val;
3504 if (of_property_read_u32(np, "rockchip,pwr18", &val))
3505 /*default set it as 3.xv power supply */
3506 vop_dev->pwr18 = false;
3508 vop_dev->pwr18 = (val ? true : false);
3510 if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
3511 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
3513 dev_drv->fb_win_map = val;
3515 if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
3516 dev_drv->bcsh.enable = false;
3518 dev_drv->bcsh.enable = (val ? true : false);
3520 if (of_property_read_u32(np, "rockchip,brightness", &val))
3521 dev_drv->bcsh.brightness = 0xffff;
3523 dev_drv->bcsh.brightness = val;
3525 if (of_property_read_u32(np, "rockchip,contrast", &val))
3526 dev_drv->bcsh.contrast = 0xffff;
3528 dev_drv->bcsh.contrast = val;
3530 if (of_property_read_u32(np, "rockchip,sat-con", &val))
3531 dev_drv->bcsh.sat_con = 0xffff;
3533 dev_drv->bcsh.sat_con = val;
3535 if (of_property_read_u32(np, "rockchip,hue", &val)) {
3536 dev_drv->bcsh.sin_hue = 0xffff;
3537 dev_drv->bcsh.cos_hue = 0xffff;
3539 dev_drv->bcsh.sin_hue = val & 0xff;
3540 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
3543 #if defined(CONFIG_ROCKCHIP_IOMMU)
3544 if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
3545 dev_drv->iommu_enabled = 0;
3547 dev_drv->iommu_enabled = val;
3549 dev_drv->iommu_enabled = 0;
3554 static int vop_probe(struct platform_device *pdev)
3556 struct vop_device *vop_dev = NULL;
3557 struct rk_lcdc_driver *dev_drv;
3558 struct device *dev = &pdev->dev;
3559 struct resource *res;
3560 struct device_node *np = pdev->dev.of_node;
3564 /* if the primary lcdc has not registered ,the extend
3565 * lcdc register later
3567 of_property_read_u32(np, "rockchip,prop", &prop);
3568 if (prop == EXTEND) {
3569 if (!is_prmry_rk_lcdc_registered())
3570 return -EPROBE_DEFER;
3572 vop_dev = devm_kzalloc(dev, sizeof(struct vop_device), GFP_KERNEL);
3576 platform_set_drvdata(pdev, vop_dev);
3578 vop_parse_dt(vop_dev);
3579 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3580 vop_dev->reg_phy_base = res->start;
3581 vop_dev->len = resource_size(res);
3582 vop_dev->regs = devm_ioremap_resource(dev, res);
3583 if (IS_ERR(vop_dev->regs))
3584 return PTR_ERR(vop_dev->regs);
3586 dev_info(dev, "vop_dev->regs=0x%lx\n", (long)vop_dev->regs);
3588 vop_dev->regsbak = devm_kzalloc(dev, vop_dev->len, GFP_KERNEL);
3589 if (IS_ERR(vop_dev->regsbak))
3590 return PTR_ERR(vop_dev->regsbak);
3593 dev_set_name(vop_dev->dev, "vop%d", vop_dev->id);
3594 dev_drv = &vop_dev->driver;
3596 dev_drv->prop = prop;
3597 dev_drv->id = vop_dev->id;
3598 dev_drv->ops = &lcdc_drv_ops;
3599 dev_drv->lcdc_win_num = ARRAY_SIZE(vop_win);
3600 dev_drv->reserved_fb = 0;
3601 spin_lock_init(&vop_dev->reg_lock);
3602 spin_lock_init(&vop_dev->irq_lock);
3604 vop_dev->irq = platform_get_irq(pdev, 0);
3605 if (vop_dev->irq < 0) {
3606 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
3611 ret = devm_request_irq(dev, vop_dev->irq, vop_isr,
3612 IRQF_DISABLED | IRQF_SHARED,
3613 dev_name(dev), vop_dev);
3615 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
3620 if (dev_drv->iommu_enabled)
3621 strcpy(dev_drv->mmu_dts_name, VOP_IOMMU_COMPATIBLE_NAME);
3623 ret = rk_fb_register(dev_drv, vop_win, vop_dev->id);
3625 dev_err(dev, "register fb for failed!\n");
3628 vop_dev->screen = dev_drv->screen0;
3629 dev_info(dev, "lcdc%d probe ok, iommu %s\n",
3630 vop_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
3635 static int vop_remove(struct platform_device *pdev)
3640 static void vop_shutdown(struct platform_device *pdev)
3642 struct vop_device *vop_dev = platform_get_drvdata(pdev);
3643 struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
3645 dev_drv->suspend_flag = 1;
3647 flush_kthread_worker(&dev_drv->update_regs_worker);
3648 kthread_stop(dev_drv->update_regs_thread);
3650 /*if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3651 dev_drv->trsm_ops->disable();*/
3653 vop_clk_disable(vop_dev);
3654 rk_disp_pwr_disable(dev_drv);
3657 #if defined(CONFIG_OF)
3658 static const struct of_device_id vop_dt_ids[] = {
3659 {.compatible = "rockchip,rk322x-lcdc",},
3664 static struct platform_driver vop_driver = {
3666 .remove = vop_remove,
3668 .name = "rk322x-lcdc",
3669 .owner = THIS_MODULE,
3670 .of_match_table = of_match_ptr(vop_dt_ids),
3672 .suspend = vop_suspend,
3673 .resume = vop_resume,
3674 .shutdown = vop_shutdown,
3677 static int __init vop_module_init(void)
3679 return platform_driver_register(&vop_driver);
3682 static void __exit vop_module_exit(void)
3684 platform_driver_unregister(&vop_driver);
3687 fs_initcall(vop_module_init);
3688 module_exit(vop_module_exit);