drivers/video/rockchip/lcdc/rk312x_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk312x_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  * Author:      zhuangwenlong<zwl@rock-chips.com>
   6  *              zhengyang<zhengyang@rock-chips.com>
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/string.h>
  22 #include <linux/mm.h>
  23 #include <linux/slab.h>
  24 #include <linux/device.h>
  25 #include <linux/delay.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <asm/div64.h>
  31 #include <asm/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37 #include <linux/rockchip-iovmm.h>
  38 #include "rk312x_lcdc.h"
  39
  40 static int dbg_thresd;
  41 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  42
  43 #define DBG(level, x...) do {                   \
  44         if (unlikely(dbg_thresd >= level))      \
  45                 printk(KERN_INFO x); } while (0)
  46
  47 #define grf_writel(offset, v)   do { \
  48                         writel_relaxed(v, RK_GRF_VIRT + offset); \
  49                         dsb(); \
  50                         } while (0)
  51
  52 static struct rk_lcdc_win lcdc_win[] = {
  53         [0] = {
  54                .name = "win0",
  55                .id = 0,
  56                .support_3d = false,
  57                },
  58         [1] = {
  59                .name = "win1",
  60                .id = 1,
  61                .support_3d = false,
  62                },
  63         [2] = {
  64                .name = "hwc",
  65                .id = 2,
  66                .support_3d = false,
  67                },
  68 };
  69
  70 static irqreturn_t rk312x_lcdc_isr(int irq, void *dev_id)
  71 {
  72         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
  73         ktime_t timestamp = ktime_get();
  74         u32 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
  75
  76         if (int_reg & m_FS_INT_STA) {
  77                 timestamp = ktime_get();
  78                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR,
  79                              v_FS_INT_CLEAR(1));
  80                 //if (lcdc_dev->driver.wait_fs) {
  81                 if (0) {
  82                         spin_lock(&(lcdc_dev->driver.cpl_lock));
  83                         complete(&(lcdc_dev->driver.frame_done));
  84                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
  85                 }
  86                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
  87                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
  88
  89         } else if (int_reg & m_LF_INT_STA) {
  90                 lcdc_dev->driver.frame_time.last_framedone_t =
  91                                 lcdc_dev->driver.frame_time.framedone_t;
  92                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
  93                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
  94                              v_LF_INT_CLEAR(1));
  95         }
  96
  97 #ifdef LCDC_IRQ_EMPTY_DEBUG
  98         if (int_reg & m_WIN0_EMPTY_INT_STA) {
  99                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_WIN0_EMPTY_INT_CLEAR,
 100                              v_WIN0_EMPTY_INT_CLEAR(1));
 101                 dev_info(lcdc_dev->dev, "win0 empty irq\n");
 102         } else if (int_reg & m_WIN1_EMPTY_INT_STA) {
 103                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_WIN1_EMPTY_INT_CLEAR,
 104                              v_WIN1_EMPTY_INT_CLEAR(1));
 105                 dev_info(lcdc_dev->dev, "win1 empty irq\n");
 106         }
 107 #endif
 108
 109         return IRQ_HANDLED;
 110 }
 111
 112 static int rk312x_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 113 {
 114 #ifdef CONFIG_RK_FPGA
 115         lcdc_dev->clk_on = 1;
 116         return 0;
 117 #endif
 118         if (!lcdc_dev->clk_on) {
 119                 clk_prepare_enable(lcdc_dev->hclk);
 120                 clk_prepare_enable(lcdc_dev->dclk);
 121                 clk_prepare_enable(lcdc_dev->aclk);
 122                 clk_prepare_enable(lcdc_dev->pd);
 123                 spin_lock(&lcdc_dev->reg_lock);
 124                 lcdc_dev->clk_on = 1;
 125                 spin_unlock(&lcdc_dev->reg_lock);
 126         }
 127
 128         return 0;
 129 }
 130
 131 static int rk312x_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 132 {
 133 #ifdef CONFIG_RK_FPGA
 134         lcdc_dev->clk_on = 0;
 135         return 0;
 136 #endif
 137         if (lcdc_dev->clk_on) {
 138                 spin_lock(&lcdc_dev->reg_lock);
 139                 lcdc_dev->clk_on = 0;
 140                 spin_unlock(&lcdc_dev->reg_lock);
 141                 mdelay(25);
 142                 clk_disable_unprepare(lcdc_dev->dclk);
 143                 clk_disable_unprepare(lcdc_dev->hclk);
 144                 clk_disable_unprepare(lcdc_dev->aclk);
 145                 clk_disable_unprepare(lcdc_dev->pd);
 146         }
 147
 148         return 0;
 149 }
 150
 151 static int rk312x_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
 152 {
 153         u32 mask, val;
 154         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 155                                                     struct lcdc_device, driver);
 156         struct rk_screen *screen = dev_drv->cur_screen;
 157
 158         spin_lock(&lcdc_dev->reg_lock);
 159         if (likely(lcdc_dev->clk_on)) {
 160                 mask = m_FS_INT_CLEAR | m_FS_INT_EN |
 161                         m_LF_INT_CLEAR | m_LF_INT_EN | m_LF_INT_NUM |
 162                         m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN;
 163                 val = v_FS_INT_CLEAR(1) | v_FS_INT_EN(1) |
 164                         v_LF_INT_CLEAR(1) | v_LF_INT_EN(1) |
 165                         v_BUS_ERR_INT_CLEAR(1) | v_BUS_ERR_INT_EN(0) |
 166                         v_LF_INT_NUM(screen->mode.vsync_len +
 167                                      screen->mode.upper_margin +
 168                                      screen->mode.yres);
 169 #ifdef LCDC_IRQ_EMPTY_DEBUG
 170                 mask |= m_WIN0_EMPTY_INT_EN | m_WIN1_EMPTY_INT_EN;
 171                 val |= v_WIN0_EMPTY_INT_EN(1) | v_WIN1_EMPTY_INT_EN(1);
 172 #endif
 173
 174                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 175                 spin_unlock(&lcdc_dev->reg_lock);
 176         } else {
 177                 spin_unlock(&lcdc_dev->reg_lock);
 178         }
 179         return 0;
 180 }
 181
 182 static int rk312x_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 183 {
 184         u32 mask, val;
 185
 186         spin_lock(&lcdc_dev->reg_lock);
 187         if (likely(lcdc_dev->clk_on)) {
 188                 mask = m_FS_INT_CLEAR | m_FS_INT_EN |
 189                         m_LF_INT_CLEAR | m_LF_INT_EN |
 190                         m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN;
 191                 val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0) |
 192                         v_LF_INT_CLEAR(0) | v_LF_INT_EN(0) |
 193                         v_BUS_ERR_INT_CLEAR(0) | v_BUS_ERR_INT_EN(0);
 194 #ifdef LCDC_IRQ_EMPTY_DEBUG
 195                 mask |= m_WIN0_EMPTY_INT_EN | m_WIN1_EMPTY_INT_EN;
 196                 val |= v_WIN0_EMPTY_INT_EN(0) | v_WIN1_EMPTY_INT_EN(0);
 197 #endif
 198
 199                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 200                 spin_unlock(&lcdc_dev->reg_lock);
 201         } else {
 202                 spin_unlock(&lcdc_dev->reg_lock);
 203         }
 204         mdelay(1);
 205         return 0;
 206 }
 207
 208 static void rk_lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 209 {
 210         int reg = 0;
 211         u32 value = 0;
 212
 213         spin_lock(&lcdc_dev->reg_lock);
 214         for (reg = 0; reg < 0xe0; reg += 4) {
 215                 value = lcdc_readl(lcdc_dev, reg);
 216         }
 217         spin_unlock(&lcdc_dev->reg_lock);
 218 }
 219
 220 static int rk312x_lcdc_alpha_cfg(struct lcdc_device *lcdc_dev)
 221 {
 222         int win0_top = 0;
 223         u32 mask, val;
 224         enum data_format win0_format = lcdc_dev->driver.win[0]->format;
 225         enum data_format win1_format = lcdc_dev->driver.win[1]->format;
 226
 227         int win0_alpha_en = ((win0_format == ARGB888)
 228                              || (win0_format == ABGR888)) ? 1 : 0;
 229         int win1_alpha_en = ((win1_format == ARGB888)
 230                              || (win1_format == ABGR888)) ? 1 : 0;
 231         u32 *_pv = (u32 *) lcdc_dev->regsbak;
 232
 233         _pv += (DSP_CTRL0 >> 2);
 234         win0_top = ((*_pv) & (m_WIN0_TOP)) >> 8;
 235         if (win0_top && (lcdc_dev->atv_layer_cnt >= 2) && (win0_alpha_en)) {
 236                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 237                 val = v_WIN0_ALPHA_EN(1) | v_WIN1_ALPHA_EN(0);
 238                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 239
 240                 mask = m_WIN0_ALPHA_MODE | m_ALPHA_MODE_SEL0 | m_ALPHA_MODE_SEL1;
 241                 val = v_WIN0_ALPHA_MODE(1) | v_ALPHA_MODE_SEL0(1) | v_ALPHA_MODE_SEL1(0);
 242                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 243         } else if ((!win0_top) && (lcdc_dev->atv_layer_cnt >= 2)
 244                    && (win1_alpha_en)) {
 245                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 246                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(1);
 247                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 248
 249                 mask = m_WIN1_ALPHA_MODE | m_ALPHA_MODE_SEL0 | m_ALPHA_MODE_SEL1;
 250                 val = v_WIN1_ALPHA_MODE(1) | v_ALPHA_MODE_SEL0(1) | v_ALPHA_MODE_SEL1(0);
 251                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 252         } else {
 253                 mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 254                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(0);
 255                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 256         }
 257
 258         if(lcdc_dev->driver.win[2]->state == 1) {
 259                 mask =  m_HWC_ALPAH_EN;
 260                 val = v_HWC_ALPAH_EN(1);
 261                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 262
 263                 mask =  m_HWC_ALPHA_MODE;
 264                 val = v_HWC_ALPHA_MODE(1);
 265                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 266         } else {
 267                 mask =  m_HWC_ALPAH_EN;
 268                 val = v_HWC_ALPAH_EN(0);
 269                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 270         }
 271
 272         return 0;
 273 }
 274
 275 static void lcdc_layer_csc_mode(struct lcdc_device *lcdc_dev,
 276                                       struct rk_lcdc_win *win)
 277 {
 278         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
 279         struct rk_screen *screen = dev_drv->cur_screen;
 280
 281         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
 282                 switch (win->fmt_cfg) {
 283                 case VOP_FORMAT_ARGB888:
 284                 case VOP_FORMAT_RGB888:
 285                 case VOP_FORMAT_RGB565:
 286                         if ((screen->mode.xres < 1280 ) &&
 287                             (screen->mode.yres < 720)) {
 288                                 win->csc_mode = VOP_R2Y_CSC_BT601;
 289                         } else {
 290                                 win->csc_mode = VOP_R2Y_CSC_BT709;
 291                         }
 292                         break;
 293                 default:
 294                         break;
 295                 }
 296                 if (win->id  == 0) {
 297                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_CSC_MODE,
 298                                      v_WIN0_CSC_MODE(win->csc_mode));
 299                 } else if (win->id  == 1) {
 300                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN1_CSC_MODE,
 301                                      v_WIN1_CSC_MODE(win->csc_mode));
 302                 }
 303         } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
 304                 switch (win->fmt_cfg) {
 305                 case VOP_FORMAT_YCBCR420:
 306                         if (win->id  == 0) {
 307                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
 308                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_CSC_MODE,
 309                                              v_WIN0_CSC_MODE(win->csc_mode));
 310                         }
 311                         break;
 312                 default:
 313                         break;
 314                 }
 315         }
 316
 317 }
 318
 319
 320 static void lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
 321                                    struct rk_lcdc_win *win)
 322 {
 323         u32 mask, val;
 324         int hwc_size;
 325
 326         if (win->state == 1) {
 327                 if (lcdc_dev->soc_type == VOP_RK312X)
 328                         lcdc_layer_csc_mode(lcdc_dev, win);
 329
 330                 if (win->id == 0) {
 331                         mask = m_WIN0_EN | m_WIN0_FORMAT | m_WIN0_RB_SWAP;
 332                         val = v_WIN0_EN(win->state) |
 333                                 v_WIN0_FORMAT(win->fmt_cfg) |
 334                                 v_WIN0_RB_SWAP(win->swap_rb);
 335                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 336                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB,
 337                                     v_X_SCL_FACTOR(win->scale_yrgb_x) |
 338                                     v_Y_SCL_FACTOR(win->scale_yrgb_y));
 339                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR,
 340                                     v_X_SCL_FACTOR(win->scale_cbcr_x) |
 341                                     v_Y_SCL_FACTOR(win->scale_cbcr_y));
 342
 343                         lcdc_msk_reg(lcdc_dev, WIN0_VIR,
 344                                      m_YRGB_VIR | m_CBBR_VIR,
 345                                      v_YRGB_VIR(win->area[0].y_vir_stride) |
 346                                      v_CBCR_VIR(win->area[0].uv_vir_stride));
 347                         lcdc_writel(lcdc_dev, WIN0_ACT_INFO,
 348                                     v_ACT_WIDTH(win->area[0].xact) |
 349                                     v_ACT_HEIGHT(win->area[0].yact));
 350                         lcdc_writel(lcdc_dev, WIN0_DSP_ST,
 351                                     v_DSP_STX(win->area[0].dsp_stx) |
 352                                     v_DSP_STY(win->area[0].dsp_sty));
 353                         lcdc_writel(lcdc_dev, WIN0_DSP_INFO,
 354                                     v_DSP_WIDTH(win->area[0].xsize) |
 355                                     v_DSP_HEIGHT(win->area[0].ysize));
 356
 357                         lcdc_writel(lcdc_dev, WIN0_YRGB_MST,
 358                                     win->area[0].y_addr);
 359                         lcdc_writel(lcdc_dev, WIN0_CBR_MST,
 360                                     win->area[0].uv_addr);
 361                 } else if (win->id == 1) {
 362                         mask = m_WIN1_EN | m_WIN1_FORMAT | m_WIN1_RB_SWAP;
 363                         val = v_WIN1_EN(win->state) |
 364                                 v_WIN1_FORMAT(win->fmt_cfg) |
 365                                 v_WIN1_RB_SWAP(win->swap_rb);
 366                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 367                         /* rk312x unsupport win1 scale */
 368                         if (lcdc_dev->soc_type == VOP_RK3036) {
 369                                 lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_YRGB,
 370                                         v_X_SCL_FACTOR(win->scale_yrgb_x) |
 371                                         v_Y_SCL_FACTOR(win->scale_yrgb_y));
 372                                 lcdc_writel(lcdc_dev, WIN1_ACT_INFO,
 373                                             v_ACT_WIDTH(win->area[0].xact) |
 374                                             v_ACT_HEIGHT(win->area[0].yact));
 375                                 lcdc_writel(lcdc_dev, WIN1_DSP_INFO,
 376                                             v_DSP_WIDTH(win->area[0].xsize) |
 377                                             v_DSP_HEIGHT(win->area[0].ysize));
 378                                 lcdc_writel(lcdc_dev, WIN1_DSP_ST,
 379                                             v_DSP_STX(win->area[0].dsp_stx) |
 380                                             v_DSP_STY(win->area[0].dsp_sty));
 381                                 lcdc_writel(lcdc_dev, WIN1_MST, win->area[0].y_addr);
 382                         } else {
 383                                 lcdc_writel(lcdc_dev, WIN1_DSP_INFO_RK312X,
 384                                             v_DSP_WIDTH(win->area[0].xsize) |
 385                                             v_DSP_HEIGHT(win->area[0].ysize));
 386                                 lcdc_writel(lcdc_dev, WIN1_DSP_ST_RK312X,
 387                                             v_DSP_STX(win->area[0].dsp_stx) |
 388                                             v_DSP_STY(win->area[0].dsp_sty));
 389
 390                                 lcdc_writel(lcdc_dev, WIN1_MST_RK312X, win->area[0].y_addr);
 391                         }
 392
 393                         lcdc_msk_reg(lcdc_dev, WIN1_VIR, m_YRGB_VIR,
 394                                      v_YRGB_VIR(win->area[0].y_vir_stride));
 395
 396
 397                 } else if (win->id == 2) {
 398                         mask = m_HWC_EN;
 399                         val = v_HWC_EN(win->state);
 400                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 401                         if((win->area[0].xsize == 32) &&(win->area[0].ysize == 32))
 402                                 hwc_size = 0;
 403                         else if((win->area[0].xsize == 64) &&(win->area[0].ysize == 64))
 404                                 hwc_size = 1;
 405                         else
 406                                 dev_err(lcdc_dev->dev,"unsupport hwc size:x=%d,y=%d\n",
 407                                         win->area[0].xsize,win->area[0].ysize);
 408                         lcdc_writel(lcdc_dev, HWC_DSP_ST,
 409                                     v_DSP_STX(win->area[0].dsp_stx) |
 410                                     v_DSP_STY(win->area[0].dsp_sty));
 411
 412                         lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
 413                 }
 414         } else {
 415                 win->area[0].y_addr = 0;
 416                 win->area[0].uv_addr = 0;
 417                 if (win->id == 0)
 418                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN,
 419                                      v_WIN0_EN(0));
 420                 else if (win->id == 1)
 421                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN1_EN,
 422                                      v_WIN1_EN(0));
 423                 else if (win->id == 2)
 424                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_EN, v_HWC_EN(0));
 425         }
 426         rk312x_lcdc_alpha_cfg(lcdc_dev);
 427 }
 428
 429 static void lcdc_layer_enable(struct lcdc_device *lcdc_dev, unsigned int win_id,
 430                               bool open)
 431 {
 432         spin_lock(&lcdc_dev->reg_lock);
 433         if (likely(lcdc_dev->clk_on)
 434             && lcdc_dev->driver.win[win_id]->state != open) {
 435                 if (open) {
 436                         if (!lcdc_dev->atv_layer_cnt) {
 437                                 dev_info(lcdc_dev->dev,
 438                                          "wakeup from standby!\n");
 439                                 lcdc_dev->standby = 0;
 440                         }
 441                         lcdc_dev->atv_layer_cnt++;
 442                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
 443                         lcdc_dev->atv_layer_cnt--;
 444                 }
 445                 lcdc_dev->driver.win[win_id]->state = open;
 446                 if (!open) {
 447                         lcdc_layer_update_regs(lcdc_dev,
 448                                                lcdc_dev->driver.win[win_id]);
 449                         lcdc_cfg_done(lcdc_dev);
 450                 }
 451                 /*if no layer used,disable lcdc */
 452                 if (!lcdc_dev->atv_layer_cnt) {
 453                         dev_info(lcdc_dev->dev,
 454                                  "no layer is used,go to standby!\n");
 455                         lcdc_dev->standby = 1;
 456                 }
 457         }
 458         spin_unlock(&lcdc_dev->reg_lock);
 459 }
 460
 461 static int rk312x_lcdc_reg_update(struct rk_lcdc_driver *dev_drv)
 462 {
 463         struct lcdc_device *lcdc_dev =
 464             container_of(dev_drv, struct lcdc_device, driver);
 465         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 466         struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1];
 467         int timeout;
 468         unsigned long flags;
 469         spin_lock(&lcdc_dev->reg_lock);
 470         if (likely(lcdc_dev->clk_on)) {
 471                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
 472                              v_LCDC_STANDBY(lcdc_dev->standby));
 473                 lcdc_layer_update_regs(lcdc_dev, win0);
 474                 lcdc_layer_update_regs(lcdc_dev, win1);
 475                 rk312x_lcdc_alpha_cfg(lcdc_dev);
 476                 lcdc_cfg_done(lcdc_dev);
 477
 478         }
 479         spin_unlock(&lcdc_dev->reg_lock);
 480         //if (dev_drv->wait_fs) {
 481         if (0) {
 482                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
 483                 init_completion(&dev_drv->frame_done);
 484                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
 485                 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
 486                                                       msecs_to_jiffies
 487                                                       (dev_drv->cur_screen->ft +
 488                                                        5));
 489                 if (!timeout && (!dev_drv->frame_done.done)) {
 490                         dev_warn(lcdc_dev->dev,
 491                                  "wait for new frame start time out!\n");
 492                         return -ETIMEDOUT;
 493                 }
 494         }
 495         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
 496         return 0;
 497
 498 }
 499
 500 static void rk312x_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
 501 {
 502         memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0xe0);
 503 }
 504
 505 static void rk312x_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
 506 {
 507         u32 mask, val;
 508         struct lcdc_device *lcdc_dev =
 509             container_of(dev_drv, struct lcdc_device, driver);
 510
 511         spin_lock(&lcdc_dev->reg_lock);
 512         if (likely(lcdc_dev->clk_on)) {
 513                 mask = m_MMU_EN | m_AXI_MAX_OUTSTANDING_EN |
 514                         m_AXI_OUTSTANDING_MAX_NUM;
 515                 val = v_MMU_EN(1) | v_AXI_OUTSTANDING_MAX_NUM(31) |
 516                         v_AXI_MAX_OUTSTANDING_EN(1);
 517                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 518         }
 519         spin_unlock(&lcdc_dev->reg_lock);
 520 }
 521 static int rk312x_lcdc_set_hwc_lut(struct rk_lcdc_driver *dev_drv, int *hwc_lut,int mode)
 522 {
 523         int i = 0;
 524         int __iomem *c;
 525         int v;
 526         int len=256*4;
 527         struct lcdc_device *lcdc_dev =
 528                 container_of(dev_drv, struct lcdc_device, driver);
 529         if(dev_drv->hwc_lut == NULL) {
 530                 dev_drv->hwc_lut = devm_kzalloc(lcdc_dev->dev, len, GFP_KERNEL);
 531         }
 532         spin_lock(&lcdc_dev->reg_lock);
 533         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(0));
 534         lcdc_cfg_done(lcdc_dev);
 535         mdelay(25);
 536         for (i = 0; i < 256; i++) {
 537                 if(mode == 1)
 538                         dev_drv->hwc_lut[i] = hwc_lut[i];
 539                 v = dev_drv->hwc_lut[i];
 540                 c = lcdc_dev->hwc_lut_addr_base + (i<<2);
 541                 writel_relaxed(v, c);
 542         }
 543         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(1));
 544         lcdc_cfg_done(lcdc_dev);
 545         spin_unlock(&lcdc_dev->reg_lock);
 546         return 0;
 547
 548 }
 549 static int rk312x_lcdc_set_lut(struct rk_lcdc_driver *dev_drv)
 550 {
 551         int i = 0;
 552         int __iomem *c;
 553         int v;
 554         struct lcdc_device *lcdc_dev =
 555                 container_of(dev_drv, struct lcdc_device, driver);
 556
 557         spin_lock(&lcdc_dev->reg_lock);
 558         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
 559         lcdc_cfg_done(lcdc_dev);
 560         mdelay(25);
 561         for (i = 0; i < 256; i++) {
 562                 v = dev_drv->cur_screen->dsp_lut[i];
 563                 c = lcdc_dev->dsp_lut_addr_base + (i<<2);
 564                 writel_relaxed(v, c);
 565
 566         }
 567         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
 568         lcdc_cfg_done(lcdc_dev);
 569         spin_unlock(&lcdc_dev->reg_lock);
 570         return 0;
 571
 572 }
 573
 574 static int rk312x_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
 575 {
 576 #ifdef CONFIG_RK_FPGA
 577         return 0;
 578 #endif
 579         int ret, fps;
 580         struct lcdc_device *lcdc_dev =
 581             container_of(dev_drv, struct lcdc_device, driver);
 582         struct rk_screen *screen = dev_drv->cur_screen;
 583
 584         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
 585         if (ret)
 586                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
 587         lcdc_dev->pixclock =
 588             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
 589         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
 590
 591         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
 592         screen->ft = 1000 / fps;
 593         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
 594                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
 595         return 0;
 596
 597 }
 598
 599 /********do basic init*********/
 600 static int rk312x_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 601 {
 602         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 603                                                     struct lcdc_device, driver);
 604         if (lcdc_dev->pre_init)
 605                 return 0;
 606
 607         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 608         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 609         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 610         lcdc_dev->sclk = devm_clk_get(lcdc_dev->dev, "sclk_lcdc");
 611         lcdc_dev->pd   = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
 612         lcdc_dev->pll_sclk = devm_clk_get(lcdc_dev->dev, "sclk_pll");
 613
 614         if ( /*IS_ERR(lcdc_dev->pd) || */ (IS_ERR(lcdc_dev->aclk)) ||
 615             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 616                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 617                         lcdc_dev->id);
 618         }
 619
 620         rk_disp_pwr_enable(dev_drv);
 621         rk312x_lcdc_clk_enable(lcdc_dev);
 622
 623         /* backup reg config at uboot */
 624         rk_lcdc_read_reg_defalut_cfg(lcdc_dev);
 625
 626         /* config for the FRC mode of dither down */
 627         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 628         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 629         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0x55aaaa55);
 630         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x55aaaa55);
 631         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 632         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 633
 634         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_AUTO_GATING_EN, v_AUTO_GATING_EN(0));
 635         lcdc_cfg_done(lcdc_dev);
 636         if (dev_drv->iommu_enabled)     /* disable win0 to workaround iommu pagefault */
 637                 lcdc_layer_enable(lcdc_dev, 0, 0);
 638         lcdc_dev->pre_init = true;
 639
 640         return 0;
 641 }
 642
 643 static void rk312x_lcdc_deinit(struct lcdc_device *lcdc_dev)
 644 {
 645         u32 mask, val;
 646
 647         spin_lock(&lcdc_dev->reg_lock);
 648         if (likely(lcdc_dev->clk_on)) {
 649                 mask = m_FS_INT_CLEAR | m_FS_INT_EN |
 650                         m_LF_INT_CLEAR | m_LF_INT_EN |
 651                         m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN;
 652                 val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0) |
 653                         v_LF_INT_CLEAR(0) | v_LF_INT_EN(0) |
 654                         v_BUS_ERR_INT_CLEAR(0) | v_BUS_ERR_INT_EN(0);
 655                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 656                 lcdc_set_bit(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY);
 657                 lcdc_cfg_done(lcdc_dev);
 658                 spin_unlock(&lcdc_dev->reg_lock);
 659         } else {
 660                 spin_unlock(&lcdc_dev->reg_lock);
 661         }
 662         mdelay(1);
 663
 664 }
 665
 666 static u32 calc_sclk_freq(struct rk_screen *src_screen, struct rk_screen *dst_screen)
 667 {
 668         u32 dsp_vtotal;
 669         u64 dsp_htotal;
 670         u32 dsp_in_vtotal;
 671         u64 dsp_in_htotal;
 672         u64 sclk_freq;
 673
 674         if (!src_screen || !dst_screen)
 675                 return 0;
 676
 677         dsp_vtotal = dst_screen->mode.yres;
 678         dsp_htotal = dst_screen->mode.left_margin + dst_screen->mode.hsync_len +
 679                      dst_screen->mode.xres + dst_screen->mode.right_margin;
 680         dsp_in_vtotal = src_screen->mode.yres;
 681         dsp_in_htotal = src_screen->mode.left_margin +
 682                         src_screen->mode.hsync_len +
 683                         src_screen->mode.xres + src_screen->mode.right_margin;
 684         sclk_freq = dsp_vtotal * dsp_htotal * src_screen->mode.pixclock;
 685         do_div(sclk_freq, dsp_in_vtotal * dsp_in_htotal);
 686
 687         return (u32)sclk_freq;
 688 }
 689
 690 #define SCLK_PLL_LIMIT  594000000
 691 static u32 calc_sclk_pll_freq(u32 sclk_freq)
 692 {
 693 #define ACCURACY_LEV    100
 694         u32 pll_freq = 0;
 695         u32 decimal_num = 0;
 696         u16 max_multi_num = 0, multi_num = 0, remainder_num = 0;
 697         u32 less_delta = 0, greater_delta = 0;
 698
 699         if (sclk_freq == 0)
 700                 return 0;
 701
 702         max_multi_num = SCLK_PLL_LIMIT / sclk_freq;
 703         decimal_num = (sclk_freq / (1000000 / ACCURACY_LEV)) % ACCURACY_LEV;
 704         multi_num = ACCURACY_LEV / decimal_num;
 705
 706         if (multi_num > max_multi_num) {
 707                 multi_num = max_multi_num;
 708         } else if (decimal_num != 0) {
 709                 remainder_num = ACCURACY_LEV % decimal_num;
 710                 if (remainder_num != 0) {
 711                         less_delta = ACCURACY_LEV - (decimal_num * multi_num);
 712                         greater_delta = decimal_num * (multi_num + 1) - ACCURACY_LEV;
 713                         multi_num = (less_delta < greater_delta) ? multi_num : (multi_num + 1);
 714                 }
 715         }
 716
 717         pll_freq = sclk_freq * multi_num;
 718         return pll_freq;
 719 }
 720
 721 static int calc_dsp_frm_vst_hst(struct rk_screen *src, struct rk_screen *dst)
 722 {
 723         u32 BP_in, BP_out;
 724         u32 v_scale_ratio;
 725         long long  T_frm_st;
 726         u64 T_BP_in, T_BP_out, T_Delta, Tin;
 727         u64 rate = (1 << 16);
 728         u64 temp;
 729         u32 dsp_htotal, src_htotal, src_vtotal;
 730
 731         if (unlikely(!src) || unlikely(!dst))
 732                 return -1;
 733
 734         dsp_htotal = dst->mode.left_margin + dst->mode.hsync_len +
 735                      dst->mode.xres + dst->mode.right_margin;
 736         src_htotal = src->mode.left_margin + src->mode.hsync_len +
 737                      src->mode.xres + src->mode.right_margin;
 738         src_vtotal = src->mode.upper_margin + src->mode.vsync_len +
 739                      src->mode.yres + src->mode.lower_margin;
 740         BP_in  = (src->mode.upper_margin + src->mode.vsync_len) * src_htotal;
 741         BP_out = (dst->mode.upper_margin + dst->mode.vsync_len) * dsp_htotal;
 742
 743         v_scale_ratio = dst->mode.yres / src->mode.yres;
 744
 745         T_BP_in = rate * BP_in;
 746         do_div(T_BP_in, src->mode.pixclock);
 747         T_BP_out = rate * BP_out;
 748         do_div(T_BP_out, dst->mode.pixclock);
 749         if (v_scale_ratio < 2)
 750                 T_Delta = rate * 4 * src_htotal;
 751         else
 752                 T_Delta = rate * 12 * src_htotal;
 753
 754         do_div(T_Delta, src->mode.pixclock);
 755         Tin = rate * src_vtotal * src_htotal;
 756         do_div(Tin, src->mode.pixclock);
 757
 758         T_frm_st = (T_BP_in + T_Delta - T_BP_out);
 759         if (T_frm_st < 0)
 760                 T_frm_st  += Tin;
 761
 762         temp = T_frm_st * src->mode.pixclock;
 763         dst->scl_hst = do_div(temp, src_htotal * rate);
 764         dst->scl_vst = temp;
 765         dst->scl_hst = (T_frm_st * src->mode.pixclock / rate - dst->scl_vst * src_htotal);
 766
 767         return 0;
 768 }
 769
 770 static int rk312x_lcdc_set_scaler(struct rk_lcdc_driver *dev_drv,
 771                                   struct rk_screen *dst_screen, bool enable)
 772 {
 773         u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end;
 774         u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end;
 775         u32 dsp_hbor_end, dsp_hbor_st, dsp_vbor_end, dsp_vbor_st;
 776         u32 scl_v_factor, scl_h_factor;
 777         u32 dst_frame_hst, dst_frame_vst;
 778         u32 src_w, src_h, dst_w, dst_h;
 779         u16 bor_right = 0;
 780         u16 bor_left = 0;
 781         u16 bor_up = 0;
 782         u16 bor_down = 0;
 783         u32 pll_freq = 0;
 784         struct rk_screen *src;
 785         struct rk_screen *dst;
 786         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 787                                                     struct lcdc_device, driver);
 788
 789         if (unlikely(!lcdc_dev->clk_on))
 790                 return 0;
 791
 792         if (!enable) {
 793                 spin_lock(&lcdc_dev->reg_lock);
 794                 lcdc_msk_reg(lcdc_dev, SCALER_CTRL,
 795                                 m_SCALER_EN | m_SCALER_OUT_ZERO | m_SCALER_OUT_EN,
 796                                 v_SCALER_EN(0) | v_SCALER_OUT_ZERO(0) | v_SCALER_OUT_EN(0));
 797                 spin_unlock(&lcdc_dev->reg_lock);
 798                 if (lcdc_dev->sclk_on) {
 799                         clk_disable_unprepare(lcdc_dev->sclk);
 800                         lcdc_dev->sclk_on = false;
 801                 }
 802                 dev_dbg(lcdc_dev->dev, "%s: disable\n", __func__);
 803                 return 0;
 804         }
 805
 806         /* rk312x used one lcdc to apply dual disp
 807          * hdmi screen is used for scaler src
 808          * prmry screen is used for scaler dst
 809          */
 810         dst = dst_screen;
 811         src = dev_drv->cur_screen;
 812         if (!dst || !src) {
 813                 dev_err(lcdc_dev->dev, "%s: dst screen is null!\n", __func__);
 814                 return -EINVAL;
 815         }
 816
 817         if (!lcdc_dev->sclk_on) {
 818                 clk_prepare_enable(lcdc_dev->sclk);
 819                 lcdc_dev->s_pixclock = calc_sclk_freq(src, dst);
 820                 pll_freq = calc_sclk_pll_freq(lcdc_dev->s_pixclock);
 821                 clk_set_rate(lcdc_dev->pll_sclk, pll_freq);
 822                 clk_set_rate(lcdc_dev->sclk, lcdc_dev->s_pixclock);
 823                 lcdc_dev->sclk_on = true;
 824                 dev_info(lcdc_dev->dev, "%s:sclk=%d\n", __func__,
 825                          lcdc_dev->s_pixclock);
 826         }
 827
 828         /* config scale timing */
 829         calc_dsp_frm_vst_hst(src, dst);
 830         dst_frame_vst = dst->scl_vst;
 831         dst_frame_hst = dst->scl_hst;
 832
 833         dsp_htotal    = dst->mode.hsync_len + dst->mode.left_margin +
 834                         dst->mode.xres + dst->mode.right_margin;
 835         dsp_hs_end    = dst->mode.hsync_len;
 836
 837         dsp_vtotal    = dst->mode.vsync_len + dst->mode.upper_margin +
 838                         dst->mode.yres + dst->mode.lower_margin;
 839         dsp_vs_end    = dst->mode.vsync_len;
 840
 841         dsp_hbor_end  = dst->mode.hsync_len + dst->mode.left_margin +
 842                         dst->mode.xres;
 843         dsp_hbor_st   = dst->mode.hsync_len + dst->mode.left_margin;
 844         dsp_vbor_end  = dst->mode.vsync_len + dst->mode.upper_margin +
 845                         dst->mode.yres;
 846         dsp_vbor_st   = dst->mode.vsync_len + dst->mode.upper_margin;
 847
 848         dsp_hact_st   = dsp_hbor_st  + bor_left;
 849         dsp_hact_end  = dsp_hbor_end - bor_right;
 850         dsp_vact_st   = dsp_vbor_st  + bor_up;
 851         dsp_vact_end  = dsp_vbor_end - bor_down;
 852
 853         src_w = src->mode.xres;
 854         src_h = src->mode.yres;
 855         dst_w = dsp_hact_end - dsp_hact_st;
 856         dst_h = dsp_vact_end - dsp_vact_st;
 857
 858         /* calc scale factor */
 859         scl_h_factor = ((src_w - 1) << 12) / (dst_w - 1);
 860         scl_v_factor = ((src_h - 1) << 12) / (dst_h - 1);
 861
 862         spin_lock(&lcdc_dev->reg_lock);
 863         if (dst->color_mode != src->color_mode) {
 864                 /*dev_drv->output_color = dst->color_mode;
 865                 if (dev_drv->output_color == COLOR_YCBCR)
 866                         dev_drv->overlay_mode = VOP_YUV_DOMAIN;
 867                 else
 868                         dev_drv->overlay_mode = VOP_RGB_DOMAIN;
 869                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_SW_OVERLAY_MODE,
 870                              v_SW_OVERLAY_MODE(dev_drv->overlay_mode));*/
 871         }
 872
 873         lcdc_writel(lcdc_dev, SCALER_FACTOR,
 874                     v_SCALER_H_FACTOR(scl_h_factor) |
 875                     v_SCALER_V_FACTOR(scl_v_factor));
 876
 877         lcdc_writel(lcdc_dev, SCALER_FRAME_ST,
 878                     v_SCALER_FRAME_HST(dst_frame_hst) |
 879                     v_SCALER_FRAME_VST(dst_frame_vst));
 880         lcdc_writel(lcdc_dev, SCALER_DSP_HOR_TIMING,
 881                     v_SCALER_HS_END(dsp_hs_end) |
 882                     v_SCALER_HTOTAL(dsp_htotal));
 883         lcdc_writel(lcdc_dev, SCALER_DSP_HACT_ST_END,
 884                     v_SCALER_HAEP(dsp_hact_end) |
 885                     v_SCALER_HASP(dsp_hact_st));
 886         lcdc_writel(lcdc_dev, SCALER_DSP_VER_TIMING,
 887                     v_SCALER_VS_END(dsp_vs_end) |
 888                     v_SCALER_VTOTAL(dsp_vtotal));
 889         lcdc_writel(lcdc_dev, SCALER_DSP_VACT_ST_END,
 890                     v_SCALER_VAEP(dsp_vact_end) |
 891                     v_SCALER_VASP(dsp_vact_st));
 892         lcdc_writel(lcdc_dev, SCALER_DSP_HBOR_TIMING,
 893                     v_SCALER_HBOR_END(dsp_hbor_end) |
 894                     v_SCALER_HBOR_ST(dsp_hbor_st));
 895         lcdc_writel(lcdc_dev, SCALER_DSP_VBOR_TIMING,
 896                     v_SCALER_VBOR_END(dsp_vbor_end) |
 897                     v_SCALER_VBOR_ST(dsp_vbor_st));
 898         lcdc_msk_reg(lcdc_dev, SCALER_CTRL,
 899                     m_SCALER_EN | m_SCALER_OUT_ZERO | m_SCALER_OUT_EN,
 900                     v_SCALER_EN(1) | v_SCALER_OUT_ZERO(0) | v_SCALER_OUT_EN(1));
 901
 902         lcdc_cfg_done(lcdc_dev);
 903         spin_unlock(&lcdc_dev->reg_lock);
 904
 905         return 0;
 906 }
 907
 908 static int rk312x_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
 909 {
 910         u16 face = 0;
 911         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 912                                                     struct lcdc_device, driver);
 913         struct rk_screen *screen = dev_drv->cur_screen;
 914         u16 right_margin = screen->mode.right_margin;
 915         u16 left_margin = screen->mode.left_margin;
 916         u16 lower_margin = screen->mode.lower_margin;
 917         u16 upper_margin = screen->mode.upper_margin;
 918         u16 x_res = screen->mode.xres;
 919         u16 y_res = screen->mode.yres;
 920         u32 mask, val;
 921
 922         spin_lock(&lcdc_dev->reg_lock);
 923         if (likely(lcdc_dev->clk_on)) {
 924                 /* Select output color domain */
 925                 /*dev_drv->output_color = screen->color_mode;
 926                 if (lcdc_dev->soc_type == VOP_RK312X) {
 927                         if (dev_drv->output_color == COLOR_YCBCR)
 928                                 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
 929                         else
 930                                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
 931                 } else {
 932                         dev_drv->output_color = COLOR_RGB;
 933                         dev_drv->overlay_mode = VOP_RGB_DOMAIN;
 934                 }*/
 935                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;/*something wrong at yuv domain*/
 936
 937                 switch (screen->type) {
 938                 case SCREEN_RGB:
 939                         if (lcdc_dev->soc_type == VOP_RK312X) {
 940                                 mask = m_RGB_DCLK_EN | m_RGB_DCLK_INVERT;
 941                                 val = v_RGB_DCLK_EN(1) | v_RGB_DCLK_INVERT(0);
 942                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 943                         }
 944                         break;
 945                 case SCREEN_LVDS:
 946                         if (lcdc_dev->soc_type == VOP_RK312X) {
 947                                 mask = m_LVDS_DCLK_EN | m_LVDS_DCLK_INVERT;
 948                                 val = v_LVDS_DCLK_EN(1) | v_LVDS_DCLK_INVERT(1);
 949                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 950                         }
 951                         break;
 952                 case SCREEN_MIPI:
 953                         if (lcdc_dev->soc_type == VOP_RK312X) {
 954                                 mask = m_MIPI_DCLK_EN | m_MIPI_DCLK_INVERT;
 955                                 val = v_MIPI_DCLK_EN(1) | v_MIPI_DCLK_INVERT(0);
 956                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 957                         }
 958                         break;
 959                 case SCREEN_HDMI:
 960                         mask = m_HDMI_DCLK_EN;
 961                         val = v_HDMI_DCLK_EN(1);
 962                         if (screen->pixelrepeat) {
 963                                 mask |= m_CORE_CLK_DIV_EN;
 964                                 val |= v_CORE_CLK_DIV_EN(1);
 965                         } else {
 966                                 mask |= m_CORE_CLK_DIV_EN;
 967                                 val |= v_CORE_CLK_DIV_EN(0);
 968                         }
 969                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 970                         if (lcdc_dev->soc_type == VOP_RK312X) {
 971                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 972                                              m_SW_UV_OFFSET_EN,
 973                                              v_SW_UV_OFFSET_EN(0));
 974                                 mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
 975                                        m_HDMI_DEN_POL;
 976                                 val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
 977                                       v_HDMI_VSYNC_POL(screen->pin_vsync) |
 978                                       v_HDMI_DEN_POL(screen->pin_den);
 979                                 lcdc_msk_reg(lcdc_dev, INT_SCALER, mask, val);
 980                         } else {
 981                                 mask = (1 << 4) | (1 << 5) | (1 << 6);
 982                                 val = (screen->pin_hsync << 4) |
 983                                         (screen->pin_vsync << 5) |
 984                                         (screen->pin_den << 6);
 985                                 grf_writel(RK3036_GRF_SOC_CON2, (mask << 16) | val);
 986                         }
 987                         break;
 988                 case SCREEN_TVOUT:
 989                 case SCREEN_TVOUT_TEST:
 990                         mask = m_TVE_DAC_DCLK_EN;
 991                         val = v_TVE_DAC_DCLK_EN(1);
 992                         if (screen->pixelrepeat) {
 993                                 mask |= m_CORE_CLK_DIV_EN;
 994                                 val |= v_CORE_CLK_DIV_EN(1);
 995                         }
 996                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 997                         if (x_res == 720 && y_res == 576)
 998                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_TVE_MODE,
 999                                              v_TVE_MODE(TV_PAL));
1000                         else if (x_res == 720 && y_res == 480)
1001                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_TVE_MODE,
1002                                              v_TVE_MODE(TV_NTSC));
1003                         else {
1004                                 dev_err(lcdc_dev->dev,
1005                                         "unsupported video timing!\n");
1006                                 return -1;
1007                         }
1008                         if (lcdc_dev->soc_type == VOP_RK312X) {
1009                                 if (screen->type == SCREEN_TVOUT_TEST)/*for TVE index test,vop must ovarlay at yuv domain*/
1010                                         dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1011                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1012                                              m_SW_UV_OFFSET_EN,
1013                                              v_SW_UV_OFFSET_EN(1));
1014                         }
1015                         break;
1016                 default:
1017                         dev_err(lcdc_dev->dev, "un supported interface!\n");
1018                         break;
1019                 }
1020                 if (lcdc_dev->soc_type == VOP_RK312X) {
1021                         switch (screen->face) {
1022                         case OUT_P565:
1023                                 face = OUT_P565;
1024                                 mask = m_DITHER_DOWN_EN |
1025                                         m_DITHER_DOWN_MODE |
1026                                         m_DITHER_DOWN_SEL;
1027                                 val = v_DITHER_DOWN_EN(1) |
1028                                         v_DITHER_DOWN_MODE(0) |
1029                                         v_DITHER_DOWN_SEL(1);
1030                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1031                                 break;
1032                         case OUT_P666:
1033                                 face = OUT_P666;
1034                                 mask = m_DITHER_DOWN_EN |
1035                                         m_DITHER_DOWN_MODE |
1036                                         m_DITHER_DOWN_SEL;
1037                                 val = v_DITHER_DOWN_EN(1) |
1038                                         v_DITHER_DOWN_MODE(1) |
1039                                         v_DITHER_DOWN_SEL(1);
1040                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1041                                 break;
1042                         case OUT_D888_P565:
1043                                 face = OUT_P888;
1044                                 mask = m_DITHER_DOWN_EN |
1045                                         m_DITHER_DOWN_MODE |
1046                                         m_DITHER_DOWN_SEL;
1047                                 val = v_DITHER_DOWN_EN(1) |
1048                                         v_DITHER_DOWN_MODE(0) |
1049                                         v_DITHER_DOWN_SEL(1);
1050                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1051                                 break;
1052                         case OUT_D888_P666:
1053                                 face = OUT_P888;
1054                                 mask = m_DITHER_DOWN_EN |
1055                                         m_DITHER_DOWN_MODE |
1056                                         m_DITHER_DOWN_SEL;
1057                                 val = v_DITHER_DOWN_EN(1) |
1058                                         v_DITHER_DOWN_MODE(1) |
1059                                         v_DITHER_DOWN_SEL(1);
1060                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1061                                 break;
1062                         case OUT_P888:
1063                                 face = OUT_P888;
1064                                 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1065                                 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1066                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1067                                 break;
1068                         default:
1069                                 dev_err(lcdc_dev->dev, "un supported interface!\n");
1070                                 break;
1071                         }
1072                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_SW_OVERLAY_MODE,
1073                                      v_SW_OVERLAY_MODE(dev_drv->overlay_mode));
1074                 }
1075
1076                 mask = m_DSP_OUT_FORMAT | m_HSYNC_POL | m_VSYNC_POL |
1077                     m_DEN_POL | m_DCLK_POL;
1078                 val = v_DSP_OUT_FORMAT(face) | v_HSYNC_POL(screen->pin_hsync) |
1079                     v_VSYNC_POL(screen->pin_vsync) |
1080                     v_DEN_POL(screen->pin_den) |
1081                     v_DCLK_POL(screen->pin_dclk);
1082                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1083
1084                 mask = m_BG_COLOR | m_DSP_BG_SWAP | m_DSP_RB_SWAP |
1085                     m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1086                     m_DSP_DUMMY_SWAP | m_BLANK_EN | m_BLACK_EN;
1087
1088                 val = v_BG_COLOR(0x000000) | v_DSP_BG_SWAP(screen->swap_gb) |
1089                     v_DSP_RB_SWAP(screen->swap_rb) |
1090                     v_DSP_RG_SWAP(screen->swap_rg) |
1091                     v_DSP_DELTA_SWAP(screen->swap_delta) |
1092                     v_DSP_DUMMY_SWAP(screen->swap_dumy) |
1093                     v_BLANK_EN(0) | v_BLACK_EN(0);
1094                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1095
1096                 /* config timing */
1097                 val = v_HSYNC(screen->mode.hsync_len) |
1098                     v_HORPRD(screen->mode.hsync_len + left_margin + x_res +
1099                              right_margin);
1100                 lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END, val);
1101                 val = v_HAEP(screen->mode.hsync_len + left_margin + x_res) |
1102                     v_HASP(screen->mode.hsync_len + left_margin);
1103                 lcdc_writel(lcdc_dev, DSP_HACT_ST_END, val);
1104
1105                 if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1106                         /* First Field Timing */
1107                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END,
1108                                     v_VSYNC(screen->mode.vsync_len) |
1109                                     v_VERPRD(2 * (screen->mode.vsync_len + upper_margin + lower_margin) +
1110                                              y_res + 1));
1111                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END,
1112                                     v_VAEP(screen->mode.vsync_len +
1113                                            upper_margin + y_res / 2) |
1114                                     v_VASP(screen->mode.vsync_len +
1115                                            upper_margin));
1116                         /* Second Field Timing */
1117                         lcdc_writel(lcdc_dev, DSP_VS_ST_END_F1,
1118                                     v_VSYNC_ST_F1(screen->mode.vsync_len +
1119                                                   upper_margin + y_res / 2 +
1120                                                   lower_margin) |
1121                                     v_VSYNC_END_F1(2 * screen->mode.vsync_len +
1122                                                    upper_margin + y_res / 2 +
1123                                                    lower_margin));
1124                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END_F1,
1125                                     v_VAEP(2 * (screen->mode.vsync_len + upper_margin) +
1126                                            y_res + lower_margin + 1) |
1127                                     v_VASP(2 * (screen->mode.vsync_len + upper_margin) +
1128                                            y_res / 2 + lower_margin + 1));
1129
1130                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1131                                      m_INTERLACE_DSP_EN |
1132                                      m_WIN0_YRGB_DEFLICK_EN |
1133                                      m_WIN0_CBR_DEFLICK_EN |
1134                                      m_INTERLACE_FIELD_POL |
1135                                      m_WIN0_INTERLACE_EN |
1136                                      m_WIN1_INTERLACE_EN,
1137                                      v_INTERLACE_DSP_EN(1) |
1138                                      v_WIN0_YRGB_DEFLICK_EN(1) |
1139                                      v_WIN0_CBR_DEFLICK_EN(1) |
1140                                      v_INTERLACE_FIELD_POL(0) |
1141                                      v_WIN0_INTERLACE_EN(1) |
1142                                      v_WIN1_INTERLACE_EN(1));
1143                         mask = m_LF_INT_NUM;
1144                         val = v_LF_INT_NUM(screen->mode.vsync_len +
1145                                            screen->mode.upper_margin +
1146                                            screen->mode.yres/2);
1147                         lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
1148                 } else {
1149                         val = v_VSYNC(screen->mode.vsync_len) |
1150                             v_VERPRD(screen->mode.vsync_len + upper_margin +
1151                                      y_res + lower_margin);
1152                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, val);
1153
1154                         val = v_VAEP(screen->mode.vsync_len + upper_margin + y_res) |
1155                             v_VASP(screen->mode.vsync_len + upper_margin);
1156                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END, val);
1157
1158                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1159                                      m_INTERLACE_DSP_EN |
1160                                      m_WIN0_YRGB_DEFLICK_EN |
1161                                      m_WIN0_CBR_DEFLICK_EN |
1162                                      m_INTERLACE_FIELD_POL |
1163                                      m_WIN0_INTERLACE_EN |
1164                                      m_WIN1_INTERLACE_EN,
1165                                      v_INTERLACE_DSP_EN(0) |
1166                                      v_WIN0_YRGB_DEFLICK_EN(0) |
1167                                      v_WIN0_CBR_DEFLICK_EN(0) |
1168                                      v_INTERLACE_FIELD_POL(0) |
1169                                      v_WIN0_INTERLACE_EN(0) |
1170                                      v_WIN1_INTERLACE_EN(0));
1171                         mask = m_LF_INT_NUM;
1172                         val = v_LF_INT_NUM(screen->mode.vsync_len +
1173                                            screen->mode.upper_margin +
1174                                            screen->mode.yres);
1175                         lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
1176                 }
1177
1178         }
1179         spin_unlock(&lcdc_dev->reg_lock);
1180
1181         rk312x_lcdc_set_dclk(dev_drv);
1182         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1183                 dev_drv->trsm_ops->enable();
1184         if (screen->init)
1185                 screen->init();
1186
1187         return 0;
1188 }
1189
1190 static int rk312x_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1191                             bool open)
1192 {
1193         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1194                                                     struct lcdc_device, driver);
1195
1196         /* enable clk,when first layer open */
1197         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1198                 rockchip_set_system_status(SYS_STATUS_LCDC0);
1199                 rk312x_lcdc_pre_init(dev_drv);
1200                 rk312x_lcdc_clk_enable(lcdc_dev);
1201 #if defined(CONFIG_ROCKCHIP_IOMMU)
1202                 if (dev_drv->iommu_enabled) {
1203                         if (!dev_drv->mmu_dev) {
1204                                 dev_drv->mmu_dev =
1205                                         rk_fb_get_sysmmu_device_by_compatible(dev_drv->mmu_dts_name);
1206                                 if (dev_drv->mmu_dev) {
1207                                         rk_fb_platform_set_sysmmu(dev_drv->mmu_dev,
1208                                                                   dev_drv->dev);
1209                                 } else {
1210                                         dev_err(dev_drv->dev,
1211                                                 "failed to get rockchip iommu device\n");
1212                                         return -1;
1213                                 }
1214                         }
1215                         if (dev_drv->mmu_dev)
1216                                 rockchip_iovmm_activate(dev_drv->dev);
1217                 }
1218 #endif
1219                 rk312x_lcdc_reg_restore(lcdc_dev);
1220                 if (dev_drv->iommu_enabled)
1221                         rk312x_lcdc_mmu_en(dev_drv);
1222                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
1223                         rk312x_lcdc_set_dclk(dev_drv);
1224                         rk312x_lcdc_enable_irq(dev_drv);
1225                 } else {
1226                         rk312x_load_screen(dev_drv, 1);
1227                 }
1228
1229                 /* set screen lut */
1230                 if (dev_drv->cur_screen->dsp_lut)
1231                         rk312x_lcdc_set_lut(dev_drv);
1232         }
1233
1234         if (win_id < ARRAY_SIZE(lcdc_win))
1235                 lcdc_layer_enable(lcdc_dev, win_id, open);
1236         else
1237                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1238
1239         /* when all layer closed,disable clk */
1240         if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1241                 rk312x_lcdc_disable_irq(lcdc_dev);
1242                 rk312x_lcdc_reg_update(dev_drv);
1243 #if defined(CONFIG_ROCKCHIP_IOMMU)
1244                 if (dev_drv->iommu_enabled) {
1245                         if (dev_drv->mmu_dev)
1246                                 rockchip_iovmm_deactivate(dev_drv->dev);
1247                 }
1248 #endif
1249                 rk312x_lcdc_clk_disable(lcdc_dev);
1250                 rockchip_clear_system_status(SYS_STATUS_LCDC0);
1251         }
1252
1253         return 0;
1254 }
1255
1256 static int rk312x_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
1257 {
1258         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1259                                                     struct lcdc_device, driver);
1260         struct rk_screen *screen = dev_drv->cur_screen;
1261         struct rk_lcdc_win *win = NULL;
1262         char fmt[9] = "NULL";
1263
1264         if (!screen) {
1265                 dev_err(dev_drv->dev, "screen is null!\n");
1266                 return -ENOENT;
1267         }
1268
1269         if (win_id == 0) {
1270                 win = dev_drv->win[0];
1271         } else if (win_id == 1) {
1272                 win = dev_drv->win[1];
1273         } else if (win_id == 2) {
1274                 win = dev_drv->win[2];
1275         } else {
1276                 dev_err(dev_drv->dev, "un supported win number:%d\n", win_id);
1277                 return -EINVAL;
1278         }
1279
1280         spin_lock(&lcdc_dev->reg_lock);
1281         win->area[0].dsp_stx = win->area[0].xpos + screen->mode.left_margin +
1282                                 screen->mode.hsync_len;
1283         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1284                 win->area[0].ysize /= 2;
1285                 win->area[0].dsp_sty = win->area[0].ypos / 2 +
1286                                         screen->mode.upper_margin +
1287                                         screen->mode.vsync_len;
1288         } else {
1289                 win->area[0].dsp_sty = win->area[0].ypos +
1290                                         screen->mode.upper_margin +
1291                                         screen->mode.vsync_len;
1292         }
1293         win->scale_yrgb_x = CalScale(win->area[0].xact, win->area[0].xsize);
1294         win->scale_yrgb_y = CalScale(win->area[0].yact, win->area[0].ysize);
1295
1296         switch (win->format) {
1297         case ARGB888:
1298                 win->fmt_cfg = VOP_FORMAT_ARGB888;
1299                 win->swap_rb = 0;
1300                 break;
1301         case XBGR888:
1302                 win->fmt_cfg = VOP_FORMAT_ARGB888;
1303                 win->swap_rb = 1;
1304                 break;
1305         case ABGR888:
1306                 win->fmt_cfg = VOP_FORMAT_ARGB888;
1307                 win->swap_rb = 1;
1308                 break;
1309         case RGB888:
1310                 win->fmt_cfg = VOP_FORMAT_RGB888;
1311                 win->swap_rb = 0;
1312                 break;
1313         case RGB565:
1314                 win->fmt_cfg = VOP_FORMAT_RGB565;
1315                 win->swap_rb = 0;
1316                 break;
1317         case YUV444:
1318                 if (win_id == 0) {
1319                         win->fmt_cfg = VOP_FORMAT_YCBCR444;
1320                         win->scale_cbcr_x =
1321                             CalScale(win->area[0].xact, win->area[0].xsize);
1322                         win->scale_cbcr_y =
1323                             CalScale(win->area[0].yact, win->area[0].ysize);
1324                         win->swap_rb = 0;
1325                 } else {
1326                         dev_err(lcdc_dev->driver.dev,
1327                                 "%s:un supported format!\n", __func__);
1328                 }
1329                 break;
1330         case YUV422:
1331                 if (win_id == 0) {
1332                         win->fmt_cfg = VOP_FORMAT_YCBCR422;
1333                         win->scale_cbcr_x = CalScale((win->area[0].xact / 2),
1334                                                      win->area[0].xsize);
1335                         win->scale_cbcr_y =
1336                             CalScale(win->area[0].yact, win->area[0].ysize);
1337                         win->swap_rb = 0;
1338                 } else {
1339                         dev_err(lcdc_dev->driver.dev,
1340                                 "%s:un supported format!\n", __func__);
1341                 }
1342                 break;
1343         case YUV420:
1344                 if (win_id == 0) {
1345                         win->fmt_cfg = VOP_FORMAT_YCBCR420;
1346                         win->scale_cbcr_x =
1347                             CalScale(win->area[0].xact / 2, win->area[0].xsize);
1348                         win->scale_cbcr_y =
1349                             CalScale(win->area[0].yact / 2, win->area[0].ysize);
1350                         win->swap_rb = 0;
1351                 } else {
1352                         dev_err(lcdc_dev->driver.dev,
1353                                 "%s:un supported format!\n", __func__);
1354                 }
1355                 break;
1356         default:
1357                 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
1358                         __func__);
1359                 break;
1360         }
1361         spin_unlock(&lcdc_dev->reg_lock);
1362
1363         DBG(1,
1364             "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
1365             ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, __func__,
1366             get_format_string(win->format, fmt), win->area[0].xact,
1367             win->area[0].yact, win->area[0].xsize, win->area[0].ysize,
1368             win->area[0].xvir, win->area[0].yvir, win->area[0].xpos,
1369             win->area[0].ypos);
1370         return 0;
1371 }
1372
1373 static int rk312x_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
1374 {
1375         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1376                                                     struct lcdc_device, driver);
1377         struct rk_lcdc_win *win = NULL;
1378         struct rk_screen *screen = dev_drv->cur_screen;
1379
1380         if (!screen) {
1381                 dev_err(dev_drv->dev, "screen is null!\n");
1382                 return -ENOENT;
1383         }
1384
1385         if (win_id == 0) {
1386                 win = dev_drv->win[0];
1387         } else if (win_id == 1) {
1388                 win = dev_drv->win[1];
1389         } else if (win_id == 2) {
1390                 win = dev_drv->win[2];
1391         }else {
1392                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1393                 return -EINVAL;
1394         }
1395
1396         spin_lock(&lcdc_dev->reg_lock);
1397         if (likely(lcdc_dev->clk_on)) {
1398                 win->area[0].y_addr =
1399                     win->area[0].smem_start + win->area[0].y_offset;
1400                 win->area[0].uv_addr =
1401                     win->area[0].cbr_start + win->area[0].c_offset;
1402                 if (win->area[0].y_addr)
1403                         lcdc_layer_update_regs(lcdc_dev, win);
1404                 /* lcdc_cfg_done(lcdc_dev); */
1405         }
1406         spin_unlock(&lcdc_dev->reg_lock);
1407
1408         DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n",
1409             lcdc_dev->id, __func__, win->area[0].y_addr, win->area[0].uv_addr,
1410             win->area[0].y_offset);
1411         /* this is the first frame of the system,enable frame start interrupt */
1412         if ((dev_drv->first_frame)) {
1413                 dev_drv->first_frame = 0;
1414                 rk312x_lcdc_enable_irq(dev_drv);
1415
1416         }
1417
1418         return 0;
1419 }
1420
1421 static int rk312x_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
1422                              unsigned long arg, int win_id)
1423 {
1424         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1425                                                     struct lcdc_device, driver);
1426         u32 panel_size[2];
1427         void __user *argp = (void __user *)arg;
1428         struct color_key_cfg clr_key_cfg;
1429
1430         switch (cmd) {
1431         case RK_FBIOGET_PANEL_SIZE:
1432                 panel_size[0] = lcdc_dev->screen->mode.xres;
1433                 panel_size[1] = lcdc_dev->screen->mode.yres;
1434                 if (copy_to_user(argp, panel_size, 8))
1435                         return -EFAULT;
1436                 break;
1437         case RK_FBIOPUT_COLOR_KEY_CFG:
1438                 if (copy_from_user(&clr_key_cfg, argp,
1439                                    sizeof(struct color_key_cfg)))
1440                         return -EFAULT;
1441                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
1442                             clr_key_cfg.win0_color_key_cfg);
1443                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
1444                             clr_key_cfg.win1_color_key_cfg);
1445                 break;
1446
1447         default:
1448                 break;
1449         }
1450         return 0;
1451 }
1452
1453 static int rk312x_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
1454                                   const char *id)
1455 {
1456         int win_id = 0;
1457         mutex_lock(&dev_drv->fb_win_id_mutex);
1458         if (!strcmp(id, "fb0"))
1459                 win_id = dev_drv->fb0_win_id;
1460         else if (!strcmp(id, "fb1"))
1461                 win_id = dev_drv->fb1_win_id;
1462         else if (!strcmp(id, "fb2"))
1463                 win_id = dev_drv->fb2_win_id;
1464         mutex_unlock(&dev_drv->fb_win_id_mutex);
1465
1466         return win_id;
1467 }
1468
1469 static int rk312x_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
1470 {
1471         return 0;
1472 }
1473
1474 static int rk312x_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
1475                                bool set)
1476 {
1477         struct lcdc_device *lcdc_dev =
1478             container_of(dev_drv, struct lcdc_device, driver);
1479         int ovl;
1480         spin_lock(&lcdc_dev->reg_lock);
1481         if (lcdc_dev->clk_on) {
1482                 if (set) {
1483                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_TOP,
1484                                      v_WIN0_TOP(swap));
1485                         ovl = swap;
1486                 } else {
1487                         ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP);
1488                 }
1489         } else {
1490                 ovl = -EPERM;
1491         }
1492         spin_unlock(&lcdc_dev->reg_lock);
1493
1494         return ovl;
1495 }
1496
1497 static int rk312x_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
1498 {
1499
1500         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1501                                                     struct lcdc_device, driver);
1502         if (dev_drv->suspend_flag)
1503                 return 0;
1504         dev_drv->suspend_flag = 1;
1505         flush_kthread_worker(&dev_drv->update_regs_worker);
1506
1507         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
1508                 dev_drv->trsm_ops->disable();
1509         spin_lock(&lcdc_dev->reg_lock);
1510         if (likely(lcdc_dev->clk_on)) {
1511                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, v_BLANK_EN(1));
1512                 lcdc_msk_reg(lcdc_dev, INT_STATUS,
1513                              m_FS_INT_CLEAR | m_LF_INT_CLEAR,
1514                              v_FS_INT_CLEAR(1) | v_LF_INT_CLEAR(1));
1515                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1516                              v_DSP_OUT_ZERO(1));
1517                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1518                              v_LCDC_STANDBY(1));
1519                 lcdc_cfg_done(lcdc_dev);
1520
1521                 if (dev_drv->iommu_enabled) {
1522                         if (dev_drv->mmu_dev)
1523                                 rockchip_iovmm_deactivate(dev_drv->dev);
1524                 }
1525
1526                 spin_unlock(&lcdc_dev->reg_lock);
1527         } else {
1528                 spin_unlock(&lcdc_dev->reg_lock);
1529                 return 0;
1530         }
1531         rk312x_lcdc_clk_disable(lcdc_dev);
1532         rk_disp_pwr_disable(dev_drv);
1533         return 0;
1534 }
1535
1536 static int rk312x_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
1537 {
1538         struct lcdc_device *lcdc_dev =
1539             container_of(dev_drv, struct lcdc_device, driver);
1540
1541         if (!dev_drv->suspend_flag)
1542                 return 0;
1543         rk_disp_pwr_enable(dev_drv);
1544         dev_drv->suspend_flag = 0;
1545
1546         if (lcdc_dev->atv_layer_cnt) {
1547                 rk312x_lcdc_clk_enable(lcdc_dev);
1548                 rk312x_lcdc_reg_restore(lcdc_dev);
1549                 /* set screen lut */
1550                 if (dev_drv->cur_screen->dsp_lut)
1551                         rk312x_lcdc_set_lut(dev_drv);
1552                 /*set hwc lut*/
1553                 //rk312x_lcdc_set_hwc_lut(dev_drv, dev_drv->hwc_lut, 0);
1554
1555                 spin_lock(&lcdc_dev->reg_lock);
1556
1557                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1558                              v_DSP_OUT_ZERO(0));
1559                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1560                              v_LCDC_STANDBY(0));
1561                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, v_BLANK_EN(0));
1562                 lcdc_cfg_done(lcdc_dev);
1563
1564                 if (dev_drv->iommu_enabled) {
1565                         if (dev_drv->mmu_dev)
1566                                 rockchip_iovmm_activate(dev_drv->dev);
1567                 }
1568
1569                 spin_unlock(&lcdc_dev->reg_lock);
1570         }
1571
1572         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1573                 dev_drv->trsm_ops->enable();
1574         return 0;
1575 }
1576
1577 static int rk312x_lcdc_blank(struct rk_lcdc_driver *dev_drv,
1578                              int win_id, int blank_mode)
1579 {
1580         switch (blank_mode) {
1581         case FB_BLANK_UNBLANK:
1582                 rk312x_lcdc_early_resume(dev_drv);
1583                 break;
1584         case FB_BLANK_NORMAL:
1585                 rk312x_lcdc_early_suspend(dev_drv);
1586                 break;
1587         default:
1588                 rk312x_lcdc_early_suspend(dev_drv);
1589                 break;
1590         }
1591
1592         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
1593
1594         return 0;
1595 }
1596
1597 static int rk312x_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv)
1598 {
1599         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1600                                                     struct lcdc_device, driver);
1601         spin_lock(&lcdc_dev->reg_lock);
1602         if (lcdc_dev->clk_on)
1603                 lcdc_cfg_done(lcdc_dev);
1604         spin_unlock(&lcdc_dev->reg_lock);
1605         return 0;
1606 }
1607
1608 /*
1609         a:[-30~0]:
1610             sin_hue = sin(a)*256 +0x100;
1611             cos_hue = cos(a)*256;
1612         a:[0~30]
1613             sin_hue = sin(a)*256;
1614             cos_hue = cos(a)*256;
1615 */
1616 static int rk312x_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
1617                                     bcsh_hue_mode mode)
1618 {
1619
1620         struct lcdc_device *lcdc_dev =
1621             container_of(dev_drv, struct lcdc_device, driver);
1622         u32 val;
1623
1624         spin_lock(&lcdc_dev->reg_lock);
1625         if (lcdc_dev->clk_on) {
1626                 val = lcdc_readl(lcdc_dev, BCSH_H);
1627                 switch (mode) {
1628                 case H_SIN:
1629                         val &= m_BCSH_SIN_HUE;
1630                         break;
1631                 case H_COS:
1632                         val &= m_BCSH_COS_HUE;
1633                         val >>= 16;
1634                         break;
1635                 default:
1636                         break;
1637                 }
1638         }
1639         spin_unlock(&lcdc_dev->reg_lock);
1640
1641         return val;
1642 }
1643
1644 static int rk312x_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv, int sin_hue,
1645                                     int cos_hue)
1646 {
1647
1648         struct lcdc_device *lcdc_dev =
1649             container_of(dev_drv, struct lcdc_device, driver);
1650         u32 mask, val;
1651
1652         spin_lock(&lcdc_dev->reg_lock);
1653         if (lcdc_dev->clk_on) {
1654                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
1655                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
1656                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
1657                 lcdc_cfg_done(lcdc_dev);
1658         }
1659         spin_unlock(&lcdc_dev->reg_lock);
1660
1661         return 0;
1662 }
1663
1664 static int rk312x_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1665                                     bcsh_bcs_mode mode, int value)
1666 {
1667         struct lcdc_device *lcdc_dev =
1668             container_of(dev_drv, struct lcdc_device, driver);
1669         u32 mask, val;
1670
1671         spin_lock(&lcdc_dev->reg_lock);
1672         if (lcdc_dev->clk_on) {
1673                 switch (mode) {
1674                 case BRIGHTNESS:
1675                         /* from 0 to 255,typical is 128 */
1676                         if (value < 0x80)
1677                                 value += 0x80;
1678                         else if (value >= 0x80)
1679                                 value = value - 0x80;
1680                         mask = m_BCSH_BRIGHTNESS;
1681                         val = v_BCSH_BRIGHTNESS(value);
1682                         break;
1683                 case CONTRAST:
1684                         /* from 0 to 510,typical is 256 */
1685                         mask = m_BCSH_CONTRAST;
1686                         val = v_BCSH_CONTRAST(value);
1687                         break;
1688                 case SAT_CON:
1689                         /* from 0 to 1015,typical is 256 */
1690                         mask = m_BCSH_SAT_CON;
1691                         val = v_BCSH_SAT_CON(value);
1692                         break;
1693                 default:
1694                         break;
1695                 }
1696                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
1697                 lcdc_cfg_done(lcdc_dev);
1698         }
1699         spin_unlock(&lcdc_dev->reg_lock);
1700         return val;
1701 }
1702
1703 static int rk312x_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1704                                     bcsh_bcs_mode mode)
1705 {
1706         struct lcdc_device *lcdc_dev =
1707             container_of(dev_drv, struct lcdc_device, driver);
1708         u32 val;
1709
1710         spin_lock(&lcdc_dev->reg_lock);
1711         if (lcdc_dev->clk_on) {
1712                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
1713                 switch (mode) {
1714                 case BRIGHTNESS:
1715                         val &= m_BCSH_BRIGHTNESS;
1716                         if (val > 0x80)
1717                                 val -= 0x80;
1718                         else
1719                                 val += 0x80;
1720                         break;
1721                 case CONTRAST:
1722                         val &= m_BCSH_CONTRAST;
1723                         val >>= 8;
1724                         break;
1725                 case SAT_CON:
1726                         val &= m_BCSH_SAT_CON;
1727                         val >>= 20;
1728                         break;
1729                 default:
1730                         break;
1731                 }
1732         }
1733         spin_unlock(&lcdc_dev->reg_lock);
1734         return val;
1735 }
1736
1737 static int rk312x_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
1738 {
1739         struct lcdc_device *lcdc_dev =
1740             container_of(dev_drv, struct lcdc_device, driver);
1741         u32 mask, val;
1742
1743         spin_lock(&lcdc_dev->reg_lock);
1744         if (lcdc_dev->clk_on) {
1745                 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1746                         if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1747                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL, m_BCSH_Y2R_EN,
1748                                                 v_BCSH_Y2R_EN(0));
1749                         else    /* YUV2RGB */
1750                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1751                                                 m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE,
1752                                                 v_BCSH_Y2R_EN(1) | v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG));
1753                 } else {        /* overlay_mode=VOP_RGB_DOMAIN */
1754                         if (dev_drv->output_color == COLOR_RGB) /* bypass */
1755                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL, m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1756                                                 v_BCSH_R2Y_EN(1) | v_BCSH_Y2R_EN(1));
1757                         else    /* RGB2YUV */
1758                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1759                                                 m_BCSH_R2Y_EN | m_BCSH_R2Y_CSC_MODE,
1760                                                 v_BCSH_R2Y_EN(1) | v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG));
1761                 }
1762                 if (open) {
1763                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,m_BCSH_EN | m_BCSH_OUT_MODE,
1764                                     v_BCSH_EN(1) | v_BCSH_OUT_MODE(3));
1765                         lcdc_writel(lcdc_dev, BCSH_BCS,
1766                                     v_BCSH_BRIGHTNESS(0x00) |
1767                                     v_BCSH_CONTRAST(0x80) |
1768                                     v_BCSH_SAT_CON(0x80));
1769                         lcdc_writel(lcdc_dev, BCSH_H, v_BCSH_COS_HUE(0x80));
1770                 } else {
1771                         mask = m_BCSH_EN;
1772                         val = v_BCSH_EN(0);
1773                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL, mask, val);
1774                 }
1775                 lcdc_cfg_done(lcdc_dev);
1776
1777         }
1778
1779         spin_unlock(&lcdc_dev->reg_lock);
1780         return 0;
1781 }
1782
1783 static int rk312x_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
1784 {
1785         mutex_lock(&dev_drv->fb_win_id_mutex);
1786         if (order == FB_DEFAULT_ORDER)
1787                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2;    /*  FB0_WIN1_FB1_WIN0_FB2_WIN2; for box */
1788         dev_drv->fb2_win_id = order / 100;
1789         dev_drv->fb1_win_id = (order / 10) % 10;
1790         dev_drv->fb0_win_id = order % 10;
1791         mutex_unlock(&dev_drv->fb_win_id_mutex);
1792
1793         return 0;
1794 }
1795
1796 static int rk312x_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
1797                                bool set)
1798 {
1799         struct lcdc_device *lcdc_dev =
1800             container_of(dev_drv, struct lcdc_device, driver);
1801         struct rk_screen *screen = dev_drv->cur_screen;
1802         u64 ft = 0;
1803         u32 dotclk;
1804         int ret;
1805         u32 pixclock;
1806         u32 x_total, y_total;
1807         if (set) {
1808                 ft = div_u64(1000000000000llu, fps);
1809                 x_total =
1810                     screen->mode.upper_margin + screen->mode.lower_margin +
1811                     screen->mode.yres + screen->mode.vsync_len;
1812                 y_total =
1813                     screen->mode.left_margin + screen->mode.right_margin +
1814                     screen->mode.xres + screen->mode.hsync_len;
1815                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
1816                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
1817                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
1818         }
1819
1820         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1821         dev_drv->pixclock = lcdc_dev->pixclock = pixclock;
1822         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
1823         screen->ft = 1000 / fps;        /*one frame time in ms */
1824
1825         if (set)
1826                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
1827                          clk_get_rate(lcdc_dev->dclk), fps);
1828
1829         return fps;
1830 }
1831
1832 static int rk312x_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
1833                                             int enable)
1834 {
1835        struct lcdc_device *lcdc_dev =
1836                                 container_of(dev_drv,struct lcdc_device,driver);
1837        if (enable)
1838                enable_irq(lcdc_dev->irq);
1839        else
1840                disable_irq(lcdc_dev->irq);
1841        return 0;
1842 }
1843
1844 static int rk312x_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
1845 {
1846         struct lcdc_device *lcdc_dev =
1847             container_of(dev_drv, struct lcdc_device, driver);
1848         u32 int_reg;
1849         int ret;
1850
1851         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
1852                 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
1853                 if (int_reg & m_LF_INT_STA) {
1854                         dev_drv->frame_time.last_framedone_t =
1855                                         dev_drv->frame_time.framedone_t;
1856                         dev_drv->frame_time.framedone_t = cpu_clock(0);
1857                         lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
1858                                      v_LF_INT_CLEAR(1));
1859                         ret = RK_LF_STATUS_FC;
1860                 } else
1861                         ret = RK_LF_STATUS_FR;
1862         } else {
1863                 ret = RK_LF_STATUS_NC;
1864         }
1865
1866         return ret;
1867 }
1868
1869 static int rk312x_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
1870                                     unsigned int *dsp_addr)
1871 {
1872         struct lcdc_device *lcdc_dev =
1873             container_of(dev_drv, struct lcdc_device, driver);
1874
1875         if (lcdc_dev->clk_on) {
1876                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1877                 if (lcdc_dev->soc_type == VOP_RK3036)
1878                         dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_MST);
1879                 else if (lcdc_dev->soc_type == VOP_RK312X)
1880                         dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_MST_RK312X);
1881         }
1882         return 0;
1883 }
1884
1885 static ssize_t rk312x_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
1886                                          char *buf, int win_id)
1887 {
1888         struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device,
1889                                                     driver);
1890         char format_w0[9] = "NULL";
1891         char format_w1[9] = "NULL";
1892         char status_w0[9] = "NULL";
1893         char status_w1[9] = "NULL";
1894         u32 fmt_id, act_info, dsp_info, dsp_st, factor;
1895         u16 xvir_w0, x_act_w0, y_act_w0, x_dsp_w0, y_dsp_w0, x_st_w0, y_st_w0;
1896         u16 xvir_w1, x_act_w1, y_act_w1, x_dsp_w1, y_dsp_w1, x_st_w1, y_st_w1;
1897         u16 x_factor, y_factor, x_scale, y_scale;
1898         u16 ovl;
1899         u32 win1_dsp_yaddr = 0;
1900
1901         spin_lock(&lcdc_dev->reg_lock);
1902         if (lcdc_dev->clk_on) {
1903                 /* data format */
1904                 fmt_id = lcdc_readl(lcdc_dev, SYS_CTRL);
1905                 get_format_string((fmt_id & m_WIN0_FORMAT) >> 3, format_w0);
1906                 get_format_string((fmt_id & m_WIN1_FORMAT) >> 6, format_w1);
1907
1908                 /* win status */
1909                 if (fmt_id & m_WIN0_EN)
1910                         strcpy(status_w0, "enabled");
1911                 else
1912                         strcpy(status_w0, "disabled");
1913
1914                 if ((fmt_id & m_WIN1_EN) >> 1)
1915                         strcpy(status_w1, "enabled");
1916                 else
1917                         strcpy(status_w1, "disabled");
1918
1919                 /* ovl */
1920                 ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP);
1921
1922                 /* xvir */
1923                 xvir_w0 = lcdc_readl(lcdc_dev, WIN0_VIR) & m_YRGB_VIR;
1924                 xvir_w1 = lcdc_readl(lcdc_dev, WIN1_VIR) & m_YRGB_VIR;
1925
1926                 /* xact/yact */
1927                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1928                 x_act_w0 = (act_info & m_ACT_WIDTH) + 1;
1929                 y_act_w0 = ((act_info & m_ACT_HEIGHT) >> 16) + 1;
1930
1931                 if (lcdc_dev->soc_type == VOP_RK3036) {
1932                         act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
1933                         x_act_w1 = (act_info & m_ACT_WIDTH) + 1;
1934                         y_act_w1 = ((act_info & m_ACT_HEIGHT) >> 16) + 1;
1935                 } else if (lcdc_dev->soc_type == VOP_RK312X) {
1936                         /* rk312x unsupport win1 scaler,so have no act info */
1937                         x_act_w1 = 0;
1938                         y_act_w1 = 0;
1939                 }
1940
1941                 /* xsize/ysize */
1942                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
1943                 x_dsp_w0 = (dsp_info & m_DSP_WIDTH) + 1;
1944                 y_dsp_w0 = ((dsp_info & m_DSP_HEIGHT) >> 16) + 1;
1945
1946                 if (lcdc_dev->soc_type == VOP_RK3036)
1947                         dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
1948                 else if (lcdc_dev->soc_type == VOP_RK312X)
1949                         dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO_RK312X);
1950                 x_dsp_w1 = (dsp_info & m_DSP_WIDTH) + 1;
1951                 y_dsp_w1 = ((dsp_info & m_DSP_HEIGHT) >> 16) + 1;
1952
1953                 /* xpos/ypos */
1954                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
1955                 x_st_w0 = dsp_st & m_DSP_STX;
1956                 y_st_w0 = (dsp_st & m_DSP_STY) >> 16;
1957
1958                 if (lcdc_dev->soc_type == VOP_RK3036)
1959                         dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
1960                 else if (lcdc_dev->soc_type == VOP_RK312X)
1961                         dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST_RK312X);
1962
1963                 x_st_w1 = dsp_st & m_DSP_STX;
1964                 y_st_w1 = (dsp_st & m_DSP_STY) >> 16;
1965
1966                 /* scale factor */
1967                 factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
1968                 x_factor = factor & m_X_SCL_FACTOR;
1969                 y_factor = (factor & m_Y_SCL_FACTOR) >> 16;
1970                 x_scale = 4096 * 100 / x_factor;
1971                 y_scale = 4096 * 100 / y_factor;
1972
1973                 /* dsp addr */
1974                 if (lcdc_dev->soc_type == VOP_RK3036)
1975                         win1_dsp_yaddr = lcdc_readl(lcdc_dev, WIN1_MST);
1976                 else if (lcdc_dev->soc_type == VOP_RK312X)
1977                         win1_dsp_yaddr = lcdc_readl(lcdc_dev, WIN1_MST_RK312X);
1978         } else {
1979                 spin_unlock(&lcdc_dev->reg_lock);
1980                 return -EPERM;
1981         }
1982         spin_unlock(&lcdc_dev->reg_lock);
1983         return snprintf(buf, PAGE_SIZE,
1984                         "win0:%s\n"
1985                         "xvir:%d\n"
1986                         "xact:%d\n"
1987                         "yact:%d\n"
1988                         "xdsp:%d\n"
1989                         "ydsp:%d\n"
1990                         "x_st:%d\n"
1991                         "y_st:%d\n"
1992                         "x_scale:%d.%d\n"
1993                         "y_scale:%d.%d\n"
1994                         "format:%s\n"
1995                         "YRGB buffer addr:0x%08x\n"
1996                         "CBR buffer addr:0x%08x\n\n"
1997                         "win1:%s\n"
1998                         "xvir:%d\n"
1999                         "xact:%d\n"
2000                         "yact:%d\n"
2001                         "xdsp:%d\n"
2002                         "ydsp:%d\n"
2003                         "x_st:%d\n"
2004                         "y_st:%d\n"
2005                         "format:%s\n"
2006                         "YRGB buffer addr:0x%08x\n"
2007                         "overlay:%s\n",
2008                         status_w0,
2009                         xvir_w0,
2010                         x_act_w0,
2011                         y_act_w0,
2012                         x_dsp_w0,
2013                         y_dsp_w0,
2014                         x_st_w0,
2015                         y_st_w0,
2016                         x_scale / 100,
2017                         x_scale % 100,
2018                         y_scale / 100,
2019                         y_scale % 100,
2020                         format_w0,
2021                         lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
2022                         lcdc_readl(lcdc_dev, WIN0_CBR_MST),
2023                         status_w1,
2024                         xvir_w1,
2025                         x_act_w1,
2026                         y_act_w1,
2027                         x_dsp_w1,
2028                         y_dsp_w1,
2029                         x_st_w1,
2030                         y_st_w1,
2031                         format_w1,
2032                         win1_dsp_yaddr,
2033                         ovl ? "win0 on the top of win1\n" :
2034                         "win1 on the top of win0\n");
2035 }
2036
2037 static int rk312x_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
2038 {
2039         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2040                                                     struct lcdc_device,
2041                                                     driver);
2042         int *cbase = (int *)lcdc_dev->regs;
2043         int *regsbak = (int *)lcdc_dev->regsbak;
2044         int i, j;
2045
2046         printk("back up reg:\n");
2047         for (i = 0; i <= (0xDC >> 4); i++) {
2048                 for (j = 0; j < 4; j++)
2049                         printk("%08x  ", *(regsbak + i * 4 + j));
2050                 printk("\n");
2051         }
2052
2053         printk("lcdc reg:\n");
2054         for (i = 0; i <= (0xDC >> 4); i++) {
2055                 for (j = 0; j < 4; j++)
2056                         printk("%08x  ", readl_relaxed(cbase + i * 4 + j));
2057                 printk("\n");
2058         }
2059         return 0;
2060 }
2061
2062 static int rk312x_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
2063 {
2064         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2065                                                     struct lcdc_device, driver);
2066         if (lcdc_dev->soc_type == VOP_RK312X) {
2067                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
2068                              v_DIRECT_PATH_EN(open));
2069                 lcdc_cfg_done(lcdc_dev);
2070         }
2071         return 0;
2072 }
2073
2074 static int rk312x_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
2075 {
2076         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2077                                                     struct lcdc_device, driver);
2078
2079         if (lcdc_dev->soc_type == VOP_RK312X) {
2080                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_LAYER,
2081                              v_DIRECT_PATH_LAYER(win_id));
2082                 lcdc_cfg_done(lcdc_dev);
2083         }
2084         return 0;
2085
2086 }
2087
2088 static int rk312x_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
2089 {
2090         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2091                                                     struct lcdc_device, driver);
2092         int ovl = 0;
2093
2094         if (lcdc_dev->soc_type == VOP_RK312X)
2095                 ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
2096
2097         return ovl;
2098 }
2099
2100 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
2101         .open = rk312x_lcdc_open,
2102         .load_screen = rk312x_load_screen,
2103         .set_par = rk312x_lcdc_set_par,
2104         .pan_display = rk312x_lcdc_pan_display,
2105         .blank = rk312x_lcdc_blank,
2106         .ioctl = rk312x_lcdc_ioctl,
2107         .get_win_state = rk312x_lcdc_get_win_state,
2108         .ovl_mgr = rk312x_lcdc_ovl_mgr,
2109         .get_disp_info = rk312x_lcdc_get_disp_info,
2110         .fps_mgr = rk312x_lcdc_fps_mgr,
2111         .fb_get_win_id = rk312x_lcdc_get_win_id,
2112         .fb_win_remap = rk312x_fb_win_remap,
2113         .poll_vblank = rk312x_lcdc_poll_vblank,
2114         .get_dsp_addr = rk312x_lcdc_get_dsp_addr,
2115         .cfg_done = rk312x_lcdc_cfg_done,
2116         .dump_reg = rk312x_lcdc_reg_dump,
2117         .dpi_open = rk312x_lcdc_dpi_open,
2118         .dpi_win_sel = rk312x_lcdc_dpi_win_sel,
2119         .dpi_status = rk312x_lcdc_dpi_status,
2120         .set_dsp_bcsh_hue = rk312x_lcdc_set_bcsh_hue,
2121         .set_dsp_bcsh_bcs = rk312x_lcdc_set_bcsh_bcs,
2122         .get_dsp_bcsh_hue = rk312x_lcdc_get_bcsh_hue,
2123         .get_dsp_bcsh_bcs = rk312x_lcdc_get_bcsh_bcs,
2124         .open_bcsh = rk312x_lcdc_open_bcsh,
2125         .set_screen_scaler = rk312x_lcdc_set_scaler,
2126         .set_hwc_lut = rk312x_lcdc_set_hwc_lut,
2127         .set_irq_to_cpu = rk312x_lcdc_set_irq_to_cpu,
2128 };
2129 #if 0
2130 static const struct rk_lcdc_drvdata rk3036_lcdc_drvdata = {
2131         .soc_type = VOP_RK3036,
2132 };
2133 #endif
2134 static const struct rk_lcdc_drvdata rk312x_lcdc_drvdata = {
2135         .soc_type = VOP_RK312X,
2136 };
2137
2138 #if defined(CONFIG_OF)
2139 static const struct of_device_id rk312x_lcdc_dt_ids[] = {
2140 #if 0
2141         {
2142                 .compatible = "rockchip,rk3036-lcdc",
2143                 .data = (void *)&rk3036_lcdc_drvdata,
2144         },
2145 #endif
2146         {
2147                 .compatible = "rockchip,rk312x-lcdc",
2148                 .data = (void *)&rk312x_lcdc_drvdata,
2149         },
2150 };
2151 #endif
2152
2153 static int rk312x_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
2154 {
2155         struct device_node *np = lcdc_dev->dev->of_node;
2156         const struct of_device_id *match;
2157         const struct rk_lcdc_drvdata *lcdc_drvdata;
2158         int val;
2159
2160 #if defined(CONFIG_ROCKCHIP_IOMMU)
2161         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
2162                 lcdc_dev->driver.iommu_enabled = 0;
2163         else
2164                 lcdc_dev->driver.iommu_enabled = val;
2165 #else
2166         lcdc_dev->driver.iommu_enabled = 0;
2167 #endif
2168
2169         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
2170                 lcdc_dev->driver.fb_win_map = FB_DEFAULT_ORDER;
2171         else
2172                 lcdc_dev->driver.fb_win_map = val;
2173
2174         match = of_match_node(rk312x_lcdc_dt_ids, np);
2175         if (match) {
2176                 lcdc_drvdata = (const struct rk_lcdc_drvdata *)match->data;
2177                 lcdc_dev->soc_type = lcdc_drvdata->soc_type;
2178         } else {
2179                 return PTR_ERR(match);
2180         }
2181
2182         return 0;
2183 }
2184
2185 static int rk312x_lcdc_probe(struct platform_device *pdev)
2186 {
2187         struct lcdc_device *lcdc_dev = NULL;
2188         struct rk_lcdc_driver *dev_drv;
2189         struct device *dev = &pdev->dev;
2190         struct resource *res;
2191         int ret;
2192
2193         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
2194         if (!lcdc_dev) {
2195                 dev_err(&pdev->dev, "rk312x lcdc device kzalloc fail!\n");
2196                 return -ENOMEM;
2197         }
2198         platform_set_drvdata(pdev, lcdc_dev);
2199         lcdc_dev->dev = dev;
2200         if (rk312x_lcdc_parse_dt(lcdc_dev)) {
2201                 dev_err(lcdc_dev->dev, "rk312x lcdc parse dt failed!\n");
2202                 goto err_parse_dt;
2203         }
2204
2205         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2206         lcdc_dev->reg_phy_base = res->start;
2207         lcdc_dev->len = resource_size(res);
2208         lcdc_dev->regs = devm_ioremap_resource(dev, res);
2209         if (IS_ERR(lcdc_dev->regs)) {
2210                 ret = PTR_ERR(lcdc_dev->regs);
2211                 goto err_remap_reg;
2212         }
2213
2214         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
2215         if (IS_ERR(lcdc_dev->regsbak)) {
2216                 dev_err(&pdev->dev, "rk312x lcdc device kmalloc fail!\n");
2217                 ret = PTR_ERR(lcdc_dev->regsbak);
2218                 goto err_remap_reg;
2219         }
2220         lcdc_dev->hwc_lut_addr_base = (lcdc_dev->regs + HWC_LUT_ADDR);
2221         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + DSP_LUT_ADDR);
2222         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
2223         dev_drv = &lcdc_dev->driver;
2224         dev_drv->dev = dev;
2225         dev_drv->prop = PRMRY;
2226         dev_drv->id = lcdc_dev->id;
2227         dev_drv->ops = &lcdc_drv_ops;
2228         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
2229         spin_lock_init(&lcdc_dev->reg_lock);
2230
2231         lcdc_dev->irq = platform_get_irq(pdev, 0);
2232         if (lcdc_dev->irq < 0) {
2233                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
2234                         lcdc_dev->id);
2235                 ret = -ENXIO;
2236                 goto err_request_irq;
2237         }
2238
2239         ret = devm_request_irq(dev, lcdc_dev->irq, rk312x_lcdc_isr,
2240                                IRQF_DISABLED | IRQF_SHARED, dev_name(dev), lcdc_dev);
2241         if (ret) {
2242                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
2243                         lcdc_dev->irq, ret);
2244                 goto err_request_irq;
2245         }
2246
2247         if (dev_drv->iommu_enabled)
2248                 strcpy(dev_drv->mmu_dts_name, VOP_IOMMU_COMPATIBLE_NAME);
2249
2250         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
2251         if (ret < 0) {
2252                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
2253                 goto err_register_fb;
2254         }
2255         lcdc_dev->screen = dev_drv->screen0;
2256
2257         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
2258                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
2259         return 0;
2260
2261 err_register_fb:
2262 err_request_irq:
2263         devm_kfree(lcdc_dev->dev, lcdc_dev->regsbak);
2264 err_remap_reg:
2265 err_parse_dt:
2266         devm_kfree(&pdev->dev, lcdc_dev);
2267         return ret;
2268 }
2269
2270 #if defined(CONFIG_PM)
2271 static int rk312x_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
2272 {
2273         return 0;
2274 }
2275
2276 static int rk312x_lcdc_resume(struct platform_device *pdev)
2277 {
2278         return 0;
2279 }
2280 #else
2281 #define rk312x_lcdc_suspend NULL
2282 #define rk312x_lcdc_resume  NULL
2283 #endif
2284
2285 static int rk312x_lcdc_remove(struct platform_device *pdev)
2286 {
2287         return 0;
2288 }
2289
2290 static void rk312x_lcdc_shutdown(struct platform_device *pdev)
2291 {
2292         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
2293
2294         rk312x_lcdc_deinit(lcdc_dev);
2295         rk312x_lcdc_clk_disable(lcdc_dev);
2296         rk_disp_pwr_disable(&lcdc_dev->driver);
2297 }
2298
2299 static struct platform_driver rk312x_lcdc_driver = {
2300         .probe = rk312x_lcdc_probe,
2301         .remove = rk312x_lcdc_remove,
2302         .driver = {
2303                    .name = "rk312x-lcdc",
2304                    .owner = THIS_MODULE,
2305                    .of_match_table = of_match_ptr(rk312x_lcdc_dt_ids),
2306                    },
2307         .suspend = rk312x_lcdc_suspend,
2308         .resume = rk312x_lcdc_resume,
2309         .shutdown = rk312x_lcdc_shutdown,
2310 };
2311
2312 static int __init rk312x_lcdc_module_init(void)
2313 {
2314         return platform_driver_register(&rk312x_lcdc_driver);
2315 }
2316
2317 static void __exit rk312x_lcdc_module_exit(void)
2318 {
2319         platform_driver_unregister(&rk312x_lcdc_driver);
2320 }
2321
2322 fs_initcall(rk312x_lcdc_module_init);
2323 module_exit(rk312x_lcdc_module_exit);