drivers/video/rockchip/lcdc/rk312x_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk312x_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  * Author:      zhuangwenlong<zwl@rock-chips.com>
   6  *              zhengyang<zhengyang@rock-chips.com>
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/string.h>
  22 #include <linux/mm.h>
  23 #include <linux/slab.h>
  24 #include <linux/device.h>
  25 #include <linux/delay.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <asm/div64.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37 #include <linux/rockchip-iovmm.h>
  38 #include "rk312x_lcdc.h"
  39 #include <linux/rockchip/dvfs.h>
  40
  41 static int dbg_thresd;
  42 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  43
  44 #define DBG(level, x...) do {                   \
  45         if (unlikely(dbg_thresd >= level))      \
  46                 pr_info(KERN_INFO x); \
  47                         } while (0)
  48
  49 #define grf_writel(offset, v)   do { \
  50                         writel_relaxed(v, RK_GRF_VIRT + offset); \
  51                         dsb(); \
  52                         } while (0)
  53
  54 static struct rk_lcdc_win lcdc_win[] = {
  55         [0] = {
  56                .name = "win0",
  57                .id = 0,
  58                .support_3d = false,
  59                },
  60         [1] = {
  61                .name = "win1",
  62                .id = 1,
  63                .support_3d = false,
  64                },
  65         [2] = {
  66                .name = "hwc",
  67                .id = 2,
  68                .support_3d = false,
  69                },
  70 };
  71
  72 static irqreturn_t rk312x_lcdc_isr(int irq, void *dev_id)
  73 {
  74         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
  75         ktime_t timestamp = ktime_get();
  76         u32 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
  77
  78         if (int_reg & m_FS_INT_STA) {
  79                 timestamp = ktime_get();
  80                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR,
  81                              v_FS_INT_CLEAR(1));
  82                 /*if (lcdc_dev->driver.wait_fs) {*/
  83                 if (0) {
  84                         spin_lock(&(lcdc_dev->driver.cpl_lock));
  85                         complete(&(lcdc_dev->driver.frame_done));
  86                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
  87                 }
  88                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
  89                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
  90
  91         } else if (int_reg & m_LF_INT_STA) {
  92                 lcdc_dev->driver.frame_time.last_framedone_t =
  93                                 lcdc_dev->driver.frame_time.framedone_t;
  94                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
  95                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
  96                              v_LF_INT_CLEAR(1));
  97         }
  98
  99 #ifdef LCDC_IRQ_EMPTY_DEBUG
 100         if (int_reg & m_WIN0_EMPTY_INT_STA) {
 101                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_WIN0_EMPTY_INT_CLEAR,
 102                              v_WIN0_EMPTY_INT_CLEAR(1));
 103                 dev_info(lcdc_dev->dev, "win0 empty irq\n");
 104         } else if (int_reg & m_WIN1_EMPTY_INT_STA) {
 105                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_WIN1_EMPTY_INT_CLEAR,
 106                              v_WIN1_EMPTY_INT_CLEAR(1));
 107                 dev_info(lcdc_dev->dev, "win1 empty irq\n");
 108         }
 109 #endif
 110
 111         return IRQ_HANDLED;
 112 }
 113
 114 static int rk312x_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 115 {
 116 #ifdef CONFIG_RK_FPGA
 117         lcdc_dev->clk_on = 1;
 118         return 0;
 119 #endif
 120         if (!lcdc_dev->clk_on) {
 121                 clk_prepare_enable(lcdc_dev->hclk);
 122                 clk_prepare_enable(lcdc_dev->dclk);
 123                 clk_prepare_enable(lcdc_dev->aclk);
 124                 clk_prepare_enable(lcdc_dev->pd);
 125                 spin_lock(&lcdc_dev->reg_lock);
 126                 lcdc_dev->clk_on = 1;
 127                 spin_unlock(&lcdc_dev->reg_lock);
 128         }
 129
 130         return 0;
 131 }
 132
 133 static int rk312x_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 134 {
 135 #ifdef CONFIG_RK_FPGA
 136         lcdc_dev->clk_on = 0;
 137         return 0;
 138 #endif
 139         if (lcdc_dev->clk_on) {
 140                 spin_lock(&lcdc_dev->reg_lock);
 141                 lcdc_dev->clk_on = 0;
 142                 spin_unlock(&lcdc_dev->reg_lock);
 143                 mdelay(25);
 144                 clk_disable_unprepare(lcdc_dev->dclk);
 145                 clk_disable_unprepare(lcdc_dev->hclk);
 146                 clk_disable_unprepare(lcdc_dev->aclk);
 147                 clk_disable_unprepare(lcdc_dev->pd);
 148         }
 149
 150         return 0;
 151 }
 152
 153 static int rk312x_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
 154 {
 155         u32 mask, val;
 156         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 157                                                     struct lcdc_device, driver);
 158         /*struct rk_screen *screen = dev_drv->cur_screen;*/
 159
 160         spin_lock(&lcdc_dev->reg_lock);
 161         if (likely(lcdc_dev->clk_on)) {
 162                         mask = m_FS_INT_CLEAR | m_FS_INT_EN |
 163                         m_LF_INT_CLEAR | m_LF_INT_EN |
 164                         m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN;
 165                 val = v_FS_INT_CLEAR(1) | v_FS_INT_EN(1) |
 166                         v_LF_INT_CLEAR(1) | v_LF_INT_EN(1) |
 167                         v_BUS_ERR_INT_CLEAR(1) | v_BUS_ERR_INT_EN(0);
 168                 #if 0
 169                         mask |= m_LF_INT_NUM;
 170                         val  |= v_LF_INT_NUM(screen->mode.vsync_len +
 171                                                 screen->mode.upper_margin +
 172                                                 screen->mode.yres)
 173                 #endif
 174 #ifdef LCDC_IRQ_EMPTY_DEBUG
 175                 mask |= m_WIN0_EMPTY_INT_EN | m_WIN1_EMPTY_INT_EN;
 176                 val |= v_WIN0_EMPTY_INT_EN(1) | v_WIN1_EMPTY_INT_EN(1);
 177 #endif
 178
 179                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 180                 spin_unlock(&lcdc_dev->reg_lock);
 181         } else {
 182                 spin_unlock(&lcdc_dev->reg_lock);
 183         }
 184
 185         return 0;
 186 }
 187
 188 static int rk312x_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 189 {
 190         u32 mask, val;
 191
 192         spin_lock(&lcdc_dev->reg_lock);
 193         if (likely(lcdc_dev->clk_on)) {
 194                 mask = m_FS_INT_CLEAR | m_FS_INT_EN |
 195                         m_LF_INT_CLEAR | m_LF_INT_EN |
 196                         m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN;
 197                 val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0) |
 198                         v_LF_INT_CLEAR(0) | v_LF_INT_EN(0) |
 199                         v_BUS_ERR_INT_CLEAR(0) | v_BUS_ERR_INT_EN(0);
 200 #ifdef LCDC_IRQ_EMPTY_DEBUG
 201                 mask |= m_WIN0_EMPTY_INT_EN | m_WIN1_EMPTY_INT_EN;
 202                 val |= v_WIN0_EMPTY_INT_EN(0) | v_WIN1_EMPTY_INT_EN(0);
 203 #endif
 204
 205                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 206                 spin_unlock(&lcdc_dev->reg_lock);
 207         } else {
 208                 spin_unlock(&lcdc_dev->reg_lock);
 209         }
 210         mdelay(1);
 211         return 0;
 212 }
 213
 214
 215 static int win0_set_addr(struct lcdc_device *lcdc_dev, u32 addr)
 216 {
 217         spin_lock(&lcdc_dev->reg_lock);
 218         lcdc_writel(lcdc_dev, WIN0_YRGB_MST, addr);
 219         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN, v_WIN0_EN(1));
 220         lcdc_cfg_done(lcdc_dev);
 221         spin_unlock(&lcdc_dev->reg_lock);
 222
 223         return 0;
 224 }
 225
 226 static int win1_set_addr(struct lcdc_device *lcdc_dev, u32 addr)
 227 {
 228         spin_lock(&lcdc_dev->reg_lock);
 229         if (lcdc_dev->soc_type == VOP_RK3036)
 230                 lcdc_writel(lcdc_dev, WIN1_MST, addr);
 231         else
 232                 lcdc_writel(lcdc_dev, WIN1_MST_RK312X, addr);
 233         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN1_EN, v_WIN1_EN(1));
 234         lcdc_cfg_done(lcdc_dev);
 235         spin_unlock(&lcdc_dev->reg_lock);
 236         return 0;
 237 }
 238
 239 int rk312x_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
 240                                     int win_id, u32 addr)
 241 {
 242         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 243                                 struct lcdc_device, driver);
 244         if (win_id == 0)
 245                 win0_set_addr(lcdc_dev, addr);
 246         else
 247                 win1_set_addr(lcdc_dev, addr);
 248
 249         return 0;
 250 }
 251
 252 static void rk_lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 253 {
 254         int reg = 0;
 255         u32 val = 0;
 256         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 257         struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1];
 258
 259         spin_lock(&lcdc_dev->reg_lock);
 260         for (reg = 0; reg < 0xe0; reg += 4) {
 261                 val = lcdc_readl_backup(lcdc_dev, reg);
 262                 if (reg == WIN0_ACT_INFO) {
 263                         win0->area[0].xact = (val & m_ACT_WIDTH)+1;
 264                         win0->area[0].yact = ((val & m_ACT_HEIGHT)>>16)+1;
 265                 }
 266
 267                 if (lcdc_dev->soc_type == VOP_RK312X) {
 268                         if (reg == WIN1_DSP_INFO_RK312X) {
 269                                 win1->area[0].xact = (val & m_DSP_WIDTH) + 1;
 270                                 win1->area[0].yact =
 271                                         ((val & m_DSP_HEIGHT) >> 16) + 1;
 272                         }
 273                 } else {
 274                         if (reg == WIN1_ACT_INFO) {
 275                                 win1->area[0].xact = (val & m_ACT_WIDTH) + 1;
 276                                 win1->area[0].yact =
 277                                         ((val & m_ACT_HEIGHT) >> 16) + 1;
 278                         }
 279                 }
 280         }
 281         spin_unlock(&lcdc_dev->reg_lock);
 282 }
 283
 284 static int rk312x_lcdc_alpha_cfg(struct lcdc_device *lcdc_dev)
 285 {
 286         int win0_top = 0;
 287         u32 mask, val;
 288         enum data_format win0_format = lcdc_dev->driver.win[0]->area[0].format;
 289         enum data_format win1_format = lcdc_dev->driver.win[1]->area[0].format;
 290
 291         int win0_alpha_en = ((win0_format == ARGB888) ||
 292                                 (win0_format == ABGR888)) ? 1 : 0;
 293         int win1_alpha_en = ((win1_format == ARGB888) ||
 294                                 (win1_format == ABGR888)) ? 1 : 0;
 295         int atv_layer_cnt = lcdc_dev->driver.win[0]->state +
 296                         lcdc_dev->driver.win[1]->state;
 297         u32 *_pv = (u32 *)lcdc_dev->regsbak;
 298
 299         _pv += (DSP_CTRL0 >> 2);
 300         win0_top = ((*_pv) & (m_WIN0_TOP)) >> 8;
 301         if (win0_top && (atv_layer_cnt >= 2) && (win0_alpha_en)) {
 302                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 303                 val = v_WIN0_ALPHA_EN(1) | v_WIN1_ALPHA_EN(0);
 304                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 305
 306                 mask = m_WIN0_ALPHA_MODE |
 307                                 m_ALPHA_MODE_SEL0 | m_ALPHA_MODE_SEL1;
 308                 val = v_WIN0_ALPHA_MODE(1) |
 309                                 v_ALPHA_MODE_SEL0(1) | v_ALPHA_MODE_SEL1(0);
 310                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 311                 /*this vop bg layer not support yuv domain overlay,so bg val
 312                 have to set 0x800a80 equeal to 0x000000 at rgb domian,after
 313                 android start we recover to 0x00000*/
 314                 mask = m_BG_COLOR;
 315                 val = v_BG_COLOR(0x000000);
 316                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
 317         } else if ((!win0_top) && (atv_layer_cnt >= 2) &&
 318                                 (win1_alpha_en)) {
 319                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 320                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(1);
 321                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 322
 323                 mask = m_WIN1_ALPHA_MODE |
 324                                 m_ALPHA_MODE_SEL0 | m_ALPHA_MODE_SEL1;
 325                 if (lcdc_dev->driver.overlay_mode == VOP_YUV_DOMAIN)
 326                         val = v_WIN0_ALPHA_MODE(1) |
 327                               v_ALPHA_MODE_SEL0(0) |
 328                               v_ALPHA_MODE_SEL1(0);
 329                 else
 330                         val = v_WIN1_ALPHA_MODE(1) |
 331                               v_ALPHA_MODE_SEL0(1) |
 332                               v_ALPHA_MODE_SEL1(0);
 333                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 334                 /*this vop bg layer not support yuv domain overlay,so bg val
 335                 have to set 0x800a80 equeal to 0x000000 at rgb domian,after
 336                 android start we recover to 0x00000*/
 337                 mask = m_BG_COLOR;
 338                 val = v_BG_COLOR(0x000000);
 339                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
 340         } else {
 341                 mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 342                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(0);
 343                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 344         }
 345
 346         if (lcdc_dev->driver.win[2]->state == 1) {
 347                 mask =  m_HWC_ALPAH_EN;
 348                 val = v_HWC_ALPAH_EN(1);
 349                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 350
 351                 mask =  m_HWC_ALPHA_MODE;
 352                 val = v_HWC_ALPHA_MODE(1);
 353                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 354         } else {
 355                 mask =  m_HWC_ALPAH_EN;
 356                 val = v_HWC_ALPAH_EN(0);
 357                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 358         }
 359
 360         return 0;
 361 }
 362
 363 static void lcdc_layer_csc_mode(struct lcdc_device *lcdc_dev,
 364                                 struct rk_lcdc_win *win)
 365 {
 366         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
 367         struct rk_screen *screen = dev_drv->cur_screen;
 368
 369         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
 370                 switch (win->area[0].fmt_cfg) {
 371                 case VOP_FORMAT_ARGB888:
 372                 case VOP_FORMAT_RGB888:
 373                 case VOP_FORMAT_RGB565:
 374                         if ((screen->mode.xres < 1280) &&
 375                             (screen->mode.yres < 720)) {
 376                                 win->csc_mode = VOP_R2Y_CSC_BT601;
 377                         } else {
 378                                 win->csc_mode = VOP_R2Y_CSC_BT709;
 379                         }
 380                         break;
 381                 default:
 382                         break;
 383                 }
 384                 if (win->id  == 0) {
 385                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_CSC_MODE,
 386                                      v_WIN0_CSC_MODE(win->csc_mode));
 387                 } else if (win->id  == 1) {
 388                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN1_CSC_MODE,
 389                                      v_WIN1_CSC_MODE(win->csc_mode));
 390                 }
 391         } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
 392                 switch (win->area[0].fmt_cfg) {
 393                 case VOP_FORMAT_YCBCR420:
 394                         if (win->id  == 0) {
 395                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
 396                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 397                                              m_WIN0_CSC_MODE,
 398                                         v_WIN0_CSC_MODE(win->csc_mode));
 399                         }
 400                         break;
 401                 default:
 402                         break;
 403                 }
 404         }
 405 }
 406
 407
 408 static void lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
 409                                    struct rk_lcdc_win *win)
 410 {
 411         u32 mask, val;
 412         int hwc_size;
 413
 414         if (win->state == 1) {
 415                 if (lcdc_dev->soc_type == VOP_RK312X)
 416                         lcdc_layer_csc_mode(lcdc_dev, win);
 417
 418                 if (win->id == 0) {
 419                         mask = m_WIN0_EN | m_WIN0_FORMAT | m_WIN0_RB_SWAP |
 420                                 m_WIN0_UV_SWAP;
 421                         val = v_WIN0_EN(win->state) |
 422                                 v_WIN0_FORMAT(win->area[0].fmt_cfg) |
 423                                 v_WIN0_RB_SWAP(win->area[0].swap_rb) |
 424                                 v_WIN0_UV_SWAP(win->area[0].swap_uv);
 425                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 426                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB,
 427                                     v_X_SCL_FACTOR(win->scale_yrgb_x) |
 428                                     v_Y_SCL_FACTOR(win->scale_yrgb_y));
 429                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR,
 430                                     v_X_SCL_FACTOR(win->scale_cbcr_x) |
 431                                     v_Y_SCL_FACTOR(win->scale_cbcr_y));
 432
 433                         lcdc_msk_reg(lcdc_dev, WIN0_VIR,
 434                                      m_YRGB_VIR | m_CBBR_VIR,
 435                                      v_YRGB_VIR(win->area[0].y_vir_stride) |
 436                                      v_CBCR_VIR(win->area[0].uv_vir_stride));
 437                         lcdc_writel(lcdc_dev, WIN0_ACT_INFO,
 438                                     v_ACT_WIDTH(win->area[0].xact) |
 439                                     v_ACT_HEIGHT(win->area[0].yact));
 440                         lcdc_writel(lcdc_dev, WIN0_DSP_ST,
 441                                     v_DSP_STX(win->area[0].dsp_stx) |
 442                                     v_DSP_STY(win->area[0].dsp_sty));
 443                         lcdc_writel(lcdc_dev, WIN0_DSP_INFO,
 444                                     v_DSP_WIDTH(win->area[0].xsize) |
 445                                     v_DSP_HEIGHT(win->area[0].ysize));
 446
 447                         lcdc_writel(lcdc_dev, WIN0_YRGB_MST,
 448                                     win->area[0].y_addr);
 449                         lcdc_writel(lcdc_dev, WIN0_CBR_MST,
 450                                     win->area[0].uv_addr);
 451                 } else if (win->id == 1) {
 452                         mask = m_WIN1_EN | m_WIN1_FORMAT | m_WIN1_RB_SWAP;
 453                         val = v_WIN1_EN(win->state) |
 454                                         v_WIN1_FORMAT(win->area[0].fmt_cfg) |
 455                                         v_WIN1_RB_SWAP(win->area[0].swap_rb);
 456                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 457                         /* rk312x unsupport win1 scale */
 458                         if (lcdc_dev->soc_type == VOP_RK3036) {
 459                                 lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_YRGB,
 460                                             v_X_SCL_FACTOR(win->scale_yrgb_x) |
 461                                             v_Y_SCL_FACTOR(win->scale_yrgb_y));
 462                                 lcdc_writel(lcdc_dev, WIN1_ACT_INFO,
 463                                             v_ACT_WIDTH(win->area[0].xact) |
 464                                             v_ACT_HEIGHT(win->area[0].yact));
 465                                 lcdc_writel(lcdc_dev, WIN1_DSP_INFO,
 466                                             v_DSP_WIDTH(win->area[0].xsize) |
 467                                             v_DSP_HEIGHT(win->area[0].ysize));
 468                                 lcdc_writel(lcdc_dev, WIN1_DSP_ST,
 469                                             v_DSP_STX(win->area[0].dsp_stx) |
 470                                             v_DSP_STY(win->area[0].dsp_sty));
 471                                 lcdc_writel(lcdc_dev,
 472                                             WIN1_MST, win->area[0].y_addr);
 473                         } else {
 474                                 lcdc_writel(lcdc_dev, WIN1_DSP_INFO_RK312X,
 475                                             v_DSP_WIDTH(win->area[0].xsize) |
 476                                             v_DSP_HEIGHT(win->area[0].ysize));
 477                                 lcdc_writel(lcdc_dev, WIN1_DSP_ST_RK312X,
 478                                             v_DSP_STX(win->area[0].dsp_stx) |
 479                                             v_DSP_STY(win->area[0].dsp_sty));
 480
 481                                 lcdc_writel(lcdc_dev,
 482                                             WIN1_MST_RK312X,
 483                                             win->area[0].y_addr);
 484                         }
 485
 486                         lcdc_msk_reg(lcdc_dev, WIN1_VIR, m_YRGB_VIR,
 487                                      v_YRGB_VIR(win->area[0].y_vir_stride));
 488
 489
 490                 } else if (win->id == 2) {
 491                         mask = m_HWC_EN | m_HWC_LODAD_EN;
 492                         val = v_HWC_EN(win->state) | v_HWC_LODAD_EN(1);
 493                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 494                         if ((win->area[0].xsize == 32) &&
 495                             (win->area[0].ysize == 32))
 496                                 hwc_size = 0;
 497                         else if ((win->area[0].xsize == 64) &&
 498                                  (win->area[0].ysize == 64))
 499                                 hwc_size = 1;
 500                         else
 501                                 dev_err(lcdc_dev->dev, "unsupport hwc size:x=%d,y=%d\n",
 502                                         win->area[0].xsize, win->area[0].ysize);
 503                         lcdc_writel(lcdc_dev, HWC_DSP_ST,
 504                                     v_DSP_STX(win->area[0].dsp_stx) |
 505                                     v_DSP_STY(win->area[0].dsp_sty));
 506
 507                         lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
 508                 }
 509         } else {
 510                 win->area[0].y_addr = 0;
 511                 win->area[0].uv_addr = 0;
 512                 if (win->id == 0) {
 513                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN,
 514                                      v_WIN0_EN(0));
 515                         lcdc_writel(lcdc_dev, WIN0_YRGB_MST,
 516                                     win->area[0].y_addr);
 517                         lcdc_writel(lcdc_dev, WIN0_CBR_MST,
 518                                     win->area[0].uv_addr);
 519                 } else if (win->id == 1) {
 520                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN1_EN,
 521                                      v_WIN1_EN(0));
 522                          lcdc_writel(lcdc_dev, WIN1_MST, win->area[0].y_addr);
 523                 } else if (win->id == 2) {
 524                         lcdc_msk_reg(lcdc_dev,
 525                                      SYS_CTRL, m_HWC_EN | m_HWC_LODAD_EN,
 526                                      v_HWC_EN(0) | v_HWC_LODAD_EN(0));
 527                         lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
 528                 }
 529         }
 530         rk312x_lcdc_alpha_cfg(lcdc_dev);
 531 }
 532
 533 static void lcdc_layer_enable(struct lcdc_device *lcdc_dev, unsigned int win_id,
 534                               bool open)
 535 {
 536         spin_lock(&lcdc_dev->reg_lock);
 537         if (likely(lcdc_dev->clk_on) &&
 538             lcdc_dev->driver.win[win_id]->state != open) {
 539                 if (open) {
 540                         if (!lcdc_dev->atv_layer_cnt) {
 541                                 dev_info(lcdc_dev->dev,
 542                                          "wakeup from standby!\n");
 543                                 lcdc_dev->standby = 0;
 544                         }
 545                         lcdc_dev->atv_layer_cnt  |= (1 << win_id);
 546                 } else if ((lcdc_dev->atv_layer_cnt & (1 << win_id)) && (!open)) {
 547                          lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
 548                 }
 549                 lcdc_dev->driver.win[win_id]->state = open;
 550                 if (!open) {
 551                         lcdc_layer_update_regs(lcdc_dev,
 552                                                lcdc_dev->driver.win[win_id]);
 553                         lcdc_cfg_done(lcdc_dev);
 554                 }
 555                 /*if no layer used,disable lcdc */
 556                 if (!lcdc_dev->atv_layer_cnt) {
 557                         dev_info(lcdc_dev->dev,
 558                                  "no layer is used,go to standby!\n");
 559                         lcdc_dev->standby = 1;
 560                 }
 561         }
 562         spin_unlock(&lcdc_dev->reg_lock);
 563 }
 564 /*
 565 static int rk312x_lcdc_reg_update(struct rk_lcdc_driver *dev_drv)
 566 {
 567         struct lcdc_device *lcdc_dev =
 568             container_of(dev_drv, struct lcdc_device, driver);
 569         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 570         struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1];
 571         int timeout;
 572         unsigned long flags;
 573         spin_lock(&lcdc_dev->reg_lock);
 574         if (likely(lcdc_dev->clk_on)) {
 575                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
 576                              v_LCDC_STANDBY(lcdc_dev->standby));
 577                 lcdc_layer_update_regs(lcdc_dev, win0);
 578                 lcdc_layer_update_regs(lcdc_dev, win1);
 579                 rk312x_lcdc_alpha_cfg(lcdc_dev);
 580                 lcdc_cfg_done(lcdc_dev);
 581
 582         }
 583         spin_unlock(&lcdc_dev->reg_lock);
 584         //if (dev_drv->wait_fs) {
 585         if (0) {
 586                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
 587                 init_completion(&dev_drv->frame_done);
 588                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
 589                 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
 590                                                       msecs_to_jiffies
 591                                                       (dev_drv->cur_screen->ft +
 592                                                        5));
 593                 if (!timeout && (!dev_drv->frame_done.done)) {
 594                         dev_warn(lcdc_dev->dev,
 595                                  "wait for new frame start time out!\n");
 596                         return -ETIMEDOUT;
 597                 }
 598         }
 599         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
 600         return 0;
 601
 602 }*/
 603
 604 static void rk312x_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
 605 {
 606         memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0xe0);
 607 }
 608
 609 static int rk312x_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
 610 {
 611         u32 mask, val;
 612         struct lcdc_device *lcdc_dev =
 613             container_of(dev_drv, struct lcdc_device, driver);
 614
 615         /*spin_lock(&lcdc_dev->reg_lock);*/
 616         if (likely(lcdc_dev->clk_on)) {
 617                 mask = m_MMU_EN | m_AXI_MAX_OUTSTANDING_EN |
 618                         m_AXI_OUTSTANDING_MAX_NUM;
 619                 val = v_MMU_EN(1) | v_AXI_OUTSTANDING_MAX_NUM(31) |
 620                         v_AXI_MAX_OUTSTANDING_EN(1);
 621                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 622         }
 623         /*spin_unlock(&lcdc_dev->reg_lock);*/
 624         #if defined(CONFIG_ROCKCHIP_IOMMU)
 625         if (dev_drv->iommu_enabled) {
 626                 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
 627                         lcdc_dev->iommu_status = 1;
 628                         rockchip_iovmm_activate(dev_drv->dev);
 629                 }
 630         }
 631         #endif
 632
 633         return 0;
 634 }
 635
 636 static int rk312x_lcdc_set_hwc_lut(struct rk_lcdc_driver *dev_drv,
 637                                    int *hwc_lut, int mode)
 638 {
 639         int i = 0;
 640         int __iomem *c;
 641         int v;
 642         int len = 256*4;
 643         struct lcdc_device *lcdc_dev =
 644                         container_of(dev_drv, struct lcdc_device, driver);
 645         if (dev_drv->hwc_lut == NULL)
 646                 dev_drv->hwc_lut = devm_kzalloc(lcdc_dev->dev, len, GFP_KERNEL);
 647
 648         spin_lock(&lcdc_dev->reg_lock);
 649         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(0));
 650         lcdc_cfg_done(lcdc_dev);
 651         mdelay(25);
 652         for (i = 0; i < 256; i++) {
 653                 if (mode == 1)
 654                         dev_drv->hwc_lut[i] = hwc_lut[i];
 655                 v = dev_drv->hwc_lut[i];
 656                 c = lcdc_dev->hwc_lut_addr_base + i;
 657                 writel_relaxed(v, c);
 658         }
 659         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(1));
 660         lcdc_cfg_done(lcdc_dev);
 661         spin_unlock(&lcdc_dev->reg_lock);
 662
 663         return 0;
 664 }
 665
 666 static int rk312x_lcdc_set_lut(struct rk_lcdc_driver *dev_drv,
 667                                int *dsp_lut)
 668 {
 669         int i = 0;
 670         int __iomem *c;
 671         int v;
 672         struct lcdc_device *lcdc_dev =
 673                 container_of(dev_drv, struct lcdc_device, driver);
 674
 675         if (!dsp_lut)
 676                 return 0;
 677
 678         spin_lock(&lcdc_dev->reg_lock);
 679         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
 680         lcdc_cfg_done(lcdc_dev);
 681         mdelay(25);
 682         for (i = 0; i < 256; i++) {
 683                 v = dsp_lut[i];
 684                 c = lcdc_dev->dsp_lut_addr_base + i;
 685                 writel_relaxed(v, c);
 686         }
 687         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
 688         lcdc_cfg_done(lcdc_dev);
 689         spin_unlock(&lcdc_dev->reg_lock);
 690         return 0;
 691 }
 692
 693 static int rk312x_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv,
 694                                     int reset_rate)
 695 {
 696 #ifdef CONFIG_RK_FPGA
 697         return 0;
 698 #endif
 699         int ret, fps;
 700         struct lcdc_device *lcdc_dev =
 701             container_of(dev_drv, struct lcdc_device, driver);
 702         struct rk_screen *screen = dev_drv->cur_screen;
 703
 704         if (reset_rate)
 705                 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
 706         if (ret)
 707                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
 708         lcdc_dev->pixclock =
 709             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
 710         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
 711
 712         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
 713         screen->ft = 1000 / fps;
 714         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
 715                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
 716         return 0;
 717 }
 718
 719 /********do basic init*********/
 720 static int rk312x_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 721 {
 722         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 723                                                     struct lcdc_device, driver);
 724         if (lcdc_dev->pre_init)
 725                 return 0;
 726
 727         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 728         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 729         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 730         lcdc_dev->sclk = devm_clk_get(lcdc_dev->dev, "sclk_lcdc");
 731         lcdc_dev->pd   = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
 732         lcdc_dev->pll_sclk = devm_clk_get(lcdc_dev->dev, "sclk_pll");
 733
 734         if (/*IS_ERR(lcdc_dev->pd) || */ (IS_ERR(lcdc_dev->aclk)) ||
 735             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 736                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 737                         lcdc_dev->id);
 738         }
 739
 740         rk_disp_pwr_enable(dev_drv);
 741         rk312x_lcdc_clk_enable(lcdc_dev);
 742
 743         /* backup reg config at uboot */
 744         rk_lcdc_read_reg_defalut_cfg(lcdc_dev);
 745
 746         /* config for the FRC mode of dither down */
 747         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 748         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 749         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0x55aaaa55);
 750         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x55aaaa55);
 751         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 752         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 753
 754         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_AUTO_GATING_EN, v_AUTO_GATING_EN(0));
 755         lcdc_cfg_done(lcdc_dev);
 756         /*if (dev_drv->iommu_enabled)
 757                 {// disable all wins to workaround iommu pagefault
 758                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN | m_WIN1_EN,
 759                              v_WIN0_EN(0) | v_WIN1_EN(0));
 760                 lcdc_cfg_done(lcdc_dev);
 761                 while(lcdc_readl(lcdc_dev, SYS_CTRL) & (m_WIN0_EN | m_WIN1_EN));
 762         }*/
 763         if ((dev_drv->ops->open_bcsh) && (dev_drv->output_color == COLOR_YCBCR)) {
 764                 if (support_uboot_display())
 765                         dev_drv->bcsh_init_status = 1;
 766                 else
 767                         dev_drv->ops->open_bcsh(dev_drv, 1);
 768         }
 769         lcdc_dev->pre_init = true;
 770
 771         return 0;
 772 }
 773
 774 static void rk312x_lcdc_deinit(struct lcdc_device *lcdc_dev)
 775 {
 776         rk312x_lcdc_disable_irq(lcdc_dev);
 777 }
 778
 779 static u32 calc_sclk_freq(struct rk_screen *src_screen,
 780                           struct rk_screen *dst_screen)
 781 {
 782         u32 dsp_vtotal;
 783         u64 dsp_htotal;
 784         u32 dsp_in_vtotal;
 785         u64 dsp_in_htotal;
 786         u64 sclk_freq;
 787
 788         if (!src_screen || !dst_screen)
 789                 return 0;
 790
 791         dsp_vtotal = dst_screen->mode.yres;
 792         dsp_htotal = dst_screen->mode.left_margin + dst_screen->mode.hsync_len +
 793                         dst_screen->mode.xres + dst_screen->mode.right_margin;
 794         dsp_in_vtotal = src_screen->mode.yres;
 795         dsp_in_htotal = src_screen->mode.left_margin +
 796                         src_screen->mode.hsync_len +
 797                         src_screen->mode.xres + src_screen->mode.right_margin;
 798         sclk_freq = dsp_vtotal * dsp_htotal * src_screen->mode.pixclock;
 799         do_div(sclk_freq, dsp_in_vtotal * dsp_in_htotal);
 800
 801         return (u32)sclk_freq;
 802 }
 803
 804 #define SCLK_PLL_LIMIT          594000000
 805 #define GPU_FREQ_MAX_LIMIT      297000000
 806 #define GPU_FREQ_NEED           400000000
 807
 808 static u32 calc_sclk_pll_freq(u32 sclk_freq)
 809 {
 810         u32 multi_num;
 811
 812         if (sclk_freq < (SCLK_PLL_LIMIT / 10)) {
 813                 return (sclk_freq * 10);
 814         } else {
 815                 multi_num = GPU_FREQ_NEED / sclk_freq;
 816                 return (sclk_freq * multi_num);
 817         }
 818 }
 819
 820 static int calc_dsp_frm_vst_hst(struct rk_screen *src,
 821                                 struct rk_screen *dst, u32 sclk_freq)
 822 {
 823         u32 BP_in, BP_out;
 824         u32 v_scale_ratio;
 825         long long T_frm_st;
 826         u64 T_BP_in, T_BP_out, T_Delta, Tin;
 827         u32 src_pixclock, dst_pixclock;
 828         u64 temp;
 829         u32 dsp_htotal, dsp_vtotal, src_htotal, src_vtotal;
 830
 831         if (unlikely(!src) || unlikely(!dst))
 832                 return -1;
 833
 834         src_pixclock = div_u64(1000000000000llu, src->mode.pixclock);
 835         dst_pixclock = div_u64(1000000000000llu, sclk_freq);
 836         dsp_htotal = dst->mode.left_margin + dst->mode.hsync_len +
 837                      dst->mode.xres + dst->mode.right_margin;
 838         dsp_vtotal = dst->mode.upper_margin + dst->mode.vsync_len +
 839                      dst->mode.yres + dst->mode.lower_margin;
 840         src_htotal = src->mode.left_margin + src->mode.hsync_len +
 841                      src->mode.xres + src->mode.right_margin;
 842         src_vtotal = src->mode.upper_margin + src->mode.vsync_len +
 843                      src->mode.yres + src->mode.lower_margin;
 844         BP_in  = (src->mode.upper_margin + src->mode.vsync_len) * src_htotal +
 845                  src->mode.hsync_len + src->mode.left_margin;
 846         BP_out = (dst->mode.upper_margin + dst->mode.vsync_len) * dsp_htotal +
 847                  dst->mode.hsync_len + dst->mode.left_margin;
 848
 849         T_BP_in = BP_in * src_pixclock;
 850         T_BP_out = BP_out * dst_pixclock;
 851         Tin = src_vtotal * src_htotal * src_pixclock;
 852
 853         v_scale_ratio = src->mode.yres / dst->mode.yres;
 854         if (v_scale_ratio <= 2)
 855                 T_Delta = 5 * src_htotal * src_pixclock;
 856         else
 857                 T_Delta = 12 * src_htotal * src_pixclock;
 858
 859         if (T_BP_in + T_Delta > T_BP_out)
 860                 T_frm_st = (T_BP_in + T_Delta - T_BP_out);
 861         else
 862                 T_frm_st = Tin - (T_BP_out - (T_BP_in + T_Delta));
 863
 864         /* (T_frm_st = scl_vst * src_htotal * src_pixclock +
 865                                                 scl_hst * src_pixclock) */
 866         temp = do_div(T_frm_st, src_pixclock);
 867         temp = do_div(T_frm_st, src_htotal);
 868         dst->scl_hst = temp - 1;
 869         dst->scl_vst = T_frm_st;
 870
 871         return 0;
 872 }
 873
 874 static int rk312x_lcdc_set_scaler(struct rk_lcdc_driver *dev_drv,
 875                                   struct rk_screen *dst_screen, bool enable)
 876 {
 877         u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end;
 878         u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end;
 879         u32 dsp_hbor_end, dsp_hbor_st, dsp_vbor_end, dsp_vbor_st;
 880         u32 scl_v_factor, scl_h_factor;
 881         u32 dst_frame_hst, dst_frame_vst;
 882         u32 src_w, src_h, dst_w, dst_h;
 883         u16 bor_right = 0;
 884         u16 bor_left = 0;
 885         u16 bor_up = 0;
 886         u16 bor_down = 0;
 887         u32 pll_freq = 0;
 888         struct rk_screen *src;
 889         struct rk_screen *dst;
 890         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 891                                                     struct lcdc_device, driver);
 892         struct dvfs_node *gpu_clk = clk_get_dvfs_node("clk_gpu");
 893
 894         if (unlikely(!lcdc_dev->clk_on))
 895                 return 0;
 896
 897         if (!enable) {
 898                 spin_lock(&lcdc_dev->reg_lock);
 899                 lcdc_msk_reg(lcdc_dev, SCALER_CTRL,
 900                              m_SCALER_EN | m_SCALER_OUT_ZERO |
 901                                         m_SCALER_OUT_EN,
 902                                         v_SCALER_EN(0) | v_SCALER_OUT_ZERO(1) |
 903                                         v_SCALER_OUT_EN(0));
 904                 lcdc_cfg_done(lcdc_dev);
 905                 spin_unlock(&lcdc_dev->reg_lock);
 906                 if (lcdc_dev->sclk_on) {
 907                         clk_disable_unprepare(lcdc_dev->sclk);
 908                         lcdc_dev->sclk_on = false;
 909                 }
 910
 911                 /* switch pll freq as default when sclk is no used */
 912                 if (clk_get_rate(lcdc_dev->pll_sclk) != GPU_FREQ_NEED) {
 913                         dvfs_clk_enable_limit(gpu_clk, GPU_FREQ_MAX_LIMIT,
 914                                               GPU_FREQ_MAX_LIMIT);
 915                         clk_set_rate(lcdc_dev->pll_sclk, GPU_FREQ_NEED);
 916                         dvfs_clk_enable_limit(gpu_clk, 0, -1);
 917                 }
 918                 dev_dbg(lcdc_dev->dev, "%s: disable\n", __func__);
 919                 return 0;
 920         }
 921
 922         /*
 923          * rk312x used one lcdc to apply dual disp
 924          * hdmi screen is used for scaler src
 925          * prmry screen is used for scaler dst
 926          */
 927         dst = dst_screen;
 928         src = dev_drv->cur_screen;
 929         if (!dst || !src) {
 930                 dev_err(lcdc_dev->dev, "%s: dst screen is null!\n", __func__);
 931                 return -EINVAL;
 932         }
 933
 934         if (!lcdc_dev->sclk_on) {
 935                 clk_prepare_enable(lcdc_dev->sclk);
 936                 lcdc_dev->s_pixclock = calc_sclk_freq(src, dst);
 937                 pll_freq = calc_sclk_pll_freq(lcdc_dev->s_pixclock);
 938
 939                 /* limit gpu freq */
 940                 dvfs_clk_enable_limit(gpu_clk,
 941                                       GPU_FREQ_MAX_LIMIT,
 942                                       GPU_FREQ_MAX_LIMIT);
 943                 /* set pll freq */
 944                 clk_set_rate(lcdc_dev->pll_sclk, pll_freq);
 945                 /* cancel limit gpu freq */
 946                 dvfs_clk_enable_limit(gpu_clk, 0, -1);
 947
 948                 clk_set_rate(lcdc_dev->sclk, lcdc_dev->s_pixclock);
 949                 lcdc_dev->sclk_on = true;
 950                 dev_info(lcdc_dev->dev, "%s:sclk=%d\n", __func__,
 951                          lcdc_dev->s_pixclock);
 952         }
 953
 954         /* config scale timing */
 955         calc_dsp_frm_vst_hst(src, dst, lcdc_dev->s_pixclock);
 956         dst_frame_vst = dst->scl_vst;
 957         dst_frame_hst = dst->scl_hst;
 958
 959         dsp_htotal    = dst->mode.hsync_len + dst->mode.left_margin +
 960                         dst->mode.xres + dst->mode.right_margin;
 961         dsp_hs_end    = dst->mode.hsync_len;
 962
 963         dsp_vtotal    = dst->mode.vsync_len + dst->mode.upper_margin +
 964                         dst->mode.yres + dst->mode.lower_margin;
 965         dsp_vs_end    = dst->mode.vsync_len;
 966
 967         dsp_hbor_end  = dst->mode.hsync_len + dst->mode.left_margin +
 968                         dst->mode.xres;
 969         dsp_hbor_st   = dst->mode.hsync_len + dst->mode.left_margin;
 970         dsp_vbor_end  = dst->mode.vsync_len + dst->mode.upper_margin +
 971                         dst->mode.yres;
 972         dsp_vbor_st   = dst->mode.vsync_len + dst->mode.upper_margin;
 973
 974         dsp_hact_st   = dsp_hbor_st  + bor_left;
 975         dsp_hact_end  = dsp_hbor_end - bor_right;
 976         dsp_vact_st   = dsp_vbor_st  + bor_up;
 977         dsp_vact_end  = dsp_vbor_end - bor_down;
 978
 979         src_w = src->mode.xres;
 980         src_h = src->mode.yres;
 981         dst_w = dsp_hact_end - dsp_hact_st;
 982         dst_h = dsp_vact_end - dsp_vact_st;
 983
 984         /* calc scale factor */
 985         scl_h_factor = ((src_w - 1) << 12) / (dst_w - 1);
 986         scl_v_factor = ((src_h - 1) << 12) / (dst_h - 1);
 987
 988         spin_lock(&lcdc_dev->reg_lock);
 989         if (dst->color_mode != src->color_mode) {
 990                 /*dev_drv->output_color = dst->color_mode;
 991                 if (dev_drv->output_color == COLOR_YCBCR)
 992                         dev_drv->overlay_mode = VOP_YUV_DOMAIN;
 993                 else
 994                         dev_drv->overlay_mode = VOP_RGB_DOMAIN;
 995                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_SW_OVERLAY_MODE,
 996                              v_SW_OVERLAY_MODE(dev_drv->overlay_mode));*/
 997         }
 998
 999         lcdc_writel(lcdc_dev, SCALER_FACTOR,
1000                     v_SCALER_H_FACTOR(scl_h_factor) |
1001                     v_SCALER_V_FACTOR(scl_v_factor));
1002
1003         lcdc_writel(lcdc_dev, SCALER_FRAME_ST,
1004                     v_SCALER_FRAME_HST(dst_frame_hst) |
1005                     v_SCALER_FRAME_VST(dst_frame_vst));
1006         lcdc_writel(lcdc_dev, SCALER_DSP_HOR_TIMING,
1007                     v_SCALER_HS_END(dsp_hs_end) |
1008                     v_SCALER_HTOTAL(dsp_htotal));
1009         lcdc_writel(lcdc_dev, SCALER_DSP_HACT_ST_END,
1010                     v_SCALER_HAEP(dsp_hact_end) |
1011                     v_SCALER_HASP(dsp_hact_st));
1012         lcdc_writel(lcdc_dev, SCALER_DSP_VER_TIMING,
1013                     v_SCALER_VS_END(dsp_vs_end) |
1014                     v_SCALER_VTOTAL(dsp_vtotal));
1015         lcdc_writel(lcdc_dev, SCALER_DSP_VACT_ST_END,
1016                     v_SCALER_VAEP(dsp_vact_end) |
1017                     v_SCALER_VASP(dsp_vact_st));
1018         lcdc_writel(lcdc_dev, SCALER_DSP_HBOR_TIMING,
1019                     v_SCALER_HBOR_END(dsp_hbor_end) |
1020                     v_SCALER_HBOR_ST(dsp_hbor_st));
1021         lcdc_writel(lcdc_dev, SCALER_DSP_VBOR_TIMING,
1022                     v_SCALER_VBOR_END(dsp_vbor_end) |
1023                     v_SCALER_VBOR_ST(dsp_vbor_st));
1024         lcdc_msk_reg(lcdc_dev, SCALER_CTRL,
1025                      m_SCALER_VSYNC_VST | m_SCALER_VSYNC_MODE,
1026                      v_SCALER_VSYNC_VST(4) | v_SCALER_VSYNC_MODE(2));
1027         lcdc_msk_reg(lcdc_dev, SCALER_CTRL,
1028                      m_SCALER_EN | m_SCALER_OUT_ZERO |
1029                      m_SCALER_OUT_EN,
1030                      v_SCALER_EN(1) | v_SCALER_OUT_ZERO(0) |
1031                      v_SCALER_OUT_EN(1));
1032
1033         lcdc_cfg_done(lcdc_dev);
1034         spin_unlock(&lcdc_dev->reg_lock);
1035
1036         return 0;
1037 }
1038
1039 static void rk312x_lcdc_select_bcsh(struct rk_lcdc_driver *dev_drv,
1040                                     struct lcdc_device *lcdc_dev)
1041 {
1042         u32 bcsh_ctrl;
1043         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1044                 if (dev_drv->output_color == COLOR_YCBCR)/* bypass */
1045                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1046                                      m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1047                                      v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1048         else    /* YUV2RGB */
1049                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1050                              m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1051                              m_BCSH_R2Y_EN,
1052                              v_BCSH_Y2R_EN(1) |
1053                              v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1054                              v_BCSH_R2Y_EN(0));
1055         } else {        /* overlay_mode=VOP_RGB_DOMAIN */
1056                 if (dev_drv->output_color == COLOR_RGB) {
1057                         /* bypass */
1058                         bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1059                         if (((bcsh_ctrl&m_BCSH_EN) == 1) ||
1060                                 (dev_drv->bcsh.enable == 1))/*bcsh enabled*/
1061                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1062                                         m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1063                                         v_BCSH_R2Y_EN(1) | v_BCSH_Y2R_EN(1));
1064                         else/*bcsh disabled*/
1065                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1066                                         m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1067                                         v_BCSH_R2Y_EN(0) | v_BCSH_Y2R_EN(0));
1068                 } else  /* RGB2YUV */
1069                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1070                                      m_BCSH_R2Y_EN |
1071                                         m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1072                                         v_BCSH_R2Y_EN(1) |
1073                                         v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1074                                         v_BCSH_Y2R_EN(0));
1075                 }
1076 }
1077
1078 static int rk312x_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1079                                   u16 *yact, int *format, u32 *dsp_addr)
1080 {
1081         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1082                                                     struct lcdc_device, driver);
1083         u32 val;
1084
1085         spin_lock(&lcdc_dev->reg_lock);
1086
1087         val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1088         *xact = (val & m_ACT_WIDTH)+1;
1089         *yact = ((val & m_ACT_HEIGHT)>>16)+1;
1090
1091         val = lcdc_readl(lcdc_dev, SYS_CTRL);
1092
1093         *format = (val & m_WIN0_FORMAT) >> 3;
1094         *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1095
1096         spin_unlock(&lcdc_dev->reg_lock);
1097
1098         return 0;
1099 }
1100
1101 static int rk312x_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1102                               int format, u16 xact, u16 yact, u16 xvir)
1103 {
1104         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1105                                                     struct lcdc_device, driver);
1106         u32 val, mask;
1107
1108         mask = m_WIN0_FORMAT;
1109         val = v_WIN0_FORMAT(format);
1110         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1111
1112         lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_YRGB_VIR,
1113                         v_YRGB_VIR(xvir));
1114         lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_ACT_WIDTH(xact) |
1115                     v_ACT_HEIGHT(yact));
1116
1117         lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1118
1119         lcdc_cfg_done(lcdc_dev);
1120
1121         return 0;
1122 }
1123
1124 static int rk312x_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1125 {
1126         u16 face = 0;
1127         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1128                                                     struct lcdc_device, driver);
1129         struct rk_screen *screen = dev_drv->cur_screen;
1130         u16 right_margin = screen->mode.right_margin;
1131         u16 left_margin = screen->mode.left_margin;
1132         u16 lower_margin = screen->mode.lower_margin;
1133         u16 upper_margin = screen->mode.upper_margin;
1134         u16 x_res = screen->mode.xres;
1135         u16 y_res = screen->mode.yres;
1136         u32 mask, val;
1137
1138         spin_lock(&lcdc_dev->reg_lock);
1139         if (likely(lcdc_dev->clk_on)) {
1140                 lcdc_msk_reg(lcdc_dev, SYS_CTRL,
1141                              m_LCDC_STANDBY, v_LCDC_STANDBY(1));
1142                 lcdc_cfg_done(lcdc_dev);
1143                 mdelay(50);
1144                 /* Select output color domain */
1145                 /*dev_drv->output_color = screen->color_mode;
1146                 if (lcdc_dev->soc_type == VOP_RK312X) {
1147                         if (dev_drv->output_color == COLOR_YCBCR)
1148                                 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1149                         else
1150                                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1151                 } else {
1152                         dev_drv->output_color = COLOR_RGB;
1153                         dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1154                 }*/
1155                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1156                 /*something wrong at yuv domain*/
1157
1158                 switch (screen->type) {
1159                 case SCREEN_RGB:
1160                         if (lcdc_dev->soc_type == VOP_RK312X) {
1161                                 mask = m_RGB_DCLK_EN | m_RGB_DCLK_INVERT;
1162                                 val = v_RGB_DCLK_EN(1) | v_RGB_DCLK_INVERT(0);
1163                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
1164                         }
1165                         break;
1166                 case SCREEN_LVDS:
1167                         if (lcdc_dev->soc_type == VOP_RK312X) {
1168                                 mask = m_LVDS_DCLK_EN | m_LVDS_DCLK_INVERT;
1169                                 val = v_LVDS_DCLK_EN(1) | v_LVDS_DCLK_INVERT(1);
1170                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
1171                         }
1172                         break;
1173                 case SCREEN_MIPI:
1174                         if (lcdc_dev->soc_type == VOP_RK312X) {
1175                                 mask = m_MIPI_DCLK_EN | m_MIPI_DCLK_INVERT;
1176                                 val = v_MIPI_DCLK_EN(1) | v_MIPI_DCLK_INVERT(0);
1177                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
1178                         }
1179                         break;
1180                 case SCREEN_HDMI:
1181                         mask = m_HDMI_DCLK_EN;
1182                         val = v_HDMI_DCLK_EN(1);
1183                         if (screen->pixelrepeat) {
1184                                 mask |= m_CORE_CLK_DIV_EN;
1185                                 val |= v_CORE_CLK_DIV_EN(1);
1186                         } else {
1187                                 mask |= m_CORE_CLK_DIV_EN;
1188                                 val |= v_CORE_CLK_DIV_EN(0);
1189                         }
1190                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
1191                         if (lcdc_dev->soc_type == VOP_RK312X) {
1192                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1193                                      m_SW_UV_OFFSET_EN,
1194                                      v_SW_UV_OFFSET_EN(0));
1195                                 mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
1196                                        m_HDMI_DEN_POL;
1197                                 val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
1198                                       v_HDMI_VSYNC_POL(screen->pin_vsync) |
1199                                       v_HDMI_DEN_POL(screen->pin_den);
1200                                 lcdc_msk_reg(lcdc_dev, INT_SCALER, mask, val);
1201                         } else {
1202                                 mask = (1 << 4) | (1 << 5) | (1 << 6);
1203                                 val = (screen->pin_hsync << 4) |
1204                                         (screen->pin_vsync << 5) |
1205                                         (screen->pin_den << 6);
1206                                 grf_writel(RK3036_GRF_SOC_CON2,
1207                                            (mask << 16) | val);
1208                         }
1209                         rk312x_lcdc_select_bcsh(dev_drv,  lcdc_dev);
1210                         break;
1211                 case SCREEN_TVOUT:
1212                 case SCREEN_TVOUT_TEST:
1213                         mask = m_TVE_DAC_DCLK_EN;
1214                         val = v_TVE_DAC_DCLK_EN(1);
1215                         if (screen->pixelrepeat) {
1216                                 mask |= m_CORE_CLK_DIV_EN;
1217                                 val |= v_CORE_CLK_DIV_EN(1);
1218                         }
1219                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
1220                         if (x_res == 720 && y_res == 576)
1221                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_TVE_MODE,
1222                                              v_TVE_MODE(TV_PAL));
1223                         else if (x_res == 720 && y_res == 480)
1224                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_TVE_MODE,
1225                                              v_TVE_MODE(TV_NTSC));
1226                         else {
1227                                 dev_err(lcdc_dev->dev,
1228                                         "unsupported video timing!\n");
1229                                 return -1;
1230                         }
1231                         if (lcdc_dev->soc_type == VOP_RK312X) {
1232                                 if (screen->type == SCREEN_TVOUT_TEST)
1233                         /*for TVE index test,vop must ovarlay at yuv domain*/
1234                                         dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1235                                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1236                                                      m_SW_UV_OFFSET_EN,
1237                                                      v_SW_UV_OFFSET_EN(1));
1238
1239                         rk312x_lcdc_select_bcsh(dev_drv, lcdc_dev);
1240                         }
1241                         break;
1242                 default:
1243                         dev_err(lcdc_dev->dev, "un supported interface!\n");
1244                         break;
1245                 }
1246                 if (lcdc_dev->soc_type == VOP_RK312X) {
1247                         switch (dev_drv->screen0->face) {
1248                         case OUT_P565:
1249                                 face = OUT_P565;
1250                                 mask = m_DITHER_DOWN_EN |
1251                                        m_DITHER_DOWN_MODE |
1252                                        m_DITHER_DOWN_SEL;
1253                                 val = v_DITHER_DOWN_EN(1) |
1254                                       v_DITHER_DOWN_MODE(0) |
1255                                       v_DITHER_DOWN_SEL(1);
1256                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1257                                 break;
1258                         case OUT_P666:
1259                                 face = OUT_P666;
1260                                 mask = m_DITHER_DOWN_EN |
1261                                        m_DITHER_DOWN_MODE |
1262                                        m_DITHER_DOWN_SEL;
1263                                 val = v_DITHER_DOWN_EN(1) |
1264                                       v_DITHER_DOWN_MODE(1) |
1265                                       v_DITHER_DOWN_SEL(1);
1266                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1267                                 break;
1268                         case OUT_D888_P565:
1269                                 face = OUT_P888;
1270                                 mask = m_DITHER_DOWN_EN |
1271                                        m_DITHER_DOWN_MODE |
1272                                        m_DITHER_DOWN_SEL;
1273                                 val = v_DITHER_DOWN_EN(1) |
1274                                       v_DITHER_DOWN_MODE(0) |
1275                                       v_DITHER_DOWN_SEL(1);
1276                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1277                                 break;
1278                         case OUT_D888_P666:
1279                                 face = OUT_P888;
1280                                 mask = m_DITHER_DOWN_EN |
1281                                        m_DITHER_DOWN_MODE |
1282                                        m_DITHER_DOWN_SEL;
1283                                 val = v_DITHER_DOWN_EN(1) |
1284                                       v_DITHER_DOWN_MODE(1) |
1285                                       v_DITHER_DOWN_SEL(1);
1286                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1287                                 break;
1288                         case OUT_P888:
1289                                 face = OUT_P888;
1290                                 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1291                                 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1292                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1293                                 break;
1294                         default:
1295                                 dev_err(lcdc_dev->dev, "un supported interface!\n");
1296                                 break;
1297                         }
1298                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_SW_OVERLAY_MODE,
1299                                      v_SW_OVERLAY_MODE(dev_drv->overlay_mode));
1300                 }
1301
1302                 mask = m_HSYNC_POL | m_VSYNC_POL |
1303                        m_DEN_POL | m_DCLK_POL;
1304                 val = v_HSYNC_POL(screen->pin_hsync) |
1305                       v_VSYNC_POL(screen->pin_vsync) |
1306                       v_DEN_POL(screen->pin_den) |
1307                       v_DCLK_POL(screen->pin_dclk);
1308
1309                 if (screen->type != SCREEN_HDMI) {
1310                         mask |= m_DSP_OUT_FORMAT;
1311                         val |= v_DSP_OUT_FORMAT(face);
1312                 }
1313
1314                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1315
1316                 mask = m_BG_COLOR | m_DSP_BG_SWAP | m_DSP_RB_SWAP |
1317                        m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1318                        m_DSP_DUMMY_SWAP | m_BLANK_EN | m_BLACK_EN;
1319
1320                 val = v_BG_COLOR(0x000000) | v_DSP_BG_SWAP(screen->swap_gb) |
1321                       v_DSP_RB_SWAP(screen->swap_rb) |
1322                       v_DSP_RG_SWAP(screen->swap_rg) |
1323                       v_DSP_DELTA_SWAP(screen->swap_delta) |
1324                       v_DSP_DUMMY_SWAP(screen->swap_dumy) |
1325                       v_BLANK_EN(0) | v_BLACK_EN(0);
1326                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1327
1328                 /* config timing */
1329                 val = v_HSYNC(screen->mode.hsync_len) |
1330                       v_HORPRD(screen->mode.hsync_len + left_margin + x_res +
1331                                 right_margin);
1332                 lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END, val);
1333                 val = v_HAEP(screen->mode.hsync_len + left_margin + x_res) |
1334                       v_HASP(screen->mode.hsync_len + left_margin);
1335                 lcdc_writel(lcdc_dev, DSP_HACT_ST_END, val);
1336
1337                 if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1338                         /* First Field Timing */
1339                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END,
1340                                     v_VSYNC(screen->mode.vsync_len) |
1341                                     v_VERPRD(2 * (screen->mode.vsync_len +
1342                                                   upper_margin +
1343                                                   lower_margin) + y_res + 1));
1344                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END,
1345                                     v_VAEP(screen->mode.vsync_len +
1346                                            upper_margin + y_res / 2) |
1347                                     v_VASP(screen->mode.vsync_len +
1348                                            upper_margin));
1349                         /* Second Field Timing */
1350                         lcdc_writel(lcdc_dev, DSP_VS_ST_END_F1,
1351                                     v_VSYNC_ST_F1(screen->mode.vsync_len +
1352                                                   upper_margin + y_res / 2 +
1353                                                 lower_margin) |
1354                                     v_VSYNC_END_F1(2 * screen->mode.vsync_len +
1355                                                    upper_margin + y_res / 2 +
1356                                                    lower_margin));
1357                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END_F1,
1358                                     v_VAEP(2 * (screen->mode.vsync_len +
1359                                                 upper_margin) +
1360                                                 y_res + lower_margin + 1) |
1361                                     v_VASP(2 * (screen->mode.vsync_len +
1362                                                 upper_margin) +
1363                                                 y_res / 2 + lower_margin + 1));
1364
1365                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1366                                      m_INTERLACE_DSP_EN |
1367                                      m_WIN0_YRGB_DEFLICK_EN |
1368                                      m_WIN0_CBR_DEFLICK_EN |
1369                                      m_INTERLACE_FIELD_POL |
1370                                      m_WIN0_INTERLACE_EN |
1371                                      m_WIN1_INTERLACE_EN,
1372                                      v_INTERLACE_DSP_EN(1) |
1373                                      v_WIN0_YRGB_DEFLICK_EN(1) |
1374                                      v_WIN0_CBR_DEFLICK_EN(1) |
1375                                      v_INTERLACE_FIELD_POL(0) |
1376                                      v_WIN0_INTERLACE_EN(1) |
1377                                      v_WIN1_INTERLACE_EN(1));
1378                         mask = m_LF_INT_NUM;
1379                         val = v_LF_INT_NUM(screen->mode.vsync_len +
1380                                            screen->mode.upper_margin +
1381                                            screen->mode.yres/2);
1382                         lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
1383                 } else {
1384                         val = v_VSYNC(screen->mode.vsync_len) |
1385                               v_VERPRD(screen->mode.vsync_len + upper_margin +
1386                                      y_res + lower_margin);
1387                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, val);
1388
1389                         val = v_VAEP(screen->mode.vsync_len +
1390                                      upper_margin + y_res) |
1391                               v_VASP(screen->mode.vsync_len + upper_margin);
1392                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END, val);
1393
1394                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1395                                      m_INTERLACE_DSP_EN |
1396                                      m_WIN0_YRGB_DEFLICK_EN |
1397                                      m_WIN0_CBR_DEFLICK_EN |
1398                                      m_INTERLACE_FIELD_POL |
1399                                      m_WIN0_INTERLACE_EN |
1400                                      m_WIN1_INTERLACE_EN,
1401                                      v_INTERLACE_DSP_EN(0) |
1402                                      v_WIN0_YRGB_DEFLICK_EN(0) |
1403                                      v_WIN0_CBR_DEFLICK_EN(0) |
1404                                      v_INTERLACE_FIELD_POL(0) |
1405                                      v_WIN0_INTERLACE_EN(0) |
1406                                      v_WIN1_INTERLACE_EN(0));
1407                         mask = m_LF_INT_NUM;
1408                         val = v_LF_INT_NUM(screen->mode.vsync_len +
1409                                            screen->mode.upper_margin +
1410                                            screen->mode.yres);
1411                         lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
1412                 }
1413         }
1414         spin_unlock(&lcdc_dev->reg_lock);
1415         rk312x_lcdc_set_dclk(dev_drv, 1);
1416         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY, v_LCDC_STANDBY(0));
1417         lcdc_cfg_done(lcdc_dev);
1418         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1419                 dev_drv->trsm_ops->enable();
1420         if (screen->init)
1421                 screen->init();
1422
1423         return 0;
1424 }
1425
1426 static int rk312x_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1427                             bool open)
1428 {
1429         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1430                                                     struct lcdc_device, driver);
1431
1432         /* enable clk,when first layer open */
1433         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1434                 rockchip_set_system_status(SYS_STATUS_LCDC0);
1435                 rk312x_lcdc_pre_init(dev_drv);
1436                 rk312x_lcdc_clk_enable(lcdc_dev);
1437 #if defined(CONFIG_ROCKCHIP_IOMMU)
1438                 if (dev_drv->iommu_enabled) {
1439                         if (!dev_drv->mmu_dev) {
1440                                 dev_drv->mmu_dev =
1441                                         rk_fb_get_sysmmu_device_by_compatible(dev_drv->mmu_dts_name);
1442                                 if (dev_drv->mmu_dev) {
1443                                         rk_fb_platform_set_sysmmu(dev_drv->mmu_dev,
1444                                                                   dev_drv->dev);
1445                                 } else {
1446                                         dev_err(dev_drv->dev,
1447                                                 "failed to get rockchip iommu device\n");
1448                                         return -1;
1449                                 }
1450                         }
1451                         /*if (dev_drv->mmu_dev)
1452                                 rockchip_iovmm_activate(dev_drv->dev);*/
1453                 }
1454 #endif
1455                 rk312x_lcdc_reg_restore(lcdc_dev);
1456                 /*if (dev_drv->iommu_enabled)
1457                         rk312x_lcdc_mmu_en(dev_drv);*/
1458                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
1459                         rk312x_lcdc_set_dclk(dev_drv, 0);
1460                         rk312x_lcdc_enable_irq(dev_drv);
1461                 } else {
1462                         rk312x_load_screen(dev_drv, 1);
1463                 }
1464
1465                 /* set screen lut */
1466                 if (dev_drv->cur_screen->dsp_lut)
1467                         rk312x_lcdc_set_lut(dev_drv,
1468                                             dev_drv->cur_screen->dsp_lut);
1469         }
1470
1471         if (win_id < ARRAY_SIZE(lcdc_win))
1472                 lcdc_layer_enable(lcdc_dev, win_id, open);
1473         else
1474                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1475
1476         /* when all layer closed,disable clk */
1477 /*      if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1478                 rk312x_lcdc_disable_irq(lcdc_dev);
1479                 rk312x_lcdc_reg_update(dev_drv);
1480 #if defined(CONFIG_ROCKCHIP_IOMMU)
1481                 if (dev_drv->iommu_enabled) {
1482                         if (dev_drv->mmu_dev)
1483                                 rockchip_iovmm_deactivate(dev_drv->dev);
1484                 }
1485 #endif
1486                 rk312x_lcdc_clk_disable(lcdc_dev);
1487                 rockchip_clear_system_status(SYS_STATUS_LCDC0);
1488         }*/
1489         return 0;
1490 }
1491
1492 static int rk312x_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
1493 {
1494         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1495                                                     struct lcdc_device, driver);
1496         struct rk_screen *screen = dev_drv->cur_screen;
1497         struct rk_lcdc_win *win = NULL;
1498         char fmt[9] = "NULL";
1499
1500         if (!screen) {
1501                 dev_err(dev_drv->dev, "screen is null!\n");
1502                 return -ENOENT;
1503         }
1504
1505         if (win_id == 0) {
1506                 win = dev_drv->win[0];
1507         } else if (win_id == 1) {
1508                 win = dev_drv->win[1];
1509         } else if (win_id == 2) {
1510                 win = dev_drv->win[2];
1511         } else {
1512                 dev_err(dev_drv->dev, "un supported win number:%d\n", win_id);
1513                 return -EINVAL;
1514         }
1515
1516         spin_lock(&lcdc_dev->reg_lock);
1517         win->area[0].dsp_stx = win->area[0].xpos + screen->mode.left_margin +
1518                                screen->mode.hsync_len;
1519         if (win_id == 1) {
1520                 if ((win->area[0].xact != win->area[0].xsize) ||
1521                     (win->area[0].yact != win->area[0].ysize)) {
1522                         pr_err("win[1],not support scale\n");
1523                         pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
1524                                 win->area[0].xact,win->area[0].yact,
1525                                 win->area[0].xsize,win->area[0].ysize);
1526                         win->area[0].xsize = win->area[0].xact;
1527                         win->area[0].ysize = win->area[0].yact;
1528                     }
1529         }
1530         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1531                 win->area[0].ysize /= 2;
1532                 win->area[0].dsp_sty = win->area[0].ypos / 2 +
1533                                        screen->mode.upper_margin +
1534                                        screen->mode.vsync_len;
1535         } else {
1536                 win->area[0].dsp_sty = win->area[0].ypos +
1537                                        screen->mode.upper_margin +
1538                                        screen->mode.vsync_len;
1539         }
1540         win->scale_yrgb_x = CalScale(win->area[0].xact, win->area[0].xsize);
1541         win->scale_yrgb_y = CalScale(win->area[0].yact, win->area[0].ysize);
1542
1543         switch (win->area[0].format) {
1544         case ARGB888:
1545                 win->area[0].fmt_cfg = VOP_FORMAT_ARGB888;
1546                 win->area[0].swap_rb = 0;
1547                 win->area[0].swap_uv = 0;
1548                 break;
1549         case XBGR888:
1550                 win->area[0].fmt_cfg = VOP_FORMAT_ARGB888;
1551                 win->area[0].swap_rb = 1;
1552                 win->area[0].swap_uv = 0;
1553                 break;
1554         case ABGR888:
1555                 win->area[0].fmt_cfg = VOP_FORMAT_ARGB888;
1556                 win->area[0].swap_rb = 1;
1557                 win->area[0].swap_uv = 0;
1558                 break;
1559         case RGB888:
1560                 win->area[0].fmt_cfg = VOP_FORMAT_RGB888;
1561                 win->area[0].swap_rb = 0;
1562                 win->area[0].swap_uv = 0;
1563                 break;
1564         case RGB565:
1565                 win->area[0].fmt_cfg = VOP_FORMAT_RGB565;
1566                 win->area[0].swap_rb = 0;
1567                 break;
1568         case YUV444:
1569                 if (win_id == 0) {
1570                         win->area[0].fmt_cfg = VOP_FORMAT_YCBCR444;
1571                         win->scale_cbcr_x =
1572                             CalScale(win->area[0].xact, win->area[0].xsize);
1573                         win->scale_cbcr_y =
1574                             CalScale(win->area[0].yact, win->area[0].ysize);
1575                         win->area[0].swap_rb = 0;
1576                         win->area[0].swap_uv = 0;
1577                 } else {
1578                         dev_err(lcdc_dev->driver.dev,
1579                                 "%s:un supported format!\n", __func__);
1580                 }
1581                 break;
1582         case YUV422:
1583                 if (win_id == 0) {
1584                         win->area[0].fmt_cfg = VOP_FORMAT_YCBCR422;
1585                         win->scale_cbcr_x = CalScale((win->area[0].xact / 2),
1586                                             win->area[0].xsize);
1587                         win->scale_cbcr_y =
1588                             CalScale(win->area[0].yact, win->area[0].ysize);
1589                         win->area[0].swap_rb = 0;
1590                         win->area[0].swap_uv = 0;
1591                 } else {
1592                         dev_err(lcdc_dev->driver.dev,
1593                                 "%s:un supported format!\n", __func__);
1594                 }
1595                 break;
1596         case YUV420:
1597                 if (win_id == 0) {
1598                         win->area[0].fmt_cfg = VOP_FORMAT_YCBCR420;
1599                         win->scale_cbcr_x =
1600                             CalScale(win->area[0].xact / 2, win->area[0].xsize);
1601                         win->scale_cbcr_y =
1602                             CalScale(win->area[0].yact / 2, win->area[0].ysize);
1603                         win->area[0].swap_rb = 0;
1604                         win->area[0].swap_uv = 0;
1605                 } else {
1606                         dev_err(lcdc_dev->driver.dev,
1607                                 "%s:un supported format!\n", __func__);
1608                 }
1609                 break;
1610         case YUV420_NV21:
1611                 if (win_id == 0) {
1612                         win->area[0].fmt_cfg = VOP_FORMAT_YCBCR420;
1613                         win->scale_cbcr_x =
1614                             CalScale(win->area[0].xact / 2, win->area[0].xsize);
1615                         win->scale_cbcr_y =
1616                             CalScale(win->area[0].yact / 2, win->area[0].ysize);
1617                         win->area[0].swap_rb = 0;
1618                         win->area[0].swap_uv = 1;
1619                 } else {
1620                         dev_err(lcdc_dev->driver.dev,
1621                                 "%s:un supported format!\n", __func__);
1622                 }
1623                 break;
1624         default:
1625                 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
1626                         __func__);
1627                 break;
1628         }
1629         spin_unlock(&lcdc_dev->reg_lock);
1630
1631         DBG(1,
1632             "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
1633             ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, __func__,
1634             get_format_string(win->area[0].format, fmt), win->area[0].xact,
1635             win->area[0].yact, win->area[0].xsize, win->area[0].ysize,
1636             win->area[0].xvir, win->area[0].yvir, win->area[0].xpos,
1637             win->area[0].ypos);
1638         return 0;
1639 }
1640
1641 static int rk312x_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
1642 {
1643         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1644                                                     struct lcdc_device, driver);
1645         struct rk_lcdc_win *win = NULL;
1646         struct rk_screen *screen = dev_drv->cur_screen;
1647
1648         if (!screen) {
1649                 dev_err(dev_drv->dev, "screen is null!\n");
1650                 return -ENOENT;
1651         }
1652
1653         if (win_id == 0) {
1654                 win = dev_drv->win[0];
1655         } else if (win_id == 1) {
1656                 win = dev_drv->win[1];
1657         } else if (win_id == 2) {
1658                 win = dev_drv->win[2];
1659         } else {
1660                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1661                 return -EINVAL;
1662         }
1663
1664         spin_lock(&lcdc_dev->reg_lock);
1665         if (likely(lcdc_dev->clk_on)) {
1666                 win->area[0].y_addr =
1667                     win->area[0].smem_start + win->area[0].y_offset;
1668                 win->area[0].uv_addr =
1669                     win->area[0].cbr_start + win->area[0].c_offset;
1670                 if (win->area[0].y_addr)
1671                         lcdc_layer_update_regs(lcdc_dev, win);
1672                 /* lcdc_cfg_done(lcdc_dev); */
1673         }
1674         spin_unlock(&lcdc_dev->reg_lock);
1675
1676         DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n",
1677             lcdc_dev->id, __func__, win->area[0].y_addr, win->area[0].uv_addr,
1678             win->area[0].y_offset);
1679         /* this is the first frame of the system,enable frame start interrupt */
1680         if ((dev_drv->first_frame)) {
1681                 dev_drv->first_frame = 0;
1682                 rk312x_lcdc_enable_irq(dev_drv);
1683         }
1684
1685         return 0;
1686 }
1687
1688 static int rk312x_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
1689                              unsigned long arg, int win_id)
1690 {
1691         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1692                                                     struct lcdc_device, driver);
1693         u32 panel_size[2];
1694         void __user *argp = (void __user *)arg;
1695         struct color_key_cfg clr_key_cfg;
1696
1697         switch (cmd) {
1698         case RK_FBIOGET_PANEL_SIZE:
1699                 panel_size[0] = lcdc_dev->screen->mode.xres;
1700                 panel_size[1] = lcdc_dev->screen->mode.yres;
1701                 if (copy_to_user(argp, panel_size, 8))
1702                         return -EFAULT;
1703                 break;
1704         case RK_FBIOPUT_COLOR_KEY_CFG:
1705                 if (copy_from_user(&clr_key_cfg, argp,
1706                                    sizeof(struct color_key_cfg)))
1707                         return -EFAULT;
1708                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
1709                             clr_key_cfg.win0_color_key_cfg);
1710                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
1711                             clr_key_cfg.win1_color_key_cfg);
1712                 break;
1713
1714         default:
1715                 break;
1716         }
1717         return 0;
1718 }
1719
1720 static int rk312x_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
1721                                   const char *id)
1722 {
1723         int win_id = 0;
1724
1725         mutex_lock(&dev_drv->fb_win_id_mutex);
1726         if (!strcmp(id, "fb0"))
1727                 win_id = dev_drv->fb0_win_id;
1728         else if (!strcmp(id, "fb1"))
1729                 win_id = dev_drv->fb1_win_id;
1730         else if (!strcmp(id, "fb2"))
1731                 win_id = dev_drv->fb2_win_id;
1732         mutex_unlock(&dev_drv->fb_win_id_mutex);
1733
1734         return win_id;
1735 }
1736
1737 static int rk312x_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
1738 {
1739         struct lcdc_device *lcdc_dev =
1740                 container_of(dev_drv, struct lcdc_device, driver);
1741         int win_status = 0;
1742
1743         if (win_id == 0)
1744                 win_status = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_WIN0_EN);
1745         else if (win_id == 1)
1746                 win_status = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_WIN1_EN);
1747         else
1748                 pr_err("!!!%s,win_id :%d,unsupport!!!\n",__func__,win_id);
1749
1750         return win_status;
1751 }
1752
1753 static int rk312x_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
1754                                bool set)
1755 {
1756         struct lcdc_device *lcdc_dev =
1757             container_of(dev_drv, struct lcdc_device, driver);
1758         int ovl;
1759
1760         spin_lock(&lcdc_dev->reg_lock);
1761         if (lcdc_dev->clk_on) {
1762                 if (set) {
1763                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_TOP,
1764                                      v_WIN0_TOP(swap));
1765                         ovl = swap;
1766                 } else {
1767                         ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP);
1768                 }
1769         } else {
1770                 ovl = -EPERM;
1771         }
1772         spin_unlock(&lcdc_dev->reg_lock);
1773
1774         return ovl;
1775 }
1776
1777 static int rk312x_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
1778 {
1779         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1780                                                     struct lcdc_device, driver);
1781         struct device_node *backlight;
1782
1783         if (lcdc_dev->backlight)
1784                 return 0;
1785
1786         backlight = of_parse_phandle(lcdc_dev->dev->of_node,
1787                                      "backlight", 0);
1788         if (backlight) {
1789                 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
1790                 if (!lcdc_dev->backlight)
1791                         dev_info(lcdc_dev->dev, "No find backlight device\n");
1792         } else {
1793                 dev_info(lcdc_dev->dev, "No find backlight device node\n");
1794         }
1795
1796         return 0;
1797 }
1798
1799 static int rk312x_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
1800 {
1801         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1802                                                     struct lcdc_device, driver);
1803         if (dev_drv->suspend_flag)
1804                 return 0;
1805
1806         /* close the backlight */
1807         rk312x_lcdc_get_backlight_device(dev_drv);
1808         if (lcdc_dev->backlight) {
1809                 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
1810                 backlight_update_status(lcdc_dev->backlight);
1811         }
1812
1813         dev_drv->suspend_flag = 1;
1814         flush_kthread_worker(&dev_drv->update_regs_worker);
1815
1816         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
1817                 dev_drv->trsm_ops->disable();
1818         spin_lock(&lcdc_dev->reg_lock);
1819         if (likely(lcdc_dev->clk_on)) {
1820                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, v_BLANK_EN(1));
1821                 lcdc_msk_reg(lcdc_dev, INT_STATUS,
1822                              m_FS_INT_CLEAR | m_LF_INT_CLEAR,
1823                              v_FS_INT_CLEAR(1) | v_LF_INT_CLEAR(1));
1824                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1825                              v_DSP_OUT_ZERO(1));
1826                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1827                              v_LCDC_STANDBY(1));
1828                 lcdc_cfg_done(lcdc_dev);
1829
1830                 if (dev_drv->iommu_enabled) {
1831                         if (dev_drv->mmu_dev)
1832                                 rockchip_iovmm_deactivate(dev_drv->dev);
1833                 }
1834
1835                 spin_unlock(&lcdc_dev->reg_lock);
1836         } else {
1837                 spin_unlock(&lcdc_dev->reg_lock);
1838                 return 0;
1839         }
1840         rk312x_lcdc_clk_disable(lcdc_dev);
1841         rk_disp_pwr_disable(dev_drv);
1842         return 0;
1843 }
1844
1845 static int rk312x_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
1846 {
1847         struct lcdc_device *lcdc_dev =
1848             container_of(dev_drv, struct lcdc_device, driver);
1849
1850         if (!dev_drv->suspend_flag)
1851                 return 0;
1852         rk_disp_pwr_enable(dev_drv);
1853
1854         rk312x_lcdc_clk_enable(lcdc_dev);
1855         rk312x_lcdc_reg_restore(lcdc_dev);
1856
1857         /* config for the FRC mode of dither down */
1858         if (dev_drv->cur_screen &&
1859                         dev_drv->cur_screen->face != OUT_P888) {
1860                 lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
1861                 lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
1862                 lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0x55aaaa55);
1863                 lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x55aaaa55);
1864                 lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
1865                 lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
1866         }
1867
1868         /* set screen lut */
1869         if (dev_drv->cur_screen && dev_drv->cur_screen->dsp_lut)
1870                 rk312x_lcdc_set_lut(dev_drv,
1871                                     dev_drv->cur_screen->dsp_lut);
1872         /*set hwc lut*/
1873         rk312x_lcdc_set_hwc_lut(dev_drv, dev_drv->hwc_lut, 0);
1874
1875         spin_lock(&lcdc_dev->reg_lock);
1876
1877         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1878                         v_DSP_OUT_ZERO(0));
1879         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1880                         v_LCDC_STANDBY(0));
1881         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, v_BLANK_EN(0));
1882         lcdc_cfg_done(lcdc_dev);
1883
1884         if (dev_drv->iommu_enabled) {
1885                 if (dev_drv->mmu_dev)
1886                         rockchip_iovmm_activate(dev_drv->dev);
1887         }
1888
1889         spin_unlock(&lcdc_dev->reg_lock);
1890         dev_drv->suspend_flag = 0;
1891
1892         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1893                 dev_drv->trsm_ops->enable();
1894         mdelay(100);
1895
1896         return 0;
1897 }
1898
1899 static int rk312x_lcdc_blank(struct rk_lcdc_driver *dev_drv,
1900                              int win_id, int blank_mode)
1901 {
1902         switch (blank_mode) {
1903         case FB_BLANK_UNBLANK:
1904                 rk312x_lcdc_early_resume(dev_drv);
1905                 break;
1906         case FB_BLANK_NORMAL:
1907                 rk312x_lcdc_early_suspend(dev_drv);
1908                 break;
1909         default:
1910                 rk312x_lcdc_early_suspend(dev_drv);
1911                 break;
1912         }
1913
1914         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
1915
1916         return 0;
1917 }
1918
1919 static int rk312x_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv)
1920 {
1921         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1922                                                     struct lcdc_device, driver);
1923         int i;
1924         struct rk_lcdc_win *win = NULL;
1925
1926         spin_lock(&lcdc_dev->reg_lock);
1927         if (lcdc_dev->clk_on) {
1928                 for (i = 0; i < ARRAY_SIZE(lcdc_win); i++) {
1929                         win = dev_drv->win[i];
1930                         if ((win->state == 0) && (win->last_state == 1))
1931                                 lcdc_layer_update_regs(lcdc_dev, win);
1932                         win->last_state = win->state;
1933                 }
1934                 lcdc_cfg_done(lcdc_dev);
1935         }
1936         spin_unlock(&lcdc_dev->reg_lock);
1937         return 0;
1938 }
1939
1940 /*
1941         a:[-30~0]:
1942             sin_hue = sin(a)*256 +0x100;
1943             cos_hue = cos(a)*256;
1944         a:[0~30]
1945             sin_hue = sin(a)*256;
1946             cos_hue = cos(a)*256;
1947 */
1948 static int rk312x_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
1949                                     bcsh_hue_mode mode)
1950 {
1951         struct lcdc_device *lcdc_dev =
1952             container_of(dev_drv, struct lcdc_device, driver);
1953         u32 val;
1954
1955         spin_lock(&lcdc_dev->reg_lock);
1956         if (lcdc_dev->clk_on) {
1957                 val = lcdc_readl(lcdc_dev, BCSH_H);
1958                 switch (mode) {
1959                 case H_SIN:
1960                         val &= m_BCSH_SIN_HUE;
1961                         break;
1962                 case H_COS:
1963                         val &= m_BCSH_COS_HUE;
1964                         val >>= 16;
1965                         break;
1966                 default:
1967                         break;
1968                 }
1969         }
1970         spin_unlock(&lcdc_dev->reg_lock);
1971
1972         return val;
1973 }
1974
1975 static int rk312x_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv, int sin_hue,
1976                                     int cos_hue)
1977 {
1978         struct lcdc_device *lcdc_dev =
1979             container_of(dev_drv, struct lcdc_device, driver);
1980         u32 mask, val;
1981
1982         spin_lock(&lcdc_dev->reg_lock);
1983         if (lcdc_dev->clk_on) {
1984                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
1985                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
1986                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
1987                 lcdc_cfg_done(lcdc_dev);
1988         }
1989         spin_unlock(&lcdc_dev->reg_lock);
1990
1991         return 0;
1992 }
1993
1994 static int rk312x_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1995                                     bcsh_bcs_mode mode, int value)
1996 {
1997         struct lcdc_device *lcdc_dev =
1998             container_of(dev_drv, struct lcdc_device, driver);
1999         u32 mask, val;
2000
2001         spin_lock(&lcdc_dev->reg_lock);
2002         if (lcdc_dev->clk_on) {
2003                 switch (mode) {
2004                 case BRIGHTNESS:
2005                         /* from 0 to 255,typical is 128 */
2006                         if (value < 0x80)
2007                                 value += 0x80;
2008                         else if (value >= 0x80)
2009                                 value = value - 0x80;
2010                         mask = m_BCSH_BRIGHTNESS;
2011                         val = v_BCSH_BRIGHTNESS(value);
2012                         break;
2013                 case CONTRAST:
2014                         /* from 0 to 510,typical is 256 */
2015                         mask = m_BCSH_CONTRAST;
2016                         val = v_BCSH_CONTRAST(value);
2017                         break;
2018                 case SAT_CON:
2019                         /* from 0 to 1015,typical is 256 */
2020                         mask = m_BCSH_SAT_CON;
2021                         val = v_BCSH_SAT_CON(value);
2022                         break;
2023                 default:
2024                         break;
2025                 }
2026                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
2027                 lcdc_cfg_done(lcdc_dev);
2028         }
2029         spin_unlock(&lcdc_dev->reg_lock);
2030         return val;
2031 }
2032
2033 static int rk312x_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
2034                                     bcsh_bcs_mode mode)
2035 {
2036         struct lcdc_device *lcdc_dev =
2037             container_of(dev_drv, struct lcdc_device, driver);
2038         u32 val;
2039
2040         spin_lock(&lcdc_dev->reg_lock);
2041         if (lcdc_dev->clk_on) {
2042                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
2043                 switch (mode) {
2044                 case BRIGHTNESS:
2045                         val &= m_BCSH_BRIGHTNESS;
2046                         if (val > 0x80)
2047                                 val -= 0x80;
2048                         else
2049                                 val += 0x80;
2050                         break;
2051                 case CONTRAST:
2052                         val &= m_BCSH_CONTRAST;
2053                         val >>= 8;
2054                         break;
2055                 case SAT_CON:
2056                         val &= m_BCSH_SAT_CON;
2057                         val >>= 20;
2058                         break;
2059                 default:
2060                         break;
2061                 }
2062         }
2063         spin_unlock(&lcdc_dev->reg_lock);
2064         return val;
2065 }
2066
2067 static int rk312x_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
2068 {
2069         struct lcdc_device *lcdc_dev =
2070             container_of(dev_drv, struct lcdc_device, driver);
2071         u32 mask, val;
2072         if (dev_drv->bcsh_init_status && open) {
2073                 dev_drv->bcsh_init_status = 0;
2074                 return 0;
2075         }
2076         spin_lock(&lcdc_dev->reg_lock);
2077         if (lcdc_dev->clk_on) {
2078                 if (open) {
2079                         lcdc_msk_reg(lcdc_dev,
2080                                      BCSH_CTRL, m_BCSH_EN | m_BCSH_OUT_MODE,
2081                                      v_BCSH_EN(1) | v_BCSH_OUT_MODE(3));
2082                         lcdc_writel(lcdc_dev, BCSH_BCS,
2083                                     v_BCSH_BRIGHTNESS(0x00) |
2084                                     v_BCSH_CONTRAST(0x80) |
2085                                     v_BCSH_SAT_CON(0x80));
2086                         lcdc_writel(lcdc_dev, BCSH_H, v_BCSH_COS_HUE(0x80));
2087                         dev_drv->bcsh.enable = 1;
2088                 } else {
2089                         mask = m_BCSH_EN;
2090                         val = v_BCSH_EN(0);
2091                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL, mask, val);
2092                         dev_drv->bcsh.enable = 0;
2093                 }
2094                 rk312x_lcdc_select_bcsh(dev_drv,  lcdc_dev);
2095                 lcdc_cfg_done(lcdc_dev);
2096         }
2097
2098         spin_unlock(&lcdc_dev->reg_lock);
2099         return 0;
2100 }
2101
2102 static int rk312x_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
2103 {
2104         struct rk_lcdc_win_area area;
2105         int fb2_win_id, fb1_win_id, fb0_win_id;
2106
2107         mutex_lock(&dev_drv->fb_win_id_mutex);
2108         if (order == FB_DEFAULT_ORDER)
2109                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2;
2110
2111         fb2_win_id = order / 100;
2112         fb1_win_id = (order / 10) % 10;
2113         fb0_win_id = order % 10;
2114
2115         if (fb0_win_id != dev_drv->fb0_win_id) {
2116                 area = dev_drv->win[(int)dev_drv->fb0_win_id]->area[0];
2117                 dev_drv->win[(int)dev_drv->fb0_win_id]->area[0] =
2118                         dev_drv->win[fb0_win_id]->area[0];
2119                 dev_drv->win[fb0_win_id]->area[0] = area;
2120                 dev_drv->fb0_win_id = fb0_win_id;
2121         }
2122         dev_drv->fb1_win_id = fb1_win_id;
2123         dev_drv->fb2_win_id = fb2_win_id;
2124
2125         mutex_unlock(&dev_drv->fb_win_id_mutex);
2126
2127         return 0;
2128 }
2129
2130 static int rk312x_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
2131                                bool set)
2132 {
2133         struct lcdc_device *lcdc_dev =
2134             container_of(dev_drv, struct lcdc_device, driver);
2135         struct rk_screen *screen = dev_drv->cur_screen;
2136         u64 ft = 0;
2137         u32 dotclk;
2138         int ret;
2139         u32 pixclock;
2140         u32 x_total, y_total;
2141
2142         if (set) {
2143                 ft = div_u64(1000000000000llu, fps);
2144                 x_total =
2145                     screen->mode.upper_margin + screen->mode.lower_margin +
2146                     screen->mode.yres + screen->mode.vsync_len;
2147                 y_total =
2148                     screen->mode.left_margin + screen->mode.right_margin +
2149                     screen->mode.xres + screen->mode.hsync_len;
2150                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
2151                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
2152                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
2153         }
2154
2155         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
2156         dev_drv->pixclock = lcdc_dev->pixclock = pixclock;
2157         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
2158         screen->ft = 1000 / fps;        /*one frame time in ms */
2159
2160         if (set)
2161                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
2162                          clk_get_rate(lcdc_dev->dclk), fps);
2163
2164         return fps;
2165 }
2166
2167 static int rk312x_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
2168                                       int enable)
2169 {
2170         struct lcdc_device *lcdc_dev =
2171                                 container_of(dev_drv,
2172                                              struct lcdc_device, driver);
2173         if (enable)
2174                 enable_irq(lcdc_dev->irq);
2175         else
2176                 disable_irq(lcdc_dev->irq);
2177         return 0;
2178 }
2179
2180 static int rk312x_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
2181 {
2182         struct lcdc_device *lcdc_dev =
2183             container_of(dev_drv, struct lcdc_device, driver);
2184         u32 int_reg;
2185         int ret;
2186
2187         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
2188                 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
2189                 if (int_reg & m_LF_INT_STA) {
2190                         dev_drv->frame_time.last_framedone_t =
2191                                         dev_drv->frame_time.framedone_t;
2192                         dev_drv->frame_time.framedone_t = cpu_clock(0);
2193                         lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
2194                                      v_LF_INT_CLEAR(1));
2195                         ret = RK_LF_STATUS_FC;
2196                 } else {
2197                         ret = RK_LF_STATUS_FR;
2198                 }
2199         } else {
2200                 ret = RK_LF_STATUS_NC;
2201         }
2202
2203         return ret;
2204 }
2205
2206 static int rk312x_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
2207                                     unsigned int *dsp_addr)
2208 {
2209         struct lcdc_device *lcdc_dev =
2210             container_of(dev_drv, struct lcdc_device, driver);
2211
2212         if (lcdc_dev->clk_on) {
2213                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
2214                 if (lcdc_dev->soc_type == VOP_RK3036)
2215                         dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_MST);
2216                 else if (lcdc_dev->soc_type == VOP_RK312X)
2217                         dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_MST_RK312X);
2218         }
2219         return 0;
2220 }
2221
2222 static ssize_t rk312x_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
2223                                          char *buf, int win_id)
2224 {
2225         struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device,
2226                                                     driver);
2227         char format_w0[9] = "NULL";
2228         char format_w1[9] = "NULL";
2229         char status_w0[9] = "NULL";
2230         char status_w1[9] = "NULL";
2231         u32 fmt_id, act_info, dsp_info, dsp_st, factor;
2232         u16 xvir_w0, x_act_w0, y_act_w0, x_dsp_w0, y_dsp_w0, x_st_w0, y_st_w0;
2233         u16 xvir_w1, x_act_w1, y_act_w1, x_dsp_w1, y_dsp_w1, x_st_w1, y_st_w1;
2234         u16 x_factor, y_factor, x_scale, y_scale;
2235         u16 ovl;
2236         u32 win1_dsp_yaddr = 0;
2237
2238         spin_lock(&lcdc_dev->reg_lock);
2239         if (lcdc_dev->clk_on) {
2240                 /* data format */
2241                 fmt_id = lcdc_readl(lcdc_dev, SYS_CTRL);
2242                 get_format_string((fmt_id & m_WIN0_FORMAT) >> 3, format_w0);
2243                 get_format_string((fmt_id & m_WIN1_FORMAT) >> 6, format_w1);
2244
2245                 /* win status */
2246                 if (fmt_id & m_WIN0_EN)
2247                         strcpy(status_w0, "enabled");
2248                 else
2249                         strcpy(status_w0, "disabled");
2250
2251                 if ((fmt_id & m_WIN1_EN) >> 1)
2252                         strcpy(status_w1, "enabled");
2253                 else
2254                         strcpy(status_w1, "disabled");
2255
2256                 /* ovl */
2257                 ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP);
2258
2259                 /* xvir */
2260                 xvir_w0 = lcdc_readl(lcdc_dev, WIN0_VIR) & m_YRGB_VIR;
2261                 xvir_w1 = lcdc_readl(lcdc_dev, WIN1_VIR) & m_YRGB_VIR;
2262
2263                 /* xact/yact */
2264                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
2265                 x_act_w0 = (act_info & m_ACT_WIDTH) + 1;
2266                 y_act_w0 = ((act_info & m_ACT_HEIGHT) >> 16) + 1;
2267
2268                 if (lcdc_dev->soc_type == VOP_RK3036) {
2269                         act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
2270                         x_act_w1 = (act_info & m_ACT_WIDTH) + 1;
2271                         y_act_w1 = ((act_info & m_ACT_HEIGHT) >> 16) + 1;
2272                 } else if (lcdc_dev->soc_type == VOP_RK312X) {
2273                         /* rk312x unsupport win1 scaler,so have no act info */
2274                         x_act_w1 = 0;
2275                         y_act_w1 = 0;
2276                 }
2277
2278                 /* xsize/ysize */
2279                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
2280                 x_dsp_w0 = (dsp_info & m_DSP_WIDTH) + 1;
2281                 y_dsp_w0 = ((dsp_info & m_DSP_HEIGHT) >> 16) + 1;
2282
2283                 if (lcdc_dev->soc_type == VOP_RK3036)
2284                         dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
2285                 else if (lcdc_dev->soc_type == VOP_RK312X)
2286                         dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO_RK312X);
2287                 x_dsp_w1 = (dsp_info & m_DSP_WIDTH) + 1;
2288                 y_dsp_w1 = ((dsp_info & m_DSP_HEIGHT) >> 16) + 1;
2289
2290                 /* xpos/ypos */
2291                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
2292                 x_st_w0 = dsp_st & m_DSP_STX;
2293                 y_st_w0 = (dsp_st & m_DSP_STY) >> 16;
2294
2295                 if (lcdc_dev->soc_type == VOP_RK3036)
2296                         dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
2297                 else if (lcdc_dev->soc_type == VOP_RK312X)
2298                         dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST_RK312X);
2299
2300                 x_st_w1 = dsp_st & m_DSP_STX;
2301                 y_st_w1 = (dsp_st & m_DSP_STY) >> 16;
2302
2303                 /* scale factor */
2304                 factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
2305                 x_factor = factor & m_X_SCL_FACTOR;
2306                 y_factor = (factor & m_Y_SCL_FACTOR) >> 16;
2307                 x_scale = 4096 * 100 / x_factor;
2308                 y_scale = 4096 * 100 / y_factor;
2309
2310                 /* dsp addr */
2311                 if (lcdc_dev->soc_type == VOP_RK3036)
2312                         win1_dsp_yaddr = lcdc_readl(lcdc_dev, WIN1_MST);
2313                 else if (lcdc_dev->soc_type == VOP_RK312X)
2314                         win1_dsp_yaddr = lcdc_readl(lcdc_dev, WIN1_MST_RK312X);
2315         } else {
2316                 spin_unlock(&lcdc_dev->reg_lock);
2317                 return -EPERM;
2318         }
2319         spin_unlock(&lcdc_dev->reg_lock);
2320         return snprintf(buf, PAGE_SIZE,
2321                         "win0:%s\n"
2322                         "xvir:%d\n"
2323                         "xact:%d\n"
2324                         "yact:%d\n"
2325                         "xdsp:%d\n"
2326                         "ydsp:%d\n"
2327                         "x_st:%d\n"
2328                         "y_st:%d\n"
2329                         "x_scale:%d.%d\n"
2330                         "y_scale:%d.%d\n"
2331                         "format:%s\n"
2332                         "YRGB buffer addr:0x%08x\n"
2333                         "CBR buffer addr:0x%08x\n\n"
2334                         "win1:%s\n"
2335                         "xvir:%d\n"
2336                         "xact:%d\n"
2337                         "yact:%d\n"
2338                         "xdsp:%d\n"
2339                         "ydsp:%d\n"
2340                         "x_st:%d\n"
2341                         "y_st:%d\n"
2342                         "format:%s\n"
2343                         "YRGB buffer addr:0x%08x\n"
2344                         "overlay:%s\n",
2345                         status_w0,
2346                         xvir_w0,
2347                         x_act_w0,
2348                         y_act_w0,
2349                         x_dsp_w0,
2350                         y_dsp_w0,
2351                         x_st_w0,
2352                         y_st_w0,
2353                         x_scale / 100,
2354                         x_scale % 100,
2355                         y_scale / 100,
2356                         y_scale % 100,
2357                         format_w0,
2358                         lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
2359                         lcdc_readl(lcdc_dev, WIN0_CBR_MST),
2360                         status_w1,
2361                         xvir_w1,
2362                         x_act_w1,
2363                         y_act_w1,
2364                         x_dsp_w1,
2365                         y_dsp_w1,
2366                         x_st_w1,
2367                         y_st_w1,
2368                         format_w1,
2369                         win1_dsp_yaddr,
2370                         ovl ? "win0 on the top of win1\n" :
2371                         "win1 on the top of win0\n");
2372 }
2373
2374 static int rk312x_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
2375 {
2376         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2377                                                     struct lcdc_device,
2378                                                     driver);
2379         int *cbase = (int *)lcdc_dev->regs;
2380         int *regsbak = (int *)lcdc_dev->regsbak;
2381         int i, j;
2382
2383         pr_info("back up reg:\n");
2384         for (i = 0; i <= (0xDC >> 4); i++) {
2385                 for (j = 0; j < 4; j++)
2386                         pr_info("%08x  ", *(regsbak + i * 4 + j));
2387                 pr_info("\n");
2388         }
2389
2390         pr_info("lcdc reg:\n");
2391         for (i = 0; i <= (0xDC >> 4); i++) {
2392                 for (j = 0; j < 4; j++)
2393                         pr_info("%08x  ", readl_relaxed(cbase + i * 4 + j));
2394                 pr_info("\n");
2395         }
2396         return 0;
2397 }
2398
2399 static int rk312x_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
2400 {
2401         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2402                                                     struct lcdc_device, driver);
2403         if (lcdc_dev->soc_type == VOP_RK312X) {
2404                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
2405                              v_DIRECT_PATH_EN(open));
2406                 lcdc_cfg_done(lcdc_dev);
2407         }
2408         return 0;
2409 }
2410
2411 static int rk312x_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
2412 {
2413         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2414                                                     struct lcdc_device, driver);
2415
2416         if (lcdc_dev->soc_type == VOP_RK312X) {
2417                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_LAYER,
2418                              v_DIRECT_PATH_LAYER(win_id));
2419                 lcdc_cfg_done(lcdc_dev);
2420         }
2421         return 0;
2422 }
2423
2424 static int rk312x_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
2425 {
2426         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2427                                                     struct lcdc_device, driver);
2428         int ovl = 0;
2429
2430         if (lcdc_dev->soc_type == VOP_RK312X)
2431                 ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
2432
2433         return ovl;
2434 }
2435
2436 static int rk312x_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
2437 {
2438         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2439                                                     struct lcdc_device, driver);
2440
2441         rk312x_lcdc_get_backlight_device(dev_drv);
2442
2443         if (enable) {
2444                 /* close the backlight */
2445                 if (lcdc_dev->backlight) {
2446                         lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
2447                         backlight_update_status(lcdc_dev->backlight);
2448                 }
2449
2450                 spin_lock(&lcdc_dev->reg_lock);
2451                 if (likely(lcdc_dev->clk_on)) {
2452                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLACK_EN,
2453                                      v_BLACK_EN(1));
2454                         lcdc_cfg_done(lcdc_dev);
2455                 }
2456                 spin_unlock(&lcdc_dev->reg_lock);
2457
2458                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
2459                         dev_drv->trsm_ops->disable();
2460         } else {
2461                 spin_lock(&lcdc_dev->reg_lock);
2462                 if (likely(lcdc_dev->clk_on)) {
2463                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLACK_EN,
2464                                      v_BLACK_EN(0));
2465                         lcdc_cfg_done(lcdc_dev);
2466                 }
2467                 spin_unlock(&lcdc_dev->reg_lock);
2468                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2469                         dev_drv->trsm_ops->enable();
2470                 msleep(100);
2471                 /* open the backlight */
2472                 if (lcdc_dev->backlight) {
2473                         lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
2474                         backlight_update_status(lcdc_dev->backlight);
2475                 }
2476         }
2477
2478         return 0;
2479 }
2480
2481
2482 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
2483         .open = rk312x_lcdc_open,
2484         .load_screen = rk312x_load_screen,
2485         .get_dspbuf_info = rk312x_get_dspbuf_info,
2486         .post_dspbuf = rk312x_post_dspbuf,
2487         .set_par = rk312x_lcdc_set_par,
2488         .pan_display = rk312x_lcdc_pan_display,
2489         .direct_set_addr = rk312x_lcdc_direct_set_win_addr,
2490         .blank = rk312x_lcdc_blank,
2491         .ioctl = rk312x_lcdc_ioctl,
2492         .get_win_state = rk312x_lcdc_get_win_state,
2493         .ovl_mgr = rk312x_lcdc_ovl_mgr,
2494         .get_disp_info = rk312x_lcdc_get_disp_info,
2495         .fps_mgr = rk312x_lcdc_fps_mgr,
2496         .fb_get_win_id = rk312x_lcdc_get_win_id,
2497         .fb_win_remap = rk312x_fb_win_remap,
2498         .poll_vblank = rk312x_lcdc_poll_vblank,
2499         .get_dsp_addr = rk312x_lcdc_get_dsp_addr,
2500         .cfg_done = rk312x_lcdc_cfg_done,
2501         .dump_reg = rk312x_lcdc_reg_dump,
2502         .dpi_open = rk312x_lcdc_dpi_open,
2503         .dpi_win_sel = rk312x_lcdc_dpi_win_sel,
2504         .dpi_status = rk312x_lcdc_dpi_status,
2505         .set_dsp_bcsh_hue = rk312x_lcdc_set_bcsh_hue,
2506         .set_dsp_bcsh_bcs = rk312x_lcdc_set_bcsh_bcs,
2507         .get_dsp_bcsh_hue = rk312x_lcdc_get_bcsh_hue,
2508         .get_dsp_bcsh_bcs = rk312x_lcdc_get_bcsh_bcs,
2509         .open_bcsh = rk312x_lcdc_open_bcsh,
2510         .set_screen_scaler = rk312x_lcdc_set_scaler,
2511         .set_dsp_lut = rk312x_lcdc_set_lut,
2512         .set_hwc_lut = rk312x_lcdc_set_hwc_lut,
2513         .set_irq_to_cpu = rk312x_lcdc_set_irq_to_cpu,
2514         .dsp_black = rk312x_lcdc_dsp_black,
2515         .mmu_en = rk312x_lcdc_mmu_en,
2516 };
2517 #if 0
2518 static const struct rk_lcdc_drvdata rk3036_lcdc_drvdata = {
2519         .soc_type = VOP_RK3036,
2520 };
2521 #endif
2522 static const struct rk_lcdc_drvdata rk312x_lcdc_drvdata = {
2523         .soc_type = VOP_RK312X,
2524 };
2525
2526 #if defined(CONFIG_OF)
2527 static const struct of_device_id rk312x_lcdc_dt_ids[] = {
2528 #if 0
2529         {
2530                 .compatible = "rockchip,rk3036-lcdc",
2531                 .data = (void *)&rk3036_lcdc_drvdata,
2532         },
2533 #endif
2534         {
2535                 .compatible = "rockchip,rk312x-lcdc",
2536                 .data = (void *)&rk312x_lcdc_drvdata,
2537         },
2538 };
2539 #endif
2540
2541 static int rk312x_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
2542 {
2543         struct device_node *np = lcdc_dev->dev->of_node;
2544         const struct of_device_id *match;
2545         const struct rk_lcdc_drvdata *lcdc_drvdata;
2546         int val;
2547
2548 #if defined(CONFIG_ROCKCHIP_IOMMU)
2549         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
2550                 lcdc_dev->driver.iommu_enabled = 0;
2551         else
2552                 lcdc_dev->driver.iommu_enabled = val;
2553 #else
2554         lcdc_dev->driver.iommu_enabled = 0;
2555 #endif
2556
2557         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
2558                 lcdc_dev->driver.fb_win_map = FB_DEFAULT_ORDER;
2559         else
2560                 lcdc_dev->driver.fb_win_map = val;
2561
2562         match = of_match_node(rk312x_lcdc_dt_ids, np);
2563         if (match) {
2564                 lcdc_drvdata = (const struct rk_lcdc_drvdata *)match->data;
2565                 lcdc_dev->soc_type = lcdc_drvdata->soc_type;
2566         } else {
2567                 return PTR_ERR(match);
2568         }
2569
2570         return 0;
2571 }
2572
2573 static int rk312x_lcdc_probe(struct platform_device *pdev)
2574 {
2575         struct lcdc_device *lcdc_dev = NULL;
2576         struct rk_lcdc_driver *dev_drv;
2577         struct device *dev = &pdev->dev;
2578         struct resource *res;
2579         int ret;
2580
2581         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
2582         if (!lcdc_dev) {
2583                 dev_err(&pdev->dev, "rk312x lcdc device kzalloc fail!\n");
2584                 return -ENOMEM;
2585         }
2586         platform_set_drvdata(pdev, lcdc_dev);
2587         lcdc_dev->dev = dev;
2588         if (rk312x_lcdc_parse_dt(lcdc_dev)) {
2589                 dev_err(lcdc_dev->dev, "rk312x lcdc parse dt failed!\n");
2590                 goto err_parse_dt;
2591         }
2592
2593         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2594         lcdc_dev->reg_phy_base = res->start;
2595         lcdc_dev->len = resource_size(res);
2596         lcdc_dev->regs = devm_ioremap_resource(dev, res);
2597         if (IS_ERR(lcdc_dev->regs)) {
2598                 ret = PTR_ERR(lcdc_dev->regs);
2599                 goto err_remap_reg;
2600         }
2601
2602         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
2603         if (IS_ERR(lcdc_dev->regsbak)) {
2604                 dev_err(&pdev->dev, "rk312x lcdc device kmalloc fail!\n");
2605                 ret = PTR_ERR(lcdc_dev->regsbak);
2606                 goto err_remap_reg;
2607         }
2608         lcdc_dev->hwc_lut_addr_base = (lcdc_dev->regs + HWC_LUT_ADDR);
2609         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + DSP_LUT_ADDR);
2610         lcdc_dev->prop = PRMRY;
2611         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
2612         dev_drv = &lcdc_dev->driver;
2613         dev_drv->dev = dev;
2614         dev_drv->prop = lcdc_dev->prop;
2615         dev_drv->id = lcdc_dev->id;
2616         dev_drv->ops = &lcdc_drv_ops;
2617         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
2618         spin_lock_init(&lcdc_dev->reg_lock);
2619
2620         lcdc_dev->irq = platform_get_irq(pdev, 0);
2621         if (lcdc_dev->irq < 0) {
2622                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
2623                         lcdc_dev->id);
2624                 ret = -ENXIO;
2625                 goto err_request_irq;
2626         }
2627
2628         ret = devm_request_irq(dev, lcdc_dev->irq, rk312x_lcdc_isr,
2629                                IRQF_DISABLED | IRQF_SHARED,
2630                                dev_name(dev), lcdc_dev);
2631         if (ret) {
2632                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
2633                         lcdc_dev->irq, ret);
2634                 goto err_request_irq;
2635         }
2636
2637         if (dev_drv->iommu_enabled)
2638                 strcpy(dev_drv->mmu_dts_name, VOP_IOMMU_COMPATIBLE_NAME);
2639
2640         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
2641         if (ret < 0) {
2642                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
2643                 goto err_register_fb;
2644         }
2645         lcdc_dev->screen = dev_drv->screen0;
2646
2647         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
2648                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
2649
2650         return 0;
2651 err_register_fb:
2652 err_request_irq:
2653         devm_kfree(lcdc_dev->dev, lcdc_dev->regsbak);
2654 err_remap_reg:
2655 err_parse_dt:
2656         devm_kfree(&pdev->dev, lcdc_dev);
2657         return ret;
2658 }
2659
2660 #if defined(CONFIG_PM)
2661 static int rk312x_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
2662 {
2663         return 0;
2664 }
2665
2666 static int rk312x_lcdc_resume(struct platform_device *pdev)
2667 {
2668         return 0;
2669 }
2670 #else
2671 #define rk312x_lcdc_suspend NULL
2672 #define rk312x_lcdc_resume  NULL
2673 #endif
2674
2675 static int rk312x_lcdc_remove(struct platform_device *pdev)
2676 {
2677         return 0;
2678 }
2679
2680 static void rk312x_lcdc_shutdown(struct platform_device *pdev)
2681 {
2682         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
2683         struct rk_lcdc_driver *dev_drv=&lcdc_dev->driver;
2684
2685         flush_kthread_worker(&dev_drv->update_regs_worker);
2686         kthread_stop(dev_drv->update_regs_thread);
2687
2688         rk312x_lcdc_deinit(lcdc_dev);
2689         rk312x_lcdc_clk_disable(lcdc_dev);
2690         rk_disp_pwr_disable(&lcdc_dev->driver);
2691 }
2692
2693 static struct platform_driver rk312x_lcdc_driver = {
2694         .probe = rk312x_lcdc_probe,
2695         .remove = rk312x_lcdc_remove,
2696         .driver = {
2697                    .name = "rk312x-lcdc",
2698                    .owner = THIS_MODULE,
2699                    .of_match_table = of_match_ptr(rk312x_lcdc_dt_ids),
2700                    },
2701         .suspend = rk312x_lcdc_suspend,
2702         .resume = rk312x_lcdc_resume,
2703         .shutdown = rk312x_lcdc_shutdown,
2704 };
2705
2706 static int __init rk312x_lcdc_module_init(void)
2707 {
2708         return platform_driver_register(&rk312x_lcdc_driver);
2709 }
2710
2711 static void __exit rk312x_lcdc_module_exit(void)
2712 {
2713         platform_driver_unregister(&rk312x_lcdc_driver);
2714 }
2715
2716 fs_initcall(rk312x_lcdc_module_init);
2717 module_exit(rk312x_lcdc_module_exit);