4 #include<linux/rk_fb.h>
8 #define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk))
9 #define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val)
10 #define LcdRdReg(inf, addr) (inf->preg->addr)
11 #define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk))
12 #define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk))
13 #define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk))
14 #define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val))
15 #define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb()
17 /********************************************************************
19 ********************************************************************/
20 /* LCDCµÄ¼Ä´æÆ÷½á¹¹ */
22 typedef volatile struct tagLCDC_REG
24 /* offset 0x00~0xc0 */
25 unsigned int SYS_CTRL0; //0x00 system control register 0
26 unsigned int SYS_CTRL1; //0x04 system control register 1
27 unsigned int DSP_CTRL0; //0x08 display control register 0
28 unsigned int DSP_CTRL1; //0x0c display control register 1
29 unsigned int INT_STATUS; //0x10 Interrupt status register
30 unsigned int MCU_CTRL ; //0x14 MCU mode contol register
31 unsigned int BLEND_CTRL; //0x18 Blending control register
32 unsigned int WIN0_COLOR_KEY_CTRL; //0x1c Win0 blending control register
33 unsigned int WIN1_COLOR_KEY_CTRL; //0x20 Win1 blending control register
34 unsigned int WIN2_COLOR_KEY_CTRL; //0x24 Win2 blending control register
35 unsigned int WIN0_YRGB_MST0; //0x28 Win0 active YRGB memory start address0
36 unsigned int WIN0_CBR_MST0; //0x2c Win0 active Cbr memory start address0
37 unsigned int WIN0_YRGB_MST1; //0x30 Win0 active YRGB memory start address1
38 unsigned int WIN0_CBR_MST1; //0x34 Win0 active Cbr memory start address1
39 unsigned int WIN0_VIR; //0x38 WIN0 virtual display width/height
40 unsigned int WIN0_ACT_INFO; //0x3C Win0 active window width/height
41 unsigned int WIN0_DSP_INFO; //0x40 Win0 display width/height on panel
42 unsigned int WIN0_DSP_ST; //0x44 Win0 display start point on panel
43 unsigned int WIN0_SCL_FACTOR_YRGB; //0x48Win0 YRGB scaling factor setting
44 unsigned int WIN0_SCL_FACTOR_CBR; //0x4c Win0 YRGB scaling factor setting
45 unsigned int WIN0_SCL_OFFSET; //0x50 Win0 Cbr scaling start point offset
46 unsigned int WIN1_YRGB_MST; //0x54 Win1 active YRGB memory start address
47 unsigned int WIN1_CBR_MST; //0x58 Win1 active Cbr memory start address
48 unsigned int WIN1_VIR; //0x5c WIN1 virtual display width/height
49 unsigned int WIN1_ACT_INFO; //0x60 Win1 active window width/height
50 unsigned int WIN1_DSP_INFO; //0x64 Win1 display width/height on panel
51 unsigned int WIN1_DSP_ST; //0x68 Win1 display start point on panel
52 unsigned int WIN1_SCL_FACTOR_YRGB; //0x6c Win1 YRGB scaling factor setting
53 unsigned int WIN1_SCL_FACTOR_CBR; //0x70 Win1 YRGB scaling factor setting
54 unsigned int WIN1_SCL_OFFSET; //0x74 Win1 Cbr scaling start point offset
55 unsigned int WIN2_MST; //0x78 win2 memort start address
56 unsigned int WIN2_VIR; //0x7c win2 virtual stride
57 unsigned int WIN2_DSP_INFO; //0x80 Win2 display width/height on panel
58 unsigned int WIN2_DSP_ST; //0x84 Win2 display start point on panel
59 unsigned int HWC_MST; //0x88 HWC memory start address
60 unsigned int HWC_DSP_ST; //0x8C HWC display start point on panel
61 unsigned int HWC_COLOR_LUT0; //0x90 Hardware cursor color 2¡¯b01 look up table 0
62 unsigned int HWC_COLOR_LUT1; //0x94 Hardware cursor color 2¡¯b10 look up table 1
63 unsigned int HWC_COLOR_LUT2; //0x98 Hardware cursor color 2¡¯b11 look up table 2
64 unsigned int DSP_HTOTAL_HS_END; //0x9c Panel scanning horizontal width and hsync pulse end point
65 unsigned int DSP_HACT_ST_END; //0xa0 Panel active horizontal scanning start/end point
66 unsigned int DSP_VTOTAL_VS_END; //0xa4 Panel scanning vertical height and vsync pulse end point
67 unsigned int DSP_VACT_ST_END; //0xa8 Panel active vertical scanning start/end point
68 unsigned int DSP_VS_ST_END_F1; //0xac Vertical scanning start point and vsync pulse end point of even filed in interlace mode
69 unsigned int DSP_VACT_ST_END_F1; //0xb0 Vertical scanning active start/end point of even filed in interlace mode
70 unsigned int reserved0[(0xc0-0xb4)/4];
71 unsigned int REG_CFG_DONE; //0xc0 REGISTER CONFIG FINISH
72 unsigned int reserved1[(0x100-0xc4)/4];
73 unsigned int MCU_BYPASS_WPORT; //0x100 MCU BYPASS MODE, DATA Write Only Port
74 unsigned int reserved2[(0x200-0x104)/4];
75 unsigned int MCU_BYPASS_RPORT; //0x200 MCU BYPASS MODE, DATA Read Only Port
76 unsigned int reserved3[(0x400-0x204)/4];
77 unsigned int WIN2_LUT_ADDR;
78 unsigned int reserved4[(0x800-0x404)/4];
79 unsigned int DSP_LUT_ADDR;
81 } LCDC_REG, *pLCDC_REG;
85 #define SYS_CTRL0 0x00 //0x00 system control register 0
86 #define SYS_CTRL1 0x04 //0x04 system control register 1
87 #define DSP_CTRL0 0x08 //0x08 display control register 0
88 #define DSP_CTRL1 0x0c //0x0c display control register 1
89 #define INT_STATUS 0x10 //0x10 Interrupt status register
90 #define MCU_CTRL 0x14 //0x14 MCU mode contol register
91 #define BLEND_CTRL 0x18 //0x18 Blending control register
92 #define WIN0_COLOR_KEY_CTRL 0x1c //0x1c Win0 blending control register
93 #define WIN1_COLOR_KEY_CTRL 0x20 //0x20 Win1 blending control register
94 #define WIN2_COLOR_KEY_CTRL 0x24 //0x24 Win2 blending control register
95 #define WIN0_YRGB_MST0 0x28 //0x28 Win0 active YRGB memory start address0
96 #define WIN0_CBR_MST0 0x2c //0x2c Win0 active Cbr memory start address0
97 #define WIN0_YRGB_MST1 0x30 //0x30 Win0 active YRGB memory start address1
98 #define WIN0_CBR_MST1 0x34 //0x34 Win0 active Cbr memory start address1
99 #define WIN0_VIR 0x38 //0x38 WIN0 virtual display width/height
100 #define WIN0_ACT_INFO 0x3c //0x3C Win0 active window width/height
101 #define WIN0_DSP_INFO 0x40 //0x40 Win0 display width/height on panel
102 #define WIN0_DSP_ST 0x44 //0x44 Win0 display start point on panel
103 #define WIN0_SCL_FACTOR_YRGB 0x48 //0x48Win0 YRGB scaling factor setting
104 #define WIN0_SCL_FACTOR_CBR 0x4c //0x4c Win0 YRGB scaling factor setting
105 #define WIN0_SCL_OFFSET 0x50 //0x50 Win0 Cbr scaling start point offset
106 #define WIN1_YRGB_MST 0x54 //0x54 Win1 active YRGB memory start address
107 #define WIN1_CBR_MST 0x58 //0x58 Win1 active Cbr memory start address
108 #define WIN1_VIR 0x5c //0x5c WIN1 virtual display width/height
109 #define WIN1_ACT_INFO 0x60 //0x60 Win1 active window width/height
110 #define WIN1_DSP_INFO 0x64 //0x64 Win1 display width/height on panel
111 #define WIN1_DSP_ST 0x68 //0x68 Win1 display start point on panel
112 #define WIN1_SCL_FACTOR_YRGB 0x6c //0x6c Win1 YRGB scaling factor setting
113 #define WIN1_SCL_FACTOR_CBR 0x70 //0x70 Win1 YRGB scaling factor setting
114 #define WIN1_SCL_OFFSET 0x74 //0x74 Win1 Cbr scaling start point offset
115 #define WIN2_MST 0x78 //0x78 win2 memort start address
116 #define WIN2_VIR 0x7c //0x7c win2 virtual stride
117 #define WIN2_DSP_INFO 0x80 //0x80 Win2 display width/height on panel
118 #define WIN2_DSP_ST 0x84 //0x84 Win2 display start point on panel
119 #define HWC_MST 0x88 //0x88 HWC memory start address
120 #define HWC_DSP_ST 0x8c //0x8C HWC display start point on panel
121 #define HWC_COLOR_LUT0 0x90 //0x90 Hardware cursor color 2¡¯b01 look up table 0
122 #define HWC_COLOR_LUT1 0x94 //0x94 Hardware cursor color 2¡¯b10 look up table 1
123 #define HWC_COLOR_LUT2 0x98 //0x98 Hardware cursor color 2¡¯b11 look up table 2
124 #define DSP_HTOTAL_HS_END 0x9c //0x9c Panel scanning horizontal width and hsync pulse end point
125 #define DSP_HACT_ST_END 0xa0 //0xa0 Panel active horizontal scanning start/end point
126 #define DSP_VTOTAL_VS_END 0xa4 //0xa4 Panel scanning vertical height and vsync pulse end point
127 #define DSP_VACT_ST_END 0xa8 //0xa8 Panel active vertical scanning start/end point
128 #define DSP_VS_ST_END_F1 0xac //0xac Vertical scanning start point and vsync pulse end point of even filed in interlace mode
129 #define DSP_VACT_ST_END_F1 0xb0 //0xb0 Vertical scanning active start/end point of even filed in interlace mode
130 #define REG_CFG_DONE 0xc0 //0xc0 REGISTER CONFIG FINISH
131 #define MCU_BYPASS_WPORT 0x100 //0x100 MCU BYPASS MODE, DATA Write Only Port
132 #define MCU_BYPASS_RPORT 0x200 //0x200 MCU BYPASS MODE, DATA Read Only Port
133 #define WIN2_LUT_ADDR 0x400
134 #define DSP_LUT_ADDR 0x800
137 #define lcdc_writel(lcdc_dev,offset,v) do { \
138 u32 *_pv = (u32*)lcdc_dev->regsbak; \
139 _pv += (offset >> 2); \
140 writel_relaxed(v,lcdc_dev->regs+offset);\
144 #define lcdc_readl(lcdc_dev,offset) \
145 readl_relaxed(lcdc_dev->regs+offset)
147 #define lcdc_read_bit(lcdc_dev,offset,msk) ( { \
148 u32 _v = readl_relaxed(lcdc_dev->regs+offset); \
151 #define lcdc_set_bit(lcdc_dev,offset,msk) do { \
152 u32* _pv = (u32*)lcdc_dev->regsbak; \
153 _pv += (offset >> 2); \
155 writel_relaxed(*_pv,lcdc_dev->regs + offset); \
158 #define lcdc_clr_bit(lcdc_dev,offset,msk) do{ \
159 u32* _pv = (u32*)lcdc_dev->regsbak; \
160 _pv += (offset >> 2); \
162 writel_relaxed(*_pv,lcdc_dev->regs + offset); \
165 #define lcdc_msk_reg(lcdc_dev,offset,msk,v) do { \
166 u32 *_pv = (u32*)lcdc_dev->regsbak; \
167 _pv += (offset >> 2); \
170 writel_relaxed(*_pv,lcdc_dev->regs+offset); \
173 #define lcdc_cfg_done(lcdc_dev) do{ \
174 writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE); \
182 #define m_LCDC_DMA_STOP (1<<0)
183 #define m_LCDC_STANDBY (1<<1)
184 #define m_HWC_RELOAD_EN (1<<2)
185 #define m_W0_AXI_OUTSTANDING_DISABLE (1<<3)
186 #define m_W1_AXI_OUTSTANDING_DISABLE (1<<4)
187 #define m_W2_AXI_OUTSTANDING_DISABLE (1<<5)
188 #define m_DMA_BURST_LENGTH (3<<6)
189 #define m_WIN0_YRGB_CHANNEL0_ID ((0x07)<<8)
190 #define m_WIN0_CBR_CHANNEL0_ID ((0x07)<<11)
191 #define m_WIN0_YRGB_CHANNEL1_ID ((0x07)<<14)
192 #define m_WIN0_CBR_CHANNEL1_ID ((0x07)<<17)
193 #define m_WIN1_YRGB_CHANNEL_ID ((0x07)<<20)
194 #define m_WIN1_CBR_CHANNEL_ID ((0x07)<<23)
195 #define m_WIN2_CHANNEL_ID ((0x07)<<26)
196 #define m_HWC_CHANNEL_ID ((0x07)<<29)
202 #define v_LCDC_DMA_STOP(x) (((x)&1)<<0)
203 #define v_LCDC_STANDBY(x) (((x)&1)<<1)
204 #define v_HWC_RELOAD_EN(x) (((x)&1)<<2)
205 #define v_W0_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<3)
206 #define v_W1_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<4)
207 #define v_W2_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<5)
208 #define v_DMA_BURST_LENGTH(x) (((x)&3)<<6)
209 #define v_WIN0_YRGB_CHANNEL0_ID(x) (((x)&7)<<8)
210 #define v_WIN0_CBR_CHANNEL0_ID(x) (((x)&7)<<11)
211 #define v_WIN0_YRGB_CHANNEL1_ID(x) (((x)&7)<<14)
212 #define v_WIN0_CBR_CHANNEL1_ID(x) (((x)&7)<<17)
213 #define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&7)<<20)
214 #define v_WIN1_CBR_CHANNEL_ID(x) (((x)&7)<<23)
215 #define v_WIN2_CHANNEL_ID(x) (((x)&7)<<26)
216 #define v_HWC_CHANNEL_ID(x) (((x)&7)<<29)
221 #define m_W0_EN (1<<0)
222 #define m_W1_EN (1<<1)
223 #define m_W2_EN (1<<2)
224 #define m_HWC_EN (1<<3)
225 #define m_W0_FORMAT (7<<4)
226 #define m_W1_FORMAT (7<<7)
227 #define m_W2_FORMAT (7<<10)
228 #define m_HWC_COLOR_MODE (1<<13)
229 #define m_HWC_SIZE_SELET (1<<14)
230 #define m_W0_3D_MODE_EN (1<<15)
231 #define m_W0_3D_MODE_SELET (7<<16)
232 #define m_W0_RGB_RB_SWAP (1<<19)
233 #define m_W0_RGB_ALPHA_SWAP (1<<20)
234 #define m_W0_YRGB_M8_SWAP (1<<21)
235 #define m_W0_CBCR_SWAP (1<<22)
236 #define m_W1_RGB_RB_SWAP (1<<23)
237 #define m_W1_RGB_ALPHA_SWAP (1<<24)
238 #define m_W1_YRGB_M8_SWAP (1<<25)
239 #define m_W1_CBCR_SWAP (1<<26)
240 #define m_W2_RGB_RB_SWAP (1<<27)
241 #define m_W2_RGB_ALPHA_SWAP (1<<28)
242 #define m_W2_8pp_PALETTE_ENDIAN_SELECT (1<<29)
243 #define m_W2_LUT_RAM_EN (1<<30)
244 #define m_DSP_LUT_RAM_EN (1<<31)
246 #define v_W0_EN(x) (((x)&1)<<0)
247 #define v_W1_EN(x) (((x)&1)<<1)
248 #define v_W2_EN(x) (((x)&1)<<2)
249 #define v_HWC_EN(x) (((x)&1)<<3)
250 #define v_W0_FORMAT(x) (((x)&7)<<4)
251 #define v_W1_FORMAT(x) (((x)&7)<<7)
252 #define v_W2_FORMAT(x) (((x)&7)<<10)
253 #define v_HWC_COLOR_MODE(x) (((x)&1)<<13)
254 #define v_HWC_SIZE_SELET(x) (((x)&1)<<14)
255 #define v_W0_3D_MODE_EN(x) (((x)&1)<<15)
256 #define v_W0_3D_MODE_SELET(x) (((x)&3)<<16)
257 #define v_W0_RGB_RB_SWAP(x) (((x)&1)<<19)
258 #define v_W0_RGB_ALPHA_SWAP(x) (((x)&1)<<20)
259 #define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<21)
260 #define v_W0_CBCR_SWAP(x) (((x)&1)<<22)
261 #define v_W1_RGB_RB_SWAP(x) (((x)&1)<<23)
262 #define v_W1_RGB_ALPHA_SWAP(x) (((x)&1)<<24)
263 #define v_W1_YRGB_M8_SWAP(x) (((x)&1)<<25)
264 #define v_W1_CBCR_SWAP(x) (((x)&1)<<26)
265 #define v_W2_RGB_RB_SWAP(x) (((x)&1)<<27)
266 #define v_W2_RGB_ALPHA_SWAP(x) (((x)&1)<<28)
267 #define v_W2_8pp_PALETTE_ENDIAN_SELECT (((x)&1)<<29)
268 #define v_W2_LUT_RAM_EN(x) (((x)&1)<<30)
269 #define v_DSP_LUT_RAM_EN(x) (((x)&1)<<31)
272 #define m_DISPLAY_FORMAT (0x0f<<0)
273 #define m_HSYNC_POLARITY (1<<4)
274 #define m_VSYNC_POLARITY (1<<5)
275 #define m_DEN_POLARITY (1<<6)
276 #define m_DCLK_POLARITY (1<<7)
277 #define m_W0W1_POSITION_SWAP (1<<8)
278 #define m_DITHER_UP_EN (1<<9)
279 #define m_DITHER_DOWN_MODE (1<<10)
280 #define m_DITHER_DOWN_EN (1<<11)
281 #define m_INTERLACE_DSP_EN (1<<12)
282 #define m_INTERLACE_FIELD_POLARITY (1<<13)
283 #define m_W0_INTERLACE_READ_MODE (1<<14)
284 #define m_W1_INTERLACE_READ_MODE (1<<15)
285 #define m_W2_INTERLACE_READ_MODE (1<<16)
286 #define m_W0_YRGB_DEFLICK_MODE (1<<17)
287 #define m_W0_CBR_DEFLICK_MODE (1<<18)
288 #define m_W1_YRGB_DEFLICK_MODE (1<<19)
289 #define m_W1_CBR_DEFLICK_MODE (1<<20)
290 #define m_W0_ALPHA_MODE (1<<21)
291 #define m_W1_ALPHA_MODE (1<<22)
292 #define m_W2_ALPHA_MODE (1<<23)
293 #define m_W0_COLOR_SPACE_CONVERSION (3<<24)
294 #define m_W1_COLOR_SPACE_CONVERSION (3<<26)
295 #define m_W2_COLOR_SPACE_CONVERSION (1<<28)
296 #define m_YCRCB_CLIP_EN (1<<29)
297 #define m_CBR_FILTER_656 (1<<30)
298 #define m_LCDC_AXICLK_AUTO_ENABLE (1<<31) //eanble for low power
300 #define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0)
301 #define v_HSYNC_POLARITY(x) (((x)&1)<<4)
302 #define v_VSYNC_POLARITY(x) (((x)&1)<<5)
303 #define v_DEN_POLARITY(x) (((x)&1)<<6)
304 #define v_DCLK_POLARITY(x) (((x)&1)<<7)
305 #define v_W0W1_POSITION_SWAP(x) (((x)&1)<<8)
306 #define v_DITHER_UP_EN(x) (((x)&1)<<9)
307 #define v_DITHER_DOWN_MODE(x) (((x)&1)<<10)
308 #define v_DITHER_DOWN_EN(x) (((x)&1)<<11)
309 #define v_INTERLACE_DSP_EN(x) (((x)&1)<<12)
310 #define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13)
311 #define v_W0_INTERLACE_READ_MODE(x) (((x)&1)<<14)
312 #define v_W1_INTERLACE_READ_MODE(x) (((x)&1)<<15)
313 #define v_W2_INTERLACE_READ_MODE(x) (((x)&1)<<16)
314 #define v_W0_YRGB_DEFLICK_MODE(x) (((x)&1)<<17)
315 #define v_W0_CBR_DEFLICK_MODE(x) (((x)&1)<<18)
316 #define v_W1_YRGB_DEFLICK_MODE(x) (((x)&1)<<19)
317 #define v_W1_CBR_DEFLICK_MODE(x) (((x)&1)<<20)
318 #define v_W0_ALPHA_MODE(x) (((x)&1)<<21)
319 #define v_W1_ALPHA_MODE(x) (((x)&1)<<22)
320 #define v_W2_ALPHA_MODE(x) (((x)&1)<<23)
321 #define v_W0_COLOR_SPACE_CONVERSION(x) (((x)&3)<<24)
322 #define v_W1_COLOR_SPACE_CONVERSION(x) (((x)&3)<<26)
323 #define v_W2_COLOR_SPACE_CONVERSION(x) (((x)&1)<<28)
324 #define v_YCRCB_CLIP_EN(x) (((x)&1)<<29)
325 #define v_CBR_FILTER_656(x) (((x)&1)<<30)
326 #define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<31) //eanble for low power
329 #define m_BG_COLOR (0xffffff<<0)
330 #define m_BG_B (0xff<<0)
331 #define m_BG_G (0xff<<8)
332 #define m_BG_R (0xff<<16)
333 #define m_BLANK_MODE (1<<24)
334 #define m_BLACK_MODE (1<<25)
335 #define m_OUTPUT_BG_SWAP (1<<26)
336 #define m_OUTPUT_RB_SWAP (1<<27)
337 #define m_OUTPUT_RG_SWAP (1<<28)
338 #define m_DELTA_SWAP (1<<29)
339 #define m_DUMMY_SWAP (1<<30)
341 #define v_BG_COLOR(x) (((x)&0xffffff)<<0)
342 #define v_BG_B(x) (((x)&0xff)<<0)
343 #define v_BG_G(x) (((x)&0xff)<<8)
344 #define v_BG_R(x) (((x)&0xff)<<16)
345 #define v_BLANK_MODE(x) (((x)&1)<<24)
346 #define v_BLACK_MODE(x) (((x)&1)<<25)
347 #define v_OUTPUT_BG_SWAP(x) (((x)&1)<<26)
348 #define v_OUTPUT_RB_SWAP(x) (((x)&1)<<27)
349 #define v_OUTPUT_RG_SWAP(x) (((x)&1)<<28)
350 #define v_DELTA_SWAP(x) (((x)&1)<<29)
351 #define v_DUMMY_SWAP(x) (((x)&1)<<30)
355 #define v_HOR_START_INT_STA (1<<0) //status
356 #define v_FRM_START_INT_STA (1<<1)
357 #define v_LINE_FLAG_INT_STA (1<<2)
358 #define v_BUS_ERR_INT_STA (1<<3)
359 #define m_HOR_START_INT_EN (1<<4) //enable
360 #define m_FRM_START_INT_EN (1<<5)
361 #define m_LINE_FLAG_INT_EN (1<<6)
362 #define m_BUS_ERR_INT_EN (1<<7)
363 #define m_HOR_START_INT_CLEAR (1<<8) //auto clear
364 #define m_FRM_START_INT_CLEAR (1<<9)
365 #define m_LINE_FLAG_INT_CLEAR (1<<10)
366 #define m_BUS_ERR_INT_CLEAR (1<<11)
367 #define m_LINE_FLAG_NUM (0xfff<<12)
368 #define v_HOR_START_INT_EN(x) (((x)&1)<<4)
369 #define v_FRM_START_INT_EN(x) (((x)&1)<<5)
370 #define v_LINE_FLAG_INT_EN(x) (((x)&1)<<6)
371 #define v_BUS_ERR_INT_EN(x) (((x)&1)<<7)
372 #define v_HOR_START_INT_CLEAR(x) (((x)&1)<<8)
373 #define v_FRM_START_INT_CLEAR(x) (((x)&1)<<9)
374 #define v_LINE_FLAG_INT_CLEAR(x) (((x)&1)<<10)
375 #define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11)
376 #define v_LINE_FLAG_NUM(x) (((x)&0xfff)<<12)
380 //LCDC_MCU_TIMING_CTRL
381 #define m_MCU_WRITE_PERIOD (0x3f<<0)
382 #define m_MCU_CS_ST (0xf<<6)
383 #define m_MCU_CS_END (0x3f<<10)
384 #define m_MCU_RW_ST (0xf<<16)
385 #define m_MCU_RW_END (0x3f<<20)
386 #define m_MCU_BPS_CLK_SEL (1<<26)
387 #define m_MCU_HOLDMODE_SELECT (1<<27)
388 #define m_MCU_HOLDMODE_FRAME_ST (1<<28)
389 #define m_MCU_RS_SELECT (1<<29)
390 #define m_MCU_BYPASSMODE_SELECT (1<<30)
391 #define m_MCU_OUTPUT_SELECT (1<<31)
392 #define v_MCU_WRITE_PERIOD(x) (((x)&0x3f)<<0)
393 #define v_MCU_CS_ST(x) (((x)&0xf)<<6)
394 #define v_MCU_CS_END(x) (((x)&0x3f)<<10)
395 #define v_MCU_RW_ST(x) (((x)&0xf)<<16)
396 #define v_MCU_RW_END(x) (((x)&0x3f)<<20)
397 #define v_MCU_BPS_CLK_SEL (((x)&1)<<26)
398 #define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27)
399 #define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28)
400 #define v_MCU_RS_SELECT(x) (((x)&1)<<29)
401 #define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30)
402 #define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31)
405 #define m_W0_BLEND_EN (1<<0)
406 #define m_W1_BLEND_EN (1<<1)
407 #define m_W2_BLEND_EN (1<<2)
408 #define m_HWC_BLEND_EN (1<<3)
409 #define m_W0_BLEND_FACTOR (15<<4)
410 #define m_W1_BLEND_FACTOR (0xff<<8)
411 #define m_W2_BLEND_FACTOR (0xff<<16)
412 #define m_HWC_BLEND_FACTOR (0xff<<24)
414 #define v_W0_BLEND_EN(x) (((x)&1)<<0)
415 #define v_W1_BLEND_EN(x) (((x)&1)<<1)
416 #define v_W2_BLEND_EN(x) (((x)&1)<<2)
417 #define v_HWC_BLEND_EN(x) (((x)&1)<<3)
418 #define v_W0_BLEND_FACTOR(x) (((x)&15)<<4)
419 #define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<8)
420 #define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<16)
421 #define v_HWC_BLEND_FACTOR(x) (((x)&0xff)<<24)
424 //LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL
425 #define m_KEYCOLOR (0xffffff<<0)
426 #define m_KEYCOLOR_B (0xff<<0)
427 #define m_KEYCOLOR_G (0xff<<8)
428 #define m_KEYCOLOR_R (0xff<<16)
429 #define m_COLORKEY_EN (1<<24)
430 #define v_KEYCOLOR(x) (((x)&0xffffff)<<0)
431 #define v_KEYCOLOR_B(x) (((x)&0xff)<<0)
432 #define v_KEYCOLOR_G(x) (((x)&0xff)<<8)
433 #define v_KEYCOLOR_R(x) (((x)&0xff)<<16)
434 #define v_COLORKEY_EN(x) (((x)&1)<<24)
436 //LCDC_DEFLICKER_SCL_OFFSET
437 #define m_W0_YRGB_VSD_OFFSET (0xff<<0)
438 #define m_W0_YRGB_VSP_OFFSET (0xff<<8)
439 #define m_W1_VSD_OFFSET (0xff<<16)
440 #define m_W1_VSP_OFFSET (0xff<<24)
441 #define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0)
442 #define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8)
443 #define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16)
444 #define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24)
451 #define m_W0_YRGB_CH_ID (0xF<<0)
452 #define m_W0_CBR_CH_ID (0xF<<4)
453 #define m_W1_YRGB_CH_ID (0xF<<8)
454 #define m_W2_CH_ID (0xF<<12)
455 #define m_HWC_CH_ID (0xF<<16)
456 #define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0)
457 #define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4)
458 #define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8)
459 #define v_W2_CH_ID(x) (((x)&0xF)<<12)
460 #define v_HWC_CH_ID(x) (((x)&0xF)<<16)
464 #define m_WORDLO (0xffff<<0)
465 #define m_WORDHI (0xffff<<16)
466 #define v_WORDLO(x) (((x)&0xffff)<<0)
467 #define v_WORDHI(x) (((x)&0xffff)<<16)
470 //LCDC_WINx_SCL_FACTOR_Y/CBCR
471 #define v_X_SCL_FACTOR(x) ((x)<<0)
472 #define v_Y_SCL_FACTOR(x) ((x)<<16)
474 //LCDC_DSP_HTOTAL_HS_END
475 #define v_HSYNC(x) ((x)<<0) //hsync pulse width
476 #define v_HORPRD(x) ((x)<<16) //horizontal period
479 //LCDC_DSP_HACT_ST_END
480 #define v_HAEP(x) ((x)<<0) //horizontal active end point
481 #define v_HASP(x) ((x)<<16) //horizontal active start point
483 //LCDC_DSP_VTOTAL_VS_END
484 #define v_VSYNC(x) ((x)<<0)
485 #define v_VERPRD(x) ((x)<<16)
487 //LCDC_DSP_VACT_ST_END
488 #define v_VAEP(x) ((x)<<0)
489 #define v_VASP(x) ((x)<<16)
492 //LCDC_WINx_VIR ,x is number of words of win0 virtual width
493 #define v_ARGB888_VIRWIDTH(x) (x)
494 #define v_RGB888_VIRWIDTH(x) (((x*3)>>2)+((x)%3))
495 #define v_RGB565_VIRWIDTH(x) (((x)>>1) + ((x%2)?1:0))
496 #define v_YUV_VIRWIDTH(x) (((x)>>2) +((x%4)?1:0))
498 #define m_ACTWIDTH (0xffff<<0)
499 #define m_ACTHEIGHT (0xffff<<16)
500 #define v_ACTWIDTH(x) (((x)&0xffff)<<0)
501 #define v_ACTHEIGHT(x) (((x)&0xffff)<<16)
503 #define m_VIRST_X (0xffff<<0)
504 #define m_VIRST_Y (0xffff<<16)
505 #define v_VIRST_X(x) (((x)&0xffff)<<0)
506 #define v_VIRST_Y(x) (((x)&0xffff)<<16)
508 #define m_PANELST_X (0x3ff<<0)
509 #define m_PANELST_Y (0x3ff<<16)
510 #define v_PANELST_X(x) (((x)&0x3ff)<<0)
511 #define v_PANELST_Y(x) (((x)&0x3ff)<<16)
513 #define m_PANELWIDTH (0x3ff<<0)
514 #define m_PANELHEIGHT (0x3ff<<16)
515 #define v_PANELWIDTH(x) (((x)&0x3ff)<<0)
516 #define v_PANELHEIGHT(x) (((x)&0x3ff)<<16)
518 #define m_HWC_B (0xff<<0)
519 #define m_HWC_G (0xff<<8)
520 #define m_HWC_R (0xff<<16)
521 #define m_W0_YRGB_HSP_OFFSET (0xff<<24)
522 #define m_W0_YRGB_HSD_OFFSET (0xff<<24)
523 #define v_HWC_B(x) (((x)&0xff)<<0)
524 #define v_HWC_G(x) (((x)&0xff)<<8)
525 #define v_HWC_R(x) (((x)&0xff)<<16)
526 #define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24)
527 #define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24)
530 #define v_ACT_WIDTH(x) ((x-1)<<0)
531 #define v_ACT_HEIGHT(x) ((x-1)<<16)
534 #define v_DSP_WIDTH(x) ((x-1)<<0)
535 #define v_DSP_HEIGHT(x) ((x-1)<<16)
537 //LCDC_WIN0_DSP_ST //x,y start point of the panel scanning
538 #define v_DSP_STX(x) (x<<0)
539 #define v_DSP_STY(x) (x<<16)
541 //Panel display scanning
542 #define m_PANEL_HSYNC_WIDTH (0x3ff<<0)
543 #define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16)
544 #define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0)
545 #define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16)
547 #define m_PANEL_END (0x3ff<<0)
548 #define m_PANEL_START (0x3ff<<16)
549 #define v_PANEL_END(x) (((x)&0x3ff)<<0)
550 #define v_PANEL_START(x) (((x)&0x3ff)<<16)
552 #define m_PANEL_VSYNC_WIDTH (0x3ff<<0)
553 #define m_PANEL_VERTICAL_PERIOD (0x3ff<<16)
554 #define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0)
555 #define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16)
558 #define m_HSCALE_FACTOR (0xffff<<0)
559 #define m_VSCALE_FACTOR (0xffff<<16)
560 #define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0)
561 #define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16)
563 #define m_W0_CBR_HSD_OFFSET (0xff<<0)
564 #define m_W0_CBR_HSP_OFFSET (0xff<<8)
565 #define m_W0_CBR_VSD_OFFSET (0xff<<16)
566 #define m_W0_CBR_VSP_OFFSET (0xff<<24)
567 #define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0)
568 #define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8)
569 #define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16)
570 #define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24)
574 #define CalScale(x, y) (((u32)x*0x1000)/y)
575 struct rk30_lcdc_device{
577 struct rk_lcdc_device_driver driver;
580 //LCDC_REG *preg; // LCDC reg base address and backup reg
583 void *regsbak; //back up reg
584 int __iomem *dsp_lut_addr_base;
586 void __iomem *reg_vir_base; // virtual basic address of lcdc register
587 u32 reg_phy_base; // physical basic address of lcdc register
588 u32 len; // physical map length of lcdc register
589 spinlock_t reg_lock; //one time only one process allowed to config the register
590 bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed
591 u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc
595 struct clk *pd; //lcdc power domain
596 struct clk *hclk; //lcdc AHP clk
597 struct clk *dclk; //lcdc dclk
598 struct clk *aclk; //lcdc share memory frequency
599 struct clk *aclk_parent; //lcdc aclk divider frequency source
600 struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable.
601 struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable.
602 struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable.
603 struct clk *pd_display; // display power domain
609 struct rk30_lcdc_device lcdc0;
610 struct rk30_lcdc_device lcdc1;
616 volatile u32 y_offset;
617 volatile u32 c_offset;
625 u32 xpos; //size in panel
627 u32 xsize; //start point in panel
629 enum data_format format;
631 wait_queue_head_t wait;
632 struct win_set mirror;
633 struct win_set displ;
641 static inline void lcdc_writel(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 v)
643 u32 *_pv = (u32*)lcdc_dev->regsbak;
644 _pv += (offset >> 2);
646 writel_relaxed(v,lcdc_dev->regs+offset);
649 static inline u32 lcdc_readl(struct rk30_lcdc_device *lcdc_dev,u32 offset)
652 u32 *_pv = (u32*)lcdc_dev->regsbak;
653 _pv += (offset >> 2);
654 v = readl_relaxed(lcdc_dev->regs+offset);
659 static inline u32 lcdc_read_bit(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 msk)
661 u32 _v = readl_relaxed(lcdc_dev->regs+offset);
666 static inline void lcdc_set_bit(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 msk)
668 u32* _pv = (u32*)lcdc_dev->regsbak;
669 _pv += (offset >> 2);
671 writel_relaxed(*_pv,lcdc_dev->regs + offset);
674 static inline void lcdc_clr_bit(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 msk)
676 u32* _pv = (u32*)lcdc_dev->regsbak;
677 _pv += (offset >> 2);
679 writel_relaxed(*_pv,lcdc_dev->regs + offset);
682 static inline void lcdc_msk_reg(struct rk30_lcdc_device *lcdc_dev,u32 offset,u32 msk,u32 v)
684 u32 *_pv = (u32*)lcdc_dev->regsbak;
685 _pv += (offset >> 2);
688 writel_relaxed(*_pv,lcdc_dev->regs+offset);
691 static inline void lcdc_cfg_done(struct rk30_lcdc_device *lcdc_dev)
693 writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE);