1 /* drivers/video/rockchip/chips/rk29_fb.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __RK3066B_LCDC_H
17 #define __RK3066B_LCDC_H
19 #include<linux/rk_fb.h>
21 #define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk))
22 #define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val)
23 #define LcdRdReg(inf, addr) (inf->preg->addr)
24 #define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk))
25 #define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk))
26 #define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk))
27 #define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val))
28 #define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb()
31 /********************************************************************
33 ********************************************************************/
35 #define m_W2_FORMAT (3<<0)
36 #define m_W1_FORMAT (1<<2)
37 #define m_W0_FORMAT (7<<3)
38 #define m_W0_CBR_DEFLICK_EN (1<<6)
39 #define m_W0_YRGB_DEFLICK_EN (1<<7)
40 #define m_INTERIACE_EN (1<<8)
41 #define m_W2_EN (1<<9)
42 #define m_W1_EN (1<<10)
43 #define m_W0_EN (1<<11)
44 #define m_HWC_EN (1<<12)
45 #define m_HWC_RELOAD_EN (1<<13)
46 #define m_W2_INTERLACE_READ (1<<14)
47 #define m_W1_INTERLACE_READ (1<<15)
48 #define m_W0_INTERLACE_READ (1<<16)
49 #define m_LCDC_STANDBY (1<<17)
50 #define m_HWC_BURST (3<<18)
51 #define m_W2_BURST (3<<20)
52 #define m_W1_BURST (3<<22)
53 #define m_W0_BURST (3<<24)
54 #define m_W2_LUT_CTL (1<<26)
55 #define m_DSIP_LUT_CTL (1<<27)
56 #define m_HWC_REVERSED_COLOR (1<<28)
57 #define m_W1_AXI_OUTSTANDING2 (1<<29)
58 #define m_W0_AXI_OUTSTANDING2 (1<<30)
59 #define m_LCDC_AXICLK_AUTO_ENABLE (1<<31)
61 #define v_W2_FORMAT(x) (((x)&3)<<0)
62 #define v_W1_FORMAT(x) (((x)&1)<<2)
63 #define v_W0_FORMAT(x) (((x)&7)<<3)
64 #define v_W0_CBR_DEFLICK_EN(x) (((x)&1)<<6)
65 #define v_W0_YRGB_DEFLICK_EN(x) (((x)&1)<<7)
66 #define v_INTERIACE_EN(x) (((x)&1)<<8)
67 #define v_W2_EN(x) (((x)&)1<<9)
68 #define v_W1_EN(x) (((x)&1)<<10)
69 #define v_W0_EN(x) (((x)&1)<<11)
70 #define v_HWC_EN(x) (((x)&1)<<12)
71 #define v_HWC_RELOAD_EN(x) (((x)&1)<<13)
72 #define v_W2_INTERLACE_READ(x) (((x)&1)<<14)
73 #define v_W1_INTERLACE_READ(x) (((x)&1)<<15)
74 #define v_W0_INTERLACE_READ(x) (((x)&1)<<16)
75 #define v_LCDC_STANDBY(x) (((x)&1)<<17)
76 #define v_HWC_BURST(x) (((x)&3)<<18)
77 #define v_W2_BURST(x) (((x)&3)<<20)
78 #define v_W1_BURST(x) (((x)&3)<<22)
79 #define v_W0_BURST(x) (((x)&3)<<24)
80 #define v_W2_LUT_CTL(x) (((x)&1)<<26)
81 #define v_DSIP_LUT_CTL(x) (((x)&1)<<27)
82 #define v_HWC_REVERSED_COLOR(x) (((x)&1)<<28)
83 #define v_W1_AXI_OUTSTANDING2(x) (((x)&1)<<29)
84 #define v_W0_AXI_OUTSTANDING2(x) (((x)&1)<<30)
85 #define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<31)
88 #define m_W1_565_RB_SWAP (1<<0)
89 #define m_W0_565_RB_SWAP (1<<1)
90 #define m_W0_YRGB_M8_SWAP (1<<2)
91 #define m_W0_YRGB_R_SHIFT_SWAP (1<<3)
92 #define m_W0_CBR_R_SHIFT_SWAP (1<<4)
93 #define m_W0_YRGB_16_SWAP (1<<5)
94 #define m_W0_YRGB_8_SWAP (1<<6)
95 #define m_W0_CBR_16_SWAP (1<<7)
96 #define m_W0_CBR_8_SWAP (1<<8)
97 #define m_W1_16_SWAP (1<<9)
98 #define m_W1_8_SWAP (1<<10)
99 #define m_W1_R_SHIFT_SWAP (1<<11)
100 #define m_OUTPUT_BG_SWAP (1<<12)
101 #define m_OUTPUT_RB_SWAP (1<<13)
102 #define m_OUTPUT_RG_SWAP (1<<14)
103 #define m_DELTA_SWAP (1<<15)
104 #define m_DUMMY_SWAP (1<<16)
105 #define m_W2_BYTE_SWAP (1<<17)
106 #define v_W1_565_RB_SWAP(x) (((x)&1)<<0)
107 #define v_W0_565_RB_SWAP(x) (((x)&1)<<1)
108 #define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<2)
109 #define v_W0_YRGB_R_SHIFT_SWAP(x) (((x)&1)<<3)
110 #define v_W0_CBR_R_SHIFT_SWAP(x) (((x)&1)<<4)
111 #define v_W0_YRGB_16_SWAP(x) (((x)&1)<<5)
112 #define v_W0_YRGB_8_SWAP(x) (((x)&1)<<6)
113 #define v_W0_CBR_16_SWAP(x) (((x)&1)<<7)
114 #define v_W0_CBR_8_SWAP(x) (((x)&1)<<8)
115 #define v_W1_16_SWAP(x) (((x)&1)<<9)
116 #define v_W1_8_SWAP(x) (((x)&1)<<10)
117 #define v_W1_R_SHIFT_SWAP(x) (((x)&1)<<11)
118 #define v_OUTPUT_BG_SWAP(x) (((x)&1)<<12)
119 #define v_OUTPUT_RB_SWAP(x) (((x)&1)<<13)
120 #define v_OUTPUT_RG_SWAP(x) (((x)&1)<<14)
121 #define v_DELTA_SWAP(x) (((x)&1)<<15)
122 #define v_DUMMY_SWAP(x) (((x)&1)<<16)
123 #define v_W2_BYTE_SWAP(x) (((x)&1)<<17)
125 //LCDC_MCU_TIMING_CTRL
126 #define m_MCU_WRITE_PERIOD (31<<0)
127 #define m_MCU_CS_ST (31<<5)
128 #define m_MCU_CS_END (31<<10)
129 #define m_MCU_RW_ST (31<<15)
130 #define m_MCU_RW_END (31<<20)
131 #define m_MCU_HOLDMODE_SELECT (1<<27)
132 #define m_MCU_HOLDMODE_FRAME_ST (1<<28)
133 #define m_MCU_RS_SELECT (1<<29)
134 #define m_MCU_BYPASSMODE_SELECT (1<<30)
135 #define m_MCU_OUTPUT_SELECT (1<<31)
136 #define v_MCU_WRITE_PERIOD(x) (((x)&31)<<0)
137 #define v_MCU_CS_ST(x) (((x)&31)<<5)
138 #define v_MCU_CS_END(x) (((x)&31)<<10)
139 #define v_MCU_RW_ST(x) (((x)&31)<<15)
140 #define v_MCU_RW_END(x) (((x)&31)<<20)
141 #define v_MCU_HOLD_STATUS(x) (((x)&1)<<26)
142 #define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27)
143 #define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28)
144 #define v_MCU_RS_SELECT(x) (((x)&1)<<29)
145 #define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30)
146 #define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31)
149 #define m_HWC_BLEND_EN (1<<0)
150 #define m_W2_BLEND_EN (1<<1)
151 #define m_W1_BLEND_EN (1<<2)
152 #define m_W0_BLEND_EN (1<<3)
153 #define m_HWC_BLEND_FACTOR (15<<4)
154 #define m_W2_BLEND_FACTOR (0xff<<8)
155 #define m_W1_BLEND_FACTOR (0xff<<16)
156 #define m_W0_BLEND_FACTOR (0xff<<24)
158 #define v_HWC_BLEND_EN(x) (((x)&1)<<0)
159 #define v_W2_BLEND_EN(x) (((x)&1)<<1)
160 #define v_W1_BLEND_EN(x) (((x)&1)<<2)
161 #define v_W0_BLEND_EN(x) (((x)&1)<<3)
162 #define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4)
163 #define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8)
164 #define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16)
165 #define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24)
168 //LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL
169 #define m_KEYCOLOR (0xffffff<<0)
170 #define m_KEYCOLOR_B (0xff<<0)
171 #define m_KEYCOLOR_G (0xff<<8)
172 #define m_KEYCOLOR_R (0xff<<16)
173 #define m_COLORKEY_EN (1<<24)
174 #define v_KEYCOLOR(x) (((x)&0xffffff)<<0)
175 #define v_KEYCOLOR_B(x) (((x)&0xff)<<0)
176 #define v_KEYCOLOR_G(x) (((x)&0xff)<<8)
177 #define v_KEYCOLOR_R(x) (((x)&0xff)<<16)
178 #define v_COLORKEY_EN(x) (((x)&1)<<24)
180 //LCDC_DEFLICKER_SCL_OFFSET
181 #define m_W0_YRGB_VSD_OFFSET (0xff<<0)
182 #define m_W0_YRGB_VSP_OFFSET (0xff<<8)
183 #define m_W1_VSD_OFFSET (0xff<<16)
184 #define m_W1_VSP_OFFSET (0xff<<24)
185 #define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0)
186 #define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8)
187 #define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16)
188 #define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24)
191 #define m_DISPLAY_FORMAT (0xf<<0)
192 #define m_HSYNC_POLARITY (1<<4)
193 #define m_VSYNC_POLARITY (1<<5)
194 #define m_DEN_POLARITY (1<<6)
195 #define m_DCLK_POLARITY (1<<7)
196 #define m_COLOR_SPACE_CONVERSION (3<<8)
197 #define m_DITHER_UP_EN (1<<10)
198 #define m_DITHER_DOWN_MODE (1<<11)
199 #define m_DITHER_DOWN_EN (1<<12)
200 #define m_INTERLACE_FIELD_POLARITY (1<<13)
201 #define m_YUV_CLIP (1<<14)
202 #define m_W1_TRANSP_FROM (1<<15)
203 #define m_W0_TRANSP_FROM (1<<16)
204 #define m_W0W1_POSITION_SWAP (1<<17)
205 #define m_W1_CLIP_EN (1<<18)
206 #define m_W0_CLIP_EN (1<<19)
207 #define m_W0_YCBR_PRIORITY_MODE (1<<20)
208 #define m_CBR_FILTER_656 (1<<21)
209 #define m_W2_CHIP_EN (1<<22)
211 #define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0)
212 #define v_HSYNC_POLARITY(x) (((x)&1)<<4)
213 #define v_VSYNC_POLARITY(x) (((x)&1)<<5)
214 #define v_DEN_POLARITY(x) (((x)&1)<<6)
215 #define v_DCLK_POLARITY(x) (((x)&1)<<7)
216 #define v_COLOR_SPACE_CONVERSION(x) (((x)&3)<<8)
217 #define v_DITHER_UP_EN(x) (((x)&1)<<10)
218 #define v_DITHER_DOWN_MODE(x) (((x)&1)<<11)
219 #define v_DITHER_DOWN_EN(x) (((x)&1)<<12)
220 #define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13)
221 #define v_YUV_CLIP(x) (((x)&1)<<14)
222 #define v_W1_TRANSP_FROM(x) (((x)&1)<<15)
223 #define v_W0_TRANSP_FROM(x) (((x)&1)<<16)
224 #define v_W0W1_POSITION_SWAP(x) (((x)&1)<<17)
225 #define v_W1_CLIP_EN(x) (((x)&1)<<18)
226 #define v_W0_CLIP_EN(x) (((x)&1)<<19)
227 #define v_W0_YCBR_PRIORITY_MODE(x) (((x)&1)<<20)
228 #define v_CBR_FILTER_656(x) (((x)&1)<<21)
229 #define v_W2_CHIP_EN(x) (((x)&1)<<22)
233 #define m_BG_COLOR (0xffffff<<0)
234 #define m_BG_B (0xff<<0)
235 #define m_BG_G (0xff<<8)
236 #define m_BG_R (0xff<<16)
237 #define m_BLANK_MODE (1<<24)
238 #define m_BLACK_MODE (1<<25)
239 #define m_DISP_FILTER_FACTOR (3<<26)
240 #define m_DISP_FILTER_MODE (1<<28)
241 #define m_DISP_FILTER_EN (1<<29)
242 #define v_BG_COLOR(x) (((x)&0xffffff)<<0)
243 #define v_BG_B(x) (((x)&0xff)<<0)
244 #define v_BG_G(x) (((x)&0xff)<<8)
245 #define v_BG_R(x) (((x)&0xff)<<16)
246 #define v_BLANK_MODE(x) (((x)&1)<<24)
247 #define v_BLACK_MODE(x) (((x)&1)<<25)
248 #define v_DISP_FILTER_FACTOR(x) (((x)&3)<<26)
249 #define v_DISP_FILTER_MODE(x) (((x)&1)<<28)
250 #define v_DISP_FILTER_EN(x) (((x)&1)<<29)
253 #define m_HOR_START (1<<0)
254 #define m_FRM_START (1<<1)
255 #define m_SCANNING_FLAG (1<<2)
256 #define m_HOR_STARTMASK (1<<3)
257 #define m_FRM_STARTMASK (1<<4)
258 #define m_SCANNING_MASK (1<<5)
259 #define m_HOR_STARTCLEAR (1<<6)
260 #define m_FRM_STARTCLEAR (1<<7)
261 #define m_SCANNING_CLEAR (1<<8)
262 #define m_SCAN_LINE_NUM (0x7ff<<9)
263 #define v_HOR_START(x) (((x)&1)<<0)
264 #define v_FRM_START(x) (((x)&1)<<1)
265 #define v_SCANNING_FLAG(x) (((x)&1)<<2)
266 #define v_HOR_STARTMASK(x) (((x)&1)<<3)
267 #define v_FRM_STARTMASK(x) (((x)&1)<<4)
268 #define v_SCANNING_MASK(x) (((x)&1)<<5)
269 #define v_HOR_STARTCLEAR(x) (((x)&1)<<6)
270 #define v_FRM_STARTCLEAR(x) (((x)&1)<<7)
271 #define v_SCANNING_CLEAR(x) (((x)&1)<<8)
272 #define v_SCAN_LINE_NUM(x) (((x)&0x7ff)<<9)
275 #define m_W0_YRGB_CH_ID (0xF<<0)
276 #define m_W0_CBR_CH_ID (0xF<<4)
277 #define m_W1_YRGB_CH_ID (0xF<<8)
278 #define m_W2_CH_ID (0xF<<12)
279 #define m_HWC_CH_ID (0xF<<16)
280 #define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0)
281 #define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4)
282 #define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8)
283 #define v_W2_CH_ID(x) (((x)&0xF)<<12)
284 #define v_HWC_CH_ID(x) (((x)&0xF)<<16)
288 #define m_WORDLO (0xffff<<0)
289 #define m_WORDHI (0xffff<<16)
290 #define v_WORDLO(x) (((x)&0xffff)<<0)
291 #define v_WORDHI(x) (((x)&0xffff)<<16)
293 #define m_BIT11LO (0x7ff<<0)
294 #define m_BIT11HI (0x7ff<<16)
295 #define v_BIT11LO(x) (((x)&0x7ff)<<0)
296 #define v_BIT11HI(x) (((x)&0x7ff)<<16)
298 #define m_BIT12LO (0xfff<<0)
299 #define m_BIT12HI (0xfff<<16)
300 #define v_BIT12LO(x) (((x)&0xfff)<<0)
301 #define v_BIT12HI(x) (((x)&0xfff)<<16)
304 #define m_VIRWIDTH (0xffff<<0)
305 #define m_VIRHEIGHT (0xffff<<16)
306 #define v_VIRWIDTH(x) (((x)&0xffff)<<0)
307 #define v_VIRHEIGHT(x) (((x)&0xffff)<<16)
309 #define m_ACTWIDTH (0xffff<<0)
310 #define m_ACTHEIGHT (0xffff<<16)
311 #define v_ACTWIDTH(x) (((x)&0xffff)<<0)
312 #define v_ACTHEIGHT(x) (((x)&0xffff)<<16)
314 #define m_VIRST_X (0xffff<<0)
315 #define m_VIRST_Y (0xffff<<16)
316 #define v_VIRST_X(x) (((x)&0xffff)<<0)
317 #define v_VIRST_Y(x) (((x)&0xffff)<<16)
319 #define m_PANELST_X (0x3ff<<0)
320 #define m_PANELST_Y (0x3ff<<16)
321 #define v_PANELST_X(x) (((x)&0x3ff)<<0)
322 #define v_PANELST_Y(x) (((x)&0x3ff)<<16)
324 #define m_PANELWIDTH (0x3ff<<0)
325 #define m_PANELHEIGHT (0x3ff<<16)
326 #define v_PANELWIDTH(x) (((x)&0x3ff)<<0)
327 #define v_PANELHEIGHT(x) (((x)&0x3ff)<<16)
329 #define m_HWC_B (0xff<<0)
330 #define m_HWC_G (0xff<<8)
331 #define m_HWC_R (0xff<<16)
332 #define m_W0_YRGB_HSP_OFFSET (0xff<<24)
333 #define m_W0_YRGB_HSD_OFFSET (0xff<<24)
334 #define v_HWC_B(x) (((x)&0xff)<<0)
335 #define v_HWC_G(x) (((x)&0xff)<<8)
336 #define v_HWC_R(x) (((x)&0xff)<<16)
337 #define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24)
338 #define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24)
341 //Panel display scanning
342 #define m_PANEL_HSYNC_WIDTH (0x3ff<<0)
343 #define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16)
344 #define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0)
345 #define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16)
347 #define m_PANEL_END (0x3ff<<0)
348 #define m_PANEL_START (0x3ff<<16)
349 #define v_PANEL_END(x) (((x)&0x3ff)<<0)
350 #define v_PANEL_START(x) (((x)&0x3ff)<<16)
352 #define m_PANEL_VSYNC_WIDTH (0x3ff<<0)
353 #define m_PANEL_VERTICAL_PERIOD (0x3ff<<16)
354 #define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0)
355 #define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16)
358 #define m_HSCALE_FACTOR (0xffff<<0)
359 #define m_VSCALE_FACTOR (0xffff<<16)
360 #define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0)
361 #define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16)
363 #define m_W0_CBR_HSD_OFFSET (0xff<<0)
364 #define m_W0_CBR_HSP_OFFSET (0xff<<8)
365 #define m_W0_CBR_VSD_OFFSET (0xff<<16)
366 #define m_W0_CBR_VSP_OFFSET (0xff<<24)
367 #define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0)
368 #define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8)
369 #define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16)
370 #define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24)
373 #define m_WIN1_FIFO_FULL_LEVEL (0x7f << 0)
374 #define m_WIN2_FIFO_FULL_LEVEL (0x1f << 7)
375 #define v_WIN1_FIFO_FULL_LEVEL(x) (((x)&0x7f) << 0)
376 #define v_WIN2_FIFO_FULL_LEVEL(x) (((x)&0x1f) << 7)
379 #define m_WIN0_YRGB_CHANNEL_ID ((0x0f)<<0)
380 #define m_WIN0_CBR_CHANNEL_ID ((0x0f)<<4)
381 #define m_WIN1_YRGB_CHANNEL_ID ((0x0f)<<8)
382 #define m_WIN2_CHANNEL_ID ((0x0f)<<12)
383 #define m_HWC_CHANNEL_ID ((0x0f)<<16)
384 #define v_WIN0_YRGB_CHANNEL_ID(x) (((x)&0x0f)<<0)
385 #define v_WIN0_CBR_CHANNEL_ID(x) (((x)&0x0f)<<4)
386 #define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&0x0f)<<8)
387 #define v_WIN2_CHANNEL_ID(x) (((x)&0x0f)<<12)
388 #define v_HWC_CHANNEL_ID(x) (((x)&0x0f)<<16)
391 //LCDC_WINx_SCL_FACTOR_Y/CBCR
392 #define v_X_SCL_FACTOR(x) ((x)<<0)
393 #define v_Y_SCL_FACTOR(x) ((x)<<16)
395 //LCDC_DSP_HTOTAL_HS_END
396 #define v_HSYNC(x) ((x)<<0) //hsync pulse width
397 #define v_HORPRD(x) ((x)<<16) //horizontal period
400 //LCDC_DSP_HACT_ST_END
401 #define v_HAEP(x) ((x)<<0) //horizontal active end point
402 #define v_HASP(x) ((x)<<16) //horizontal active start point
404 //LCDC_DSP_VTOTAL_VS_END
405 #define v_VSYNC(x) ((x)<<0)
406 #define v_VERPRD(x) ((x)<<16)
408 //LCDC_DSP_VACT_ST_END
409 #define v_VAEP(x) ((x)<<0)
410 #define v_VASP(x) ((x)<<16)
413 #define v_ACT_WIDTH(x) ((x)<<0)
414 #define v_ACT_HEIGHT(x) ((x)<<16)
417 #define v_DSP_WIDTH(x) ((x)<<0)
418 #define v_DSP_HEIGHT(x) ((x)<<16)
420 //LCDC_WIN0_DSP_ST //x,y start point of the panel scanning
421 #define v_DSP_STX(x) (x<<0)
422 #define v_DSP_STY(x) (x<<16)
425 /********************************************************************
427 ********************************************************************/
428 /* LCDCµÄ¼Ä´æÆ÷½á¹¹ */
430 typedef volatile struct tagLCDC_REG
432 /* offset 0x00~0xc0 */
433 unsigned int SYS_CFG; //0x00 SYSTEM configure register
434 unsigned int SWAP_CTRL; //0x04 Data SWAP control
435 unsigned int MCU_CTRL; //0x08 MCU TIMING control register
436 unsigned int BLEND_CTRL; //0x0c Blending control register
437 unsigned int WIN0_COLOR_KEY_CTRL; //0x10 Win0 blending control register
438 unsigned int WIN1_COLOR_KEY_CTRL; //0x14 Win1 blending control register
439 unsigned int WIN2_VIR; //0x18 WIN2 virtual display width
440 unsigned int DSP_CTRL0; //0x1c Display control register0
441 unsigned int DSP_CTRL1; //0x20 Display control register1
442 unsigned int INT_STATUS; //0x24 Interrupt status register
443 unsigned int WIN0_VIR; //0x28 WIN0 virtual display width/height
444 unsigned int WIN0_YRGB_MST; //0x2c Win0 active YRGB memory start address
445 unsigned int WIN0_CBR_MST; //0x30 Win0 active Cbr memory start address
446 unsigned int WIN0_ACT_INFO; //0x34 Win0 active window width/height
447 unsigned int WIN0_DSP_ST; //0x38 Win0 display start point on panel
448 unsigned int WIN0_DSP_INFO; //0x3c Win0 display width/height on panel
449 unsigned int WIN1_VIR; //0x40 Win1 virtual display width/height
450 unsigned int WIN1_YRGB_MST; //0x44 Win1 active memory start address
451 unsigned int WIN1_DSP_INFO; //0x48 Win1 display width/height on panel
452 unsigned int WIN1_DSP_ST; //0x4c Win1 display start point on panel
453 unsigned int WIN2_MST; //0X50 Win2 memory start address
454 unsigned int WIN2_DSP_INFO; //0x54 Win1 display width/height on panel
455 unsigned int WIN2_DSP_ST; //0x58 Win1 display start point on panel
456 unsigned int HWC_MST; //0x5C HWC memory start address
457 unsigned int HWC_DSP_ST; //0x60 HWC display start point on panel
458 unsigned int HWC_COLOR_LUT0; //0x64 Hardware cursor color 2¡¯b01 look up table 0
459 unsigned int HWC_COLOR_LUT1; //0x68 Hardware cursor color 2¡¯b10 look up table 1
460 unsigned int HWC_COLOR_LUT2; //0x6c Hardware cursor color 2¡¯b11 look up table 2
461 unsigned int DSP_HTOTAL_HS_END; //0x70 Panel scanning horizontal width and hsync pulse end point
462 unsigned int DSP_HACT_ST_END; //0x74 Panel active horizontal scanning start/end point
463 unsigned int DSP_VTOTAL_VS_END; //0x78 Panel scanning vertical height and vsync pulse end point
464 unsigned int DSP_VACT_ST_END; //0x7c Panel active vertical scanning start/end point
465 unsigned int DSP_VS_ST_END_F1; //0x80 Vertical scanning start point and vsync pulse end point of even filed in interlace mode
466 unsigned int DSP_VACT_ST_END_F1; //0x84 Vertical scanning active start/end point of even filed in interlace mode
467 unsigned int WIN0_SCL_FACTOR_YRGB; //0x88 Win0 YRGB scaling down factor setting
468 unsigned int WIN0_SCL_FACTOR_CBR; //0x8c Win0 YRGB scaling up factor setting
469 unsigned int WIN0_SCL_OFFSET; //0x90 Win0 Cbr scaling start point offset
470 unsigned int FIFO_WATER_MARK; //0x94 Fifo water mark
471 unsigned int AXI_MS_ID; //0x98 Axi master ID
472 unsigned int reserved0; //0x9c
473 unsigned int REG_CFG_DONE; //0xa0 REGISTER CONFIG FINISH
474 unsigned int reserved1[(0x100-0xa4)/4];
475 unsigned int MCU_BYPASS_WPORT; //0x100 MCU BYPASS MODE, DATA Write Only Port
476 unsigned int reserved2[(0x200-0x104)/4];
477 unsigned int MCU_BYPASS_RPORT; //0x200 MCU BYPASS MODE, DATA Read Only Port
478 } LCDC_REG, *pLCDC_REG;
480 #define Win2_LUT_ADDR 0x400
481 #define DSP_LUT_ADDR 0x800
486 #define ROTATE_180 180
487 #define ROTATE_270 270
488 #define X_MIRROR (1<<10)
489 #define Y_MIRROR (1<<11)
494 #define CalScale(x, y) (((u32)x*0x1000)/y)
495 struct rk3066b_lcdc_device{
497 struct rk_lcdc_device_driver driver;
500 LCDC_REG *preg; // LCDC reg base address and backup reg
503 void __iomem *reg_vir_base; // virtual basic address of lcdc register
504 u32 reg_phy_base; // physical basic address of lcdc register
505 u32 len; // physical map length of lcdc register
506 spinlock_t reg_lock; //one time only one process allowed to config the register
507 int __iomem *dsp_lut_addr_base;
508 bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed
509 u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc
513 struct clk *pd; //lcdc power domain
514 struct clk *hclk; //lcdc AHP clk
515 struct clk *dclk; //lcdc dclk
516 struct clk *aclk; //lcdc share memory frequency
517 struct clk *aclk_parent; //lcdc aclk divider frequency source
518 struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable.
519 struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable.
520 struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable.
521 struct clk *pd_display; // display power domain
527 struct rk3066b_lcdc_device lcdc0;
528 struct rk3066b_lcdc_device lcdc1;
534 volatile u32 y_offset;
535 volatile u32 c_offset;
543 u32 xpos; //size in panel
545 u32 xsize; //start point in panel
547 enum data_format format;
549 wait_queue_head_t wait;
550 struct win_set mirror;
551 struct win_set displ;