1 #include <linux/delay.h>
2 #include <linux/interrupt.h>
3 #include <linux/rockchip/grf.h>
4 #include <linux/rockchip/iomap.h>
5 #include "rockchip_hdmiv2.h"
6 #include "rockchip_hdmiv2_hw.h"
8 static const struct phy_mpll_config_tab PHY_MPLL_TABLE[] = {
9 /*tmdsclk = (pixclk / ref_cntrl ) * (fbdiv2 * fbdiv1) / nctrl / tmdsmhl
10 opmode: 0:HDMI1.4 1:HDMI2.0
12 /* |pixclock| tmdsclock|pixrepet|colordepth|prepdiv|tmdsmhl|opmode|
13 fbdiv2|fbdiv1|ref_cntrl|nctrl|propctrl|intctrl|gmpctrl| */
14 {27000000, 27000000, 0, 8, 0, 0, 0,
16 {27000000, 33750000, 0, 10, 1, 0, 0,
18 {27000000, 40500000, 0, 12, 2, 0, 0,
20 {27000000, 54000000, 0, 16, 3, 0, 0,
22 /* {74250000, 74250000, 0, 8, 0, 0, 0,
23 1, 3, 0, 2, 5, 0, 1}, */
24 {74250000, 74250000, 0, 8, 0, 0, 0,
26 {74250000, 92812500, 0, 10, 1, 0, 0,
28 {74250000, 111375000, 0, 12, 2, 0, 0,
30 {74250000, 148500000, 0, 16, 3, 0, 0,
32 {148500000, 74250000, 0, 8, 0, 0, 0,
34 {148500000, 148500000, 0, 8, 0, 0, 0,
36 {148500000, 185625000, 0, 10, 1, 0, 0,
38 {148500000, 222750000, 0, 12, 2, 0, 0,
40 {148500000, 297000000, 0, 16, 3, 0, 0,
42 {297000000, 148500000, 0, 8, 0, 0, 0,
44 {297000000, 297000000, 0, 8, 0, 0, 0,
46 {297000000, 371250000, 0, 10, 1, 3, 1,
48 {297000000, 445500000, 0, 12, 2, 3, 1,
50 {297000000, 594000000, 0, 16, 3, 3, 1,
52 /* {594000000, 297000000, 0, 8, 0, 0, 0,
53 1, 3, 3, 1, 0, 0, 3},*/
54 {594000000, 297000000, 0, 8, 0, 0, 0,
56 {594000000, 371250000, 0, 10, 1, 3, 1,
58 {594000000, 445500000, 0, 12, 2, 3, 1,
60 {594000000, 594000000, 0, 16, 3, 3, 1,
62 {594000000, 594000000, 0, 8, 0, 3, 1,
65 /* ddc i2c master reset */
66 static void rockchip_hdmiv2_i2cm_reset(struct hdmi_dev *hdmi_dev)
68 hdmi_msk_reg(hdmi_dev, I2CM_SOFTRSTZ,
69 m_I2CM_SOFTRST, v_I2CM_SOFTRST(0));
70 usleep_range(90, 100);
73 /*set read/write offset,set read/write mode*/
74 static void rockchip_hdmiv2_i2cm_write_request(struct hdmi_dev *hdmi_dev,
77 hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
78 hdmi_writel(hdmi_dev, I2CM_DATAO, data);
79 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_WR, v_I2CM_WR(1));
82 static void rockchip_hdmiv2_i2cm_read_request(struct hdmi_dev *hdmi_dev,
85 hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
86 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_RD, v_I2CM_RD(1));
89 static void rockchip_hdmiv2_i2cm_write_data(struct hdmi_dev *hdmi_dev,
96 while (trytime-- > 0) {
97 rockchip_hdmiv2_i2cm_write_request(hdmi_dev, offset, data);
99 usleep_range(900, 1000);
100 interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
102 hdmi_writel(hdmi_dev,
103 IH_I2CM_STAT0, interrupt);
105 if (interrupt & (m_SCDC_READREQ |
106 m_I2CM_DONE | m_I2CM_ERROR))
110 if (interrupt & m_I2CM_DONE) {
111 dev_dbg(hdmi_dev->hdmi->dev,
112 "[%s] write offset %02x data %02x success\n",
113 __func__, offset, data);
115 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
116 dev_err(hdmi_dev->hdmi->dev,
117 "[%s] write data error\n", __func__);
118 rockchip_hdmiv2_i2cm_reset(hdmi_dev);
123 static int rockchip_hdmiv2_i2cm_read_data(struct hdmi_dev *hdmi_dev, u8 offset)
129 while (trytime-- > 0) {
130 rockchip_hdmiv2_i2cm_read_request(hdmi_dev, offset);
132 usleep_range(900, 1000);
133 interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
135 hdmi_writel(hdmi_dev, IH_I2CM_STAT0, interrupt);
137 if (interrupt & (m_SCDC_READREQ |
138 m_I2CM_DONE | m_I2CM_ERROR))
142 if (interrupt & m_I2CM_DONE) {
143 val = hdmi_readl(hdmi_dev, I2CM_DATAI);
145 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
146 pr_err("[%s] read data error\n", __func__);
147 rockchip_hdmiv2_i2cm_reset(hdmi_dev);
153 static void rockchip_hdmiv2_i2cm_mask_int(struct hdmi_dev *hdmi_dev, int mask)
156 hdmi_msk_reg(hdmi_dev, I2CM_INT,
157 m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(0));
158 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
159 m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
160 v_I2CM_NACK_MASK(0) | v_I2CM_ARB_MASK(0));
162 hdmi_msk_reg(hdmi_dev, I2CM_INT,
163 m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(1));
164 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
165 m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
166 v_I2CM_NACK_MASK(1) | v_I2CM_ARB_MASK(1));
170 #define I2C_DIV_FACTOR 100000
171 static u16 i2c_count(u16 sfrclock, u16 sclmintime)
173 unsigned long tmp_scl_period = 0;
175 if (((sfrclock * sclmintime) % I2C_DIV_FACTOR) != 0)
176 tmp_scl_period = (unsigned long)((sfrclock * sclmintime) +
177 (I2C_DIV_FACTOR - ((sfrclock * sclmintime) %
178 I2C_DIV_FACTOR))) / I2C_DIV_FACTOR;
180 tmp_scl_period = (unsigned long)(sfrclock * sclmintime) /
183 return (u16)(tmp_scl_period);
186 #define EDID_I2C_MIN_SS_SCL_HIGH_TIME 50000
187 #define EDID_I2C_MIN_SS_SCL_LOW_TIME 50000
189 static void rockchip_hdmiv2_i2cm_clk_init(struct hdmi_dev *hdmi_dev)
191 /* Set DDC I2C CLK which devided from DDC_CLK. */
192 hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_0_ADDR,
193 i2c_count(24000, EDID_I2C_MIN_SS_SCL_HIGH_TIME));
194 hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_0_ADDR,
195 i2c_count(24000, EDID_I2C_MIN_SS_SCL_LOW_TIME));
196 hdmi_msk_reg(hdmi_dev, I2CM_DIV, m_I2CM_FAST_STD_MODE,
197 v_I2CM_FAST_STD_MODE(STANDARD_MODE));
200 static int rockchip_hdmiv2_scdc_get_sink_version(struct hdmi_dev *hdmi_dev)
202 return rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SINK_VER);
205 static void rockchip_hdmiv2_scdc_set_source_version(struct hdmi_dev *hdmi_dev,
208 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, version, SCDC_SOURCE_VER);
212 static void rockchip_hdmiv2_scdc_read_request(struct hdmi_dev *hdmi_dev,
215 hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
216 m_I2CM_READ_REQ_EN, v_I2CM_READ_REQ_EN(enable));
217 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, enable, SCDC_CONFIG_0);
221 static void rockchip_hdmiv2_scdc_update_read(struct hdmi_dev *hdmi_dev)
223 hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
224 m_I2CM_READ_UPDATE, v_I2CM_READ_UPDATE(1));
228 static int rockchip_hdmiv2_scdc_get_scambling_status(struct hdmi_dev *hdmi_dev)
232 val = rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SCRAMBLER_STAT);
236 static void rockchip_hdmiv2_scdc_enable_polling(struct hdmi_dev *hdmi_dev,
239 rockchip_hdmiv2_scdc_read_request(hdmi_dev, enable);
240 hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
241 m_I2CM_UPRD_VSYNC_EN, v_I2CM_UPRD_VSYNC_EN(enable));
244 static int rockchip_hdmiv2_scdc_get_status_reg0(struct hdmi_dev *hdmi_dev)
246 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
247 rockchip_hdmiv2_scdc_update_read(hdmi_dev);
248 return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE0);
251 static int rockchip_hdmiv2_scdc_get_status_reg1(struct hdmi_dev *hdmi_dev)
253 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
254 rockchip_hdmiv2_scdc_update_read(hdmi_dev);
255 return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE1);
259 static void rockchip_hdmiv2_scdc_init(struct hdmi_dev *hdmi_dev)
261 rockchip_hdmiv2_i2cm_reset(hdmi_dev);
262 rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
263 rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
264 /* set scdc i2c addr */
265 hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_SCDC_ADDR);
266 rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);/*enable interrupt*/
270 static int rockchip_hdmiv2_scrambling_enable(struct hdmi_dev *hdmi_dev,
273 HDMIDBG("%s enable %d\n", __func__, enable);
275 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
276 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 1, SCDC_TMDS_CONFIG);
277 /* TMDS software reset request */
278 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
279 m_TMDS_SWRST, v_TMDS_SWRST(0));
280 /* Enable/Disable Scrambling */
281 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
282 m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(1));
284 /* Enable/Disable Scrambling */
285 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
286 m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
287 /* TMDS software reset request */
288 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
289 m_TMDS_SWRST, v_TMDS_SWRST(0));
290 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
291 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 0, SCDC_TMDS_CONFIG);
298 static const struct phy_mpll_config_tab *get_phy_mpll_tab(
299 unsigned int pixclock, unsigned int tmdsclk,
300 char pixrepet, char colordepth)
306 HDMIDBG("%s pixClock %u pixRepet %d colorDepth %d\n",
307 __func__, pixclock, pixrepet, colordepth);
308 for (i = 0; i < ARRAY_SIZE(PHY_MPLL_TABLE); i++) {
309 if ((PHY_MPLL_TABLE[i].pix_clock == pixclock) &&
310 (PHY_MPLL_TABLE[i].tmdsclock == tmdsclk) &&
311 (PHY_MPLL_TABLE[i].pix_repet == pixrepet) &&
312 (PHY_MPLL_TABLE[i].color_depth == colordepth))
313 return &PHY_MPLL_TABLE[i];
318 static void rockchip_hdmiv2_powerdown(struct hdmi_dev *hdmi_dev)
320 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
321 m_PDDQ_SIG | m_TXPWRON_SIG | m_ENHPD_RXSENSE_SIG,
322 v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) |
323 v_ENHPD_RXSENSE_SIG(1));
324 hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
327 int rockchip_hdmiv2_write_phy(struct hdmi_dev *hdmi_dev,
328 int reg_addr, int val)
330 int trytime = 2, i = 0, op_status = 0;
333 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
334 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_1, (val >> 8) & 0xff);
335 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_0, val & 0xff);
336 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_WRITE);
340 usleep_range(900, 1000);
341 op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
343 hdmi_writel(hdmi_dev,
347 if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
351 if (op_status & m_I2CMPHY_DONE)
354 dev_err(hdmi_dev->hdmi->dev,
355 "[%s] operation error,trytime=%d\n",
363 int rockchip_hdmiv2_read_phy(struct hdmi_dev *hdmi_dev,
366 int trytime = 2, i = 0, op_status = 0;
370 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
371 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_1, 0x00);
372 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_0, 0x00);
373 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_READ);
377 usleep_range(900, 1000);
378 op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
380 hdmi_writel(hdmi_dev, IH_I2CMPHY_STAT0,
383 if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
387 if (op_status & m_I2CMPHY_DONE) {
388 val = hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_1);
389 val = (val & 0xff) << 8;
390 val += (hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_0) & 0xff);
391 pr_debug("phy_reg0x%02x: 0x%04x",
395 pr_err("[%s] operation error,trytime=%d\n",
404 static int rockchip_hdmiv2_config_phy(struct hdmi_dev *hdmi_dev)
407 const struct phy_mpll_config_tab *phy_mpll = NULL;
409 hdmi_msk_reg(hdmi_dev, PHY_I2CM_DIV,
410 m_PHY_I2CM_FAST_STD, v_PHY_I2CM_FAST_STD(0));
412 /* hdmi_writel(hdmi_dev, PHY_CONF0, 0x1e); */
413 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
414 m_PDDQ_SIG | m_TXPWRON_SIG | m_SVSRET_SIG,
415 v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) | v_SVSRET_SIG(1));
417 if (hdmi_dev->tmdsclk_ratio_change &&
418 hdmi_dev->hdmi->edid.scdc_present == 1) {
419 mutex_lock(&hdmi_dev->ddc_lock);
420 rockchip_hdmiv2_scdc_init(hdmi_dev);
421 stat = rockchip_hdmiv2_i2cm_read_data(hdmi_dev,
423 if (hdmi_dev->tmdsclk > 340000000)
427 rockchip_hdmiv2_i2cm_write_data(hdmi_dev,
428 stat, SCDC_TMDS_CONFIG);
429 mutex_unlock(&hdmi_dev->ddc_lock);
432 hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(1));
433 usleep_range(1000, 2000);
434 hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(0));
436 /* Set slave address as PHY GEN2 address */
437 hdmi_writel(hdmi_dev, PHY_I2CM_SLAVE, PHY_GEN2_ADDR);
439 /* config the required PHY I2C register */
440 phy_mpll = get_phy_mpll_tab(hdmi_dev->pixelclk,
442 hdmi_dev->pixelrepeat - 1,
443 hdmi_dev->colordepth);
445 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_OPMODE_PLLCFG,
446 v_PREP_DIV(phy_mpll->prep_div) |
448 phy_mpll->tmdsmhl_cntrl) |
449 v_OPMODE(phy_mpll->opmode) |
451 phy_mpll->fbdiv2_cntrl) |
453 phy_mpll->fbdiv1_cntrl) |
454 v_REF_CNTRL(phy_mpll->ref_cntrl) |
455 v_MPLL_N_CNTRL(phy_mpll->n_cntrl));
456 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLCURRCTRL,
458 phy_mpll->prop_cntrl) |
460 phy_mpll->int_cntrl));
461 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLGMPCTRL,
463 phy_mpll->gmp_cntrl));
466 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL,
467 v_OVERRIDE(1) | v_SLOPEBOOST(0) |
468 v_TX_SYMON(1) | v_TX_TRAON(0) |
469 v_TX_TRBON(0) | v_CLK_SYMON(1));
470 if (hdmi_dev->tmdsclk > 340000000) {
471 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
472 v_TX_TERM(R50_OHMS));
473 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
477 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
478 v_TX_TERM(R100_OHMS));
479 if (hdmi_dev->tmdsclk > 165000000)
480 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
484 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
488 /* rockchip_hdmiv2_write_phy(hdmi_dev, 0x05, 0x8000); */
489 if (hdmi_dev->tmdsclk_ratio_change)
492 hdmi_writel(hdmi_dev, PHY_CONF0, 0x2e);
494 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
495 m_PDDQ_SIG | m_TXPWRON_SIG | m_ENHPD_RXSENSE_SIG,
496 v_PDDQ_SIG(0) | v_TXPWRON_SIG(1) |
497 v_ENHPD_RXSENSE_SIG(1));
499 /* check if the PHY PLL is locked */
500 #define PHY_TIMEOUT 10000
501 while (i++ < PHY_TIMEOUT) {
503 stat = hdmi_readl(hdmi_dev, PHY_STAT0);
504 if (stat & m_PHY_LOCK)
506 usleep_range(1000, 2000);
509 if ((stat & m_PHY_LOCK) == 0) {
510 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
511 dev_err(hdmi_dev->hdmi->dev,
512 "PHY PLL not locked: PCLK_ON=%d,TMDSCLK_ON=%d\n",
513 (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
520 static int rockchip_hdmiv2_video_framecomposer(struct hdmi *hdmi_drv,
521 struct hdmi_video *vpara)
523 struct hdmi_dev *hdmi_dev = hdmi_drv->property->priv;
524 int value, vsync_pol, hsync_pol, de_pol;
525 struct hdmi_video_timing *timing = NULL;
526 struct fb_videomode *mode = NULL;
527 u32 sink_version, tmdsclk;
529 vsync_pol = hdmi_drv->lcdc->cur_screen->pin_vsync;
530 hsync_pol = hdmi_drv->lcdc->cur_screen->pin_hsync;
531 de_pol = (hdmi_drv->lcdc->cur_screen->pin_den == 0) ? 1 : 0;
533 hdmi_msk_reg(hdmi_dev, A_VIDPOLCFG,
534 m_DATAEN_POL | m_VSYNC_POL | m_HSYNC_POL,
535 v_DATAEN_POL(de_pol) |
536 v_VSYNC_POL(vsync_pol) |
537 v_HSYNC_POL(hsync_pol));
539 timing = (struct hdmi_video_timing *)hdmi_vic2timing(vpara->vic);
540 if (timing == NULL) {
541 dev_err(hdmi_drv->dev,
542 "[%s] not found vic %d\n", __func__, vpara->vic);
545 mode = &(timing->mode);
546 if (vpara->color_input == HDMI_COLOR_YCBCR420)
547 tmdsclk = mode->pixclock / 2;
549 tmdsclk = mode->pixclock;
550 switch (vpara->color_output_depth) {
552 tmdsclk += tmdsclk / 4;
555 tmdsclk += tmdsclk / 2;
565 if (tmdsclk > 594000000) {
566 vpara->color_output_depth = 8;
567 tmdsclk = mode->pixclock;
569 pr_info("pixel clk is %u tmds clk is %u\n", mode->pixclock, tmdsclk);
570 if ((tmdsclk > 340000000 && hdmi_dev->tmdsclk < 340000000) ||
571 (tmdsclk < 340000000 && hdmi_dev->tmdsclk > 340000000))
572 hdmi_dev->tmdsclk_ratio_change = true;
574 hdmi_dev->tmdsclk_ratio_change = false;
576 hdmi_dev->tmdsclk = tmdsclk;
577 hdmi_dev->pixelclk = mode->pixclock;
578 hdmi_dev->pixelrepeat = timing->pixelrepeat;
579 hdmi_dev->colordepth = vpara->color_output_depth;
581 /* Video Register has already been set in uboot,
582 so we no need to set again */
587 /* Start/stop HDCP keepout window generation */
588 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
589 m_FC_HDCP_KEEPOUT, v_FC_HDCP_KEEPOUT(1));
590 if (hdmi_drv->edid.scdc_present == 1) {
591 if (tmdsclk > 340000000) {/* used for HDMI 2.0 TX */
592 mutex_lock(&hdmi_dev->ddc_lock);
593 rockchip_hdmiv2_scdc_init(hdmi_dev);
595 rockchip_hdmiv2_scdc_get_sink_version(hdmi_dev);
596 pr_info("sink scdc version is %d\n", sink_version);
597 sink_version = hdmi_drv->edid.hf_vsdb_version;
598 rockchip_hdmiv2_scdc_set_source_version(hdmi_dev,
600 if (hdmi_drv->edid.rr_capable == 1)
601 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
602 rockchip_hdmiv2_scrambling_enable(hdmi_dev, 1);
603 mutex_unlock(&hdmi_dev->ddc_lock);
605 mutex_lock(&hdmi_dev->ddc_lock);
606 rockchip_hdmiv2_scdc_init(hdmi_dev);
607 rockchip_hdmiv2_scrambling_enable(hdmi_dev, 0);
608 mutex_unlock(&hdmi_dev->ddc_lock);
612 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
613 m_FC_VSYNC_POL | m_FC_HSYNC_POL | m_FC_DE_POL |
614 m_FC_HDMI_DVI | m_FC_INTERLACE_MODE,
615 v_FC_VSYNC_POL(vsync_pol) | v_FC_HSYNC_POL(hsync_pol) |
616 v_FC_DE_POL(de_pol) | v_FC_HDMI_DVI(vpara->sink_hdmi) |
617 v_FC_INTERLACE_MODE(mode->vmode));
618 if (mode->vmode == FB_VMODE_INTERLACED)
619 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
620 m_FC_VBLANK, v_FC_VBLANK(1));
622 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
623 m_FC_VBLANK, v_FC_VBLANK(0));
626 if (vpara->color_input == HDMI_COLOR_YCBCR420)
628 hdmi_writel(hdmi_dev, FC_INHACTIV1, v_FC_HACTIVE1(value >> 8));
629 hdmi_writel(hdmi_dev, FC_INHACTIV0, (value & 0xff));
632 hdmi_writel(hdmi_dev, FC_INVACTIV1, v_FC_VACTIVE1(value >> 8));
633 hdmi_writel(hdmi_dev, FC_INVACTIV0, (value & 0xff));
635 value = mode->hsync_len + mode->left_margin + mode->right_margin;
636 if (vpara->color_input == HDMI_COLOR_YCBCR420)
638 hdmi_writel(hdmi_dev, FC_INHBLANK1, v_FC_HBLANK1(value >> 8));
639 hdmi_writel(hdmi_dev, FC_INHBLANK0, (value & 0xff));
641 value = mode->vsync_len + mode->upper_margin + mode->lower_margin;
642 hdmi_writel(hdmi_dev, FC_INVBLANK, (value & 0xff));
644 value = mode->right_margin;
645 if (vpara->color_input == HDMI_COLOR_YCBCR420)
647 hdmi_writel(hdmi_dev, FC_HSYNCINDELAY1, v_FC_HSYNCINDEAY1(value >> 8));
648 hdmi_writel(hdmi_dev, FC_HSYNCINDELAY0, (value & 0xff));
650 value = mode->lower_margin;
651 hdmi_writel(hdmi_dev, FC_VSYNCINDELAY, (value & 0xff));
653 value = mode->hsync_len;
654 if (vpara->color_input == HDMI_COLOR_YCBCR420)
656 hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH1, v_FC_HSYNCWIDTH1(value >> 8));
657 hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH0, (value & 0xff));
659 value = mode->vsync_len;
660 hdmi_writel(hdmi_dev, FC_VSYNCINWIDTH, (value & 0xff));
662 /*Set the control period minimum duration
663 (min. of 12 pixel clock cycles, refer to HDMI 1.4b specification)*/
664 hdmi_writel(hdmi_dev, FC_CTRLDUR, 12);
665 hdmi_writel(hdmi_dev, FC_EXCTRLDUR, 32);
667 /* spacing < 256^2 * config / tmdsClock, spacing <= 50ms
668 * worst case: tmdsClock == 25MHz => config <= 19
670 hdmi_writel(hdmi_dev, FC_EXCTRLSPAC,
671 (hdmi_dev->tmdsclk/1000) * 50 / (256 * 512));
674 /*Set PreambleFilter*/
675 for (i = 0; i < 3; i++) {
676 value = (i + 1) * 11;
677 if (i == 0) /*channel 0*/
678 hdmi_writel(hdmi_dev, FC_CH0PREAM, value);
679 else if (i == 1) /*channel 1*/
680 hdmi_writel(hdmi_dev, FC_CH1PREAM, value & 0x3f);
681 else if (i == 2) /*channel 2*/
682 hdmi_writel(hdmi_dev, FC_CH2PREAM, value & 0x3f);
686 hdmi_writel(hdmi_dev, FC_PRCONF, v_FC_PR_FACTOR(timing->pixelrepeat));
691 static int rockchip_hdmiv2_video_packetizer(struct hdmi_dev *hdmi_dev,
692 struct hdmi_video *vpara)
694 unsigned char color_depth = 0;
695 unsigned char output_select = 0;
696 unsigned char remap_size = 0;
698 if (vpara->color_output == HDMI_COLOR_YCBCR422) {
699 switch (vpara->color_output_depth) {
701 remap_size = YCC422_16BIT;
704 remap_size = YCC422_20BIT;
707 remap_size = YCC422_24BIT;
710 remap_size = YCC422_16BIT;
714 output_select = OUT_FROM_YCC422_REMAP;
715 /*Config remap size for the different color Depth*/
716 hdmi_msk_reg(hdmi_dev, VP_REMAP,
717 m_YCC422_SIZE, v_YCC422_SIZE(remap_size));
719 switch (vpara->color_output_depth) {
721 color_depth = COLOR_DEPTH_30BIT;
722 output_select = OUT_FROM_PIXEL_PACKING;
725 color_depth = COLOR_DEPTH_36BIT;
726 output_select = OUT_FROM_PIXEL_PACKING;
729 color_depth = COLOR_DEPTH_48BIT;
730 output_select = OUT_FROM_PIXEL_PACKING;
734 color_depth = COLOR_DEPTH_24BIT_DEFAULT;
735 output_select = OUT_FROM_8BIT_BYPASS;
739 /*Config Color Depth*/
740 hdmi_msk_reg(hdmi_dev, VP_PR_CD,
741 m_COLOR_DEPTH, v_COLOR_DEPTH(color_depth));
744 /*Config pixel repettion*/
745 hdmi_msk_reg(hdmi_dev, VP_PR_CD, m_DESIRED_PR_FACTOR,
746 v_DESIRED_PR_FACTOR(hdmi_dev->pixelrepeat - 1));
747 if (hdmi_dev->pixelrepeat > 1)
748 hdmi_msk_reg(hdmi_dev, VP_CONF,
749 m_PIXEL_REPET_EN | m_BYPASS_SEL,
750 v_PIXEL_REPET_EN(1) | v_BYPASS_SEL(0));
752 hdmi_msk_reg(hdmi_dev, VP_CONF,
753 m_PIXEL_REPET_EN | m_BYPASS_SEL,
754 v_PIXEL_REPET_EN(0) | v_BYPASS_SEL(1));
756 /*config output select*/
757 if (output_select == OUT_FROM_PIXEL_PACKING) { /* pixel packing */
758 hdmi_msk_reg(hdmi_dev, VP_CONF,
759 m_BYPASS_EN | m_PIXEL_PACK_EN |
760 m_YCC422_EN | m_OUTPUT_SEL,
761 v_BYPASS_EN(0) | v_PIXEL_PACK_EN(1) |
762 v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
763 } else if (output_select == OUT_FROM_YCC422_REMAP) { /* YCC422 */
764 hdmi_msk_reg(hdmi_dev, VP_CONF,
765 m_BYPASS_EN | m_PIXEL_PACK_EN |
766 m_YCC422_EN | m_OUTPUT_SEL,
767 v_BYPASS_EN(0) | v_PIXEL_PACK_EN(0) |
768 v_YCC422_EN(1) | v_OUTPUT_SEL(output_select));
769 } else if (output_select == OUT_FROM_8BIT_BYPASS ||
770 output_select == 3) { /* bypass */
771 hdmi_msk_reg(hdmi_dev, VP_CONF,
772 m_BYPASS_EN | m_PIXEL_PACK_EN |
773 m_YCC422_EN | m_OUTPUT_SEL,
774 v_BYPASS_EN(1) | v_PIXEL_PACK_EN(0) |
775 v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
778 #if defined(HDMI_VIDEO_STUFFING)
779 /* YCC422 and pixel packing stuffing*/
780 hdmi_msk_reg(hdmi_dev, VP_STUFF, m_PR_STUFFING, v_PR_STUFFING(1));
781 hdmi_msk_reg(hdmi_dev, VP_STUFF,
782 m_YCC422_STUFFING | m_PP_STUFFING,
783 v_YCC422_STUFFING(1) | v_PP_STUFFING(1));
788 static int rockchip_hdmiv2_video_sampler(struct hdmi_dev *hdmi_dev,
789 struct hdmi_video *vpara)
793 if (vpara->color_input == HDMI_COLOR_YCBCR422) {
794 /* YCC422 mapping is discontinued - only map 1 is supported */
795 switch (vpara->color_output_depth) {
797 map_code = VIDEO_YCBCR422_8BIT;
800 map_code = VIDEO_YCBCR422_10BIT;
803 map_code = VIDEO_YCBCR422_12BIT;
806 map_code = VIDEO_YCBCR422_8BIT;
809 } else if (vpara->color_input == HDMI_COLOR_YCBCR420 ||
810 vpara->color_input == HDMI_COLOR_YCBCR444) {
811 switch (vpara->color_output_depth) {
813 map_code = VIDEO_YCBCR444_10BIT;
816 map_code = VIDEO_YCBCR444_12BIT;
819 map_code = VIDEO_YCBCR444_16BIT;
823 map_code = VIDEO_YCBCR444_8BIT;
827 switch (vpara->color_output_depth) {
829 map_code = VIDEO_RGB444_10BIT;
832 map_code = VIDEO_RGB444_12BIT;
835 map_code = VIDEO_RGB444_16BIT;
839 map_code = VIDEO_RGB444_8BIT;
842 map_code += (vpara->color_input == HDMI_COLOR_YCBCR444) ?
846 /* Set Data enable signal from external
847 and set video sample input mapping */
848 hdmi_msk_reg(hdmi_dev, TX_INVID0,
849 m_INTERNAL_DE_GEN | m_VIDEO_MAPPING,
850 v_INTERNAL_DE_GEN(0) | v_VIDEO_MAPPING(map_code));
852 #if defined(HDMI_VIDEO_STUFFING)
853 hdmi_writel(hdmi_dev, TX_GYDATA0, 0x00);
854 hdmi_writel(hdmi_dev, TX_GYDATA1, 0x00);
855 hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
856 m_GYDATA_STUFF, v_GYDATA_STUFF(1));
857 hdmi_writel(hdmi_dev, TX_RCRDATA0, 0x00);
858 hdmi_writel(hdmi_dev, TX_RCRDATA1, 0x00);
859 hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
860 m_RCRDATA_STUFF, v_RCRDATA_STUFF(1));
861 hdmi_writel(hdmi_dev, TX_BCBDATA0, 0x00);
862 hdmi_writel(hdmi_dev, TX_BCBDATA1, 0x00);
863 hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
864 m_BCBDATA_STUFF, v_BCBDATA_STUFF(1));
869 static const char coeff_csc[][24] = {
873 C1 | C2 | C3 | C4 | */
874 { /* CSC_RGB_0_255_TO_RGB_16_235_8BIT */
875 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, /*G*/
876 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x00, 0x40, /*R*/
877 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x00, 0x40, /*B*/
879 { /* CSC_RGB_0_255_TO_RGB_16_235_10BIT */
880 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, /*G*/
881 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x01, 0x00, /*R*/
882 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x01, 0x00, /*B*/
884 { /* CSC_RGB_0_255_TO_ITU601_16_235_8BIT */
885 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x00, 0x40, /*Y*/
886 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x02, 0x00, /*Cr*/
887 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x02, 0x00, /*Cb*/
889 { /* CSC_RGB_0_255_TO_ITU601_16_235_10BIT */
890 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x01, 0x00, /*Y*/
891 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x08, 0x00, /*Cr*/
892 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x08, 0x00, /*Cb*/
894 { /* CSC_RGB_0_255_TO_ITU709_16_235_8BIT */
895 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x00, 0x40, /*Y*/
896 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x02, 0x00, /*Cr*/
897 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x02, 0x00, /*Cb*/
899 { /* CSC_RGB_0_255_TO_ITU709_16_235_10BIT */
900 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x01, 0x00, /*Y*/
901 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x08, 0x00, /*Cr*/
902 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x08, 0x00, /*Cb*/
905 { /* CSC_ITU601_16_235_TO_RGB_0_255_8BIT */
906 0x20, 0x00, 0x69, 0x26, 0x74, 0xfd, 0x01, 0x0e, /*G*/
907 0x20, 0x00, 0x2c, 0xdd, 0x00, 0x00, 0x7e, 0x9a, /*R*/
908 0x20, 0x00, 0x00, 0x00, 0x38, 0xb4, 0x7e, 0x3b, /*B*/
910 { /* CSC_ITU709_16_235_TO_RGB_0_255_8BIT */
911 0x20, 0x00, 0x71, 0x06, 0x7a, 0x02, 0x00, 0xa7, /*G*/
912 0x20, 0x00, 0x32, 0x64, 0x00, 0x00, 0x7e, 0x6d, /*R*/
913 0x20, 0x00, 0x00, 0x00, 0x3b, 0x61, 0x7e, 0x25, /*B*/
917 static int rockchip_hdmiv2_video_csc(struct hdmi_dev *hdmi_dev,
918 struct hdmi_video *vpara)
920 int i, mode, interpolation, decimation, csc_scale;
921 const char *coeff = NULL;
922 unsigned char color_depth = 0;
924 if (vpara->color_input == vpara->color_output) {
925 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
926 m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(0));
930 if (vpara->color_input == HDMI_COLOR_YCBCR422 &&
931 vpara->color_output != HDMI_COLOR_YCBCR422 &&
932 vpara->color_output != HDMI_COLOR_YCBCR420) {
934 hdmi_msk_reg(hdmi_dev, CSC_CFG,
935 m_CSC_INTPMODE, v_CSC_INTPMODE(interpolation));
938 if ((vpara->color_input == HDMI_COLOR_RGB_0_255 ||
939 vpara->color_input == HDMI_COLOR_YCBCR444) &&
940 vpara->color_output == HDMI_COLOR_YCBCR422) {
942 hdmi_msk_reg(hdmi_dev, CSC_CFG,
943 m_CSC_DECIMODE, v_CSC_DECIMODE(decimation));
946 switch (vpara->vic) {
947 case HDMI_720X480I_60HZ_4_3:
948 case HDMI_720X576I_50HZ_4_3:
949 case HDMI_720X480P_60HZ_4_3:
950 case HDMI_720X576P_50HZ_4_3:
951 case HDMI_720X480I_60HZ_16_9:
952 case HDMI_720X576I_50HZ_16_9:
953 case HDMI_720X480P_60HZ_16_9:
954 case HDMI_720X576P_50HZ_16_9:
955 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
956 vpara->color_output >= HDMI_COLOR_YCBCR444) {
957 mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
959 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
960 vpara->color_output == HDMI_COLOR_RGB_0_255) {
961 mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT;
966 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
967 vpara->color_output >= HDMI_COLOR_YCBCR444) {
968 mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
970 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
971 vpara->color_output == HDMI_COLOR_RGB_0_255) {
972 mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT;
978 if ((vpara->color_input == HDMI_COLOR_RGB_0_255) &&
979 (vpara->color_output == HDMI_COLOR_RGB_16_235)) {
980 mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
984 switch (vpara->color_output_depth) {
986 color_depth = COLOR_DEPTH_30BIT;
990 color_depth = COLOR_DEPTH_36BIT;
994 color_depth = COLOR_DEPTH_48BIT;
999 color_depth = COLOR_DEPTH_24BIT;
1003 coeff = coeff_csc[mode];
1004 for (i = 0; i < 24; i++)
1005 hdmi_writel(hdmi_dev, CSC_COEF_A1_MSB + i, coeff[i]);
1007 hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1008 m_CSC_SCALE, v_CSC_SCALE(csc_scale));
1009 /*config CSC_COLOR_DEPTH*/
1010 hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1011 m_CSC_COLOR_DEPTH, v_CSC_COLOR_DEPTH(color_depth));
1014 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1015 m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(1));
1021 static int hdmi_dev_detect_hotplug(struct hdmi *hdmi)
1023 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1024 u32 value = hdmi_readl(hdmi_dev, PHY_STAT0);
1026 HDMIDBG("[%s] reg%x value %02x\n", __func__, PHY_STAT0, value);
1028 if (value & m_PHY_HPD)
1029 return HDMI_HPD_ACTIVED;
1031 return HDMI_HPD_REMOVED;
1034 static int hdmi_dev_read_edid(struct hdmi *hdmi, int block, unsigned char *buff)
1036 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1037 int i = 0, n = 0, index = 0, ret = -1, trytime = 5;
1038 int offset = (block % 2) * 0x80;
1041 HDMIDBG("[%s] block %d\n", __func__, block);
1043 rockchip_hdmiv2_i2cm_reset(hdmi_dev);
1045 /* Set DDC I2C CLK which devided from DDC_CLK to 100KHz. */
1046 rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
1048 /* Enable I2C interrupt for reading edid */
1049 rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);
1051 hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_EDID_ADDR);
1052 hdmi_writel(hdmi_dev, I2CM_SEGADDR, DDC_I2C_SEG_ADDR);
1053 hdmi_writel(hdmi_dev, I2CM_SEGPTR, block / 2);
1054 for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
1055 for (trytime = 0; trytime < 5; trytime++) {
1056 hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset + 8 * n);
1057 /* enable extend sequential read operation */
1059 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1060 m_I2CM_RD8, v_I2CM_RD8(1));
1062 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1068 usleep_range(900, 1000);
1069 interrupt = hdmi_readl(hdmi_dev,
1072 hdmi_writel(hdmi_dev,
1073 IH_I2CM_STAT0, interrupt);
1076 (m_SCDC_READREQ | m_I2CM_DONE |
1081 if (interrupt & m_I2CM_DONE) {
1082 for (index = 0; index < 8; index++)
1083 buff[8 * n + index] =
1084 hdmi_readl(hdmi_dev,
1088 if (n == HDMI_EDID_BLOCK_SIZE / 8 - 1) {
1093 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
1095 "[%s] edid read %d error\n",
1096 __func__, offset + 8 * n);
1101 "[%s] edid read error\n", __func__);
1107 /* Disable I2C interrupt */
1108 rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
1112 static void hdmi_dev_config_avi(struct hdmi_dev *hdmi_dev,
1113 struct hdmi_video *vpara)
1115 unsigned char colorimetry, ext_colorimetry, aspect_ratio, y1y0;
1116 unsigned char rgb_quan_range = AVI_QUANTIZATION_RANGE_DEFAULT;
1118 /* Set AVI infoFrame Data byte1 */
1119 if (vpara->color_output == HDMI_COLOR_YCBCR444)
1120 y1y0 = AVI_COLOR_MODE_YCBCR444;
1121 else if (vpara->color_output == HDMI_COLOR_YCBCR422)
1122 y1y0 = AVI_COLOR_MODE_YCBCR422;
1123 else if (vpara->color_output == HDMI_COLOR_YCBCR420)
1124 y1y0 = AVI_COLOR_MODE_YCBCR420;
1126 y1y0 = AVI_COLOR_MODE_RGB;
1128 hdmi_msk_reg(hdmi_dev, FC_AVICONF0,
1129 m_FC_ACTIV_FORMAT | m_FC_RGC_YCC,
1130 v_FC_RGC_YCC(y1y0) | v_FC_ACTIV_FORMAT(1));
1132 /* Set AVI infoFrame Data byte2 */
1133 switch (vpara->vic) {
1134 case HDMI_720X480I_60HZ_4_3:
1135 case HDMI_720X576I_50HZ_4_3:
1136 case HDMI_720X480P_60HZ_4_3:
1137 case HDMI_720X576P_50HZ_4_3:
1138 aspect_ratio = AVI_CODED_FRAME_ASPECT_4_3;
1139 colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1141 case HDMI_720X480I_60HZ_16_9:
1142 case HDMI_720X576I_50HZ_16_9:
1143 case HDMI_720X480P_60HZ_16_9:
1144 case HDMI_720X576P_50HZ_16_9:
1145 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1146 colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1149 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1150 colorimetry = AVI_COLORIMETRY_ITU709;
1153 if (vpara->color_output_depth > 8) {
1154 colorimetry = AVI_COLORIMETRY_EXTENDED;
1155 ext_colorimetry = 6;
1156 } else if (vpara->color_output == HDMI_COLOR_RGB_16_235 ||
1157 vpara->color_output == HDMI_COLOR_RGB_0_255) {
1158 colorimetry = AVI_COLORIMETRY_NO_DATA;
1159 ext_colorimetry = 0;
1162 hdmi_writel(hdmi_dev, FC_AVICONF1,
1163 v_FC_COLORIMETRY(colorimetry) |
1164 v_FC_PIC_ASPEC_RATIO(aspect_ratio) |
1165 v_FC_ACT_ASPEC_RATIO(ACTIVE_ASPECT_RATE_DEFAULT));
1167 /* Set AVI infoFrame Data byte3 */
1168 hdmi_msk_reg(hdmi_dev, FC_AVICONF2,
1169 m_FC_EXT_COLORIMETRY | m_FC_QUAN_RANGE,
1170 v_FC_EXT_COLORIMETRY(ext_colorimetry) |
1171 v_FC_QUAN_RANGE(rgb_quan_range));
1173 /* Set AVI infoFrame Data byte4 */
1174 if ((vpara->vic > 92 && vpara->vic < 96) || (vpara->vic == 98))
1175 hdmi_writel(hdmi_dev, FC_AVIVID, 0);
1177 hdmi_writel(hdmi_dev, FC_AVIVID, vpara->vic & 0xff);
1178 /* Set AVI infoFrame Data byte5 */
1179 hdmi_msk_reg(hdmi_dev, FC_AVICONF3, m_FC_YQ | m_FC_CN,
1180 v_FC_YQ(YQ_LIMITED_RANGE) | v_FC_CN(CN_GRAPHICS));
1183 static int hdmi_dev_config_vsi(struct hdmi *hdmi,
1184 unsigned char vic_3d, unsigned char format)
1186 int i = 0, id = 0x000c03;
1187 unsigned char data[3] = {0};
1189 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1191 HDMIDBG("[%s] vic %d format %d.\n", __func__, vic_3d, format);
1193 hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(0));
1194 hdmi_writel(hdmi_dev, FC_VSDIEEEID2, id & 0xff);
1195 hdmi_writel(hdmi_dev, FC_VSDIEEEID1, (id >> 8) & 0xff);
1196 hdmi_writel(hdmi_dev, FC_VSDIEEEID0, (id >> 16) & 0xff);
1198 data[0] = format << 5; /* PB4 --HDMI_Video_Format */
1200 case HDMI_VIDEO_FORMAT_4KX2K:
1201 data[1] = vic_3d; /* PB5--HDMI_VIC */
1204 case HDMI_VIDEO_FORMAT_3D:
1205 data[1] = vic_3d << 4; /* PB5--3D_Structure field */
1206 data[2] = 0; /* PB6--3D_Ext_Data field */
1214 for (i = 0; i < 3; i++)
1215 hdmi_writel(hdmi_dev, FC_VSDPAYLOAD0 + i, data[i]);
1216 hdmi_writel(hdmi_dev, FC_VSDSIZE, 0x6);
1217 /* if (auto_send) { */
1218 hdmi_writel(hdmi_dev, FC_DATAUTO1, 0);
1219 hdmi_writel(hdmi_dev, FC_DATAUTO2, 0x11);
1220 hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(1));
1223 hdmi_msk_reg(hdmi_dev, FC_DATMAN, m_VSD_MAN, v_VSD_MAN(1));
1229 static int hdmi_dev_config_video(struct hdmi *hdmi, struct hdmi_video *vpara)
1231 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1233 HDMIDBG("%s vic %d 3dformat %d color mode %d color depth %d\n",
1234 __func__, vpara->vic, vpara->format_3d,
1235 vpara->color_output, vpara->color_output_depth);
1237 if (hdmi_dev->soctype == HDMI_SOC_RK3288)
1238 vpara->color_input = HDMI_COLOR_RGB_0_255;
1241 /* befor configure video, we power off phy */
1242 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1243 m_PDDQ_SIG | m_TXPWRON_SIG,
1244 v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1246 /* force output blue */
1247 if (vpara->color_output == HDMI_COLOR_RGB_0_255) {
1248 hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x00); /*R*/
1249 hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x00); /*G*/
1250 hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x00); /*B*/
1251 } else if (vpara->color_output == HDMI_COLOR_RGB_16_235) {
1252 hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x10); /*R*/
1253 hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10); /*G*/
1254 hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x10); /*B*/
1256 hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x80); /*R*/
1257 hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10); /*G*/
1258 hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x80); /*B*/
1260 hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1261 m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1262 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1265 if (rockchip_hdmiv2_video_framecomposer(hdmi, vpara) < 0)
1268 if (rockchip_hdmiv2_video_packetizer(hdmi_dev, vpara) < 0)
1270 /* Color space convert */
1271 if (rockchip_hdmiv2_video_csc(hdmi_dev, vpara) < 0)
1273 if (rockchip_hdmiv2_video_sampler(hdmi_dev, vpara) < 0)
1276 if (vpara->sink_hdmi == OUTPUT_HDMI) {
1277 hdmi_dev_config_avi(hdmi_dev, vpara);
1278 if (vpara->format_3d != HDMI_3D_NONE) {
1279 hdmi_dev_config_vsi(hdmi,
1281 HDMI_VIDEO_FORMAT_3D);
1282 } else if ((vpara->vic > 92 && vpara->vic < 96) ||
1283 (vpara->vic == 98)) {
1284 vpara->vic = (vpara->vic == 98) ?
1285 4 : (96 - vpara->vic);
1286 hdmi_dev_config_vsi(hdmi,
1288 HDMI_VIDEO_FORMAT_4KX2K);
1290 hdmi_dev_config_vsi(hdmi,
1292 HDMI_VIDEO_FORMAT_NORMAL);
1294 dev_info(hdmi->dev, "[%s] sucess output HDMI.\n", __func__);
1296 dev_info(hdmi->dev, "[%s] sucess output DVI.\n", __func__);
1299 rockchip_hdmiv2_config_phy(hdmi_dev);
1303 static void hdmi_dev_config_aai(struct hdmi_dev *hdmi_dev,
1304 struct hdmi_audio *audio)
1306 /*Refer to CEA861-E Audio infoFrame*/
1307 /*Set both Audio Channel Count and Audio Coding
1308 Type Refer to Stream Head for HDMI*/
1309 hdmi_msk_reg(hdmi_dev, FC_AUDICONF0,
1310 m_FC_CHN_CNT | m_FC_CODING_TYEP,
1311 v_FC_CHN_CNT(audio->channel-1) | v_FC_CODING_TYEP(0));
1313 /*Set both Audio Sample Size and Sample Frequency
1314 Refer to Stream Head for HDMI*/
1315 hdmi_msk_reg(hdmi_dev, FC_AUDICONF1,
1316 m_FC_SAMPLE_SIZE | m_FC_SAMPLE_FREQ,
1317 v_FC_SAMPLE_SIZE(0) | v_FC_SAMPLE_FREQ(0));
1319 /*Set Channel Allocation*/
1320 hdmi_writel(hdmi_dev, FC_AUDICONF2, 0x00);
1322 /*Set LFEPBL¡¢DOWN-MIX INH and LSV*/
1323 hdmi_writel(hdmi_dev, FC_AUDICONF3, 0x00);
1326 static int hdmi_dev_config_audio(struct hdmi *hdmi, struct hdmi_audio *audio)
1328 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1329 int word_length = 0, channel = 0, mclk_fs;
1330 unsigned int N = 0, CTS = 0;
1333 HDMIDBG("%s\n", __func__);
1335 if (audio->channel < 3)
1336 channel = I2S_CHANNEL_1_2;
1337 else if (audio->channel < 5)
1338 channel = I2S_CHANNEL_3_4;
1339 else if (audio->channel < 7)
1340 channel = I2S_CHANNEL_5_6;
1342 channel = I2S_CHANNEL_7_8;
1344 switch (audio->rate) {
1345 case HDMI_AUDIO_FS_32000:
1348 if (hdmi_dev->tmdsclk >= 594000000)
1350 else if (hdmi_dev->tmdsclk >= 297000000)
1354 /*div a num to avoid the value is exceed 2^32(int)*/
1355 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 32);
1357 case HDMI_AUDIO_FS_44100:
1360 if (hdmi_dev->tmdsclk >= 594000000)
1362 else if (hdmi_dev->tmdsclk >= 297000000)
1367 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 441);
1369 case HDMI_AUDIO_FS_48000:
1372 if (hdmi_dev->tmdsclk >= 594000000) /*FS_153.6*/
1374 else if (hdmi_dev->tmdsclk >= 297000000)
1379 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 48);
1381 case HDMI_AUDIO_FS_88200:
1384 if (hdmi_dev->tmdsclk >= 594000000)
1386 else if (hdmi_dev->tmdsclk >= 297000000)
1391 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 882);
1393 case HDMI_AUDIO_FS_96000:
1396 if (hdmi_dev->tmdsclk >= 594000000) /*FS_153.6*/
1398 else if (hdmi_dev->tmdsclk >= 297000000)
1403 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 96);
1405 case HDMI_AUDIO_FS_176400:
1408 if (hdmi_dev->tmdsclk >= 594000000)
1409 N = N_1764K_HIGHCLK;
1410 else if (hdmi_dev->tmdsclk >= 297000000)
1415 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 1764);
1417 case HDMI_AUDIO_FS_192000:
1420 if (hdmi_dev->tmdsclk >= 594000000) /*FS_153.6*/
1422 else if (hdmi_dev->tmdsclk >= 297000000)
1427 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 192);
1430 dev_err(hdmi_dev->hdmi->dev,
1431 "[%s] not support such sample rate %d\n",
1432 __func__, audio->rate);
1436 switch (audio->word_length) {
1437 case HDMI_AUDIO_WORD_LENGTH_16bit:
1438 word_length = I2S_16BIT_SAMPLE;
1440 case HDMI_AUDIO_WORD_LENGTH_20bit:
1441 word_length = I2S_20BIT_SAMPLE;
1443 case HDMI_AUDIO_WORD_LENGTH_24bit:
1444 word_length = I2S_24BIT_SAMPLE;
1447 word_length = I2S_16BIT_SAMPLE;
1450 HDMIDBG("rate = %d, tmdsclk = %u, N = %d, CTS = %d\n",
1451 audio->rate, hdmi_dev->tmdsclk, N, CTS);
1452 /* more than 2 channels => layout 1 else layout 0 */
1453 hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1455 v_AUD_PACK_LAYOUT((audio->channel > 2) ? 1 : 0));
1457 if (hdmi_dev->audiosrc == HDMI_AUDIO_SRC_SPDIF) {
1459 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1460 m_I2S_SEL, v_I2S_SEL(AUDIO_SPDIF_GPA));
1461 hdmi_msk_reg(hdmi_dev, AUD_SPDIF1,
1462 m_SET_NLPCM | m_SPDIF_WIDTH,
1463 v_SET_NLPCM(PCM_LINEAR) |
1464 v_SPDIF_WIDTH(word_length));
1465 /*Mask fifo empty and full int and reset fifo*/
1466 hdmi_msk_reg(hdmi_dev, AUD_SPDIFINT,
1467 m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1468 v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1469 hdmi_msk_reg(hdmi_dev, AUD_SPDIF0,
1470 m_SW_SAUD_FIFO_RST, v_SW_SAUD_FIFO_RST(1));
1472 /*Mask fifo empty and full int and reset fifo*/
1473 hdmi_msk_reg(hdmi_dev, AUD_INT,
1474 m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1475 v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1476 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1477 m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1478 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1479 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1480 usleep_range(90, 100);
1481 if (I2S_CHANNEL_7_8 == channel) {
1482 HDMIDBG("hbr mode.\n");
1483 hdmi_writel(hdmi_dev, AUD_CONF2, 0x1);
1484 word_length = I2S_24BIT_SAMPLE;
1485 } else if ((HDMI_AUDIO_FS_48000 == audio->rate) ||
1486 (HDMI_AUDIO_FS_192000 == audio->rate)) {
1487 HDMIDBG("nlpcm mode.\n");
1488 hdmi_writel(hdmi_dev, AUD_CONF2, 0x2);
1489 word_length = I2S_24BIT_SAMPLE;
1491 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1493 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1494 m_I2S_SEL | m_I2S_IN_EN,
1495 v_I2S_SEL(AUDIO_I2S) | v_I2S_IN_EN(channel));
1496 hdmi_writel(hdmi_dev, AUD_CONF1,
1497 v_I2S_MODE(I2S_STANDARD_MODE) |
1498 v_I2S_WIDTH(word_length));
1501 hdmi_msk_reg(hdmi_dev, AUD_INPUTCLKFS,
1502 m_LFS_FACTOR, v_LFS_FACTOR(mclk_fs));
1505 hdmi_msk_reg(hdmi_dev, AUD_N3, m_NCTS_ATOMIC_WR, v_NCTS_ATOMIC_WR(1));
1506 /*Set CTS by manual*/
1507 hdmi_msk_reg(hdmi_dev, AUD_CTS3,
1508 m_N_SHIFT | m_CTS_MANUAL | m_AUD_CTS3,
1509 v_N_SHIFT(N_SHIFT_1) |
1511 v_AUD_CTS3(CTS >> 16));
1512 hdmi_writel(hdmi_dev, AUD_CTS2, (CTS >> 8) & 0xff);
1513 hdmi_writel(hdmi_dev, AUD_CTS1, CTS & 0xff);
1515 hdmi_msk_reg(hdmi_dev, AUD_N3, m_AUD_N3, v_AUD_N3(N >> 16));
1516 hdmi_writel(hdmi_dev, AUD_N2, (N >> 8) & 0xff);
1517 hdmi_writel(hdmi_dev, AUD_N1, N & 0xff);
1519 /* set channel status register */
1520 hdmi_msk_reg(hdmi_dev, FC_AUDSCHNLS7,
1521 m_AUDIO_SAMPLE_RATE, v_AUDIO_SAMPLE_RATE(rate));
1522 hdmi_writel(hdmi_dev, FC_AUDSCHNLS8, ((~rate) << 4) | 0x2);
1524 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1525 m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1527 hdmi_dev_config_aai(hdmi_dev, audio);
1532 static int hdmi_dev_control_output(struct hdmi *hdmi, int enable)
1534 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1535 struct hdmi_video vpara;
1537 HDMIDBG("[%s] %d\n", __func__, enable);
1538 if (enable == HDMI_AV_UNMUTE) {
1539 hdmi_writel(hdmi_dev, FC_DBGFORCE, 0x00);
1540 if (hdmi->edid.sink_hdmi == OUTPUT_HDMI)
1541 hdmi_msk_reg(hdmi_dev, FC_GCP,
1542 m_FC_SET_AVMUTE | m_FC_CLR_AVMUTE,
1543 v_FC_SET_AVMUTE(0) | v_FC_CLR_AVMUTE(1));
1545 if (enable & HDMI_VIDEO_MUTE) {
1546 hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1547 m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1548 if (hdmi->edid.sink_hdmi == OUTPUT_HDMI) {
1549 hdmi_msk_reg(hdmi_dev, FC_GCP,
1552 v_FC_SET_AVMUTE(1) |
1553 v_FC_CLR_AVMUTE(0));
1554 vpara.vic = hdmi->vic;
1555 vpara.color_output = HDMI_COLOR_RGB_0_255;
1556 hdmi_dev_config_avi(hdmi_dev, &vpara);
1559 /* if (enable & HDMI_AUDIO_MUTE) {
1560 hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1562 v_AUD_PACK_SAMPFIT(0x0F));
1564 */ if (enable == (HDMI_VIDEO_MUTE | HDMI_AUDIO_MUTE)) {
1566 if (hdmi->ops->hdcp_power_off_cb)
1567 hdmi->ops->hdcp_power_off_cb(hdmi);
1568 rockchip_hdmiv2_powerdown(hdmi_dev);
1569 hdmi_dev->tmdsclk = 0;
1571 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1572 m_PDDQ_SIG | m_TXPWRON_SIG,
1573 v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1574 hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
1580 static int hdmi_dev_insert(struct hdmi *hdmi)
1582 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1584 HDMIDBG("%s\n", __func__);
1586 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1587 return HDMI_ERROR_SUCESS;
1590 static int hdmi_dev_remove(struct hdmi *hdmi)
1592 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1594 HDMIDBG("%s\n", __func__);
1595 if (hdmi->ops->hdcp_power_off_cb)
1596 hdmi->ops->hdcp_power_off_cb(hdmi);
1597 rockchip_hdmiv2_powerdown(hdmi_dev);
1598 hdmi_dev->tmdsclk = 0;
1599 return HDMI_ERROR_SUCESS;
1602 static int hdmi_dev_enable(struct hdmi *hdmi)
1604 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1606 HDMIDBG("%s\n", __func__);
1607 if (!hdmi_dev->enable) {
1608 hdmi_writel(hdmi_dev, IH_MUTE, 0x00);
1609 hdmi_dev->enable = 1;
1611 hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 10, NULL);
1615 static int hdmi_dev_disable(struct hdmi *hdmi)
1617 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1619 HDMIDBG("%s\n", __func__);
1620 if (hdmi_dev->enable) {
1621 hdmi_dev->enable = 0;
1622 hdmi_writel(hdmi_dev, IH_MUTE, 0x1);
1627 void rockchip_hdmiv2_dev_init_ops(struct hdmi_ops *ops)
1630 ops->enable = hdmi_dev_enable;
1631 ops->disable = hdmi_dev_disable;
1632 ops->getstatus = hdmi_dev_detect_hotplug;
1633 ops->insert = hdmi_dev_insert;
1634 ops->remove = hdmi_dev_remove;
1635 ops->getedid = hdmi_dev_read_edid;
1636 ops->setvideo = hdmi_dev_config_video;
1637 ops->setaudio = hdmi_dev_config_audio;
1638 ops->setmute = hdmi_dev_control_output;
1639 ops->setvsi = hdmi_dev_config_vsi;
1643 void rockchip_hdmiv2_dev_initial(struct hdmi_dev *hdmi_dev)
1645 struct hdmi *hdmi = hdmi_dev->hdmi;
1649 if (hdmi_dev->soctype == HDMI_SOC_RK3288) {
1650 writel_relaxed((1 << 9) | (1 << 25),
1651 RK_CRU_VIRT + 0x01d4);
1653 writel_relaxed((0 << 9) | (1 << 25),
1654 RK_CRU_VIRT + 0x01d4);
1655 } else if (hdmi_dev->soctype == HDMI_SOC_RK3368) {
1656 pr_info("reset hdmi\n");
1657 regmap_write(hdmi_dev->grf_base, 0x031c,
1658 (1 << 9) | (1 << 25));
1660 regmap_write(hdmi_dev->grf_base, 0x031c,
1661 (0 << 9) | (1 << 25));
1663 rockchip_hdmiv2_powerdown(hdmi_dev);
1665 /*mute unnecessary interrrupt, only enable hpd*/
1666 hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT0, 0xff);
1667 hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT1, 0xff);
1668 hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT2, 0xff);
1669 hdmi_writel(hdmi_dev, IH_MUTE_AS_STAT0, 0xff);
1670 hdmi_writel(hdmi_dev, IH_MUTE_PHY_STAT0, 0xfe);
1671 hdmi_writel(hdmi_dev, IH_MUTE_I2CM_STAT0, 0xff);
1672 hdmi_writel(hdmi_dev, IH_MUTE_CEC_STAT0, 0xff);
1673 hdmi_writel(hdmi_dev, IH_MUTE_VP_STAT0, 0xff);
1674 hdmi_writel(hdmi_dev, IH_MUTE_I2CMPHY_STAT0, 0xff);
1675 hdmi_writel(hdmi_dev, IH_MUTE_AHBDMAAUD_STAT0, 0xff);
1677 /* disable hdcp interrup */
1678 hdmi_writel(hdmi_dev, A_APIINTMSK, 0xff);
1679 hdmi_writel(hdmi_dev, PHY_MASK, 0xf1);
1681 if (hdmi->property->feature & SUPPORT_CEC)
1682 rockchip_hdmiv2_cec_init(hdmi);
1683 if (hdmi->property->feature & SUPPORT_HDCP)
1684 rockchip_hdmiv2_hdcp_init(hdmi);
1687 irqreturn_t rockchip_hdmiv2_dev_irq(int irq, void *priv)
1689 struct hdmi_dev *hdmi_dev = priv;
1690 struct hdmi *hdmi = hdmi_dev->hdmi;
1691 char phy_pol = hdmi_readl(hdmi_dev, PHY_POL0);
1692 char phy_status = hdmi_readl(hdmi_dev, PHY_STAT0);
1693 char phy_int0 = hdmi_readl(hdmi_dev, PHY_INI0);
1695 char fc_stat0 = hdmi_readl(hdmi_dev, IH_FC_STAT0);
1696 char fc_stat1 = hdmi_readl(hdmi_dev, IH_FC_STAT1);
1697 char fc_stat2 = hdmi_readl(hdmi_dev, IH_FC_STAT2);
1698 char aud_int = hdmi_readl(hdmi_dev, IH_AS_SATA0);
1699 char phy_int = hdmi_readl(hdmi_dev, IH_PHY_STAT0);
1700 char vp_stat0 = hdmi_readl(hdmi_dev, IH_VP_STAT0);
1701 char cec_int = hdmi_readl(hdmi_dev, IH_CEC_STAT0);
1702 char hdcp_int = hdmi_readl(hdmi_dev, A_APIINTSTAT);
1703 char hdcp2_int = hdmi_readl(hdmi_dev, HDCP2REG_STAT);
1706 hdmi_writel(hdmi_dev, IH_FC_STAT0, fc_stat0);
1707 hdmi_writel(hdmi_dev, IH_FC_STAT1, fc_stat1);
1708 hdmi_writel(hdmi_dev, IH_FC_STAT2, fc_stat2);
1709 hdmi_writel(hdmi_dev, IH_VP_STAT0, vp_stat0);
1711 if (phy_int0 || phy_int) {
1712 phy_pol = (phy_int0 & (~phy_status)) | ((~phy_int0) & phy_pol);
1713 hdmi_writel(hdmi_dev, PHY_POL0, phy_pol);
1714 hdmi_writel(hdmi_dev, IH_PHY_STAT0, phy_int);
1715 if ((phy_int & m_HPD) || ((phy_int & 0x3c) == 0x3c))
1716 hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 20, NULL);
1721 hdmi_writel(hdmi_dev, IH_AS_SATA0, aud_int);
1722 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1723 m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1724 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1728 hdmi_writel(hdmi_dev, IH_CEC_STAT0, cec_int);
1729 rockchip_hdmiv2_cec_isr(hdmi_dev, cec_int);
1733 hdmi_writel(hdmi_dev, A_APIINTCLR, hdcp_int);
1734 rockchip_hdmiv2_hdcp_isr(hdmi_dev, hdcp_int);
1739 hdmi_writel(hdmi_dev, HDCP2REG_STAT, hdcp2_int);
1740 pr_info("hdcp2_int is 0x%02x\n", hdcp2_int);
1741 if ((hdcp2_int & m_HDCP2_AUTH_FAIL ||
1742 hdcp2_int & m_HDCP2_AUTH_LOST) &&
1743 hdmi_dev->hdcp2_start) {
1744 pr_info("hdcp2 failed or lost\n");
1745 hdmi_dev->hdcp2_start();