drivers/video/rockchip/hdmi/rockchip-hdmiv2/rockchip_hdmiv2_hw.c

   1 #include <linux/clk.h>
   2 #include <linux/delay.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/rockchip/cru.h>
   5 #include <linux/rockchip/grf.h>
   6 #include <linux/rockchip/iomap.h>
   7 #include "rockchip_hdmiv2.h"
   8 #include "rockchip_hdmiv2_hw.h"
   9 #include <linux/rockchip/grf.h>
  10
  11 #define HDMI_SEL_LCDC(x, bit)   ((((x) & 1) << bit) | (1 << (16 + bit)))
  12 #define grf_writel(v, offset)   writel_relaxed(v, RK_GRF_VIRT + offset)
  13 #define RK3399_GRF_SOC_CON20 0x6250
  14
  15 static const struct phy_mpll_config_tab PHY_MPLL_TABLE[] = {
  16 /*      tmdsclk = (pixclk / ref_cntrl ) * (fbdiv2 * fbdiv1) / nctrl / tmdsmhl
  17  *      opmode: 0:HDMI1.4       1:HDMI2.0
  18  *
  19  *      |pixclock|      tmdsclock|pixrepet|colordepth|prepdiv|tmdsmhl|opmode|
  20  *              fbdiv2|fbdiv1|ref_cntrl|nctrl|propctrl|intctrl|gmpctrl|
  21  */
  22         {27000000,      27000000,       0,      8,      0,      0,      0,
  23                 2,      3,      0,      3,      3,      0,      0},
  24         {27000000,      27000000,       1,      8,      0,      0,      0,
  25                 2,      3,      0,      3,      3,      0,      0},
  26         {27000000,      33750000,       0,      10,     1,      0,      0,
  27                 5,      1,      0,      3,      3,      0,      0},
  28         {27000000,      33750000,       1,      10,     1,      0,      0,
  29                 5,      1,      0,      3,      3,      0,      0},
  30         {27000000,      40500000,       0,      12,     2,      0,      0,
  31                 3,      3,      0,      3,      3,      0,      0},
  32         {27000000,      54000000,       0,      16,     3,      0,      0,
  33                 2,      3,      0,      2,      5,      0,      1},
  34         {59400000,      59400000,       0,      8,      0,      0,      0,
  35                 1,      3,      0,      2,      5,      0,      1},
  36         {59400000,      74250000,       0,      10,     1,      0,      0,
  37                 5,      0,      0,      2,      5,      0,      1},
  38         {59400000,      89100000,       0,      12,     2,      0,      0,
  39                 2,      2,      0,      2,      5,      0,      1},
  40         {59400000,      118800000,      0,      16,     3,      0,      0,
  41                 1,      3,      0,      1,      7,      0,      2},
  42         {65000000,      65000000,       0,      8,      0,      0,      0,
  43                 1,      3,      0,      2,      5,      0,      1},
  44         {74250000,      74250000,       0,      8,      0,      0,      0,
  45                 4,      3,      3,      2,      7,      0,      3},
  46         {74250000,      92812500,       0,      10,     1,      0,      0,
  47                 5,      0,      1,      1,      7,      0,      2},
  48         {74250000,      111375000,      0,      12,     2,      0,      0,
  49                 1,      2,      0,      1,      7,      0,      2},
  50         {74250000,      148500000,      0,      16,     3,      0,      0,
  51                 1,      3,      0,      1,      7,      0,      2},
  52         {83500000,      83500000,       0,      8,      0,      0,      0,
  53                 1,      3,      0,      2,      5,      0,      1},
  54         {85500000,      85500000,       0,      8,      0,      0,      0,
  55                 1,      3,      0,      2,      5,      0,      1},
  56         {106500000,     106500000,      0,      8,      0,      0,      0,
  57                 1,      1,      0,      1,      7,      0,      2},
  58         {108000000,     108000000,      0,      8,      0,      0,      0,
  59                 1,      1,      0,      1,      7,      0,      2},
  60         {146250000,     146250000,      0,      8,      0,      0,      0,
  61                 1,      1,      0,      1,      7,      0,      2},
  62         {148500000,     74250000,       0,      8,      0,      0,      0,
  63                 1,      1,      1,      1,      0,      0,      3},
  64         {148500000,     148500000,      0,      8,      0,      0,      0,
  65                 1,      1,      0,      1,      0,      0,      3},
  66         {148500000,     185625000,      0,      10,     1,      0,      0,
  67                 5,      0,      3,      0,      7,      0,      3},
  68         {148500000,     222750000,      0,      12,     2,      0,      0,
  69                 1,      2,      1,      0,      7,      0,      3},
  70         {148500000,     297000000,      0,      16,     3,      0,      0,
  71                 1,      1,      0,      0,      7,      0,      3},
  72         {148500000,     297000000,      0,      8,      0,      0,      0,
  73                 1,      1,      0,      0,      0,      0,      3},
  74         {148500000,     594000000,      0,      8,      0,      3,      1,
  75                 1,      3,      0,      0,      0,      0,      3},
  76         {269390000,     269390000,      0,      8,      0,      0,      0,
  77                 1,      0,      0,      0,      0,      0,      3},
  78         {297000000,     148500000,      0,      8,      0,      0,      0,
  79                 1,      0,      1,      0,      0,      0,      3},
  80         {297000000,     297000000,      0,      8,      0,      0,      0,
  81                 1,      0,      0,      0,      0,      0,      3},
  82         {297000000,     371250000,      0,      10,     1,      3,      1,
  83                 5,      1,      3,      1,      7,      0,      3},
  84         {297000000,     445500000,      0,      12,     2,      3,      1,
  85                 1,      2,      0,      1,      7,      0,      3},
  86         {297000000,     594000000,      0,      16,     3,      3,      1,
  87                 1,      3,      1,      0,      0,      0,      3},
  88         {340000000,     340000000,      0,      8,      0,      0,      0,
  89                 1,      0,      0,      0,      0,      0,      3},
  90         {403000000,     403000000,      0,      8,      0,      3,      1,
  91                 1,      3,      3,      0,      0,      0,      3},
  92         {594000000,     297000000,      0,      8,      0,      0,      0,
  93                 1,      0,      1,      0,      0,      0,      3},
  94         {594000000,     371250000,      0,      10,     1,      3,      1,
  95                 5,      0,      3,      1,      7,      0,      3},
  96         {594000000,     445500000,      0,      12,     2,      3,      1,
  97                 1,      2,      1,      1,      7,      0,      3},
  98         {594000000,     594000000,      0,      16,     3,      3,      1,
  99                 1,      3,      3,      0,      0,      0,      3},
 100         {594000000,     594000000,      0,      8,      0,      3,      1,
 101                 1,      3,      3,      0,      0,      0,      3},
 102 };
 103
 104 static const struct ext_pll_config_tab EXT_PLL_TABLE[] = {
 105         {27000000,      27000000,       8,      1,      90,     3,      2,
 106                 2,      10,     3,      3,      4,      0,      1,      40,
 107                 8},
 108         {27000000,      33750000,       10,     1,      90,     1,      3,
 109                 3,      10,     3,      3,      4,      0,      1,      40,
 110                 8},
 111         {59400000,      59400000,       8,      1,      99,     3,      2,
 112                 2,      1,      3,      3,      4,      0,      1,      40,
 113                 8},
 114         {59400000,      74250000,       10,     1,      99,     1,      2,
 115                 2,      1,      3,      3,      4,      0,      1,      40,
 116                 8},
 117         {74250000,      74250000,       8,      1,      99,     1,      2,
 118                 2,      1,      2,      3,      4,      0,      1,      40,
 119                 8},
 120         {74250000,      92812500,       10,     4,      495,    1,      2,
 121                 2,      1,      3,      3,      4,      0,      2,      40,
 122                 4},
 123         {148500000,     148500000,      8,      1,      99,     1,      1,
 124                 1,      1,      2,      2,      2,      0,      2,      40,
 125                 4},
 126         {148500000,     185625000,      10,     4,      495,    0,      2,
 127                 2,      1,      3,      2,      2,      0,      4,      40,
 128                 2},
 129         {297000000,     297000000,      8,      1,      99,     0,      1,
 130                 1,      1,      0,      2,      2,      0,      4,      40,
 131                 2},
 132         {297000000,     371250000,      10,     4,      495,    1,      2,
 133                 0,      1,      3,      1,      1,      0,      8,      40,
 134                 1},
 135         {594000000,     297000000,      8,      1,      99,     0,      1,
 136                 1,      1,      0,      2,      1,      0,      4,      40,
 137                 2},
 138         {594000000,     371250000,      10,     4,      495,    1,      2,
 139                 0,      1,      3,      1,      1,      1,      8,      40,
 140                 1},
 141         {594000000,     594000000,      8,      1,      99,     0,      2,
 142                 0,      1,      0,      1,      1,      0,      8,      40,
 143                 1},
 144 };
 145
 146 /* ddc i2c master reset */
 147 static void rockchip_hdmiv2_i2cm_reset(struct hdmi_dev *hdmi_dev)
 148 {
 149         hdmi_msk_reg(hdmi_dev, I2CM_SOFTRSTZ,
 150                      m_I2CM_SOFTRST, v_I2CM_SOFTRST(0));
 151         usleep_range(90, 100);
 152 }
 153
 154 /*set read/write offset,set read/write mode*/
 155 static void rockchip_hdmiv2_i2cm_write_request(struct hdmi_dev *hdmi_dev,
 156                                                u8 offset, u8 data)
 157 {
 158         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
 159         hdmi_writel(hdmi_dev, I2CM_DATAO, data);
 160         hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_WR, v_I2CM_WR(1));
 161 }
 162
 163 static void rockchip_hdmiv2_i2cm_read_request(struct hdmi_dev *hdmi_dev,
 164                                               u8 offset)
 165 {
 166         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
 167         hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_RD, v_I2CM_RD(1));
 168 }
 169
 170 static void rockchip_hdmiv2_i2cm_write_data(struct hdmi_dev *hdmi_dev,
 171                                             u8 data, u8 offset)
 172 {
 173         u8 interrupt = 0;
 174         int trytime = 2;
 175         int i = 20;
 176
 177         while (trytime-- > 0) {
 178                 rockchip_hdmiv2_i2cm_write_request(hdmi_dev, offset, data);
 179                 while (i--) {
 180                         usleep_range(900, 1000);
 181                         interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
 182                         if (interrupt)
 183                                 hdmi_writel(hdmi_dev,
 184                                             IH_I2CM_STAT0, interrupt);
 185
 186                         if (interrupt & (m_SCDC_READREQ |
 187                                          m_I2CM_DONE | m_I2CM_ERROR))
 188                                 break;
 189                 }
 190
 191                 if (interrupt & m_I2CM_DONE) {
 192                         dev_dbg(hdmi_dev->hdmi->dev,
 193                                 "[%s] write offset %02x data %02x success\n",
 194                                 __func__, offset, data);
 195                         trytime = 0;
 196                 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
 197                         dev_err(hdmi_dev->hdmi->dev,
 198                                 "[%s] write data error\n", __func__);
 199                         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 200                 }
 201         }
 202 }
 203
 204 static int rockchip_hdmiv2_i2cm_read_data(struct hdmi_dev *hdmi_dev, u8 offset)
 205 {
 206         u8 interrupt = 0, val;
 207         int trytime = 2;
 208         int i = 20;
 209
 210         while (trytime-- > 0) {
 211                 rockchip_hdmiv2_i2cm_read_request(hdmi_dev, offset);
 212                 while (i--) {
 213                         usleep_range(900, 1000);
 214                         interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
 215                         if (interrupt)
 216                                 hdmi_writel(hdmi_dev, IH_I2CM_STAT0, interrupt);
 217
 218                         if (interrupt & (m_SCDC_READREQ |
 219                                 m_I2CM_DONE | m_I2CM_ERROR))
 220                                 break;
 221                 }
 222
 223                 if (interrupt & m_I2CM_DONE) {
 224                         val = hdmi_readl(hdmi_dev, I2CM_DATAI);
 225                         trytime = 0;
 226                 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
 227                         pr_err("[%s] read data error\n", __func__);
 228                         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 229                 }
 230         }
 231         return val;
 232 }
 233
 234 static void rockchip_hdmiv2_i2cm_mask_int(struct hdmi_dev *hdmi_dev, int mask)
 235 {
 236         if (!mask) {
 237                 hdmi_msk_reg(hdmi_dev, I2CM_INT,
 238                              m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(0));
 239                 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
 240                              m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
 241                              v_I2CM_NACK_MASK(0) | v_I2CM_ARB_MASK(0));
 242         } else {
 243                 hdmi_msk_reg(hdmi_dev, I2CM_INT,
 244                              m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(1));
 245                 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
 246                              m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
 247                              v_I2CM_NACK_MASK(1) | v_I2CM_ARB_MASK(1));
 248         }
 249 }
 250
 251 #define I2C_DIV_FACTOR 1000000
 252 static u16 i2c_count(u16 sfrclock, u16 sclmintime)
 253 {
 254         unsigned long tmp_scl_period = 0;
 255
 256         if (((sfrclock * sclmintime) % I2C_DIV_FACTOR) != 0)
 257                 tmp_scl_period = (unsigned long)((sfrclock * sclmintime) +
 258                                 (I2C_DIV_FACTOR - ((sfrclock * sclmintime) %
 259                                 I2C_DIV_FACTOR))) / I2C_DIV_FACTOR;
 260         else
 261                 tmp_scl_period = (unsigned long)(sfrclock * sclmintime) /
 262                                 I2C_DIV_FACTOR;
 263
 264         return (u16)(tmp_scl_period);
 265 }
 266
 267 #define EDID_I2C_MIN_SS_SCL_HIGH_TIME   9625
 268 #define EDID_I2C_MIN_SS_SCL_LOW_TIME    10000
 269
 270 static void rockchip_hdmiv2_i2cm_clk_init(struct hdmi_dev *hdmi_dev)
 271 {
 272         int value;
 273
 274         /* Set DDC I2C CLK which divided from DDC_CLK. */
 275         value = i2c_count(24000, EDID_I2C_MIN_SS_SCL_HIGH_TIME);
 276         hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_0_ADDR,
 277                     value & 0xff);
 278         hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_1_ADDR,
 279                     (value >> 8) & 0xff);
 280         value = i2c_count(24000, EDID_I2C_MIN_SS_SCL_LOW_TIME);
 281         hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_0_ADDR,
 282                     value & 0xff);
 283         hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_1_ADDR,
 284                     (value >> 8) & 0xff);
 285         hdmi_msk_reg(hdmi_dev, I2CM_DIV, m_I2CM_FAST_STD_MODE,
 286                      v_I2CM_FAST_STD_MODE(STANDARD_MODE));
 287 }
 288
 289 static int rockchip_hdmiv2_scdc_get_sink_version(struct hdmi_dev *hdmi_dev)
 290 {
 291         return rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SINK_VER);
 292 }
 293
 294 static void rockchip_hdmiv2_scdc_set_source_version(struct hdmi_dev *hdmi_dev,
 295                                                     u8 version)
 296 {
 297         rockchip_hdmiv2_i2cm_write_data(hdmi_dev, version, SCDC_SOURCE_VER);
 298 }
 299
 300 static void rockchip_hdmiv2_scdc_read_request(struct hdmi_dev *hdmi_dev,
 301                                               int enable)
 302 {
 303         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 304                      m_I2CM_READ_REQ_EN, v_I2CM_READ_REQ_EN(enable));
 305         rockchip_hdmiv2_i2cm_write_data(hdmi_dev, enable, SCDC_CONFIG_0);
 306 }
 307
 308 #ifdef HDMI_20_SCDC
 309 static void rockchip_hdmiv2_scdc_update_read(struct hdmi_dev *hdmi_dev)
 310 {
 311         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 312                      m_I2CM_READ_UPDATE, v_I2CM_READ_UPDATE(1));
 313 }
 314
 315 static int rockchip_hdmiv2_scdc_get_scambling_status(struct hdmi_dev *hdmi_dev)
 316 {
 317         int val;
 318
 319         val = rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SCRAMBLER_STAT);
 320         return val;
 321 }
 322
 323 static void rockchip_hdmiv2_scdc_enable_polling(struct hdmi_dev *hdmi_dev,
 324                                                 int enable)
 325 {
 326         rockchip_hdmiv2_scdc_read_request(hdmi_dev, enable);
 327         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 328                      m_I2CM_UPRD_VSYNC_EN, v_I2CM_UPRD_VSYNC_EN(enable));
 329 }
 330
 331 static int rockchip_hdmiv2_scdc_get_status_reg0(struct hdmi_dev *hdmi_dev)
 332 {
 333         rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 334         rockchip_hdmiv2_scdc_update_read(hdmi_dev);
 335         return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE0);
 336 }
 337
 338 static int rockchip_hdmiv2_scdc_get_status_reg1(struct hdmi_dev *hdmi_dev)
 339 {
 340         rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 341         rockchip_hdmiv2_scdc_update_read(hdmi_dev);
 342         return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE1);
 343 }
 344 #endif
 345
 346 static void rockchip_hdmiv2_scdc_init(struct hdmi_dev *hdmi_dev)
 347 {
 348         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 349         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
 350         rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
 351         /* set scdc i2c addr */
 352         hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_SCDC_ADDR);
 353         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);/*enable interrupt*/
 354 }
 355
 356 static void rockchip_hdmiv2_scdc_set_tmds_rate(struct hdmi_dev *hdmi_dev)
 357 {
 358         int stat;
 359
 360         mutex_lock(&hdmi_dev->ddc_lock);
 361         rockchip_hdmiv2_scdc_init(hdmi_dev);
 362         stat = rockchip_hdmiv2_i2cm_read_data(hdmi_dev,
 363                                               SCDC_TMDS_CONFIG);
 364         if (hdmi_dev->tmdsclk > 340000000)
 365                 stat |= 2;
 366         else
 367                 stat &= 0x1;
 368         rockchip_hdmiv2_i2cm_write_data(hdmi_dev,
 369                                         stat, SCDC_TMDS_CONFIG);
 370         mutex_unlock(&hdmi_dev->ddc_lock);
 371 }
 372
 373 static int rockchip_hdmiv2_scrambling_enable(struct hdmi_dev *hdmi_dev,
 374                                              int enable)
 375 {
 376         HDMIDBG("%s enable %d\n", __func__, enable);
 377         if (enable == 1) {
 378                 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
 379                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 1, SCDC_TMDS_CONFIG);
 380                 /* TMDS software reset request */
 381                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 382                              m_TMDS_SWRST, v_TMDS_SWRST(0));
 383                 /* Enable/Disable Scrambling */
 384                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 385                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(1));
 386         } else {
 387                 /* Enable/Disable Scrambling */
 388                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 389                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
 390                 /* TMDS software reset request */
 391                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 392                              m_TMDS_SWRST, v_TMDS_SWRST(0));
 393                 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
 394                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 0, SCDC_TMDS_CONFIG);
 395         }
 396         return 0;
 397 }
 398
 399 static const struct ext_pll_config_tab *get_phy_ext_tab(
 400                 unsigned int pixclock, unsigned int tmdsclk,
 401                 char colordepth)
 402 {
 403         int i;
 404
 405         if (pixclock == 0)
 406                 return NULL;
 407         HDMIDBG("%s pixClock %u tmdsclk %u colorDepth %d\n",
 408                 __func__, pixclock, tmdsclk, colordepth);
 409         for (i = 0; i < ARRAY_SIZE(EXT_PLL_TABLE); i++) {
 410                 if ((EXT_PLL_TABLE[i].pix_clock == pixclock) &&
 411                     (EXT_PLL_TABLE[i].tmdsclock == tmdsclk) &&
 412                     (EXT_PLL_TABLE[i].color_depth == colordepth))
 413                         return &EXT_PLL_TABLE[i];
 414         }
 415         return NULL;
 416 }
 417
 418 static const struct phy_mpll_config_tab *get_phy_mpll_tab(
 419                 unsigned int pixclock, unsigned int tmdsclk,
 420                 char pixrepet, char colordepth)
 421 {
 422         int i;
 423
 424         if (pixclock == 0)
 425                 return NULL;
 426         HDMIDBG("%s pixClock %u tmdsclk %u pixRepet %d colorDepth %d\n",
 427                 __func__, pixclock, tmdsclk, pixrepet, colordepth);
 428         for (i = 0; i < ARRAY_SIZE(PHY_MPLL_TABLE); i++) {
 429                 if ((PHY_MPLL_TABLE[i].pix_clock == pixclock) &&
 430                     (PHY_MPLL_TABLE[i].tmdsclock == tmdsclk) &&
 431                     (PHY_MPLL_TABLE[i].pix_repet == pixrepet) &&
 432                     (PHY_MPLL_TABLE[i].color_depth == colordepth))
 433                         return &PHY_MPLL_TABLE[i];
 434         }
 435         return NULL;
 436 }
 437
 438 static void rockchip_hdmiv2_powerdown(struct hdmi_dev *hdmi_dev)
 439 {
 440         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(1));
 441         if (hdmi_dev->soctype != HDMI_SOC_RK322X) {
 442                 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 443                              m_PDDQ_SIG | m_TXPWRON_SIG |
 444                              m_ENHPD_RXSENSE_SIG | m_SVSRET_SIG,
 445                              v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) |
 446                              v_ENHPD_RXSENSE_SIG(1)) | v_SVSRET_SIG(0);
 447         } else {
 448                 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 449                              m_TXPWRON_SIG | m_ENHPD_RXSENSE_SIG,
 450                              v_TXPWRON_SIG(0) | v_ENHPD_RXSENSE_SIG(0));
 451                 regmap_write(hdmi_dev->grf_base,
 452                              RK322X_GRF_SOC_CON2,
 453                              RK322X_PLL_PDATA_DEN);
 454         }
 455         hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
 456 }
 457
 458 int rockchip_hdmiv2_write_phy(struct hdmi_dev *hdmi_dev,
 459                               int reg_addr, int val)
 460 {
 461         int trytime = 2, i = 0, op_status = 0;
 462
 463         if (hdmi_dev->phybase) {
 464                 writel_relaxed(val, hdmi_dev->phybase + (reg_addr) * 0x04);
 465                 return 0;
 466         }
 467         while (trytime--) {
 468                 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
 469                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_1, (val >> 8) & 0xff);
 470                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_0, val & 0xff);
 471                 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_WRITE);
 472
 473                 i = 20;
 474                 while (i--) {
 475                         usleep_range(900, 1000);
 476                         op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
 477                         if (op_status)
 478                                 hdmi_writel(hdmi_dev,
 479                                             IH_I2CMPHY_STAT0,
 480                                             op_status);
 481
 482                         if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
 483                                 break;
 484                 }
 485
 486                 if (!(op_status & m_I2CMPHY_DONE))
 487                         dev_err(hdmi_dev->hdmi->dev,
 488                                 "[%s] operation error,trytime=%d\n",
 489                                 __func__, trytime);
 490                 else
 491                         return 0;
 492                 msleep(100);
 493         }
 494
 495         return -1;
 496 }
 497
 498 int rockchip_hdmiv2_read_phy(struct hdmi_dev *hdmi_dev,
 499                              int reg_addr)
 500 {
 501         int trytime = 2, i = 0, op_status = 0;
 502         int val = 0;
 503
 504         if (hdmi_dev->phybase)
 505                 return readl_relaxed(hdmi_dev->phybase + (reg_addr) * 0x04);
 506
 507         while (trytime--) {
 508                 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
 509                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_1, 0x00);
 510                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_0, 0x00);
 511                 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_READ);
 512
 513                 i = 20;
 514                 while (i--) {
 515                         usleep_range(900, 1000);
 516                         op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
 517                         if (op_status)
 518                                 hdmi_writel(hdmi_dev, IH_I2CMPHY_STAT0,
 519                                             op_status);
 520
 521                         if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
 522                                 break;
 523                 }
 524
 525                 if (!(op_status & m_I2CMPHY_DONE)) {
 526                         pr_err("[%s] operation error,trytime=%d\n",
 527                                __func__, trytime);
 528                 } else {
 529                         val = hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_1);
 530                         val = (val & 0xff) << 8;
 531                         val += (hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_0) & 0xff);
 532                         pr_debug("phy_reg0x%02x: 0x%04x",
 533                                  reg_addr, val);
 534                         return val;
 535                 }
 536                 msleep(100);
 537         }
 538
 539         return -1;
 540 }
 541
 542 #define PHY_TIMEOUT     10000
 543
 544 static int ext_phy_config(struct hdmi_dev *hdmi_dev)
 545 {
 546         int stat = 0, i = 0, temp;
 547         const struct ext_pll_config_tab *phy_ext = NULL;
 548
 549         if (hdmi_dev->grf_base)
 550                 regmap_write(hdmi_dev->grf_base,
 551                              RK322X_GRF_SOC_CON2,
 552                              RK322X_PLL_POWER_DOWN |
 553                              RK322X_PLL_PDATA_DEN);
 554         if (hdmi_dev->tmdsclk_ratio_change &&
 555             hdmi_dev->hdmi->edid.scdc_present == 1)
 556                 rockchip_hdmiv2_scdc_set_tmds_rate(hdmi_dev);
 557
 558         /* config the required PHY I2C register */
 559         phy_ext = get_phy_ext_tab(hdmi_dev->pixelclk,
 560                                   hdmi_dev->tmdsclk,
 561                                   hdmi_dev->colordepth);
 562         if (phy_ext) {
 563                 stat = ((phy_ext->pll_nf >> 1) & EXT_PHY_PLL_FB_BIT8_MASK) |
 564                        ((phy_ext->vco_div_5 & 1) << 5) |
 565                        (phy_ext->pll_nd & EXT_PHY_PLL_PRE_DIVIDER_MASK);
 566                 rockchip_hdmiv2_write_phy(hdmi_dev,
 567                                           EXT_PHY_PLL_PRE_DIVIDER, stat);
 568                 stat = phy_ext->pll_nf & 0xff;
 569                 rockchip_hdmiv2_write_phy(hdmi_dev,
 570                                           EXT_PHY_PLL_FB_DIVIDER, stat);
 571                 stat = (phy_ext->pclk_divider_a & EXT_PHY_PCLK_DIVIDERA_MASK) |
 572                        ((phy_ext->pclk_divider_b & 3) << 5);
 573                 rockchip_hdmiv2_write_phy(hdmi_dev,
 574                                           EXT_PHY_PCLK_DIVIDER1, stat);
 575                 stat = (phy_ext->pclk_divider_d & EXT_PHY_PCLK_DIVIDERD_MASK) |
 576                        ((phy_ext->pclk_divider_c & 3) << 5);
 577                 rockchip_hdmiv2_write_phy(hdmi_dev,
 578                                           EXT_PHY_PCLK_DIVIDER2, stat);
 579                 stat = ((phy_ext->tmsd_divider_c & 3) << 4) |
 580                        ((phy_ext->tmsd_divider_a & 3) << 2) |
 581                        (phy_ext->tmsd_divider_b & 3);
 582                 rockchip_hdmiv2_write_phy(hdmi_dev,
 583                                           EXT_PHY_TMDSCLK_DIVIDER, stat);
 584                 rockchip_hdmiv2_write_phy(hdmi_dev,
 585                                           EXT_PHY_PPLL_FB_DIVIDER,
 586                                           phy_ext->ppll_nf);
 587
 588                 if (phy_ext->ppll_no == 1) {
 589                         rockchip_hdmiv2_write_phy(hdmi_dev,
 590                                                   EXT_PHY_PPLL_POST_DIVIDER,
 591                                                   0);
 592                         stat = 0x20 | phy_ext->ppll_nd;
 593                         rockchip_hdmiv2_write_phy(hdmi_dev,
 594                                                   EXT_PHY_PPLL_PRE_DIVIDER,
 595                                                   stat);
 596                 } else {
 597                         stat = ((phy_ext->ppll_no / 2) - 1) << 4;
 598                         rockchip_hdmiv2_write_phy(hdmi_dev,
 599                                                   EXT_PHY_PPLL_POST_DIVIDER,
 600                                                   stat);
 601                         stat = 0xe0 | phy_ext->ppll_nd;
 602                         rockchip_hdmiv2_write_phy(hdmi_dev,
 603                                                   EXT_PHY_PPLL_PRE_DIVIDER,
 604                                                   stat);
 605                 }
 606         } else {
 607                 pr_err("%s no supported phy configuration.\n", __func__);
 608                 return -1;
 609         }
 610
 611         if (hdmi_dev->phy_table) {
 612                 for (i = 0; i < hdmi_dev->phy_table_size; i++) {
 613                         temp = hdmi_dev->phy_table[i].maxfreq;
 614                         if (hdmi_dev->tmdsclk <= temp)
 615                                 break;
 616                 }
 617         }
 618
 619         if (i != hdmi_dev->phy_table_size) {
 620                 if (hdmi_dev->phy_table[i].slopeboost) {
 621                         rockchip_hdmiv2_write_phy(hdmi_dev,
 622                                                   EXT_PHY_SIGNAL_CTRL, 0xff);
 623                         temp = hdmi_dev->phy_table[i].slopeboost - 1;
 624                         stat = ((temp & 3) << 6) | ((temp & 3) << 4) |
 625                                ((temp & 3) << 2) | (temp & 3);
 626                         rockchip_hdmiv2_write_phy(hdmi_dev,
 627                                                   EXT_PHY_SLOPEBOOST, stat);
 628                 } else {
 629                         rockchip_hdmiv2_write_phy(hdmi_dev,
 630                                                   EXT_PHY_SIGNAL_CTRL, 0x0f);
 631                 }
 632                 stat = ((hdmi_dev->phy_table[i].pre_emphasis & 3) << 4) |
 633                        ((hdmi_dev->phy_table[i].pre_emphasis & 3) << 2) |
 634                        (hdmi_dev->phy_table[i].pre_emphasis & 3);
 635                 rockchip_hdmiv2_write_phy(hdmi_dev,
 636                                           EXT_PHY_PREEMPHASIS, stat);
 637                 stat = ((hdmi_dev->phy_table[i].clk_level & 0xf) << 4) |
 638                        (hdmi_dev->phy_table[i].data2_level & 0xf);
 639                 rockchip_hdmiv2_write_phy(hdmi_dev,
 640                                           EXT_PHY_LEVEL1, stat);
 641                 stat = ((hdmi_dev->phy_table[i].data1_level & 0xf) << 4) |
 642                        (hdmi_dev->phy_table[i].data0_level & 0xf);
 643                 rockchip_hdmiv2_write_phy(hdmi_dev,
 644                                           EXT_PHY_LEVEL2, stat);
 645         } else {
 646                 rockchip_hdmiv2_write_phy(hdmi_dev,
 647                                           EXT_PHY_SIGNAL_CTRL, 0x0f);
 648         }
 649         rockchip_hdmiv2_write_phy(hdmi_dev, 0xf3, 0x22);
 650
 651         stat = clk_get_rate(hdmi_dev->pclk_phy) / 100000;
 652         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL,
 653                                   ((stat >> 8) & 0xff) | 0x80);
 654         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL_DIV_L,
 655                                   stat & 0xff);
 656         if (hdmi_dev->tmdsclk > 340000000)
 657                 stat = EXT_PHY_AUTO_R100_OHMS;
 658         else if (hdmi_dev->tmdsclk > 200000000)
 659                 stat = EXT_PHY_AUTO_R50_OHMS;
 660         else
 661                 stat = EXT_PHY_AUTO_ROPEN_CIRCUIT;
 662         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_RESIS_AUTO,
 663                                   stat | 0x20);
 664         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL,
 665                                   (stat >> 8) & 0xff);
 666         if (hdmi_dev->tmdsclk > 200000000)
 667                 stat = 0;
 668         else
 669                 stat = 0x11;
 670         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_PLL_BW, stat);
 671         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_PPLL_BW, 0x27);
 672         if (hdmi_dev->grf_base)
 673                 regmap_write(hdmi_dev->grf_base,
 674                              RK322X_GRF_SOC_CON2,
 675                              RK322X_PLL_POWER_UP);
 676         if (hdmi_dev->tmdsclk_ratio_change)
 677                 msleep(100);
 678         else
 679                 usleep_range(900, 1000);
 680         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 681                      m_TXPWRON_SIG, v_TXPWRON_SIG(1));
 682         i = 0;
 683         while (i++ < PHY_TIMEOUT) {
 684                 if ((i % 10) == 0) {
 685                         temp = EXT_PHY_PPLL_POST_DIVIDER;
 686                         stat = rockchip_hdmiv2_read_phy(hdmi_dev, temp);
 687                         if (stat & EXT_PHY_PPLL_LOCK_STATUS_MASK)
 688                                 break;
 689                         usleep_range(1000, 2000);
 690                 }
 691         }
 692         if ((stat & EXT_PHY_PPLL_LOCK_STATUS_MASK) == 0) {
 693                 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
 694                 dev_err(hdmi_dev->hdmi->dev,
 695                         "PHY PLL not locked: PCLK_ON=%ld,TMDSCLK_ON=%ld\n",
 696                         (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
 697                 return -1;
 698         }
 699
 700         if (hdmi_dev->grf_base)
 701                 regmap_write(hdmi_dev->grf_base,
 702                              RK322X_GRF_SOC_CON2,
 703                              RK322X_PLL_PDATA_EN);
 704
 705         return 0;
 706 }
 707
 708 static int rockchip_hdmiv2_config_phy(struct hdmi_dev *hdmi_dev)
 709 {
 710         int stat = 0, i = 0;
 711         const struct phy_mpll_config_tab *phy_mpll = NULL;
 712
 713         if (hdmi_dev->soctype == HDMI_SOC_RK322X) {
 714                 return ext_phy_config(hdmi_dev);
 715         } else if (hdmi_dev->soctype == HDMI_SOC_RK3366) {
 716                 if (hdmi_dev->pixelclk > 148500000)
 717                         clk_set_rate(hdmi_dev->pclk_phy, 148500000);
 718                 else
 719                         clk_set_rate(hdmi_dev->pclk_phy, hdmi_dev->pixelclk);
 720         } else if (hdmi_dev->soctype == HDMI_SOC_RK3399) {
 721                 clk_set_rate(hdmi_dev->pclk_phy, hdmi_dev->pixelclk);
 722         }
 723
 724         hdmi_msk_reg(hdmi_dev, PHY_I2CM_DIV,
 725                      m_PHY_I2CM_FAST_STD, v_PHY_I2CM_FAST_STD(0));
 726         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(1));
 727         /* power off PHY */
 728         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 729                      m_PDDQ_SIG | m_TXPWRON_SIG | m_SVSRET_SIG,
 730                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) | v_SVSRET_SIG(1));
 731
 732         if (hdmi_dev->tmdsclk_ratio_change &&
 733             hdmi_dev->hdmi->edid.scdc_present == 1)
 734                 rockchip_hdmiv2_scdc_set_tmds_rate(hdmi_dev);
 735
 736         /* reset PHY */
 737         hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(1));
 738         usleep_range(1000, 2000);
 739         hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(0));
 740
 741         /* Set slave address as PHY GEN2 address */
 742         hdmi_writel(hdmi_dev, PHY_I2CM_SLAVE, PHY_GEN2_ADDR);
 743
 744         /* config the required PHY I2C register */
 745         if (hdmi_dev->soctype == HDMI_SOC_RK3366 &&
 746             hdmi_dev->pixelclk > 148500000)
 747                 phy_mpll = get_phy_mpll_tab(148500000,
 748                                             hdmi_dev->tmdsclk,
 749                                             hdmi_dev->pixelrepeat - 1,
 750                                             hdmi_dev->colordepth);
 751         else
 752                 phy_mpll = get_phy_mpll_tab(hdmi_dev->pixelclk,
 753                                             hdmi_dev->tmdsclk,
 754                                             hdmi_dev->pixelrepeat - 1,
 755                                             hdmi_dev->colordepth);
 756         if (phy_mpll) {
 757                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_OPMODE_PLLCFG,
 758                                           v_PREP_DIV(phy_mpll->prep_div) |
 759                                           v_TMDS_CNTRL(
 760                                           phy_mpll->tmdsmhl_cntrl) |
 761                                           v_OPMODE(phy_mpll->opmode) |
 762                                           v_FBDIV2_CNTRL(
 763                                           phy_mpll->fbdiv2_cntrl) |
 764                                           v_FBDIV1_CNTRL(
 765                                           phy_mpll->fbdiv1_cntrl) |
 766                                           v_REF_CNTRL(phy_mpll->ref_cntrl) |
 767                                           v_MPLL_N_CNTRL(phy_mpll->n_cntrl));
 768                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLCURRCTRL,
 769                                           v_MPLL_PROP_CNTRL(
 770                                           phy_mpll->prop_cntrl) |
 771                                           v_MPLL_INT_CNTRL(
 772                                           phy_mpll->int_cntrl));
 773                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLGMPCTRL,
 774                                           v_MPLL_GMP_CNTRL(
 775                                           phy_mpll->gmp_cntrl));
 776         }
 777
 778         if (hdmi_dev->phy_table) {
 779                 for (i = 0; i < hdmi_dev->phy_table_size; i++)
 780                         if (hdmi_dev->tmdsclk <= hdmi_dev->phy_table[i].maxfreq)
 781                                 break;
 782         }
 783         if (i == hdmi_dev->phy_table_size) {
 784                 pr_info("%s use default phy settings\n", __func__);
 785                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL,
 786                                           v_OVERRIDE(1) | v_SLOPEBOOST(0) |
 787                                           v_TX_SYMON(1) | v_CLK_SYMON(1) |
 788                                           v_PREEMPHASIS(0));
 789                 if (hdmi_dev->tmdsclk > 340000000)
 790                         rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
 791                                                   v_SUP_TXLVL(9) |
 792                                                   v_SUP_CLKLVL(17));
 793                 else if (hdmi_dev->tmdsclk > 165000000)
 794                         rockchip_hdmiv2_write_phy(hdmi_dev,
 795                                                   PHYTX_VLEVCTRL,
 796                                                   v_SUP_TXLVL(14) |
 797                                                   v_SUP_CLKLVL(17));
 798                 else
 799                         rockchip_hdmiv2_write_phy(hdmi_dev,
 800                                                   PHYTX_VLEVCTRL,
 801                                                   v_SUP_TXLVL(18) |
 802                                                   v_SUP_CLKLVL(17));
 803         } else {
 804                 stat = v_OVERRIDE(1) | v_TX_SYMON(1) | v_CLK_SYMON(1) |
 805                        v_PREEMPHASIS(hdmi_dev->phy_table[i].pre_emphasis) |
 806                        v_SLOPEBOOST(hdmi_dev->phy_table[i].slopeboost);
 807                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL, stat);
 808
 809                 stat = v_SUP_CLKLVL(hdmi_dev->phy_table[i].clk_level) |
 810                        v_SUP_TXLVL(hdmi_dev->phy_table[i].data0_level);
 811                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL, stat);
 812         }
 813
 814         if (hdmi_dev->tmdsclk > 340000000)
 815                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
 816                                           v_TX_TERM(R50_OHMS));
 817         else
 818                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
 819                                           v_TX_TERM(R100_OHMS));
 820         /* rockchip_hdmiv2_write_phy(hdmi_dev, 0x05, 0x8000); */
 821         if (hdmi_dev->tmdsclk_ratio_change)
 822                 msleep(100);
 823         /* power on PHY */
 824         hdmi_writel(hdmi_dev, PHY_CONF0, 0x2e);
 825
 826         /* check if the PHY PLL is locked */
 827
 828         i = 0;
 829         while (i++ < PHY_TIMEOUT) {
 830                 if ((i % 10) == 0) {
 831                         stat = hdmi_readl(hdmi_dev, PHY_STAT0);
 832                         if (stat & m_PHY_LOCK)
 833                                 break;
 834                         usleep_range(1000, 2000);
 835                 }
 836         }
 837         if ((stat & m_PHY_LOCK) == 0) {
 838                 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
 839                 dev_err(hdmi_dev->hdmi->dev,
 840                         "PHY PLL not locked: PCLK_ON=%ld,TMDSCLK_ON=%ld\n",
 841                         (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
 842                 return -1;
 843         }
 844         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(0));
 845         return 0;
 846 }
 847
 848 static int rockchip_hdmiv2_video_framecomposer(struct hdmi *hdmi_drv,
 849                                                struct hdmi_video *vpara)
 850 {
 851         struct hdmi_dev *hdmi_dev = hdmi_drv->property->priv;
 852         int value, vsync_pol, hsync_pol, de_pol;
 853         struct hdmi_video_timing *timing = NULL;
 854         struct fb_videomode *mode = NULL;
 855         u32 sink_version, tmdsclk;
 856
 857         vsync_pol = hdmi_drv->lcdc->cur_screen->pin_vsync;
 858         hsync_pol = hdmi_drv->lcdc->cur_screen->pin_hsync;
 859         de_pol = (hdmi_drv->lcdc->cur_screen->pin_den == 0) ? 1 : 0;
 860
 861         hdmi_msk_reg(hdmi_dev, A_VIDPOLCFG,
 862                      m_DATAEN_POL | m_VSYNC_POL | m_HSYNC_POL,
 863                      v_DATAEN_POL(de_pol) |
 864                      v_VSYNC_POL(vsync_pol) |
 865                      v_HSYNC_POL(hsync_pol));
 866
 867         timing = (struct hdmi_video_timing *)hdmi_vic2timing(vpara->vic);
 868         if (!timing) {
 869                 dev_err(hdmi_drv->dev,
 870                         "[%s] not found vic %d\n", __func__, vpara->vic);
 871                 return -ENOENT;
 872         }
 873         mode = &timing->mode;
 874         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 875                 tmdsclk = mode->pixclock / 2;
 876         else if (vpara->format_3d == HDMI_3D_FRAME_PACKING)
 877                 tmdsclk = 2 * mode->pixclock;
 878         else
 879                 tmdsclk = mode->pixclock;
 880         if (vpara->color_output != HDMI_COLOR_YCBCR422) {
 881                 switch (vpara->color_output_depth) {
 882                 case 10:
 883                         tmdsclk += tmdsclk / 4;
 884                         break;
 885                 case 12:
 886                         tmdsclk += tmdsclk / 2;
 887                         break;
 888                 case 16:
 889                         tmdsclk += tmdsclk;
 890                         break;
 891                 case 8:
 892                 default:
 893                         break;
 894                 }
 895         } else if (vpara->color_output_depth > 12) {
 896                 /* YCbCr422 mode only support up to 12bit */
 897                 vpara->color_output_depth = 12;
 898         }
 899         if ((tmdsclk > 594000000) ||
 900             (tmdsclk > 340000000 &&
 901              tmdsclk > hdmi_drv->edid.maxtmdsclock)) {
 902                 pr_warn("out of max tmds clock, limit to 8bit\n");
 903                 vpara->color_output_depth = 8;
 904                 if (vpara->color_input == HDMI_COLOR_YCBCR420)
 905                         tmdsclk = mode->pixclock / 2;
 906                 else if (vpara->format_3d != HDMI_3D_FRAME_PACKING)
 907                         tmdsclk = mode->pixclock;
 908                 else
 909                         return -1;
 910         }
 911
 912         if ((tmdsclk > 340000000) ||
 913             (tmdsclk < 340000000 && hdmi_dev->tmdsclk > 340000000))
 914                 hdmi_dev->tmdsclk_ratio_change = true;
 915         else
 916                 hdmi_dev->tmdsclk_ratio_change = false;
 917
 918         hdmi_dev->tmdsclk = tmdsclk;
 919         if (vpara->format_3d == HDMI_3D_FRAME_PACKING)
 920                 hdmi_dev->pixelclk = 2 * mode->pixclock;
 921         else
 922                 hdmi_dev->pixelclk = mode->pixclock;
 923         hdmi_dev->pixelrepeat = timing->pixelrepeat;
 924         /* hdmi_dev->colordepth is used for find pll config.
 925          * For YCbCr422, tmdsclk is same on all color depth.
 926          */
 927         if (vpara->color_output == HDMI_COLOR_YCBCR422)
 928                 hdmi_dev->colordepth = 8;
 929         else
 930                 hdmi_dev->colordepth = vpara->color_output_depth;
 931         pr_info("pixel clk is %lu tmds clk is %u\n",
 932                 hdmi_dev->pixelclk, hdmi_dev->tmdsclk);
 933         /* Start/stop HDCP keepout window generation */
 934         hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 935                      m_FC_HDCP_KEEPOUT, v_FC_HDCP_KEEPOUT(1));
 936         if (hdmi_drv->edid.scdc_present == 1 && !hdmi_drv->uboot) {
 937                 if (tmdsclk > 340000000 ||
 938                     hdmi_drv->edid.lte_340mcsc_scramble) {
 939                         /* used for HDMI 2.0 TX */
 940                         mutex_lock(&hdmi_dev->ddc_lock);
 941                         rockchip_hdmiv2_scdc_init(hdmi_dev);
 942                         sink_version =
 943                         rockchip_hdmiv2_scdc_get_sink_version(hdmi_dev);
 944                         pr_info("sink scdc version is %d\n", sink_version);
 945                         sink_version = hdmi_drv->edid.hf_vsdb_version;
 946                         rockchip_hdmiv2_scdc_set_source_version(hdmi_dev,
 947                                                                 sink_version);
 948                         if (hdmi_drv->edid.rr_capable == 1)
 949                                 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 950                         rockchip_hdmiv2_scrambling_enable(hdmi_dev, 1);
 951                         mutex_unlock(&hdmi_dev->ddc_lock);
 952                 } else {
 953                         mutex_lock(&hdmi_dev->ddc_lock);
 954                         rockchip_hdmiv2_scdc_init(hdmi_dev);
 955                         rockchip_hdmiv2_scrambling_enable(hdmi_dev, 0);
 956                         mutex_unlock(&hdmi_dev->ddc_lock);
 957                 }
 958         } else {
 959                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 960                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
 961         }
 962
 963         hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 964                      m_FC_VSYNC_POL | m_FC_HSYNC_POL | m_FC_DE_POL |
 965                      m_FC_HDMI_DVI | m_FC_INTERLACE_MODE,
 966                      v_FC_VSYNC_POL(vsync_pol) | v_FC_HSYNC_POL(hsync_pol) |
 967                      v_FC_DE_POL(de_pol) | v_FC_HDMI_DVI(vpara->sink_hdmi) |
 968                      v_FC_INTERLACE_MODE(mode->vmode));
 969         if ((mode->vmode & FB_VMODE_INTERLACED) &&
 970             vpara->format_3d != HDMI_3D_FRAME_PACKING)
 971                 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 972                              m_FC_VBLANK, v_FC_VBLANK(1));
 973         else
 974                 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 975                              m_FC_VBLANK, v_FC_VBLANK(0));
 976
 977         value = mode->xres;
 978         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 979                 value = value / 2;
 980         hdmi_writel(hdmi_dev, FC_INHACTIV1, v_FC_HACTIVE1(value >> 8));
 981         hdmi_writel(hdmi_dev, FC_INHACTIV0, (value & 0xff));
 982
 983         if (vpara->format_3d == HDMI_3D_FRAME_PACKING) {
 984                 if (mode->vmode == 0)
 985                         value = 2 * mode->yres +
 986                                 mode->upper_margin +
 987                                 mode->lower_margin +
 988                                 mode->vsync_len;
 989                 else
 990                         value = 2 * mode->yres +
 991                                 3 * (mode->upper_margin +
 992                                      mode->lower_margin +
 993                                      mode->vsync_len) + 2;
 994         } else {
 995                 value = mode->yres;
 996         }
 997         hdmi_writel(hdmi_dev, FC_INVACTIV1, v_FC_VACTIVE1(value >> 8));
 998         hdmi_writel(hdmi_dev, FC_INVACTIV0, (value & 0xff));
 999
1000         value = mode->hsync_len + mode->left_margin + mode->right_margin;
1001         if (vpara->color_input == HDMI_COLOR_YCBCR420)
1002                 value = value / 2;
1003         hdmi_writel(hdmi_dev, FC_INHBLANK1, v_FC_HBLANK1(value >> 8));
1004         hdmi_writel(hdmi_dev, FC_INHBLANK0, (value & 0xff));
1005
1006         value = mode->vsync_len + mode->upper_margin + mode->lower_margin;
1007         hdmi_writel(hdmi_dev, FC_INVBLANK, (value & 0xff));
1008
1009         value = mode->right_margin;
1010         if (vpara->color_input == HDMI_COLOR_YCBCR420)
1011                 value = value / 2;
1012         hdmi_writel(hdmi_dev, FC_HSYNCINDELAY1, v_FC_HSYNCINDEAY1(value >> 8));
1013         hdmi_writel(hdmi_dev, FC_HSYNCINDELAY0, (value & 0xff));
1014
1015         value = mode->lower_margin;
1016         hdmi_writel(hdmi_dev, FC_VSYNCINDELAY, (value & 0xff));
1017
1018         value = mode->hsync_len;
1019         if (vpara->color_input == HDMI_COLOR_YCBCR420)
1020                 value = value / 2;
1021         hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH1, v_FC_HSYNCWIDTH1(value >> 8));
1022         hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH0, (value & 0xff));
1023
1024         value = mode->vsync_len;
1025         hdmi_writel(hdmi_dev, FC_VSYNCINWIDTH, (value & 0xff));
1026
1027         /* Set the control period minimum duration (min. of 12 pixel
1028          * clock cycles, refer to HDMI 1.4b specification)
1029          */
1030         hdmi_writel(hdmi_dev, FC_CTRLDUR, 12);
1031         hdmi_writel(hdmi_dev, FC_EXCTRLDUR, 32);
1032
1033         /* spacing < 256^2 * config / tmdsClock, spacing <= 50ms
1034          * worst case: tmdsClock == 25MHz => config <= 19
1035          */
1036         hdmi_writel(hdmi_dev, FC_EXCTRLSPAC,
1037                     (hdmi_dev->tmdsclk / 1000) * 50 / (256 * 512));
1038
1039         hdmi_writel(hdmi_dev, FC_PRCONF,
1040                     v_FC_PR_FACTOR(timing->pixelrepeat) |
1041                     v_FC_PR_FACTOR_OUT(timing->pixelrepeat - 1));
1042
1043         return 0;
1044 }
1045
1046 static int rockchip_hdmiv2_video_packetizer(struct hdmi_dev *hdmi_dev,
1047                                             struct hdmi_video *vpara)
1048 {
1049         unsigned char color_depth = COLOR_DEPTH_24BIT_DEFAULT;
1050         unsigned char output_select = 0;
1051         unsigned char remap_size = 0;
1052
1053         if (vpara->color_output == HDMI_COLOR_YCBCR422) {
1054                 switch (vpara->color_output_depth) {
1055                 case 8:
1056                         remap_size = YCC422_16BIT;
1057                         break;
1058                 case 10:
1059                         remap_size = YCC422_20BIT;
1060                         break;
1061                 case 12:
1062                         remap_size = YCC422_24BIT;
1063                         break;
1064                 default:
1065                         remap_size = YCC422_16BIT;
1066                         break;
1067                 }
1068
1069                 output_select = OUT_FROM_YCC422_REMAP;
1070                 /*Config remap size for the different color Depth*/
1071                 hdmi_msk_reg(hdmi_dev, VP_REMAP,
1072                              m_YCC422_SIZE, v_YCC422_SIZE(remap_size));
1073         } else {
1074                 switch (vpara->color_output_depth) {
1075                 case 10:
1076                         color_depth = COLOR_DEPTH_30BIT;
1077                         output_select = OUT_FROM_PIXEL_PACKING;
1078                         break;
1079                 case 12:
1080                         color_depth = COLOR_DEPTH_36BIT;
1081                         output_select = OUT_FROM_PIXEL_PACKING;
1082                         break;
1083                 case 16:
1084                         color_depth = COLOR_DEPTH_48BIT;
1085                         output_select = OUT_FROM_PIXEL_PACKING;
1086                         break;
1087                 case 8:
1088                 default:
1089                         color_depth = COLOR_DEPTH_24BIT_DEFAULT;
1090                         output_select = OUT_FROM_8BIT_BYPASS;
1091                         break;
1092                 }
1093         }
1094         /*Config Color Depth*/
1095         hdmi_msk_reg(hdmi_dev, VP_PR_CD,
1096                      m_COLOR_DEPTH, v_COLOR_DEPTH(color_depth));
1097         /*Config pixel repettion*/
1098         hdmi_msk_reg(hdmi_dev, VP_PR_CD, m_DESIRED_PR_FACTOR,
1099                      v_DESIRED_PR_FACTOR(hdmi_dev->pixelrepeat - 1));
1100         if (hdmi_dev->pixelrepeat > 1)
1101                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1102                              m_PIXEL_REPET_EN | m_BYPASS_SEL,
1103                              v_PIXEL_REPET_EN(1) | v_BYPASS_SEL(0));
1104         else
1105                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1106                              m_PIXEL_REPET_EN | m_BYPASS_SEL,
1107                              v_PIXEL_REPET_EN(0) | v_BYPASS_SEL(1));
1108
1109         /*config output select*/
1110         if (output_select == OUT_FROM_PIXEL_PACKING) { /* pixel packing */
1111                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1112                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1113                              m_YCC422_EN | m_OUTPUT_SEL,
1114                              v_BYPASS_EN(0) | v_PIXEL_PACK_EN(1) |
1115                              v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
1116         } else if (output_select == OUT_FROM_YCC422_REMAP) { /* YCC422 */
1117                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1118                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1119                              m_YCC422_EN | m_OUTPUT_SEL,
1120                              v_BYPASS_EN(0) | v_PIXEL_PACK_EN(0) |
1121                              v_YCC422_EN(1) | v_OUTPUT_SEL(output_select));
1122         } else if (output_select == OUT_FROM_8BIT_BYPASS ||
1123                    output_select == 3) { /* bypass */
1124                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1125                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1126                              m_YCC422_EN | m_OUTPUT_SEL,
1127                              v_BYPASS_EN(1) | v_PIXEL_PACK_EN(0) |
1128                              v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
1129         }
1130
1131 #if defined(HDMI_VIDEO_STUFFING)
1132         /* YCC422 and pixel packing stuffing*/
1133         hdmi_msk_reg(hdmi_dev, VP_STUFF, m_PR_STUFFING, v_PR_STUFFING(1));
1134         hdmi_msk_reg(hdmi_dev, VP_STUFF,
1135                      m_YCC422_STUFFING | m_PP_STUFFING,
1136                      v_YCC422_STUFFING(1) | v_PP_STUFFING(1));
1137 #endif
1138         return 0;
1139 }
1140
1141 static int rockchip_hdmiv2_video_sampler(struct hdmi_dev *hdmi_dev,
1142                                          struct hdmi_video *vpara)
1143 {
1144         int map_code = 0;
1145
1146         if (vpara->color_input == HDMI_COLOR_YCBCR422) {
1147                 /* YCC422 mapping is discontinued - only map 1 is supported */
1148                 switch (vpara->color_output_depth) {
1149                 case 8:
1150                         map_code = VIDEO_YCBCR422_8BIT;
1151                         break;
1152                 case 10:
1153                         map_code = VIDEO_YCBCR422_10BIT;
1154                         break;
1155                 case 12:
1156                         map_code = VIDEO_YCBCR422_12BIT;
1157                         break;
1158                 default:
1159                         map_code = VIDEO_YCBCR422_8BIT;
1160                         break;
1161                 }
1162         } else if (vpara->color_input == HDMI_COLOR_YCBCR420 ||
1163                    vpara->color_input == HDMI_COLOR_YCBCR444) {
1164                 switch (vpara->color_output_depth) {
1165                 case 10:
1166                         map_code = VIDEO_YCBCR444_10BIT;
1167                         break;
1168                 case 12:
1169                         map_code = VIDEO_YCBCR444_12BIT;
1170                         break;
1171                 case 16:
1172                         map_code = VIDEO_YCBCR444_16BIT;
1173                         break;
1174                 case 8:
1175                 default:
1176                         map_code = VIDEO_YCBCR444_8BIT;
1177                         break;
1178                 }
1179         } else {
1180                 switch (vpara->color_output_depth) {
1181                 case 10:
1182                         map_code = VIDEO_RGB444_10BIT;
1183                         break;
1184                 case 12:
1185                         map_code = VIDEO_RGB444_12BIT;
1186                         break;
1187                 case 16:
1188                         map_code = VIDEO_RGB444_16BIT;
1189                         break;
1190                 case 8:
1191                 default:
1192                         map_code = VIDEO_RGB444_8BIT;
1193                         break;
1194                 }
1195                 map_code += (vpara->color_input == HDMI_COLOR_YCBCR444) ?
1196                             8 : 0;
1197         }
1198
1199         /* Set Data enable signal from external
1200          * and set video sample input mapping
1201          */
1202         hdmi_msk_reg(hdmi_dev, TX_INVID0,
1203                      m_INTERNAL_DE_GEN | m_VIDEO_MAPPING,
1204                      v_INTERNAL_DE_GEN(0) | v_VIDEO_MAPPING(map_code));
1205
1206 #if defined(HDMI_VIDEO_STUFFING)
1207         hdmi_writel(hdmi_dev, TX_GYDATA0, 0x00);
1208         hdmi_writel(hdmi_dev, TX_GYDATA1, 0x00);
1209         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1210                      m_GYDATA_STUFF, v_GYDATA_STUFF(1));
1211         hdmi_writel(hdmi_dev, TX_RCRDATA0, 0x00);
1212         hdmi_writel(hdmi_dev, TX_RCRDATA1, 0x00);
1213         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1214                      m_RCRDATA_STUFF, v_RCRDATA_STUFF(1));
1215         hdmi_writel(hdmi_dev, TX_BCBDATA0, 0x00);
1216         hdmi_writel(hdmi_dev, TX_BCBDATA1, 0x00);
1217         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1218                      m_BCBDATA_STUFF, v_BCBDATA_STUFF(1));
1219 #endif
1220         return 0;
1221 }
1222
1223 static const char coeff_csc[][24] = {
1224                 /*   G          R           B           Bias
1225                  *   A1    |    A2     |    A3     |    A4    |
1226                  *   B1    |    B2     |    B3     |    B4    |
1227                  *   C1    |    C2     |    C3     |    C4    |
1228                  */
1229         {       /* CSC_BYPASS */
1230                 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
1231                 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
1232                 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
1233         },
1234         {       /* CSC_RGB_0_255_TO_RGB_16_235_8BIT */
1235                 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,         /*G*/
1236                 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x00, 0x40,         /*R*/
1237                 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x00, 0x40,         /*B*/
1238         },
1239         {       /* CSC_RGB_0_255_TO_RGB_16_235_10BIT */
1240                 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,         /*G*/
1241                 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x01, 0x00,         /*R*/
1242                 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x01, 0x00,         /*B*/
1243         },
1244         {       /* CSC_RGB_0_255_TO_ITU601_16_235_8BIT */
1245                 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x00, 0x40,         /*Y*/
1246                 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x02, 0x00,         /*Cr*/
1247                 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x02, 0x00,         /*Cb*/
1248         },
1249         {       /* CSC_RGB_0_255_TO_ITU601_16_235_10BIT */
1250                 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x01, 0x00,         /*Y*/
1251                 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x08, 0x00,         /*Cr*/
1252                 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x08, 0x00,         /*Cb*/
1253         },
1254         {       /* CSC_RGB_0_255_TO_ITU709_16_235_8BIT */
1255                 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x00, 0x40,         /*Y*/
1256                 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x02, 0x00,         /*Cr*/
1257                 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x02, 0x00,         /*Cb*/
1258         },
1259         {       /* CSC_RGB_0_255_TO_ITU709_16_235_10BIT */
1260                 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x01, 0x00,         /*Y*/
1261                 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x08, 0x00,         /*Cr*/
1262                 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x08, 0x00,         /*Cb*/
1263         },
1264                 /* Y            Cr          Cb          Bias */
1265         {       /* CSC_ITU601_16_235_TO_RGB_0_255_8BIT */
1266                 0x20, 0x00, 0x69, 0x26, 0x74, 0xfd, 0x01, 0x0e,         /*G*/
1267                 0x20, 0x00, 0x2c, 0xdd, 0x00, 0x00, 0x7e, 0x9a,         /*R*/
1268                 0x20, 0x00, 0x00, 0x00, 0x38, 0xb4, 0x7e, 0x3b,         /*B*/
1269         },
1270         {       /* CSC_ITU709_16_235_TO_RGB_0_255_8BIT */
1271                 0x20, 0x00, 0x71, 0x06, 0x7a, 0x02, 0x00, 0xa7,         /*G*/
1272                 0x20, 0x00, 0x32, 0x64, 0x00, 0x00, 0x7e, 0x6d,         /*R*/
1273                 0x20, 0x00, 0x00, 0x00, 0x3b, 0x61, 0x7e, 0x25,         /*B*/
1274         },
1275 };
1276
1277 static int rockchip_hdmiv2_video_csc(struct hdmi_dev *hdmi_dev,
1278                                      struct hdmi_video *vpara)
1279 {
1280         int i, mode, interpolation, decimation, csc_scale = 0;
1281         const char *coeff = NULL;
1282         unsigned char color_depth = 0;
1283
1284         if (vpara->color_input == vpara->color_output) {
1285                 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1286                              m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(0));
1287                 return 0;
1288         }
1289
1290         if (vpara->color_input == HDMI_COLOR_YCBCR422 &&
1291             vpara->color_output != HDMI_COLOR_YCBCR422 &&
1292             vpara->color_output != HDMI_COLOR_YCBCR420) {
1293                 interpolation = 1;
1294                 hdmi_msk_reg(hdmi_dev, CSC_CFG,
1295                              m_CSC_INTPMODE, v_CSC_INTPMODE(interpolation));
1296         }
1297
1298         if ((vpara->color_input == HDMI_COLOR_RGB_0_255 ||
1299              vpara->color_input == HDMI_COLOR_YCBCR444) &&
1300              vpara->color_output == HDMI_COLOR_YCBCR422) {
1301                 decimation = 1;
1302                 hdmi_msk_reg(hdmi_dev, CSC_CFG,
1303                              m_CSC_DECIMODE, v_CSC_DECIMODE(decimation));
1304         }
1305
1306         mode = CSC_BYPASS;
1307         csc_scale = 0;
1308
1309         switch (vpara->vic) {
1310         case HDMI_720X480I_60HZ_4_3:
1311         case HDMI_720X576I_50HZ_4_3:
1312         case HDMI_720X480P_60HZ_4_3:
1313         case HDMI_720X576P_50HZ_4_3:
1314         case HDMI_720X480I_60HZ_16_9:
1315         case HDMI_720X576I_50HZ_16_9:
1316         case HDMI_720X480P_60HZ_16_9:
1317         case HDMI_720X576P_50HZ_16_9:
1318                 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
1319                     vpara->color_output >= HDMI_COLOR_YCBCR444) {
1320                         mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
1321                         csc_scale = 0;
1322                 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
1323                            vpara->color_output == HDMI_COLOR_RGB_0_255) {
1324                         mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT;
1325                         csc_scale = 1;
1326                 }
1327                 break;
1328         default:
1329                 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
1330                     vpara->color_output >= HDMI_COLOR_YCBCR444) {
1331                         mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
1332                         csc_scale = 0;
1333                 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
1334                            vpara->color_output == HDMI_COLOR_RGB_0_255) {
1335                         mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT;
1336                         csc_scale = 1;
1337                 }
1338                 break;
1339         }
1340
1341         if ((vpara->color_input == HDMI_COLOR_RGB_0_255) &&
1342             (vpara->color_output == HDMI_COLOR_RGB_16_235)) {
1343                 mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
1344                 csc_scale = 0;
1345         }
1346
1347         switch (vpara->color_output_depth) {
1348         case 10:
1349                 color_depth = COLOR_DEPTH_30BIT;
1350                 mode += 1;
1351                 break;
1352         case 12:
1353                 color_depth = COLOR_DEPTH_36BIT;
1354                 mode += 2;
1355                 break;
1356         case 16:
1357                 color_depth = COLOR_DEPTH_48BIT;
1358                 mode += 3;
1359                 break;
1360         case 8:
1361         default:
1362                 color_depth = COLOR_DEPTH_24BIT;
1363                 break;
1364         }
1365
1366         coeff = coeff_csc[mode];
1367         for (i = 0; i < 24; i++)
1368                 hdmi_writel(hdmi_dev, CSC_COEF_A1_MSB + i, coeff[i]);
1369
1370         hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1371                      m_CSC_SCALE, v_CSC_SCALE(csc_scale));
1372         /*config CSC_COLOR_DEPTH*/
1373         hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1374                      m_CSC_COLOR_DEPTH, v_CSC_COLOR_DEPTH(color_depth));
1375
1376         /* enable CSC */
1377         hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1378                      m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(1));
1379
1380         return 0;
1381 }
1382
1383 static int hdmi_dev_detect_hotplug(struct hdmi *hdmi)
1384 {
1385         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1386         u32 value;
1387
1388         value = hdmi_readl(hdmi_dev, PHY_STAT0);
1389         HDMIDBG("[%s] reg%x value %02x\n", __func__, PHY_STAT0, value);
1390         if (value & m_PHY_HPD)
1391                 return HDMI_HPD_ACTIVED;
1392
1393         return HDMI_HPD_REMOVED;
1394 }
1395
1396 static int hdmi_dev_read_edid(struct hdmi *hdmi, int block, unsigned char *buff)
1397 {
1398         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1399         int i = 0, n = 0, index = 0, ret = -1, trytime = 5;
1400         int offset = (block % 2) * 0x80;
1401         int interrupt = 0;
1402
1403         HDMIDBG("[%s] block %d\n", __func__, block);
1404
1405         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
1406
1407         /* Set DDC I2C CLK which divided from DDC_CLK to 100KHz. */
1408         rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
1409
1410         /* Enable I2C interrupt for reading edid */
1411         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);
1412
1413         hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_EDID_ADDR);
1414         hdmi_writel(hdmi_dev, I2CM_SEGADDR, DDC_I2C_SEG_ADDR);
1415         hdmi_writel(hdmi_dev, I2CM_SEGPTR, block / 2);
1416         for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
1417                 for (trytime = 0; trytime < 5; trytime++) {
1418                         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset + 8 * n);
1419                         /* enable extend sequential read operation */
1420                         if (block == 0)
1421                                 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1422                                              m_I2CM_RD8, v_I2CM_RD8(1));
1423                         else
1424                                 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1425                                              m_I2CM_RD8_EXT,
1426                                              v_I2CM_RD8_EXT(1));
1427
1428                         i = 20;
1429                         while (i--) {
1430                                 usleep_range(900, 1000);
1431                                 interrupt = hdmi_readl(hdmi_dev,
1432                                                        IH_I2CM_STAT0);
1433                                 if (interrupt)
1434                                         hdmi_writel(hdmi_dev,
1435                                                     IH_I2CM_STAT0, interrupt);
1436
1437                                 if (interrupt &
1438                                     (m_SCDC_READREQ | m_I2CM_DONE |
1439                                      m_I2CM_ERROR))
1440                                         break;
1441                         }
1442
1443                         if (interrupt & m_I2CM_DONE) {
1444                                 for (index = 0; index < 8; index++)
1445                                         buff[8 * n + index] =
1446                                                 hdmi_readl(hdmi_dev,
1447                                                            I2CM_READ_BUFF0 +
1448                                                            index);
1449
1450                                 if (n == HDMI_EDID_BLOCK_SIZE / 8 - 1) {
1451                                         ret = 0;
1452                                         goto exit;
1453                                 }
1454                                 break;
1455                         } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
1456                                 dev_err(hdmi->dev,
1457                                         "[%s] edid read %d error\n",
1458                                         __func__, offset + 8 * n);
1459                         }
1460                 }
1461                 if (trytime == 5) {
1462                         dev_err(hdmi->dev,
1463                                 "[%s] edid read error\n", __func__);
1464                         break;
1465                 }
1466         }
1467
1468 exit:
1469         /* Disable I2C interrupt */
1470         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
1471         return ret;
1472 }
1473
1474 static void hdmi_dev_config_avi(struct hdmi_dev *hdmi_dev,
1475                                 struct hdmi_video *vpara)
1476 {
1477         unsigned char colorimetry, ext_colorimetry = 0, aspect_ratio, y1y0;
1478         unsigned char rgb_quan_range = AVI_QUANTIZATION_RANGE_DEFAULT;
1479
1480         hdmi_msk_reg(hdmi_dev, FC_DATAUTO3, m_AVI_AUTO, v_AVI_AUTO(0));
1481         hdmi_msk_reg(hdmi_dev, IH_FC_STAT1,
1482                      m_AVI_INFOFRAME, v_AVI_INFOFRAME(1));
1483         /* Set AVI infoFrame Data byte1 */
1484         if (vpara->color_output == HDMI_COLOR_YCBCR444)
1485                 y1y0 = AVI_COLOR_MODE_YCBCR444;
1486         else if (vpara->color_output == HDMI_COLOR_YCBCR422)
1487                 y1y0 = AVI_COLOR_MODE_YCBCR422;
1488         else if (vpara->color_output == HDMI_COLOR_YCBCR420)
1489                 y1y0 = AVI_COLOR_MODE_YCBCR420;
1490         else
1491                 y1y0 = AVI_COLOR_MODE_RGB;
1492
1493         hdmi_msk_reg(hdmi_dev, FC_AVICONF0,
1494                      m_FC_ACTIV_FORMAT | m_FC_RGC_YCC,
1495                      v_FC_RGC_YCC(y1y0) | v_FC_ACTIV_FORMAT(1));
1496
1497         /* Set AVI infoFrame Data byte2 */
1498         switch (vpara->vic) {
1499         case HDMI_720X480I_60HZ_4_3:
1500         case HDMI_720X576I_50HZ_4_3:
1501         case HDMI_720X480P_60HZ_4_3:
1502         case HDMI_720X576P_50HZ_4_3:
1503                 aspect_ratio = AVI_CODED_FRAME_ASPECT_4_3;
1504                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1505                         colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1506                 break;
1507         case HDMI_720X480I_60HZ_16_9:
1508         case HDMI_720X576I_50HZ_16_9:
1509         case HDMI_720X480P_60HZ_16_9:
1510         case HDMI_720X576P_50HZ_16_9:
1511                 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1512                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1513                         colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1514                 break;
1515         default:
1516                 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1517                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1518                         colorimetry = AVI_COLORIMETRY_ITU709;
1519         }
1520
1521         if (vpara->colorimetry > HDMI_COLORIMETRY_ITU709) {
1522                 colorimetry = AVI_COLORIMETRY_EXTENDED;
1523                 ext_colorimetry = vpara->colorimetry;
1524         } else if (vpara->color_output == HDMI_COLOR_RGB_16_235 ||
1525                  vpara->color_output == HDMI_COLOR_RGB_0_255) {
1526                 colorimetry = AVI_COLORIMETRY_NO_DATA;
1527         } else if (vpara->colorimetry != HDMI_COLORIMETRY_NO_DATA) {
1528                 colorimetry = vpara->colorimetry;
1529         }
1530
1531         hdmi_writel(hdmi_dev, FC_AVICONF1,
1532                     v_FC_COLORIMETRY(colorimetry) |
1533                     v_FC_PIC_ASPEC_RATIO(aspect_ratio) |
1534                     v_FC_ACT_ASPEC_RATIO(ACTIVE_ASPECT_RATE_DEFAULT));
1535
1536         /* Set AVI infoFrame Data byte3 */
1537         hdmi_msk_reg(hdmi_dev, FC_AVICONF2,
1538                      m_FC_EXT_COLORIMETRY | m_FC_QUAN_RANGE,
1539                      v_FC_EXT_COLORIMETRY(ext_colorimetry) |
1540                      v_FC_QUAN_RANGE(rgb_quan_range));
1541
1542         /* Set AVI infoFrame Data byte4 */
1543         if ((vpara->vic > 92 && vpara->vic < 96) ||
1544             (vpara->vic == 98) ||
1545             (vpara->vic & HDMI_VIDEO_DMT) ||
1546             (vpara->vic & HDMI_VIDEO_DISCRETE_VR))
1547                 hdmi_writel(hdmi_dev, FC_AVIVID, 0);
1548         else
1549                 hdmi_writel(hdmi_dev, FC_AVIVID, vpara->vic & 0xff);
1550         /* Set AVI infoFrame Data byte5 */
1551         hdmi_msk_reg(hdmi_dev, FC_AVICONF3, m_FC_YQ | m_FC_CN,
1552                      v_FC_YQ(YQ_LIMITED_RANGE) | v_FC_CN(CN_GRAPHICS));
1553         hdmi_msk_reg(hdmi_dev, FC_DATAUTO3, m_AVI_AUTO, v_AVI_AUTO(1));
1554 }
1555
1556 static int hdmi_dev_config_vsi(struct hdmi *hdmi,
1557                                unsigned char vic_3d, unsigned char format)
1558 {
1559         int i = 0, id = 0x000c03;
1560         unsigned char data[3] = {0};
1561
1562         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1563
1564         HDMIDBG("[%s] vic %d format %d.\n", __func__, vic_3d, format);
1565
1566         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(0));
1567         hdmi_writel(hdmi_dev, FC_VSDIEEEID2, id & 0xff);
1568         hdmi_writel(hdmi_dev, FC_VSDIEEEID1, (id >> 8) & 0xff);
1569         hdmi_writel(hdmi_dev, FC_VSDIEEEID0, (id >> 16) & 0xff);
1570
1571         data[0] = format << 5;  /* PB4 --HDMI_Video_Format */
1572         switch (format) {
1573         case HDMI_VIDEO_FORMAT_4KX2K:
1574                 data[1] = vic_3d;       /* PB5--HDMI_VIC */
1575                 data[2] = 0;
1576                 break;
1577         case HDMI_VIDEO_FORMAT_3D:
1578                 data[1] = vic_3d << 4;  /* PB5--3D_Structure field */
1579                 data[2] = 0;            /* PB6--3D_Ext_Data field */
1580                 break;
1581         default:
1582                 data[1] = 0;
1583                 data[2] = 0;
1584                 break;
1585         }
1586
1587         for (i = 0; i < 3; i++)
1588                 hdmi_writel(hdmi_dev, FC_VSDPAYLOAD0 + i, data[i]);
1589         hdmi_writel(hdmi_dev, FC_VSDSIZE, 0x6);
1590
1591         hdmi_writel(hdmi_dev, FC_DATAUTO1, 0);
1592         hdmi_writel(hdmi_dev, FC_DATAUTO2, 0x11);
1593         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(1));
1594         return 0;
1595 }
1596
1597 static int hdmi_dev_config_spd(struct hdmi *hdmi, const char *vendor,
1598                                const char *product, char deviceinfo)
1599 {
1600         struct hdmi_dev *hdmi_dev;
1601         int i, len;
1602
1603         if (!hdmi || !vendor || !product)
1604                 return -1;
1605         hdmi_dev = hdmi->property->priv;
1606
1607         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_SPD_AUTO, v_SPD_AUTO(0));
1608         len = strlen(vendor);
1609         for (i = 0; i < 8; i++) {
1610                 if (i < len)
1611                         hdmi_writel(hdmi_dev, FC_SPDVENDORNAME0 + i,
1612                                     vendor[i]);
1613                 else
1614                         hdmi_writel(hdmi_dev, FC_SPDVENDORNAME0 + i,
1615                                     0);
1616         }
1617         len = strlen(product);
1618         for (i = 0; i < 16; i++) {
1619                 if (i < len)
1620                         hdmi_writel(hdmi_dev, FC_SPDPRODUCTNAME0 + i,
1621                                     product[i]);
1622                 else
1623                         hdmi_writel(hdmi_dev, FC_SPDPRODUCTNAME0 + i,
1624                                     0);
1625         }
1626         hdmi_writel(hdmi_dev, FC_SPDDEVICEINF, deviceinfo);
1627         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_SPD_AUTO, v_SPD_AUTO(1));
1628         return 0;
1629 }
1630
1631 static int hdmi_dev_config_video(struct hdmi *hdmi, struct hdmi_video *vpara)
1632 {
1633         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1634
1635         HDMIDBG("%s vic %d 3dformat %d color mode %d color depth %d\n",
1636                 __func__, vpara->vic, vpara->format_3d,
1637                 vpara->color_output, vpara->color_output_depth);
1638
1639         if (hdmi_dev->soctype == HDMI_SOC_RK3288)
1640                 vpara->color_input = HDMI_COLOR_RGB_0_255;
1641
1642         if (!hdmi->uboot) {
1643                 /* before configure video, we power off phy */
1644                 if (hdmi_dev->soctype != HDMI_SOC_RK322X) {
1645                         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1646                                      m_PDDQ_SIG | m_TXPWRON_SIG,
1647                                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1648                 } else {
1649                         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1650                                      m_ENHPD_RXSENSE_SIG,
1651                                      v_ENHPD_RXSENSE_SIG(1));
1652                         regmap_write(hdmi_dev->grf_base,
1653                                      RK322X_GRF_SOC_CON2,
1654                                      RK322X_PLL_POWER_DOWN);
1655                 }
1656                 /* force output blue */
1657                 if (vpara->color_output == HDMI_COLOR_RGB_0_255) {
1658                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x00);       /*R*/
1659                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x00);       /*G*/
1660                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x00);       /*B*/
1661                 } else if (vpara->color_output == HDMI_COLOR_RGB_16_235) {
1662                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x10);       /*R*/
1663                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10);       /*G*/
1664                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x10);       /*B*/
1665                 } else {
1666                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x80);       /*Cr*/
1667                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10);       /*Y*/
1668                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x80);       /*Cb*/
1669                 }
1670                 hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1671                              m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1672                 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1673         }
1674
1675         if (rockchip_hdmiv2_video_framecomposer(hdmi, vpara) < 0)
1676                 return -1;
1677
1678         if (rockchip_hdmiv2_video_packetizer(hdmi_dev, vpara) < 0)
1679                 return -1;
1680         /* Color space convert */
1681         if (rockchip_hdmiv2_video_csc(hdmi_dev, vpara) < 0)
1682                 return -1;
1683         if (rockchip_hdmiv2_video_sampler(hdmi_dev, vpara) < 0)
1684                 return -1;
1685
1686         if (vpara->sink_hdmi == OUTPUT_HDMI) {
1687                 hdmi_dev_config_avi(hdmi_dev, vpara);
1688                 hdmi_dev_config_spd(hdmi, hdmi_dev->vendor_name,
1689                                     hdmi_dev->product_name,
1690                                     hdmi_dev->deviceinfo);
1691                 if (vpara->format_3d != HDMI_3D_NONE) {
1692                         hdmi_dev_config_vsi(hdmi,
1693                                             vpara->format_3d,
1694                                             HDMI_VIDEO_FORMAT_3D);
1695                 } else if ((vpara->vic > 92 && vpara->vic < 96) ||
1696                          (vpara->vic == 98)) {
1697                         vpara->vic = (vpara->vic == 98) ?
1698                                      4 : (96 - vpara->vic);
1699                         hdmi_dev_config_vsi(hdmi,
1700                                             vpara->vic,
1701                                             HDMI_VIDEO_FORMAT_4KX2K);
1702                 } else {
1703                         hdmi_dev_config_vsi(hdmi,
1704                                             vpara->vic,
1705                                             HDMI_VIDEO_FORMAT_NORMAL);
1706                 }
1707                 dev_info(hdmi->dev, "[%s] success output HDMI.\n", __func__);
1708         } else {
1709                 dev_info(hdmi->dev, "[%s] success output DVI.\n", __func__);
1710         }
1711
1712         if (!hdmi->uboot)
1713                 rockchip_hdmiv2_config_phy(hdmi_dev);
1714         else
1715                 hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(0));
1716         return 0;
1717 }
1718
1719 static void hdmi_dev_config_aai(struct hdmi_dev *hdmi_dev,
1720                                 struct hdmi_audio *audio)
1721 {
1722         /* Refer to CEA861-E Audio infoFrame
1723          * Set both Audio Channel Count and Audio Coding
1724          * Type Refer to Stream Head for HDMI
1725          */
1726         hdmi_msk_reg(hdmi_dev, FC_AUDICONF0,
1727                      m_FC_CHN_CNT | m_FC_CODING_TYPE,
1728                      v_FC_CHN_CNT(audio->channel - 1) | v_FC_CODING_TYPE(0));
1729
1730         /* Set both Audio Sample Size and Sample Frequency
1731          * Refer to Stream Head for HDMI
1732          */
1733         hdmi_msk_reg(hdmi_dev, FC_AUDICONF1,
1734                      m_FC_SAMPLE_SIZE | m_FC_SAMPLE_FREQ,
1735                      v_FC_SAMPLE_SIZE(0) | v_FC_SAMPLE_FREQ(0));
1736
1737         /* Set Channel Allocation */
1738         hdmi_writel(hdmi_dev, FC_AUDICONF2, 0x00);
1739
1740         /* Set LFEPBLDOWN-MIX INH and LSV */
1741         hdmi_writel(hdmi_dev, FC_AUDICONF3, 0x00);
1742 }
1743
1744 static int hdmi_dev_config_audio(struct hdmi *hdmi, struct hdmi_audio *audio)
1745 {
1746         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1747         int word_length = 0, channel = 0, mclk_fs;
1748         unsigned int N = 0, CTS = 0;
1749         int rate = 0;
1750         char design_id;
1751
1752         HDMIDBG("%s\n", __func__);
1753
1754         if (audio->channel < 3)
1755                 channel = I2S_CHANNEL_1_2;
1756         else if (audio->channel < 5)
1757                 channel = I2S_CHANNEL_3_4;
1758         else if (audio->channel < 7)
1759                 channel = I2S_CHANNEL_5_6;
1760         else
1761                 channel = I2S_CHANNEL_7_8;
1762
1763         switch (audio->rate) {
1764         case HDMI_AUDIO_FS_32000:
1765                 mclk_fs = FS_128;
1766                 rate = AUDIO_32K;
1767                 if (hdmi_dev->tmdsclk >= 594000000)
1768                         N = N_32K_HIGHCLK;
1769                 else if (hdmi_dev->tmdsclk >= 297000000)
1770                         N = N_32K_MIDCLK;
1771                 else
1772                         N = N_32K_LOWCLK;
1773                 /*div a num to avoid the value is exceed 2^32(int)*/
1774                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 32);
1775                 break;
1776         case HDMI_AUDIO_FS_44100:
1777                 mclk_fs = FS_128;
1778                 rate = AUDIO_441K;
1779                 if (hdmi_dev->tmdsclk >= 594000000)
1780                         N = N_441K_HIGHCLK;
1781                 else if (hdmi_dev->tmdsclk >= 297000000)
1782                         N = N_441K_MIDCLK;
1783                 else
1784                         N = N_441K_LOWCLK;
1785
1786                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 100, 441);
1787                 break;
1788         case HDMI_AUDIO_FS_48000:
1789                 mclk_fs = FS_128;
1790                 rate = AUDIO_48K;
1791                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1792                         N = N_48K_HIGHCLK;
1793                 else if (hdmi_dev->tmdsclk >= 297000000)
1794                         N = N_48K_MIDCLK;
1795                 else
1796                         N = N_48K_LOWCLK;
1797
1798                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 48);
1799                 break;
1800         case HDMI_AUDIO_FS_88200:
1801                 mclk_fs = FS_128;
1802                 rate = AUDIO_882K;
1803                 if (hdmi_dev->tmdsclk >= 594000000)
1804                         N = N_882K_HIGHCLK;
1805                 else if (hdmi_dev->tmdsclk >= 297000000)
1806                         N = N_882K_MIDCLK;
1807                 else
1808                         N = N_882K_LOWCLK;
1809
1810                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 100, 882);
1811                 break;
1812         case HDMI_AUDIO_FS_96000:
1813                 mclk_fs = FS_128;
1814                 rate = AUDIO_96K;
1815                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1816                         N = N_96K_HIGHCLK;
1817                 else if (hdmi_dev->tmdsclk >= 297000000)
1818                         N = N_96K_MIDCLK;
1819                 else
1820                         N = N_96K_LOWCLK;
1821
1822                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 96);
1823                 break;
1824         case HDMI_AUDIO_FS_176400:
1825                 mclk_fs = FS_128;
1826                 rate = AUDIO_1764K;
1827                 if (hdmi_dev->tmdsclk >= 594000000)
1828                         N = N_1764K_HIGHCLK;
1829                 else if (hdmi_dev->tmdsclk >= 297000000)
1830                         N = N_1764K_MIDCLK;
1831                 else
1832                         N = N_1764K_LOWCLK;
1833
1834                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 100, 1764);
1835                 break;
1836         case HDMI_AUDIO_FS_192000:
1837                 mclk_fs = FS_128;
1838                 rate = AUDIO_192K;
1839                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1840                         N = N_192K_HIGHCLK;
1841                 else if (hdmi_dev->tmdsclk >= 297000000)
1842                         N = N_192K_MIDCLK;
1843                 else
1844                         N = N_192K_LOWCLK;
1845
1846                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 192);
1847                 break;
1848         default:
1849                 dev_err(hdmi_dev->hdmi->dev,
1850                         "[%s] not support such sample rate %d\n",
1851                         __func__, audio->rate);
1852                 return -ENOENT;
1853         }
1854
1855         switch (audio->word_length) {
1856         case HDMI_AUDIO_WORD_LENGTH_16bit:
1857                 word_length = I2S_16BIT_SAMPLE;
1858                 break;
1859         case HDMI_AUDIO_WORD_LENGTH_20bit:
1860                 word_length = I2S_20BIT_SAMPLE;
1861                 break;
1862         case HDMI_AUDIO_WORD_LENGTH_24bit:
1863                 word_length = I2S_24BIT_SAMPLE;
1864                 break;
1865         default:
1866                 word_length = I2S_16BIT_SAMPLE;
1867         }
1868
1869         HDMIDBG("rate = %d, tmdsclk = %u, N = %d, CTS = %d\n",
1870                 audio->rate, hdmi_dev->tmdsclk, N, CTS);
1871         /* more than 2 channels => layout 1 else layout 0 */
1872         hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1873                      m_AUD_PACK_LAYOUT,
1874                      v_AUD_PACK_LAYOUT((audio->channel > 2) ? 1 : 0));
1875
1876         if (hdmi_dev->audiosrc == HDMI_AUDIO_SRC_SPDIF) {
1877                 mclk_fs = FS_128;
1878                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1879                              m_I2S_SEL, v_I2S_SEL(AUDIO_SPDIF_GPA));
1880                 hdmi_msk_reg(hdmi_dev, AUD_SPDIF1,
1881                              m_SET_NLPCM | m_SPDIF_WIDTH,
1882                              v_SET_NLPCM(PCM_LINEAR) |
1883                              v_SPDIF_WIDTH(word_length));
1884                 /*Mask fifo empty and full int and reset fifo*/
1885                 hdmi_msk_reg(hdmi_dev, AUD_SPDIFINT,
1886                              m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1887                              v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1888                 hdmi_msk_reg(hdmi_dev, AUD_SPDIF0,
1889                              m_SW_SAUD_FIFO_RST, v_SW_SAUD_FIFO_RST(1));
1890         } else {
1891                 /*Mask fifo empty and full int and reset fifo*/
1892                 hdmi_msk_reg(hdmi_dev, AUD_INT,
1893                              m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1894                              v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1895                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1896                              m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1897                 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1898                 design_id = hdmi_readl(hdmi_dev, DESIGN_ID);
1899                 if (design_id >= 0x21)
1900                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x4);
1901                 else
1902                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1903                 usleep_range(90, 100);
1904                 /*
1905                  * when we try to use hdmi nlpcm mode
1906                  * we should use set AUD_CONF2 to open this route and set
1907                  * word_length to 24bit for b.p.c.u.v with 16bit raw data
1908                  * when the bitstream data  up to 8 channel, we should use
1909                  * the hdmi hbr mode
1910                  * HBR Mode : Dolby TrueHD
1911                  *            Dolby Atmos
1912                  *            DTS-HDMA
1913                  * NLPCM Mode :
1914                  * FS_32000 FS_44100 FS_48000 : Dolby Digital &  DTS
1915                  * FS_176400 FS_192000        : Dolby Digital Plus
1916                  */
1917                 if (audio->type == HDMI_AUDIO_NLPCM) {
1918                         if (channel == I2S_CHANNEL_7_8) {
1919                                 HDMIDBG("hbr mode.\n");
1920                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x1);
1921                                 word_length = I2S_24BIT_SAMPLE;
1922                         } else if ((audio->rate == HDMI_AUDIO_FS_32000) ||
1923                                    (audio->rate == HDMI_AUDIO_FS_44100) ||
1924                                    (audio->rate == HDMI_AUDIO_FS_48000) ||
1925                                    (audio->rate == HDMI_AUDIO_FS_176400) ||
1926                                    (audio->rate == HDMI_AUDIO_FS_192000)) {
1927                                 HDMIDBG("nlpcm mode.\n");
1928                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x2);
1929                                 word_length = I2S_24BIT_SAMPLE;
1930                         } else {
1931                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1932                         }
1933                 } else {
1934                         if (design_id >= 0x21)
1935                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x4);
1936                         else
1937                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1938                 }
1939                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1940                              m_I2S_SEL | m_I2S_IN_EN,
1941                              v_I2S_SEL(AUDIO_I2S) | v_I2S_IN_EN(channel));
1942                 hdmi_writel(hdmi_dev, AUD_CONF1,
1943                             v_I2S_MODE(I2S_STANDARD_MODE) |
1944                             v_I2S_WIDTH(word_length));
1945         }
1946
1947         hdmi_msk_reg(hdmi_dev, AUD_INPUTCLKFS,
1948                      m_LFS_FACTOR, v_LFS_FACTOR(mclk_fs));
1949
1950         /*Set N value*/
1951         hdmi_msk_reg(hdmi_dev, AUD_N3, m_NCTS_ATOMIC_WR, v_NCTS_ATOMIC_WR(1));
1952         /*Set CTS by manual*/
1953         hdmi_msk_reg(hdmi_dev, AUD_CTS3,
1954                      m_N_SHIFT | m_CTS_MANUAL | m_AUD_CTS3,
1955                      v_N_SHIFT(N_SHIFT_1) |
1956                      v_CTS_MANUAL(1) |
1957                      v_AUD_CTS3(CTS >> 16));
1958         hdmi_writel(hdmi_dev, AUD_CTS2, (CTS >> 8) & 0xff);
1959         hdmi_writel(hdmi_dev, AUD_CTS1, CTS & 0xff);
1960
1961         hdmi_msk_reg(hdmi_dev, AUD_N3, m_AUD_N3, v_AUD_N3(N >> 16));
1962         hdmi_writel(hdmi_dev, AUD_N2, (N >> 8) & 0xff);
1963         hdmi_writel(hdmi_dev, AUD_N1, N & 0xff);
1964
1965         /* set channel status register */
1966         hdmi_msk_reg(hdmi_dev, FC_AUDSCHNLS7,
1967                      m_AUDIO_SAMPLE_RATE, v_AUDIO_SAMPLE_RATE(rate));
1968         hdmi_writel(hdmi_dev, FC_AUDSCHNLS8, ((~rate) << 4) | 0x2);
1969
1970         hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1971                      m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1972
1973         hdmi_dev_config_aai(hdmi_dev, audio);
1974
1975         return 0;
1976 }
1977
1978 static int hdmi_dev_control_output(struct hdmi *hdmi, int enable)
1979 {
1980         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1981         struct hdmi_video vpara;
1982
1983         HDMIDBG("[%s] %d\n", __func__, enable);
1984         if (enable == HDMI_AV_UNMUTE) {
1985                 hdmi_writel(hdmi_dev, FC_DBGFORCE, 0x00);
1986                 if (hdmi->edid.sink_hdmi == OUTPUT_HDMI)
1987                         hdmi_msk_reg(hdmi_dev, FC_GCP,
1988                                      m_FC_SET_AVMUTE | m_FC_CLR_AVMUTE,
1989                                      v_FC_SET_AVMUTE(0) | v_FC_CLR_AVMUTE(1));
1990         } else {
1991                 if (enable & HDMI_VIDEO_MUTE) {
1992                         hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1993                                      m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1994                         if (hdmi->edid.sink_hdmi == OUTPUT_HDMI) {
1995                                 hdmi_msk_reg(hdmi_dev, FC_GCP,
1996                                              m_FC_SET_AVMUTE |
1997                                              m_FC_CLR_AVMUTE,
1998                                              v_FC_SET_AVMUTE(1) |
1999                                              v_FC_CLR_AVMUTE(0));
2000                                 vpara.vic = hdmi->vic;
2001                                 vpara.color_output = HDMI_COLOR_RGB_0_255;
2002                                 hdmi_dev_config_avi(hdmi_dev, &vpara);
2003                                 while ((!hdmi_readl(hdmi_dev, IH_FC_STAT1)) &
2004                                        m_AVI_INFOFRAME) {
2005                                         usleep_range(900, 1000);
2006                                 }
2007                         }
2008                 }
2009 /*              if (enable & HDMI_AUDIO_MUTE) {
2010  *                      hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
2011  *                                   m_AUD_PACK_SAMPFIT,
2012  *                                   v_AUD_PACK_SAMPFIT(0x0F));
2013  *              }
2014  */
2015                 if (enable == (HDMI_VIDEO_MUTE | HDMI_AUDIO_MUTE)) {
2016                         if (hdmi->ops->hdcp_power_off_cb)
2017                                 hdmi->ops->hdcp_power_off_cb(hdmi);
2018                         rockchip_hdmiv2_powerdown(hdmi_dev);
2019                 }
2020         }
2021         return 0;
2022 }
2023
2024 static int hdmi_dev_insert(struct hdmi *hdmi)
2025 {
2026         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2027
2028         HDMIDBG("%s\n", __func__);
2029         if (!hdmi->uboot)
2030                 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
2031         return HDMI_ERROR_SUCCESS;
2032 }
2033
2034 static int hdmi_dev_remove(struct hdmi *hdmi)
2035 {
2036         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2037
2038         HDMIDBG("%s\n", __func__);
2039         if (hdmi->ops->hdcp_power_off_cb)
2040                 hdmi->ops->hdcp_power_off_cb(hdmi);
2041         rockchip_hdmiv2_powerdown(hdmi_dev);
2042         hdmi_dev->tmdsclk = 0;
2043         return HDMI_ERROR_SUCCESS;
2044 }
2045
2046 static int hdmi_dev_enable(struct hdmi *hdmi)
2047 {
2048         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2049
2050         HDMIDBG("%s\n", __func__);
2051         if (!hdmi_dev->enable) {
2052                 hdmi_writel(hdmi_dev, IH_MUTE, 0x00);
2053                 hdmi_dev->enable = 1;
2054         }
2055         hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 10, 0);
2056         return 0;
2057 }
2058
2059 static int hdmi_dev_disable(struct hdmi *hdmi)
2060 {
2061         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2062
2063         HDMIDBG("%s\n", __func__);
2064         if (hdmi_dev->enable) {
2065                 hdmi_dev->enable = 0;
2066                 hdmi_writel(hdmi_dev, IH_MUTE, 0x1);
2067         }
2068         return 0;
2069 }
2070
2071 void rockchip_hdmiv2_dev_init_ops(struct hdmi_ops *ops)
2072 {
2073         if (ops) {
2074                 ops->enable     = hdmi_dev_enable;
2075                 ops->disable    = hdmi_dev_disable;
2076                 ops->getstatus  = hdmi_dev_detect_hotplug;
2077                 ops->insert     = hdmi_dev_insert;
2078                 ops->remove     = hdmi_dev_remove;
2079                 ops->getedid    = hdmi_dev_read_edid;
2080                 ops->setvideo   = hdmi_dev_config_video;
2081                 ops->setaudio   = hdmi_dev_config_audio;
2082                 ops->setmute    = hdmi_dev_control_output;
2083                 ops->setvsi     = hdmi_dev_config_vsi;
2084         }
2085 }
2086
2087 void rockchip_hdmiv2_dev_initial(struct hdmi_dev *hdmi_dev)
2088 {
2089         struct hdmi *hdmi = hdmi_dev->hdmi;
2090
2091         /*lcdc source select*/
2092         if (hdmi_dev->soctype == HDMI_SOC_RK3288) {
2093                 grf_writel(HDMI_SEL_LCDC(hdmi->property->videosrc, 4),
2094                            RK3288_GRF_SOC_CON6);
2095                 /* select GPIO7_C0 as cec pin */
2096                 grf_writel(((1 << 12) | (1 << 28)), RK3288_GRF_SOC_CON8);
2097         } else if (hdmi_dev->soctype == HDMI_SOC_RK3399) {
2098                 regmap_write(hdmi_dev->grf_base,
2099                              RK3399_GRF_SOC_CON20,
2100                              HDMI_SEL_LCDC(hdmi->property->videosrc, 6));
2101         }
2102
2103         if (!hdmi->uboot) {
2104                 pr_info("reset hdmi\n");
2105                 if (hdmi_dev->soctype == HDMI_SOC_RK3288) {
2106                         rk3288_cru_set_soft_reset(RK3288_SOFT_RST_HDMI, true);
2107                         usleep_range(10, 20);
2108                         rk3288_cru_set_soft_reset(RK3288_SOFT_RST_HDMI, false);
2109                 } else {
2110                         if (hdmi_dev->soctype == HDMI_SOC_RK322X) {
2111                                 regmap_write(hdmi_dev->grf_base,
2112                                              RK322X_GRF_SOC_CON2,
2113                                              RK322X_DDC_MASK_EN);
2114                                 regmap_write(hdmi_dev->grf_base,
2115                                              RK322X_GRF_SOC_CON6,
2116                                              RK322X_IO_3V_DOMAIN);
2117                         }
2118                         reset_control_assert(hdmi_dev->reset);
2119                         usleep_range(10, 20);
2120                         reset_control_deassert(hdmi_dev->reset);
2121                 }
2122                 rockchip_hdmiv2_powerdown(hdmi_dev);
2123         } else {
2124                 hdmi->hotplug = hdmi_dev_detect_hotplug(hdmi);
2125                 if (hdmi->hotplug != HDMI_HPD_ACTIVED)
2126                         hdmi->uboot = 0;
2127         }
2128         /*mute unnecessary interrupt, only enable hpd*/
2129         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT0, 0xff);
2130         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT1, 0xff);
2131         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT2, 0xff);
2132         hdmi_writel(hdmi_dev, IH_MUTE_AS_STAT0, 0xff);
2133         hdmi_writel(hdmi_dev, IH_MUTE_PHY_STAT0, 0xfc);
2134         hdmi_writel(hdmi_dev, IH_MUTE_I2CM_STAT0, 0xff);
2135         hdmi_writel(hdmi_dev, IH_MUTE_CEC_STAT0, 0xff);
2136         hdmi_writel(hdmi_dev, IH_MUTE_VP_STAT0, 0xff);
2137         hdmi_writel(hdmi_dev, IH_MUTE_I2CMPHY_STAT0, 0xff);
2138         hdmi_writel(hdmi_dev, IH_MUTE_AHBDMAAUD_STAT0, 0xff);
2139
2140         /* disable hdcp interrupt */
2141         hdmi_writel(hdmi_dev, A_APIINTMSK, 0xff);
2142         hdmi_writel(hdmi_dev, PHY_MASK, 0xf1);
2143
2144         if (hdmi->property->feature & SUPPORT_CEC)
2145                 rockchip_hdmiv2_cec_init(hdmi);
2146         if (hdmi->property->feature & SUPPORT_HDCP)
2147                 rockchip_hdmiv2_hdcp_init(hdmi);
2148 }
2149
2150 irqreturn_t rockchip_hdmiv2_dev_irq(int irq, void *priv)
2151 {
2152         struct hdmi_dev *hdmi_dev = priv;
2153         struct hdmi *hdmi = hdmi_dev->hdmi;
2154         char phy_pol = hdmi_readl(hdmi_dev, PHY_POL0);
2155         char phy_status = hdmi_readl(hdmi_dev, PHY_STAT0);
2156         char phy_int0 = hdmi_readl(hdmi_dev, PHY_INI0);
2157         /*read interrupt*/
2158         char fc_stat0 = hdmi_readl(hdmi_dev, IH_FC_STAT0);
2159         char fc_stat1 = hdmi_readl(hdmi_dev, IH_FC_STAT1);
2160         char fc_stat2 = hdmi_readl(hdmi_dev, IH_FC_STAT2);
2161         char aud_int = hdmi_readl(hdmi_dev, IH_AS_SATA0);
2162         char phy_int = hdmi_readl(hdmi_dev, IH_PHY_STAT0);
2163         char vp_stat0 = hdmi_readl(hdmi_dev, IH_VP_STAT0);
2164         char cec_int = hdmi_readl(hdmi_dev, IH_CEC_STAT0);
2165         char hdcp_int = hdmi_readl(hdmi_dev, A_APIINTSTAT);
2166         char hdcp2_int = hdmi_readl(hdmi_dev, HDCP2REG_STAT);
2167
2168         /*clear interrupt*/
2169         hdmi_writel(hdmi_dev, IH_FC_STAT0, fc_stat0);
2170         hdmi_writel(hdmi_dev, IH_FC_STAT1, fc_stat1);
2171         hdmi_writel(hdmi_dev, IH_FC_STAT2, fc_stat2);
2172         hdmi_writel(hdmi_dev, IH_VP_STAT0, vp_stat0);
2173
2174         if (phy_int0 || phy_int) {
2175                 if ((phy_int0 & m_PHY_LOCK) &&
2176                     (phy_pol & m_PHY_LOCK) == 0) {
2177                         pr_info("hdmi phy pll unlock\n");
2178                         hdmi_submit_work(hdmi, HDMI_SET_VIDEO, 0, 0);
2179                 }
2180                 phy_pol = (phy_int0 & (~phy_status)) | ((~phy_int0) & phy_pol);
2181                 hdmi_writel(hdmi_dev, PHY_POL0, phy_pol);
2182                 hdmi_writel(hdmi_dev, IH_PHY_STAT0, phy_int);
2183                 if ((phy_int & m_HPD) || ((phy_int & 0x3c) == 0x3c))
2184                         hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 20, 0);
2185         }
2186
2187         /* Audio error */
2188         if (aud_int) {
2189                 hdmi_writel(hdmi_dev, IH_AS_SATA0, aud_int);
2190                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
2191                              m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
2192                 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
2193         }
2194         /* CEC */
2195         if (cec_int) {
2196                 hdmi_writel(hdmi_dev, IH_CEC_STAT0, cec_int);
2197                 if (hdmi_dev->hdmi->property->feature & SUPPORT_CEC)
2198                         rockchip_hdmiv2_cec_isr(hdmi_dev, cec_int);
2199         }
2200         /* HDCP */
2201         if (hdcp_int) {
2202                 hdmi_writel(hdmi_dev, A_APIINTCLR, hdcp_int);
2203                 rockchip_hdmiv2_hdcp_isr(hdmi_dev, hdcp_int);
2204         }
2205
2206         /* HDCP2 */
2207         if (hdcp2_int) {
2208                 hdmi_writel(hdmi_dev, HDCP2REG_STAT, hdcp2_int);
2209                 pr_info("hdcp2_int is 0x%02x\n", hdcp2_int);
2210                 if ((hdcp2_int & m_HDCP2_AUTH_FAIL ||
2211                      hdcp2_int & m_HDCP2_AUTH_LOST) &&
2212                     hdmi_dev->hdcp2_start) {
2213                         pr_info("hdcp2 failed or lost\n");
2214                         hdmi_dev->hdcp2_start();
2215                 }
2216         }
2217         return IRQ_HANDLED;
2218 }