drivers/video/rockchip/hdmi/rockchip-hdmiv2/rockchip_hdmiv2_hw.c

   1 #include <linux/clk.h>
   2 #include <linux/delay.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/rockchip/cru.h>
   5 #include <linux/rockchip/grf.h>
   6 #include <linux/rockchip/iomap.h>
   7 #include "rockchip_hdmiv2.h"
   8 #include "rockchip_hdmiv2_hw.h"
   9 #include <linux/rockchip/grf.h>
  10
  11 #define HDMI_SEL_LCDC(x, bit)   ((((x) & 1) << bit) | (1 << (16 + bit)))
  12 #define grf_writel(v, offset)   writel_relaxed(v, RK_GRF_VIRT + offset)
  13 #define RK3399_GRF_SOC_CON20 0x6250
  14
  15 static const struct phy_mpll_config_tab PHY_MPLL_TABLE[] = {
  16 /*      tmdsclk = (pixclk / ref_cntrl ) * (fbdiv2 * fbdiv1) / nctrl / tmdsmhl
  17  *      opmode: 0:HDMI1.4       1:HDMI2.0
  18  *
  19  *      |pixclock|      tmdsclock|pixrepet|colordepth|prepdiv|tmdsmhl|opmode|
  20  *              fbdiv2|fbdiv1|ref_cntrl|nctrl|propctrl|intctrl|gmpctrl|
  21  */
  22         {27000000,      27000000,       0,      8,      0,      0,      0,
  23                 2,      3,      0,      3,      3,      0,      0},
  24         {27000000,      27000000,       1,      8,      0,      0,      0,
  25                 2,      3,      0,      3,      3,      0,      0},
  26         {27000000,      33750000,       0,      10,     1,      0,      0,
  27                 5,      1,      0,      3,      3,      0,      0},
  28         {27000000,      33750000,       1,      10,     1,      0,      0,
  29                 5,      1,      0,      3,      3,      0,      0},
  30         {27000000,      40500000,       0,      12,     2,      0,      0,
  31                 3,      3,      0,      3,      3,      0,      0},
  32         {27000000,      54000000,       0,      16,     3,      0,      0,
  33                 2,      3,      0,      2,      5,      0,      1},
  34         {59400000,      59400000,       0,      8,      0,      0,      0,
  35                 1,      3,      0,      2,      5,      0,      1},
  36         {59400000,      74250000,       0,      10,     1,      0,      0,
  37                 5,      0,      0,      2,      5,      0,      1},
  38         {59400000,      89100000,       0,      12,     2,      0,      0,
  39                 2,      2,      0,      2,      5,      0,      1},
  40         {59400000,      118800000,      0,      16,     3,      0,      0,
  41                 1,      3,      0,      1,      7,      0,      2},
  42         {65000000,      65000000,       0,      8,      0,      0,      0,
  43                 1,      3,      0,      2,      5,      0,      1},
  44         {74250000,      74250000,       0,      8,      0,      0,      0,
  45                 4,      3,      3,      2,      7,      0,      3},
  46         {74250000,      92812500,       0,      10,     1,      0,      0,
  47                 5,      0,      1,      1,      7,      0,      2},
  48         {74250000,      111375000,      0,      12,     2,      0,      0,
  49                 1,      2,      0,      1,      7,      0,      2},
  50         {74250000,      148500000,      0,      16,     3,      0,      0,
  51                 1,      3,      0,      1,      7,      0,      2},
  52         {83500000,      83500000,       0,      8,      0,      0,      0,
  53                 1,      3,      0,      2,      5,      0,      1},
  54         {85500000,      85500000,       0,      8,      0,      0,      0,
  55                 1,      3,      0,      2,      5,      0,      1},
  56         {106500000,     106500000,      0,      8,      0,      0,      0,
  57                 1,      1,      0,      1,      7,      0,      2},
  58         {108000000,     108000000,      0,      8,      0,      0,      0,
  59                 1,      1,      0,      1,      7,      0,      2},
  60         {146250000,     146250000,      0,      8,      0,      0,      0,
  61                 1,      1,      0,      1,      7,      0,      2},
  62         {148500000,     74250000,       0,      8,      0,      0,      0,
  63                 1,      1,      1,      1,      0,      0,      3},
  64         {148500000,     148500000,      0,      8,      0,      0,      0,
  65                 1,      1,      0,      1,      0,      0,      3},
  66         {148500000,     185625000,      0,      10,     1,      0,      0,
  67                 5,      0,      3,      0,      7,      0,      3},
  68         {148500000,     222750000,      0,      12,     2,      0,      0,
  69                 1,      2,      1,      0,      7,      0,      3},
  70         {148500000,     297000000,      0,      16,     3,      0,      0,
  71                 1,      1,      0,      0,      7,      0,      3},
  72         {148500000,     297000000,      0,      8,      0,      0,      0,
  73                 1,      1,      0,      0,      0,      0,      3},
  74         {148500000,     594000000,      0,      8,      0,      3,      1,
  75                 1,      3,      0,      0,      0,      0,      3},
  76         {269390000,     269390000,      0,      8,      0,      0,      0,
  77                 1,      0,      0,      0,      0,      0,      3},
  78         {285000000,     285000000,      0,      8,      0,      0,      0,
  79                 1,      0,      0,      0,      0,      0,      3},
  80         {297000000,     148500000,      0,      8,      0,      0,      0,
  81                 1,      0,      1,      0,      0,      0,      3},
  82         {297000000,     297000000,      0,      8,      0,      0,      0,
  83                 1,      0,      0,      0,      0,      0,      3},
  84         {297000000,     371250000,      0,      10,     1,      3,      1,
  85                 5,      1,      3,      1,      7,      0,      3},
  86         {297000000,     445500000,      0,      12,     2,      3,      1,
  87                 1,      2,      0,      1,      7,      0,      3},
  88         {297000000,     594000000,      0,      16,     3,      3,      1,
  89                 1,      3,      1,      0,      0,      0,      3},
  90         {340000000,     340000000,      0,      8,      0,      0,      0,
  91                 1,      0,      0,      0,      0,      0,      3},
  92         {403000000,     403000000,      0,      8,      0,      3,      1,
  93                 1,      3,      3,      0,      0,      0,      3},
  94         {594000000,     297000000,      0,      8,      0,      0,      0,
  95                 1,      0,      1,      0,      0,      0,      3},
  96         {594000000,     371250000,      0,      10,     1,      3,      1,
  97                 5,      0,      3,      1,      7,      0,      3},
  98         {594000000,     445500000,      0,      12,     2,      3,      1,
  99                 1,      2,      1,      1,      7,      0,      3},
 100         {594000000,     594000000,      0,      16,     3,      3,      1,
 101                 1,      3,      3,      0,      0,      0,      3},
 102         {594000000,     594000000,      0,      8,      0,      3,      1,
 103                 1,      3,      3,      0,      0,      0,      3},
 104 };
 105
 106 static const struct ext_pll_config_tab EXT_PLL_TABLE[] = {
 107         {27000000,      27000000,       8,      1,      90,     3,      2,
 108                 2,      10,     3,      3,      4,      0,      1,      40,
 109                 8},
 110         {27000000,      33750000,       10,     1,      90,     1,      3,
 111                 3,      10,     3,      3,      4,      0,      1,      40,
 112                 8},
 113         {59400000,      59400000,       8,      1,      99,     3,      2,
 114                 2,      1,      3,      3,      4,      0,      1,      40,
 115                 8},
 116         {59400000,      74250000,       10,     1,      99,     1,      2,
 117                 2,      1,      3,      3,      4,      0,      1,      40,
 118                 8},
 119         {74250000,      74250000,       8,      1,      99,     1,      2,
 120                 2,      1,      2,      3,      4,      0,      1,      40,
 121                 8},
 122         {74250000,      92812500,       10,     4,      495,    1,      2,
 123                 2,      1,      3,      3,      4,      0,      2,      40,
 124                 4},
 125         {148500000,     148500000,      8,      1,      99,     1,      1,
 126                 1,      1,      2,      2,      2,      0,      2,      40,
 127                 4},
 128         {148500000,     185625000,      10,     4,      495,    0,      2,
 129                 2,      1,      3,      2,      2,      0,      4,      40,
 130                 2},
 131         {297000000,     297000000,      8,      1,      99,     0,      1,
 132                 1,      1,      0,      2,      2,      0,      4,      40,
 133                 2},
 134         {297000000,     371250000,      10,     4,      495,    1,      2,
 135                 0,      1,      3,      1,      1,      0,      8,      40,
 136                 1},
 137         {594000000,     297000000,      8,      1,      99,     0,      1,
 138                 1,      1,      0,      2,      1,      0,      4,      40,
 139                 2},
 140         {594000000,     371250000,      10,     4,      495,    1,      2,
 141                 0,      1,      3,      1,      1,      1,      8,      40,
 142                 1},
 143         {594000000,     594000000,      8,      1,      99,     0,      2,
 144                 0,      1,      0,      1,      1,      0,      8,      40,
 145                 1},
 146 };
 147
 148 /* ddc i2c master reset */
 149 static void rockchip_hdmiv2_i2cm_reset(struct hdmi_dev *hdmi_dev)
 150 {
 151         hdmi_msk_reg(hdmi_dev, I2CM_SOFTRSTZ,
 152                      m_I2CM_SOFTRST, v_I2CM_SOFTRST(0));
 153         usleep_range(90, 100);
 154 }
 155
 156 /*set read/write offset,set read/write mode*/
 157 static void rockchip_hdmiv2_i2cm_write_request(struct hdmi_dev *hdmi_dev,
 158                                                u8 offset, u8 data)
 159 {
 160         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
 161         hdmi_writel(hdmi_dev, I2CM_DATAO, data);
 162         hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_WR, v_I2CM_WR(1));
 163 }
 164
 165 static void rockchip_hdmiv2_i2cm_read_request(struct hdmi_dev *hdmi_dev,
 166                                               u8 offset)
 167 {
 168         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
 169         hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_RD, v_I2CM_RD(1));
 170 }
 171
 172 static void rockchip_hdmiv2_i2cm_write_data(struct hdmi_dev *hdmi_dev,
 173                                             u8 data, u8 offset)
 174 {
 175         u8 interrupt = 0;
 176         int trytime = 2;
 177         int i = 20;
 178
 179         while (trytime-- > 0) {
 180                 rockchip_hdmiv2_i2cm_write_request(hdmi_dev, offset, data);
 181                 while (i--) {
 182                         usleep_range(900, 1000);
 183                         interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
 184                         if (interrupt)
 185                                 hdmi_writel(hdmi_dev,
 186                                             IH_I2CM_STAT0, interrupt);
 187
 188                         if (interrupt & (m_SCDC_READREQ |
 189                                          m_I2CM_DONE | m_I2CM_ERROR))
 190                                 break;
 191                 }
 192
 193                 if (interrupt & m_I2CM_DONE) {
 194                         dev_dbg(hdmi_dev->hdmi->dev,
 195                                 "[%s] write offset %02x data %02x success\n",
 196                                 __func__, offset, data);
 197                         trytime = 0;
 198                 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
 199                         dev_err(hdmi_dev->hdmi->dev,
 200                                 "[%s] write data error\n", __func__);
 201                         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 202                 }
 203         }
 204 }
 205
 206 static int rockchip_hdmiv2_i2cm_read_data(struct hdmi_dev *hdmi_dev, u8 offset)
 207 {
 208         u8 interrupt = 0, val;
 209         int trytime = 2;
 210         int i = 20;
 211
 212         while (trytime-- > 0) {
 213                 rockchip_hdmiv2_i2cm_read_request(hdmi_dev, offset);
 214                 while (i--) {
 215                         usleep_range(900, 1000);
 216                         interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
 217                         if (interrupt)
 218                                 hdmi_writel(hdmi_dev, IH_I2CM_STAT0, interrupt);
 219
 220                         if (interrupt & (m_SCDC_READREQ |
 221                                 m_I2CM_DONE | m_I2CM_ERROR))
 222                                 break;
 223                 }
 224
 225                 if (interrupt & m_I2CM_DONE) {
 226                         val = hdmi_readl(hdmi_dev, I2CM_DATAI);
 227                         trytime = 0;
 228                 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
 229                         pr_err("[%s] read data error\n", __func__);
 230                         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 231                 }
 232         }
 233         return val;
 234 }
 235
 236 static void rockchip_hdmiv2_i2cm_mask_int(struct hdmi_dev *hdmi_dev, int mask)
 237 {
 238         if (!mask) {
 239                 hdmi_msk_reg(hdmi_dev, I2CM_INT,
 240                              m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(0));
 241                 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
 242                              m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
 243                              v_I2CM_NACK_MASK(0) | v_I2CM_ARB_MASK(0));
 244         } else {
 245                 hdmi_msk_reg(hdmi_dev, I2CM_INT,
 246                              m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(1));
 247                 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
 248                              m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
 249                              v_I2CM_NACK_MASK(1) | v_I2CM_ARB_MASK(1));
 250         }
 251 }
 252
 253 #define I2C_DIV_FACTOR 1000000
 254 static u16 i2c_count(u16 sfrclock, u16 sclmintime)
 255 {
 256         unsigned long tmp_scl_period = 0;
 257
 258         if (((sfrclock * sclmintime) % I2C_DIV_FACTOR) != 0)
 259                 tmp_scl_period = (unsigned long)((sfrclock * sclmintime) +
 260                                 (I2C_DIV_FACTOR - ((sfrclock * sclmintime) %
 261                                 I2C_DIV_FACTOR))) / I2C_DIV_FACTOR;
 262         else
 263                 tmp_scl_period = (unsigned long)(sfrclock * sclmintime) /
 264                                 I2C_DIV_FACTOR;
 265
 266         return (u16)(tmp_scl_period);
 267 }
 268
 269 #define EDID_I2C_MIN_SS_SCL_HIGH_TIME   9625
 270 #define EDID_I2C_MIN_SS_SCL_LOW_TIME    10000
 271
 272 static void rockchip_hdmiv2_i2cm_clk_init(struct hdmi_dev *hdmi_dev)
 273 {
 274         int value;
 275
 276         /* Set DDC I2C CLK which divided from DDC_CLK. */
 277         value = i2c_count(24000, EDID_I2C_MIN_SS_SCL_HIGH_TIME);
 278         hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_0_ADDR,
 279                     value & 0xff);
 280         hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_1_ADDR,
 281                     (value >> 8) & 0xff);
 282         value = i2c_count(24000, EDID_I2C_MIN_SS_SCL_LOW_TIME);
 283         hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_0_ADDR,
 284                     value & 0xff);
 285         hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_1_ADDR,
 286                     (value >> 8) & 0xff);
 287         hdmi_msk_reg(hdmi_dev, I2CM_DIV, m_I2CM_FAST_STD_MODE,
 288                      v_I2CM_FAST_STD_MODE(STANDARD_MODE));
 289 }
 290
 291 static int rockchip_hdmiv2_scdc_get_sink_version(struct hdmi_dev *hdmi_dev)
 292 {
 293         return rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SINK_VER);
 294 }
 295
 296 static void rockchip_hdmiv2_scdc_set_source_version(struct hdmi_dev *hdmi_dev,
 297                                                     u8 version)
 298 {
 299         rockchip_hdmiv2_i2cm_write_data(hdmi_dev, version, SCDC_SOURCE_VER);
 300 }
 301
 302 static void rockchip_hdmiv2_scdc_read_request(struct hdmi_dev *hdmi_dev,
 303                                               int enable)
 304 {
 305         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 306                      m_I2CM_READ_REQ_EN, v_I2CM_READ_REQ_EN(enable));
 307         rockchip_hdmiv2_i2cm_write_data(hdmi_dev, enable, SCDC_CONFIG_0);
 308 }
 309
 310 #ifdef HDMI_20_SCDC
 311 static void rockchip_hdmiv2_scdc_update_read(struct hdmi_dev *hdmi_dev)
 312 {
 313         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 314                      m_I2CM_READ_UPDATE, v_I2CM_READ_UPDATE(1));
 315 }
 316
 317 static int rockchip_hdmiv2_scdc_get_scambling_status(struct hdmi_dev *hdmi_dev)
 318 {
 319         int val;
 320
 321         val = rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SCRAMBLER_STAT);
 322         return val;
 323 }
 324
 325 static void rockchip_hdmiv2_scdc_enable_polling(struct hdmi_dev *hdmi_dev,
 326                                                 int enable)
 327 {
 328         rockchip_hdmiv2_scdc_read_request(hdmi_dev, enable);
 329         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 330                      m_I2CM_UPRD_VSYNC_EN, v_I2CM_UPRD_VSYNC_EN(enable));
 331 }
 332
 333 static int rockchip_hdmiv2_scdc_get_status_reg0(struct hdmi_dev *hdmi_dev)
 334 {
 335         rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 336         rockchip_hdmiv2_scdc_update_read(hdmi_dev);
 337         return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE0);
 338 }
 339
 340 static int rockchip_hdmiv2_scdc_get_status_reg1(struct hdmi_dev *hdmi_dev)
 341 {
 342         rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 343         rockchip_hdmiv2_scdc_update_read(hdmi_dev);
 344         return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE1);
 345 }
 346 #endif
 347
 348 static void rockchip_hdmiv2_scdc_init(struct hdmi_dev *hdmi_dev)
 349 {
 350         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 351         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
 352         rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
 353         /* set scdc i2c addr */
 354         hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_SCDC_ADDR);
 355         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);/*enable interrupt*/
 356 }
 357
 358 static void rockchip_hdmiv2_scdc_set_tmds_rate(struct hdmi_dev *hdmi_dev)
 359 {
 360         int stat;
 361
 362         mutex_lock(&hdmi_dev->ddc_lock);
 363         rockchip_hdmiv2_scdc_init(hdmi_dev);
 364         stat = rockchip_hdmiv2_i2cm_read_data(hdmi_dev,
 365                                               SCDC_TMDS_CONFIG);
 366         if (hdmi_dev->tmdsclk > 340000000)
 367                 stat |= 2;
 368         else
 369                 stat &= 0x1;
 370         rockchip_hdmiv2_i2cm_write_data(hdmi_dev,
 371                                         stat, SCDC_TMDS_CONFIG);
 372         mutex_unlock(&hdmi_dev->ddc_lock);
 373 }
 374
 375 static int rockchip_hdmiv2_scrambling_enable(struct hdmi_dev *hdmi_dev,
 376                                              int enable)
 377 {
 378         HDMIDBG(2, "%s enable %d\n", __func__, enable);
 379         if (enable == 1) {
 380                 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
 381                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 1, SCDC_TMDS_CONFIG);
 382                 /* TMDS software reset request */
 383                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 384                              m_TMDS_SWRST, v_TMDS_SWRST(0));
 385                 /* Enable/Disable Scrambling */
 386                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 387                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(1));
 388         } else {
 389                 /* Enable/Disable Scrambling */
 390                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 391                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
 392                 /* TMDS software reset request */
 393                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 394                              m_TMDS_SWRST, v_TMDS_SWRST(0));
 395                 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
 396                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 0, SCDC_TMDS_CONFIG);
 397         }
 398         return 0;
 399 }
 400
 401 static const struct ext_pll_config_tab *get_phy_ext_tab(
 402                 unsigned int pixclock, unsigned int tmdsclk,
 403                 char colordepth)
 404 {
 405         int i;
 406
 407         if (pixclock == 0)
 408                 return NULL;
 409         HDMIDBG(2, "%s pixClock %u tmdsclk %u colorDepth %d\n",
 410                 __func__, pixclock, tmdsclk, colordepth);
 411         for (i = 0; i < ARRAY_SIZE(EXT_PLL_TABLE); i++) {
 412                 if ((EXT_PLL_TABLE[i].pix_clock == pixclock) &&
 413                     (EXT_PLL_TABLE[i].tmdsclock == tmdsclk) &&
 414                     (EXT_PLL_TABLE[i].color_depth == colordepth))
 415                         return &EXT_PLL_TABLE[i];
 416         }
 417         return NULL;
 418 }
 419
 420 static const struct phy_mpll_config_tab *get_phy_mpll_tab(
 421                 unsigned int pixclock, unsigned int tmdsclk,
 422                 char pixrepet, char colordepth)
 423 {
 424         int i;
 425
 426         if (pixclock == 0)
 427                 return NULL;
 428         HDMIDBG(2, "%s pixClock %u tmdsclk %u pixRepet %d colorDepth %d\n",
 429                 __func__, pixclock, tmdsclk, pixrepet, colordepth);
 430         for (i = 0; i < ARRAY_SIZE(PHY_MPLL_TABLE); i++) {
 431                 if ((PHY_MPLL_TABLE[i].pix_clock == pixclock) &&
 432                     (PHY_MPLL_TABLE[i].tmdsclock == tmdsclk) &&
 433                     (PHY_MPLL_TABLE[i].pix_repet == pixrepet) &&
 434                     (PHY_MPLL_TABLE[i].color_depth == colordepth))
 435                         return &PHY_MPLL_TABLE[i];
 436         }
 437         return NULL;
 438 }
 439
 440 static void rockchip_hdmiv2_powerdown(struct hdmi_dev *hdmi_dev)
 441 {
 442         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(1));
 443         if (hdmi_dev->soctype != HDMI_SOC_RK322X) {
 444                 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 445                              m_PDDQ_SIG | m_TXPWRON_SIG |
 446                              m_ENHPD_RXSENSE_SIG | m_SVSRET_SIG,
 447                              v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) |
 448                              v_ENHPD_RXSENSE_SIG(1)) | v_SVSRET_SIG(0);
 449         } else {
 450                 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 451                              m_TXPWRON_SIG | m_ENHPD_RXSENSE_SIG,
 452                              v_TXPWRON_SIG(0) | v_ENHPD_RXSENSE_SIG(0));
 453                 regmap_write(hdmi_dev->grf_base,
 454                              RK322X_GRF_SOC_CON2,
 455                              RK322X_PLL_PDATA_DEN);
 456         }
 457         hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
 458 }
 459
 460 int rockchip_hdmiv2_write_phy(struct hdmi_dev *hdmi_dev,
 461                               int reg_addr, int val)
 462 {
 463         int trytime = 2, i = 0, op_status = 0;
 464
 465         if (hdmi_dev->phybase) {
 466                 writel_relaxed(val, hdmi_dev->phybase + (reg_addr) * 0x04);
 467                 return 0;
 468         }
 469         while (trytime--) {
 470                 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
 471                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_1, (val >> 8) & 0xff);
 472                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_0, val & 0xff);
 473                 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_WRITE);
 474
 475                 i = 20;
 476                 while (i--) {
 477                         usleep_range(900, 1000);
 478                         op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
 479                         if (op_status)
 480                                 hdmi_writel(hdmi_dev,
 481                                             IH_I2CMPHY_STAT0,
 482                                             op_status);
 483
 484                         if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
 485                                 break;
 486                 }
 487
 488                 if (!(op_status & m_I2CMPHY_DONE))
 489                         dev_err(hdmi_dev->hdmi->dev,
 490                                 "[%s] operation error,trytime=%d\n",
 491                                 __func__, trytime);
 492                 else
 493                         return 0;
 494                 msleep(100);
 495         }
 496
 497         return -1;
 498 }
 499
 500 int rockchip_hdmiv2_read_phy(struct hdmi_dev *hdmi_dev,
 501                              int reg_addr)
 502 {
 503         int trytime = 2, i = 0, op_status = 0;
 504         int val = 0;
 505
 506         if (hdmi_dev->phybase)
 507                 return readl_relaxed(hdmi_dev->phybase + (reg_addr) * 0x04);
 508
 509         while (trytime--) {
 510                 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
 511                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_1, 0x00);
 512                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_0, 0x00);
 513                 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_READ);
 514
 515                 i = 20;
 516                 while (i--) {
 517                         usleep_range(900, 1000);
 518                         op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
 519                         if (op_status)
 520                                 hdmi_writel(hdmi_dev, IH_I2CMPHY_STAT0,
 521                                             op_status);
 522
 523                         if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
 524                                 break;
 525                 }
 526
 527                 if (!(op_status & m_I2CMPHY_DONE)) {
 528                         pr_err("[%s] operation error,trytime=%d\n",
 529                                __func__, trytime);
 530                 } else {
 531                         val = hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_1);
 532                         val = (val & 0xff) << 8;
 533                         val += (hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_0) & 0xff);
 534                         pr_debug("phy_reg0x%02x: 0x%04x",
 535                                  reg_addr, val);
 536                         return val;
 537                 }
 538                 msleep(100);
 539         }
 540
 541         return -1;
 542 }
 543
 544 #define PHY_TIMEOUT     10000
 545
 546 static int ext_phy_config(struct hdmi_dev *hdmi_dev)
 547 {
 548         int stat = 0, i = 0, temp;
 549         const struct ext_pll_config_tab *phy_ext = NULL;
 550
 551         if (hdmi_dev->grf_base)
 552                 regmap_write(hdmi_dev->grf_base,
 553                              RK322X_GRF_SOC_CON2,
 554                              RK322X_PLL_POWER_DOWN |
 555                              RK322X_PLL_PDATA_DEN);
 556         if (hdmi_dev->tmdsclk_ratio_change &&
 557             hdmi_dev->hdmi->edid.scdc_present == 1)
 558                 rockchip_hdmiv2_scdc_set_tmds_rate(hdmi_dev);
 559
 560         /* config the required PHY I2C register */
 561         phy_ext = get_phy_ext_tab(hdmi_dev->pixelclk,
 562                                   hdmi_dev->tmdsclk,
 563                                   hdmi_dev->colordepth);
 564         if (phy_ext) {
 565                 stat = ((phy_ext->pll_nf >> 1) & EXT_PHY_PLL_FB_BIT8_MASK) |
 566                        ((phy_ext->vco_div_5 & 1) << 5) |
 567                        (phy_ext->pll_nd & EXT_PHY_PLL_PRE_DIVIDER_MASK);
 568                 rockchip_hdmiv2_write_phy(hdmi_dev,
 569                                           EXT_PHY_PLL_PRE_DIVIDER, stat);
 570                 stat = phy_ext->pll_nf & 0xff;
 571                 rockchip_hdmiv2_write_phy(hdmi_dev,
 572                                           EXT_PHY_PLL_FB_DIVIDER, stat);
 573                 stat = (phy_ext->pclk_divider_a & EXT_PHY_PCLK_DIVIDERA_MASK) |
 574                        ((phy_ext->pclk_divider_b & 3) << 5);
 575                 rockchip_hdmiv2_write_phy(hdmi_dev,
 576                                           EXT_PHY_PCLK_DIVIDER1, stat);
 577                 stat = (phy_ext->pclk_divider_d & EXT_PHY_PCLK_DIVIDERD_MASK) |
 578                        ((phy_ext->pclk_divider_c & 3) << 5);
 579                 rockchip_hdmiv2_write_phy(hdmi_dev,
 580                                           EXT_PHY_PCLK_DIVIDER2, stat);
 581                 stat = ((phy_ext->tmsd_divider_c & 3) << 4) |
 582                        ((phy_ext->tmsd_divider_a & 3) << 2) |
 583                        (phy_ext->tmsd_divider_b & 3);
 584                 rockchip_hdmiv2_write_phy(hdmi_dev,
 585                                           EXT_PHY_TMDSCLK_DIVIDER, stat);
 586                 rockchip_hdmiv2_write_phy(hdmi_dev,
 587                                           EXT_PHY_PPLL_FB_DIVIDER,
 588                                           phy_ext->ppll_nf);
 589
 590                 if (phy_ext->ppll_no == 1) {
 591                         rockchip_hdmiv2_write_phy(hdmi_dev,
 592                                                   EXT_PHY_PPLL_POST_DIVIDER,
 593                                                   0);
 594                         stat = 0x20 | phy_ext->ppll_nd;
 595                         rockchip_hdmiv2_write_phy(hdmi_dev,
 596                                                   EXT_PHY_PPLL_PRE_DIVIDER,
 597                                                   stat);
 598                 } else {
 599                         stat = ((phy_ext->ppll_no / 2) - 1) << 4;
 600                         rockchip_hdmiv2_write_phy(hdmi_dev,
 601                                                   EXT_PHY_PPLL_POST_DIVIDER,
 602                                                   stat);
 603                         stat = 0xe0 | phy_ext->ppll_nd;
 604                         rockchip_hdmiv2_write_phy(hdmi_dev,
 605                                                   EXT_PHY_PPLL_PRE_DIVIDER,
 606                                                   stat);
 607                 }
 608         } else {
 609                 pr_err("%s no supported phy configuration.\n", __func__);
 610                 return -1;
 611         }
 612
 613         if (hdmi_dev->phy_table) {
 614                 for (i = 0; i < hdmi_dev->phy_table_size; i++) {
 615                         temp = hdmi_dev->phy_table[i].maxfreq;
 616                         if (hdmi_dev->tmdsclk <= temp)
 617                                 break;
 618                 }
 619         }
 620
 621         if (i != hdmi_dev->phy_table_size) {
 622                 if (hdmi_dev->phy_table[i].slopeboost) {
 623                         rockchip_hdmiv2_write_phy(hdmi_dev,
 624                                                   EXT_PHY_SIGNAL_CTRL, 0xff);
 625                         temp = hdmi_dev->phy_table[i].slopeboost - 1;
 626                         stat = ((temp & 3) << 6) | ((temp & 3) << 4) |
 627                                ((temp & 3) << 2) | (temp & 3);
 628                         rockchip_hdmiv2_write_phy(hdmi_dev,
 629                                                   EXT_PHY_SLOPEBOOST, stat);
 630                 } else {
 631                         rockchip_hdmiv2_write_phy(hdmi_dev,
 632                                                   EXT_PHY_SIGNAL_CTRL, 0x0f);
 633                 }
 634                 stat = ((hdmi_dev->phy_table[i].pre_emphasis & 3) << 4) |
 635                        ((hdmi_dev->phy_table[i].pre_emphasis & 3) << 2) |
 636                        (hdmi_dev->phy_table[i].pre_emphasis & 3);
 637                 rockchip_hdmiv2_write_phy(hdmi_dev,
 638                                           EXT_PHY_PREEMPHASIS, stat);
 639                 stat = ((hdmi_dev->phy_table[i].clk_level & 0xf) << 4) |
 640                        (hdmi_dev->phy_table[i].data2_level & 0xf);
 641                 rockchip_hdmiv2_write_phy(hdmi_dev,
 642                                           EXT_PHY_LEVEL1, stat);
 643                 stat = ((hdmi_dev->phy_table[i].data1_level & 0xf) << 4) |
 644                        (hdmi_dev->phy_table[i].data0_level & 0xf);
 645                 rockchip_hdmiv2_write_phy(hdmi_dev,
 646                                           EXT_PHY_LEVEL2, stat);
 647         } else {
 648                 rockchip_hdmiv2_write_phy(hdmi_dev,
 649                                           EXT_PHY_SIGNAL_CTRL, 0x0f);
 650         }
 651         rockchip_hdmiv2_write_phy(hdmi_dev, 0xf3, 0x22);
 652
 653         stat = clk_get_rate(hdmi_dev->pclk_phy) / 100000;
 654         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL,
 655                                   ((stat >> 8) & 0xff) | 0x80);
 656         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL_DIV_L,
 657                                   stat & 0xff);
 658         if (hdmi_dev->tmdsclk > 340000000)
 659                 stat = EXT_PHY_AUTO_R100_OHMS;
 660         else if (hdmi_dev->tmdsclk > 200000000)
 661                 stat = EXT_PHY_AUTO_R50_OHMS;
 662         else
 663                 stat = EXT_PHY_AUTO_ROPEN_CIRCUIT;
 664         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_RESIS_AUTO,
 665                                   stat | 0x20);
 666         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL,
 667                                   (stat >> 8) & 0xff);
 668         if (hdmi_dev->tmdsclk > 200000000)
 669                 stat = 0;
 670         else
 671                 stat = 0x11;
 672         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_PLL_BW, stat);
 673         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_PPLL_BW, 0x27);
 674         if (hdmi_dev->grf_base)
 675                 regmap_write(hdmi_dev->grf_base,
 676                              RK322X_GRF_SOC_CON2,
 677                              RK322X_PLL_POWER_UP);
 678         if (hdmi_dev->tmdsclk_ratio_change)
 679                 msleep(100);
 680         else
 681                 usleep_range(900, 1000);
 682         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 683                      m_TXPWRON_SIG, v_TXPWRON_SIG(1));
 684         i = 0;
 685         while (i++ < PHY_TIMEOUT) {
 686                 if ((i % 10) == 0) {
 687                         temp = EXT_PHY_PPLL_POST_DIVIDER;
 688                         stat = rockchip_hdmiv2_read_phy(hdmi_dev, temp);
 689                         if (stat & EXT_PHY_PPLL_LOCK_STATUS_MASK)
 690                                 break;
 691                         usleep_range(1000, 2000);
 692                 }
 693         }
 694         if ((stat & EXT_PHY_PPLL_LOCK_STATUS_MASK) == 0) {
 695                 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
 696                 dev_err(hdmi_dev->hdmi->dev,
 697                         "PHY PLL not locked: PCLK_ON=%ld,TMDSCLK_ON=%ld\n",
 698                         (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
 699                 return -1;
 700         }
 701
 702         if (hdmi_dev->grf_base)
 703                 regmap_write(hdmi_dev->grf_base,
 704                              RK322X_GRF_SOC_CON2,
 705                              RK322X_PLL_PDATA_EN);
 706
 707         return 0;
 708 }
 709
 710 static int rockchip_hdmiv2_config_phy(struct hdmi_dev *hdmi_dev)
 711 {
 712         int stat = 0, i = 0;
 713         const struct phy_mpll_config_tab *phy_mpll = NULL;
 714
 715         if (hdmi_dev->soctype == HDMI_SOC_RK322X) {
 716                 return ext_phy_config(hdmi_dev);
 717         } else if (hdmi_dev->soctype == HDMI_SOC_RK3366) {
 718                 if (hdmi_dev->pixelclk > 148500000)
 719                         clk_set_rate(hdmi_dev->pclk_phy, 148500000);
 720                 else
 721                         clk_set_rate(hdmi_dev->pclk_phy, hdmi_dev->pixelclk);
 722         } else if (hdmi_dev->soctype == HDMI_SOC_RK3399) {
 723                 clk_set_rate(hdmi_dev->pclk_phy, hdmi_dev->pixelclk);
 724         }
 725
 726         hdmi_msk_reg(hdmi_dev, PHY_I2CM_DIV,
 727                      m_PHY_I2CM_FAST_STD, v_PHY_I2CM_FAST_STD(0));
 728         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(1));
 729         /* power off PHY */
 730         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 731                      m_PDDQ_SIG | m_TXPWRON_SIG | m_SVSRET_SIG,
 732                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) | v_SVSRET_SIG(1));
 733
 734         if (hdmi_dev->tmdsclk_ratio_change &&
 735             hdmi_dev->hdmi->edid.scdc_present == 1)
 736                 rockchip_hdmiv2_scdc_set_tmds_rate(hdmi_dev);
 737
 738         /* reset PHY */
 739         hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(1));
 740         usleep_range(1000, 2000);
 741         hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(0));
 742
 743         /* Set slave address as PHY GEN2 address */
 744         hdmi_writel(hdmi_dev, PHY_I2CM_SLAVE, PHY_GEN2_ADDR);
 745
 746         /* config the required PHY I2C register */
 747         if (hdmi_dev->soctype == HDMI_SOC_RK3366 &&
 748             hdmi_dev->pixelclk > 148500000)
 749                 phy_mpll = get_phy_mpll_tab(148500000,
 750                                             hdmi_dev->tmdsclk,
 751                                             hdmi_dev->pixelrepeat - 1,
 752                                             hdmi_dev->colordepth);
 753         else
 754                 phy_mpll = get_phy_mpll_tab(hdmi_dev->pixelclk,
 755                                             hdmi_dev->tmdsclk,
 756                                             hdmi_dev->pixelrepeat - 1,
 757                                             hdmi_dev->colordepth);
 758         if (phy_mpll) {
 759                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_OPMODE_PLLCFG,
 760                                           v_PREP_DIV(phy_mpll->prep_div) |
 761                                           v_TMDS_CNTRL(
 762                                           phy_mpll->tmdsmhl_cntrl) |
 763                                           v_OPMODE(phy_mpll->opmode) |
 764                                           v_FBDIV2_CNTRL(
 765                                           phy_mpll->fbdiv2_cntrl) |
 766                                           v_FBDIV1_CNTRL(
 767                                           phy_mpll->fbdiv1_cntrl) |
 768                                           v_REF_CNTRL(phy_mpll->ref_cntrl) |
 769                                           v_MPLL_N_CNTRL(phy_mpll->n_cntrl));
 770                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLCURRCTRL,
 771                                           v_MPLL_PROP_CNTRL(
 772                                           phy_mpll->prop_cntrl) |
 773                                           v_MPLL_INT_CNTRL(
 774                                           phy_mpll->int_cntrl));
 775                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLGMPCTRL,
 776                                           v_MPLL_GMP_CNTRL(
 777                                           phy_mpll->gmp_cntrl));
 778         }
 779
 780         if (hdmi_dev->phy_table) {
 781                 for (i = 0; i < hdmi_dev->phy_table_size; i++)
 782                         if (hdmi_dev->tmdsclk <= hdmi_dev->phy_table[i].maxfreq)
 783                                 break;
 784         }
 785         if (i == hdmi_dev->phy_table_size) {
 786                 pr_info("%s use default phy settings\n", __func__);
 787                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL,
 788                                           v_OVERRIDE(1) | v_SLOPEBOOST(0) |
 789                                           v_TX_SYMON(1) | v_CLK_SYMON(1) |
 790                                           v_PREEMPHASIS(0));
 791                 if (hdmi_dev->tmdsclk > 340000000)
 792                         rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
 793                                                   v_SUP_TXLVL(9) |
 794                                                   v_SUP_CLKLVL(17));
 795                 else if (hdmi_dev->tmdsclk > 165000000)
 796                         rockchip_hdmiv2_write_phy(hdmi_dev,
 797                                                   PHYTX_VLEVCTRL,
 798                                                   v_SUP_TXLVL(14) |
 799                                                   v_SUP_CLKLVL(17));
 800                 else
 801                         rockchip_hdmiv2_write_phy(hdmi_dev,
 802                                                   PHYTX_VLEVCTRL,
 803                                                   v_SUP_TXLVL(18) |
 804                                                   v_SUP_CLKLVL(17));
 805         } else {
 806                 stat = v_OVERRIDE(1) | v_TX_SYMON(1) | v_CLK_SYMON(1) |
 807                        v_PREEMPHASIS(hdmi_dev->phy_table[i].pre_emphasis) |
 808                        v_SLOPEBOOST(hdmi_dev->phy_table[i].slopeboost);
 809                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL, stat);
 810
 811                 stat = v_SUP_CLKLVL(hdmi_dev->phy_table[i].clk_level) |
 812                        v_SUP_TXLVL(hdmi_dev->phy_table[i].data0_level);
 813                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL, stat);
 814         }
 815
 816         if (hdmi_dev->tmdsclk > 340000000)
 817                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
 818                                           v_TX_TERM(R50_OHMS));
 819         else
 820                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
 821                                           v_TX_TERM(R100_OHMS));
 822         /* rockchip_hdmiv2_write_phy(hdmi_dev, 0x05, 0x8000); */
 823         if (hdmi_dev->tmdsclk_ratio_change)
 824                 msleep(100);
 825         /* power on PHY */
 826         hdmi_writel(hdmi_dev, PHY_CONF0, 0x2e);
 827
 828         /* check if the PHY PLL is locked */
 829
 830         i = 0;
 831         while (i++ < PHY_TIMEOUT) {
 832                 if ((i % 10) == 0) {
 833                         stat = hdmi_readl(hdmi_dev, PHY_STAT0);
 834                         if (stat & m_PHY_LOCK)
 835                                 break;
 836                         usleep_range(1000, 2000);
 837                 }
 838         }
 839         if ((stat & m_PHY_LOCK) == 0) {
 840                 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
 841                 dev_err(hdmi_dev->hdmi->dev,
 842                         "PHY PLL not locked: PCLK_ON=%ld,TMDSCLK_ON=%ld\n",
 843                         (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
 844                 return -1;
 845         }
 846         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(0));
 847         return 0;
 848 }
 849
 850 static int rockchip_hdmiv2_video_framecomposer(struct hdmi *hdmi_drv,
 851                                                struct hdmi_video *vpara)
 852 {
 853         struct hdmi_dev *hdmi_dev = hdmi_drv->property->priv;
 854         int value, vsync_pol, hsync_pol, de_pol;
 855         struct hdmi_video_timing *timing = NULL;
 856         struct fb_videomode *mode = NULL;
 857         u32 sink_version, tmdsclk;
 858
 859         vsync_pol = hdmi_drv->lcdc->cur_screen->pin_vsync;
 860         hsync_pol = hdmi_drv->lcdc->cur_screen->pin_hsync;
 861         de_pol = (hdmi_drv->lcdc->cur_screen->pin_den == 0) ? 1 : 0;
 862
 863         hdmi_msk_reg(hdmi_dev, A_VIDPOLCFG,
 864                      m_DATAEN_POL | m_VSYNC_POL | m_HSYNC_POL,
 865                      v_DATAEN_POL(de_pol) |
 866                      v_VSYNC_POL(vsync_pol) |
 867                      v_HSYNC_POL(hsync_pol));
 868
 869         timing = (struct hdmi_video_timing *)hdmi_vic2timing(vpara->vic);
 870         if (!timing) {
 871                 dev_err(hdmi_drv->dev,
 872                         "[%s] not found vic %d\n", __func__, vpara->vic);
 873                 return -ENOENT;
 874         }
 875         mode = &timing->mode;
 876         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 877                 tmdsclk = mode->pixclock / 2;
 878         else if (vpara->format_3d == HDMI_3D_FRAME_PACKING)
 879                 tmdsclk = 2 * mode->pixclock;
 880         else
 881                 tmdsclk = mode->pixclock;
 882         if (vpara->color_output != HDMI_COLOR_YCBCR422) {
 883                 switch (vpara->color_output_depth) {
 884                 case 10:
 885                         tmdsclk += tmdsclk / 4;
 886                         break;
 887                 case 12:
 888                         tmdsclk += tmdsclk / 2;
 889                         break;
 890                 case 16:
 891                         tmdsclk += tmdsclk;
 892                         break;
 893                 case 8:
 894                 default:
 895                         break;
 896                 }
 897         } else if (vpara->color_output_depth > 12) {
 898                 /* YCbCr422 mode only support up to 12bit */
 899                 vpara->color_output_depth = 12;
 900         }
 901         if ((tmdsclk > 594000000) ||
 902             (tmdsclk > 340000000 &&
 903              tmdsclk > hdmi_drv->edid.maxtmdsclock)) {
 904                 pr_warn("out of max tmds clock, limit to 8bit\n");
 905                 vpara->color_output_depth = 8;
 906                 if (vpara->color_input == HDMI_COLOR_YCBCR420)
 907                         tmdsclk = mode->pixclock / 2;
 908                 else if (vpara->format_3d != HDMI_3D_FRAME_PACKING)
 909                         tmdsclk = mode->pixclock;
 910                 else
 911                         return -1;
 912         }
 913
 914         if ((tmdsclk > 340000000) ||
 915             (tmdsclk < 340000000 && hdmi_dev->tmdsclk > 340000000))
 916                 hdmi_dev->tmdsclk_ratio_change = true;
 917         else
 918                 hdmi_dev->tmdsclk_ratio_change = false;
 919
 920         hdmi_dev->tmdsclk = tmdsclk;
 921         if (vpara->format_3d == HDMI_3D_FRAME_PACKING)
 922                 hdmi_dev->pixelclk = 2 * mode->pixclock;
 923         else
 924                 hdmi_dev->pixelclk = mode->pixclock;
 925         hdmi_dev->pixelrepeat = timing->pixelrepeat;
 926         /* hdmi_dev->colordepth is used for find pll config.
 927          * For YCbCr422, tmdsclk is same on all color depth.
 928          */
 929         if (vpara->color_output == HDMI_COLOR_YCBCR422)
 930                 hdmi_dev->colordepth = 8;
 931         else
 932                 hdmi_dev->colordepth = vpara->color_output_depth;
 933         pr_info("pixel clk is %lu tmds clk is %u\n",
 934                 hdmi_dev->pixelclk, hdmi_dev->tmdsclk);
 935         /* Start/stop HDCP keepout window generation */
 936         hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 937                      m_FC_HDCP_KEEPOUT, v_FC_HDCP_KEEPOUT(1));
 938         if (hdmi_drv->edid.scdc_present == 1 && !hdmi_drv->uboot) {
 939                 if (tmdsclk > 340000000 ||
 940                     hdmi_drv->edid.lte_340mcsc_scramble) {
 941                         /* used for HDMI 2.0 TX */
 942                         mutex_lock(&hdmi_dev->ddc_lock);
 943                         rockchip_hdmiv2_scdc_init(hdmi_dev);
 944                         sink_version =
 945                         rockchip_hdmiv2_scdc_get_sink_version(hdmi_dev);
 946                         pr_info("sink scdc version is %d\n", sink_version);
 947                         sink_version = hdmi_drv->edid.hf_vsdb_version;
 948                         rockchip_hdmiv2_scdc_set_source_version(hdmi_dev,
 949                                                                 sink_version);
 950                         if (hdmi_drv->edid.rr_capable == 1)
 951                                 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 952                         rockchip_hdmiv2_scrambling_enable(hdmi_dev, 1);
 953                         mutex_unlock(&hdmi_dev->ddc_lock);
 954                 } else {
 955                         mutex_lock(&hdmi_dev->ddc_lock);
 956                         rockchip_hdmiv2_scdc_init(hdmi_dev);
 957                         rockchip_hdmiv2_scrambling_enable(hdmi_dev, 0);
 958                         mutex_unlock(&hdmi_dev->ddc_lock);
 959                 }
 960         } else {
 961                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 962                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
 963         }
 964
 965         hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 966                      m_FC_VSYNC_POL | m_FC_HSYNC_POL | m_FC_DE_POL |
 967                      m_FC_HDMI_DVI | m_FC_INTERLACE_MODE,
 968                      v_FC_VSYNC_POL(vsync_pol) | v_FC_HSYNC_POL(hsync_pol) |
 969                      v_FC_DE_POL(de_pol) | v_FC_HDMI_DVI(vpara->sink_hdmi) |
 970                      v_FC_INTERLACE_MODE(mode->vmode));
 971         if ((mode->vmode & FB_VMODE_INTERLACED) &&
 972             vpara->format_3d != HDMI_3D_FRAME_PACKING)
 973                 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 974                              m_FC_VBLANK, v_FC_VBLANK(1));
 975         else
 976                 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 977                              m_FC_VBLANK, v_FC_VBLANK(0));
 978
 979         value = mode->xres;
 980         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 981                 value = value / 2;
 982         hdmi_writel(hdmi_dev, FC_INHACTIV1, v_FC_HACTIVE1(value >> 8));
 983         hdmi_writel(hdmi_dev, FC_INHACTIV0, (value & 0xff));
 984
 985         if (vpara->format_3d == HDMI_3D_FRAME_PACKING) {
 986                 if (mode->vmode == 0)
 987                         value = 2 * mode->yres +
 988                                 mode->upper_margin +
 989                                 mode->lower_margin +
 990                                 mode->vsync_len;
 991                 else
 992                         value = 2 * mode->yres +
 993                                 3 * (mode->upper_margin +
 994                                      mode->lower_margin +
 995                                      mode->vsync_len) + 2;
 996         } else {
 997                 value = mode->yres;
 998         }
 999         hdmi_writel(hdmi_dev, FC_INVACTIV1, v_FC_VACTIVE1(value >> 8));
1000         hdmi_writel(hdmi_dev, FC_INVACTIV0, (value & 0xff));
1001
1002         value = mode->hsync_len + mode->left_margin + mode->right_margin;
1003         if (vpara->color_input == HDMI_COLOR_YCBCR420)
1004                 value = value / 2;
1005         hdmi_writel(hdmi_dev, FC_INHBLANK1, v_FC_HBLANK1(value >> 8));
1006         hdmi_writel(hdmi_dev, FC_INHBLANK0, (value & 0xff));
1007
1008         value = mode->vsync_len + mode->upper_margin + mode->lower_margin;
1009         hdmi_writel(hdmi_dev, FC_INVBLANK, (value & 0xff));
1010
1011         value = mode->right_margin;
1012         if (vpara->color_input == HDMI_COLOR_YCBCR420)
1013                 value = value / 2;
1014         hdmi_writel(hdmi_dev, FC_HSYNCINDELAY1, v_FC_HSYNCINDEAY1(value >> 8));
1015         hdmi_writel(hdmi_dev, FC_HSYNCINDELAY0, (value & 0xff));
1016
1017         value = mode->lower_margin;
1018         hdmi_writel(hdmi_dev, FC_VSYNCINDELAY, (value & 0xff));
1019
1020         value = mode->hsync_len;
1021         if (vpara->color_input == HDMI_COLOR_YCBCR420)
1022                 value = value / 2;
1023         hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH1, v_FC_HSYNCWIDTH1(value >> 8));
1024         hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH0, (value & 0xff));
1025
1026         value = mode->vsync_len;
1027         hdmi_writel(hdmi_dev, FC_VSYNCINWIDTH, (value & 0xff));
1028
1029         /* Set the control period minimum duration (min. of 12 pixel
1030          * clock cycles, refer to HDMI 1.4b specification)
1031          */
1032         hdmi_writel(hdmi_dev, FC_CTRLDUR, 12);
1033         hdmi_writel(hdmi_dev, FC_EXCTRLDUR, 32);
1034
1035         /* spacing < 256^2 * config / tmdsClock, spacing <= 50ms
1036          * worst case: tmdsClock == 25MHz => config <= 19
1037          */
1038         hdmi_writel(hdmi_dev, FC_EXCTRLSPAC,
1039                     (hdmi_dev->tmdsclk / 1000) * 50 / (256 * 512));
1040
1041         hdmi_writel(hdmi_dev, FC_PRCONF,
1042                     v_FC_PR_FACTOR(timing->pixelrepeat) |
1043                     v_FC_PR_FACTOR_OUT(timing->pixelrepeat - 1));
1044
1045         return 0;
1046 }
1047
1048 static int rockchip_hdmiv2_video_packetizer(struct hdmi_dev *hdmi_dev,
1049                                             struct hdmi_video *vpara)
1050 {
1051         unsigned char color_depth = COLOR_DEPTH_24BIT_DEFAULT;
1052         unsigned char output_select = 0;
1053         unsigned char remap_size = 0;
1054
1055         if (vpara->color_output == HDMI_COLOR_YCBCR422) {
1056                 switch (vpara->color_output_depth) {
1057                 case 8:
1058                         remap_size = YCC422_16BIT;
1059                         break;
1060                 case 10:
1061                         remap_size = YCC422_20BIT;
1062                         break;
1063                 case 12:
1064                         remap_size = YCC422_24BIT;
1065                         break;
1066                 default:
1067                         remap_size = YCC422_16BIT;
1068                         break;
1069                 }
1070
1071                 output_select = OUT_FROM_YCC422_REMAP;
1072                 /*Config remap size for the different color Depth*/
1073                 hdmi_msk_reg(hdmi_dev, VP_REMAP,
1074                              m_YCC422_SIZE, v_YCC422_SIZE(remap_size));
1075         } else {
1076                 switch (vpara->color_output_depth) {
1077                 case 10:
1078                         color_depth = COLOR_DEPTH_30BIT;
1079                         output_select = OUT_FROM_PIXEL_PACKING;
1080                         break;
1081                 case 12:
1082                         color_depth = COLOR_DEPTH_36BIT;
1083                         output_select = OUT_FROM_PIXEL_PACKING;
1084                         break;
1085                 case 16:
1086                         color_depth = COLOR_DEPTH_48BIT;
1087                         output_select = OUT_FROM_PIXEL_PACKING;
1088                         break;
1089                 case 8:
1090                 default:
1091                         color_depth = COLOR_DEPTH_24BIT_DEFAULT;
1092                         output_select = OUT_FROM_8BIT_BYPASS;
1093                         break;
1094                 }
1095         }
1096         /*Config Color Depth*/
1097         hdmi_msk_reg(hdmi_dev, VP_PR_CD,
1098                      m_COLOR_DEPTH, v_COLOR_DEPTH(color_depth));
1099         /*Config pixel repettion*/
1100         hdmi_msk_reg(hdmi_dev, VP_PR_CD, m_DESIRED_PR_FACTOR,
1101                      v_DESIRED_PR_FACTOR(hdmi_dev->pixelrepeat - 1));
1102         if (hdmi_dev->pixelrepeat > 1)
1103                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1104                              m_PIXEL_REPET_EN | m_BYPASS_SEL,
1105                              v_PIXEL_REPET_EN(1) | v_BYPASS_SEL(0));
1106         else
1107                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1108                              m_PIXEL_REPET_EN | m_BYPASS_SEL,
1109                              v_PIXEL_REPET_EN(0) | v_BYPASS_SEL(1));
1110
1111         /*config output select*/
1112         if (output_select == OUT_FROM_PIXEL_PACKING) { /* pixel packing */
1113                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1114                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1115                              m_YCC422_EN | m_OUTPUT_SEL,
1116                              v_BYPASS_EN(0) | v_PIXEL_PACK_EN(1) |
1117                              v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
1118         } else if (output_select == OUT_FROM_YCC422_REMAP) { /* YCC422 */
1119                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1120                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1121                              m_YCC422_EN | m_OUTPUT_SEL,
1122                              v_BYPASS_EN(0) | v_PIXEL_PACK_EN(0) |
1123                              v_YCC422_EN(1) | v_OUTPUT_SEL(output_select));
1124         } else if (output_select == OUT_FROM_8BIT_BYPASS ||
1125                    output_select == 3) { /* bypass */
1126                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1127                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1128                              m_YCC422_EN | m_OUTPUT_SEL,
1129                              v_BYPASS_EN(1) | v_PIXEL_PACK_EN(0) |
1130                              v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
1131         }
1132
1133 #if defined(HDMI_VIDEO_STUFFING)
1134         /* YCC422 and pixel packing stuffing*/
1135         hdmi_msk_reg(hdmi_dev, VP_STUFF, m_PR_STUFFING, v_PR_STUFFING(1));
1136         hdmi_msk_reg(hdmi_dev, VP_STUFF,
1137                      m_YCC422_STUFFING | m_PP_STUFFING,
1138                      v_YCC422_STUFFING(1) | v_PP_STUFFING(1));
1139 #endif
1140         return 0;
1141 }
1142
1143 static int rockchip_hdmiv2_video_sampler(struct hdmi_dev *hdmi_dev,
1144                                          struct hdmi_video *vpara)
1145 {
1146         int map_code = 0;
1147
1148         if (vpara->color_input == HDMI_COLOR_YCBCR422) {
1149                 /* YCC422 mapping is discontinued - only map 1 is supported */
1150                 switch (vpara->color_output_depth) {
1151                 case 8:
1152                         map_code = VIDEO_YCBCR422_8BIT;
1153                         break;
1154                 case 10:
1155                         map_code = VIDEO_YCBCR422_10BIT;
1156                         break;
1157                 case 12:
1158                         map_code = VIDEO_YCBCR422_12BIT;
1159                         break;
1160                 default:
1161                         map_code = VIDEO_YCBCR422_8BIT;
1162                         break;
1163                 }
1164         } else if (vpara->color_input == HDMI_COLOR_YCBCR420 ||
1165                    vpara->color_input == HDMI_COLOR_YCBCR444) {
1166                 switch (vpara->color_output_depth) {
1167                 case 10:
1168                         map_code = VIDEO_YCBCR444_10BIT;
1169                         break;
1170                 case 12:
1171                         map_code = VIDEO_YCBCR444_12BIT;
1172                         break;
1173                 case 16:
1174                         map_code = VIDEO_YCBCR444_16BIT;
1175                         break;
1176                 case 8:
1177                 default:
1178                         map_code = VIDEO_YCBCR444_8BIT;
1179                         break;
1180                 }
1181         } else {
1182                 switch (vpara->color_output_depth) {
1183                 case 10:
1184                         map_code = VIDEO_RGB444_10BIT;
1185                         break;
1186                 case 12:
1187                         map_code = VIDEO_RGB444_12BIT;
1188                         break;
1189                 case 16:
1190                         map_code = VIDEO_RGB444_16BIT;
1191                         break;
1192                 case 8:
1193                 default:
1194                         map_code = VIDEO_RGB444_8BIT;
1195                         break;
1196                 }
1197                 map_code += (vpara->color_input == HDMI_COLOR_YCBCR444) ?
1198                             8 : 0;
1199         }
1200
1201         /* Set Data enable signal from external
1202          * and set video sample input mapping
1203          */
1204         hdmi_msk_reg(hdmi_dev, TX_INVID0,
1205                      m_INTERNAL_DE_GEN | m_VIDEO_MAPPING,
1206                      v_INTERNAL_DE_GEN(0) | v_VIDEO_MAPPING(map_code));
1207
1208 #if defined(HDMI_VIDEO_STUFFING)
1209         hdmi_writel(hdmi_dev, TX_GYDATA0, 0x00);
1210         hdmi_writel(hdmi_dev, TX_GYDATA1, 0x00);
1211         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1212                      m_GYDATA_STUFF, v_GYDATA_STUFF(1));
1213         hdmi_writel(hdmi_dev, TX_RCRDATA0, 0x00);
1214         hdmi_writel(hdmi_dev, TX_RCRDATA1, 0x00);
1215         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1216                      m_RCRDATA_STUFF, v_RCRDATA_STUFF(1));
1217         hdmi_writel(hdmi_dev, TX_BCBDATA0, 0x00);
1218         hdmi_writel(hdmi_dev, TX_BCBDATA1, 0x00);
1219         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1220                      m_BCBDATA_STUFF, v_BCBDATA_STUFF(1));
1221 #endif
1222         return 0;
1223 }
1224
1225 static const char coeff_csc[][24] = {
1226                 /*   G          R           B           Bias
1227                  *   A1    |    A2     |    A3     |    A4    |
1228                  *   B1    |    B2     |    B3     |    B4    |
1229                  *   C1    |    C2     |    C3     |    C4    |
1230                  */
1231         {       /* CSC_BYPASS */
1232                 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
1233                 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
1234                 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
1235         },
1236         {       /* CSC_RGB_0_255_TO_RGB_16_235_8BIT */
1237                 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,         /*G*/
1238                 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x00, 0x40,         /*R*/
1239                 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x00, 0x40,         /*B*/
1240         },
1241         {       /* CSC_RGB_0_255_TO_RGB_16_235_10BIT */
1242                 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,         /*G*/
1243                 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x01, 0x00,         /*R*/
1244                 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x01, 0x00,         /*B*/
1245         },
1246         {       /* CSC_RGB_0_255_TO_ITU601_16_235_8BIT */
1247                 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x00, 0x40,         /*Y*/
1248                 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x02, 0x00,         /*Cr*/
1249                 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x02, 0x00,         /*Cb*/
1250         },
1251         {       /* CSC_RGB_0_255_TO_ITU601_16_235_10BIT */
1252                 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x01, 0x00,         /*Y*/
1253                 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x08, 0x00,         /*Cr*/
1254                 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x08, 0x00,         /*Cb*/
1255         },
1256         {       /* CSC_RGB_0_255_TO_ITU709_16_235_8BIT */
1257                 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x00, 0x40,         /*Y*/
1258                 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x02, 0x00,         /*Cr*/
1259                 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x02, 0x00,         /*Cb*/
1260         },
1261         {       /* CSC_RGB_0_255_TO_ITU709_16_235_10BIT */
1262                 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x01, 0x00,         /*Y*/
1263                 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x08, 0x00,         /*Cr*/
1264                 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x08, 0x00,         /*Cb*/
1265         },
1266                 /* Y            Cr          Cb          Bias */
1267         {       /* CSC_ITU601_16_235_TO_RGB_0_255_8BIT */
1268                 0x20, 0x00, 0x69, 0x26, 0x74, 0xfd, 0x01, 0x0e,         /*G*/
1269                 0x20, 0x00, 0x2c, 0xdd, 0x00, 0x00, 0x7e, 0x9a,         /*R*/
1270                 0x20, 0x00, 0x00, 0x00, 0x38, 0xb4, 0x7e, 0x3b,         /*B*/
1271         },
1272         {       /* CSC_ITU709_16_235_TO_RGB_0_255_8BIT */
1273                 0x20, 0x00, 0x71, 0x06, 0x7a, 0x02, 0x00, 0xa7,         /*G*/
1274                 0x20, 0x00, 0x32, 0x64, 0x00, 0x00, 0x7e, 0x6d,         /*R*/
1275                 0x20, 0x00, 0x00, 0x00, 0x3b, 0x61, 0x7e, 0x25,         /*B*/
1276         },
1277 };
1278
1279 static int rockchip_hdmiv2_video_csc(struct hdmi_dev *hdmi_dev,
1280                                      struct hdmi_video *vpara)
1281 {
1282         int i, mode, interpolation, decimation, csc_scale = 0;
1283         const char *coeff = NULL;
1284         unsigned char color_depth = 0;
1285
1286         if (vpara->color_input == vpara->color_output) {
1287                 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1288                              m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(0));
1289                 return 0;
1290         }
1291
1292         if (vpara->color_input == HDMI_COLOR_YCBCR422 &&
1293             vpara->color_output != HDMI_COLOR_YCBCR422 &&
1294             vpara->color_output != HDMI_COLOR_YCBCR420) {
1295                 interpolation = 1;
1296                 hdmi_msk_reg(hdmi_dev, CSC_CFG,
1297                              m_CSC_INTPMODE, v_CSC_INTPMODE(interpolation));
1298         }
1299
1300         if ((vpara->color_input == HDMI_COLOR_RGB_0_255 ||
1301              vpara->color_input == HDMI_COLOR_YCBCR444) &&
1302              vpara->color_output == HDMI_COLOR_YCBCR422) {
1303                 decimation = 1;
1304                 hdmi_msk_reg(hdmi_dev, CSC_CFG,
1305                              m_CSC_DECIMODE, v_CSC_DECIMODE(decimation));
1306         }
1307
1308         mode = CSC_BYPASS;
1309         csc_scale = 0;
1310
1311         switch (vpara->vic) {
1312         case HDMI_720X480I_60HZ_4_3:
1313         case HDMI_720X576I_50HZ_4_3:
1314         case HDMI_720X480P_60HZ_4_3:
1315         case HDMI_720X576P_50HZ_4_3:
1316         case HDMI_720X480I_60HZ_16_9:
1317         case HDMI_720X576I_50HZ_16_9:
1318         case HDMI_720X480P_60HZ_16_9:
1319         case HDMI_720X576P_50HZ_16_9:
1320                 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
1321                     vpara->color_output >= HDMI_COLOR_YCBCR444) {
1322                         mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
1323                         csc_scale = 0;
1324                 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
1325                            vpara->color_output == HDMI_COLOR_RGB_0_255) {
1326                         mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT;
1327                         csc_scale = 1;
1328                 }
1329                 break;
1330         default:
1331                 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
1332                     vpara->color_output >= HDMI_COLOR_YCBCR444) {
1333                         mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
1334                         csc_scale = 0;
1335                 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
1336                            vpara->color_output == HDMI_COLOR_RGB_0_255) {
1337                         mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT;
1338                         csc_scale = 1;
1339                 }
1340                 break;
1341         }
1342
1343         if ((vpara->color_input == HDMI_COLOR_RGB_0_255) &&
1344             (vpara->color_output == HDMI_COLOR_RGB_16_235)) {
1345                 mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
1346                 csc_scale = 0;
1347         }
1348
1349         switch (vpara->color_output_depth) {
1350         case 10:
1351                 color_depth = COLOR_DEPTH_30BIT;
1352                 mode += 1;
1353                 break;
1354         case 12:
1355                 color_depth = COLOR_DEPTH_36BIT;
1356                 mode += 2;
1357                 break;
1358         case 16:
1359                 color_depth = COLOR_DEPTH_48BIT;
1360                 mode += 3;
1361                 break;
1362         case 8:
1363         default:
1364                 color_depth = COLOR_DEPTH_24BIT;
1365                 break;
1366         }
1367
1368         coeff = coeff_csc[mode];
1369         for (i = 0; i < 24; i++)
1370                 hdmi_writel(hdmi_dev, CSC_COEF_A1_MSB + i, coeff[i]);
1371
1372         hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1373                      m_CSC_SCALE, v_CSC_SCALE(csc_scale));
1374         /*config CSC_COLOR_DEPTH*/
1375         hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1376                      m_CSC_COLOR_DEPTH, v_CSC_COLOR_DEPTH(color_depth));
1377
1378         /* enable CSC */
1379         hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1380                      m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(1));
1381
1382         return 0;
1383 }
1384
1385 static int hdmi_dev_detect_hotplug(struct hdmi *hdmi)
1386 {
1387         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1388         u32 value;
1389
1390         value = hdmi_readl(hdmi_dev, PHY_STAT0);
1391         HDMIDBG(2, "[%s] reg%x value %02x\n", __func__, PHY_STAT0, value);
1392         if (value & m_PHY_HPD)
1393                 return HDMI_HPD_ACTIVED;
1394
1395         return HDMI_HPD_REMOVED;
1396 }
1397
1398 static int hdmi_dev_read_edid(struct hdmi *hdmi, int block, unsigned char *buff)
1399 {
1400         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1401         int i = 0, n = 0, index = 0, ret = -1, trytime = 5;
1402         int offset = (block % 2) * 0x80;
1403         int interrupt = 0;
1404
1405         HDMIDBG(2, "[%s] block %d\n", __func__, block);
1406
1407         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
1408
1409         /* Set DDC I2C CLK which divided from DDC_CLK to 100KHz. */
1410         rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
1411
1412         /* Enable I2C interrupt for reading edid */
1413         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);
1414
1415         hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_EDID_ADDR);
1416         hdmi_writel(hdmi_dev, I2CM_SEGADDR, DDC_I2C_SEG_ADDR);
1417         hdmi_writel(hdmi_dev, I2CM_SEGPTR, block / 2);
1418         for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
1419                 for (trytime = 0; trytime < 5; trytime++) {
1420                         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset + 8 * n);
1421                         /* enable extend sequential read operation */
1422                         if (block == 0)
1423                                 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1424                                              m_I2CM_RD8, v_I2CM_RD8(1));
1425                         else
1426                                 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1427                                              m_I2CM_RD8_EXT,
1428                                              v_I2CM_RD8_EXT(1));
1429
1430                         i = 20;
1431                         while (i--) {
1432                                 usleep_range(900, 1000);
1433                                 interrupt = hdmi_readl(hdmi_dev,
1434                                                        IH_I2CM_STAT0);
1435                                 if (interrupt)
1436                                         hdmi_writel(hdmi_dev,
1437                                                     IH_I2CM_STAT0, interrupt);
1438
1439                                 if (interrupt &
1440                                     (m_SCDC_READREQ | m_I2CM_DONE |
1441                                      m_I2CM_ERROR))
1442                                         break;
1443                         }
1444
1445                         if (interrupt & m_I2CM_DONE) {
1446                                 for (index = 0; index < 8; index++)
1447                                         buff[8 * n + index] =
1448                                                 hdmi_readl(hdmi_dev,
1449                                                            I2CM_READ_BUFF0 +
1450                                                            index);
1451
1452                                 if (n == HDMI_EDID_BLOCK_SIZE / 8 - 1) {
1453                                         ret = 0;
1454                                         goto exit;
1455                                 }
1456                                 break;
1457                         } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
1458                                 dev_err(hdmi->dev,
1459                                         "[%s] edid read %d error\n",
1460                                         __func__, offset + 8 * n);
1461                         }
1462                 }
1463                 if (trytime == 5) {
1464                         dev_err(hdmi->dev,
1465                                 "[%s] edid read error\n", __func__);
1466                         break;
1467                 }
1468         }
1469
1470 exit:
1471         /* Disable I2C interrupt */
1472         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
1473         return ret;
1474 }
1475
1476 static void hdmi_dev_config_avi(struct hdmi_dev *hdmi_dev,
1477                                 struct hdmi_video *vpara)
1478 {
1479         unsigned char colorimetry, ext_colorimetry = 0, aspect_ratio, y1y0;
1480         unsigned char rgb_quan_range = AVI_QUANTIZATION_RANGE_DEFAULT;
1481
1482         hdmi_msk_reg(hdmi_dev, FC_DATAUTO3, m_AVI_AUTO, v_AVI_AUTO(0));
1483         hdmi_msk_reg(hdmi_dev, IH_FC_STAT1,
1484                      m_AVI_INFOFRAME, v_AVI_INFOFRAME(1));
1485         /* Set AVI infoFrame Data byte1 */
1486         if (vpara->color_output == HDMI_COLOR_YCBCR444)
1487                 y1y0 = AVI_COLOR_MODE_YCBCR444;
1488         else if (vpara->color_output == HDMI_COLOR_YCBCR422)
1489                 y1y0 = AVI_COLOR_MODE_YCBCR422;
1490         else if (vpara->color_output == HDMI_COLOR_YCBCR420)
1491                 y1y0 = AVI_COLOR_MODE_YCBCR420;
1492         else
1493                 y1y0 = AVI_COLOR_MODE_RGB;
1494
1495         hdmi_msk_reg(hdmi_dev, FC_AVICONF0,
1496                      m_FC_ACTIV_FORMAT | m_FC_RGC_YCC,
1497                      v_FC_RGC_YCC(y1y0) | v_FC_ACTIV_FORMAT(1));
1498
1499         /* Set AVI infoFrame Data byte2 */
1500         switch (vpara->vic) {
1501         case HDMI_720X480I_60HZ_4_3:
1502         case HDMI_720X576I_50HZ_4_3:
1503         case HDMI_720X480P_60HZ_4_3:
1504         case HDMI_720X576P_50HZ_4_3:
1505                 aspect_ratio = AVI_CODED_FRAME_ASPECT_4_3;
1506                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1507                         colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1508                 break;
1509         case HDMI_720X480I_60HZ_16_9:
1510         case HDMI_720X576I_50HZ_16_9:
1511         case HDMI_720X480P_60HZ_16_9:
1512         case HDMI_720X576P_50HZ_16_9:
1513                 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1514                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1515                         colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1516                 break;
1517         default:
1518                 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1519                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1520                         colorimetry = AVI_COLORIMETRY_ITU709;
1521         }
1522
1523         if (vpara->colorimetry > HDMI_COLORIMETRY_ITU709) {
1524                 colorimetry = AVI_COLORIMETRY_EXTENDED;
1525                 ext_colorimetry = vpara->colorimetry;
1526         } else if (vpara->color_output == HDMI_COLOR_RGB_16_235 ||
1527                  vpara->color_output == HDMI_COLOR_RGB_0_255) {
1528                 colorimetry = AVI_COLORIMETRY_NO_DATA;
1529         } else if (vpara->colorimetry != HDMI_COLORIMETRY_NO_DATA) {
1530                 colorimetry = vpara->colorimetry;
1531         }
1532
1533         hdmi_writel(hdmi_dev, FC_AVICONF1,
1534                     v_FC_COLORIMETRY(colorimetry) |
1535                     v_FC_PIC_ASPEC_RATIO(aspect_ratio) |
1536                     v_FC_ACT_ASPEC_RATIO(ACTIVE_ASPECT_RATE_DEFAULT));
1537
1538         /* Set AVI infoFrame Data byte3 */
1539         hdmi_msk_reg(hdmi_dev, FC_AVICONF2,
1540                      m_FC_EXT_COLORIMETRY | m_FC_QUAN_RANGE,
1541                      v_FC_EXT_COLORIMETRY(ext_colorimetry) |
1542                      v_FC_QUAN_RANGE(rgb_quan_range));
1543
1544         /* Set AVI infoFrame Data byte4 */
1545         if ((vpara->vic > 92 && vpara->vic < 96) ||
1546             (vpara->vic == 98) ||
1547             (vpara->vic & HDMI_VIDEO_DMT) ||
1548             (vpara->vic & HDMI_VIDEO_DISCRETE_VR))
1549                 hdmi_writel(hdmi_dev, FC_AVIVID, 0);
1550         else
1551                 hdmi_writel(hdmi_dev, FC_AVIVID, vpara->vic & 0xff);
1552         /* Set AVI infoFrame Data byte5 */
1553         hdmi_msk_reg(hdmi_dev, FC_AVICONF3, m_FC_YQ | m_FC_CN,
1554                      v_FC_YQ(YQ_LIMITED_RANGE) | v_FC_CN(CN_GRAPHICS));
1555         hdmi_msk_reg(hdmi_dev, FC_DATAUTO3, m_AVI_AUTO, v_AVI_AUTO(1));
1556 }
1557
1558 static int hdmi_dev_config_vsi(struct hdmi *hdmi,
1559                                unsigned char vic_3d, unsigned char format)
1560 {
1561         int i = 0, id = 0x000c03;
1562         unsigned char data[3] = {0};
1563
1564         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1565
1566         HDMIDBG(2, "[%s] vic %d format %d.\n", __func__, vic_3d, format);
1567
1568         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(0));
1569         hdmi_writel(hdmi_dev, FC_VSDIEEEID2, id & 0xff);
1570         hdmi_writel(hdmi_dev, FC_VSDIEEEID1, (id >> 8) & 0xff);
1571         hdmi_writel(hdmi_dev, FC_VSDIEEEID0, (id >> 16) & 0xff);
1572
1573         data[0] = format << 5;  /* PB4 --HDMI_Video_Format */
1574         switch (format) {
1575         case HDMI_VIDEO_FORMAT_4KX2K:
1576                 data[1] = vic_3d;       /* PB5--HDMI_VIC */
1577                 data[2] = 0;
1578                 break;
1579         case HDMI_VIDEO_FORMAT_3D:
1580                 data[1] = vic_3d << 4;  /* PB5--3D_Structure field */
1581                 data[2] = 0;            /* PB6--3D_Ext_Data field */
1582                 break;
1583         default:
1584                 data[1] = 0;
1585                 data[2] = 0;
1586                 break;
1587         }
1588
1589         for (i = 0; i < 3; i++)
1590                 hdmi_writel(hdmi_dev, FC_VSDPAYLOAD0 + i, data[i]);
1591         hdmi_writel(hdmi_dev, FC_VSDSIZE, 0x6);
1592
1593         hdmi_writel(hdmi_dev, FC_DATAUTO1, 0);
1594         hdmi_writel(hdmi_dev, FC_DATAUTO2, 0x11);
1595         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(1));
1596         return 0;
1597 }
1598
1599 static int hdmi_dev_config_spd(struct hdmi *hdmi, const char *vendor,
1600                                const char *product, char deviceinfo)
1601 {
1602         struct hdmi_dev *hdmi_dev;
1603         int i, len;
1604
1605         if (!hdmi || !vendor || !product)
1606                 return -1;
1607         hdmi_dev = hdmi->property->priv;
1608
1609         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_SPD_AUTO, v_SPD_AUTO(0));
1610         len = strlen(vendor);
1611         for (i = 0; i < 8; i++) {
1612                 if (i < len)
1613                         hdmi_writel(hdmi_dev, FC_SPDVENDORNAME0 + i,
1614                                     vendor[i]);
1615                 else
1616                         hdmi_writel(hdmi_dev, FC_SPDVENDORNAME0 + i,
1617                                     0);
1618         }
1619         len = strlen(product);
1620         for (i = 0; i < 16; i++) {
1621                 if (i < len)
1622                         hdmi_writel(hdmi_dev, FC_SPDPRODUCTNAME0 + i,
1623                                     product[i]);
1624                 else
1625                         hdmi_writel(hdmi_dev, FC_SPDPRODUCTNAME0 + i,
1626                                     0);
1627         }
1628         hdmi_writel(hdmi_dev, FC_SPDDEVICEINF, deviceinfo);
1629         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_SPD_AUTO, v_SPD_AUTO(1));
1630         return 0;
1631 }
1632
1633 static int hdmi_dev_config_video(struct hdmi *hdmi, struct hdmi_video *vpara)
1634 {
1635         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1636
1637         HDMIDBG(2, "%s vic %d 3dformat %d color mode %d color depth %d\n",
1638                 __func__, vpara->vic, vpara->format_3d,
1639                 vpara->color_output, vpara->color_output_depth);
1640
1641         if (hdmi_dev->soctype == HDMI_SOC_RK3288)
1642                 vpara->color_input = HDMI_COLOR_RGB_0_255;
1643
1644         if (!hdmi->uboot) {
1645                 /* before configure video, we power off phy */
1646                 if (hdmi_dev->soctype != HDMI_SOC_RK322X) {
1647                         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1648                                      m_PDDQ_SIG | m_TXPWRON_SIG,
1649                                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1650                 } else {
1651                         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1652                                      m_ENHPD_RXSENSE_SIG,
1653                                      v_ENHPD_RXSENSE_SIG(1));
1654                         regmap_write(hdmi_dev->grf_base,
1655                                      RK322X_GRF_SOC_CON2,
1656                                      RK322X_PLL_POWER_DOWN);
1657                 }
1658                 /* force output blue */
1659                 if (vpara->color_output == HDMI_COLOR_RGB_0_255) {
1660                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x00);       /*R*/
1661                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x00);       /*G*/
1662                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x00);       /*B*/
1663                 } else if (vpara->color_output == HDMI_COLOR_RGB_16_235) {
1664                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x10);       /*R*/
1665                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10);       /*G*/
1666                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x10);       /*B*/
1667                 } else {
1668                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x80);       /*Cr*/
1669                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10);       /*Y*/
1670                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x80);       /*Cb*/
1671                 }
1672                 hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1673                              m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1674                 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1675         }
1676
1677         if (rockchip_hdmiv2_video_framecomposer(hdmi, vpara) < 0)
1678                 return -1;
1679
1680         if (rockchip_hdmiv2_video_packetizer(hdmi_dev, vpara) < 0)
1681                 return -1;
1682         /* Color space convert */
1683         if (rockchip_hdmiv2_video_csc(hdmi_dev, vpara) < 0)
1684                 return -1;
1685         if (rockchip_hdmiv2_video_sampler(hdmi_dev, vpara) < 0)
1686                 return -1;
1687
1688         if (vpara->sink_hdmi == OUTPUT_HDMI) {
1689                 hdmi_dev_config_avi(hdmi_dev, vpara);
1690                 hdmi_dev_config_spd(hdmi, hdmi_dev->vendor_name,
1691                                     hdmi_dev->product_name,
1692                                     hdmi_dev->deviceinfo);
1693                 if (vpara->format_3d != HDMI_3D_NONE) {
1694                         hdmi_dev_config_vsi(hdmi,
1695                                             vpara->format_3d,
1696                                             HDMI_VIDEO_FORMAT_3D);
1697                 } else if ((vpara->vic > 92 && vpara->vic < 96) ||
1698                          (vpara->vic == 98)) {
1699                         vpara->vic = (vpara->vic == 98) ?
1700                                      4 : (96 - vpara->vic);
1701                         hdmi_dev_config_vsi(hdmi,
1702                                             vpara->vic,
1703                                             HDMI_VIDEO_FORMAT_4KX2K);
1704                 } else {
1705                         hdmi_dev_config_vsi(hdmi,
1706                                             vpara->vic,
1707                                             HDMI_VIDEO_FORMAT_NORMAL);
1708                 }
1709                 dev_info(hdmi->dev, "[%s] success output HDMI.\n", __func__);
1710         } else {
1711                 dev_info(hdmi->dev, "[%s] success output DVI.\n", __func__);
1712         }
1713
1714         if (!hdmi->uboot)
1715                 rockchip_hdmiv2_config_phy(hdmi_dev);
1716         else
1717                 hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(0));
1718         return 0;
1719 }
1720
1721 static void hdmi_dev_config_aai(struct hdmi_dev *hdmi_dev,
1722                                 struct hdmi_audio *audio)
1723 {
1724         /* Refer to CEA861-E Audio infoFrame
1725          * Set both Audio Channel Count and Audio Coding
1726          * Type Refer to Stream Head for HDMI
1727          */
1728         hdmi_msk_reg(hdmi_dev, FC_AUDICONF0,
1729                      m_FC_CHN_CNT | m_FC_CODING_TYPE,
1730                      v_FC_CHN_CNT(audio->channel - 1) | v_FC_CODING_TYPE(0));
1731
1732         /* Set both Audio Sample Size and Sample Frequency
1733          * Refer to Stream Head for HDMI
1734          */
1735         hdmi_msk_reg(hdmi_dev, FC_AUDICONF1,
1736                      m_FC_SAMPLE_SIZE | m_FC_SAMPLE_FREQ,
1737                      v_FC_SAMPLE_SIZE(0) | v_FC_SAMPLE_FREQ(0));
1738
1739         /* Set Channel Allocation */
1740         hdmi_writel(hdmi_dev, FC_AUDICONF2, 0x00);
1741
1742         /* Set LFEPBLDOWN-MIX INH and LSV */
1743         hdmi_writel(hdmi_dev, FC_AUDICONF3, 0x00);
1744 }
1745
1746 static int hdmi_dev_config_audio(struct hdmi *hdmi, struct hdmi_audio *audio)
1747 {
1748         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1749         int word_length = 0, channel = 0, mclk_fs;
1750         unsigned int N = 0, CTS = 0;
1751         int rate = 0;
1752         char design_id;
1753
1754         HDMIDBG(2, "%s\n", __func__);
1755
1756         if (audio->channel < 3)
1757                 channel = I2S_CHANNEL_1_2;
1758         else if (audio->channel < 5)
1759                 channel = I2S_CHANNEL_3_4;
1760         else if (audio->channel < 7)
1761                 channel = I2S_CHANNEL_5_6;
1762         else
1763                 channel = I2S_CHANNEL_7_8;
1764
1765         switch (audio->rate) {
1766         case HDMI_AUDIO_FS_32000:
1767                 mclk_fs = FS_128;
1768                 rate = AUDIO_32K;
1769                 if (hdmi_dev->tmdsclk >= 594000000)
1770                         N = N_32K_HIGHCLK;
1771                 else if (hdmi_dev->tmdsclk >= 297000000)
1772                         N = N_32K_MIDCLK;
1773                 else
1774                         N = N_32K_LOWCLK;
1775                 /*div a num to avoid the value is exceed 2^32(int)*/
1776                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 32);
1777                 break;
1778         case HDMI_AUDIO_FS_44100:
1779                 mclk_fs = FS_128;
1780                 rate = AUDIO_441K;
1781                 if (hdmi_dev->tmdsclk >= 594000000)
1782                         N = N_441K_HIGHCLK;
1783                 else if (hdmi_dev->tmdsclk >= 297000000)
1784                         N = N_441K_MIDCLK;
1785                 else
1786                         N = N_441K_LOWCLK;
1787
1788                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 100, 441);
1789                 break;
1790         case HDMI_AUDIO_FS_48000:
1791                 mclk_fs = FS_128;
1792                 rate = AUDIO_48K;
1793                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1794                         N = N_48K_HIGHCLK;
1795                 else if (hdmi_dev->tmdsclk >= 297000000)
1796                         N = N_48K_MIDCLK;
1797                 else
1798                         N = N_48K_LOWCLK;
1799
1800                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 48);
1801                 break;
1802         case HDMI_AUDIO_FS_88200:
1803                 mclk_fs = FS_128;
1804                 rate = AUDIO_882K;
1805                 if (hdmi_dev->tmdsclk >= 594000000)
1806                         N = N_882K_HIGHCLK;
1807                 else if (hdmi_dev->tmdsclk >= 297000000)
1808                         N = N_882K_MIDCLK;
1809                 else
1810                         N = N_882K_LOWCLK;
1811
1812                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 100, 882);
1813                 break;
1814         case HDMI_AUDIO_FS_96000:
1815                 mclk_fs = FS_128;
1816                 rate = AUDIO_96K;
1817                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1818                         N = N_96K_HIGHCLK;
1819                 else if (hdmi_dev->tmdsclk >= 297000000)
1820                         N = N_96K_MIDCLK;
1821                 else
1822                         N = N_96K_LOWCLK;
1823
1824                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 96);
1825                 break;
1826         case HDMI_AUDIO_FS_176400:
1827                 mclk_fs = FS_128;
1828                 rate = AUDIO_1764K;
1829                 if (hdmi_dev->tmdsclk >= 594000000)
1830                         N = N_1764K_HIGHCLK;
1831                 else if (hdmi_dev->tmdsclk >= 297000000)
1832                         N = N_1764K_MIDCLK;
1833                 else
1834                         N = N_1764K_LOWCLK;
1835
1836                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 100, 1764);
1837                 break;
1838         case HDMI_AUDIO_FS_192000:
1839                 mclk_fs = FS_128;
1840                 rate = AUDIO_192K;
1841                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1842                         N = N_192K_HIGHCLK;
1843                 else if (hdmi_dev->tmdsclk >= 297000000)
1844                         N = N_192K_MIDCLK;
1845                 else
1846                         N = N_192K_LOWCLK;
1847
1848                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 192);
1849                 break;
1850         default:
1851                 dev_err(hdmi_dev->hdmi->dev,
1852                         "[%s] not support such sample rate %d\n",
1853                         __func__, audio->rate);
1854                 return -ENOENT;
1855         }
1856
1857         switch (audio->word_length) {
1858         case HDMI_AUDIO_WORD_LENGTH_16bit:
1859                 word_length = I2S_16BIT_SAMPLE;
1860                 break;
1861         case HDMI_AUDIO_WORD_LENGTH_20bit:
1862                 word_length = I2S_20BIT_SAMPLE;
1863                 break;
1864         case HDMI_AUDIO_WORD_LENGTH_24bit:
1865                 word_length = I2S_24BIT_SAMPLE;
1866                 break;
1867         default:
1868                 word_length = I2S_16BIT_SAMPLE;
1869         }
1870
1871         HDMIDBG(2, "rate = %d, tmdsclk = %u, N = %d, CTS = %d\n",
1872                 audio->rate, hdmi_dev->tmdsclk, N, CTS);
1873         /* more than 2 channels => layout 1 else layout 0 */
1874         hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1875                      m_AUD_PACK_LAYOUT,
1876                      v_AUD_PACK_LAYOUT((audio->channel > 2) ? 1 : 0));
1877
1878         if (hdmi_dev->audiosrc == HDMI_AUDIO_SRC_SPDIF) {
1879                 mclk_fs = FS_128;
1880                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1881                              m_I2S_SEL, v_I2S_SEL(AUDIO_SPDIF_GPA));
1882                 hdmi_msk_reg(hdmi_dev, AUD_SPDIF1,
1883                              m_SET_NLPCM | m_SPDIF_WIDTH,
1884                              v_SET_NLPCM(PCM_LINEAR) |
1885                              v_SPDIF_WIDTH(word_length));
1886                 /*Mask fifo empty and full int and reset fifo*/
1887                 hdmi_msk_reg(hdmi_dev, AUD_SPDIFINT,
1888                              m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1889                              v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1890                 hdmi_msk_reg(hdmi_dev, AUD_SPDIF0,
1891                              m_SW_SAUD_FIFO_RST, v_SW_SAUD_FIFO_RST(1));
1892         } else {
1893                 /*Mask fifo empty and full int and reset fifo*/
1894                 hdmi_msk_reg(hdmi_dev, AUD_INT,
1895                              m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1896                              v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1897                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1898                              m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1899                 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1900                 design_id = hdmi_readl(hdmi_dev, DESIGN_ID);
1901                 if (design_id >= 0x21)
1902                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x4);
1903                 else
1904                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1905                 usleep_range(90, 100);
1906                 /*
1907                  * when we try to use hdmi nlpcm mode
1908                  * we should use set AUD_CONF2 to open this route and set
1909                  * word_length to 24bit for b.p.c.u.v with 16bit raw data
1910                  * when the bitstream data  up to 8 channel, we should use
1911                  * the hdmi hbr mode
1912                  * HBR Mode : Dolby TrueHD
1913                  *            Dolby Atmos
1914                  *            DTS-HDMA
1915                  * NLPCM Mode :
1916                  * FS_32000 FS_44100 FS_48000 : Dolby Digital &  DTS
1917                  * FS_176400 FS_192000        : Dolby Digital Plus
1918                  */
1919                 if (audio->type == HDMI_AUDIO_NLPCM) {
1920                         if (channel == I2S_CHANNEL_7_8) {
1921                                 HDMIDBG(2, "hbr mode.\n");
1922                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x1);
1923                                 word_length = I2S_24BIT_SAMPLE;
1924                         } else if ((audio->rate == HDMI_AUDIO_FS_32000) ||
1925                                    (audio->rate == HDMI_AUDIO_FS_44100) ||
1926                                    (audio->rate == HDMI_AUDIO_FS_48000) ||
1927                                    (audio->rate == HDMI_AUDIO_FS_176400) ||
1928                                    (audio->rate == HDMI_AUDIO_FS_192000)) {
1929                                 HDMIDBG(2, "nlpcm mode.\n");
1930                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x2);
1931                                 word_length = I2S_24BIT_SAMPLE;
1932                         } else {
1933                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1934                         }
1935                 } else {
1936                         if (design_id >= 0x21)
1937                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x4);
1938                         else
1939                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1940                 }
1941                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1942                              m_I2S_SEL | m_I2S_IN_EN,
1943                              v_I2S_SEL(AUDIO_I2S) | v_I2S_IN_EN(channel));
1944                 hdmi_writel(hdmi_dev, AUD_CONF1,
1945                             v_I2S_MODE(I2S_STANDARD_MODE) |
1946                             v_I2S_WIDTH(word_length));
1947         }
1948
1949         hdmi_msk_reg(hdmi_dev, AUD_INPUTCLKFS,
1950                      m_LFS_FACTOR, v_LFS_FACTOR(mclk_fs));
1951
1952         /*Set N value*/
1953         hdmi_msk_reg(hdmi_dev, AUD_N3, m_NCTS_ATOMIC_WR, v_NCTS_ATOMIC_WR(1));
1954         /*Set CTS by manual*/
1955         hdmi_msk_reg(hdmi_dev, AUD_CTS3,
1956                      m_N_SHIFT | m_CTS_MANUAL | m_AUD_CTS3,
1957                      v_N_SHIFT(N_SHIFT_1) |
1958                      v_CTS_MANUAL(1) |
1959                      v_AUD_CTS3(CTS >> 16));
1960         hdmi_writel(hdmi_dev, AUD_CTS2, (CTS >> 8) & 0xff);
1961         hdmi_writel(hdmi_dev, AUD_CTS1, CTS & 0xff);
1962
1963         hdmi_msk_reg(hdmi_dev, AUD_N3, m_AUD_N3, v_AUD_N3(N >> 16));
1964         hdmi_writel(hdmi_dev, AUD_N2, (N >> 8) & 0xff);
1965         hdmi_writel(hdmi_dev, AUD_N1, N & 0xff);
1966
1967         /* set channel status register */
1968         hdmi_msk_reg(hdmi_dev, FC_AUDSCHNLS7,
1969                      m_AUDIO_SAMPLE_RATE, v_AUDIO_SAMPLE_RATE(rate));
1970         hdmi_writel(hdmi_dev, FC_AUDSCHNLS8, ((~rate) << 4) | 0x2);
1971
1972         hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1973                      m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1974
1975         hdmi_dev_config_aai(hdmi_dev, audio);
1976
1977         return 0;
1978 }
1979
1980 static int hdmi_dev_control_output(struct hdmi *hdmi, int enable)
1981 {
1982         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1983         struct hdmi_video vpara;
1984
1985         HDMIDBG(2, "[%s] %d\n", __func__, enable);
1986         if (enable == HDMI_AV_UNMUTE) {
1987                 hdmi_writel(hdmi_dev, FC_DBGFORCE, 0x00);
1988                 if (hdmi->edid.sink_hdmi == OUTPUT_HDMI)
1989                         hdmi_msk_reg(hdmi_dev, FC_GCP,
1990                                      m_FC_SET_AVMUTE | m_FC_CLR_AVMUTE,
1991                                      v_FC_SET_AVMUTE(0) | v_FC_CLR_AVMUTE(1));
1992         } else {
1993                 if (enable & HDMI_VIDEO_MUTE) {
1994                         hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1995                                      m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1996                         if (hdmi->edid.sink_hdmi == OUTPUT_HDMI) {
1997                                 hdmi_msk_reg(hdmi_dev, FC_GCP,
1998                                              m_FC_SET_AVMUTE |
1999                                              m_FC_CLR_AVMUTE,
2000                                              v_FC_SET_AVMUTE(1) |
2001                                              v_FC_CLR_AVMUTE(0));
2002                                 vpara.vic = hdmi->vic;
2003                                 vpara.color_output = HDMI_COLOR_RGB_0_255;
2004                                 hdmi_dev_config_avi(hdmi_dev, &vpara);
2005                                 while ((!hdmi_readl(hdmi_dev, IH_FC_STAT1)) &
2006                                        m_AVI_INFOFRAME) {
2007                                         usleep_range(900, 1000);
2008                                 }
2009                         }
2010                 }
2011 /*              if (enable & HDMI_AUDIO_MUTE) {
2012  *                      hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
2013  *                                   m_AUD_PACK_SAMPFIT,
2014  *                                   v_AUD_PACK_SAMPFIT(0x0F));
2015  *              }
2016  */
2017                 if (enable == (HDMI_VIDEO_MUTE | HDMI_AUDIO_MUTE)) {
2018                         if (hdmi->ops->hdcp_power_off_cb)
2019                                 hdmi->ops->hdcp_power_off_cb(hdmi);
2020                         rockchip_hdmiv2_powerdown(hdmi_dev);
2021                 }
2022         }
2023         return 0;
2024 }
2025
2026 static int hdmi_dev_insert(struct hdmi *hdmi)
2027 {
2028         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2029
2030         HDMIDBG(2, "%s\n", __func__);
2031         if (!hdmi->uboot)
2032                 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
2033         return HDMI_ERROR_SUCCESS;
2034 }
2035
2036 static int hdmi_dev_remove(struct hdmi *hdmi)
2037 {
2038         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2039
2040         HDMIDBG(2, "%s\n", __func__);
2041         if (hdmi->ops->hdcp_power_off_cb)
2042                 hdmi->ops->hdcp_power_off_cb(hdmi);
2043         rockchip_hdmiv2_powerdown(hdmi_dev);
2044         hdmi_dev->tmdsclk = 0;
2045         return HDMI_ERROR_SUCCESS;
2046 }
2047
2048 static int hdmi_dev_enable(struct hdmi *hdmi)
2049 {
2050         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2051
2052         HDMIDBG(2, "%s\n", __func__);
2053         if (!hdmi_dev->enable) {
2054                 hdmi_writel(hdmi_dev, IH_MUTE, 0x00);
2055                 hdmi_dev->enable = 1;
2056         }
2057         hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 10, 0);
2058         return 0;
2059 }
2060
2061 static int hdmi_dev_disable(struct hdmi *hdmi)
2062 {
2063         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2064
2065         HDMIDBG(2, "%s\n", __func__);
2066         if (hdmi_dev->enable) {
2067                 hdmi_dev->enable = 0;
2068                 hdmi_writel(hdmi_dev, IH_MUTE, 0x1);
2069         }
2070         return 0;
2071 }
2072
2073 void rockchip_hdmiv2_dev_init_ops(struct hdmi_ops *ops)
2074 {
2075         if (ops) {
2076                 ops->enable     = hdmi_dev_enable;
2077                 ops->disable    = hdmi_dev_disable;
2078                 ops->getstatus  = hdmi_dev_detect_hotplug;
2079                 ops->insert     = hdmi_dev_insert;
2080                 ops->remove     = hdmi_dev_remove;
2081                 ops->getedid    = hdmi_dev_read_edid;
2082                 ops->setvideo   = hdmi_dev_config_video;
2083                 ops->setaudio   = hdmi_dev_config_audio;
2084                 ops->setmute    = hdmi_dev_control_output;
2085                 ops->setvsi     = hdmi_dev_config_vsi;
2086         }
2087 }
2088
2089 void rockchip_hdmiv2_dev_initial(struct hdmi_dev *hdmi_dev)
2090 {
2091         struct hdmi *hdmi = hdmi_dev->hdmi;
2092
2093         /*lcdc source select*/
2094         if (hdmi_dev->soctype == HDMI_SOC_RK3288) {
2095                 grf_writel(HDMI_SEL_LCDC(hdmi->property->videosrc, 4),
2096                            RK3288_GRF_SOC_CON6);
2097                 /* select GPIO7_C0 as cec pin */
2098                 grf_writel(((1 << 12) | (1 << 28)), RK3288_GRF_SOC_CON8);
2099         } else if (hdmi_dev->soctype == HDMI_SOC_RK3399) {
2100                 regmap_write(hdmi_dev->grf_base,
2101                              RK3399_GRF_SOC_CON20,
2102                              HDMI_SEL_LCDC(hdmi->property->videosrc, 6));
2103         }
2104
2105         if (!hdmi->uboot) {
2106                 pr_info("reset hdmi\n");
2107                 if (hdmi_dev->soctype == HDMI_SOC_RK3288) {
2108                         rk3288_cru_set_soft_reset(RK3288_SOFT_RST_HDMI, true);
2109                         usleep_range(10, 20);
2110                         rk3288_cru_set_soft_reset(RK3288_SOFT_RST_HDMI, false);
2111                 } else {
2112                         if (hdmi_dev->soctype == HDMI_SOC_RK322X) {
2113                                 regmap_write(hdmi_dev->grf_base,
2114                                              RK322X_GRF_SOC_CON2,
2115                                              RK322X_DDC_MASK_EN);
2116                                 regmap_write(hdmi_dev->grf_base,
2117                                              RK322X_GRF_SOC_CON6,
2118                                              RK322X_IO_3V_DOMAIN);
2119                         }
2120                         reset_control_assert(hdmi_dev->reset);
2121                         usleep_range(10, 20);
2122                         reset_control_deassert(hdmi_dev->reset);
2123                 }
2124                 rockchip_hdmiv2_powerdown(hdmi_dev);
2125         } else {
2126                 hdmi->hotplug = hdmi_dev_detect_hotplug(hdmi);
2127                 if (hdmi->hotplug != HDMI_HPD_ACTIVED)
2128                         hdmi->uboot = 0;
2129         }
2130         /*mute unnecessary interrupt, only enable hpd*/
2131         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT0, 0xff);
2132         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT1, 0xff);
2133         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT2, 0xff);
2134         hdmi_writel(hdmi_dev, IH_MUTE_AS_STAT0, 0xff);
2135         hdmi_writel(hdmi_dev, IH_MUTE_PHY_STAT0, 0xfc);
2136         hdmi_writel(hdmi_dev, IH_MUTE_I2CM_STAT0, 0xff);
2137         hdmi_writel(hdmi_dev, IH_MUTE_CEC_STAT0, 0xff);
2138         hdmi_writel(hdmi_dev, IH_MUTE_VP_STAT0, 0xff);
2139         hdmi_writel(hdmi_dev, IH_MUTE_I2CMPHY_STAT0, 0xff);
2140         hdmi_writel(hdmi_dev, IH_MUTE_AHBDMAAUD_STAT0, 0xff);
2141
2142         /* disable hdcp interrupt */
2143         hdmi_writel(hdmi_dev, A_APIINTMSK, 0xff);
2144         hdmi_writel(hdmi_dev, PHY_MASK, 0xf1);
2145
2146         if (hdmi->property->feature & SUPPORT_CEC)
2147                 rockchip_hdmiv2_cec_init(hdmi);
2148         if (hdmi->property->feature & SUPPORT_HDCP)
2149                 rockchip_hdmiv2_hdcp_init(hdmi);
2150 }
2151
2152 irqreturn_t rockchip_hdmiv2_dev_irq(int irq, void *priv)
2153 {
2154         struct hdmi_dev *hdmi_dev = priv;
2155         struct hdmi *hdmi = hdmi_dev->hdmi;
2156         char phy_pol = hdmi_readl(hdmi_dev, PHY_POL0);
2157         char phy_status = hdmi_readl(hdmi_dev, PHY_STAT0);
2158         char phy_int0 = hdmi_readl(hdmi_dev, PHY_INI0);
2159         /*read interrupt*/
2160         char fc_stat0 = hdmi_readl(hdmi_dev, IH_FC_STAT0);
2161         char fc_stat1 = hdmi_readl(hdmi_dev, IH_FC_STAT1);
2162         char fc_stat2 = hdmi_readl(hdmi_dev, IH_FC_STAT2);
2163         char aud_int = hdmi_readl(hdmi_dev, IH_AS_SATA0);
2164         char phy_int = hdmi_readl(hdmi_dev, IH_PHY_STAT0);
2165         char vp_stat0 = hdmi_readl(hdmi_dev, IH_VP_STAT0);
2166         char cec_int = hdmi_readl(hdmi_dev, IH_CEC_STAT0);
2167         char hdcp_int = hdmi_readl(hdmi_dev, A_APIINTSTAT);
2168         char hdcp2_int = hdmi_readl(hdmi_dev, HDCP2REG_STAT);
2169
2170         /*clear interrupt*/
2171         hdmi_writel(hdmi_dev, IH_FC_STAT0, fc_stat0);
2172         hdmi_writel(hdmi_dev, IH_FC_STAT1, fc_stat1);
2173         hdmi_writel(hdmi_dev, IH_FC_STAT2, fc_stat2);
2174         hdmi_writel(hdmi_dev, IH_VP_STAT0, vp_stat0);
2175
2176         if (phy_int0 || phy_int) {
2177                 if ((phy_int0 & m_PHY_LOCK) &&
2178                     (phy_pol & m_PHY_LOCK) == 0) {
2179                         pr_info("hdmi phy pll unlock\n");
2180                         hdmi_submit_work(hdmi, HDMI_SET_VIDEO, 0, 0);
2181                 }
2182                 phy_pol = (phy_int0 & (~phy_status)) | ((~phy_int0) & phy_pol);
2183                 hdmi_writel(hdmi_dev, PHY_POL0, phy_pol);
2184                 hdmi_writel(hdmi_dev, IH_PHY_STAT0, phy_int);
2185                 if ((phy_int & m_HPD) || ((phy_int & 0x3c) == 0x3c))
2186                         hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 20, 0);
2187         }
2188
2189         /* Audio error */
2190         if (aud_int) {
2191                 hdmi_writel(hdmi_dev, IH_AS_SATA0, aud_int);
2192                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
2193                              m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
2194                 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
2195         }
2196         /* CEC */
2197         if (cec_int) {
2198                 hdmi_writel(hdmi_dev, IH_CEC_STAT0, cec_int);
2199                 if (hdmi_dev->hdmi->property->feature & SUPPORT_CEC)
2200                         rockchip_hdmiv2_cec_isr(hdmi_dev, cec_int);
2201         }
2202         /* HDCP */
2203         if (hdcp_int) {
2204                 hdmi_writel(hdmi_dev, A_APIINTCLR, hdcp_int);
2205                 rockchip_hdmiv2_hdcp_isr(hdmi_dev, hdcp_int);
2206         }
2207
2208         /* HDCP2 */
2209         if (hdcp2_int) {
2210                 hdmi_writel(hdmi_dev, HDCP2REG_STAT, hdcp2_int);
2211                 pr_info("hdcp2_int is 0x%02x\n", hdcp2_int);
2212                 if ((hdcp2_int & m_HDCP2_AUTH_FAIL ||
2213                      hdcp2_int & m_HDCP2_AUTH_LOST) &&
2214                     hdmi_dev->hdcp2_start) {
2215                         pr_info("hdcp2 failed or lost\n");
2216                         hdmi_dev->hdcp2_start();
2217                 }
2218         }
2219         return IRQ_HANDLED;
2220 }