drivers/video/omap2/dss/hdmi_phy.c

   1 /*
   2  * HDMI PHY
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/delay.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/platform_device.h>
  16 #include <video/omapdss.h>
  17
  18 #include "dss.h"
  19 #include "ti_hdmi.h"
  20 #include "ti_hdmi_4xxx_ip.h"
  21
  22 #define HDMI_IRQ_LINK_CONNECT           (1 << 25)
  23 #define HDMI_IRQ_LINK_DISCONNECT        (1 << 26)
  24
  25 static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx,
  26                 u32 val)
  27 {
  28         __raw_writel(val, base_addr + idx);
  29 }
  30
  31 static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx)
  32 {
  33         return __raw_readl(base_addr + idx);
  34 }
  35
  36 #define REG_FLD_MOD(base, idx, val, start, end) \
  37         hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
  38                                                         val, start, end))
  39 #define REG_GET(base, idx, start, end) \
  40         FLD_GET(hdmi_read_reg(base, idx), start, end)
  41
  42 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
  43                 const u16 idx, int b2, int b1, u32 val)
  44 {
  45         u32 t = 0;
  46         while (val != REG_GET(base_addr, idx, b2, b1)) {
  47                 udelay(1);
  48                 if (t++ > 10000)
  49                         return !val;
  50         }
  51         return val;
  52 }
  53
  54 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s)
  55 {
  56 #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
  57                 hdmi_read_reg(phy->base, r))
  58
  59         DUMPPHY(HDMI_TXPHY_TX_CTRL);
  60         DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
  61         DUMPPHY(HDMI_TXPHY_POWER_CTRL);
  62         DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
  63 }
  64
  65 static irqreturn_t hdmi_irq_handler(int irq, void *data)
  66 {
  67         struct hdmi_wp_data *wp = data;
  68         u32 irqstatus;
  69
  70         irqstatus = hdmi_wp_get_irqstatus(wp);
  71         hdmi_wp_set_irqstatus(wp, irqstatus);
  72
  73         if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
  74                         irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  75                 /*
  76                  * If we get both connect and disconnect interrupts at the same
  77                  * time, turn off the PHY, clear interrupts, and restart, which
  78                  * raises connect interrupt if a cable is connected, or nothing
  79                  * if cable is not connected.
  80                  */
  81                 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
  82
  83                 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
  84                                 HDMI_IRQ_LINK_DISCONNECT);
  85
  86                 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  87         } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
  88                 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
  89         } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  90                 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  91         }
  92
  93         return IRQ_HANDLED;
  94 }
  95
  96 int hdmi_phy_enable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp,
  97                         struct hdmi_config *cfg)
  98 {
  99         u16 r = 0;
 100         u32 irqstatus;
 101
 102         hdmi_wp_clear_irqenable(wp, 0xffffffff);
 103
 104         irqstatus = hdmi_wp_get_irqstatus(wp);
 105         hdmi_wp_set_irqstatus(wp, irqstatus);
 106
 107         r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
 108         if (r)
 109                 return r;
 110
 111         /*
 112          * Read address 0 in order to get the SCP reset done completed
 113          * Dummy access performed to make sure reset is done
 114          */
 115         hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL);
 116
 117         /*
 118          * Write to phy address 0 to configure the clock
 119          * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
 120          */
 121         REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
 122
 123         /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
 124         hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
 125
 126         /* Setup max LDO voltage */
 127         REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
 128
 129         /* Write to phy address 3 to change the polarity control */
 130         REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
 131
 132         r = request_threaded_irq(phy->irq, NULL, hdmi_irq_handler,
 133                                 IRQF_ONESHOT, "OMAP HDMI", wp);
 134         if (r) {
 135                 DSSERR("HDMI IRQ request failed\n");
 136                 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
 137                 return r;
 138         }
 139
 140         hdmi_wp_set_irqenable(wp,
 141                 HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
 142
 143         return 0;
 144 }
 145
 146 void hdmi_phy_disable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp)
 147 {
 148         free_irq(phy->irq, wp);
 149
 150         hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
 151 }
 152
 153 #define PHY_OFFSET      0x300
 154 #define PHY_SIZE        0x100
 155
 156 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy)
 157 {
 158         struct resource *res;
 159         struct resource temp_res;
 160
 161         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_txphy");
 162         if (!res) {
 163                 DSSDBG("can't get PHY mem resource by name\n");
 164                 /*
 165                  * if hwmod/DT doesn't have the memory resource information
 166                  * split into HDMI sub blocks by name, we try again by getting
 167                  * the platform's first resource. this code will be removed when
 168                  * the driver can get the mem resources by name
 169                  */
 170                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 171                 if (!res) {
 172                         DSSERR("can't get PHY mem resource\n");
 173                         return -EINVAL;
 174                 }
 175
 176                 temp_res.start = res->start + PHY_OFFSET;
 177                 temp_res.end = temp_res.start + PHY_SIZE - 1;
 178                 res = &temp_res;
 179         }
 180
 181         phy->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 182         if (!phy->base) {
 183                 DSSERR("can't ioremap TX PHY\n");
 184                 return -ENOMEM;
 185         }
 186
 187         phy->irq = platform_get_irq(pdev, 0);
 188         if (phy->irq < 0) {
 189                 DSSERR("platform_get_irq failed\n");
 190                 return -ENODEV;
 191         }
 192
 193         return 0;
 194 }