drivers/video/omap2/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/io.h>
  27 #include <linux/err.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/clk.h>
  31
  32 #include <plat/display.h>
  33 #include <plat/clock.h>
  34 #include "dss.h"
  35 #include "dss_features.h"
  36
  37 #define DSS_SZ_REGS                     SZ_512
  38
  39 struct dss_reg {
  40         u16 idx;
  41 };
  42
  43 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  44
  45 #define DSS_REVISION                    DSS_REG(0x0000)
  46 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  47 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  48 #define DSS_IRQSTATUS                   DSS_REG(0x0018)
  49 #define DSS_CONTROL                     DSS_REG(0x0040)
  50 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  51 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  52 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  53
  54 #define REG_GET(idx, start, end) \
  55         FLD_GET(dss_read_reg(idx), start, end)
  56
  57 #define REG_FLD_MOD(idx, val, start, end) \
  58         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  59
  60 static struct {
  61         struct platform_device *pdev;
  62         void __iomem    *base;
  63         int             ctx_id;
  64
  65         struct clk      *dpll4_m4_ck;
  66         struct clk      *dss_ick;
  67         struct clk      *dss_fck;
  68         struct clk      *dss_sys_clk;
  69         struct clk      *dss_tv_fck;
  70         struct clk      *dss_video_fck;
  71         unsigned        num_clks_enabled;
  72
  73         unsigned long   cache_req_pck;
  74         unsigned long   cache_prate;
  75         struct dss_clock_info cache_dss_cinfo;
  76         struct dispc_clock_info cache_dispc_cinfo;
  77
  78         enum dss_clk_source dsi_clk_source;
  79         enum dss_clk_source dispc_clk_source;
  80
  81         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
  82 } dss;
  83
  84 static void dss_clk_enable_all_no_ctx(void);
  85 static void dss_clk_disable_all_no_ctx(void);
  86 static void dss_clk_enable_no_ctx(enum dss_clock clks);
  87 static void dss_clk_disable_no_ctx(enum dss_clock clks);
  88
  89 static int _omap_dss_wait_reset(void);
  90
  91 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
  92 {
  93         __raw_writel(val, dss.base + idx.idx);
  94 }
  95
  96 static inline u32 dss_read_reg(const struct dss_reg idx)
  97 {
  98         return __raw_readl(dss.base + idx.idx);
  99 }
 100
 101 #define SR(reg) \
 102         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
 103 #define RR(reg) \
 104         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
 105
 106 void dss_save_context(void)
 107 {
 108         if (cpu_is_omap24xx())
 109                 return;
 110
 111         SR(SYSCONFIG);
 112         SR(CONTROL);
 113
 114         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 115                         OMAP_DISPLAY_TYPE_SDI) {
 116                 SR(SDI_CONTROL);
 117                 SR(PLL_CONTROL);
 118         }
 119 }
 120
 121 void dss_restore_context(void)
 122 {
 123         if (_omap_dss_wait_reset())
 124                 DSSERR("DSS not coming out of reset after sleep\n");
 125
 126         RR(SYSCONFIG);
 127         RR(CONTROL);
 128
 129         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 130                         OMAP_DISPLAY_TYPE_SDI) {
 131                 RR(SDI_CONTROL);
 132                 RR(PLL_CONTROL);
 133         }
 134 }
 135
 136 #undef SR
 137 #undef RR
 138
 139 void dss_sdi_init(u8 datapairs)
 140 {
 141         u32 l;
 142
 143         BUG_ON(datapairs > 3 || datapairs < 1);
 144
 145         l = dss_read_reg(DSS_SDI_CONTROL);
 146         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 147         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 148         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 149         dss_write_reg(DSS_SDI_CONTROL, l);
 150
 151         l = dss_read_reg(DSS_PLL_CONTROL);
 152         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 153         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 154         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 155         dss_write_reg(DSS_PLL_CONTROL, l);
 156 }
 157
 158 int dss_sdi_enable(void)
 159 {
 160         unsigned long timeout;
 161
 162         dispc_pck_free_enable(1);
 163
 164         /* Reset SDI PLL */
 165         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 166         udelay(1);      /* wait 2x PCLK */
 167
 168         /* Lock SDI PLL */
 169         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 170
 171         /* Waiting for PLL lock request to complete */
 172         timeout = jiffies + msecs_to_jiffies(500);
 173         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 174                 if (time_after_eq(jiffies, timeout)) {
 175                         DSSERR("PLL lock request timed out\n");
 176                         goto err1;
 177                 }
 178         }
 179
 180         /* Clearing PLL_GO bit */
 181         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 182
 183         /* Waiting for PLL to lock */
 184         timeout = jiffies + msecs_to_jiffies(500);
 185         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 186                 if (time_after_eq(jiffies, timeout)) {
 187                         DSSERR("PLL lock timed out\n");
 188                         goto err1;
 189                 }
 190         }
 191
 192         dispc_lcd_enable_signal(1);
 193
 194         /* Waiting for SDI reset to complete */
 195         timeout = jiffies + msecs_to_jiffies(500);
 196         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 197                 if (time_after_eq(jiffies, timeout)) {
 198                         DSSERR("SDI reset timed out\n");
 199                         goto err2;
 200                 }
 201         }
 202
 203         return 0;
 204
 205  err2:
 206         dispc_lcd_enable_signal(0);
 207  err1:
 208         /* Reset SDI PLL */
 209         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 210
 211         dispc_pck_free_enable(0);
 212
 213         return -ETIMEDOUT;
 214 }
 215
 216 void dss_sdi_disable(void)
 217 {
 218         dispc_lcd_enable_signal(0);
 219
 220         dispc_pck_free_enable(0);
 221
 222         /* Reset SDI PLL */
 223         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 224 }
 225
 226 void dss_dump_clocks(struct seq_file *s)
 227 {
 228         unsigned long dpll4_ck_rate;
 229         unsigned long dpll4_m4_ck_rate;
 230
 231         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 232
 233         dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 234         dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
 235
 236         seq_printf(s, "- DSS -\n");
 237
 238         seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 239
 240         if (cpu_is_omap3630())
 241                 seq_printf(s, "dss1_alwon_fclk = %lu / %lu  = %lu\n",
 242                         dpll4_ck_rate,
 243                         dpll4_ck_rate / dpll4_m4_ck_rate,
 244                         dss_clk_get_rate(DSS_CLK_FCK));
 245         else
 246                 seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
 247                         dpll4_ck_rate,
 248                         dpll4_ck_rate / dpll4_m4_ck_rate,
 249                         dss_clk_get_rate(DSS_CLK_FCK));
 250
 251         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 252 }
 253
 254 void dss_dump_regs(struct seq_file *s)
 255 {
 256 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 257
 258         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 259
 260         DUMPREG(DSS_REVISION);
 261         DUMPREG(DSS_SYSCONFIG);
 262         DUMPREG(DSS_SYSSTATUS);
 263         DUMPREG(DSS_IRQSTATUS);
 264         DUMPREG(DSS_CONTROL);
 265
 266         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 267                         OMAP_DISPLAY_TYPE_SDI) {
 268                 DUMPREG(DSS_SDI_CONTROL);
 269                 DUMPREG(DSS_PLL_CONTROL);
 270                 DUMPREG(DSS_SDI_STATUS);
 271         }
 272
 273         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 274 #undef DUMPREG
 275 }
 276
 277 void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
 278 {
 279         int b;
 280
 281         BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC &&
 282                         clk_src != DSS_CLK_SRC_FCK);
 283
 284         b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
 285
 286         if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)
 287                 dsi_wait_dsi1_pll_active();
 288
 289         REG_FLD_MOD(DSS_CONTROL, b, 0, 0);      /* DISPC_CLK_SWITCH */
 290
 291         dss.dispc_clk_source = clk_src;
 292 }
 293
 294 void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
 295 {
 296         int b;
 297
 298         BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DSI &&
 299                         clk_src != DSS_CLK_SRC_FCK);
 300
 301         b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
 302
 303         if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)
 304                 dsi_wait_dsi2_pll_active();
 305
 306         REG_FLD_MOD(DSS_CONTROL, b, 1, 1);      /* DSI_CLK_SWITCH */
 307
 308         dss.dsi_clk_source = clk_src;
 309 }
 310
 311 enum dss_clk_source dss_get_dispc_clk_source(void)
 312 {
 313         return dss.dispc_clk_source;
 314 }
 315
 316 enum dss_clk_source dss_get_dsi_clk_source(void)
 317 {
 318         return dss.dsi_clk_source;
 319 }
 320
 321 /* calculate clock rates using dividers in cinfo */
 322 int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 323 {
 324         unsigned long prate;
 325
 326         if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||
 327                                                 cinfo->fck_div == 0)
 328                 return -EINVAL;
 329
 330         prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 331
 332         cinfo->fck = prate / cinfo->fck_div;
 333
 334         return 0;
 335 }
 336
 337 int dss_set_clock_div(struct dss_clock_info *cinfo)
 338 {
 339         unsigned long prate;
 340         int r;
 341
 342         if (cpu_is_omap34xx()) {
 343                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 344                 DSSDBG("dpll4_m4 = %ld\n", prate);
 345
 346                 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
 347                 if (r)
 348                         return r;
 349         }
 350
 351         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
 352
 353         return 0;
 354 }
 355
 356 int dss_get_clock_div(struct dss_clock_info *cinfo)
 357 {
 358         cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
 359
 360         if (cpu_is_omap34xx()) {
 361                 unsigned long prate;
 362                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 363                 if (cpu_is_omap3630())
 364                         cinfo->fck_div = prate / (cinfo->fck);
 365                 else
 366                         cinfo->fck_div = prate / (cinfo->fck / 2);
 367         } else {
 368                 cinfo->fck_div = 0;
 369         }
 370
 371         return 0;
 372 }
 373
 374 unsigned long dss_get_dpll4_rate(void)
 375 {
 376         if (cpu_is_omap34xx())
 377                 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 378         else
 379                 return 0;
 380 }
 381
 382 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 383                 struct dss_clock_info *dss_cinfo,
 384                 struct dispc_clock_info *dispc_cinfo)
 385 {
 386         unsigned long prate;
 387         struct dss_clock_info best_dss;
 388         struct dispc_clock_info best_dispc;
 389
 390         unsigned long fck, max_dss_fck;
 391
 392         u16 fck_div;
 393
 394         int match = 0;
 395         int min_fck_per_pck;
 396
 397         prate = dss_get_dpll4_rate();
 398
 399         max_dss_fck = dss_feat_get_max_dss_fck();
 400
 401         fck = dss_clk_get_rate(DSS_CLK_FCK);
 402         if (req_pck == dss.cache_req_pck &&
 403                         ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
 404                          dss.cache_dss_cinfo.fck == fck)) {
 405                 DSSDBG("dispc clock info found from cache.\n");
 406                 *dss_cinfo = dss.cache_dss_cinfo;
 407                 *dispc_cinfo = dss.cache_dispc_cinfo;
 408                 return 0;
 409         }
 410
 411         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
 412
 413         if (min_fck_per_pck &&
 414                 req_pck * min_fck_per_pck > max_dss_fck) {
 415                 DSSERR("Requested pixel clock not possible with the current "
 416                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
 417                                 "the constraint off.\n");
 418                 min_fck_per_pck = 0;
 419         }
 420
 421 retry:
 422         memset(&best_dss, 0, sizeof(best_dss));
 423         memset(&best_dispc, 0, sizeof(best_dispc));
 424
 425         if (cpu_is_omap24xx()) {
 426                 struct dispc_clock_info cur_dispc;
 427                 /* XXX can we change the clock on omap2? */
 428                 fck = dss_clk_get_rate(DSS_CLK_FCK);
 429                 fck_div = 1;
 430
 431                 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 432                 match = 1;
 433
 434                 best_dss.fck = fck;
 435                 best_dss.fck_div = fck_div;
 436
 437                 best_dispc = cur_dispc;
 438
 439                 goto found;
 440         } else if (cpu_is_omap34xx()) {
 441                 for (fck_div = (cpu_is_omap3630() ? 32 : 16);
 442                                         fck_div > 0; --fck_div) {
 443                         struct dispc_clock_info cur_dispc;
 444
 445                         if (cpu_is_omap3630())
 446                                 fck = prate / fck_div;
 447                         else
 448                                 fck = prate / fck_div * 2;
 449
 450                         if (fck > max_dss_fck)
 451                                 continue;
 452
 453                         if (min_fck_per_pck &&
 454                                         fck < req_pck * min_fck_per_pck)
 455                                 continue;
 456
 457                         match = 1;
 458
 459                         dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 460
 461                         if (abs(cur_dispc.pck - req_pck) <
 462                                         abs(best_dispc.pck - req_pck)) {
 463
 464                                 best_dss.fck = fck;
 465                                 best_dss.fck_div = fck_div;
 466
 467                                 best_dispc = cur_dispc;
 468
 469                                 if (cur_dispc.pck == req_pck)
 470                                         goto found;
 471                         }
 472                 }
 473         } else {
 474                 BUG();
 475         }
 476
 477 found:
 478         if (!match) {
 479                 if (min_fck_per_pck) {
 480                         DSSERR("Could not find suitable clock settings.\n"
 481                                         "Turning FCK/PCK constraint off and"
 482                                         "trying again.\n");
 483                         min_fck_per_pck = 0;
 484                         goto retry;
 485                 }
 486
 487                 DSSERR("Could not find suitable clock settings.\n");
 488
 489                 return -EINVAL;
 490         }
 491
 492         if (dss_cinfo)
 493                 *dss_cinfo = best_dss;
 494         if (dispc_cinfo)
 495                 *dispc_cinfo = best_dispc;
 496
 497         dss.cache_req_pck = req_pck;
 498         dss.cache_prate = prate;
 499         dss.cache_dss_cinfo = best_dss;
 500         dss.cache_dispc_cinfo = best_dispc;
 501
 502         return 0;
 503 }
 504
 505 static int _omap_dss_wait_reset(void)
 506 {
 507         int t = 0;
 508
 509         while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
 510                 if (++t > 1000) {
 511                         DSSERR("soft reset failed\n");
 512                         return -ENODEV;
 513                 }
 514                 udelay(1);
 515         }
 516
 517         return 0;
 518 }
 519
 520 static int _omap_dss_reset(void)
 521 {
 522         /* Soft reset */
 523         REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
 524         return _omap_dss_wait_reset();
 525 }
 526
 527 void dss_set_venc_output(enum omap_dss_venc_type type)
 528 {
 529         int l = 0;
 530
 531         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 532                 l = 0;
 533         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 534                 l = 1;
 535         else
 536                 BUG();
 537
 538         /* venc out selection. 0 = comp, 1 = svideo */
 539         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 540 }
 541
 542 void dss_set_dac_pwrdn_bgz(bool enable)
 543 {
 544         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 545 }
 546
 547 static int dss_init(bool skip_init)
 548 {
 549         int r;
 550         u32 rev;
 551         struct resource *dss_mem;
 552
 553         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
 554         if (!dss_mem) {
 555                 DSSERR("can't get IORESOURCE_MEM DSS\n");
 556                 r = -EINVAL;
 557                 goto fail0;
 558         }
 559         dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
 560         if (!dss.base) {
 561                 DSSERR("can't ioremap DSS\n");
 562                 r = -ENOMEM;
 563                 goto fail0;
 564         }
 565
 566         if (!skip_init) {
 567                 /* disable LCD and DIGIT output. This seems to fix the synclost
 568                  * problem that we get, if the bootloader starts the DSS and
 569                  * the kernel resets it */
 570                 omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
 571
 572                 /* We need to wait here a bit, otherwise we sometimes start to
 573                  * get synclost errors, and after that only power cycle will
 574                  * restore DSS functionality. I have no idea why this happens.
 575                  * And we have to wait _before_ resetting the DSS, but after
 576                  * enabling clocks.
 577                  */
 578                 msleep(50);
 579
 580                 _omap_dss_reset();
 581         }
 582
 583         /* autoidle */
 584         REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
 585
 586         /* Select DPLL */
 587         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
 588
 589 #ifdef CONFIG_OMAP2_DSS_VENC
 590         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
 591         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
 592         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
 593 #endif
 594
 595         if (cpu_is_omap34xx()) {
 596                 dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
 597                 if (IS_ERR(dss.dpll4_m4_ck)) {
 598                         DSSERR("Failed to get dpll4_m4_ck\n");
 599                         r = PTR_ERR(dss.dpll4_m4_ck);
 600                         goto fail1;
 601                 }
 602         }
 603
 604         dss.dsi_clk_source = DSS_CLK_SRC_FCK;
 605         dss.dispc_clk_source = DSS_CLK_SRC_FCK;
 606
 607         dss_save_context();
 608
 609         rev = dss_read_reg(DSS_REVISION);
 610         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
 611                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
 612
 613         return 0;
 614
 615 fail1:
 616         iounmap(dss.base);
 617 fail0:
 618         return r;
 619 }
 620
 621 static void dss_exit(void)
 622 {
 623         if (cpu_is_omap34xx())
 624                 clk_put(dss.dpll4_m4_ck);
 625
 626         iounmap(dss.base);
 627 }
 628
 629 /* CONTEXT */
 630 static int dss_get_ctx_id(void)
 631 {
 632         struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
 633         int r;
 634
 635         if (!pdata->board_data->get_last_off_on_transaction_id)
 636                 return 0;
 637         r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev);
 638         if (r < 0) {
 639                 dev_err(&dss.pdev->dev, "getting transaction ID failed, "
 640                                 "will force context restore\n");
 641                 r = -1;
 642         }
 643         return r;
 644 }
 645
 646 int dss_need_ctx_restore(void)
 647 {
 648         int id = dss_get_ctx_id();
 649
 650         if (id < 0 || id != dss.ctx_id) {
 651                 DSSDBG("ctx id %d -> id %d\n",
 652                                 dss.ctx_id, id);
 653                 dss.ctx_id = id;
 654                 return 1;
 655         } else {
 656                 return 0;
 657         }
 658 }
 659
 660 static void save_all_ctx(void)
 661 {
 662         DSSDBG("save context\n");
 663
 664         dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
 665
 666         dss_save_context();
 667         dispc_save_context();
 668 #ifdef CONFIG_OMAP2_DSS_DSI
 669         dsi_save_context();
 670 #endif
 671
 672         dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
 673 }
 674
 675 static void restore_all_ctx(void)
 676 {
 677         DSSDBG("restore context\n");
 678
 679         dss_clk_enable_all_no_ctx();
 680
 681         dss_restore_context();
 682         dispc_restore_context();
 683 #ifdef CONFIG_OMAP2_DSS_DSI
 684         dsi_restore_context();
 685 #endif
 686
 687         dss_clk_disable_all_no_ctx();
 688 }
 689
 690 static int dss_get_clock(struct clk **clock, const char *clk_name)
 691 {
 692         struct clk *clk;
 693
 694         clk = clk_get(&dss.pdev->dev, clk_name);
 695
 696         if (IS_ERR(clk)) {
 697                 DSSERR("can't get clock %s", clk_name);
 698                 return PTR_ERR(clk);
 699         }
 700
 701         *clock = clk;
 702
 703         DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
 704
 705         return 0;
 706 }
 707
 708 static int dss_get_clocks(void)
 709 {
 710         int r;
 711         struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
 712
 713         dss.dss_ick = NULL;
 714         dss.dss_fck = NULL;
 715         dss.dss_sys_clk = NULL;
 716         dss.dss_tv_fck = NULL;
 717         dss.dss_video_fck = NULL;
 718
 719         r = dss_get_clock(&dss.dss_ick, "ick");
 720         if (r)
 721                 goto err;
 722
 723         r = dss_get_clock(&dss.dss_fck, "fck");
 724         if (r)
 725                 goto err;
 726
 727         if (!pdata->opt_clock_available) {
 728                 r = -ENODEV;
 729                 goto err;
 730         }
 731
 732         if (pdata->opt_clock_available("sys_clk")) {
 733                 r = dss_get_clock(&dss.dss_sys_clk, "sys_clk");
 734                 if (r)
 735                         goto err;
 736         }
 737
 738         if (pdata->opt_clock_available("tv_clk")) {
 739                 r = dss_get_clock(&dss.dss_tv_fck, "tv_clk");
 740                 if (r)
 741                         goto err;
 742         }
 743
 744         if (pdata->opt_clock_available("video_clk")) {
 745                 r = dss_get_clock(&dss.dss_video_fck, "video_clk");
 746                 if (r)
 747                         goto err;
 748         }
 749
 750         return 0;
 751
 752 err:
 753         if (dss.dss_ick)
 754                 clk_put(dss.dss_ick);
 755         if (dss.dss_fck)
 756                 clk_put(dss.dss_fck);
 757         if (dss.dss_sys_clk)
 758                 clk_put(dss.dss_sys_clk);
 759         if (dss.dss_tv_fck)
 760                 clk_put(dss.dss_tv_fck);
 761         if (dss.dss_video_fck)
 762                 clk_put(dss.dss_video_fck);
 763
 764         return r;
 765 }
 766
 767 static void dss_put_clocks(void)
 768 {
 769         if (dss.dss_video_fck)
 770                 clk_put(dss.dss_video_fck);
 771         if (dss.dss_tv_fck)
 772                 clk_put(dss.dss_tv_fck);
 773         if (dss.dss_sys_clk)
 774                 clk_put(dss.dss_sys_clk);
 775         clk_put(dss.dss_fck);
 776         clk_put(dss.dss_ick);
 777 }
 778
 779 unsigned long dss_clk_get_rate(enum dss_clock clk)
 780 {
 781         switch (clk) {
 782         case DSS_CLK_ICK:
 783                 return clk_get_rate(dss.dss_ick);
 784         case DSS_CLK_FCK:
 785                 return clk_get_rate(dss.dss_fck);
 786         case DSS_CLK_SYSCK:
 787                 return clk_get_rate(dss.dss_sys_clk);
 788         case DSS_CLK_TVFCK:
 789                 return clk_get_rate(dss.dss_tv_fck);
 790         case DSS_CLK_VIDFCK:
 791                 return clk_get_rate(dss.dss_video_fck);
 792         }
 793
 794         BUG();
 795         return 0;
 796 }
 797
 798 static unsigned count_clk_bits(enum dss_clock clks)
 799 {
 800         unsigned num_clks = 0;
 801
 802         if (clks & DSS_CLK_ICK)
 803                 ++num_clks;
 804         if (clks & DSS_CLK_FCK)
 805                 ++num_clks;
 806         if (clks & DSS_CLK_SYSCK)
 807                 ++num_clks;
 808         if (clks & DSS_CLK_TVFCK)
 809                 ++num_clks;
 810         if (clks & DSS_CLK_VIDFCK)
 811                 ++num_clks;
 812
 813         return num_clks;
 814 }
 815
 816 static void dss_clk_enable_no_ctx(enum dss_clock clks)
 817 {
 818         unsigned num_clks = count_clk_bits(clks);
 819
 820         if (clks & DSS_CLK_ICK)
 821                 clk_enable(dss.dss_ick);
 822         if (clks & DSS_CLK_FCK)
 823                 clk_enable(dss.dss_fck);
 824         if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
 825                 clk_enable(dss.dss_sys_clk);
 826         if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
 827                 clk_enable(dss.dss_tv_fck);
 828         if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
 829                 clk_enable(dss.dss_video_fck);
 830
 831         dss.num_clks_enabled += num_clks;
 832 }
 833
 834 void dss_clk_enable(enum dss_clock clks)
 835 {
 836         bool check_ctx = dss.num_clks_enabled == 0;
 837
 838         dss_clk_enable_no_ctx(clks);
 839
 840         if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore())
 841                 restore_all_ctx();
 842 }
 843
 844 static void dss_clk_disable_no_ctx(enum dss_clock clks)
 845 {
 846         unsigned num_clks = count_clk_bits(clks);
 847
 848         if (clks & DSS_CLK_ICK)
 849                 clk_disable(dss.dss_ick);
 850         if (clks & DSS_CLK_FCK)
 851                 clk_disable(dss.dss_fck);
 852         if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
 853                 clk_disable(dss.dss_sys_clk);
 854         if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
 855                 clk_disable(dss.dss_tv_fck);
 856         if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
 857                 clk_disable(dss.dss_video_fck);
 858
 859         dss.num_clks_enabled -= num_clks;
 860 }
 861
 862 void dss_clk_disable(enum dss_clock clks)
 863 {
 864         if (cpu_is_omap34xx()) {
 865                 unsigned num_clks = count_clk_bits(clks);
 866
 867                 BUG_ON(dss.num_clks_enabled < num_clks);
 868
 869                 if (dss.num_clks_enabled == num_clks)
 870                         save_all_ctx();
 871         }
 872
 873         dss_clk_disable_no_ctx(clks);
 874 }
 875
 876 static void dss_clk_enable_all_no_ctx(void)
 877 {
 878         enum dss_clock clks;
 879
 880         clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
 881         if (cpu_is_omap34xx())
 882                 clks |= DSS_CLK_VIDFCK;
 883         dss_clk_enable_no_ctx(clks);
 884 }
 885
 886 static void dss_clk_disable_all_no_ctx(void)
 887 {
 888         enum dss_clock clks;
 889
 890         clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
 891         if (cpu_is_omap34xx())
 892                 clks |= DSS_CLK_VIDFCK;
 893         dss_clk_disable_no_ctx(clks);
 894 }
 895
 896 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 897 /* CLOCKS */
 898 static void core_dump_clocks(struct seq_file *s)
 899 {
 900         int i;
 901         struct clk *clocks[5] = {
 902                 dss.dss_ick,
 903                 dss.dss_fck,
 904                 dss.dss_sys_clk,
 905                 dss.dss_tv_fck,
 906                 dss.dss_video_fck
 907         };
 908
 909         seq_printf(s, "- CORE -\n");
 910
 911         seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled);
 912
 913         for (i = 0; i < 5; i++) {
 914                 if (!clocks[i])
 915                         continue;
 916                 seq_printf(s, "%-15s\t%lu\t%d\n",
 917                                 clocks[i]->name,
 918                                 clk_get_rate(clocks[i]),
 919                                 clocks[i]->usecount);
 920         }
 921 }
 922 #endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
 923
 924 /* DEBUGFS */
 925 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 926 void dss_debug_dump_clocks(struct seq_file *s)
 927 {
 928         core_dump_clocks(s);
 929         dss_dump_clocks(s);
 930         dispc_dump_clocks(s);
 931 #ifdef CONFIG_OMAP2_DSS_DSI
 932         dsi_dump_clocks(s);
 933 #endif
 934 }
 935 #endif
 936
 937
 938 /* DSS HW IP initialisation */
 939 static int omap_dsshw_probe(struct platform_device *pdev)
 940 {
 941         int r;
 942         int skip_init = 0;
 943
 944         dss.pdev = pdev;
 945
 946         r = dss_get_clocks();
 947         if (r)
 948                 goto err_clocks;
 949
 950         dss_clk_enable_all_no_ctx();
 951
 952         dss.ctx_id = dss_get_ctx_id();
 953         DSSDBG("initial ctx id %u\n", dss.ctx_id);
 954
 955 #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
 956         /* DISPC_CONTROL */
 957         if (omap_readl(0x48050440) & 1) /* LCD enabled? */
 958                 skip_init = 1;
 959 #endif
 960
 961         r = dss_init(skip_init);
 962         if (r) {
 963                 DSSERR("Failed to initialize DSS\n");
 964                 goto err_dss;
 965         }
 966
 967         dss_clk_disable_all_no_ctx();
 968         return 0;
 969
 970 err_dss:
 971         dss_clk_disable_all_no_ctx();
 972         dss_put_clocks();
 973 err_clocks:
 974         return r;
 975 }
 976
 977 static int omap_dsshw_remove(struct platform_device *pdev)
 978 {
 979
 980         dss_exit();
 981
 982         /*
 983          * As part of hwmod changes, DSS is not the only controller of dss
 984          * clocks; hwmod framework itself will also enable clocks during hwmod
 985          * init for dss, and autoidle is set in h/w for DSS. Hence, there's no
 986          * need to disable clocks if their usecounts > 1.
 987          */
 988         WARN_ON(dss.num_clks_enabled > 0);
 989
 990         dss_put_clocks();
 991         return 0;
 992 }
 993
 994 static struct platform_driver omap_dsshw_driver = {
 995         .probe          = omap_dsshw_probe,
 996         .remove         = omap_dsshw_remove,
 997         .driver         = {
 998                 .name   = "omapdss_dss",
 999                 .owner  = THIS_MODULE,
1000         },
1001 };
1002
1003 int dss_init_platform_driver(void)
1004 {
1005         return platform_driver_register(&omap_dsshw_driver);
1006 }
1007
1008 void dss_uninit_platform_driver(void)
1009 {
1010         return platform_driver_unregister(&omap_dsshw_driver);
1011 }