2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
42 #include <video/omapdss.h>
43 #include <video/mipi_display.h>
46 #include "dss_features.h"
48 /*#define VERBOSE_IRQ*/
49 #define DSI_CATCH_MISSING_TE
51 struct dsi_reg { u16 idx; };
53 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
55 #define DSI_SZ_REGS SZ_1K
56 /* DSI Protocol Engine */
58 #define DSI_REVISION DSI_REG(0x0000)
59 #define DSI_SYSCONFIG DSI_REG(0x0010)
60 #define DSI_SYSSTATUS DSI_REG(0x0014)
61 #define DSI_IRQSTATUS DSI_REG(0x0018)
62 #define DSI_IRQENABLE DSI_REG(0x001C)
63 #define DSI_CTRL DSI_REG(0x0040)
64 #define DSI_GNQ DSI_REG(0x0044)
65 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
66 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
67 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
68 #define DSI_CLK_CTRL DSI_REG(0x0054)
69 #define DSI_TIMING1 DSI_REG(0x0058)
70 #define DSI_TIMING2 DSI_REG(0x005C)
71 #define DSI_VM_TIMING1 DSI_REG(0x0060)
72 #define DSI_VM_TIMING2 DSI_REG(0x0064)
73 #define DSI_VM_TIMING3 DSI_REG(0x0068)
74 #define DSI_CLK_TIMING DSI_REG(0x006C)
75 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
76 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
77 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
78 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
79 #define DSI_VM_TIMING4 DSI_REG(0x0080)
80 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
81 #define DSI_VM_TIMING5 DSI_REG(0x0088)
82 #define DSI_VM_TIMING6 DSI_REG(0x008C)
83 #define DSI_VM_TIMING7 DSI_REG(0x0090)
84 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
85 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
86 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
87 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
88 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
89 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
90 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
91 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
95 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
96 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
97 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
98 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
99 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
101 /* DSI_PLL_CTRL_SCP */
103 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
104 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
105 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
106 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
107 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
109 #define REG_GET(dsidev, idx, start, end) \
110 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
112 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
113 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
115 /* Global interrupts */
116 #define DSI_IRQ_VC0 (1 << 0)
117 #define DSI_IRQ_VC1 (1 << 1)
118 #define DSI_IRQ_VC2 (1 << 2)
119 #define DSI_IRQ_VC3 (1 << 3)
120 #define DSI_IRQ_WAKEUP (1 << 4)
121 #define DSI_IRQ_RESYNC (1 << 5)
122 #define DSI_IRQ_PLL_LOCK (1 << 7)
123 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
124 #define DSI_IRQ_PLL_RECALL (1 << 9)
125 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
126 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
127 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
128 #define DSI_IRQ_TE_TRIGGER (1 << 16)
129 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
130 #define DSI_IRQ_SYNC_LOST (1 << 18)
131 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
132 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
133 #define DSI_IRQ_ERROR_MASK \
134 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
135 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
136 #define DSI_IRQ_CHANNEL_MASK 0xf
138 /* Virtual channel interrupts */
139 #define DSI_VC_IRQ_CS (1 << 0)
140 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
141 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
142 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
143 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
144 #define DSI_VC_IRQ_BTA (1 << 5)
145 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
146 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
147 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
148 #define DSI_VC_IRQ_ERROR_MASK \
149 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
150 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
151 DSI_VC_IRQ_FIFO_TX_UDF)
153 /* ComplexIO interrupts */
154 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
155 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
156 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
157 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
158 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
159 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
160 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
161 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
162 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
163 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
164 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
165 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
166 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
167 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
168 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
169 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
170 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
171 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
172 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
173 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
174 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
184 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
186 #define DSI_CIO_IRQ_ERROR_MASK \
187 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
188 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
189 DSI_CIO_IRQ_ERRSYNCESC5 | \
190 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
191 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
192 DSI_CIO_IRQ_ERRESC5 | \
193 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
194 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
195 DSI_CIO_IRQ_ERRCONTROL5 | \
196 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
202 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
204 #define DSI_MAX_NR_ISRS 2
205 #define DSI_MAX_NR_LANES 5
207 enum dsi_lane_function {
216 struct dsi_lane_config {
217 enum dsi_lane_function function;
221 struct dsi_isr_data {
229 DSI_FIFO_SIZE_32 = 1,
230 DSI_FIFO_SIZE_64 = 2,
231 DSI_FIFO_SIZE_96 = 3,
232 DSI_FIFO_SIZE_128 = 4,
236 DSI_VC_SOURCE_L4 = 0,
240 struct dsi_irq_stats {
241 unsigned long last_reset;
243 unsigned dsi_irqs[32];
244 unsigned vc_irqs[4][32];
245 unsigned cio_irqs[32];
248 struct dsi_isr_tables {
249 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
250 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
251 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
255 struct platform_device *pdev;
265 struct dsi_clock_info current_cinfo;
267 bool vdds_dsi_enabled;
268 struct regulator *vdds_dsi_reg;
271 enum dsi_vc_source source;
272 struct omap_dss_device *dssdev;
273 enum fifo_size fifo_size;
278 struct semaphore bus_lock;
283 struct dsi_isr_tables isr_tables;
284 /* space for a copy used by the interrupt handler */
285 struct dsi_isr_tables isr_tables_copy;
289 unsigned update_bytes;
295 void (*framedone_callback)(int, void *);
296 void *framedone_data;
298 struct delayed_work framedone_timeout_work;
300 #ifdef DSI_CATCH_MISSING_TE
301 struct timer_list te_timer;
304 unsigned long cache_req_pck;
305 unsigned long cache_clk_freq;
306 struct dsi_clock_info cache_cinfo;
309 spinlock_t errors_lock;
311 ktime_t perf_setup_time;
312 ktime_t perf_start_time;
317 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
318 spinlock_t irq_stats_lock;
319 struct dsi_irq_stats irq_stats;
321 /* DSI PLL Parameter Ranges */
322 unsigned long regm_max, regn_max;
323 unsigned long regm_dispc_max, regm_dsi_max;
324 unsigned long fint_min, fint_max;
325 unsigned long lpdiv_max;
327 unsigned num_lanes_supported;
329 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
330 unsigned num_lanes_used;
332 unsigned scp_clk_refcount;
334 struct dss_lcd_mgr_config mgr_config;
335 struct omap_video_timings timings;
336 enum omap_dss_dsi_pixel_format pix_fmt;
337 enum omap_dss_dsi_mode mode;
338 struct omap_dss_dsi_videomode_timings vm_timings;
340 struct omap_dss_output output;
343 struct dsi_packet_sent_handler_data {
344 struct platform_device *dsidev;
345 struct completion *completion;
349 static bool dsi_perf;
350 module_param(dsi_perf, bool, 0644);
353 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
355 return dev_get_drvdata(&dsidev->dev);
358 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
360 return dssdev->output->pdev;
363 struct platform_device *dsi_get_dsidev_from_id(int module)
365 struct omap_dss_output *out;
366 enum omap_dss_output_id id;
368 id = module == 0 ? OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
370 out = omap_dss_get_output(id);
375 static inline void dsi_write_reg(struct platform_device *dsidev,
376 const struct dsi_reg idx, u32 val)
378 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
380 __raw_writel(val, dsi->base + idx.idx);
383 static inline u32 dsi_read_reg(struct platform_device *dsidev,
384 const struct dsi_reg idx)
386 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
388 return __raw_readl(dsi->base + idx.idx);
391 void dsi_bus_lock(struct omap_dss_device *dssdev)
393 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
394 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
396 down(&dsi->bus_lock);
398 EXPORT_SYMBOL(dsi_bus_lock);
400 void dsi_bus_unlock(struct omap_dss_device *dssdev)
402 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
403 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
407 EXPORT_SYMBOL(dsi_bus_unlock);
409 static bool dsi_bus_is_locked(struct platform_device *dsidev)
411 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
413 return dsi->bus_lock.count == 0;
416 static void dsi_completion_handler(void *data, u32 mask)
418 complete((struct completion *)data);
421 static inline int wait_for_bit_change(struct platform_device *dsidev,
422 const struct dsi_reg idx, int bitnum, int value)
424 unsigned long timeout;
428 /* first busyloop to see if the bit changes right away */
431 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
435 /* then loop for 500ms, sleeping for 1ms in between */
436 timeout = jiffies + msecs_to_jiffies(500);
437 while (time_before(jiffies, timeout)) {
438 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
441 wait = ns_to_ktime(1000 * 1000);
442 set_current_state(TASK_UNINTERRUPTIBLE);
443 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
449 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
452 case OMAP_DSS_DSI_FMT_RGB888:
453 case OMAP_DSS_DSI_FMT_RGB666:
455 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
457 case OMAP_DSS_DSI_FMT_RGB565:
466 static void dsi_perf_mark_setup(struct platform_device *dsidev)
468 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
469 dsi->perf_setup_time = ktime_get();
472 static void dsi_perf_mark_start(struct platform_device *dsidev)
474 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
475 dsi->perf_start_time = ktime_get();
478 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
480 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
481 ktime_t t, setup_time, trans_time;
483 u32 setup_us, trans_us, total_us;
490 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
491 setup_us = (u32)ktime_to_us(setup_time);
495 trans_time = ktime_sub(t, dsi->perf_start_time);
496 trans_us = (u32)ktime_to_us(trans_time);
500 total_us = setup_us + trans_us;
502 total_bytes = dsi->update_bytes;
504 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
505 "%u bytes, %u kbytes/sec\n",
510 1000*1000 / total_us,
512 total_bytes * 1000 / total_us);
515 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
519 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
523 static inline void dsi_perf_show(struct platform_device *dsidev,
529 static void print_irq_status(u32 status)
535 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
538 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
541 if (status & DSI_IRQ_##x) \
567 static void print_irq_status_vc(int channel, u32 status)
573 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
576 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
579 if (status & DSI_VC_IRQ_##x) \
596 static void print_irq_status_cio(u32 status)
601 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
604 if (status & DSI_CIO_IRQ_##x) \
618 PIS(ERRCONTENTIONLP0_1);
619 PIS(ERRCONTENTIONLP1_1);
620 PIS(ERRCONTENTIONLP0_2);
621 PIS(ERRCONTENTIONLP1_2);
622 PIS(ERRCONTENTIONLP0_3);
623 PIS(ERRCONTENTIONLP1_3);
624 PIS(ULPSACTIVENOT_ALL0);
625 PIS(ULPSACTIVENOT_ALL1);
631 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
632 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
633 u32 *vcstatus, u32 ciostatus)
635 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
638 spin_lock(&dsi->irq_stats_lock);
640 dsi->irq_stats.irq_count++;
641 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
643 for (i = 0; i < 4; ++i)
644 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
646 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
648 spin_unlock(&dsi->irq_stats_lock);
651 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
654 static int debug_irq;
656 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
657 u32 *vcstatus, u32 ciostatus)
659 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
662 if (irqstatus & DSI_IRQ_ERROR_MASK) {
663 DSSERR("DSI error, irqstatus %x\n", irqstatus);
664 print_irq_status(irqstatus);
665 spin_lock(&dsi->errors_lock);
666 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
667 spin_unlock(&dsi->errors_lock);
668 } else if (debug_irq) {
669 print_irq_status(irqstatus);
672 for (i = 0; i < 4; ++i) {
673 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
674 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
676 print_irq_status_vc(i, vcstatus[i]);
677 } else if (debug_irq) {
678 print_irq_status_vc(i, vcstatus[i]);
682 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
683 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
684 print_irq_status_cio(ciostatus);
685 } else if (debug_irq) {
686 print_irq_status_cio(ciostatus);
690 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
691 unsigned isr_array_size, u32 irqstatus)
693 struct dsi_isr_data *isr_data;
696 for (i = 0; i < isr_array_size; i++) {
697 isr_data = &isr_array[i];
698 if (isr_data->isr && isr_data->mask & irqstatus)
699 isr_data->isr(isr_data->arg, irqstatus);
703 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
704 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
708 dsi_call_isrs(isr_tables->isr_table,
709 ARRAY_SIZE(isr_tables->isr_table),
712 for (i = 0; i < 4; ++i) {
713 if (vcstatus[i] == 0)
715 dsi_call_isrs(isr_tables->isr_table_vc[i],
716 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
721 dsi_call_isrs(isr_tables->isr_table_cio,
722 ARRAY_SIZE(isr_tables->isr_table_cio),
726 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
728 struct platform_device *dsidev;
729 struct dsi_data *dsi;
730 u32 irqstatus, vcstatus[4], ciostatus;
733 dsidev = (struct platform_device *) arg;
734 dsi = dsi_get_dsidrv_data(dsidev);
736 spin_lock(&dsi->irq_lock);
738 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
740 /* IRQ is not for us */
742 spin_unlock(&dsi->irq_lock);
746 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
747 /* flush posted write */
748 dsi_read_reg(dsidev, DSI_IRQSTATUS);
750 for (i = 0; i < 4; ++i) {
751 if ((irqstatus & (1 << i)) == 0) {
756 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
758 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
759 /* flush posted write */
760 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
763 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
764 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
766 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
767 /* flush posted write */
768 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
773 #ifdef DSI_CATCH_MISSING_TE
774 if (irqstatus & DSI_IRQ_TE_TRIGGER)
775 del_timer(&dsi->te_timer);
778 /* make a copy and unlock, so that isrs can unregister
780 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
781 sizeof(dsi->isr_tables));
783 spin_unlock(&dsi->irq_lock);
785 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
787 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
789 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
794 /* dsi->irq_lock has to be locked by the caller */
795 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
796 struct dsi_isr_data *isr_array,
797 unsigned isr_array_size, u32 default_mask,
798 const struct dsi_reg enable_reg,
799 const struct dsi_reg status_reg)
801 struct dsi_isr_data *isr_data;
808 for (i = 0; i < isr_array_size; i++) {
809 isr_data = &isr_array[i];
811 if (isr_data->isr == NULL)
814 mask |= isr_data->mask;
817 old_mask = dsi_read_reg(dsidev, enable_reg);
818 /* clear the irqstatus for newly enabled irqs */
819 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
820 dsi_write_reg(dsidev, enable_reg, mask);
822 /* flush posted writes */
823 dsi_read_reg(dsidev, enable_reg);
824 dsi_read_reg(dsidev, status_reg);
827 /* dsi->irq_lock has to be locked by the caller */
828 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
830 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
831 u32 mask = DSI_IRQ_ERROR_MASK;
832 #ifdef DSI_CATCH_MISSING_TE
833 mask |= DSI_IRQ_TE_TRIGGER;
835 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
836 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
837 DSI_IRQENABLE, DSI_IRQSTATUS);
840 /* dsi->irq_lock has to be locked by the caller */
841 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
843 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
845 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
846 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
847 DSI_VC_IRQ_ERROR_MASK,
848 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
851 /* dsi->irq_lock has to be locked by the caller */
852 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
854 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
856 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
857 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
858 DSI_CIO_IRQ_ERROR_MASK,
859 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
862 static void _dsi_initialize_irq(struct platform_device *dsidev)
864 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
868 spin_lock_irqsave(&dsi->irq_lock, flags);
870 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
872 _omap_dsi_set_irqs(dsidev);
873 for (vc = 0; vc < 4; ++vc)
874 _omap_dsi_set_irqs_vc(dsidev, vc);
875 _omap_dsi_set_irqs_cio(dsidev);
877 spin_unlock_irqrestore(&dsi->irq_lock, flags);
880 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
881 struct dsi_isr_data *isr_array, unsigned isr_array_size)
883 struct dsi_isr_data *isr_data;
889 /* check for duplicate entry and find a free slot */
891 for (i = 0; i < isr_array_size; i++) {
892 isr_data = &isr_array[i];
894 if (isr_data->isr == isr && isr_data->arg == arg &&
895 isr_data->mask == mask) {
899 if (isr_data->isr == NULL && free_idx == -1)
906 isr_data = &isr_array[free_idx];
909 isr_data->mask = mask;
914 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
915 struct dsi_isr_data *isr_array, unsigned isr_array_size)
917 struct dsi_isr_data *isr_data;
920 for (i = 0; i < isr_array_size; i++) {
921 isr_data = &isr_array[i];
922 if (isr_data->isr != isr || isr_data->arg != arg ||
923 isr_data->mask != mask)
926 isr_data->isr = NULL;
927 isr_data->arg = NULL;
936 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
939 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
943 spin_lock_irqsave(&dsi->irq_lock, flags);
945 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
946 ARRAY_SIZE(dsi->isr_tables.isr_table));
949 _omap_dsi_set_irqs(dsidev);
951 spin_unlock_irqrestore(&dsi->irq_lock, flags);
956 static int dsi_unregister_isr(struct platform_device *dsidev,
957 omap_dsi_isr_t isr, void *arg, u32 mask)
959 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
963 spin_lock_irqsave(&dsi->irq_lock, flags);
965 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
966 ARRAY_SIZE(dsi->isr_tables.isr_table));
969 _omap_dsi_set_irqs(dsidev);
971 spin_unlock_irqrestore(&dsi->irq_lock, flags);
976 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
977 omap_dsi_isr_t isr, void *arg, u32 mask)
979 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
983 spin_lock_irqsave(&dsi->irq_lock, flags);
985 r = _dsi_register_isr(isr, arg, mask,
986 dsi->isr_tables.isr_table_vc[channel],
987 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
990 _omap_dsi_set_irqs_vc(dsidev, channel);
992 spin_unlock_irqrestore(&dsi->irq_lock, flags);
997 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
998 omap_dsi_isr_t isr, void *arg, u32 mask)
1000 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1001 unsigned long flags;
1004 spin_lock_irqsave(&dsi->irq_lock, flags);
1006 r = _dsi_unregister_isr(isr, arg, mask,
1007 dsi->isr_tables.isr_table_vc[channel],
1008 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1011 _omap_dsi_set_irqs_vc(dsidev, channel);
1013 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1018 static int dsi_register_isr_cio(struct platform_device *dsidev,
1019 omap_dsi_isr_t isr, void *arg, u32 mask)
1021 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1022 unsigned long flags;
1025 spin_lock_irqsave(&dsi->irq_lock, flags);
1027 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1028 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1031 _omap_dsi_set_irqs_cio(dsidev);
1033 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1038 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1039 omap_dsi_isr_t isr, void *arg, u32 mask)
1041 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1042 unsigned long flags;
1045 spin_lock_irqsave(&dsi->irq_lock, flags);
1047 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1048 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1051 _omap_dsi_set_irqs_cio(dsidev);
1053 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1058 static u32 dsi_get_errors(struct platform_device *dsidev)
1060 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1061 unsigned long flags;
1063 spin_lock_irqsave(&dsi->errors_lock, flags);
1066 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1070 int dsi_runtime_get(struct platform_device *dsidev)
1073 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1075 DSSDBG("dsi_runtime_get\n");
1077 r = pm_runtime_get_sync(&dsi->pdev->dev);
1079 return r < 0 ? r : 0;
1082 void dsi_runtime_put(struct platform_device *dsidev)
1084 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1087 DSSDBG("dsi_runtime_put\n");
1089 r = pm_runtime_put_sync(&dsi->pdev->dev);
1090 WARN_ON(r < 0 && r != -ENOSYS);
1093 /* source clock for DSI PLL. this could also be PCLKFREE */
1094 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1097 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1100 clk_prepare_enable(dsi->sys_clk);
1102 clk_disable_unprepare(dsi->sys_clk);
1104 if (enable && dsi->pll_locked) {
1105 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1106 DSSERR("cannot lock PLL when enabling clocks\n");
1111 static void _dsi_print_reset_status(struct platform_device *dsidev)
1119 /* A dummy read using the SCP interface to any DSIPHY register is
1120 * required after DSIPHY reset to complete the reset of the DSI complex
1122 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1124 printk(KERN_DEBUG "DSI resets: ");
1126 l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1127 printk("PLL (%d) ", FLD_GET(l, 0, 0));
1129 l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1130 printk("CIO (%d) ", FLD_GET(l, 29, 29));
1132 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1142 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1143 printk("PHY (%x%x%x, %d, %d, %d)\n",
1149 FLD_GET(l, 31, 31));
1152 #define _dsi_print_reset_status(x)
1155 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1157 DSSDBG("dsi_if_enable(%d)\n", enable);
1159 enable = enable ? 1 : 0;
1160 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1162 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1163 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1170 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1172 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1174 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1177 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1179 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1181 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1184 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1186 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1188 return dsi->current_cinfo.clkin4ddr / 16;
1191 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1194 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1196 if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1197 /* DSI FCLK source is DSS_CLK_FCK */
1198 r = clk_get_rate(dsi->dss_clk);
1200 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1201 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1207 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1209 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1210 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1211 unsigned long dsi_fclk;
1212 unsigned lp_clk_div;
1213 unsigned long lp_clk;
1215 lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1217 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1220 dsi_fclk = dsi_fclk_rate(dsidev);
1222 lp_clk = dsi_fclk / 2 / lp_clk_div;
1224 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1225 dsi->current_cinfo.lp_clk = lp_clk;
1226 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1228 /* LP_CLK_DIVISOR */
1229 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1231 /* LP_RX_SYNCHRO_ENABLE */
1232 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1237 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1239 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1241 if (dsi->scp_clk_refcount++ == 0)
1242 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1245 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1247 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1249 WARN_ON(dsi->scp_clk_refcount == 0);
1250 if (--dsi->scp_clk_refcount == 0)
1251 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1254 enum dsi_pll_power_state {
1255 DSI_PLL_POWER_OFF = 0x0,
1256 DSI_PLL_POWER_ON_HSCLK = 0x1,
1257 DSI_PLL_POWER_ON_ALL = 0x2,
1258 DSI_PLL_POWER_ON_DIV = 0x3,
1261 static int dsi_pll_power(struct platform_device *dsidev,
1262 enum dsi_pll_power_state state)
1266 /* DSI-PLL power command 0x3 is not working */
1267 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1268 state == DSI_PLL_POWER_ON_DIV)
1269 state = DSI_PLL_POWER_ON_ALL;
1272 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1274 /* PLL_PWR_STATUS */
1275 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1277 DSSERR("Failed to set DSI PLL power mode to %d\n",
1287 /* calculate clock rates using dividers in cinfo */
1288 static int dsi_calc_clock_rates(struct platform_device *dsidev,
1289 struct dsi_clock_info *cinfo)
1291 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1293 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1296 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1299 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1302 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1305 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1306 cinfo->fint = cinfo->clkin / cinfo->regn;
1308 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1311 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1313 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1316 if (cinfo->regm_dispc > 0)
1317 cinfo->dsi_pll_hsdiv_dispc_clk =
1318 cinfo->clkin4ddr / cinfo->regm_dispc;
1320 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1322 if (cinfo->regm_dsi > 0)
1323 cinfo->dsi_pll_hsdiv_dsi_clk =
1324 cinfo->clkin4ddr / cinfo->regm_dsi;
1326 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1331 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
1332 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1333 struct dispc_clock_info *dispc_cinfo)
1335 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1336 struct dsi_clock_info cur, best;
1337 struct dispc_clock_info best_dispc;
1338 int min_fck_per_pck;
1340 unsigned long dss_sys_clk, max_dss_fck;
1342 dss_sys_clk = clk_get_rate(dsi->sys_clk);
1344 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1346 if (req_pck == dsi->cache_req_pck &&
1347 dsi->cache_cinfo.clkin == dss_sys_clk) {
1348 DSSDBG("DSI clock info found from cache\n");
1349 *dsi_cinfo = dsi->cache_cinfo;
1350 dispc_find_clk_divs(req_pck, dsi_cinfo->dsi_pll_hsdiv_dispc_clk,
1355 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1357 if (min_fck_per_pck &&
1358 req_pck * min_fck_per_pck > max_dss_fck) {
1359 DSSERR("Requested pixel clock not possible with the current "
1360 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1361 "the constraint off.\n");
1362 min_fck_per_pck = 0;
1365 DSSDBG("dsi_pll_calc\n");
1368 memset(&best, 0, sizeof(best));
1369 memset(&best_dispc, 0, sizeof(best_dispc));
1371 memset(&cur, 0, sizeof(cur));
1372 cur.clkin = dss_sys_clk;
1374 /* 0.75MHz < Fint = clkin / regn < 2.1MHz */
1375 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1376 for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1377 cur.fint = cur.clkin / cur.regn;
1379 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1382 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1383 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1386 a = 2 * cur.regm * (cur.clkin/1000);
1388 cur.clkin4ddr = a / b * 1000;
1390 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1393 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1394 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1395 for (cur.regm_dispc = 1; cur.regm_dispc <
1396 dsi->regm_dispc_max; ++cur.regm_dispc) {
1397 struct dispc_clock_info cur_dispc;
1398 cur.dsi_pll_hsdiv_dispc_clk =
1399 cur.clkin4ddr / cur.regm_dispc;
1401 /* this will narrow down the search a bit,
1402 * but still give pixclocks below what was
1404 if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
1407 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1410 if (min_fck_per_pck &&
1411 cur.dsi_pll_hsdiv_dispc_clk <
1412 req_pck * min_fck_per_pck)
1417 dispc_find_clk_divs(req_pck,
1418 cur.dsi_pll_hsdiv_dispc_clk,
1421 if (abs(cur_dispc.pck - req_pck) <
1422 abs(best_dispc.pck - req_pck)) {
1424 best_dispc = cur_dispc;
1426 if (cur_dispc.pck == req_pck)
1434 if (min_fck_per_pck) {
1435 DSSERR("Could not find suitable clock settings.\n"
1436 "Turning FCK/PCK constraint off and"
1438 min_fck_per_pck = 0;
1442 DSSERR("Could not find suitable clock settings.\n");
1447 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1449 best.dsi_pll_hsdiv_dsi_clk = 0;
1454 *dispc_cinfo = best_dispc;
1456 dsi->cache_req_pck = req_pck;
1457 dsi->cache_clk_freq = 0;
1458 dsi->cache_cinfo = best;
1463 static int dsi_pll_calc_ddrfreq(struct platform_device *dsidev,
1464 unsigned long req_clkin4ddr, struct dsi_clock_info *cinfo)
1466 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1467 struct dsi_clock_info cur, best;
1469 DSSDBG("dsi_pll_calc_ddrfreq\n");
1471 memset(&best, 0, sizeof(best));
1472 memset(&cur, 0, sizeof(cur));
1474 cur.clkin = clk_get_rate(dsi->sys_clk);
1476 for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1477 cur.fint = cur.clkin / cur.regn;
1479 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1482 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1483 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1486 a = 2 * cur.regm * (cur.clkin/1000);
1488 cur.clkin4ddr = a / b * 1000;
1490 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1493 if (abs(cur.clkin4ddr - req_clkin4ddr) <
1494 abs(best.clkin4ddr - req_clkin4ddr)) {
1496 DSSDBG("best %ld\n", best.clkin4ddr);
1499 if (cur.clkin4ddr == req_clkin4ddr)
1510 static void dsi_pll_calc_dsi_fck(struct platform_device *dsidev,
1511 struct dsi_clock_info *cinfo)
1513 unsigned long max_dsi_fck;
1515 max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1517 cinfo->regm_dsi = DIV_ROUND_UP(cinfo->clkin4ddr, max_dsi_fck);
1518 cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
1521 static int dsi_pll_calc_dispc_fck(struct platform_device *dsidev,
1522 unsigned long req_pck, struct dsi_clock_info *cinfo,
1523 struct dispc_clock_info *dispc_cinfo)
1525 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1526 unsigned regm_dispc, best_regm_dispc;
1527 unsigned long dispc_clk, best_dispc_clk;
1528 int min_fck_per_pck;
1529 unsigned long max_dss_fck;
1530 struct dispc_clock_info best_dispc;
1533 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1535 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1537 if (min_fck_per_pck &&
1538 req_pck * min_fck_per_pck > max_dss_fck) {
1539 DSSERR("Requested pixel clock not possible with the current "
1540 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1541 "the constraint off.\n");
1542 min_fck_per_pck = 0;
1546 best_regm_dispc = 0;
1548 memset(&best_dispc, 0, sizeof(best_dispc));
1551 for (regm_dispc = 1; regm_dispc < dsi->regm_dispc_max; ++regm_dispc) {
1552 struct dispc_clock_info cur_dispc;
1554 dispc_clk = cinfo->clkin4ddr / regm_dispc;
1556 /* this will narrow down the search a bit,
1557 * but still give pixclocks below what was
1559 if (dispc_clk < req_pck)
1562 if (dispc_clk > max_dss_fck)
1565 if (min_fck_per_pck && dispc_clk < req_pck * min_fck_per_pck)
1570 dispc_find_clk_divs(req_pck, dispc_clk, &cur_dispc);
1572 if (abs(cur_dispc.pck - req_pck) <
1573 abs(best_dispc.pck - req_pck)) {
1574 best_regm_dispc = regm_dispc;
1575 best_dispc_clk = dispc_clk;
1576 best_dispc = cur_dispc;
1578 if (cur_dispc.pck == req_pck)
1584 if (min_fck_per_pck) {
1585 DSSERR("Could not find suitable clock settings.\n"
1586 "Turning FCK/PCK constraint off and"
1588 min_fck_per_pck = 0;
1592 DSSERR("Could not find suitable clock settings.\n");
1597 cinfo->regm_dispc = best_regm_dispc;
1598 cinfo->dsi_pll_hsdiv_dispc_clk = best_dispc_clk;
1600 *dispc_cinfo = best_dispc;
1605 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1606 struct dsi_clock_info *cinfo)
1608 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1612 u8 regn_start, regn_end, regm_start, regm_end;
1613 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1617 dsi->current_cinfo.clkin = cinfo->clkin;
1618 dsi->current_cinfo.fint = cinfo->fint;
1619 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1620 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1621 cinfo->dsi_pll_hsdiv_dispc_clk;
1622 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1623 cinfo->dsi_pll_hsdiv_dsi_clk;
1625 dsi->current_cinfo.regn = cinfo->regn;
1626 dsi->current_cinfo.regm = cinfo->regm;
1627 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1628 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1630 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1632 DSSDBG("clkin rate %ld\n", cinfo->clkin);
1634 /* DSIPHY == CLKIN4DDR */
1635 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1641 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1642 cinfo->clkin4ddr / 1000 / 1000 / 2);
1644 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1646 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1647 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1648 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1649 cinfo->dsi_pll_hsdiv_dispc_clk);
1650 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1651 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1652 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1653 cinfo->dsi_pll_hsdiv_dsi_clk);
1655 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end);
1656 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end);
1657 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start,
1659 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start,
1662 /* DSI_PLL_AUTOMODE = manual */
1663 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1665 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1666 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1668 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1670 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1672 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1673 regm_dispc_start, regm_dispc_end);
1674 /* DSIPROTO_CLOCK_DIV */
1675 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1676 regm_dsi_start, regm_dsi_end);
1677 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1679 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1681 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1683 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1684 f = cinfo->fint < 1000000 ? 0x3 :
1685 cinfo->fint < 1250000 ? 0x4 :
1686 cinfo->fint < 1500000 ? 0x5 :
1687 cinfo->fint < 1750000 ? 0x6 :
1690 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1691 } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) {
1692 f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4;
1694 l = FLD_MOD(l, f, 4, 1); /* PLL_SELFREQDCO */
1697 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1698 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1699 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1700 if (dss_has_feature(FEAT_DSI_PLL_REFSEL))
1701 l = FLD_MOD(l, 3, 22, 21); /* REF_SYSCLK = sysclk */
1702 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1704 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1706 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1707 DSSERR("dsi pll go bit not going down.\n");
1712 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1713 DSSERR("cannot lock PLL\n");
1718 dsi->pll_locked = 1;
1720 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1721 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1722 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1723 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1724 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1725 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1726 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1727 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1728 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1729 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1730 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1731 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1732 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1733 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1734 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1735 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1737 DSSDBG("PLL config done\n");
1742 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1745 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1747 enum dsi_pll_power_state pwstate;
1749 DSSDBG("PLL init\n");
1751 if (dsi->vdds_dsi_reg == NULL) {
1752 struct regulator *vdds_dsi;
1754 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1756 if (IS_ERR(vdds_dsi)) {
1757 DSSERR("can't get VDDS_DSI regulator\n");
1758 return PTR_ERR(vdds_dsi);
1761 dsi->vdds_dsi_reg = vdds_dsi;
1764 dsi_enable_pll_clock(dsidev, 1);
1766 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1768 dsi_enable_scp_clk(dsidev);
1770 if (!dsi->vdds_dsi_enabled) {
1771 r = regulator_enable(dsi->vdds_dsi_reg);
1774 dsi->vdds_dsi_enabled = true;
1777 /* XXX PLL does not come out of reset without this... */
1778 dispc_pck_free_enable(1);
1780 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1781 DSSERR("PLL not coming out of reset.\n");
1783 dispc_pck_free_enable(0);
1787 /* XXX ... but if left on, we get problems when planes do not
1788 * fill the whole display. No idea about this */
1789 dispc_pck_free_enable(0);
1791 if (enable_hsclk && enable_hsdiv)
1792 pwstate = DSI_PLL_POWER_ON_ALL;
1793 else if (enable_hsclk)
1794 pwstate = DSI_PLL_POWER_ON_HSCLK;
1795 else if (enable_hsdiv)
1796 pwstate = DSI_PLL_POWER_ON_DIV;
1798 pwstate = DSI_PLL_POWER_OFF;
1800 r = dsi_pll_power(dsidev, pwstate);
1805 DSSDBG("PLL init done\n");
1809 if (dsi->vdds_dsi_enabled) {
1810 regulator_disable(dsi->vdds_dsi_reg);
1811 dsi->vdds_dsi_enabled = false;
1814 dsi_disable_scp_clk(dsidev);
1815 dsi_enable_pll_clock(dsidev, 0);
1819 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1821 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1823 dsi->pll_locked = 0;
1824 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1825 if (disconnect_lanes) {
1826 WARN_ON(!dsi->vdds_dsi_enabled);
1827 regulator_disable(dsi->vdds_dsi_reg);
1828 dsi->vdds_dsi_enabled = false;
1831 dsi_disable_scp_clk(dsidev);
1832 dsi_enable_pll_clock(dsidev, 0);
1834 DSSDBG("PLL uninit done\n");
1837 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1840 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1841 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1842 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1843 int dsi_module = dsi->module_id;
1845 dispc_clk_src = dss_get_dispc_clk_source();
1846 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1848 if (dsi_runtime_get(dsidev))
1851 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1853 seq_printf(s, "dsi pll clkin\t%lu\n", cinfo->clkin);
1855 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1857 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1858 cinfo->clkin4ddr, cinfo->regm);
1860 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1861 dss_feat_get_clk_source_name(dsi_module == 0 ?
1862 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1863 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1864 cinfo->dsi_pll_hsdiv_dispc_clk,
1866 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1869 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1870 dss_feat_get_clk_source_name(dsi_module == 0 ?
1871 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1872 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1873 cinfo->dsi_pll_hsdiv_dsi_clk,
1875 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1878 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1880 seq_printf(s, "dsi fclk source = %s (%s)\n",
1881 dss_get_generic_clk_source_name(dsi_clk_src),
1882 dss_feat_get_clk_source_name(dsi_clk_src));
1884 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1886 seq_printf(s, "DDR_CLK\t\t%lu\n",
1887 cinfo->clkin4ddr / 4);
1889 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1891 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1893 dsi_runtime_put(dsidev);
1896 void dsi_dump_clocks(struct seq_file *s)
1898 struct platform_device *dsidev;
1901 for (i = 0; i < MAX_NUM_DSI; i++) {
1902 dsidev = dsi_get_dsidev_from_id(i);
1904 dsi_dump_dsidev_clocks(dsidev, s);
1908 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1909 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1912 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1913 unsigned long flags;
1914 struct dsi_irq_stats stats;
1916 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1918 stats = dsi->irq_stats;
1919 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1920 dsi->irq_stats.last_reset = jiffies;
1922 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1924 seq_printf(s, "period %u ms\n",
1925 jiffies_to_msecs(jiffies - stats.last_reset));
1927 seq_printf(s, "irqs %d\n", stats.irq_count);
1929 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1931 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1947 PIS(LDO_POWER_GOOD);
1952 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1953 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1954 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1955 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1956 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1958 seq_printf(s, "-- VC interrupts --\n");
1967 PIS(PP_BUSY_CHANGE);
1971 seq_printf(s, "%-20s %10d\n", #x, \
1972 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1974 seq_printf(s, "-- CIO interrupts --\n");
1987 PIS(ERRCONTENTIONLP0_1);
1988 PIS(ERRCONTENTIONLP1_1);
1989 PIS(ERRCONTENTIONLP0_2);
1990 PIS(ERRCONTENTIONLP1_2);
1991 PIS(ERRCONTENTIONLP0_3);
1992 PIS(ERRCONTENTIONLP1_3);
1993 PIS(ULPSACTIVENOT_ALL0);
1994 PIS(ULPSACTIVENOT_ALL1);
1998 static void dsi1_dump_irqs(struct seq_file *s)
2000 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
2002 dsi_dump_dsidev_irqs(dsidev, s);
2005 static void dsi2_dump_irqs(struct seq_file *s)
2007 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
2009 dsi_dump_dsidev_irqs(dsidev, s);
2013 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
2016 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
2018 if (dsi_runtime_get(dsidev))
2020 dsi_enable_scp_clk(dsidev);
2022 DUMPREG(DSI_REVISION);
2023 DUMPREG(DSI_SYSCONFIG);
2024 DUMPREG(DSI_SYSSTATUS);
2025 DUMPREG(DSI_IRQSTATUS);
2026 DUMPREG(DSI_IRQENABLE);
2028 DUMPREG(DSI_COMPLEXIO_CFG1);
2029 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
2030 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
2031 DUMPREG(DSI_CLK_CTRL);
2032 DUMPREG(DSI_TIMING1);
2033 DUMPREG(DSI_TIMING2);
2034 DUMPREG(DSI_VM_TIMING1);
2035 DUMPREG(DSI_VM_TIMING2);
2036 DUMPREG(DSI_VM_TIMING3);
2037 DUMPREG(DSI_CLK_TIMING);
2038 DUMPREG(DSI_TX_FIFO_VC_SIZE);
2039 DUMPREG(DSI_RX_FIFO_VC_SIZE);
2040 DUMPREG(DSI_COMPLEXIO_CFG2);
2041 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
2042 DUMPREG(DSI_VM_TIMING4);
2043 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
2044 DUMPREG(DSI_VM_TIMING5);
2045 DUMPREG(DSI_VM_TIMING6);
2046 DUMPREG(DSI_VM_TIMING7);
2047 DUMPREG(DSI_STOPCLK_TIMING);
2049 DUMPREG(DSI_VC_CTRL(0));
2050 DUMPREG(DSI_VC_TE(0));
2051 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
2052 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
2053 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
2054 DUMPREG(DSI_VC_IRQSTATUS(0));
2055 DUMPREG(DSI_VC_IRQENABLE(0));
2057 DUMPREG(DSI_VC_CTRL(1));
2058 DUMPREG(DSI_VC_TE(1));
2059 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
2060 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
2061 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
2062 DUMPREG(DSI_VC_IRQSTATUS(1));
2063 DUMPREG(DSI_VC_IRQENABLE(1));
2065 DUMPREG(DSI_VC_CTRL(2));
2066 DUMPREG(DSI_VC_TE(2));
2067 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
2068 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
2069 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
2070 DUMPREG(DSI_VC_IRQSTATUS(2));
2071 DUMPREG(DSI_VC_IRQENABLE(2));
2073 DUMPREG(DSI_VC_CTRL(3));
2074 DUMPREG(DSI_VC_TE(3));
2075 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
2076 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
2077 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
2078 DUMPREG(DSI_VC_IRQSTATUS(3));
2079 DUMPREG(DSI_VC_IRQENABLE(3));
2081 DUMPREG(DSI_DSIPHY_CFG0);
2082 DUMPREG(DSI_DSIPHY_CFG1);
2083 DUMPREG(DSI_DSIPHY_CFG2);
2084 DUMPREG(DSI_DSIPHY_CFG5);
2086 DUMPREG(DSI_PLL_CONTROL);
2087 DUMPREG(DSI_PLL_STATUS);
2088 DUMPREG(DSI_PLL_GO);
2089 DUMPREG(DSI_PLL_CONFIGURATION1);
2090 DUMPREG(DSI_PLL_CONFIGURATION2);
2092 dsi_disable_scp_clk(dsidev);
2093 dsi_runtime_put(dsidev);
2097 static void dsi1_dump_regs(struct seq_file *s)
2099 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
2101 dsi_dump_dsidev_regs(dsidev, s);
2104 static void dsi2_dump_regs(struct seq_file *s)
2106 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
2108 dsi_dump_dsidev_regs(dsidev, s);
2111 enum dsi_cio_power_state {
2112 DSI_COMPLEXIO_POWER_OFF = 0x0,
2113 DSI_COMPLEXIO_POWER_ON = 0x1,
2114 DSI_COMPLEXIO_POWER_ULPS = 0x2,
2117 static int dsi_cio_power(struct platform_device *dsidev,
2118 enum dsi_cio_power_state state)
2123 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2126 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2129 DSSERR("failed to set complexio power state to "
2139 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2143 /* line buffer on OMAP3 is 1024 x 24bits */
2144 /* XXX: for some reason using full buffer size causes
2145 * considerable TX slowdown with update sizes that fill the
2147 if (!dss_has_feature(FEAT_DSI_GNQ))
2150 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2154 return 512 * 3; /* 512x24 bits */
2156 return 682 * 3; /* 682x24 bits */
2158 return 853 * 3; /* 853x24 bits */
2160 return 1024 * 3; /* 1024x24 bits */
2162 return 1194 * 3; /* 1194x24 bits */
2164 return 1365 * 3; /* 1365x24 bits */
2166 return 1920 * 3; /* 1920x24 bits */
2173 static int dsi_set_lane_config(struct platform_device *dsidev)
2175 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2176 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2177 static const enum dsi_lane_function functions[] = {
2187 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2189 for (i = 0; i < dsi->num_lanes_used; ++i) {
2190 unsigned offset = offsets[i];
2191 unsigned polarity, lane_number;
2194 for (t = 0; t < dsi->num_lanes_supported; ++t)
2195 if (dsi->lanes[t].function == functions[i])
2198 if (t == dsi->num_lanes_supported)
2202 polarity = dsi->lanes[t].polarity;
2204 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2205 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2208 /* clear the unused lanes */
2209 for (; i < dsi->num_lanes_supported; ++i) {
2210 unsigned offset = offsets[i];
2212 r = FLD_MOD(r, 0, offset + 2, offset);
2213 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2216 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2221 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2223 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2225 /* convert time in ns to ddr ticks, rounding up */
2226 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2227 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2230 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2232 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2234 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2235 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2238 static void dsi_cio_timings(struct platform_device *dsidev)
2241 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2242 u32 tlpx_half, tclk_trail, tclk_zero;
2245 /* calculate timings */
2247 /* 1 * DDR_CLK = 2 * UI */
2249 /* min 40ns + 4*UI max 85ns + 6*UI */
2250 ths_prepare = ns2ddr(dsidev, 70) + 2;
2252 /* min 145ns + 10*UI */
2253 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2255 /* min max(8*UI, 60ns+4*UI) */
2256 ths_trail = ns2ddr(dsidev, 60) + 5;
2259 ths_exit = ns2ddr(dsidev, 145);
2262 tlpx_half = ns2ddr(dsidev, 25);
2265 tclk_trail = ns2ddr(dsidev, 60) + 2;
2267 /* min 38ns, max 95ns */
2268 tclk_prepare = ns2ddr(dsidev, 65);
2270 /* min tclk-prepare + tclk-zero = 300ns */
2271 tclk_zero = ns2ddr(dsidev, 260);
2273 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2274 ths_prepare, ddr2ns(dsidev, ths_prepare),
2275 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2276 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2277 ths_trail, ddr2ns(dsidev, ths_trail),
2278 ths_exit, ddr2ns(dsidev, ths_exit));
2280 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2281 "tclk_zero %u (%uns)\n",
2282 tlpx_half, ddr2ns(dsidev, tlpx_half),
2283 tclk_trail, ddr2ns(dsidev, tclk_trail),
2284 tclk_zero, ddr2ns(dsidev, tclk_zero));
2285 DSSDBG("tclk_prepare %u (%uns)\n",
2286 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2288 /* program timings */
2290 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2291 r = FLD_MOD(r, ths_prepare, 31, 24);
2292 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2293 r = FLD_MOD(r, ths_trail, 15, 8);
2294 r = FLD_MOD(r, ths_exit, 7, 0);
2295 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2297 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2298 r = FLD_MOD(r, tlpx_half, 20, 16);
2299 r = FLD_MOD(r, tclk_trail, 15, 8);
2300 r = FLD_MOD(r, tclk_zero, 7, 0);
2302 if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
2303 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
2304 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
2305 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
2308 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2310 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2311 r = FLD_MOD(r, tclk_prepare, 7, 0);
2312 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2315 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2316 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
2317 unsigned mask_p, unsigned mask_n)
2319 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2322 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2326 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2327 unsigned p = dsi->lanes[i].polarity;
2329 if (mask_p & (1 << i))
2330 l |= 1 << (i * 2 + (p ? 0 : 1));
2332 if (mask_n & (1 << i))
2333 l |= 1 << (i * 2 + (p ? 1 : 0));
2337 * Bits in REGLPTXSCPDAT4TO0DXDY:
2345 /* Set the lane override configuration */
2347 /* REGLPTXSCPDAT4TO0DXDY */
2348 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2350 /* Enable lane override */
2353 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2356 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2358 /* Disable lane override */
2359 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2360 /* Reset the lane override configuration */
2361 /* REGLPTXSCPDAT4TO0DXDY */
2362 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2365 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2367 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2369 bool in_use[DSI_MAX_NR_LANES];
2370 static const u8 offsets_old[] = { 28, 27, 26 };
2371 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2374 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2375 offsets = offsets_old;
2377 offsets = offsets_new;
2379 for (i = 0; i < dsi->num_lanes_supported; ++i)
2380 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2387 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2390 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2391 if (!in_use[i] || (l & (1 << offsets[i])))
2395 if (ok == dsi->num_lanes_supported)
2399 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2400 if (!in_use[i] || (l & (1 << offsets[i])))
2403 DSSERR("CIO TXCLKESC%d domain not coming " \
2404 "out of reset\n", i);
2413 /* return bitmask of enabled lanes, lane0 being the lsb */
2414 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2416 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2420 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2421 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2428 static int dsi_cio_init(struct platform_device *dsidev)
2430 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2436 r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2440 dsi_enable_scp_clk(dsidev);
2442 /* A dummy read using the SCP interface to any DSIPHY register is
2443 * required after DSIPHY reset to complete the reset of the DSI complex
2445 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2447 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2448 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2450 goto err_scp_clk_dom;
2453 r = dsi_set_lane_config(dsidev);
2455 goto err_scp_clk_dom;
2457 /* set TX STOP MODE timer to maximum for this operation */
2458 l = dsi_read_reg(dsidev, DSI_TIMING1);
2459 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2460 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2461 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2462 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2463 dsi_write_reg(dsidev, DSI_TIMING1, l);
2465 if (dsi->ulps_enabled) {
2469 DSSDBG("manual ulps exit\n");
2471 /* ULPS is exited by Mark-1 state for 1ms, followed by
2472 * stop state. DSS HW cannot do this via the normal
2473 * ULPS exit sequence, as after reset the DSS HW thinks
2474 * that we are not in ULPS mode, and refuses to send the
2475 * sequence. So we need to send the ULPS exit sequence
2476 * manually by setting positive lines high and negative lines
2482 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2483 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2488 dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2491 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2495 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2496 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2498 goto err_cio_pwr_dom;
2501 dsi_if_enable(dsidev, true);
2502 dsi_if_enable(dsidev, false);
2503 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2505 r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2507 goto err_tx_clk_esc_rst;
2509 if (dsi->ulps_enabled) {
2510 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2511 ktime_t wait = ns_to_ktime(1000 * 1000);
2512 set_current_state(TASK_UNINTERRUPTIBLE);
2513 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2515 /* Disable the override. The lanes should be set to Mark-11
2516 * state by the HW */
2517 dsi_cio_disable_lane_override(dsidev);
2520 /* FORCE_TX_STOP_MODE_IO */
2521 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2523 dsi_cio_timings(dsidev);
2525 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2526 /* DDR_CLK_ALWAYS_ON */
2527 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2528 dsi->vm_timings.ddr_clk_always_on, 13, 13);
2531 dsi->ulps_enabled = false;
2533 DSSDBG("CIO init done\n");
2538 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2540 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2542 if (dsi->ulps_enabled)
2543 dsi_cio_disable_lane_override(dsidev);
2545 dsi_disable_scp_clk(dsidev);
2546 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2550 static void dsi_cio_uninit(struct platform_device *dsidev)
2552 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2554 /* DDR_CLK_ALWAYS_ON */
2555 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2557 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2558 dsi_disable_scp_clk(dsidev);
2559 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2562 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2563 enum fifo_size size1, enum fifo_size size2,
2564 enum fifo_size size3, enum fifo_size size4)
2566 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2571 dsi->vc[0].fifo_size = size1;
2572 dsi->vc[1].fifo_size = size2;
2573 dsi->vc[2].fifo_size = size3;
2574 dsi->vc[3].fifo_size = size4;
2576 for (i = 0; i < 4; i++) {
2578 int size = dsi->vc[i].fifo_size;
2580 if (add + size > 4) {
2581 DSSERR("Illegal FIFO configuration\n");
2586 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2588 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2592 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2595 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2596 enum fifo_size size1, enum fifo_size size2,
2597 enum fifo_size size3, enum fifo_size size4)
2599 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2604 dsi->vc[0].fifo_size = size1;
2605 dsi->vc[1].fifo_size = size2;
2606 dsi->vc[2].fifo_size = size3;
2607 dsi->vc[3].fifo_size = size4;
2609 for (i = 0; i < 4; i++) {
2611 int size = dsi->vc[i].fifo_size;
2613 if (add + size > 4) {
2614 DSSERR("Illegal FIFO configuration\n");
2619 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2621 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2625 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2628 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2632 r = dsi_read_reg(dsidev, DSI_TIMING1);
2633 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2634 dsi_write_reg(dsidev, DSI_TIMING1, r);
2636 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2637 DSSERR("TX_STOP bit not going down\n");
2644 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2646 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2649 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2651 struct dsi_packet_sent_handler_data *vp_data =
2652 (struct dsi_packet_sent_handler_data *) data;
2653 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2654 const int channel = dsi->update_channel;
2655 u8 bit = dsi->te_enabled ? 30 : 31;
2657 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2658 complete(vp_data->completion);
2661 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2663 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2664 DECLARE_COMPLETION_ONSTACK(completion);
2665 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2669 bit = dsi->te_enabled ? 30 : 31;
2671 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2672 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2676 /* Wait for completion only if TE_EN/TE_START is still set */
2677 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2678 if (wait_for_completion_timeout(&completion,
2679 msecs_to_jiffies(10)) == 0) {
2680 DSSERR("Failed to complete previous frame transfer\n");
2686 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2687 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2691 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2692 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2697 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2699 struct dsi_packet_sent_handler_data *l4_data =
2700 (struct dsi_packet_sent_handler_data *) data;
2701 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2702 const int channel = dsi->update_channel;
2704 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2705 complete(l4_data->completion);
2708 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2710 DECLARE_COMPLETION_ONSTACK(completion);
2711 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2714 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2715 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2719 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2720 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2721 if (wait_for_completion_timeout(&completion,
2722 msecs_to_jiffies(10)) == 0) {
2723 DSSERR("Failed to complete previous l4 transfer\n");
2729 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2730 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2734 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2735 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2740 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2742 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2744 WARN_ON(!dsi_bus_is_locked(dsidev));
2746 WARN_ON(in_interrupt());
2748 if (!dsi_vc_is_enabled(dsidev, channel))
2751 switch (dsi->vc[channel].source) {
2752 case DSI_VC_SOURCE_VP:
2753 return dsi_sync_vc_vp(dsidev, channel);
2754 case DSI_VC_SOURCE_L4:
2755 return dsi_sync_vc_l4(dsidev, channel);
2762 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2765 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2768 enable = enable ? 1 : 0;
2770 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2772 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2773 0, enable) != enable) {
2774 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2781 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2785 DSSDBGF("%d", channel);
2787 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2789 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2790 DSSERR("VC(%d) busy when trying to configure it!\n",
2793 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2794 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2795 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2796 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2797 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2798 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2799 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2800 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2801 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2803 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2804 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2806 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2809 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2810 enum dsi_vc_source source)
2812 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2814 if (dsi->vc[channel].source == source)
2817 DSSDBGF("%d", channel);
2819 dsi_sync_vc(dsidev, channel);
2821 dsi_vc_enable(dsidev, channel, 0);
2824 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2825 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2829 /* SOURCE, 0 = L4, 1 = video port */
2830 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2832 /* DCS_CMD_ENABLE */
2833 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2834 bool enable = source == DSI_VC_SOURCE_VP;
2835 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2838 dsi_vc_enable(dsidev, channel, 1);
2840 dsi->vc[channel].source = source;
2845 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2848 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2849 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2851 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2853 WARN_ON(!dsi_bus_is_locked(dsidev));
2855 dsi_vc_enable(dsidev, channel, 0);
2856 dsi_if_enable(dsidev, 0);
2858 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2860 dsi_vc_enable(dsidev, channel, 1);
2861 dsi_if_enable(dsidev, 1);
2863 dsi_force_tx_stop_mode_io(dsidev);
2865 /* start the DDR clock by sending a NULL packet */
2866 if (dsi->vm_timings.ddr_clk_always_on && enable)
2867 dsi_vc_send_null(dssdev, channel);
2869 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2871 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2873 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2875 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2876 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2880 (val >> 24) & 0xff);
2884 static void dsi_show_rx_ack_with_err(u16 err)
2886 DSSERR("\tACK with ERROR (%#x):\n", err);
2888 DSSERR("\t\tSoT Error\n");
2890 DSSERR("\t\tSoT Sync Error\n");
2892 DSSERR("\t\tEoT Sync Error\n");
2894 DSSERR("\t\tEscape Mode Entry Command Error\n");
2896 DSSERR("\t\tLP Transmit Sync Error\n");
2898 DSSERR("\t\tHS Receive Timeout Error\n");
2900 DSSERR("\t\tFalse Control Error\n");
2902 DSSERR("\t\t(reserved7)\n");
2904 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2906 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2907 if (err & (1 << 10))
2908 DSSERR("\t\tChecksum Error\n");
2909 if (err & (1 << 11))
2910 DSSERR("\t\tData type not recognized\n");
2911 if (err & (1 << 12))
2912 DSSERR("\t\tInvalid VC ID\n");
2913 if (err & (1 << 13))
2914 DSSERR("\t\tInvalid Transmission Length\n");
2915 if (err & (1 << 14))
2916 DSSERR("\t\t(reserved14)\n");
2917 if (err & (1 << 15))
2918 DSSERR("\t\tDSI Protocol Violation\n");
2921 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2924 /* RX_FIFO_NOT_EMPTY */
2925 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2928 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2929 DSSERR("\trawval %#08x\n", val);
2930 dt = FLD_GET(val, 5, 0);
2931 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2932 u16 err = FLD_GET(val, 23, 8);
2933 dsi_show_rx_ack_with_err(err);
2934 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2935 DSSERR("\tDCS short response, 1 byte: %#x\n",
2936 FLD_GET(val, 23, 8));
2937 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2938 DSSERR("\tDCS short response, 2 byte: %#x\n",
2939 FLD_GET(val, 23, 8));
2940 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2941 DSSERR("\tDCS long response, len %d\n",
2942 FLD_GET(val, 23, 8));
2943 dsi_vc_flush_long_data(dsidev, channel);
2945 DSSERR("\tunknown datatype 0x%02x\n", dt);
2951 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2953 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2955 if (dsi->debug_write || dsi->debug_read)
2956 DSSDBG("dsi_vc_send_bta %d\n", channel);
2958 WARN_ON(!dsi_bus_is_locked(dsidev));
2960 /* RX_FIFO_NOT_EMPTY */
2961 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2962 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2963 dsi_vc_flush_receive_data(dsidev, channel);
2966 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2968 /* flush posted write */
2969 dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2974 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2976 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2977 DECLARE_COMPLETION_ONSTACK(completion);
2981 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2982 &completion, DSI_VC_IRQ_BTA);
2986 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2987 DSI_IRQ_ERROR_MASK);
2991 r = dsi_vc_send_bta(dsidev, channel);
2995 if (wait_for_completion_timeout(&completion,
2996 msecs_to_jiffies(500)) == 0) {
2997 DSSERR("Failed to receive BTA\n");
3002 err = dsi_get_errors(dsidev);
3004 DSSERR("Error while sending BTA: %x\n", err);
3009 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
3010 DSI_IRQ_ERROR_MASK);
3012 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
3013 &completion, DSI_VC_IRQ_BTA);
3017 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
3019 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
3020 int channel, u8 data_type, u16 len, u8 ecc)
3022 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3026 WARN_ON(!dsi_bus_is_locked(dsidev));
3028 data_id = data_type | dsi->vc[channel].vc_id << 6;
3030 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
3031 FLD_VAL(ecc, 31, 24);
3033 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
3036 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
3037 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
3041 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
3043 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
3044 b1, b2, b3, b4, val); */
3046 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
3049 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
3050 u8 data_type, u8 *data, u16 len, u8 ecc)
3053 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3059 if (dsi->debug_write)
3060 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
3063 if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
3064 DSSERR("unable to send long packet: packet too long.\n");
3068 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3070 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
3073 for (i = 0; i < len >> 2; i++) {
3074 if (dsi->debug_write)
3075 DSSDBG("\tsending full packet %d\n", i);
3082 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3087 b1 = 0; b2 = 0; b3 = 0;
3089 if (dsi->debug_write)
3090 DSSDBG("\tsending remainder bytes %d\n", i);
3107 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3113 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3114 u8 data_type, u16 data, u8 ecc)
3116 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3120 WARN_ON(!dsi_bus_is_locked(dsidev));
3122 if (dsi->debug_write)
3123 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3125 data_type, data & 0xff, (data >> 8) & 0xff);
3127 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3129 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3130 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3134 data_id = data_type | dsi->vc[channel].vc_id << 6;
3136 r = (data_id << 0) | (data << 8) | (ecc << 24);
3138 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3143 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3145 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3147 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3150 EXPORT_SYMBOL(dsi_vc_send_null);
3152 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
3153 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3158 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3159 r = dsi_vc_send_short(dsidev, channel,
3160 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3161 } else if (len == 1) {
3162 r = dsi_vc_send_short(dsidev, channel,
3163 type == DSS_DSI_CONTENT_GENERIC ?
3164 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3165 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3166 } else if (len == 2) {
3167 r = dsi_vc_send_short(dsidev, channel,
3168 type == DSS_DSI_CONTENT_GENERIC ?
3169 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3170 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3171 data[0] | (data[1] << 8), 0);
3173 r = dsi_vc_send_long(dsidev, channel,
3174 type == DSS_DSI_CONTENT_GENERIC ?
3175 MIPI_DSI_GENERIC_LONG_WRITE :
3176 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3182 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3185 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3187 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3188 DSS_DSI_CONTENT_DCS);
3190 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3192 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3195 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3197 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3198 DSS_DSI_CONTENT_GENERIC);
3200 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3202 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3203 u8 *data, int len, enum dss_dsi_content_type type)
3205 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3208 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
3212 r = dsi_vc_send_bta_sync(dssdev, channel);
3216 /* RX_FIFO_NOT_EMPTY */
3217 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3218 DSSERR("rx fifo not empty after write, dumping data:\n");
3219 dsi_vc_flush_receive_data(dsidev, channel);
3226 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3227 channel, data[0], len);
3231 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3234 return dsi_vc_write_common(dssdev, channel, data, len,
3235 DSS_DSI_CONTENT_DCS);
3237 EXPORT_SYMBOL(dsi_vc_dcs_write);
3239 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3242 return dsi_vc_write_common(dssdev, channel, data, len,
3243 DSS_DSI_CONTENT_GENERIC);
3245 EXPORT_SYMBOL(dsi_vc_generic_write);
3247 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3249 return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3251 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3253 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3255 return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3257 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3259 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3265 return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3267 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3269 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3272 return dsi_vc_generic_write(dssdev, channel, ¶m, 1);
3274 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3276 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3277 u8 param1, u8 param2)
3282 return dsi_vc_generic_write(dssdev, channel, buf, 2);
3284 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3286 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
3287 int channel, u8 dcs_cmd)
3289 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3292 if (dsi->debug_read)
3293 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3296 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3298 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3299 " failed\n", channel, dcs_cmd);
3306 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
3307 int channel, u8 *reqdata, int reqlen)
3309 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3314 if (dsi->debug_read)
3315 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3319 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3321 } else if (reqlen == 1) {
3322 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3324 } else if (reqlen == 2) {
3325 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3326 data = reqdata[0] | (reqdata[1] << 8);
3332 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3334 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3335 " failed\n", channel, reqlen);
3342 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3343 u8 *buf, int buflen, enum dss_dsi_content_type type)
3345 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3350 /* RX_FIFO_NOT_EMPTY */
3351 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3352 DSSERR("RX fifo empty when trying to read.\n");
3357 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3358 if (dsi->debug_read)
3359 DSSDBG("\theader: %08x\n", val);
3360 dt = FLD_GET(val, 5, 0);
3361 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3362 u16 err = FLD_GET(val, 23, 8);
3363 dsi_show_rx_ack_with_err(err);
3367 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3368 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3369 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3370 u8 data = FLD_GET(val, 15, 8);
3371 if (dsi->debug_read)
3372 DSSDBG("\t%s short response, 1 byte: %02x\n",
3373 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3384 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3385 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3386 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3387 u16 data = FLD_GET(val, 23, 8);
3388 if (dsi->debug_read)
3389 DSSDBG("\t%s short response, 2 byte: %04x\n",
3390 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3398 buf[0] = data & 0xff;
3399 buf[1] = (data >> 8) & 0xff;
3402 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3403 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3404 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3406 int len = FLD_GET(val, 23, 8);
3407 if (dsi->debug_read)
3408 DSSDBG("\t%s long response, len %d\n",
3409 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3417 /* two byte checksum ends the packet, not included in len */
3418 for (w = 0; w < len + 2;) {
3420 val = dsi_read_reg(dsidev,
3421 DSI_VC_SHORT_PACKET_HEADER(channel));
3422 if (dsi->debug_read)
3423 DSSDBG("\t\t%02x %02x %02x %02x\n",
3427 (val >> 24) & 0xff);
3429 for (b = 0; b < 4; ++b) {
3431 buf[w] = (val >> (b * 8)) & 0xff;
3432 /* we discard the 2 byte checksum */
3439 DSSERR("\tunknown datatype 0x%02x\n", dt);
3445 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3446 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3451 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3452 u8 *buf, int buflen)
3454 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3457 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3461 r = dsi_vc_send_bta_sync(dssdev, channel);
3465 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3466 DSS_DSI_CONTENT_DCS);
3477 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3480 EXPORT_SYMBOL(dsi_vc_dcs_read);
3482 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3483 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3485 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3488 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3492 r = dsi_vc_send_bta_sync(dssdev, channel);
3496 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3497 DSS_DSI_CONTENT_GENERIC);
3509 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3514 r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3516 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3522 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3524 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3525 u8 *buf, int buflen)
3529 r = dsi_vc_generic_read(dssdev, channel, ¶m, 1, buf, buflen);
3531 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3537 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3539 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3540 u8 param1, u8 param2, u8 *buf, int buflen)
3545 reqdata[0] = param1;
3546 reqdata[1] = param2;
3548 r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3550 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3556 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3558 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3561 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3563 return dsi_vc_send_short(dsidev, channel,
3564 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3566 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3568 static int dsi_enter_ulps(struct platform_device *dsidev)
3570 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3571 DECLARE_COMPLETION_ONSTACK(completion);
3577 WARN_ON(!dsi_bus_is_locked(dsidev));
3579 WARN_ON(dsi->ulps_enabled);
3581 if (dsi->ulps_enabled)
3584 /* DDR_CLK_ALWAYS_ON */
3585 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3586 dsi_if_enable(dsidev, 0);
3587 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3588 dsi_if_enable(dsidev, 1);
3591 dsi_sync_vc(dsidev, 0);
3592 dsi_sync_vc(dsidev, 1);
3593 dsi_sync_vc(dsidev, 2);
3594 dsi_sync_vc(dsidev, 3);
3596 dsi_force_tx_stop_mode_io(dsidev);
3598 dsi_vc_enable(dsidev, 0, false);
3599 dsi_vc_enable(dsidev, 1, false);
3600 dsi_vc_enable(dsidev, 2, false);
3601 dsi_vc_enable(dsidev, 3, false);
3603 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3604 DSSERR("HS busy when enabling ULPS\n");
3608 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3609 DSSERR("LP busy when enabling ULPS\n");
3613 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3614 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3620 for (i = 0; i < dsi->num_lanes_supported; ++i) {
3621 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3625 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3626 /* LANEx_ULPS_SIG2 */
3627 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3629 /* flush posted write and wait for SCP interface to finish the write */
3630 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3632 if (wait_for_completion_timeout(&completion,
3633 msecs_to_jiffies(1000)) == 0) {
3634 DSSERR("ULPS enable timeout\n");
3639 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3640 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3642 /* Reset LANEx_ULPS_SIG2 */
3643 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3645 /* flush posted write and wait for SCP interface to finish the write */
3646 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3648 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3650 dsi_if_enable(dsidev, false);
3652 dsi->ulps_enabled = true;
3657 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3658 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3662 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3663 unsigned ticks, bool x4, bool x16)
3666 unsigned long total_ticks;
3669 BUG_ON(ticks > 0x1fff);
3671 /* ticks in DSI_FCK */
3672 fck = dsi_fclk_rate(dsidev);
3674 r = dsi_read_reg(dsidev, DSI_TIMING2);
3675 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3676 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3677 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3678 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3679 dsi_write_reg(dsidev, DSI_TIMING2, r);
3681 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3683 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3685 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3686 (total_ticks * 1000) / (fck / 1000 / 1000));
3689 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3693 unsigned long total_ticks;
3696 BUG_ON(ticks > 0x1fff);
3698 /* ticks in DSI_FCK */
3699 fck = dsi_fclk_rate(dsidev);
3701 r = dsi_read_reg(dsidev, DSI_TIMING1);
3702 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3703 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3704 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3705 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3706 dsi_write_reg(dsidev, DSI_TIMING1, r);
3708 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3710 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3712 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3713 (total_ticks * 1000) / (fck / 1000 / 1000));
3716 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3717 unsigned ticks, bool x4, bool x16)
3720 unsigned long total_ticks;
3723 BUG_ON(ticks > 0x1fff);
3725 /* ticks in DSI_FCK */
3726 fck = dsi_fclk_rate(dsidev);
3728 r = dsi_read_reg(dsidev, DSI_TIMING1);
3729 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3730 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3731 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3732 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3733 dsi_write_reg(dsidev, DSI_TIMING1, r);
3735 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3737 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3739 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3740 (total_ticks * 1000) / (fck / 1000 / 1000));
3743 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3744 unsigned ticks, bool x4, bool x16)
3747 unsigned long total_ticks;
3750 BUG_ON(ticks > 0x1fff);
3752 /* ticks in TxByteClkHS */
3753 fck = dsi_get_txbyteclkhs(dsidev);
3755 r = dsi_read_reg(dsidev, DSI_TIMING2);
3756 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3757 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3758 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3759 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3760 dsi_write_reg(dsidev, DSI_TIMING2, r);
3762 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3764 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3766 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3767 (total_ticks * 1000) / (fck / 1000 / 1000));
3770 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3772 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3773 int num_line_buffers;
3775 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3776 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3777 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3778 struct omap_video_timings *timings = &dsi->timings;
3780 * Don't use line buffers if width is greater than the video
3781 * port's line buffer size
3783 if (line_buf_size <= timings->x_res * bpp / 8)
3784 num_line_buffers = 0;
3786 num_line_buffers = 2;
3788 /* Use maximum number of line buffers in command mode */
3789 num_line_buffers = 2;
3793 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3796 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3798 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3799 bool vsync_end = dsi->vm_timings.vp_vsync_end;
3800 bool hsync_end = dsi->vm_timings.vp_hsync_end;
3803 r = dsi_read_reg(dsidev, DSI_CTRL);
3804 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3805 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3806 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
3807 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3808 r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */
3809 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3810 r = FLD_MOD(r, hsync_end, 18, 18); /* VP_HSYNC_END */
3811 dsi_write_reg(dsidev, DSI_CTRL, r);
3814 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3816 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3817 int blanking_mode = dsi->vm_timings.blanking_mode;
3818 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3819 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3820 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3824 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3825 * 1 = Long blanking packets are sent in corresponding blanking periods
3827 r = dsi_read_reg(dsidev, DSI_CTRL);
3828 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3829 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3830 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3831 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3832 dsi_write_reg(dsidev, DSI_CTRL, r);
3836 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3837 * results in maximum transition time for data and clock lanes to enter and
3838 * exit HS mode. Hence, this is the scenario where the least amount of command
3839 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3840 * clock cycles that can be used to interleave command mode data in HS so that
3841 * all scenarios are satisfied.
3843 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3844 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3849 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3850 * time of data lanes only, if it isn't set, we need to consider HS
3851 * transition time of both data and clock lanes. HS transition time
3852 * of Scenario 3 is considered.
3855 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3858 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3859 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3861 transition = max(trans1, trans2);
3864 return blank > transition ? blank - transition : 0;
3868 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3869 * results in maximum transition time for data lanes to enter and exit LP mode.
3870 * Hence, this is the scenario where the least amount of command mode data can
3871 * be interleaved. We program the minimum amount of bytes that can be
3872 * interleaved in LP so that all scenarios are satisfied.
3874 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3875 int lp_clk_div, int tdsi_fclk)
3877 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
3878 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
3879 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
3880 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3881 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
3883 /* maximum LP transition time according to Scenario 1 */
3884 trans_lp = exit_hs + max(enter_hs, 2) + 1;
3886 /* CLKIN4DDR = 16 * TXBYTECLKHS */
3887 tlp_avail = thsbyte_clk * (blank - trans_lp);
3889 ttxclkesc = tdsi_fclk * lp_clk_div;
3891 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3894 return max(lp_inter, 0);
3897 static void dsi_config_cmd_mode_interleaving(struct omap_dss_device *dssdev)
3899 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3900 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3902 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3903 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3904 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3905 int tclk_trail, ths_exit, exiths_clk;
3907 struct omap_video_timings *timings = &dsi->timings;
3908 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3909 int ndl = dsi->num_lanes_used - 1;
3910 int dsi_fclk_hsdiv = dssdev->clocks.dsi.regm_dsi + 1;
3911 int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3912 int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3913 int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3914 int bl_interleave_hs = 0, bl_interleave_lp = 0;
3917 r = dsi_read_reg(dsidev, DSI_CTRL);
3918 blanking_mode = FLD_GET(r, 20, 20);
3919 hfp_blanking_mode = FLD_GET(r, 21, 21);
3920 hbp_blanking_mode = FLD_GET(r, 22, 22);
3921 hsa_blanking_mode = FLD_GET(r, 23, 23);
3923 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3924 hbp = FLD_GET(r, 11, 0);
3925 hfp = FLD_GET(r, 23, 12);
3926 hsa = FLD_GET(r, 31, 24);
3928 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3929 ddr_clk_post = FLD_GET(r, 7, 0);
3930 ddr_clk_pre = FLD_GET(r, 15, 8);
3932 r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3933 exit_hs_mode_lat = FLD_GET(r, 15, 0);
3934 enter_hs_mode_lat = FLD_GET(r, 31, 16);
3936 r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3937 lp_clk_div = FLD_GET(r, 12, 0);
3938 ddr_alwon = FLD_GET(r, 13, 13);
3940 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3941 ths_exit = FLD_GET(r, 7, 0);
3943 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3944 tclk_trail = FLD_GET(r, 15, 8);
3946 exiths_clk = ths_exit + tclk_trail;
3948 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3949 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3951 if (!hsa_blanking_mode) {
3952 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3953 enter_hs_mode_lat, exit_hs_mode_lat,
3954 exiths_clk, ddr_clk_pre, ddr_clk_post);
3955 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3956 enter_hs_mode_lat, exit_hs_mode_lat,
3957 lp_clk_div, dsi_fclk_hsdiv);
3960 if (!hfp_blanking_mode) {
3961 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3962 enter_hs_mode_lat, exit_hs_mode_lat,
3963 exiths_clk, ddr_clk_pre, ddr_clk_post);
3964 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3965 enter_hs_mode_lat, exit_hs_mode_lat,
3966 lp_clk_div, dsi_fclk_hsdiv);
3969 if (!hbp_blanking_mode) {
3970 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3971 enter_hs_mode_lat, exit_hs_mode_lat,
3972 exiths_clk, ddr_clk_pre, ddr_clk_post);
3974 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3975 enter_hs_mode_lat, exit_hs_mode_lat,
3976 lp_clk_div, dsi_fclk_hsdiv);
3979 if (!blanking_mode) {
3980 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3981 enter_hs_mode_lat, exit_hs_mode_lat,
3982 exiths_clk, ddr_clk_pre, ddr_clk_post);
3984 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3985 enter_hs_mode_lat, exit_hs_mode_lat,
3986 lp_clk_div, dsi_fclk_hsdiv);
3989 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3990 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3993 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3994 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3997 r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3998 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3999 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
4000 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
4001 dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
4003 r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
4004 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
4005 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
4006 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
4007 dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
4009 r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
4010 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
4011 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
4012 dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
4015 static int dsi_proto_config(struct omap_dss_device *dssdev)
4017 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4018 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4022 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
4027 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
4032 /* XXX what values for the timeouts? */
4033 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
4034 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
4035 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
4036 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
4038 switch (dsi_get_pixel_size(dsi->pix_fmt)) {
4053 r = dsi_read_reg(dsidev, DSI_CTRL);
4054 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
4055 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
4056 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
4057 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
4058 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
4059 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
4060 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
4061 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
4062 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
4063 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
4064 /* DCS_CMD_CODE, 1=start, 0=continue */
4065 r = FLD_MOD(r, 0, 25, 25);
4068 dsi_write_reg(dsidev, DSI_CTRL, r);
4070 dsi_config_vp_num_line_buffers(dsidev);
4072 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4073 dsi_config_vp_sync_events(dsidev);
4074 dsi_config_blanking_modes(dsidev);
4075 dsi_config_cmd_mode_interleaving(dssdev);
4078 dsi_vc_initial_config(dsidev, 0);
4079 dsi_vc_initial_config(dsidev, 1);
4080 dsi_vc_initial_config(dsidev, 2);
4081 dsi_vc_initial_config(dsidev, 3);
4086 static void dsi_proto_timings(struct platform_device *dsidev)
4088 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4089 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
4090 unsigned tclk_pre, tclk_post;
4091 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
4092 unsigned ths_trail, ths_exit;
4093 unsigned ddr_clk_pre, ddr_clk_post;
4094 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
4096 int ndl = dsi->num_lanes_used - 1;
4099 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
4100 ths_prepare = FLD_GET(r, 31, 24);
4101 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
4102 ths_zero = ths_prepare_ths_zero - ths_prepare;
4103 ths_trail = FLD_GET(r, 15, 8);
4104 ths_exit = FLD_GET(r, 7, 0);
4106 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
4107 tlpx = FLD_GET(r, 20, 16) * 2;
4108 tclk_trail = FLD_GET(r, 15, 8);
4109 tclk_zero = FLD_GET(r, 7, 0);
4111 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
4112 tclk_prepare = FLD_GET(r, 7, 0);
4116 /* min 60ns + 52*UI */
4117 tclk_post = ns2ddr(dsidev, 60) + 26;
4119 ths_eot = DIV_ROUND_UP(4, ndl);
4121 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
4123 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
4125 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
4126 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
4128 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
4129 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
4130 r = FLD_MOD(r, ddr_clk_post, 7, 0);
4131 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
4133 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
4137 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
4138 DIV_ROUND_UP(ths_prepare, 4) +
4139 DIV_ROUND_UP(ths_zero + 3, 4);
4141 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
4143 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
4144 FLD_VAL(exit_hs_mode_lat, 15, 0);
4145 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
4147 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
4148 enter_hs_mode_lat, exit_hs_mode_lat);
4150 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4151 /* TODO: Implement a video mode check_timings function */
4152 int hsa = dsi->vm_timings.hsa;
4153 int hfp = dsi->vm_timings.hfp;
4154 int hbp = dsi->vm_timings.hbp;
4155 int vsa = dsi->vm_timings.vsa;
4156 int vfp = dsi->vm_timings.vfp;
4157 int vbp = dsi->vm_timings.vbp;
4158 int window_sync = dsi->vm_timings.window_sync;
4159 bool hsync_end = dsi->vm_timings.vp_hsync_end;
4160 struct omap_video_timings *timings = &dsi->timings;
4161 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4162 int tl, t_he, width_bytes;
4165 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
4167 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
4169 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
4170 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
4171 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
4173 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
4174 hfp, hsync_end ? hsa : 0, tl);
4175 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
4176 vsa, timings->y_res);
4178 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
4179 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
4180 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
4181 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
4182 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
4184 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
4185 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
4186 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
4187 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
4188 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
4189 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
4191 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
4192 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
4193 r = FLD_MOD(r, tl, 31, 16); /* TL */
4194 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
4198 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
4199 const struct omap_dsi_pin_config *pin_cfg)
4201 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4202 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4205 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
4209 static const enum dsi_lane_function functions[] = {
4217 num_pins = pin_cfg->num_pins;
4218 pins = pin_cfg->pins;
4220 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
4221 || num_pins % 2 != 0)
4224 for (i = 0; i < DSI_MAX_NR_LANES; ++i)
4225 lanes[i].function = DSI_LANE_UNUSED;
4229 for (i = 0; i < num_pins; i += 2) {
4236 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
4239 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
4254 lanes[lane].function = functions[i / 2];
4255 lanes[lane].polarity = pol;
4259 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
4260 dsi->num_lanes_used = num_lanes;
4264 EXPORT_SYMBOL(omapdss_dsi_configure_pins);
4266 int omapdss_dsi_set_clocks(struct omap_dss_device *dssdev,
4267 unsigned long ddr_clk, unsigned long lp_clk)
4269 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4270 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4271 struct dsi_clock_info cinfo;
4272 struct dispc_clock_info dispc_cinfo;
4273 unsigned lp_clk_div;
4274 unsigned long dsi_fclk;
4275 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
4279 DSSDBGF("ddr_clk %lu, lp_clk %lu", ddr_clk, lp_clk);
4281 mutex_lock(&dsi->lock);
4283 /* Calculate PLL output clock */
4284 r = dsi_pll_calc_ddrfreq(dsidev, ddr_clk * 4, &cinfo);
4288 /* Calculate PLL's DSI clock */
4289 dsi_pll_calc_dsi_fck(dsidev, &cinfo);
4291 /* Calculate PLL's DISPC clock and pck & lck divs */
4292 pck = cinfo.clkin4ddr / 16 * (dsi->num_lanes_used - 1) * 8 / bpp;
4293 DSSDBG("finding dispc dividers for pck %lu\n", pck);
4294 r = dsi_pll_calc_dispc_fck(dsidev, pck, &cinfo, &dispc_cinfo);
4298 /* Calculate LP clock */
4299 dsi_fclk = cinfo.dsi_pll_hsdiv_dsi_clk;
4300 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk * 2);
4302 dssdev->clocks.dsi.regn = cinfo.regn;
4303 dssdev->clocks.dsi.regm = cinfo.regm;
4304 dssdev->clocks.dsi.regm_dispc = cinfo.regm_dispc;
4305 dssdev->clocks.dsi.regm_dsi = cinfo.regm_dsi;
4307 dssdev->clocks.dsi.lp_clk_div = lp_clk_div;
4309 dssdev->clocks.dispc.channel.lck_div = dispc_cinfo.lck_div;
4310 dssdev->clocks.dispc.channel.pck_div = dispc_cinfo.pck_div;
4312 dssdev->clocks.dispc.dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK;
4314 dssdev->clocks.dispc.channel.lcd_clk_src =
4315 dsi->module_id == 0 ?
4316 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4317 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
4319 dssdev->clocks.dsi.dsi_fclk_src =
4320 dsi->module_id == 0 ?
4321 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4322 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI;
4324 mutex_unlock(&dsi->lock);
4327 mutex_unlock(&dsi->lock);
4330 EXPORT_SYMBOL(omapdss_dsi_set_clocks);
4332 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
4334 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4335 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4336 struct omap_overlay_manager *mgr = dssdev->output->manager;
4337 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4342 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4343 switch (dsi->pix_fmt) {
4344 case OMAP_DSS_DSI_FMT_RGB888:
4345 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
4347 case OMAP_DSS_DSI_FMT_RGB666:
4348 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
4350 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
4351 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
4353 case OMAP_DSS_DSI_FMT_RGB565:
4354 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
4361 dsi_if_enable(dsidev, false);
4362 dsi_vc_enable(dsidev, channel, false);
4364 /* MODE, 1 = video mode */
4365 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
4367 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
4369 dsi_vc_write_long_header(dsidev, channel, data_type,
4372 dsi_vc_enable(dsidev, channel, true);
4373 dsi_if_enable(dsidev, true);
4376 r = dss_mgr_enable(mgr);
4378 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4379 dsi_if_enable(dsidev, false);
4380 dsi_vc_enable(dsidev, channel, false);
4388 EXPORT_SYMBOL(dsi_enable_video_output);
4390 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4392 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4393 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4394 struct omap_overlay_manager *mgr = dssdev->output->manager;
4396 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4397 dsi_if_enable(dsidev, false);
4398 dsi_vc_enable(dsidev, channel, false);
4400 /* MODE, 0 = command mode */
4401 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4403 dsi_vc_enable(dsidev, channel, true);
4404 dsi_if_enable(dsidev, true);
4407 dss_mgr_disable(mgr);
4409 EXPORT_SYMBOL(dsi_disable_video_output);
4411 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev)
4413 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4414 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4415 struct omap_overlay_manager *mgr = dssdev->output->manager;
4420 unsigned packet_payload;
4421 unsigned packet_len;
4424 const unsigned channel = dsi->update_channel;
4425 const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4426 u16 w = dsi->timings.x_res;
4427 u16 h = dsi->timings.y_res;
4429 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4431 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4433 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
4434 bytespl = w * bytespp;
4435 bytespf = bytespl * h;
4437 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4438 * number of lines in a packet. See errata about VP_CLK_RATIO */
4440 if (bytespf < line_buf_size)
4441 packet_payload = bytespf;
4443 packet_payload = (line_buf_size) / bytespl * bytespl;
4445 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
4446 total_len = (bytespf / packet_payload) * packet_len;
4448 if (bytespf % packet_payload)
4449 total_len += (bytespf % packet_payload) + 1;
4451 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4452 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4454 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4457 if (dsi->te_enabled)
4458 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4460 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4461 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4463 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4464 * because DSS interrupts are not capable of waking up the CPU and the
4465 * framedone interrupt could be delayed for quite a long time. I think
4466 * the same goes for any DSS interrupts, but for some reason I have not
4467 * seen the problem anywhere else than here.
4469 dispc_disable_sidle();
4471 dsi_perf_mark_start(dsidev);
4473 r = schedule_delayed_work(&dsi->framedone_timeout_work,
4474 msecs_to_jiffies(250));
4477 dss_mgr_set_timings(mgr, &dsi->timings);
4479 dss_mgr_start_update(mgr);
4481 if (dsi->te_enabled) {
4482 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4483 * for TE is longer than the timer allows */
4484 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4486 dsi_vc_send_bta(dsidev, channel);
4488 #ifdef DSI_CATCH_MISSING_TE
4489 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4494 #ifdef DSI_CATCH_MISSING_TE
4495 static void dsi_te_timeout(unsigned long arg)
4497 DSSERR("TE not received for 250ms!\n");
4501 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4503 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4505 /* SIDLEMODE back to smart-idle */
4506 dispc_enable_sidle();
4508 if (dsi->te_enabled) {
4509 /* enable LP_RX_TO again after the TE */
4510 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4513 dsi->framedone_callback(error, dsi->framedone_data);
4516 dsi_perf_show(dsidev, "DISPC");
4519 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4521 struct dsi_data *dsi = container_of(work, struct dsi_data,
4522 framedone_timeout_work.work);
4523 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4524 * 250ms which would conflict with this timeout work. What should be
4525 * done is first cancel the transfer on the HW, and then cancel the
4526 * possibly scheduled framedone work. However, cancelling the transfer
4527 * on the HW is buggy, and would probably require resetting the whole
4530 DSSERR("Framedone not received for 250ms!\n");
4532 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4535 static void dsi_framedone_irq_callback(void *data, u32 mask)
4537 struct platform_device *dsidev = (struct platform_device *) data;
4538 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4540 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4541 * turns itself off. However, DSI still has the pixels in its buffers,
4542 * and is sending the data.
4545 cancel_delayed_work(&dsi->framedone_timeout_work);
4547 dsi_handle_framedone(dsidev, 0);
4550 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
4551 void (*callback)(int, void *), void *data)
4553 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4554 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4557 dsi_perf_mark_setup(dsidev);
4559 dsi->update_channel = channel;
4561 dsi->framedone_callback = callback;
4562 dsi->framedone_data = data;
4564 dw = dsi->timings.x_res;
4565 dh = dsi->timings.y_res;
4568 dsi->update_bytes = dw * dh *
4569 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4571 dsi_update_screen_dispc(dssdev);
4575 EXPORT_SYMBOL(omap_dsi_update);
4579 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4581 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4582 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4583 struct dispc_clock_info dispc_cinfo;
4585 unsigned long long fck;
4587 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4589 dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4590 dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4592 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4594 DSSERR("Failed to calc dispc clocks\n");
4598 dsi->mgr_config.clock_info = dispc_cinfo;
4603 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4605 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4606 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4607 struct omap_overlay_manager *mgr = dssdev->output->manager;
4611 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4612 dsi->timings.hsw = 1;
4613 dsi->timings.hfp = 1;
4614 dsi->timings.hbp = 1;
4615 dsi->timings.vsw = 1;
4616 dsi->timings.vfp = 0;
4617 dsi->timings.vbp = 0;
4619 irq = dispc_mgr_get_framedone_irq(mgr->id);
4621 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4622 (void *) dsidev, irq);
4624 DSSERR("can't get FRAMEDONE irq\n");
4628 dsi->mgr_config.stallmode = true;
4629 dsi->mgr_config.fifohandcheck = true;
4631 dsi->mgr_config.stallmode = false;
4632 dsi->mgr_config.fifohandcheck = false;
4636 * override interlace, logic level and edge related parameters in
4637 * omap_video_timings with default values
4639 dsi->timings.interlace = false;
4640 dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4641 dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4642 dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4643 dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4644 dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
4646 dss_mgr_set_timings(mgr, &dsi->timings);
4648 r = dsi_configure_dispc_clocks(dssdev);
4652 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4653 dsi->mgr_config.video_port_width =
4654 dsi_get_pixel_size(dsi->pix_fmt);
4655 dsi->mgr_config.lcden_sig_polarity = 0;
4657 dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
4661 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4662 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4663 (void *) dsidev, irq);
4668 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4670 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4671 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4672 struct omap_overlay_manager *mgr = dssdev->output->manager;
4674 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4677 irq = dispc_mgr_get_framedone_irq(mgr->id);
4679 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4680 (void *) dsidev, irq);
4684 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4686 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4687 struct dsi_clock_info cinfo;
4690 cinfo.regn = dssdev->clocks.dsi.regn;
4691 cinfo.regm = dssdev->clocks.dsi.regm;
4692 cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4693 cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4694 r = dsi_calc_clock_rates(dsidev, &cinfo);
4696 DSSERR("Failed to calc dsi clocks\n");
4700 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4702 DSSERR("Failed to set dsi clocks\n");
4709 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4711 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4712 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4713 struct omap_overlay_manager *mgr = dssdev->output->manager;
4716 r = dsi_pll_init(dsidev, true, true);
4720 r = dsi_configure_dsi_clocks(dssdev);
4724 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4725 dss_select_dsi_clk_source(dsi->module_id, dssdev->clocks.dsi.dsi_fclk_src);
4726 dss_select_lcd_clk_source(mgr->id,
4727 dssdev->clocks.dispc.channel.lcd_clk_src);
4731 r = dsi_cio_init(dsidev);
4735 _dsi_print_reset_status(dsidev);
4737 dsi_proto_timings(dsidev);
4738 dsi_set_lp_clk_divisor(dssdev);
4741 _dsi_print_reset_status(dsidev);
4743 r = dsi_proto_config(dssdev);
4747 /* enable interface */
4748 dsi_vc_enable(dsidev, 0, 1);
4749 dsi_vc_enable(dsidev, 1, 1);
4750 dsi_vc_enable(dsidev, 2, 1);
4751 dsi_vc_enable(dsidev, 3, 1);
4752 dsi_if_enable(dsidev, 1);
4753 dsi_force_tx_stop_mode_io(dsidev);
4757 dsi_cio_uninit(dsidev);
4759 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4760 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4761 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4764 dsi_pll_uninit(dsidev, true);
4769 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4770 bool disconnect_lanes, bool enter_ulps)
4772 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4773 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4774 struct omap_overlay_manager *mgr = dssdev->output->manager;
4776 if (enter_ulps && !dsi->ulps_enabled)
4777 dsi_enter_ulps(dsidev);
4779 /* disable interface */
4780 dsi_if_enable(dsidev, 0);
4781 dsi_vc_enable(dsidev, 0, 0);
4782 dsi_vc_enable(dsidev, 1, 0);
4783 dsi_vc_enable(dsidev, 2, 0);
4784 dsi_vc_enable(dsidev, 3, 0);
4786 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4787 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4788 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4789 dsi_cio_uninit(dsidev);
4790 dsi_pll_uninit(dsidev, disconnect_lanes);
4793 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4795 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4796 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4797 struct omap_dss_output *out = dssdev->output;
4800 DSSDBG("dsi_display_enable\n");
4802 WARN_ON(!dsi_bus_is_locked(dsidev));
4804 mutex_lock(&dsi->lock);
4806 if (out == NULL || out->manager == NULL) {
4807 DSSERR("failed to enable display: no output/manager\n");
4812 r = omap_dss_start_device(dssdev);
4814 DSSERR("failed to start device\n");
4818 r = dsi_runtime_get(dsidev);
4822 dsi_enable_pll_clock(dsidev, 1);
4824 _dsi_initialize_irq(dsidev);
4826 r = dsi_display_init_dispc(dssdev);
4828 goto err_init_dispc;
4830 r = dsi_display_init_dsi(dssdev);
4834 mutex_unlock(&dsi->lock);
4839 dsi_display_uninit_dispc(dssdev);
4841 dsi_enable_pll_clock(dsidev, 0);
4842 dsi_runtime_put(dsidev);
4844 omap_dss_stop_device(dssdev);
4846 mutex_unlock(&dsi->lock);
4847 DSSDBG("dsi_display_enable FAILED\n");
4850 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4852 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4853 bool disconnect_lanes, bool enter_ulps)
4855 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4856 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4858 DSSDBG("dsi_display_disable\n");
4860 WARN_ON(!dsi_bus_is_locked(dsidev));
4862 mutex_lock(&dsi->lock);
4864 dsi_sync_vc(dsidev, 0);
4865 dsi_sync_vc(dsidev, 1);
4866 dsi_sync_vc(dsidev, 2);
4867 dsi_sync_vc(dsidev, 3);
4869 dsi_display_uninit_dispc(dssdev);
4871 dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4873 dsi_runtime_put(dsidev);
4874 dsi_enable_pll_clock(dsidev, 0);
4876 omap_dss_stop_device(dssdev);
4878 mutex_unlock(&dsi->lock);
4880 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4882 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4884 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4885 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4887 dsi->te_enabled = enable;
4890 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4892 void omapdss_dsi_set_timings(struct omap_dss_device *dssdev,
4893 struct omap_video_timings *timings)
4895 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4896 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4898 mutex_lock(&dsi->lock);
4900 dsi->timings = *timings;
4902 mutex_unlock(&dsi->lock);
4904 EXPORT_SYMBOL(omapdss_dsi_set_timings);
4906 void omapdss_dsi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h)
4908 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4909 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4911 mutex_lock(&dsi->lock);
4913 dsi->timings.x_res = w;
4914 dsi->timings.y_res = h;
4916 mutex_unlock(&dsi->lock);
4918 EXPORT_SYMBOL(omapdss_dsi_set_size);
4920 void omapdss_dsi_set_pixel_format(struct omap_dss_device *dssdev,
4921 enum omap_dss_dsi_pixel_format fmt)
4923 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4924 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4926 mutex_lock(&dsi->lock);
4930 mutex_unlock(&dsi->lock);
4932 EXPORT_SYMBOL(omapdss_dsi_set_pixel_format);
4934 void omapdss_dsi_set_operation_mode(struct omap_dss_device *dssdev,
4935 enum omap_dss_dsi_mode mode)
4937 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4938 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4940 mutex_lock(&dsi->lock);
4944 mutex_unlock(&dsi->lock);
4946 EXPORT_SYMBOL(omapdss_dsi_set_operation_mode);
4948 void omapdss_dsi_set_videomode_timings(struct omap_dss_device *dssdev,
4949 struct omap_dss_dsi_videomode_timings *timings)
4951 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4952 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4954 mutex_lock(&dsi->lock);
4956 dsi->vm_timings = *timings;
4958 mutex_unlock(&dsi->lock);
4960 EXPORT_SYMBOL(omapdss_dsi_set_videomode_timings);
4962 static int __init dsi_init_display(struct omap_dss_device *dssdev)
4964 struct platform_device *dsidev =
4965 dsi_get_dsidev_from_id(dssdev->phy.dsi.module);
4966 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4968 DSSDBG("DSI init\n");
4970 if (dsi->vdds_dsi_reg == NULL) {
4971 struct regulator *vdds_dsi;
4973 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4975 if (IS_ERR(vdds_dsi)) {
4976 DSSERR("can't get VDDS_DSI regulator\n");
4977 return PTR_ERR(vdds_dsi);
4980 dsi->vdds_dsi_reg = vdds_dsi;
4986 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4988 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4989 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4992 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4993 if (!dsi->vc[i].dssdev) {
4994 dsi->vc[i].dssdev = dssdev;
5000 DSSERR("cannot get VC for display %s", dssdev->name);
5003 EXPORT_SYMBOL(omap_dsi_request_vc);
5005 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
5007 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5008 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5010 if (vc_id < 0 || vc_id > 3) {
5011 DSSERR("VC ID out of range\n");
5015 if (channel < 0 || channel > 3) {
5016 DSSERR("Virtual Channel out of range\n");
5020 if (dsi->vc[channel].dssdev != dssdev) {
5021 DSSERR("Virtual Channel not allocated to display %s\n",
5026 dsi->vc[channel].vc_id = vc_id;
5030 EXPORT_SYMBOL(omap_dsi_set_vc_id);
5032 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
5034 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5035 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5037 if ((channel >= 0 && channel <= 3) &&
5038 dsi->vc[channel].dssdev == dssdev) {
5039 dsi->vc[channel].dssdev = NULL;
5040 dsi->vc[channel].vc_id = 0;
5043 EXPORT_SYMBOL(omap_dsi_release_vc);
5045 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
5047 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
5048 DSSERR("%s (%s) not active\n",
5049 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
5050 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
5053 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
5055 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
5056 DSSERR("%s (%s) not active\n",
5057 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
5058 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
5061 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
5063 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5065 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
5066 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
5067 dsi->regm_dispc_max =
5068 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
5069 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
5070 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
5071 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
5072 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
5075 static int dsi_get_clocks(struct platform_device *dsidev)
5077 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5080 clk = clk_get(&dsidev->dev, "fck");
5082 DSSERR("can't get fck\n");
5083 return PTR_ERR(clk);
5088 clk = clk_get(&dsidev->dev, "sys_clk");
5090 DSSERR("can't get sys_clk\n");
5091 clk_put(dsi->dss_clk);
5092 dsi->dss_clk = NULL;
5093 return PTR_ERR(clk);
5101 static void dsi_put_clocks(struct platform_device *dsidev)
5103 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5106 clk_put(dsi->dss_clk);
5108 clk_put(dsi->sys_clk);
5111 static struct omap_dss_device * __init dsi_find_dssdev(struct platform_device *pdev)
5113 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
5114 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5115 const char *def_disp_name = dss_get_default_display_name();
5116 struct omap_dss_device *def_dssdev;
5121 for (i = 0; i < pdata->num_devices; ++i) {
5122 struct omap_dss_device *dssdev = pdata->devices[i];
5124 if (dssdev->type != OMAP_DISPLAY_TYPE_DSI)
5127 if (dssdev->phy.dsi.module != dsi->module_id)
5130 if (def_dssdev == NULL)
5131 def_dssdev = dssdev;
5133 if (def_disp_name != NULL &&
5134 strcmp(dssdev->name, def_disp_name) == 0) {
5135 def_dssdev = dssdev;
5143 static void __init dsi_probe_pdata(struct platform_device *dsidev)
5145 struct omap_dss_device *plat_dssdev;
5146 struct omap_dss_device *dssdev;
5149 plat_dssdev = dsi_find_dssdev(dsidev);
5154 dssdev = dss_alloc_and_init_device(&dsidev->dev);
5158 dss_copy_device_pdata(dssdev, plat_dssdev);
5160 r = dsi_init_display(dssdev);
5162 DSSERR("device %s init failed: %d\n", dssdev->name, r);
5163 dss_put_device(dssdev);
5167 r = dss_add_device(dssdev);
5169 DSSERR("device %s register failed: %d\n", dssdev->name, r);
5170 dss_put_device(dssdev);
5175 static void __init dsi_init_output(struct platform_device *dsidev)
5177 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5178 struct omap_dss_output *out = &dsi->output;
5181 out->id = dsi->module_id == 0 ?
5182 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5184 out->type = OMAP_DISPLAY_TYPE_DSI;
5186 dss_register_output(out);
5189 static void __exit dsi_uninit_output(struct platform_device *dsidev)
5191 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5192 struct omap_dss_output *out = &dsi->output;
5194 dss_unregister_output(out);
5197 /* DSI1 HW IP initialisation */
5198 static int __init omap_dsihw_probe(struct platform_device *dsidev)
5202 struct resource *dsi_mem;
5203 struct dsi_data *dsi;
5205 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5209 dsi->module_id = dsidev->id;
5211 dev_set_drvdata(&dsidev->dev, dsi);
5213 spin_lock_init(&dsi->irq_lock);
5214 spin_lock_init(&dsi->errors_lock);
5217 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5218 spin_lock_init(&dsi->irq_stats_lock);
5219 dsi->irq_stats.last_reset = jiffies;
5222 mutex_init(&dsi->lock);
5223 sema_init(&dsi->bus_lock, 1);
5225 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5226 dsi_framedone_timeout_work_callback);
5228 #ifdef DSI_CATCH_MISSING_TE
5229 init_timer(&dsi->te_timer);
5230 dsi->te_timer.function = dsi_te_timeout;
5231 dsi->te_timer.data = 0;
5233 dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
5235 DSSERR("can't get IORESOURCE_MEM DSI\n");
5239 dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start,
5240 resource_size(dsi_mem));
5242 DSSERR("can't ioremap DSI\n");
5246 dsi->irq = platform_get_irq(dsi->pdev, 0);
5248 DSSERR("platform_get_irq failed\n");
5252 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5253 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5255 DSSERR("request_irq failed\n");
5259 /* DSI VCs initialization */
5260 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5261 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5262 dsi->vc[i].dssdev = NULL;
5263 dsi->vc[i].vc_id = 0;
5266 dsi_calc_clock_param_ranges(dsidev);
5268 r = dsi_get_clocks(dsidev);
5272 pm_runtime_enable(&dsidev->dev);
5274 r = dsi_runtime_get(dsidev);
5276 goto err_runtime_get;
5278 rev = dsi_read_reg(dsidev, DSI_REVISION);
5279 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5280 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5282 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5283 * of data to 3 by default */
5284 if (dss_has_feature(FEAT_DSI_GNQ))
5286 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5288 dsi->num_lanes_supported = 3;
5290 dsi_init_output(dsidev);
5292 dsi_probe_pdata(dsidev);
5294 dsi_runtime_put(dsidev);
5296 if (dsi->module_id == 0)
5297 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5298 else if (dsi->module_id == 1)
5299 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5301 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5302 if (dsi->module_id == 0)
5303 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5304 else if (dsi->module_id == 1)
5305 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5310 pm_runtime_disable(&dsidev->dev);
5311 dsi_put_clocks(dsidev);
5315 static int __exit omap_dsihw_remove(struct platform_device *dsidev)
5317 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5319 WARN_ON(dsi->scp_clk_refcount > 0);
5321 dss_unregister_child_devices(&dsidev->dev);
5323 dsi_uninit_output(dsidev);
5325 pm_runtime_disable(&dsidev->dev);
5327 dsi_put_clocks(dsidev);
5329 if (dsi->vdds_dsi_reg != NULL) {
5330 if (dsi->vdds_dsi_enabled) {
5331 regulator_disable(dsi->vdds_dsi_reg);
5332 dsi->vdds_dsi_enabled = false;
5335 regulator_put(dsi->vdds_dsi_reg);
5336 dsi->vdds_dsi_reg = NULL;
5342 static int dsi_runtime_suspend(struct device *dev)
5344 dispc_runtime_put();
5349 static int dsi_runtime_resume(struct device *dev)
5353 r = dispc_runtime_get();
5360 static const struct dev_pm_ops dsi_pm_ops = {
5361 .runtime_suspend = dsi_runtime_suspend,
5362 .runtime_resume = dsi_runtime_resume,
5365 static struct platform_driver omap_dsihw_driver = {
5366 .remove = __exit_p(omap_dsihw_remove),
5368 .name = "omapdss_dsi",
5369 .owner = THIS_MODULE,
5374 int __init dsi_init_platform_driver(void)
5376 return platform_driver_probe(&omap_dsihw_driver, omap_dsihw_probe);
5379 void __exit dsi_uninit_platform_driver(void)
5381 platform_driver_unregister(&omap_dsihw_driver);