drivers/video/omap2/dss/dispc.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.h
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  * Author: Archit Taneja <archit@ti.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef __OMAP2_DISPC_REG_H
  22 #define __OMAP2_DISPC_REG_H
  23
  24 /* DISPC common registers */
  25 #define DISPC_REVISION                  0x0000
  26 #define DISPC_SYSCONFIG                 0x0010
  27 #define DISPC_SYSSTATUS                 0x0014
  28 #define DISPC_IRQSTATUS                 0x0018
  29 #define DISPC_IRQENABLE                 0x001C
  30 #define DISPC_CONTROL                   0x0040
  31 #define DISPC_CONFIG                    0x0044
  32 #define DISPC_CAPABLE                   0x0048
  33 #define DISPC_LINE_STATUS               0x005C
  34 #define DISPC_LINE_NUMBER               0x0060
  35 #define DISPC_GLOBAL_ALPHA              0x0074
  36 #define DISPC_CONTROL2                  0x0238
  37 #define DISPC_CONFIG2                   0x0620
  38 #define DISPC_DIVISOR                   0x0804
  39
  40 /* DISPC overlay registers */
  41 #define DISPC_OVL_BA0(n)                (DISPC_OVL_BASE(n) + \
  42                                         DISPC_BA0_OFFSET(n))
  43 #define DISPC_OVL_BA1(n)                (DISPC_OVL_BASE(n) + \
  44                                         DISPC_BA1_OFFSET(n))
  45 #define DISPC_OVL_BA0_UV(n)             (DISPC_OVL_BASE(n) + \
  46                                         DISPC_BA0_UV_OFFSET(n))
  47 #define DISPC_OVL_BA1_UV(n)             (DISPC_OVL_BASE(n) + \
  48                                         DISPC_BA1_UV_OFFSET(n))
  49 #define DISPC_OVL_POSITION(n)           (DISPC_OVL_BASE(n) + \
  50                                         DISPC_POS_OFFSET(n))
  51 #define DISPC_OVL_SIZE(n)               (DISPC_OVL_BASE(n) + \
  52                                         DISPC_SIZE_OFFSET(n))
  53 #define DISPC_OVL_ATTRIBUTES(n)         (DISPC_OVL_BASE(n) + \
  54                                         DISPC_ATTR_OFFSET(n))
  55 #define DISPC_OVL_ATTRIBUTES2(n)        (DISPC_OVL_BASE(n) + \
  56                                         DISPC_ATTR2_OFFSET(n))
  57 #define DISPC_OVL_FIFO_THRESHOLD(n)     (DISPC_OVL_BASE(n) + \
  58                                         DISPC_FIFO_THRESH_OFFSET(n))
  59 #define DISPC_OVL_FIFO_SIZE_STATUS(n)   (DISPC_OVL_BASE(n) + \
  60                                         DISPC_FIFO_SIZE_STATUS_OFFSET(n))
  61 #define DISPC_OVL_ROW_INC(n)            (DISPC_OVL_BASE(n) + \
  62                                         DISPC_ROW_INC_OFFSET(n))
  63 #define DISPC_OVL_PIXEL_INC(n)          (DISPC_OVL_BASE(n) + \
  64                                         DISPC_PIX_INC_OFFSET(n))
  65 #define DISPC_OVL_WINDOW_SKIP(n)        (DISPC_OVL_BASE(n) + \
  66                                         DISPC_WINDOW_SKIP_OFFSET(n))
  67 #define DISPC_OVL_TABLE_BA(n)           (DISPC_OVL_BASE(n) + \
  68                                         DISPC_TABLE_BA_OFFSET(n))
  69 #define DISPC_OVL_FIR(n)                (DISPC_OVL_BASE(n) + \
  70                                         DISPC_FIR_OFFSET(n))
  71 #define DISPC_OVL_FIR2(n)               (DISPC_OVL_BASE(n) + \
  72                                         DISPC_FIR2_OFFSET(n))
  73 #define DISPC_OVL_PICTURE_SIZE(n)       (DISPC_OVL_BASE(n) + \
  74                                         DISPC_PIC_SIZE_OFFSET(n))
  75 #define DISPC_OVL_ACCU0(n)              (DISPC_OVL_BASE(n) + \
  76                                         DISPC_ACCU0_OFFSET(n))
  77 #define DISPC_OVL_ACCU1(n)              (DISPC_OVL_BASE(n) + \
  78                                         DISPC_ACCU1_OFFSET(n))
  79 #define DISPC_OVL_ACCU2_0(n)            (DISPC_OVL_BASE(n) + \
  80                                         DISPC_ACCU2_0_OFFSET(n))
  81 #define DISPC_OVL_ACCU2_1(n)            (DISPC_OVL_BASE(n) + \
  82                                         DISPC_ACCU2_1_OFFSET(n))
  83 #define DISPC_OVL_FIR_COEF_H(n, i)      (DISPC_OVL_BASE(n) + \
  84                                         DISPC_FIR_COEF_H_OFFSET(n, i))
  85 #define DISPC_OVL_FIR_COEF_HV(n, i)     (DISPC_OVL_BASE(n) + \
  86                                         DISPC_FIR_COEF_HV_OFFSET(n, i))
  87 #define DISPC_OVL_FIR_COEF_H2(n, i)     (DISPC_OVL_BASE(n) + \
  88                                         DISPC_FIR_COEF_H2_OFFSET(n, i))
  89 #define DISPC_OVL_FIR_COEF_HV2(n, i)    (DISPC_OVL_BASE(n) + \
  90                                         DISPC_FIR_COEF_HV2_OFFSET(n, i))
  91 #define DISPC_OVL_CONV_COEF(n, i)       (DISPC_OVL_BASE(n) + \
  92                                         DISPC_CONV_COEF_OFFSET(n, i))
  93 #define DISPC_OVL_FIR_COEF_V(n, i)      (DISPC_OVL_BASE(n) + \
  94                                         DISPC_FIR_COEF_V_OFFSET(n, i))
  95 #define DISPC_OVL_FIR_COEF_V2(n, i)     (DISPC_OVL_BASE(n) + \
  96                                         DISPC_FIR_COEF_V2_OFFSET(n, i))
  97 #define DISPC_OVL_PRELOAD(n)            (DISPC_OVL_BASE(n) + \
  98                                         DISPC_PRELOAD_OFFSET(n))
  99
 100 /* DISPC up/downsampling FIR filter coefficient structure */
 101 struct dispc_coef {
 102         s8 hc4_vc22;
 103         s8 hc3_vc2;
 104         u8 hc2_vc1;
 105         s8 hc1_vc0;
 106         s8 hc0_vc00;
 107 };
 108
 109 const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
 110
 111 /* DISPC manager/channel specific registers */
 112 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
 113 {
 114         switch (channel) {
 115         case OMAP_DSS_CHANNEL_LCD:
 116                 return 0x004C;
 117         case OMAP_DSS_CHANNEL_DIGIT:
 118                 return 0x0050;
 119         case OMAP_DSS_CHANNEL_LCD2:
 120                 return 0x03AC;
 121         default:
 122                 BUG();
 123                 return 0;
 124         }
 125 }
 126
 127 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
 128 {
 129         switch (channel) {
 130         case OMAP_DSS_CHANNEL_LCD:
 131                 return 0x0054;
 132         case OMAP_DSS_CHANNEL_DIGIT:
 133                 return 0x0058;
 134         case OMAP_DSS_CHANNEL_LCD2:
 135                 return 0x03B0;
 136         default:
 137                 BUG();
 138                 return 0;
 139         }
 140 }
 141
 142 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
 143 {
 144         switch (channel) {
 145         case OMAP_DSS_CHANNEL_LCD:
 146                 return 0x0064;
 147         case OMAP_DSS_CHANNEL_DIGIT:
 148                 BUG();
 149                 return 0;
 150         case OMAP_DSS_CHANNEL_LCD2:
 151                 return 0x0400;
 152         default:
 153                 BUG();
 154                 return 0;
 155         }
 156 }
 157
 158 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
 159 {
 160         switch (channel) {
 161         case OMAP_DSS_CHANNEL_LCD:
 162                 return 0x0068;
 163         case OMAP_DSS_CHANNEL_DIGIT:
 164                 BUG();
 165                 return 0;
 166         case OMAP_DSS_CHANNEL_LCD2:
 167                 return 0x0404;
 168         default:
 169                 BUG();
 170                 return 0;
 171         }
 172 }
 173
 174 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
 175 {
 176         switch (channel) {
 177         case OMAP_DSS_CHANNEL_LCD:
 178                 return 0x006C;
 179         case OMAP_DSS_CHANNEL_DIGIT:
 180                 BUG();
 181                 return 0;
 182         case OMAP_DSS_CHANNEL_LCD2:
 183                 return 0x0408;
 184         default:
 185                 BUG();
 186                 return 0;
 187         }
 188 }
 189
 190 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
 191 {
 192         switch (channel) {
 193         case OMAP_DSS_CHANNEL_LCD:
 194                 return 0x0070;
 195         case OMAP_DSS_CHANNEL_DIGIT:
 196                 BUG();
 197                 return 0;
 198         case OMAP_DSS_CHANNEL_LCD2:
 199                 return 0x040C;
 200         default:
 201                 BUG();
 202                 return 0;
 203         }
 204 }
 205
 206 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
 207 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
 208 {
 209         switch (channel) {
 210         case OMAP_DSS_CHANNEL_LCD:
 211                 return 0x007C;
 212         case OMAP_DSS_CHANNEL_DIGIT:
 213                 return 0x0078;
 214         case OMAP_DSS_CHANNEL_LCD2:
 215                 return 0x03CC;
 216         default:
 217                 BUG();
 218                 return 0;
 219         }
 220 }
 221
 222 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
 223 {
 224         switch (channel) {
 225         case OMAP_DSS_CHANNEL_LCD:
 226                 return 0x01D4;
 227         case OMAP_DSS_CHANNEL_DIGIT:
 228                 BUG();
 229                 return 0;
 230         case OMAP_DSS_CHANNEL_LCD2:
 231                 return 0x03C0;
 232         default:
 233                 BUG();
 234                 return 0;
 235         }
 236 }
 237
 238 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
 239 {
 240         switch (channel) {
 241         case OMAP_DSS_CHANNEL_LCD:
 242                 return 0x01D8;
 243         case OMAP_DSS_CHANNEL_DIGIT:
 244                 BUG();
 245                 return 0;
 246         case OMAP_DSS_CHANNEL_LCD2:
 247                 return 0x03C4;
 248         default:
 249                 BUG();
 250                 return 0;
 251         }
 252 }
 253
 254 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
 255 {
 256         switch (channel) {
 257         case OMAP_DSS_CHANNEL_LCD:
 258                 return 0x01DC;
 259         case OMAP_DSS_CHANNEL_DIGIT:
 260                 BUG();
 261                 return 0;
 262         case OMAP_DSS_CHANNEL_LCD2:
 263                 return 0x03C8;
 264         default:
 265                 BUG();
 266                 return 0;
 267         }
 268 }
 269
 270 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
 271 {
 272         switch (channel) {
 273         case OMAP_DSS_CHANNEL_LCD:
 274                 return 0x0220;
 275         case OMAP_DSS_CHANNEL_DIGIT:
 276                 BUG();
 277                 return 0;
 278         case OMAP_DSS_CHANNEL_LCD2:
 279                 return 0x03BC;
 280         default:
 281                 BUG();
 282                 return 0;
 283         }
 284 }
 285
 286 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
 287 {
 288         switch (channel) {
 289         case OMAP_DSS_CHANNEL_LCD:
 290                 return 0x0224;
 291         case OMAP_DSS_CHANNEL_DIGIT:
 292                 BUG();
 293                 return 0;
 294         case OMAP_DSS_CHANNEL_LCD2:
 295                 return 0x03B8;
 296         default:
 297                 BUG();
 298                 return 0;
 299         }
 300 }
 301
 302 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
 303 {
 304         switch (channel) {
 305         case OMAP_DSS_CHANNEL_LCD:
 306                 return 0x0228;
 307         case OMAP_DSS_CHANNEL_DIGIT:
 308                 BUG();
 309                 return 0;
 310         case OMAP_DSS_CHANNEL_LCD2:
 311                 return 0x03B4;
 312         default:
 313                 BUG();
 314                 return 0;
 315         }
 316 }
 317
 318 /* DISPC overlay register base addresses */
 319 static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
 320 {
 321         switch (plane) {
 322         case OMAP_DSS_GFX:
 323                 return 0x0080;
 324         case OMAP_DSS_VIDEO1:
 325                 return 0x00BC;
 326         case OMAP_DSS_VIDEO2:
 327                 return 0x014C;
 328         case OMAP_DSS_VIDEO3:
 329                 return 0x0300;
 330         default:
 331                 BUG();
 332                 return 0;
 333         }
 334 }
 335
 336 /* DISPC overlay register offsets */
 337 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
 338 {
 339         switch (plane) {
 340         case OMAP_DSS_GFX:
 341         case OMAP_DSS_VIDEO1:
 342         case OMAP_DSS_VIDEO2:
 343                 return 0x0000;
 344         case OMAP_DSS_VIDEO3:
 345                 return 0x0008;
 346         default:
 347                 BUG();
 348                 return 0;
 349         }
 350 }
 351
 352 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
 353 {
 354         switch (plane) {
 355         case OMAP_DSS_GFX:
 356         case OMAP_DSS_VIDEO1:
 357         case OMAP_DSS_VIDEO2:
 358                 return 0x0004;
 359         case OMAP_DSS_VIDEO3:
 360                 return 0x000C;
 361         default:
 362                 BUG();
 363                 return 0;
 364         }
 365 }
 366
 367 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
 368 {
 369         switch (plane) {
 370         case OMAP_DSS_GFX:
 371                 BUG();
 372                 return 0;
 373         case OMAP_DSS_VIDEO1:
 374                 return 0x0544;
 375         case OMAP_DSS_VIDEO2:
 376                 return 0x04BC;
 377         case OMAP_DSS_VIDEO3:
 378                 return 0x0310;
 379         default:
 380                 BUG();
 381                 return 0;
 382         }
 383 }
 384
 385 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
 386 {
 387         switch (plane) {
 388         case OMAP_DSS_GFX:
 389                 BUG();
 390                 return 0;
 391         case OMAP_DSS_VIDEO1:
 392                 return 0x0548;
 393         case OMAP_DSS_VIDEO2:
 394                 return 0x04C0;
 395         case OMAP_DSS_VIDEO3:
 396                 return 0x0314;
 397         default:
 398                 BUG();
 399                 return 0;
 400         }
 401 }
 402
 403 static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
 404 {
 405         switch (plane) {
 406         case OMAP_DSS_GFX:
 407         case OMAP_DSS_VIDEO1:
 408         case OMAP_DSS_VIDEO2:
 409                 return 0x0008;
 410         case OMAP_DSS_VIDEO3:
 411                 return 0x009C;
 412         default:
 413                 BUG();
 414                 return 0;
 415         }
 416 }
 417
 418 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
 419 {
 420         switch (plane) {
 421         case OMAP_DSS_GFX:
 422         case OMAP_DSS_VIDEO1:
 423         case OMAP_DSS_VIDEO2:
 424                 return 0x000C;
 425         case OMAP_DSS_VIDEO3:
 426                 return 0x00A8;
 427         default:
 428                 BUG();
 429                 return 0;
 430         }
 431 }
 432
 433 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
 434 {
 435         switch (plane) {
 436         case OMAP_DSS_GFX:
 437                 return 0x0020;
 438         case OMAP_DSS_VIDEO1:
 439         case OMAP_DSS_VIDEO2:
 440                 return 0x0010;
 441         case OMAP_DSS_VIDEO3:
 442                 return 0x0070;
 443         default:
 444                 BUG();
 445                 return 0;
 446         }
 447 }
 448
 449 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
 450 {
 451         switch (plane) {
 452         case OMAP_DSS_GFX:
 453                 BUG();
 454                 return 0;
 455         case OMAP_DSS_VIDEO1:
 456                 return 0x0568;
 457         case OMAP_DSS_VIDEO2:
 458                 return 0x04DC;
 459         case OMAP_DSS_VIDEO3:
 460                 return 0x032C;
 461         default:
 462                 BUG();
 463                 return 0;
 464         }
 465 }
 466
 467 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
 468 {
 469         switch (plane) {
 470         case OMAP_DSS_GFX:
 471                 return 0x0024;
 472         case OMAP_DSS_VIDEO1:
 473         case OMAP_DSS_VIDEO2:
 474                 return 0x0014;
 475         case OMAP_DSS_VIDEO3:
 476                 return 0x008C;
 477         default:
 478                 BUG();
 479                 return 0;
 480         }
 481 }
 482
 483 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
 484 {
 485         switch (plane) {
 486         case OMAP_DSS_GFX:
 487                 return 0x0028;
 488         case OMAP_DSS_VIDEO1:
 489         case OMAP_DSS_VIDEO2:
 490                 return 0x0018;
 491         case OMAP_DSS_VIDEO3:
 492                 return 0x0088;
 493         default:
 494                 BUG();
 495                 return 0;
 496         }
 497 }
 498
 499 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
 500 {
 501         switch (plane) {
 502         case OMAP_DSS_GFX:
 503                 return 0x002C;
 504         case OMAP_DSS_VIDEO1:
 505         case OMAP_DSS_VIDEO2:
 506                 return 0x001C;
 507         case OMAP_DSS_VIDEO3:
 508                 return 0x00A4;
 509         default:
 510                 BUG();
 511                 return 0;
 512         }
 513 }
 514
 515 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
 516 {
 517         switch (plane) {
 518         case OMAP_DSS_GFX:
 519                 return 0x0030;
 520         case OMAP_DSS_VIDEO1:
 521         case OMAP_DSS_VIDEO2:
 522                 return 0x0020;
 523         case OMAP_DSS_VIDEO3:
 524                 return 0x0098;
 525         default:
 526                 BUG();
 527                 return 0;
 528         }
 529 }
 530
 531 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
 532 {
 533         switch (plane) {
 534         case OMAP_DSS_GFX:
 535                 return 0x0034;
 536         case OMAP_DSS_VIDEO1:
 537         case OMAP_DSS_VIDEO2:
 538         case OMAP_DSS_VIDEO3:
 539                 BUG();
 540                 return 0;
 541         default:
 542                 BUG();
 543                 return 0;
 544         }
 545 }
 546
 547 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
 548 {
 549         switch (plane) {
 550         case OMAP_DSS_GFX:
 551                 return 0x0038;
 552         case OMAP_DSS_VIDEO1:
 553         case OMAP_DSS_VIDEO2:
 554         case OMAP_DSS_VIDEO3:
 555                 BUG();
 556                 return 0;
 557         default:
 558                 BUG();
 559                 return 0;
 560         }
 561 }
 562
 563 static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
 564 {
 565         switch (plane) {
 566         case OMAP_DSS_GFX:
 567                 BUG();
 568                 return 0;
 569         case OMAP_DSS_VIDEO1:
 570         case OMAP_DSS_VIDEO2:
 571                 return 0x0024;
 572         case OMAP_DSS_VIDEO3:
 573                 return 0x0090;
 574         default:
 575                 BUG();
 576                 return 0;
 577         }
 578 }
 579
 580 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
 581 {
 582         switch (plane) {
 583         case OMAP_DSS_GFX:
 584                 BUG();
 585                 return 0;
 586         case OMAP_DSS_VIDEO1:
 587                 return 0x0580;
 588         case OMAP_DSS_VIDEO2:
 589                 return 0x055C;
 590         case OMAP_DSS_VIDEO3:
 591                 return 0x0424;
 592         default:
 593                 BUG();
 594                 return 0;
 595         }
 596 }
 597
 598 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
 599 {
 600         switch (plane) {
 601         case OMAP_DSS_GFX:
 602                 BUG();
 603                 return 0;
 604         case OMAP_DSS_VIDEO1:
 605         case OMAP_DSS_VIDEO2:
 606                 return 0x0028;
 607         case OMAP_DSS_VIDEO3:
 608                 return 0x0094;
 609         default:
 610                 BUG();
 611                 return 0;
 612         }
 613 }
 614
 615
 616 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
 617 {
 618         switch (plane) {
 619         case OMAP_DSS_GFX:
 620                 BUG();
 621                 return 0;
 622         case OMAP_DSS_VIDEO1:
 623         case OMAP_DSS_VIDEO2:
 624                 return 0x002C;
 625         case OMAP_DSS_VIDEO3:
 626                 return 0x0000;
 627         default:
 628                 BUG();
 629                 return 0;
 630         }
 631 }
 632
 633 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
 634 {
 635         switch (plane) {
 636         case OMAP_DSS_GFX:
 637                 BUG();
 638                 return 0;
 639         case OMAP_DSS_VIDEO1:
 640                 return 0x0584;
 641         case OMAP_DSS_VIDEO2:
 642                 return 0x0560;
 643         case OMAP_DSS_VIDEO3:
 644                 return 0x0428;
 645         default:
 646                 BUG();
 647                 return 0;
 648         }
 649 }
 650
 651 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
 652 {
 653         switch (plane) {
 654         case OMAP_DSS_GFX:
 655                 BUG();
 656                 return 0;
 657         case OMAP_DSS_VIDEO1:
 658         case OMAP_DSS_VIDEO2:
 659                 return 0x0030;
 660         case OMAP_DSS_VIDEO3:
 661                 return 0x0004;
 662         default:
 663                 BUG();
 664                 return 0;
 665         }
 666 }
 667
 668 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
 669 {
 670         switch (plane) {
 671         case OMAP_DSS_GFX:
 672                 BUG();
 673                 return 0;
 674         case OMAP_DSS_VIDEO1:
 675                 return 0x0588;
 676         case OMAP_DSS_VIDEO2:
 677                 return 0x0564;
 678         case OMAP_DSS_VIDEO3:
 679                 return 0x042C;
 680         default:
 681                 BUG();
 682                 return 0;
 683         }
 684 }
 685
 686 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 687 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
 688 {
 689         switch (plane) {
 690         case OMAP_DSS_GFX:
 691                 BUG();
 692                 return 0;
 693         case OMAP_DSS_VIDEO1:
 694         case OMAP_DSS_VIDEO2:
 695                 return 0x0034 + i * 0x8;
 696         case OMAP_DSS_VIDEO3:
 697                 return 0x0010 + i * 0x8;
 698         default:
 699                 BUG();
 700                 return 0;
 701         }
 702 }
 703
 704 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 705 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
 706 {
 707         switch (plane) {
 708         case OMAP_DSS_GFX:
 709                 BUG();
 710                 return 0;
 711         case OMAP_DSS_VIDEO1:
 712                 return 0x058C + i * 0x8;
 713         case OMAP_DSS_VIDEO2:
 714                 return 0x0568 + i * 0x8;
 715         case OMAP_DSS_VIDEO3:
 716                 return 0x0430 + i * 0x8;
 717         default:
 718                 BUG();
 719                 return 0;
 720         }
 721 }
 722
 723 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 724 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
 725 {
 726         switch (plane) {
 727         case OMAP_DSS_GFX:
 728                 BUG();
 729                 return 0;
 730         case OMAP_DSS_VIDEO1:
 731         case OMAP_DSS_VIDEO2:
 732                 return 0x0038 + i * 0x8;
 733         case OMAP_DSS_VIDEO3:
 734                 return 0x0014 + i * 0x8;
 735         default:
 736                 BUG();
 737                 return 0;
 738         }
 739 }
 740
 741 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 742 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
 743 {
 744         switch (plane) {
 745         case OMAP_DSS_GFX:
 746                 BUG();
 747                 return 0;
 748         case OMAP_DSS_VIDEO1:
 749                 return 0x0590 + i * 8;
 750         case OMAP_DSS_VIDEO2:
 751                 return 0x056C + i * 0x8;
 752         case OMAP_DSS_VIDEO3:
 753                 return 0x0434 + i * 0x8;
 754         default:
 755                 BUG();
 756                 return 0;
 757         }
 758 }
 759
 760 /* coef index i = {0, 1, 2, 3, 4,} */
 761 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
 762 {
 763         switch (plane) {
 764         case OMAP_DSS_GFX:
 765                 BUG();
 766                 return 0;
 767         case OMAP_DSS_VIDEO1:
 768         case OMAP_DSS_VIDEO2:
 769         case OMAP_DSS_VIDEO3:
 770                 return 0x0074 + i * 0x4;
 771         default:
 772                 BUG();
 773                 return 0;
 774         }
 775 }
 776
 777 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 778 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
 779 {
 780         switch (plane) {
 781         case OMAP_DSS_GFX:
 782                 BUG();
 783                 return 0;
 784         case OMAP_DSS_VIDEO1:
 785                 return 0x0124 + i * 0x4;
 786         case OMAP_DSS_VIDEO2:
 787                 return 0x00B4 + i * 0x4;
 788         case OMAP_DSS_VIDEO3:
 789                 return 0x0050 + i * 0x4;
 790         default:
 791                 BUG();
 792                 return 0;
 793         }
 794 }
 795
 796 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 797 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
 798 {
 799         switch (plane) {
 800         case OMAP_DSS_GFX:
 801                 BUG();
 802                 return 0;
 803         case OMAP_DSS_VIDEO1:
 804                 return 0x05CC + i * 0x4;
 805         case OMAP_DSS_VIDEO2:
 806                 return 0x05A8 + i * 0x4;
 807         case OMAP_DSS_VIDEO3:
 808                 return 0x0470 + i * 0x4;
 809         default:
 810                 BUG();
 811                 return 0;
 812         }
 813 }
 814
 815 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
 816 {
 817         switch (plane) {
 818         case OMAP_DSS_GFX:
 819                 return 0x01AC;
 820         case OMAP_DSS_VIDEO1:
 821                 return 0x0174;
 822         case OMAP_DSS_VIDEO2:
 823                 return 0x00E8;
 824         case OMAP_DSS_VIDEO3:
 825                 return 0x00A0;
 826         default:
 827                 BUG();
 828                 return 0;
 829         }
 830 }
 831 #endif