2 * linux/drivers/video/omap2/dss/dss.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DSS"
25 #include <linux/kernel.h>
26 #include <linux/module.h>
28 #include <linux/export.h>
29 #include <linux/err.h>
30 #include <linux/delay.h>
31 #include <linux/seq_file.h>
32 #include <linux/clk.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/gfp.h>
36 #include <linux/sizes.h>
39 #include <video/omapdss.h>
42 #include "dss_features.h"
44 #define DSS_SZ_REGS SZ_512
50 #define DSS_REG(idx) ((const struct dss_reg) { idx })
52 #define DSS_REVISION DSS_REG(0x0000)
53 #define DSS_SYSCONFIG DSS_REG(0x0010)
54 #define DSS_SYSSTATUS DSS_REG(0x0014)
55 #define DSS_CONTROL DSS_REG(0x0040)
56 #define DSS_SDI_CONTROL DSS_REG(0x0044)
57 #define DSS_PLL_CONTROL DSS_REG(0x0048)
58 #define DSS_SDI_STATUS DSS_REG(0x005C)
60 #define REG_GET(idx, start, end) \
61 FLD_GET(dss_read_reg(idx), start, end)
63 #define REG_FLD_MOD(idx, val, start, end) \
64 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
66 static int dss_runtime_get(void);
67 static void dss_runtime_put(void);
71 u8 dss_fck_multiplier;
72 const char *parent_clk_name;
73 enum omap_display_type *ports;
75 int (*dpi_select_source)(int port, enum omap_channel channel);
79 struct platform_device *pdev;
82 struct clk *parent_clk;
84 unsigned long dss_clk_rate;
86 unsigned long cache_req_pck;
87 unsigned long cache_prate;
88 struct dispc_clock_info cache_dispc_cinfo;
90 enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
91 enum omap_dss_clk_source dispc_clk_source;
92 enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
95 u32 ctx[DSS_SZ_REGS / sizeof(u32)];
97 const struct dss_features *feat;
100 static const char * const dss_generic_clk_source_names[] = {
101 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC",
102 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI",
103 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK",
104 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DSI_PLL2_HSDIV_DISPC",
105 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DSI_PLL2_HSDIV_DSI",
108 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
110 __raw_writel(val, dss.base + idx.idx);
113 static inline u32 dss_read_reg(const struct dss_reg idx)
115 return __raw_readl(dss.base + idx.idx);
119 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
121 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
123 static void dss_save_context(void)
125 DSSDBG("dss_save_context\n");
129 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
130 OMAP_DISPLAY_TYPE_SDI) {
135 dss.ctx_valid = true;
137 DSSDBG("context saved\n");
140 static void dss_restore_context(void)
142 DSSDBG("dss_restore_context\n");
149 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
150 OMAP_DISPLAY_TYPE_SDI) {
155 DSSDBG("context restored\n");
161 void dss_sdi_init(int datapairs)
165 BUG_ON(datapairs > 3 || datapairs < 1);
167 l = dss_read_reg(DSS_SDI_CONTROL);
168 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
169 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
170 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
171 dss_write_reg(DSS_SDI_CONTROL, l);
173 l = dss_read_reg(DSS_PLL_CONTROL);
174 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
175 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
176 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
177 dss_write_reg(DSS_PLL_CONTROL, l);
180 int dss_sdi_enable(void)
182 unsigned long timeout;
184 dispc_pck_free_enable(1);
187 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
188 udelay(1); /* wait 2x PCLK */
191 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
193 /* Waiting for PLL lock request to complete */
194 timeout = jiffies + msecs_to_jiffies(500);
195 while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
196 if (time_after_eq(jiffies, timeout)) {
197 DSSERR("PLL lock request timed out\n");
202 /* Clearing PLL_GO bit */
203 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
205 /* Waiting for PLL to lock */
206 timeout = jiffies + msecs_to_jiffies(500);
207 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
208 if (time_after_eq(jiffies, timeout)) {
209 DSSERR("PLL lock timed out\n");
214 dispc_lcd_enable_signal(1);
216 /* Waiting for SDI reset to complete */
217 timeout = jiffies + msecs_to_jiffies(500);
218 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
219 if (time_after_eq(jiffies, timeout)) {
220 DSSERR("SDI reset timed out\n");
228 dispc_lcd_enable_signal(0);
231 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
233 dispc_pck_free_enable(0);
238 void dss_sdi_disable(void)
240 dispc_lcd_enable_signal(0);
242 dispc_pck_free_enable(0);
245 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
248 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
250 return dss_generic_clk_source_names[clk_src];
253 void dss_dump_clocks(struct seq_file *s)
255 const char *fclk_name, *fclk_real_name;
256 unsigned long fclk_rate;
258 if (dss_runtime_get())
261 seq_printf(s, "- DSS -\n");
263 fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
264 fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
265 fclk_rate = clk_get_rate(dss.dss_clk);
267 seq_printf(s, "%s (%s) = %lu\n",
268 fclk_name, fclk_real_name,
274 static void dss_dump_regs(struct seq_file *s)
276 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
278 if (dss_runtime_get())
281 DUMPREG(DSS_REVISION);
282 DUMPREG(DSS_SYSCONFIG);
283 DUMPREG(DSS_SYSSTATUS);
284 DUMPREG(DSS_CONTROL);
286 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
287 OMAP_DISPLAY_TYPE_SDI) {
288 DUMPREG(DSS_SDI_CONTROL);
289 DUMPREG(DSS_PLL_CONTROL);
290 DUMPREG(DSS_SDI_STATUS);
297 static void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
303 case OMAP_DSS_CLK_SRC_FCK:
306 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
309 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
317 dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
319 REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */
321 dss.dispc_clk_source = clk_src;
324 void dss_select_dsi_clk_source(int dsi_module,
325 enum omap_dss_clk_source clk_src)
330 case OMAP_DSS_CLK_SRC_FCK:
333 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
334 BUG_ON(dsi_module != 0);
337 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
338 BUG_ON(dsi_module != 1);
346 pos = dsi_module == 0 ? 1 : 10;
347 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */
349 dss.dsi_clk_source[dsi_module] = clk_src;
352 void dss_select_lcd_clk_source(enum omap_channel channel,
353 enum omap_dss_clk_source clk_src)
357 if (!dss_has_feature(FEAT_LCD_CLK_SRC)) {
358 dss_select_dispc_clk_source(clk_src);
363 case OMAP_DSS_CLK_SRC_FCK:
366 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
367 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
370 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
371 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 &&
372 channel != OMAP_DSS_CHANNEL_LCD3);
380 pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
381 (channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19);
382 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */
384 ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
385 (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
386 dss.lcd_clk_source[ix] = clk_src;
389 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
391 return dss.dispc_clk_source;
394 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
396 return dss.dsi_clk_source[dsi_module];
399 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
401 if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
402 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
403 (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
404 return dss.lcd_clk_source[ix];
406 /* LCD_CLK source is the same as DISPC_FCLK source for
408 return dss.dispc_clk_source;
412 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
413 dss_div_calc_func func, void *data)
415 int fckd, fckd_start, fckd_stop;
417 unsigned long fck_hw_max;
418 unsigned long fckd_hw_max;
422 fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
424 if (dss.parent_clk == NULL) {
427 pckd = fck_hw_max / pck;
431 fck = clk_round_rate(dss.dss_clk, fck);
433 return func(fck, data);
436 fckd_hw_max = dss.feat->fck_div_max;
438 m = dss.feat->dss_fck_multiplier;
439 prate = clk_get_rate(dss.parent_clk);
441 fck_min = fck_min ? fck_min : 1;
443 fckd_start = min(prate * m / fck_min, fckd_hw_max);
444 fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
446 for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
447 fck = DIV_ROUND_UP(prate, fckd) * m;
456 int dss_set_fck_rate(unsigned long rate)
460 DSSDBG("set fck to %lu\n", rate);
462 r = clk_set_rate(dss.dss_clk, rate);
466 dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
468 WARN_ONCE(dss.dss_clk_rate != rate,
469 "clk rate mismatch: %lu != %lu", dss.dss_clk_rate,
475 unsigned long dss_get_dispc_clk_rate(void)
477 return dss.dss_clk_rate;
480 static int dss_setup_default_clock(void)
482 unsigned long max_dss_fck, prate;
487 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
489 if (dss.parent_clk == NULL) {
490 fck = clk_round_rate(dss.dss_clk, max_dss_fck);
492 prate = clk_get_rate(dss.parent_clk);
494 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
496 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier;
499 r = dss_set_fck_rate(fck);
506 void dss_set_venc_output(enum omap_dss_venc_type type)
510 if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
512 else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
517 /* venc out selection. 0 = comp, 1 = svideo */
518 REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
521 void dss_set_dac_pwrdn_bgz(bool enable)
523 REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
526 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)
528 enum omap_display_type dp;
529 dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
531 /* Complain about invalid selections */
532 WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC));
533 WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI));
535 /* Select only if we have options */
536 if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI))
537 REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */
540 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
542 enum omap_display_type displays;
544 displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
545 if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
546 return DSS_VENC_TV_CLK;
548 if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0)
549 return DSS_HDMI_M_PCLK;
551 return REG_GET(DSS_CONTROL, 15, 15);
554 static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel)
556 if (channel != OMAP_DSS_CHANNEL_LCD)
562 static int dss_dpi_select_source_omap4(int port, enum omap_channel channel)
567 case OMAP_DSS_CHANNEL_LCD2:
570 case OMAP_DSS_CHANNEL_DIGIT:
577 REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
582 static int dss_dpi_select_source_omap5(int port, enum omap_channel channel)
587 case OMAP_DSS_CHANNEL_LCD:
590 case OMAP_DSS_CHANNEL_LCD2:
593 case OMAP_DSS_CHANNEL_LCD3:
596 case OMAP_DSS_CHANNEL_DIGIT:
603 REG_FLD_MOD(DSS_CONTROL, val, 17, 16);
608 int dss_dpi_select_source(int port, enum omap_channel channel)
610 return dss.feat->dpi_select_source(port, channel);
613 static int dss_get_clocks(void)
617 clk = devm_clk_get(&dss.pdev->dev, "fck");
619 DSSERR("can't get clock fck\n");
625 if (dss.feat->parent_clk_name) {
626 clk = clk_get(NULL, dss.feat->parent_clk_name);
628 DSSERR("Failed to get %s\n", dss.feat->parent_clk_name);
635 dss.parent_clk = clk;
640 static void dss_put_clocks(void)
643 clk_put(dss.parent_clk);
646 static int dss_runtime_get(void)
650 DSSDBG("dss_runtime_get\n");
652 r = pm_runtime_get_sync(&dss.pdev->dev);
654 return r < 0 ? r : 0;
657 static void dss_runtime_put(void)
661 DSSDBG("dss_runtime_put\n");
663 r = pm_runtime_put_sync(&dss.pdev->dev);
664 WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
668 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
669 void dss_debug_dump_clocks(struct seq_file *s)
672 dispc_dump_clocks(s);
673 #ifdef CONFIG_OMAP2_DSS_DSI
680 static enum omap_display_type omap2plus_ports[] = {
681 OMAP_DISPLAY_TYPE_DPI,
684 static enum omap_display_type omap34xx_ports[] = {
685 OMAP_DISPLAY_TYPE_DPI,
686 OMAP_DISPLAY_TYPE_SDI,
689 static const struct dss_features omap24xx_dss_feats __initconst = {
691 * fck div max is really 16, but the divider range has gaps. The range
692 * from 1 to 6 has no gaps, so let's use that as a max.
695 .dss_fck_multiplier = 2,
696 .parent_clk_name = "core_ck",
697 .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
698 .ports = omap2plus_ports,
699 .num_ports = ARRAY_SIZE(omap2plus_ports),
702 static const struct dss_features omap34xx_dss_feats __initconst = {
704 .dss_fck_multiplier = 2,
705 .parent_clk_name = "dpll4_ck",
706 .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
707 .ports = omap34xx_ports,
708 .num_ports = ARRAY_SIZE(omap34xx_ports),
711 static const struct dss_features omap3630_dss_feats __initconst = {
713 .dss_fck_multiplier = 1,
714 .parent_clk_name = "dpll4_ck",
715 .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
716 .ports = omap2plus_ports,
717 .num_ports = ARRAY_SIZE(omap2plus_ports),
720 static const struct dss_features omap44xx_dss_feats __initconst = {
722 .dss_fck_multiplier = 1,
723 .parent_clk_name = "dpll_per_x2_ck",
724 .dpi_select_source = &dss_dpi_select_source_omap4,
725 .ports = omap2plus_ports,
726 .num_ports = ARRAY_SIZE(omap2plus_ports),
729 static const struct dss_features omap54xx_dss_feats __initconst = {
731 .dss_fck_multiplier = 1,
732 .parent_clk_name = "dpll_per_x2_ck",
733 .dpi_select_source = &dss_dpi_select_source_omap5,
734 .ports = omap2plus_ports,
735 .num_ports = ARRAY_SIZE(omap2plus_ports),
738 static const struct dss_features am43xx_dss_feats __initconst = {
740 .dss_fck_multiplier = 0,
741 .parent_clk_name = NULL,
742 .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
743 .ports = omap2plus_ports,
744 .num_ports = ARRAY_SIZE(omap2plus_ports),
747 static int __init dss_init_features(struct platform_device *pdev)
749 const struct dss_features *src;
750 struct dss_features *dst;
752 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
754 dev_err(&pdev->dev, "Failed to allocate local DSS Features\n");
758 switch (omapdss_get_version()) {
759 case OMAPDSS_VER_OMAP24xx:
760 src = &omap24xx_dss_feats;
763 case OMAPDSS_VER_OMAP34xx_ES1:
764 case OMAPDSS_VER_OMAP34xx_ES3:
765 case OMAPDSS_VER_AM35xx:
766 src = &omap34xx_dss_feats;
769 case OMAPDSS_VER_OMAP3630:
770 src = &omap3630_dss_feats;
773 case OMAPDSS_VER_OMAP4430_ES1:
774 case OMAPDSS_VER_OMAP4430_ES2:
775 case OMAPDSS_VER_OMAP4:
776 src = &omap44xx_dss_feats;
779 case OMAPDSS_VER_OMAP5:
780 src = &omap54xx_dss_feats;
783 case OMAPDSS_VER_AM43xx:
784 src = &am43xx_dss_feats;
791 memcpy(dst, src, sizeof(*dst));
797 static int __init dss_init_ports(struct platform_device *pdev)
799 struct device_node *parent = pdev->dev.of_node;
800 struct device_node *port;
806 port = omapdss_of_get_next_port(parent, NULL);
810 if (dss.feat->num_ports == 0)
814 enum omap_display_type port_type;
817 r = of_property_read_u32(port, "reg", ®);
821 if (reg >= dss.feat->num_ports)
824 port_type = dss.feat->ports[reg];
827 case OMAP_DISPLAY_TYPE_DPI:
828 dpi_init_port(pdev, port);
830 case OMAP_DISPLAY_TYPE_SDI:
831 sdi_init_port(pdev, port);
836 } while ((port = omapdss_of_get_next_port(parent, port)) != NULL);
841 static void __exit dss_uninit_ports(struct platform_device *pdev)
843 struct device_node *parent = pdev->dev.of_node;
844 struct device_node *port;
849 port = omapdss_of_get_next_port(parent, NULL);
853 if (dss.feat->num_ports == 0)
857 enum omap_display_type port_type;
861 r = of_property_read_u32(port, "reg", ®);
865 if (reg >= dss.feat->num_ports)
868 port_type = dss.feat->ports[reg];
871 case OMAP_DISPLAY_TYPE_DPI:
872 dpi_uninit_port(port);
874 case OMAP_DISPLAY_TYPE_SDI:
875 sdi_uninit_port(port);
880 } while ((port = omapdss_of_get_next_port(parent, port)) != NULL);
883 /* DSS HW IP initialisation */
884 static int __init omap_dsshw_probe(struct platform_device *pdev)
886 struct resource *dss_mem;
892 r = dss_init_features(dss.pdev);
896 dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
898 DSSERR("can't get IORESOURCE_MEM DSS\n");
902 dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
903 resource_size(dss_mem));
905 DSSERR("can't ioremap DSS\n");
909 r = dss_get_clocks();
913 r = dss_setup_default_clock();
915 goto err_setup_clocks;
917 pm_runtime_enable(&pdev->dev);
919 r = dss_runtime_get();
921 goto err_runtime_get;
923 dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
926 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
928 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
930 #ifdef CONFIG_OMAP2_DSS_VENC
931 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
932 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
933 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
935 dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
936 dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
937 dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
938 dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
939 dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
941 dss_init_ports(pdev);
943 rev = dss_read_reg(DSS_REVISION);
944 printk(KERN_INFO "OMAP DSS rev %d.%d\n",
945 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
949 dss_debugfs_create_file("dss", dss_dump_regs);
954 pm_runtime_disable(&pdev->dev);
960 static int __exit omap_dsshw_remove(struct platform_device *pdev)
962 dss_uninit_ports(pdev);
964 pm_runtime_disable(&pdev->dev);
971 static int dss_runtime_suspend(struct device *dev)
974 dss_set_min_bus_tput(dev, 0);
978 static int dss_runtime_resume(struct device *dev)
982 * Set an arbitrarily high tput request to ensure OPP100.
983 * What we should really do is to make a request to stay in OPP100,
984 * without any tput requirements, but that is not currently possible
988 r = dss_set_min_bus_tput(dev, 1000000000);
992 dss_restore_context();
996 static const struct dev_pm_ops dss_pm_ops = {
997 .runtime_suspend = dss_runtime_suspend,
998 .runtime_resume = dss_runtime_resume,
1001 static const struct of_device_id dss_of_match[] = {
1002 { .compatible = "ti,omap2-dss", },
1003 { .compatible = "ti,omap3-dss", },
1004 { .compatible = "ti,omap4-dss", },
1005 { .compatible = "ti,omap5-dss", },
1009 MODULE_DEVICE_TABLE(of, dss_of_match);
1011 static struct platform_driver omap_dsshw_driver = {
1012 .remove = __exit_p(omap_dsshw_remove),
1014 .name = "omapdss_dss",
1016 .of_match_table = dss_of_match,
1017 .suppress_bind_attrs = true,
1021 int __init dss_init_platform_driver(void)
1023 return platform_driver_probe(&omap_dsshw_driver, omap_dsshw_probe);
1026 void dss_uninit_platform_driver(void)
1028 platform_driver_unregister(&omap_dsshw_driver);