2 * linux/drivers/video/omap2/dss/dpi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DPI"
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/export.h>
28 #include <linux/err.h>
29 #include <linux/errno.h>
30 #include <linux/platform_device.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/string.h>
35 #include <video/omapdss.h>
38 #include "dss_features.h"
41 struct platform_device *pdev;
43 struct regulator *vdds_dsi_reg;
44 struct platform_device *dsidev;
48 struct omap_video_timings timings;
49 struct dss_lcd_mgr_config mgr_config;
52 struct omap_dss_device output;
54 bool port_initialized;
57 static struct platform_device *dpi_get_dsidev(enum omap_channel channel)
60 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
61 * would also be used for DISPC fclk. Meaning, when the DPI output is
62 * disabled, DISPC clock will be disabled, and TV out will stop.
64 switch (omapdss_get_version()) {
65 case OMAPDSS_VER_OMAP24xx:
66 case OMAPDSS_VER_OMAP34xx_ES1:
67 case OMAPDSS_VER_OMAP34xx_ES3:
68 case OMAPDSS_VER_OMAP3630:
69 case OMAPDSS_VER_AM35xx:
72 case OMAPDSS_VER_OMAP4430_ES1:
73 case OMAPDSS_VER_OMAP4430_ES2:
74 case OMAPDSS_VER_OMAP4:
76 case OMAP_DSS_CHANNEL_LCD:
77 return dsi_get_dsidev_from_id(0);
78 case OMAP_DSS_CHANNEL_LCD2:
79 return dsi_get_dsidev_from_id(1);
84 case OMAPDSS_VER_OMAP5:
86 case OMAP_DSS_CHANNEL_LCD:
87 return dsi_get_dsidev_from_id(0);
88 case OMAP_DSS_CHANNEL_LCD3:
89 return dsi_get_dsidev_from_id(1);
99 static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel)
102 case OMAP_DSS_CHANNEL_LCD:
103 return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC;
104 case OMAP_DSS_CHANNEL_LCD2:
105 return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
107 /* this shouldn't happen */
109 return OMAP_DSS_CLK_SRC_FCK;
113 struct dpi_clk_calc_ctx {
114 struct platform_device *dsidev;
118 unsigned long pck_min, pck_max;
122 struct dsi_clock_info dsi_cinfo;
124 struct dispc_clock_info dispc_cinfo;
127 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
128 unsigned long pck, void *data)
130 struct dpi_clk_calc_ctx *ctx = data;
133 * Odd dividers give us uneven duty cycle, causing problem when level
134 * shifted. So skip all odd dividers when the pixel clock is on the
137 if (ctx->pck_min >= 100000000) {
138 if (lckd > 1 && lckd % 2 != 0)
141 if (pckd > 1 && pckd % 2 != 0)
145 ctx->dispc_cinfo.lck_div = lckd;
146 ctx->dispc_cinfo.pck_div = pckd;
147 ctx->dispc_cinfo.lck = lck;
148 ctx->dispc_cinfo.pck = pck;
154 static bool dpi_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
157 struct dpi_clk_calc_ctx *ctx = data;
160 * Odd dividers give us uneven duty cycle, causing problem when level
161 * shifted. So skip all odd dividers when the pixel clock is on the
164 if (regm_dispc > 1 && regm_dispc % 2 != 0 && ctx->pck_min >= 100000000)
167 ctx->dsi_cinfo.regm_dispc = regm_dispc;
168 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
170 return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max,
171 dpi_calc_dispc_cb, ctx);
175 static bool dpi_calc_pll_cb(int regn, int regm, unsigned long fint,
179 struct dpi_clk_calc_ctx *ctx = data;
181 ctx->dsi_cinfo.regn = regn;
182 ctx->dsi_cinfo.regm = regm;
183 ctx->dsi_cinfo.fint = fint;
184 ctx->dsi_cinfo.clkin4ddr = pll;
186 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->pck_min,
187 dpi_calc_hsdiv_cb, ctx);
190 static bool dpi_calc_dss_cb(unsigned long fck, void *data)
192 struct dpi_clk_calc_ctx *ctx = data;
196 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
197 dpi_calc_dispc_cb, ctx);
200 static bool dpi_dsi_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
203 unsigned long pll_min, pll_max;
205 clkin = dsi_get_pll_clkin(dpi.dsidev);
207 memset(ctx, 0, sizeof(*ctx));
208 ctx->dsidev = dpi.dsidev;
209 ctx->pck_min = pck - 1000;
210 ctx->pck_max = pck + 1000;
211 ctx->dsi_cinfo.clkin = clkin;
216 return dsi_pll_calc(dpi.dsidev, clkin,
218 dpi_calc_pll_cb, ctx);
221 static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
226 * DSS fck gives us very few possibilities, so finding a good pixel
227 * clock may not be possible. We try multiple times to find the clock,
228 * each time widening the pixel clock range we look for, up to
232 for (i = 0; i < 25; ++i) {
235 memset(ctx, 0, sizeof(*ctx));
236 if (pck > 1000 * i * i * i)
237 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
240 ctx->pck_max = pck + 1000 * i * i * i;
242 ok = dss_div_calc(pck, ctx->pck_min, dpi_calc_dss_cb, ctx);
252 static int dpi_set_dsi_clk(enum omap_channel channel,
253 unsigned long pck_req, unsigned long *fck, int *lck_div,
256 struct dpi_clk_calc_ctx ctx;
260 ok = dpi_dsi_clk_calc(pck_req, &ctx);
264 r = dsi_pll_set_clock_div(dpi.dsidev, &ctx.dsi_cinfo);
268 dss_select_lcd_clk_source(channel,
269 dpi_get_alt_clk_src(channel));
271 dpi.mgr_config.clock_info = ctx.dispc_cinfo;
273 *fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
274 *lck_div = ctx.dispc_cinfo.lck_div;
275 *pck_div = ctx.dispc_cinfo.pck_div;
280 static int dpi_set_dispc_clk(unsigned long pck_req, unsigned long *fck,
281 int *lck_div, int *pck_div)
283 struct dpi_clk_calc_ctx ctx;
287 ok = dpi_dss_clk_calc(pck_req, &ctx);
291 r = dss_set_fck_rate(ctx.fck);
295 dpi.mgr_config.clock_info = ctx.dispc_cinfo;
298 *lck_div = ctx.dispc_cinfo.lck_div;
299 *pck_div = ctx.dispc_cinfo.pck_div;
304 static int dpi_set_mode(struct omap_overlay_manager *mgr)
306 struct omap_video_timings *t = &dpi.timings;
307 int lck_div = 0, pck_div = 0;
308 unsigned long fck = 0;
313 r = dpi_set_dsi_clk(mgr->id, t->pixelclock, &fck,
316 r = dpi_set_dispc_clk(t->pixelclock, &fck,
321 pck = fck / lck_div / pck_div;
323 if (pck != t->pixelclock) {
324 DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n",
330 dss_mgr_set_timings(mgr, t);
335 static void dpi_config_lcd_manager(struct omap_overlay_manager *mgr)
337 dpi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
339 dpi.mgr_config.stallmode = false;
340 dpi.mgr_config.fifohandcheck = false;
342 dpi.mgr_config.video_port_width = dpi.data_lines;
344 dpi.mgr_config.lcden_sig_polarity = 0;
346 dss_mgr_set_lcd_config(mgr, &dpi.mgr_config);
349 static int dpi_display_enable(struct omap_dss_device *dssdev)
351 struct omap_dss_device *out = &dpi.output;
354 mutex_lock(&dpi.lock);
356 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI) && !dpi.vdds_dsi_reg) {
357 DSSERR("no VDSS_DSI regulator\n");
362 if (out == NULL || out->manager == NULL) {
363 DSSERR("failed to enable display: no output/manager\n");
368 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) {
369 r = regulator_enable(dpi.vdds_dsi_reg);
374 r = dispc_runtime_get();
378 r = dss_dpi_select_source(out->manager->id);
383 r = dsi_runtime_get(dpi.dsidev);
387 r = dsi_pll_init(dpi.dsidev, 0, 1);
389 goto err_dsi_pll_init;
392 r = dpi_set_mode(out->manager);
396 dpi_config_lcd_manager(out->manager);
400 r = dss_mgr_enable(out->manager);
404 mutex_unlock(&dpi.lock);
411 dsi_pll_uninit(dpi.dsidev, true);
414 dsi_runtime_put(dpi.dsidev);
419 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
420 regulator_disable(dpi.vdds_dsi_reg);
424 mutex_unlock(&dpi.lock);
428 static void dpi_display_disable(struct omap_dss_device *dssdev)
430 struct omap_overlay_manager *mgr = dpi.output.manager;
432 mutex_lock(&dpi.lock);
434 dss_mgr_disable(mgr);
437 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
438 dsi_pll_uninit(dpi.dsidev, true);
439 dsi_runtime_put(dpi.dsidev);
444 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
445 regulator_disable(dpi.vdds_dsi_reg);
447 mutex_unlock(&dpi.lock);
450 static void dpi_set_timings(struct omap_dss_device *dssdev,
451 struct omap_video_timings *timings)
453 DSSDBG("dpi_set_timings\n");
455 mutex_lock(&dpi.lock);
457 dpi.timings = *timings;
459 mutex_unlock(&dpi.lock);
462 static void dpi_get_timings(struct omap_dss_device *dssdev,
463 struct omap_video_timings *timings)
465 mutex_lock(&dpi.lock);
467 *timings = dpi.timings;
469 mutex_unlock(&dpi.lock);
472 static int dpi_check_timings(struct omap_dss_device *dssdev,
473 struct omap_video_timings *timings)
475 struct omap_overlay_manager *mgr = dpi.output.manager;
476 int lck_div, pck_div;
479 struct dpi_clk_calc_ctx ctx;
482 if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
485 if (timings->pixelclock == 0)
489 ok = dpi_dsi_clk_calc(timings->pixelclock, &ctx);
493 fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
495 ok = dpi_dss_clk_calc(timings->pixelclock, &ctx);
502 lck_div = ctx.dispc_cinfo.lck_div;
503 pck_div = ctx.dispc_cinfo.pck_div;
505 pck = fck / lck_div / pck_div;
507 timings->pixelclock = pck;
512 static void dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
514 mutex_lock(&dpi.lock);
516 dpi.data_lines = data_lines;
518 mutex_unlock(&dpi.lock);
521 static int dpi_verify_dsi_pll(struct platform_device *dsidev)
525 /* do initial setup with the PLL to see if it is operational */
527 r = dsi_runtime_get(dsidev);
531 r = dsi_pll_init(dsidev, 0, 1);
533 dsi_runtime_put(dsidev);
537 dsi_pll_uninit(dsidev, true);
538 dsi_runtime_put(dsidev);
543 static int dpi_init_regulator(void)
545 struct regulator *vdds_dsi;
547 if (!dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
550 if (dpi.vdds_dsi_reg)
553 vdds_dsi = devm_regulator_get(&dpi.pdev->dev, "vdds_dsi");
554 if (IS_ERR(vdds_dsi)) {
555 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
556 DSSERR("can't get VDDS_DSI regulator\n");
557 return PTR_ERR(vdds_dsi);
560 dpi.vdds_dsi_reg = vdds_dsi;
565 static void dpi_init_pll(void)
567 struct platform_device *dsidev;
572 dsidev = dpi_get_dsidev(dpi.output.dispc_channel);
576 if (dpi_verify_dsi_pll(dsidev)) {
577 DSSWARN("DSI PLL not operational\n");
585 * Return a hardcoded channel for the DPI output. This should work for
586 * current use cases, but this can be later expanded to either resolve
587 * the channel in some more dynamic manner, or get the channel as a user
590 static enum omap_channel dpi_get_channel(void)
592 switch (omapdss_get_version()) {
593 case OMAPDSS_VER_OMAP24xx:
594 case OMAPDSS_VER_OMAP34xx_ES1:
595 case OMAPDSS_VER_OMAP34xx_ES3:
596 case OMAPDSS_VER_OMAP3630:
597 case OMAPDSS_VER_AM35xx:
598 return OMAP_DSS_CHANNEL_LCD;
600 case OMAPDSS_VER_OMAP4430_ES1:
601 case OMAPDSS_VER_OMAP4430_ES2:
602 case OMAPDSS_VER_OMAP4:
603 return OMAP_DSS_CHANNEL_LCD2;
605 case OMAPDSS_VER_OMAP5:
606 return OMAP_DSS_CHANNEL_LCD3;
609 DSSWARN("unsupported DSS version\n");
610 return OMAP_DSS_CHANNEL_LCD;
614 static int dpi_connect(struct omap_dss_device *dssdev,
615 struct omap_dss_device *dst)
617 struct omap_overlay_manager *mgr;
620 r = dpi_init_regulator();
626 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
630 r = dss_mgr_connect(mgr, dssdev);
634 r = omapdss_output_set_device(dssdev, dst);
636 DSSERR("failed to connect output to new device: %s\n",
638 dss_mgr_disconnect(mgr, dssdev);
645 static void dpi_disconnect(struct omap_dss_device *dssdev,
646 struct omap_dss_device *dst)
648 WARN_ON(dst != dssdev->dst);
650 if (dst != dssdev->dst)
653 omapdss_output_unset_device(dssdev);
656 dss_mgr_disconnect(dssdev->manager, dssdev);
659 static const struct omapdss_dpi_ops dpi_ops = {
660 .connect = dpi_connect,
661 .disconnect = dpi_disconnect,
663 .enable = dpi_display_enable,
664 .disable = dpi_display_disable,
666 .check_timings = dpi_check_timings,
667 .set_timings = dpi_set_timings,
668 .get_timings = dpi_get_timings,
670 .set_data_lines = dpi_set_data_lines,
673 static void dpi_init_output(struct platform_device *pdev)
675 struct omap_dss_device *out = &dpi.output;
677 out->dev = &pdev->dev;
678 out->id = OMAP_DSS_OUTPUT_DPI;
679 out->output_type = OMAP_DISPLAY_TYPE_DPI;
681 out->dispc_channel = dpi_get_channel();
682 out->ops.dpi = &dpi_ops;
683 out->owner = THIS_MODULE;
685 omapdss_register_output(out);
688 static void __exit dpi_uninit_output(struct platform_device *pdev)
690 struct omap_dss_device *out = &dpi.output;
692 omapdss_unregister_output(out);
695 static int omap_dpi_probe(struct platform_device *pdev)
699 mutex_init(&dpi.lock);
701 dpi_init_output(pdev);
706 static int __exit omap_dpi_remove(struct platform_device *pdev)
708 dpi_uninit_output(pdev);
713 static struct platform_driver omap_dpi_driver = {
714 .probe = omap_dpi_probe,
715 .remove = __exit_p(omap_dpi_remove),
717 .name = "omapdss_dpi",
718 .owner = THIS_MODULE,
722 int __init dpi_init_platform_driver(void)
724 return platform_driver_register(&omap_dpi_driver);
727 void __exit dpi_uninit_platform_driver(void)
729 platform_driver_unregister(&omap_dpi_driver);
732 int __init dpi_init_port(struct platform_device *pdev, struct device_node *port)
734 struct device_node *ep;
738 ep = omapdss_of_get_next_endpoint(port, NULL);
742 r = of_property_read_u32(ep, "data-lines", &datalines);
744 DSSERR("failed to parse datalines\n");
748 dpi.data_lines = datalines;
754 mutex_init(&dpi.lock);
756 dpi_init_output(pdev);
758 dpi.port_initialized = true;
768 void __exit dpi_uninit_port(void)
770 if (!dpi.port_initialized)
773 dpi_uninit_output(dpi.pdev);